From e0d62e664bf481cdcbb69dd7e1a4d01597900795 Mon Sep 17 00:00:00 2001
From: "C.S.M" <caosenmiao@espressif.com>
Date: Tue, 18 Nov 2025 14:41:25 +0800
Subject: [PATCH] feat(esp32s31): Add soc registers from a~i

---
 .../soc/esp32s31/register/soc/adc_reg.h       |   766 +
 .../soc/esp32s31/register/soc/adc_struct.h    |   721 +
 .../soc/esp32s31/register/soc/aes_reg.h       |   484 +
 .../soc/esp32s31/register/soc/aes_struct.h    |   376 +
 .../soc/esp32s31/register/soc/ahb_dma_reg.h   |  6419 ++++++
 .../esp32s31/register/soc/ahb_dma_struct.h    |  1582 ++
 .../soc/esp32s31/register/soc/asrc_reg.h      |   650 +
 .../soc/esp32s31/register/soc/asrc_struct.h   |   656 +
 .../soc/esp32s31/register/soc/axi_dma_reg.h   |  5757 +++++
 .../esp32s31/register/soc/axi_dma_struct.h    |  1822 ++
 .../esp32s31/register/soc/axi_perf_mon_reg.h  |  6881 ++++++
 .../register/soc/axi_perf_mon_struct.h        |  7188 ++++++
 .../esp32s31/register/soc/bitscrambler_reg.h  |   572 +
 .../register/soc/bitscrambler_struct.h        |   525 +
 .../esp32s31/register/soc/bus_monitor_reg.h   |  1389 ++
 .../register/soc/bus_monitor_struct.h         |  1333 ++
 .../soc/esp32s31/register/soc/cache_reg.h     |  6982 ++++++
 .../soc/esp32s31/register/soc/cache_struct.h  |  6274 +++++
 .../esp32s31/register/soc/cnnt_io_mux_reg.h   |  1510 ++
 .../register/soc/cnnt_io_mux_struct.h         |  1179 +
 .../soc/esp32s31/register/soc/cnnt_sys_reg.h  |   667 +
 .../esp32s31/register/soc/cnnt_sys_struct.h   |   618 +
 .../soc/esp32s31/register/soc/cordic_reg.h    |   351 +
 .../soc/esp32s31/register/soc/cordic_struct.h |   329 +
 .../soc/esp32s31/register/soc/cpu_apm_reg.h   |  1584 ++
 .../esp32s31/register/soc/cpu_apm_struct.h    |   612 +
 .../soc/esp32s31/register/soc/dac_reg.h       |   466 +
 .../soc/esp32s31/register/soc/dac_struct.h    |   423 +
 .../soc/esp32s31/register/soc/dma2d_reg.h     |  7190 ++++++
 .../soc/esp32s31/register/soc/dma2d_struct.h  |  2060 ++
 components/soc/esp32s31/register/soc/ds_reg.h |   197 +
 .../soc/esp32s31/register/soc/ds_struct.h     |   200 +
 .../soc/esp32s31/register/soc/ecc_mult_reg.h  |   224 +
 .../esp32s31/register/soc/ecc_mult_struct.h   |   210 +
 .../soc/esp32s31/register/soc/ecdsa_reg.h     |   539 +
 .../soc/esp32s31/register/soc/ecdsa_struct.h  |   557 +
 .../soc/esp32s31/register/soc/efuse_reg.h     |  2800 +++
 .../soc/esp32s31/register/soc/efuse_struct.h  |  1791 ++
 .../soc/esp32s31/register/soc/gmac_reg.h      |  7239 ++++++
 .../soc/esp32s31/register/soc/gmac_struct.h   |  6258 +++++
 .../soc/esp32s31/register/soc/gpio_ext_reg.h  |  2104 ++
 .../esp32s31/register/soc/gpio_ext_struct.h   |  1243 +
 .../soc/esp32s31/register/soc/gpio_reg.h      | 19042 ++++++++++++++++
 .../soc/esp32s31/register/soc/gpio_struct.h   |  1129 +
 .../soc/esp32s31/register/soc/hmac_reg.h      |   294 +
 .../soc/esp32s31/register/soc/hmac_struct.h   |   359 +
 .../esp32s31/register/soc/hp_alive_sys_reg.h  |   839 +
 .../register/soc/hp_alive_sys_struct.h        |   769 +
 .../soc/esp32s31/register/soc/hp_apm_reg.h    |  2574 +++
 .../soc/esp32s31/register/soc/hp_apm_struct.h |   896 +
 .../esp32s31/register/soc/hp_mem_apm_reg.h    |  1744 ++
 .../esp32s31/register/soc/hp_mem_apm_struct.h |   787 +
 .../esp32s31/register/soc/hp_peri0_pms_reg.h  |  2862 +++
 .../register/soc/hp_peri0_pms_struct.h        |  2215 ++
 .../esp32s31/register/soc/hp_peri1_pms_reg.h  |  3402 +++
 .../register/soc/hp_peri1_pms_struct.h        |  2609 +++
 .../esp32s31/register/soc/hp_sys_clkrst_reg.h |  4465 ++++
 .../register/soc/hp_sys_clkrst_struct.h       |  3773 +++
 .../soc/esp32s31/register/soc/hp_system_reg.h |  2380 ++
 .../esp32s31/register/soc/hp_system_struct.h  |  2382 ++
 .../soc/esp32s31/register/soc/huk_reg.h       |   230 +
 .../soc/esp32s31/register/soc/huk_struct.h    |   246 +
 .../soc/esp32s31/register/soc/i2c_reg.h       |  1478 ++
 .../soc/esp32s31/register/soc/i2c_struct.h    |  1233 +
 .../soc/esp32s31/register/soc/i2s_reg.h       |  1594 ++
 .../soc/esp32s31/register/soc/i2s_struct.h    |  1292 ++
 .../register/soc/icm_sys_axi_ic_reg.h         |  2790 +++
 .../register/soc/icm_sys_axi_ic_struct.h      |  3432 +++
 .../soc/esp32s31/register/soc/icm_sys_reg.h   |   134 +
 .../esp32s31/register/soc/icm_sys_struct.h    |   132 +
 .../register/soc/interrupt_core0_reg.h        |  3925 ++++
 .../register/soc/interrupt_core0_struct.h     |  4153 ++++
 .../register/soc/interrupt_core1_reg.h        |  3925 ++++
 .../register/soc/interrupt_core1_struct.h     |  4153 ++++
 .../soc/esp32s31/register/soc/io_mux_reg.h    |   516 +
 .../soc/esp32s31/register/soc/io_mux_struct.h |   145 +
 .../register/soc/iomux_mspi_pin_reg.h         |   721 +
 .../register/soc/iomux_mspi_pin_struct.h      |   551 +
 78 files changed, 173899 insertions(+)
 create mode 100644 components/soc/esp32s31/register/soc/adc_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/adc_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/aes_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/aes_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/ahb_dma_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/ahb_dma_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/asrc_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/asrc_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/axi_dma_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/axi_dma_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/axi_perf_mon_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/axi_perf_mon_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/bitscrambler_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/bitscrambler_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/bus_monitor_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/bus_monitor_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/cache_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/cache_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/cnnt_io_mux_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/cnnt_io_mux_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/cnnt_sys_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/cnnt_sys_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/cordic_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/cordic_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/cpu_apm_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/cpu_apm_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/dac_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/dac_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/dma2d_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/dma2d_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/ds_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/ds_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/ecc_mult_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/ecc_mult_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/ecdsa_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/ecdsa_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/efuse_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/efuse_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/gmac_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/gmac_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/gpio_ext_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/gpio_ext_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/gpio_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/gpio_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hmac_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hmac_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_alive_sys_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_alive_sys_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_apm_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_apm_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_mem_apm_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_peri0_pms_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_peri1_pms_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_peri1_pms_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_sys_clkrst_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_system_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/hp_system_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/huk_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/huk_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/i2c_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/i2c_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/i2s_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/i2s_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/icm_sys_axi_ic_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/icm_sys_axi_ic_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/icm_sys_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/icm_sys_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/interrupt_core0_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/interrupt_core0_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/interrupt_core1_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/interrupt_core1_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/io_mux_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/io_mux_struct.h
 create mode 100644 components/soc/esp32s31/register/soc/iomux_mspi_pin_reg.h
 create mode 100644 components/soc/esp32s31/register/soc/iomux_mspi_pin_struct.h

diff --git a/components/soc/esp32s31/register/soc/adc_reg.h b/components/soc/esp32s31/register/soc/adc_reg.h
new file mode 100644
index 00000000000..bd557f742fa
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/adc_reg.h
@@ -0,0 +1,766 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ADC_CTRL0_REG register
+ *  Register
+ */
+#define ADC_CTRL0_REG (DR_REG_ADC_BASE + 0x0)
+/** ADC_SAR1_TRIGGER_STOP : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_TRIGGER_STOP    (BIT(0))
+#define ADC_SAR1_TRIGGER_STOP_M  (ADC_SAR1_TRIGGER_STOP_V << ADC_SAR1_TRIGGER_STOP_S)
+#define ADC_SAR1_TRIGGER_STOP_V  0x00000001U
+#define ADC_SAR1_TRIGGER_STOP_S  0
+/** ADC_SAR1_TRIGGER_START : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_TRIGGER_START    (BIT(1))
+#define ADC_SAR1_TRIGGER_START_M  (ADC_SAR1_TRIGGER_START_V << ADC_SAR1_TRIGGER_START_S)
+#define ADC_SAR1_TRIGGER_START_V  0x00000001U
+#define ADC_SAR1_TRIGGER_START_S  1
+/** ADC_SAR1_TRIGGER_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  SAR clock divider
+ */
+#define ADC_SAR1_TRIGGER_MODE    0x00000003U
+#define ADC_SAR1_TRIGGER_MODE_M  (ADC_SAR1_TRIGGER_MODE_V << ADC_SAR1_TRIGGER_MODE_S)
+#define ADC_SAR1_TRIGGER_MODE_V  0x00000003U
+#define ADC_SAR1_TRIGGER_MODE_S  2
+/** ADC_SAR1_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR1_PATT_LEN    0x0000000FU
+#define ADC_SAR1_PATT_LEN_M  (ADC_SAR1_PATT_LEN_V << ADC_SAR1_PATT_LEN_S)
+#define ADC_SAR1_PATT_LEN_V  0x0000000FU
+#define ADC_SAR1_PATT_LEN_S  14
+/** ADC_SAR1_PATT_P_CLEAR : WT; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR1_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR1_PATT_P_CLEAR_M  (ADC_SAR1_PATT_P_CLEAR_V << ADC_SAR1_PATT_P_CLEAR_S)
+#define ADC_SAR1_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR1_PATT_P_CLEAR_S  22
+/** ADC_SAR1_PATT_TYPE : R/W; bitpos: [23]; default: 0;
+ *  1: select meas start as table update 0:select mead done as table update
+ */
+#define ADC_SAR1_PATT_TYPE    (BIT(23))
+#define ADC_SAR1_PATT_TYPE_M  (ADC_SAR1_PATT_TYPE_V << ADC_SAR1_PATT_TYPE_S)
+#define ADC_SAR1_PATT_TYPE_V  0x00000001U
+#define ADC_SAR1_PATT_TYPE_S  23
+/** ADC_SAR1_CLK_POS_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_SAR1_CLK_POS_SEL    (BIT(24))
+#define ADC_SAR1_CLK_POS_SEL_M  (ADC_SAR1_CLK_POS_SEL_V << ADC_SAR1_CLK_POS_SEL_S)
+#define ADC_SAR1_CLK_POS_SEL_V  0x00000001U
+#define ADC_SAR1_CLK_POS_SEL_S  24
+/** ADC_SAR1_CONTINUE_MODE_EN : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_SAR1_CONTINUE_MODE_EN    (BIT(25))
+#define ADC_SAR1_CONTINUE_MODE_EN_M  (ADC_SAR1_CONTINUE_MODE_EN_V << ADC_SAR1_CONTINUE_MODE_EN_S)
+#define ADC_SAR1_CONTINUE_MODE_EN_V  0x00000001U
+#define ADC_SAR1_CONTINUE_MODE_EN_S  25
+/** ADC_XPD_SAR1_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR1_FORCE    0x00000003U
+#define ADC_XPD_SAR1_FORCE_M  (ADC_XPD_SAR1_FORCE_V << ADC_XPD_SAR1_FORCE_S)
+#define ADC_XPD_SAR1_FORCE_V  0x00000003U
+#define ADC_XPD_SAR1_FORCE_S  26
+
+/** ADC_CTRL1_REG register
+ *  Register
+ */
+#define ADC_CTRL1_REG (DR_REG_ADC_BASE + 0x4)
+/** ADC_SAR2_TRIGGER_STOP : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_TRIGGER_STOP    (BIT(0))
+#define ADC_SAR2_TRIGGER_STOP_M  (ADC_SAR2_TRIGGER_STOP_V << ADC_SAR2_TRIGGER_STOP_S)
+#define ADC_SAR2_TRIGGER_STOP_V  0x00000001U
+#define ADC_SAR2_TRIGGER_STOP_S  0
+/** ADC_SAR2_TRIGGER_START : WT; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_TRIGGER_START    (BIT(1))
+#define ADC_SAR2_TRIGGER_START_M  (ADC_SAR2_TRIGGER_START_V << ADC_SAR2_TRIGGER_START_S)
+#define ADC_SAR2_TRIGGER_START_V  0x00000001U
+#define ADC_SAR2_TRIGGER_START_S  1
+/** ADC_SAR2_TRIGGER_MODE : R/W; bitpos: [3:2]; default: 0;
+ *  SAR clock divider
+ */
+#define ADC_SAR2_TRIGGER_MODE    0x00000003U
+#define ADC_SAR2_TRIGGER_MODE_M  (ADC_SAR2_TRIGGER_MODE_V << ADC_SAR2_TRIGGER_MODE_S)
+#define ADC_SAR2_TRIGGER_MODE_V  0x00000003U
+#define ADC_SAR2_TRIGGER_MODE_S  2
+/** ADC_SAR2_PATT_LEN : R/W; bitpos: [17:14]; default: 15;
+ *  0 ~ 15 means length 1 ~ 16
+ */
+#define ADC_SAR2_PATT_LEN    0x0000000FU
+#define ADC_SAR2_PATT_LEN_M  (ADC_SAR2_PATT_LEN_V << ADC_SAR2_PATT_LEN_S)
+#define ADC_SAR2_PATT_LEN_V  0x0000000FU
+#define ADC_SAR2_PATT_LEN_S  14
+/** ADC_SAR2_PATT_P_CLEAR : WT; bitpos: [22]; default: 0;
+ *  clear the pointer of pattern table for DIG ADC1 CTRL
+ */
+#define ADC_SAR2_PATT_P_CLEAR    (BIT(22))
+#define ADC_SAR2_PATT_P_CLEAR_M  (ADC_SAR2_PATT_P_CLEAR_V << ADC_SAR2_PATT_P_CLEAR_S)
+#define ADC_SAR2_PATT_P_CLEAR_V  0x00000001U
+#define ADC_SAR2_PATT_P_CLEAR_S  22
+/** ADC_SAR2_PATT_TYPE : R/W; bitpos: [23]; default: 0;
+ *  1: select meas start as table update 0:select mead done as table update
+ */
+#define ADC_SAR2_PATT_TYPE    (BIT(23))
+#define ADC_SAR2_PATT_TYPE_M  (ADC_SAR2_PATT_TYPE_V << ADC_SAR2_PATT_TYPE_S)
+#define ADC_SAR2_PATT_TYPE_V  0x00000001U
+#define ADC_SAR2_PATT_TYPE_S  23
+/** ADC_SAR2_CLK_POS_SEL : R/W; bitpos: [24]; default: 0;
+ *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+ *  resolution should not be larger than 11 bits.
+ */
+#define ADC_SAR2_CLK_POS_SEL    (BIT(24))
+#define ADC_SAR2_CLK_POS_SEL_M  (ADC_SAR2_CLK_POS_SEL_V << ADC_SAR2_CLK_POS_SEL_S)
+#define ADC_SAR2_CLK_POS_SEL_V  0x00000001U
+#define ADC_SAR2_CLK_POS_SEL_S  24
+/** ADC_SAR2_CONTINUE_MODE_EN : R/W; bitpos: [25]; default: 0;
+ *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+ */
+#define ADC_SAR2_CONTINUE_MODE_EN    (BIT(25))
+#define ADC_SAR2_CONTINUE_MODE_EN_M  (ADC_SAR2_CONTINUE_MODE_EN_V << ADC_SAR2_CONTINUE_MODE_EN_S)
+#define ADC_SAR2_CONTINUE_MODE_EN_V  0x00000001U
+#define ADC_SAR2_CONTINUE_MODE_EN_S  25
+/** ADC_XPD_SAR2_FORCE : R/W; bitpos: [27:26]; default: 0;
+ *  force option to xpd sar1 blocks
+ */
+#define ADC_XPD_SAR2_FORCE    0x00000003U
+#define ADC_XPD_SAR2_FORCE_M  (ADC_XPD_SAR2_FORCE_V << ADC_XPD_SAR2_FORCE_S)
+#define ADC_XPD_SAR2_FORCE_V  0x00000003U
+#define ADC_XPD_SAR2_FORCE_S  26
+
+/** ADC_CTRL2_REG register
+ *  Register
+ */
+#define ADC_CTRL2_REG (DR_REG_ADC_BASE + 0x8)
+/** ADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
+ *  to set saradc timer target
+ */
+#define ADC_TIMER_TARGET    0x00000FFFU
+#define ADC_TIMER_TARGET_M  (ADC_TIMER_TARGET_V << ADC_TIMER_TARGET_S)
+#define ADC_TIMER_TARGET_V  0x00000FFFU
+#define ADC_TIMER_TARGET_S  12
+/** ADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
+ *  to enable saradc timer trigger
+ */
+#define ADC_TIMER_EN    (BIT(24))
+#define ADC_TIMER_EN_M  (ADC_TIMER_EN_V << ADC_TIMER_EN_S)
+#define ADC_TIMER_EN_V  0x00000001U
+#define ADC_TIMER_EN_S  24
+
+/** ADC_FILTER_CTRL1_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL1_REG (DR_REG_ADC_BASE + 0xc)
+/** ADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR1    0x00000007U
+#define ADC_FILTER_FACTOR1_M  (ADC_FILTER_FACTOR1_V << ADC_FILTER_FACTOR1_S)
+#define ADC_FILTER_FACTOR1_V  0x00000007U
+#define ADC_FILTER_FACTOR1_S  26
+/** ADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
+ *  need_des
+ */
+#define ADC_FILTER_FACTOR0    0x00000007U
+#define ADC_FILTER_FACTOR0_M  (ADC_FILTER_FACTOR0_V << ADC_FILTER_FACTOR0_S)
+#define ADC_FILTER_FACTOR0_V  0x00000007U
+#define ADC_FILTER_FACTOR0_S  29
+
+/** ADC_SAR1_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x1c)
+/** ADC_SAR1_PATT_TAB1 : R/W; bitpos: [23:0]; default: 15728640;
+ *  item 0 ~ 3 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_M  (ADC_SAR1_PATT_TAB1_V << ADC_SAR1_PATT_TAB1_S)
+#define ADC_SAR1_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB1_S  0
+
+/** ADC_SAR1_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x20)
+/** ADC_SAR1_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_M  (ADC_SAR1_PATT_TAB2_V << ADC_SAR1_PATT_TAB2_S)
+#define ADC_SAR1_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB2_S  0
+
+/** ADC_SAR1_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x24)
+/** ADC_SAR1_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_M  (ADC_SAR1_PATT_TAB3_V << ADC_SAR1_PATT_TAB3_S)
+#define ADC_SAR1_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB3_S  0
+
+/** ADC_SAR1_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR1_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x28)
+/** ADC_SAR1_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+ */
+#define ADC_SAR1_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_M  (ADC_SAR1_PATT_TAB4_V << ADC_SAR1_PATT_TAB4_S)
+#define ADC_SAR1_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR1_PATT_TAB4_S  0
+
+/** ADC_SAR2_PATT_TAB1_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB1_REG (DR_REG_ADC_BASE + 0x2c)
+/** ADC_SAR2_PATT_TAB1 : R/W; bitpos: [23:0]; default: 15728640;
+ *  item 0 ~ 3 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB1    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_M  (ADC_SAR2_PATT_TAB1_V << ADC_SAR2_PATT_TAB1_S)
+#define ADC_SAR2_PATT_TAB1_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB1_S  0
+
+/** ADC_SAR2_PATT_TAB2_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB2_REG (DR_REG_ADC_BASE + 0x30)
+/** ADC_SAR2_PATT_TAB2 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB2    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_M  (ADC_SAR2_PATT_TAB2_V << ADC_SAR2_PATT_TAB2_S)
+#define ADC_SAR2_PATT_TAB2_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB2_S  0
+
+/** ADC_SAR2_PATT_TAB3_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB3_REG (DR_REG_ADC_BASE + 0x34)
+/** ADC_SAR2_PATT_TAB3 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB3    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_M  (ADC_SAR2_PATT_TAB3_V << ADC_SAR2_PATT_TAB3_S)
+#define ADC_SAR2_PATT_TAB3_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB3_S  0
+
+/** ADC_SAR2_PATT_TAB4_REG register
+ *  Register
+ */
+#define ADC_SAR2_PATT_TAB4_REG (DR_REG_ADC_BASE + 0x38)
+/** ADC_SAR2_PATT_TAB4 : R/W; bitpos: [23:0]; default: 0;
+ *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+ */
+#define ADC_SAR2_PATT_TAB4    0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_M  (ADC_SAR2_PATT_TAB4_V << ADC_SAR2_PATT_TAB4_S)
+#define ADC_SAR2_PATT_TAB4_V  0x00FFFFFFU
+#define ADC_SAR2_PATT_TAB4_S  0
+
+/** ADC_FILTER_CTRL0_REG register
+ *  Register
+ */
+#define ADC_FILTER_CTRL0_REG (DR_REG_ADC_BASE + 0x3c)
+/** ADC_FILTER_CHANNEL1 : R/W; bitpos: [18:14]; default: 13;
+ *  need_des
+ */
+#define ADC_FILTER_CHANNEL1    0x0000001FU
+#define ADC_FILTER_CHANNEL1_M  (ADC_FILTER_CHANNEL1_V << ADC_FILTER_CHANNEL1_S)
+#define ADC_FILTER_CHANNEL1_V  0x0000001FU
+#define ADC_FILTER_CHANNEL1_S  14
+/** ADC_FILTER_CHANNEL0 : R/W; bitpos: [23:19]; default: 13;
+ *  apb_adc1_filter_factor
+ */
+#define ADC_FILTER_CHANNEL0    0x0000001FU
+#define ADC_FILTER_CHANNEL0_M  (ADC_FILTER_CHANNEL0_V << ADC_FILTER_CHANNEL0_S)
+#define ADC_FILTER_CHANNEL0_V  0x0000001FU
+#define ADC_FILTER_CHANNEL0_S  19
+/** ADC_FILTER_RESET : WT; bitpos: [31]; default: 0;
+ *  enable apb_adc1_filter
+ */
+#define ADC_FILTER_RESET    (BIT(31))
+#define ADC_FILTER_RESET_M  (ADC_FILTER_RESET_V << ADC_FILTER_RESET_S)
+#define ADC_FILTER_RESET_V  0x00000001U
+#define ADC_FILTER_RESET_S  31
+
+/** ADC_SAR1_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR1_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x40)
+/** ADC_APB_SARADC1_DATA : RO; bitpos: [21:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC1_DATA    0x003FFFFFU
+#define ADC_APB_SARADC1_DATA_M  (ADC_APB_SARADC1_DATA_V << ADC_APB_SARADC1_DATA_S)
+#define ADC_APB_SARADC1_DATA_V  0x003FFFFFU
+#define ADC_APB_SARADC1_DATA_S  0
+
+/** ADC_SAR2_DATA_STATUS_REG register
+ *  Register
+ */
+#define ADC_SAR2_DATA_STATUS_REG (DR_REG_ADC_BASE + 0x44)
+/** ADC_APB_SARADC2_DATA : RO; bitpos: [21:0]; default: 0;
+ *  need_des
+ */
+#define ADC_APB_SARADC2_DATA    0x003FFFFFU
+#define ADC_APB_SARADC2_DATA_M  (ADC_APB_SARADC2_DATA_V << ADC_APB_SARADC2_DATA_S)
+#define ADC_APB_SARADC2_DATA_V  0x003FFFFFU
+#define ADC_APB_SARADC2_DATA_S  0
+
+/** ADC_THRES0_HIGH_THRES_REG register
+ *  Register
+ */
+#define ADC_THRES0_HIGH_THRES_REG (DR_REG_ADC_BASE + 0x48)
+/** ADC_THRES0_HIGH : R/W; bitpos: [16:0]; default: 255;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH    0x0001FFFFU
+#define ADC_THRES0_HIGH_M  (ADC_THRES0_HIGH_V << ADC_THRES0_HIGH_S)
+#define ADC_THRES0_HIGH_V  0x0001FFFFU
+#define ADC_THRES0_HIGH_S  0
+
+/** ADC_THRES0_LOW_THRES_REG register
+ *  Register
+ */
+#define ADC_THRES0_LOW_THRES_REG (DR_REG_ADC_BASE + 0x4c)
+/** ADC_THRES0_LOW : R/W; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW    0x0001FFFFU
+#define ADC_THRES0_LOW_M  (ADC_THRES0_LOW_V << ADC_THRES0_LOW_S)
+#define ADC_THRES0_LOW_V  0x0001FFFFU
+#define ADC_THRES0_LOW_S  0
+
+/** ADC_THRES0_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES0_CTRL_REG (DR_REG_ADC_BASE + 0x50)
+/** ADC_THRES0_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES0_CHANNEL    0x0000001FU
+#define ADC_THRES0_CHANNEL_M  (ADC_THRES0_CHANNEL_V << ADC_THRES0_CHANNEL_S)
+#define ADC_THRES0_CHANNEL_V  0x0000001FU
+#define ADC_THRES0_CHANNEL_S  0
+/** ADC_THRES0_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_EN    (BIT(5))
+#define ADC_THRES0_EN_M  (ADC_THRES0_EN_V << ADC_THRES0_EN_S)
+#define ADC_THRES0_EN_V  0x00000001U
+#define ADC_THRES0_EN_S  5
+
+/** ADC_THRES1_HIGH_THRES_REG register
+ *  Register
+ */
+#define ADC_THRES1_HIGH_THRES_REG (DR_REG_ADC_BASE + 0x54)
+/** ADC_THRES1_HIGH : R/W; bitpos: [16:0]; default: 255;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH    0x0001FFFFU
+#define ADC_THRES1_HIGH_M  (ADC_THRES1_HIGH_V << ADC_THRES1_HIGH_S)
+#define ADC_THRES1_HIGH_V  0x0001FFFFU
+#define ADC_THRES1_HIGH_S  0
+
+/** ADC_THRES1_LOW_THRES_REG register
+ *  Register
+ */
+#define ADC_THRES1_LOW_THRES_REG (DR_REG_ADC_BASE + 0x58)
+/** ADC_THRES1_LOW : R/W; bitpos: [16:0]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW    0x0001FFFFU
+#define ADC_THRES1_LOW_M  (ADC_THRES1_LOW_V << ADC_THRES1_LOW_S)
+#define ADC_THRES1_LOW_V  0x0001FFFFU
+#define ADC_THRES1_LOW_S  0
+
+/** ADC_THRES1_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES1_CTRL_REG (DR_REG_ADC_BASE + 0x5c)
+/** ADC_THRES1_CHANNEL : R/W; bitpos: [4:0]; default: 13;
+ *  need_des
+ */
+#define ADC_THRES1_CHANNEL    0x0000001FU
+#define ADC_THRES1_CHANNEL_M  (ADC_THRES1_CHANNEL_V << ADC_THRES1_CHANNEL_S)
+#define ADC_THRES1_CHANNEL_V  0x0000001FU
+#define ADC_THRES1_CHANNEL_S  0
+/** ADC_THRES1_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_EN    (BIT(5))
+#define ADC_THRES1_EN_M  (ADC_THRES1_EN_V << ADC_THRES1_EN_S)
+#define ADC_THRES1_EN_V  0x00000001U
+#define ADC_THRES1_EN_S  5
+
+/** ADC_THRES_CTRL_REG register
+ *  Register
+ */
+#define ADC_THRES_CTRL_REG (DR_REG_ADC_BASE + 0x60)
+/** ADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES_ALL_EN    (BIT(27))
+#define ADC_THRES_ALL_EN_M  (ADC_THRES_ALL_EN_V << ADC_THRES_ALL_EN_S)
+#define ADC_THRES_ALL_EN_V  0x00000001U
+#define ADC_THRES_ALL_EN_S  27
+
+/** ADC_INT_ENA_REG register
+ *  Register
+ */
+#define ADC_INT_ENA_REG (DR_REG_ADC_BASE + 0x64)
+/** ADC_FIFO_OVERFLOW_INT_ENA : R/W; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define ADC_FIFO_OVERFLOW_INT_ENA    (BIT(25))
+#define ADC_FIFO_OVERFLOW_INT_ENA_M  (ADC_FIFO_OVERFLOW_INT_ENA_V << ADC_FIFO_OVERFLOW_INT_ENA_S)
+#define ADC_FIFO_OVERFLOW_INT_ENA_V  0x00000001U
+#define ADC_FIFO_OVERFLOW_INT_ENA_S  25
+/** ADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ENA    (BIT(26))
+#define ADC_THRES1_LOW_INT_ENA_M  (ADC_THRES1_LOW_INT_ENA_V << ADC_THRES1_LOW_INT_ENA_S)
+#define ADC_THRES1_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ENA_S  26
+/** ADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ENA    (BIT(27))
+#define ADC_THRES0_LOW_INT_ENA_M  (ADC_THRES0_LOW_INT_ENA_V << ADC_THRES0_LOW_INT_ENA_S)
+#define ADC_THRES0_LOW_INT_ENA_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ENA_S  27
+/** ADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ENA    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ENA_M  (ADC_THRES1_HIGH_INT_ENA_V << ADC_THRES1_HIGH_INT_ENA_S)
+#define ADC_THRES1_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ENA_S  28
+/** ADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ENA    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ENA_M  (ADC_THRES0_HIGH_INT_ENA_V << ADC_THRES0_HIGH_INT_ENA_S)
+#define ADC_THRES0_HIGH_INT_ENA_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ENA_S  29
+/** ADC_SAR2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ENA    (BIT(30))
+#define ADC_SAR2_DONE_INT_ENA_M  (ADC_SAR2_DONE_INT_ENA_V << ADC_SAR2_DONE_INT_ENA_S)
+#define ADC_SAR2_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ENA_S  30
+/** ADC_SAR1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ENA    (BIT(31))
+#define ADC_SAR1_DONE_INT_ENA_M  (ADC_SAR1_DONE_INT_ENA_V << ADC_SAR1_DONE_INT_ENA_S)
+#define ADC_SAR1_DONE_INT_ENA_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ENA_S  31
+
+/** ADC_INT_RAW_REG register
+ *  Register
+ */
+#define ADC_INT_RAW_REG (DR_REG_ADC_BASE + 0x68)
+/** ADC_FIFO_OVERFLOW_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define ADC_FIFO_OVERFLOW_INT_RAW    (BIT(25))
+#define ADC_FIFO_OVERFLOW_INT_RAW_M  (ADC_FIFO_OVERFLOW_INT_RAW_V << ADC_FIFO_OVERFLOW_INT_RAW_S)
+#define ADC_FIFO_OVERFLOW_INT_RAW_V  0x00000001U
+#define ADC_FIFO_OVERFLOW_INT_RAW_S  25
+/** ADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_RAW    (BIT(26))
+#define ADC_THRES1_LOW_INT_RAW_M  (ADC_THRES1_LOW_INT_RAW_V << ADC_THRES1_LOW_INT_RAW_S)
+#define ADC_THRES1_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES1_LOW_INT_RAW_S  26
+/** ADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_RAW    (BIT(27))
+#define ADC_THRES0_LOW_INT_RAW_M  (ADC_THRES0_LOW_INT_RAW_V << ADC_THRES0_LOW_INT_RAW_S)
+#define ADC_THRES0_LOW_INT_RAW_V  0x00000001U
+#define ADC_THRES0_LOW_INT_RAW_S  27
+/** ADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_RAW    (BIT(28))
+#define ADC_THRES1_HIGH_INT_RAW_M  (ADC_THRES1_HIGH_INT_RAW_V << ADC_THRES1_HIGH_INT_RAW_S)
+#define ADC_THRES1_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_RAW_S  28
+/** ADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_RAW    (BIT(29))
+#define ADC_THRES0_HIGH_INT_RAW_M  (ADC_THRES0_HIGH_INT_RAW_V << ADC_THRES0_HIGH_INT_RAW_S)
+#define ADC_THRES0_HIGH_INT_RAW_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_RAW_S  29
+/** ADC_SAR2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_RAW    (BIT(30))
+#define ADC_SAR2_DONE_INT_RAW_M  (ADC_SAR2_DONE_INT_RAW_V << ADC_SAR2_DONE_INT_RAW_S)
+#define ADC_SAR2_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR2_DONE_INT_RAW_S  30
+/** ADC_SAR1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_RAW    (BIT(31))
+#define ADC_SAR1_DONE_INT_RAW_M  (ADC_SAR1_DONE_INT_RAW_V << ADC_SAR1_DONE_INT_RAW_S)
+#define ADC_SAR1_DONE_INT_RAW_V  0x00000001U
+#define ADC_SAR1_DONE_INT_RAW_S  31
+
+/** ADC_INT_ST_REG register
+ *  Register
+ */
+#define ADC_INT_ST_REG (DR_REG_ADC_BASE + 0x6c)
+/** ADC_FIFO_OVERFLOW_INT_ST : RO; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define ADC_FIFO_OVERFLOW_INT_ST    (BIT(25))
+#define ADC_FIFO_OVERFLOW_INT_ST_M  (ADC_FIFO_OVERFLOW_INT_ST_V << ADC_FIFO_OVERFLOW_INT_ST_S)
+#define ADC_FIFO_OVERFLOW_INT_ST_V  0x00000001U
+#define ADC_FIFO_OVERFLOW_INT_ST_S  25
+/** ADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_ST    (BIT(26))
+#define ADC_THRES1_LOW_INT_ST_M  (ADC_THRES1_LOW_INT_ST_V << ADC_THRES1_LOW_INT_ST_S)
+#define ADC_THRES1_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES1_LOW_INT_ST_S  26
+/** ADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_ST    (BIT(27))
+#define ADC_THRES0_LOW_INT_ST_M  (ADC_THRES0_LOW_INT_ST_V << ADC_THRES0_LOW_INT_ST_S)
+#define ADC_THRES0_LOW_INT_ST_V  0x00000001U
+#define ADC_THRES0_LOW_INT_ST_S  27
+/** ADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_ST    (BIT(28))
+#define ADC_THRES1_HIGH_INT_ST_M  (ADC_THRES1_HIGH_INT_ST_V << ADC_THRES1_HIGH_INT_ST_S)
+#define ADC_THRES1_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_ST_S  28
+/** ADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_ST    (BIT(29))
+#define ADC_THRES0_HIGH_INT_ST_M  (ADC_THRES0_HIGH_INT_ST_V << ADC_THRES0_HIGH_INT_ST_S)
+#define ADC_THRES0_HIGH_INT_ST_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_ST_S  29
+/** ADC_SAR2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_ST    (BIT(30))
+#define ADC_SAR2_DONE_INT_ST_M  (ADC_SAR2_DONE_INT_ST_V << ADC_SAR2_DONE_INT_ST_S)
+#define ADC_SAR2_DONE_INT_ST_V  0x00000001U
+#define ADC_SAR2_DONE_INT_ST_S  30
+/** ADC_SAR1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_ST    (BIT(31))
+#define ADC_SAR1_DONE_INT_ST_M  (ADC_SAR1_DONE_INT_ST_V << ADC_SAR1_DONE_INT_ST_S)
+#define ADC_SAR1_DONE_INT_ST_V  0x00000001U
+#define ADC_SAR1_DONE_INT_ST_S  31
+
+/** ADC_INT_CLR_REG register
+ *  Register
+ */
+#define ADC_INT_CLR_REG (DR_REG_ADC_BASE + 0x70)
+/** ADC_FIFO_OVERFLOW_INT_CLR : WT; bitpos: [25]; default: 0;
+ *  need_des
+ */
+#define ADC_FIFO_OVERFLOW_INT_CLR    (BIT(25))
+#define ADC_FIFO_OVERFLOW_INT_CLR_M  (ADC_FIFO_OVERFLOW_INT_CLR_V << ADC_FIFO_OVERFLOW_INT_CLR_S)
+#define ADC_FIFO_OVERFLOW_INT_CLR_V  0x00000001U
+#define ADC_FIFO_OVERFLOW_INT_CLR_S  25
+/** ADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_LOW_INT_CLR    (BIT(26))
+#define ADC_THRES1_LOW_INT_CLR_M  (ADC_THRES1_LOW_INT_CLR_V << ADC_THRES1_LOW_INT_CLR_S)
+#define ADC_THRES1_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES1_LOW_INT_CLR_S  26
+/** ADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_LOW_INT_CLR    (BIT(27))
+#define ADC_THRES0_LOW_INT_CLR_M  (ADC_THRES0_LOW_INT_CLR_V << ADC_THRES0_LOW_INT_CLR_S)
+#define ADC_THRES0_LOW_INT_CLR_V  0x00000001U
+#define ADC_THRES0_LOW_INT_CLR_S  27
+/** ADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES1_HIGH_INT_CLR    (BIT(28))
+#define ADC_THRES1_HIGH_INT_CLR_M  (ADC_THRES1_HIGH_INT_CLR_V << ADC_THRES1_HIGH_INT_CLR_S)
+#define ADC_THRES1_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES1_HIGH_INT_CLR_S  28
+/** ADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
+ *  need_des
+ */
+#define ADC_THRES0_HIGH_INT_CLR    (BIT(29))
+#define ADC_THRES0_HIGH_INT_CLR_M  (ADC_THRES0_HIGH_INT_CLR_V << ADC_THRES0_HIGH_INT_CLR_S)
+#define ADC_THRES0_HIGH_INT_CLR_V  0x00000001U
+#define ADC_THRES0_HIGH_INT_CLR_S  29
+/** ADC_SAR2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR2_DONE_INT_CLR    (BIT(30))
+#define ADC_SAR2_DONE_INT_CLR_M  (ADC_SAR2_DONE_INT_CLR_V << ADC_SAR2_DONE_INT_CLR_S)
+#define ADC_SAR2_DONE_INT_CLR_V  0x00000001U
+#define ADC_SAR2_DONE_INT_CLR_S  30
+/** ADC_SAR1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_SAR1_DONE_INT_CLR    (BIT(31))
+#define ADC_SAR1_DONE_INT_CLR_M  (ADC_SAR1_DONE_INT_CLR_V << ADC_SAR1_DONE_INT_CLR_S)
+#define ADC_SAR1_DONE_INT_CLR_V  0x00000001U
+#define ADC_SAR1_DONE_INT_CLR_S  31
+
+/** ADC_DMA_CONF_REG register
+ *  Register
+ */
+#define ADC_DMA_CONF_REG (DR_REG_ADC_BASE + 0x74)
+/** ADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
+ *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+ */
+#define ADC_APB_ADC_EOF_NUM    0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_M  (ADC_APB_ADC_EOF_NUM_V << ADC_APB_ADC_EOF_NUM_S)
+#define ADC_APB_ADC_EOF_NUM_V  0x0000FFFFU
+#define ADC_APB_ADC_EOF_NUM_S  0
+/** ADC_DMA_EOF_NUM_CLR : WT; bitpos: [16]; default: 0;
+ *  clear eof cnt
+ */
+#define ADC_DMA_EOF_NUM_CLR    (BIT(16))
+#define ADC_DMA_EOF_NUM_CLR_M  (ADC_DMA_EOF_NUM_CLR_V << ADC_DMA_EOF_NUM_CLR_S)
+#define ADC_DMA_EOF_NUM_CLR_V  0x00000001U
+#define ADC_DMA_EOF_NUM_CLR_S  16
+/** ADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
+ *  enable apb_adc use spi_dma
+ */
+#define ADC_APB_ADC_TRANS    (BIT(31))
+#define ADC_APB_ADC_TRANS_M  (ADC_APB_ADC_TRANS_V << ADC_APB_ADC_TRANS_S)
+#define ADC_APB_ADC_TRANS_V  0x00000001U
+#define ADC_APB_ADC_TRANS_S  31
+
+/** ADC_REF_CONTROL_REG register
+ *  Register
+ */
+#define ADC_REF_CONTROL_REG (DR_REG_ADC_BASE + 0x78)
+/** ADC_RTC_REF_DELAY : R/W; bitpos: [29]; default: 0;
+ *  control the refgen short vdd
+ */
+#define ADC_RTC_REF_DELAY    (BIT(29))
+#define ADC_RTC_REF_DELAY_M  (ADC_RTC_REF_DELAY_V << ADC_RTC_REF_DELAY_S)
+#define ADC_RTC_REF_DELAY_V  0x00000001U
+#define ADC_RTC_REF_DELAY_S  29
+/** ADC_RTC_PRE_CHARGE : R/W; bitpos: [30]; default: 0;
+ *  control the refgen module pre charge
+ */
+#define ADC_RTC_PRE_CHARGE    (BIT(30))
+#define ADC_RTC_PRE_CHARGE_M  (ADC_RTC_PRE_CHARGE_V << ADC_RTC_PRE_CHARGE_S)
+#define ADC_RTC_PRE_CHARGE_V  0x00000001U
+#define ADC_RTC_PRE_CHARGE_S  30
+/** ADC_RTC_XPD_REFGEN : R/W; bitpos: [31]; default: 0;
+ *  control the refgen module power up
+ */
+#define ADC_RTC_XPD_REFGEN    (BIT(31))
+#define ADC_RTC_XPD_REFGEN_M  (ADC_RTC_XPD_REFGEN_V << ADC_RTC_XPD_REFGEN_S)
+#define ADC_RTC_XPD_REFGEN_V  0x00000001U
+#define ADC_RTC_XPD_REFGEN_S  31
+
+/** ADC_RND_ECO_LOW_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_LOW_REG (DR_REG_ADC_BASE + 0x7c)
+/** ADC_ADC_RND_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  rnd eco low
+ */
+#define ADC_ADC_RND_ECO_LOW    0xFFFFFFFFU
+#define ADC_ADC_RND_ECO_LOW_M  (ADC_ADC_RND_ECO_LOW_V << ADC_ADC_RND_ECO_LOW_S)
+#define ADC_ADC_RND_ECO_LOW_V  0xFFFFFFFFU
+#define ADC_ADC_RND_ECO_LOW_S  0
+
+/** ADC_RND_ECO_HIGH_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_HIGH_REG (DR_REG_ADC_BASE + 0x80)
+/** ADC_ADC_RND_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  rnd eco high
+ */
+#define ADC_ADC_RND_ECO_HIGH    0xFFFFFFFFU
+#define ADC_ADC_RND_ECO_HIGH_M  (ADC_ADC_RND_ECO_HIGH_V << ADC_ADC_RND_ECO_HIGH_S)
+#define ADC_ADC_RND_ECO_HIGH_V  0xFFFFFFFFU
+#define ADC_ADC_RND_ECO_HIGH_S  0
+
+/** ADC_RND_ECO_CS_REG register
+ *  Register
+ */
+#define ADC_RND_ECO_CS_REG (DR_REG_ADC_BASE + 0x84)
+/** ADC_RND_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_EN    (BIT(0))
+#define ADC_RND_ECO_EN_M  (ADC_RND_ECO_EN_V << ADC_RND_ECO_EN_S)
+#define ADC_RND_ECO_EN_V  0x00000001U
+#define ADC_RND_ECO_EN_S  0
+/** ADC_RND_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define ADC_RND_ECO_RESULT    (BIT(1))
+#define ADC_RND_ECO_RESULT_M  (ADC_RND_ECO_RESULT_V << ADC_RND_ECO_RESULT_S)
+#define ADC_RND_ECO_RESULT_V  0x00000001U
+#define ADC_RND_ECO_RESULT_S  1
+
+/** ADC_CTRL_DATE_REG register
+ *  Register
+ */
+#define ADC_CTRL_DATE_REG (DR_REG_ADC_BASE + 0x3fc)
+/** ADC_CTRL_DATE : R/W; bitpos: [30:0]; default: 38830624;
+ *  need_des
+ */
+#define ADC_CTRL_DATE    0x7FFFFFFFU
+#define ADC_CTRL_DATE_M  (ADC_CTRL_DATE_V << ADC_CTRL_DATE_S)
+#define ADC_CTRL_DATE_V  0x7FFFFFFFU
+#define ADC_CTRL_DATE_S  0
+/** ADC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define ADC_CLK_EN    (BIT(31))
+#define ADC_CLK_EN_M  (ADC_CLK_EN_V << ADC_CLK_EN_S)
+#define ADC_CLK_EN_V  0x00000001U
+#define ADC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/adc_struct.h b/components/soc/esp32s31/register/soc/adc_struct.h
new file mode 100644
index 00000000000..143a7c59425
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/adc_struct.h
@@ -0,0 +1,721 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configure Register */
+/** Type of ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_trigger_stop : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_trigger_stop:1;
+        /** sar1_trigger_start : WT; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_trigger_start:1;
+        /** sar1_trigger_mode : R/W; bitpos: [3:2]; default: 0;
+         *  SAR clock divider
+         */
+        uint32_t sar1_trigger_mode:2;
+        uint32_t reserved_4:10;
+        /** sar1_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar1_patt_len:4;
+        uint32_t reserved_18:4;
+        /** sar1_patt_p_clear : WT; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar1_patt_p_clear:1;
+        /** sar1_patt_type : R/W; bitpos: [23]; default: 0;
+         *  1: select meas start as table update 0:select mead done as table update
+         */
+        uint32_t sar1_patt_type:1;
+        /** sar1_clk_pos_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t sar1_clk_pos_sel:1;
+        /** sar1_continue_mode_en : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t sar1_continue_mode_en:1;
+        /** xpd_sar1_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar1_force:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} adc_ctrl0_reg_t;
+
+/** Type of ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_trigger_stop : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_trigger_stop:1;
+        /** sar2_trigger_start : WT; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_trigger_start:1;
+        /** sar2_trigger_mode : R/W; bitpos: [3:2]; default: 0;
+         *  SAR clock divider
+         */
+        uint32_t sar2_trigger_mode:2;
+        uint32_t reserved_4:10;
+        /** sar2_patt_len : R/W; bitpos: [17:14]; default: 15;
+         *  0 ~ 15 means length 1 ~ 16
+         */
+        uint32_t sar2_patt_len:4;
+        uint32_t reserved_18:4;
+        /** sar2_patt_p_clear : WT; bitpos: [22]; default: 0;
+         *  clear the pointer of pattern table for DIG ADC1 CTRL
+         */
+        uint32_t sar2_patt_p_clear:1;
+        /** sar2_patt_type : R/W; bitpos: [23]; default: 0;
+         *  1: select meas start as table update 0:select mead done as table update
+         */
+        uint32_t sar2_patt_type:1;
+        /** sar2_clk_pos_sel : R/W; bitpos: [24]; default: 0;
+         *  1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
+         *  resolution should not be larger than 11 bits.
+         */
+        uint32_t sar2_clk_pos_sel:1;
+        /** sar2_continue_mode_en : R/W; bitpos: [25]; default: 0;
+         *  1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix
+         */
+        uint32_t sar2_continue_mode_en:1;
+        /** xpd_sar2_force : R/W; bitpos: [27:26]; default: 0;
+         *  force option to xpd sar1 blocks
+         */
+        uint32_t xpd_sar2_force:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} adc_ctrl1_reg_t;
+
+/** Type of ctrl2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** timer_target : R/W; bitpos: [23:12]; default: 10;
+         *  to set saradc timer target
+         */
+        uint32_t timer_target:12;
+        /** timer_en : R/W; bitpos: [24]; default: 0;
+         *  to enable saradc timer trigger
+         */
+        uint32_t timer_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} adc_ctrl2_reg_t;
+
+/** Type of filter_ctrl1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** filter_factor1 : R/W; bitpos: [28:26]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor1:3;
+        /** filter_factor0 : R/W; bitpos: [31:29]; default: 0;
+         *  need_des
+         */
+        uint32_t filter_factor0:3;
+    };
+    uint32_t val;
+} adc_filter_ctrl1_reg_t;
+
+/** Type of sar1_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab1 : R/W; bitpos: [23:0]; default: 15728640;
+         *  item 0 ~ 3 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab1_reg_t;
+
+/** Type of sar1_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab2_reg_t;
+
+/** Type of sar1_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab3_reg_t;
+
+/** Type of sar1_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar1_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 1 (each item one byte)
+         */
+        uint32_t sar1_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar1_patt_tab4_reg_t;
+
+/** Type of sar2_patt_tab1 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab1 : R/W; bitpos: [23:0]; default: 15728640;
+         *  item 0 ~ 3 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab1:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab1_reg_t;
+
+/** Type of sar2_patt_tab2 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab2 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 4 ~ 7 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab2:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab2_reg_t;
+
+/** Type of sar2_patt_tab3 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab3 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 8 ~ 11 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab3:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab3_reg_t;
+
+/** Type of sar2_patt_tab4 register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** sar2_patt_tab4 : R/W; bitpos: [23:0]; default: 0;
+         *  Item 12 ~ 15 for pattern table 2 (each item one byte)
+         */
+        uint32_t sar2_patt_tab4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} adc_sar2_patt_tab4_reg_t;
+
+/** Type of filter_ctrl0 register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** filter_channel1 : R/W; bitpos: [18:14]; default: 13;
+         *  need_des
+         */
+        uint32_t filter_channel1:5;
+        /** filter_channel0 : R/W; bitpos: [23:19]; default: 13;
+         *  apb_adc1_filter_factor
+         */
+        uint32_t filter_channel0:5;
+        uint32_t reserved_24:7;
+        /** filter_reset : WT; bitpos: [31]; default: 0;
+         *  enable apb_adc1_filter
+         */
+        uint32_t filter_reset:1;
+    };
+    uint32_t val;
+} adc_filter_ctrl0_reg_t;
+
+/** Type of sar1_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc1_data : RO; bitpos: [21:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc1_data:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} adc_sar1_data_status_reg_t;
+
+/** Type of sar2_data_status register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_saradc2_data : RO; bitpos: [21:0]; default: 0;
+         *  need_des
+         */
+        uint32_t apb_saradc2_data:22;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} adc_sar2_data_status_reg_t;
+
+/** Type of thres0_high_thres register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_high : R/W; bitpos: [16:0]; default: 255;
+         *  need_des
+         */
+        uint32_t thres0_high:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_thres0_high_thres_reg_t;
+
+/** Type of thres0_low_thres register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_low : R/W; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_thres0_low_thres_reg_t;
+
+/** Type of thres0_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres0_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres0_channel:5;
+        /** thres0_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} adc_thres0_ctrl_reg_t;
+
+/** Type of thres1_high_thres register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_high : R/W; bitpos: [16:0]; default: 255;
+         *  need_des
+         */
+        uint32_t thres1_high:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_thres1_high_thres_reg_t;
+
+/** Type of thres1_low_thres register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_low : R/W; bitpos: [16:0]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low:17;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} adc_thres1_low_thres_reg_t;
+
+/** Type of thres1_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** thres1_channel : R/W; bitpos: [4:0]; default: 13;
+         *  need_des
+         */
+        uint32_t thres1_channel:5;
+        /** thres1_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} adc_thres1_ctrl_reg_t;
+
+/** Type of thres_ctrl register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** thres_all_en : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres_all_en:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} adc_thres_ctrl_reg_t;
+
+/** Type of int_ena register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** fifo_overflow_int_ena : R/W; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t fifo_overflow_int_ena:1;
+        /** thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_ena:1;
+        /** thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_ena:1;
+        /** thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_ena:1;
+        /** thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_ena:1;
+        /** sar2_done_int_ena : R/W; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_ena:1;
+        /** sar1_done_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_ena:1;
+    };
+    uint32_t val;
+} adc_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** fifo_overflow_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t fifo_overflow_int_raw:1;
+        /** thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_raw:1;
+        /** thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_raw:1;
+        /** thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_raw:1;
+        /** thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_raw:1;
+        /** sar2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_raw:1;
+        /** sar1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_raw:1;
+    };
+    uint32_t val;
+} adc_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** fifo_overflow_int_st : RO; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t fifo_overflow_int_st:1;
+        /** thres1_low_int_st : RO; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_st:1;
+        /** thres0_low_int_st : RO; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_st:1;
+        /** thres1_high_int_st : RO; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_st:1;
+        /** thres0_high_int_st : RO; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_st:1;
+        /** sar2_done_int_st : RO; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_st:1;
+        /** sar1_done_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_st:1;
+    };
+    uint32_t val;
+} adc_int_st_reg_t;
+
+/** Type of int_clr register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:25;
+        /** fifo_overflow_int_clr : WT; bitpos: [25]; default: 0;
+         *  need_des
+         */
+        uint32_t fifo_overflow_int_clr:1;
+        /** thres1_low_int_clr : WT; bitpos: [26]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_low_int_clr:1;
+        /** thres0_low_int_clr : WT; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_low_int_clr:1;
+        /** thres1_high_int_clr : WT; bitpos: [28]; default: 0;
+         *  need_des
+         */
+        uint32_t thres1_high_int_clr:1;
+        /** thres0_high_int_clr : WT; bitpos: [29]; default: 0;
+         *  need_des
+         */
+        uint32_t thres0_high_int_clr:1;
+        /** sar2_done_int_clr : WT; bitpos: [30]; default: 0;
+         *  need_des
+         */
+        uint32_t sar2_done_int_clr:1;
+        /** sar1_done_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t sar1_done_int_clr:1;
+    };
+    uint32_t val;
+} adc_int_clr_reg_t;
+
+/** Type of dma_conf register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
+         *  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+         */
+        uint32_t apb_adc_eof_num:16;
+        /** dma_eof_num_clr : WT; bitpos: [16]; default: 0;
+         *  clear eof cnt
+         */
+        uint32_t dma_eof_num_clr:1;
+        uint32_t reserved_17:14;
+        /** apb_adc_trans : R/W; bitpos: [31]; default: 0;
+         *  enable apb_adc use spi_dma
+         */
+        uint32_t apb_adc_trans:1;
+    };
+    uint32_t val;
+} adc_dma_conf_reg_t;
+
+/** Type of ref_control register
+ *  Register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** rtc_ref_delay : R/W; bitpos: [29]; default: 0;
+         *  control the refgen short vdd
+         */
+        uint32_t rtc_ref_delay:1;
+        /** rtc_pre_charge : R/W; bitpos: [30]; default: 0;
+         *  control the refgen module pre charge
+         */
+        uint32_t rtc_pre_charge:1;
+        /** rtc_xpd_refgen : R/W; bitpos: [31]; default: 0;
+         *  control the refgen module power up
+         */
+        uint32_t rtc_xpd_refgen:1;
+    };
+    uint32_t val;
+} adc_ref_control_reg_t;
+
+/** Type of rnd_eco_low register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** adc_rnd_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  rnd eco low
+         */
+        uint32_t adc_rnd_eco_low:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_low_reg_t;
+
+/** Type of rnd_eco_high register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** adc_rnd_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  rnd eco high
+         */
+        uint32_t adc_rnd_eco_high:32;
+    };
+    uint32_t val;
+} adc_rnd_eco_high_reg_t;
+
+/** Type of rnd_eco_cs register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** rnd_eco_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_en:1;
+        /** rnd_eco_result : RO; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t rnd_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} adc_rnd_eco_cs_reg_t;
+
+/** Type of ctrl_date register
+ *  Register
+ */
+typedef union {
+    struct {
+        /** ctrl_date : R/W; bitpos: [30:0]; default: 38830624;
+         *  need_des
+         */
+        uint32_t ctrl_date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} adc_ctrl_date_reg_t;
+
+
+typedef struct {
+    volatile adc_ctrl0_reg_t ctrl0;
+    volatile adc_ctrl1_reg_t ctrl1;
+    volatile adc_ctrl2_reg_t ctrl2;
+    volatile adc_filter_ctrl1_reg_t filter_ctrl1;
+    uint32_t reserved_010[3];
+    volatile adc_sar1_patt_tab1_reg_t sar1_patt_tab1;
+    volatile adc_sar1_patt_tab2_reg_t sar1_patt_tab2;
+    volatile adc_sar1_patt_tab3_reg_t sar1_patt_tab3;
+    volatile adc_sar1_patt_tab4_reg_t sar1_patt_tab4;
+    volatile adc_sar2_patt_tab1_reg_t sar2_patt_tab1;
+    volatile adc_sar2_patt_tab2_reg_t sar2_patt_tab2;
+    volatile adc_sar2_patt_tab3_reg_t sar2_patt_tab3;
+    volatile adc_sar2_patt_tab4_reg_t sar2_patt_tab4;
+    volatile adc_filter_ctrl0_reg_t filter_ctrl0;
+    volatile adc_sar1_data_status_reg_t sar1_data_status;
+    volatile adc_sar2_data_status_reg_t sar2_data_status;
+    volatile adc_thres0_high_thres_reg_t thres0_high_thres;
+    volatile adc_thres0_low_thres_reg_t thres0_low_thres;
+    volatile adc_thres0_ctrl_reg_t thres0_ctrl;
+    volatile adc_thres1_high_thres_reg_t thres1_high_thres;
+    volatile adc_thres1_low_thres_reg_t thres1_low_thres;
+    volatile adc_thres1_ctrl_reg_t thres1_ctrl;
+    volatile adc_thres_ctrl_reg_t thres_ctrl;
+    volatile adc_int_ena_reg_t int_ena;
+    volatile adc_int_raw_reg_t int_raw;
+    volatile adc_int_st_reg_t int_st;
+    volatile adc_int_clr_reg_t int_clr;
+    volatile adc_dma_conf_reg_t dma_conf;
+    volatile adc_ref_control_reg_t ref_control;
+    volatile adc_rnd_eco_low_reg_t rnd_eco_low;
+    volatile adc_rnd_eco_high_reg_t rnd_eco_high;
+    volatile adc_rnd_eco_cs_reg_t rnd_eco_cs;
+    uint32_t reserved_088[221];
+    volatile adc_ctrl_date_reg_t ctrl_date;
+} adc_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/aes_reg.h b/components/soc/esp32s31/register/soc/aes_reg.h
new file mode 100644
index 00000000000..d05bbb42021
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/aes_reg.h
@@ -0,0 +1,484 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AES_KEY_0_REG register
+ *  AES key data register 0
+ */
+#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_1_REG register
+ *  AES key data register 1
+ */
+#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_2_REG register
+ *  AES key data register 2
+ */
+#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_3_REG register
+ *  AES key data register 3
+ */
+#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_4_REG register
+ *  AES key data register 4
+ */
+#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_5_REG register
+ *  AES key data register 5
+ */
+#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_6_REG register
+ *  AES key data register 6
+ */
+#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_KEY_7_REG register
+ *  AES key data register 7
+ */
+#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
+/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores key_0 that is a part of key material.
+ */
+#define AES_KEY_0    0xFFFFFFFFU
+#define AES_KEY_0_M  (AES_KEY_0_V << AES_KEY_0_S)
+#define AES_KEY_0_V  0xFFFFFFFFU
+#define AES_KEY_0_S  0
+
+/** AES_TEXT_IN_0_REG register
+ *  Source text data register 0
+ */
+#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_1_REG register
+ *  Source text data register 1
+ */
+#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_2_REG register
+ *  Source text data register 2
+ */
+#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_IN_3_REG register
+ *  Source text data register 3
+ */
+#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
+/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_in_0 that is a part of source text material.
+ */
+#define AES_TEXT_IN_0    0xFFFFFFFFU
+#define AES_TEXT_IN_0_M  (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
+#define AES_TEXT_IN_0_V  0xFFFFFFFFU
+#define AES_TEXT_IN_0_S  0
+
+/** AES_TEXT_OUT_0_REG register
+ *  Result text data register 0
+ */
+#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_1_REG register
+ *  Result text data register 1
+ */
+#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_2_REG register
+ *  Result text data register 2
+ */
+#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_TEXT_OUT_3_REG register
+ *  Result text data register 3
+ */
+#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
+/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
+ *  This bits stores text_out_0 that is a part of result text material.
+ */
+#define AES_TEXT_OUT_0    0xFFFFFFFFU
+#define AES_TEXT_OUT_0_M  (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
+#define AES_TEXT_OUT_0_V  0xFFFFFFFFU
+#define AES_TEXT_OUT_0_S  0
+
+/** AES_MODE_REG register
+ *  Defines key length and encryption / decryption
+ */
+#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
+/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the key length and encryption / decryption of the AES accelerator.
+ *  0: AES-128 encryption
+ *  1: AES-192 encryption
+ *  2: AES-256 encryption
+ *  3: Reserved
+ *  4: AES-128 decryption
+ *  5: AES-192 decryption
+ *  6: AES-256 decryption
+ *  7: Reserved
+ */
+#define AES_MODE    0x00000007U
+#define AES_MODE_M  (AES_MODE_V << AES_MODE_S)
+#define AES_MODE_V  0x00000007U
+#define AES_MODE_S  0
+/** AES_USE_HARDWARE_KEY : R/W; bitpos: [4]; default: 0;
+ *  Configures the AES accelerator use software key or hardware key.
+ *  0: Software key.
+ *  1: Hardware key.
+ */
+#define AES_USE_HARDWARE_KEY    (BIT(4))
+#define AES_USE_HARDWARE_KEY_M  (AES_USE_HARDWARE_KEY_V << AES_USE_HARDWARE_KEY_S)
+#define AES_USE_HARDWARE_KEY_V  0x00000001U
+#define AES_USE_HARDWARE_KEY_S  4
+
+/** AES_TRIGGER_REG register
+ *  Operation start controlling register
+ */
+#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
+/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to start AES operation.
+ *  0: No effect
+ *  1: Start
+ */
+#define AES_TRIGGER    (BIT(0))
+#define AES_TRIGGER_M  (AES_TRIGGER_V << AES_TRIGGER_S)
+#define AES_TRIGGER_V  0x00000001U
+#define AES_TRIGGER_S  0
+
+/** AES_STATE_REG register
+ *  Operation status register
+ */
+#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
+/** AES_STATE : RO; bitpos: [1:0]; default: 0;
+ *  Represents the working status of the AES accelerator.
+ *  In Typical AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: No effect
+ *  3: No effect
+ *  In DMA-AES working mode:
+ *  0: IDLE
+ *  1: WORK
+ *  2: DONE
+ *  3: No effect
+ */
+#define AES_STATE    0x00000003U
+#define AES_STATE_M  (AES_STATE_V << AES_STATE_S)
+#define AES_STATE_V  0x00000003U
+#define AES_STATE_S  0
+
+/** AES_IV_MEM register
+ *  The memory that stores initialization vector
+ */
+#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
+#define AES_IV_MEM_SIZE_BYTES 16
+
+/** AES_H_MEM register
+ *  The memory that stores GCM hash subkey
+ */
+#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
+#define AES_H_MEM_SIZE_BYTES 16
+
+/** AES_J0_MEM register
+ *  The memory that stores J0
+ */
+#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
+#define AES_J0_MEM_SIZE_BYTES 16
+
+/** AES_T0_MEM register
+ *  The memory that stores T0
+ */
+#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
+#define AES_T0_MEM_SIZE_BYTES 16
+
+/** AES_DMA_ENABLE_REG register
+ *  Selects the working mode of the AES accelerator
+ */
+#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
+/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Configures the working mode of the AES accelerator.
+ *  0: Typical AES
+ *  1: DMA-AES
+ */
+#define AES_DMA_ENABLE    (BIT(0))
+#define AES_DMA_ENABLE_M  (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
+#define AES_DMA_ENABLE_V  0x00000001U
+#define AES_DMA_ENABLE_S  0
+
+/** AES_BLOCK_MODE_REG register
+ *  Defines the block cipher mode
+ */
+#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
+/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
+ *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+ *  working mode.
+ *  0: ECB (Electronic Code Block)
+ *  1: CBC (Cipher Block Chaining)
+ *  2: OFB (Output FeedBack)
+ *  3: CTR (Counter)
+ *  4: CFB8 (8-bit Cipher FeedBack)
+ *  5: CFB128 (128-bit Cipher FeedBack)
+ *  6: GCM
+ *  7: Reserved
+ */
+#define AES_BLOCK_MODE    0x00000007U
+#define AES_BLOCK_MODE_M  (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
+#define AES_BLOCK_MODE_V  0x00000007U
+#define AES_BLOCK_MODE_S  0
+
+/** AES_BLOCK_NUM_REG register
+ *  Block number configuration register
+ */
+#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
+/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
+ *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+ *  operates under the DMA-AES working mode. For details, see Section . "
+ */
+#define AES_BLOCK_NUM    0xFFFFFFFFU
+#define AES_BLOCK_NUM_M  (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
+#define AES_BLOCK_NUM_V  0xFFFFFFFFU
+#define AES_BLOCK_NUM_S  0
+
+/** AES_INC_SEL_REG register
+ *  Standard incrementing function register
+ */
+#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
+/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures the Standard Incrementing Function for CTR block operation.
+ *  0: INC_32
+ *  1: INC_128
+ */
+#define AES_INC_SEL    (BIT(0))
+#define AES_INC_SEL_M  (AES_INC_SEL_V << AES_INC_SEL_S)
+#define AES_INC_SEL_V  0x00000001U
+#define AES_INC_SEL_S  0
+
+/** AES_INT_CLEAR_REG register
+ *  DMA-AES interrupt clear register
+ */
+#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
+/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear AES interrupt.
+ *  0: No effect
+ *  1: Clear
+ */
+#define AES_INT_CLEAR    (BIT(0))
+#define AES_INT_CLEAR_M  (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
+#define AES_INT_CLEAR_V  0x00000001U
+#define AES_INT_CLEAR_S  0
+
+/** AES_INT_ENA_REG register
+ *  DMA-AES interrupt enable register
+ */
+#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
+/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable AES interrupt.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AES_INT_ENA    (BIT(0))
+#define AES_INT_ENA_M  (AES_INT_ENA_V << AES_INT_ENA_S)
+#define AES_INT_ENA_V  0x00000001U
+#define AES_INT_ENA_S  0
+
+/** AES_DATE_REG register
+ *  AES version control register
+ */
+#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
+/** AES_DATE : R/W; bitpos: [27:0]; default: 38826624;
+ *  This bits stores the version information of AES.
+ */
+#define AES_DATE    0x0FFFFFFFU
+#define AES_DATE_M  (AES_DATE_V << AES_DATE_S)
+#define AES_DATE_V  0x0FFFFFFFU
+#define AES_DATE_S  0
+
+/** AES_DMA_EXIT_REG register
+ *  Operation exit controlling register
+ */
+#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
+/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to exit AES operation.
+ *  0: No effect
+ *  1: Exit
+ *  Only valid for DMA-AES operation.
+ */
+#define AES_DMA_EXIT    (BIT(0))
+#define AES_DMA_EXIT_M  (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
+#define AES_DMA_EXIT_V  0x00000001U
+#define AES_DMA_EXIT_S  0
+
+/** AES_RX_RESET_REG register
+ *  AES-DMA reset rx-fifo register
+ */
+#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
+/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset rx_fifo under dma_aes working mode.
+ */
+#define AES_RX_RESET    (BIT(0))
+#define AES_RX_RESET_M  (AES_RX_RESET_V << AES_RX_RESET_S)
+#define AES_RX_RESET_V  0x00000001U
+#define AES_RX_RESET_S  0
+
+/** AES_TX_RESET_REG register
+ *  AES-DMA reset tx-fifo register
+ */
+#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
+/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset tx_fifo under dma_aes working mode.
+ */
+#define AES_TX_RESET    (BIT(0))
+#define AES_TX_RESET_M  (AES_TX_RESET_V << AES_TX_RESET_S)
+#define AES_TX_RESET_V  0x00000001U
+#define AES_TX_RESET_S  0
+
+/** AES_PSEUDO_REG register
+ *  AES PSEUDO function configure register
+ */
+#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
+/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
+ *  This bit decides whether the pseudo round function is enable or not.
+ */
+#define AES_PSEUDO_EN    (BIT(0))
+#define AES_PSEUDO_EN_M  (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
+#define AES_PSEUDO_EN_V  0x00000001U
+#define AES_PSEUDO_EN_S  0
+/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
+ *  Those bits decides the basic number of pseudo round number.
+ */
+#define AES_PSEUDO_BASE    0x0000000FU
+#define AES_PSEUDO_BASE_M  (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
+#define AES_PSEUDO_BASE_V  0x0000000FU
+#define AES_PSEUDO_BASE_S  1
+/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
+ *  Those bits decides the increment number of pseudo round number
+ */
+#define AES_PSEUDO_INC    0x00000003U
+#define AES_PSEUDO_INC_M  (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
+#define AES_PSEUDO_INC_V  0x00000003U
+#define AES_PSEUDO_INC_S  5
+/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
+ *  Those bits decides the update frequency of the pseudo-key.
+ */
+#define AES_PSEUDO_RNG_CNT    0x00000007U
+#define AES_PSEUDO_RNG_CNT_M  (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
+#define AES_PSEUDO_RNG_CNT_V  0x00000007U
+#define AES_PSEUDO_RNG_CNT_S  7
+
+/** AES_FREE_REG register
+ *  AES free state register
+ */
+#define AES_FREE_REG (DR_REG_AES_BASE + 0xd4)
+/** AES_FREE : R/W; bitpos: [0]; default: 1;
+ *  0: AES is non-free;
+ *  1:AES is free.
+ */
+#define AES_FREE    (BIT(0))
+#define AES_FREE_M  (AES_FREE_V << AES_FREE_S)
+#define AES_FREE_V  0x00000001U
+#define AES_FREE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/aes_struct.h b/components/soc/esp32s31/register/soc/aes_struct.h
new file mode 100644
index 00000000000..99cf3f3bcdc
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/aes_struct.h
@@ -0,0 +1,376 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Key Registers */
+/** Type of key_n register
+ *  AES key data register n
+ */
+typedef union {
+    struct {
+        /** key_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores key_0 that is a part of key material.
+         */
+        uint32_t key_0:32;
+    };
+    uint32_t val;
+} aes_key_n_reg_t;
+
+
+/** Group: TEXT_IN Registers */
+/** Type of text_in_n register
+ *  Source text data register n
+ */
+typedef union {
+    struct {
+        /** text_in_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_in_0 that is a part of source text material.
+         */
+        uint32_t text_in_0:32;
+    };
+    uint32_t val;
+} aes_text_in_n_reg_t;
+
+
+/** Group: TEXT_OUT Registers */
+/** Type of text_out_n register
+ *  Result text data register n
+ */
+typedef union {
+    struct {
+        /** text_out_0 : R/W; bitpos: [31:0]; default: 0;
+         *  This bits stores text_out_0 that is a part of result text material.
+         */
+        uint32_t text_out_0:32;
+    };
+    uint32_t val;
+} aes_text_out_n_reg_t;
+
+
+/** Group: Control / Configuration Registers */
+/** Type of mode register
+ *  Defines key length and encryption / decryption
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the key length and encryption / decryption of the AES accelerator.
+         *  0: AES-128 encryption
+         *  1: AES-192 encryption
+         *  2: AES-256 encryption
+         *  3: Reserved
+         *  4: AES-128 decryption
+         *  5: AES-192 decryption
+         *  6: AES-256 decryption
+         *  7: Reserved
+         */
+        uint32_t mode:3;
+        uint32_t reserved_3:1;
+        /** use_hardware_key : R/W; bitpos: [4]; default: 0;
+         *  Configures the AES accelerator use software key or hardware key.
+         *  0: Software key.
+         *  1: Hardware key.
+         */
+        uint32_t use_hardware_key:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} aes_mode_reg_t;
+
+/** Type of trigger register
+ *  Operation start controlling register
+ */
+typedef union {
+    struct {
+        /** trigger : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to start AES operation.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trigger:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_trigger_reg_t;
+
+/** Type of dma_enable register
+ *  Selects the working mode of the AES accelerator
+ */
+typedef union {
+    struct {
+        /** dma_enable : R/W; bitpos: [0]; default: 0;
+         *  Configures the working mode of the AES accelerator.
+         *  0: Typical AES
+         *  1: DMA-AES
+         */
+        uint32_t dma_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_enable_reg_t;
+
+/** Type of block_mode register
+ *  Defines the block cipher mode
+ */
+typedef union {
+    struct {
+        /** block_mode : R/W; bitpos: [2:0]; default: 0;
+         *  Configures the block cipher mode of the AES accelerator operating under the DMA-AES
+         *  working mode.
+         *  0: ECB (Electronic Code Block)
+         *  1: CBC (Cipher Block Chaining)
+         *  2: OFB (Output FeedBack)
+         *  3: CTR (Counter)
+         *  4: CFB8 (8-bit Cipher FeedBack)
+         *  5: CFB128 (128-bit Cipher FeedBack)
+         *  6: GCM
+         *  7: Reserved
+         */
+        uint32_t block_mode:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} aes_block_mode_reg_t;
+
+/** Type of block_num register
+ *  Block number configuration register
+ */
+typedef union {
+    struct {
+        /** block_num : R/W; bitpos: [31:0]; default: 0;
+         *  Represents the Block Number of plaintext or ciphertext when the AES accelerator
+         *  operates under the DMA-AES working mode. For details, see Section . "
+         */
+        uint32_t block_num:32;
+    };
+    uint32_t val;
+} aes_block_num_reg_t;
+
+/** Type of inc_sel register
+ *  Standard incrementing function register
+ */
+typedef union {
+    struct {
+        /** inc_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures the Standard Incrementing Function for CTR block operation.
+         *  0: INC_32
+         *  1: INC_128
+         */
+        uint32_t inc_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_inc_sel_reg_t;
+
+/** Type of dma_exit register
+ *  Operation exit controlling register
+ */
+typedef union {
+    struct {
+        /** dma_exit : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to exit AES operation.
+         *  0: No effect
+         *  1: Exit
+         *  Only valid for DMA-AES operation.
+         */
+        uint32_t dma_exit:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_dma_exit_reg_t;
+
+/** Type of rx_reset register
+ *  AES-DMA reset rx-fifo register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset rx_fifo under dma_aes working mode.
+         */
+        uint32_t rx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_rx_reset_reg_t;
+
+/** Type of tx_reset register
+ *  AES-DMA reset tx-fifo register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset tx_fifo under dma_aes working mode.
+         */
+        uint32_t tx_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_tx_reset_reg_t;
+
+
+/** Group: Configuration register */
+/** Type of pseudo register
+ *  AES PSEUDO function configure register
+ */
+typedef union {
+    struct {
+        /** pseudo_en : R/W; bitpos: [0]; default: 0;
+         *  This bit decides whether the pseudo round function is enable or not.
+         */
+        uint32_t pseudo_en:1;
+        /** pseudo_base : R/W; bitpos: [4:1]; default: 2;
+         *  Those bits decides the basic number of pseudo round number.
+         */
+        uint32_t pseudo_base:4;
+        /** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
+         *  Those bits decides the increment number of pseudo round number
+         */
+        uint32_t pseudo_inc:2;
+        /** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
+         *  Those bits decides the update frequency of the pseudo-key.
+         */
+        uint32_t pseudo_rng_cnt:3;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} aes_pseudo_reg_t;
+
+
+/** Group: Status Register */
+/** Type of state register
+ *  Operation status register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  Represents the working status of the AES accelerator.
+         *  In Typical AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: No effect
+         *  3: No effect
+         *  In DMA-AES working mode:
+         *  0: IDLE
+         *  1: WORK
+         *  2: DONE
+         *  3: No effect
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} aes_state_reg_t;
+
+/** Type of free register
+ *  AES free state register
+ */
+typedef union {
+    struct {
+        /** free : R/W; bitpos: [0]; default: 1;
+         *  0: AES is non-free;
+         *  1:AES is free.
+         */
+        uint32_t free:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_free_reg_t;
+
+
+/** Group: memory type */
+
+/** Group: Interrupt Registers */
+/** Type of int_clear register
+ *  DMA-AES interrupt clear register
+ */
+typedef union {
+    struct {
+        /** int_clear : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear AES interrupt.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t int_clear:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_clear_reg_t;
+
+/** Type of int_ena register
+ *  DMA-AES interrupt enable register
+ */
+typedef union {
+    struct {
+        /** int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable AES interrupt.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} aes_int_ena_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  AES version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38826624;
+         *  This bits stores the version information of AES.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} aes_date_reg_t;
+
+
+typedef struct {
+    volatile aes_key_n_reg_t key_n[8];
+    volatile aes_text_in_n_reg_t text_in_n[4];
+    volatile aes_text_out_n_reg_t text_out_n[4];
+    volatile aes_mode_reg_t mode;
+    uint32_t reserved_044;
+    volatile aes_trigger_reg_t trigger;
+    volatile aes_state_reg_t state;
+    volatile uint32_t iv[4];
+    volatile uint32_t h[4];
+    volatile uint32_t j0[4];
+    volatile uint32_t t0[4];
+    volatile aes_dma_enable_reg_t dma_enable;
+    volatile aes_block_mode_reg_t block_mode;
+    volatile aes_block_num_reg_t block_num;
+    volatile aes_inc_sel_reg_t inc_sel;
+    uint32_t reserved_0a0[3];
+    volatile aes_int_clear_reg_t int_clear;
+    volatile aes_int_ena_reg_t int_ena;
+    volatile aes_date_reg_t date;
+    volatile aes_dma_exit_reg_t dma_exit;
+    uint32_t reserved_0bc;
+    volatile aes_rx_reset_reg_t rx_reset;
+    volatile aes_tx_reset_reg_t tx_reset;
+    uint32_t reserved_0c8[2];
+    volatile aes_pseudo_reg_t pseudo;
+    volatile aes_free_reg_t free;
+} aes_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(aes_dev_t) == 0xd8, "Invalid size of aes_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ahb_dma_reg.h b/components/soc/esp32s31/register/soc/ahb_dma_reg.h
new file mode 100644
index 00000000000..90953cac933
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ahb_dma_reg.h
@@ -0,0 +1,6419 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AHB_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x0)
+/** AHB_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH0_INT.
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_M  (AHB_DMA_IN_DONE_CH0_INT_RAW_V << AHB_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x4)
+/** AHB_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH0_INT.
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ST_M  (AHB_DMA_IN_DONE_CH0_INT_ST_V << AHB_DMA_IN_DONE_CH0_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ST_V << AHB_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ST_V << AHB_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x8)
+/** AHB_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH0_INT.
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_M  (AHB_DMA_IN_DONE_CH0_INT_ENA_V << AHB_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define AHB_DMA_IN_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0xc)
+/** AHB_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH0_INT.
+ */
+#define AHB_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_M  (AHB_DMA_IN_DONE_CH0_INT_CLR_V << AHB_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH0_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH0_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH0_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH0_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH0_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x10)
+/** AHB_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH1_INT.
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_M  (AHB_DMA_IN_DONE_CH1_INT_RAW_V << AHB_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x14)
+/** AHB_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH1_INT.
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ST_M  (AHB_DMA_IN_DONE_CH1_INT_ST_V << AHB_DMA_IN_DONE_CH1_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ST_V << AHB_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ST_V << AHB_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x18)
+/** AHB_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH1_INT.
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_M  (AHB_DMA_IN_DONE_CH1_INT_ENA_V << AHB_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define AHB_DMA_IN_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x1c)
+/** AHB_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH1_INT.
+ */
+#define AHB_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_M  (AHB_DMA_IN_DONE_CH1_INT_CLR_V << AHB_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH1_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH1_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH1_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH1_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH1_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x20)
+/** AHB_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH2_INT.
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_M  (AHB_DMA_IN_DONE_CH2_INT_RAW_V << AHB_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x24)
+/** AHB_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH2_INT.
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ST_M  (AHB_DMA_IN_DONE_CH2_INT_ST_V << AHB_DMA_IN_DONE_CH2_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ST_V << AHB_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ST_V << AHB_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x28)
+/** AHB_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH2_INT.
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_M  (AHB_DMA_IN_DONE_CH2_INT_ENA_V << AHB_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define AHB_DMA_IN_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x2c)
+/** AHB_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH2_INT.
+ */
+#define AHB_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_M  (AHB_DMA_IN_DONE_CH2_INT_CLR_V << AHB_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH2_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH2_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH2_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH2_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH2_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH3_REG register
+ *  Raw interrupt status of RX channel 3
+ */
+#define AHB_DMA_IN_INT_RAW_CH3_REG (DR_REG_AHB_DMA_BASE + 0x30)
+/** AHB_DMA_IN_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH3_INT.
+ */
+#define AHB_DMA_IN_DONE_CH3_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH3_INT_RAW_M  (AHB_DMA_IN_DONE_CH3_INT_RAW_V << AHB_DMA_IN_DONE_CH3_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH3_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH3_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH3_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH3_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH3_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH3_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH3_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH3_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH3_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH3_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH3_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH3_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH3_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH3_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH3_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH3_REG register
+ *  Masked interrupt status of RX channel 3
+ */
+#define AHB_DMA_IN_INT_ST_CH3_REG (DR_REG_AHB_DMA_BASE + 0x34)
+/** AHB_DMA_IN_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH3_INT.
+ */
+#define AHB_DMA_IN_DONE_CH3_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH3_INT_ST_M  (AHB_DMA_IN_DONE_CH3_INT_ST_V << AHB_DMA_IN_DONE_CH3_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH3_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH3_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH3_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH3_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH3_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH3_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH3_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH3_INT_ST_V << AHB_DMA_INFIFO_OVF_CH3_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH3_INT_ST_V << AHB_DMA_INFIFO_UDF_CH3_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH3_REG register
+ *  Interrupt enable bits of RX channel 3
+ */
+#define AHB_DMA_IN_INT_ENA_CH3_REG (DR_REG_AHB_DMA_BASE + 0x38)
+/** AHB_DMA_IN_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH3_INT.
+ */
+#define AHB_DMA_IN_DONE_CH3_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH3_INT_ENA_M  (AHB_DMA_IN_DONE_CH3_INT_ENA_V << AHB_DMA_IN_DONE_CH3_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH3_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH3_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH3_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH3_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH3_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH3_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH3_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH3_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH3_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH3_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH3_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH3_REG register
+ *  Interrupt clear bits of RX channel 3
+ */
+#define AHB_DMA_IN_INT_CLR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x3c)
+/** AHB_DMA_IN_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH3_INT.
+ */
+#define AHB_DMA_IN_DONE_CH3_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH3_INT_CLR_M  (AHB_DMA_IN_DONE_CH3_INT_CLR_V << AHB_DMA_IN_DONE_CH3_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH3_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH3_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH3_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH3_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH3_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH3_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH3_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH3_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH3_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH3_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH3_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH3_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH3_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH3_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH3_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH3_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH3_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH3_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH3_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH3_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH3_INT_CLR_S  7
+
+/** AHB_DMA_IN_INT_RAW_CH4_REG register
+ *  Raw interrupt status of RX channel 4
+ */
+#define AHB_DMA_IN_INT_RAW_CH4_REG (DR_REG_AHB_DMA_BASE + 0x40)
+/** AHB_DMA_IN_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DONE_CH4_INT.
+ */
+#define AHB_DMA_IN_DONE_CH4_INT_RAW    (BIT(0))
+#define AHB_DMA_IN_DONE_CH4_INT_RAW_M  (AHB_DMA_IN_DONE_CH4_INT_RAW_V << AHB_DMA_IN_DONE_CH4_INT_RAW_S)
+#define AHB_DMA_IN_DONE_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH4_INT_RAW_S  0
+/** AHB_DMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_RAW    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_RAW_M  (AHB_DMA_IN_SUC_EOF_CH4_INT_RAW_V << AHB_DMA_IN_SUC_EOF_CH4_INT_RAW_S)
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_RAW_S  1
+/** AHB_DMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_RAW    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_RAW_M  (AHB_DMA_IN_ERR_EOF_CH4_INT_RAW_V << AHB_DMA_IN_ERR_EOF_CH4_INT_RAW_S)
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_RAW_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW_M  (AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW_V << AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_RAW_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_M  (AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V << AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S  4
+/** AHB_DMA_INFIFO_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH4_INT_RAW    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH4_INT_RAW_M  (AHB_DMA_INFIFO_OVF_CH4_INT_RAW_V << AHB_DMA_INFIFO_OVF_CH4_INT_RAW_S)
+#define AHB_DMA_INFIFO_OVF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH4_INT_RAW_S  5
+/** AHB_DMA_INFIFO_UDF_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH4_INT_RAW    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH4_INT_RAW_M  (AHB_DMA_INFIFO_UDF_CH4_INT_RAW_V << AHB_DMA_INFIFO_UDF_CH4_INT_RAW_S)
+#define AHB_DMA_INFIFO_UDF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH4_INT_RAW_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_RAW_S  7
+
+/** AHB_DMA_IN_INT_ST_CH4_REG register
+ *  Masked interrupt status of RX channel 4
+ */
+#define AHB_DMA_IN_INT_ST_CH4_REG (DR_REG_AHB_DMA_BASE + 0x44)
+/** AHB_DMA_IN_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DONE_CH4_INT.
+ */
+#define AHB_DMA_IN_DONE_CH4_INT_ST    (BIT(0))
+#define AHB_DMA_IN_DONE_CH4_INT_ST_M  (AHB_DMA_IN_DONE_CH4_INT_ST_V << AHB_DMA_IN_DONE_CH4_INT_ST_S)
+#define AHB_DMA_IN_DONE_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH4_INT_ST_S  0
+/** AHB_DMA_IN_SUC_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ST    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ST_M  (AHB_DMA_IN_SUC_EOF_CH4_INT_ST_V << AHB_DMA_IN_SUC_EOF_CH4_INT_ST_S)
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ST_S  1
+/** AHB_DMA_IN_ERR_EOF_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ST    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ST_M  (AHB_DMA_IN_ERR_EOF_CH4_INT_ST_V << AHB_DMA_IN_ERR_EOF_CH4_INT_ST_S)
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ST_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ST    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ST_M  (AHB_DMA_IN_DSCR_ERR_CH4_INT_ST_V << AHB_DMA_IN_DSCR_ERR_CH4_INT_ST_S)
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ST_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST_M  (AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V << AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ST_S  4
+/** AHB_DMA_INFIFO_OVF_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ST    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ST_M  (AHB_DMA_INFIFO_OVF_CH4_INT_ST_V << AHB_DMA_INFIFO_OVF_CH4_INT_ST_S)
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ST_S  5
+/** AHB_DMA_INFIFO_UDF_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ST    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ST_M  (AHB_DMA_INFIFO_UDF_CH4_INT_ST_V << AHB_DMA_INFIFO_UDF_CH4_INT_ST_S)
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ST_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ST_S  7
+
+/** AHB_DMA_IN_INT_ENA_CH4_REG register
+ *  Interrupt enable bits of RX channel 4
+ */
+#define AHB_DMA_IN_INT_ENA_CH4_REG (DR_REG_AHB_DMA_BASE + 0x48)
+/** AHB_DMA_IN_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DONE_CH4_INT.
+ */
+#define AHB_DMA_IN_DONE_CH4_INT_ENA    (BIT(0))
+#define AHB_DMA_IN_DONE_CH4_INT_ENA_M  (AHB_DMA_IN_DONE_CH4_INT_ENA_V << AHB_DMA_IN_DONE_CH4_INT_ENA_S)
+#define AHB_DMA_IN_DONE_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH4_INT_ENA_S  0
+/** AHB_DMA_IN_SUC_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ENA    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ENA_M  (AHB_DMA_IN_SUC_EOF_CH4_INT_ENA_V << AHB_DMA_IN_SUC_EOF_CH4_INT_ENA_S)
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_ENA_S  1
+/** AHB_DMA_IN_ERR_EOF_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ENA    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ENA_M  (AHB_DMA_IN_ERR_EOF_CH4_INT_ENA_V << AHB_DMA_IN_ERR_EOF_CH4_INT_ENA_S)
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_ENA_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA_M  (AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA_V << AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_ENA_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_M  (AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V << AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S  4
+/** AHB_DMA_INFIFO_OVF_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ENA    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ENA_M  (AHB_DMA_INFIFO_OVF_CH4_INT_ENA_V << AHB_DMA_INFIFO_OVF_CH4_INT_ENA_S)
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH4_INT_ENA_S  5
+/** AHB_DMA_INFIFO_UDF_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_INFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ENA    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ENA_M  (AHB_DMA_INFIFO_UDF_CH4_INT_ENA_V << AHB_DMA_INFIFO_UDF_CH4_INT_ENA_S)
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH4_INT_ENA_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_ENA_S  7
+
+/** AHB_DMA_IN_INT_CLR_CH4_REG register
+ *  Interrupt clear bits of RX channel 4
+ */
+#define AHB_DMA_IN_INT_CLR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x4c)
+/** AHB_DMA_IN_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DONE_CH4_INT.
+ */
+#define AHB_DMA_IN_DONE_CH4_INT_CLR    (BIT(0))
+#define AHB_DMA_IN_DONE_CH4_INT_CLR_M  (AHB_DMA_IN_DONE_CH4_INT_CLR_V << AHB_DMA_IN_DONE_CH4_INT_CLR_S)
+#define AHB_DMA_IN_DONE_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DONE_CH4_INT_CLR_S  0
+/** AHB_DMA_IN_SUC_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_CLR    (BIT(1))
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_CLR_M  (AHB_DMA_IN_SUC_EOF_CH4_INT_CLR_V << AHB_DMA_IN_SUC_EOF_CH4_INT_CLR_S)
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_SUC_EOF_CH4_INT_CLR_S  1
+/** AHB_DMA_IN_ERR_EOF_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CH4_INT.
+ */
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_CLR    (BIT(2))
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_CLR_M  (AHB_DMA_IN_ERR_EOF_CH4_INT_CLR_V << AHB_DMA_IN_ERR_EOF_CH4_INT_CLR_S)
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_ERR_EOF_CH4_INT_CLR_S  2
+/** AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR    (BIT(3))
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR_M  (AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR_V << AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_ERR_CH4_INT_CLR_S  3
+/** AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CH4_INT.
+ */
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR    (BIT(4))
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_M  (AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V << AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S)
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S  4
+/** AHB_DMA_INFIFO_OVF_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_OVF_CH4_INT_CLR    (BIT(5))
+#define AHB_DMA_INFIFO_OVF_CH4_INT_CLR_M  (AHB_DMA_INFIFO_OVF_CH4_INT_CLR_V << AHB_DMA_INFIFO_OVF_CH4_INT_CLR_S)
+#define AHB_DMA_INFIFO_OVF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_OVF_CH4_INT_CLR_S  5
+/** AHB_DMA_INFIFO_UDF_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_INFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_INFIFO_UDF_CH4_INT_CLR    (BIT(6))
+#define AHB_DMA_INFIFO_UDF_CH4_INT_CLR_M  (AHB_DMA_INFIFO_UDF_CH4_INT_CLR_V << AHB_DMA_INFIFO_UDF_CH4_INT_CLR_S)
+#define AHB_DMA_INFIFO_UDF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_INFIFO_UDF_CH4_INT_CLR_S  6
+/** AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR    (BIT(7))
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR_M  (AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR_V << AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR_S)
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_IN_AHBINF_RESP_ERR_CH4_INT_CLR_S  7
+
+/** AHB_DMA_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AHB_DMA_BASE + 0x50)
+/** AHB_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH0_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_M  (AHB_DMA_OUT_DONE_CH0_INT_RAW_V << AHB_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ST_CH0_REG (DR_REG_AHB_DMA_BASE + 0x54)
+/** AHB_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH0_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_M  (AHB_DMA_OUT_DONE_CH0_INT_ST_V << AHB_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_EOF_CH0_INT_ST_V << AHB_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AHB_DMA_BASE + 0x58)
+/** AHB_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH0_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_M  (AHB_DMA_OUT_DONE_CH0_INT_ENA_V << AHB_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define AHB_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x5c)
+/** AHB_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH0_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_M  (AHB_DMA_OUT_DONE_CH0_INT_CLR_V << AHB_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH0_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH0_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH0_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH0_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH0_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH0_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AHB_DMA_BASE + 0x60)
+/** AHB_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH1_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_M  (AHB_DMA_OUT_DONE_CH1_INT_RAW_V << AHB_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ST_CH1_REG (DR_REG_AHB_DMA_BASE + 0x64)
+/** AHB_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH1_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_M  (AHB_DMA_OUT_DONE_CH1_INT_ST_V << AHB_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_EOF_CH1_INT_ST_V << AHB_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AHB_DMA_BASE + 0x68)
+/** AHB_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH1_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_M  (AHB_DMA_OUT_DONE_CH1_INT_ENA_V << AHB_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define AHB_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x6c)
+/** AHB_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH1_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_M  (AHB_DMA_OUT_DONE_CH1_INT_CLR_V << AHB_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH1_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH1_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH1_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH1_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH1_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH1_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AHB_DMA_BASE + 0x70)
+/** AHB_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH2_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_M  (AHB_DMA_OUT_DONE_CH2_INT_RAW_V << AHB_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ST_CH2_REG (DR_REG_AHB_DMA_BASE + 0x74)
+/** AHB_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH2_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_M  (AHB_DMA_OUT_DONE_CH2_INT_ST_V << AHB_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_EOF_CH2_INT_ST_V << AHB_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AHB_DMA_BASE + 0x78)
+/** AHB_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH2_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_M  (AHB_DMA_OUT_DONE_CH2_INT_ENA_V << AHB_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define AHB_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x7c)
+/** AHB_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH2_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_M  (AHB_DMA_OUT_DONE_CH2_INT_CLR_V << AHB_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH2_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH2_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH2_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH2_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH2_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH2_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH3_REG register
+ *  Raw interrupt status of TX channel 3
+ */
+#define AHB_DMA_OUT_INT_RAW_CH3_REG (DR_REG_AHB_DMA_BASE + 0x80)
+/** AHB_DMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH3_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH3_INT_RAW_M  (AHB_DMA_OUT_DONE_CH3_INT_RAW_V << AHB_DMA_OUT_DONE_CH3_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH3_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH3_INT_RAW_M  (AHB_DMA_OUT_EOF_CH3_INT_RAW_V << AHB_DMA_OUT_EOF_CH3_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH3_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH3_REG register
+ *  Masked interrupt status of TX channel 3
+ */
+#define AHB_DMA_OUT_INT_ST_CH3_REG (DR_REG_AHB_DMA_BASE + 0x84)
+/** AHB_DMA_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH3_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH3_INT_ST_M  (AHB_DMA_OUT_DONE_CH3_INT_ST_V << AHB_DMA_OUT_DONE_CH3_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH3_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH3_INT_ST_M  (AHB_DMA_OUT_EOF_CH3_INT_ST_V << AHB_DMA_OUT_EOF_CH3_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH3_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH3_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH3_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH3_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH3_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH3_REG register
+ *  Interrupt enable bits of TX channel 3
+ */
+#define AHB_DMA_OUT_INT_ENA_CH3_REG (DR_REG_AHB_DMA_BASE + 0x88)
+/** AHB_DMA_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH3_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH3_INT_ENA_M  (AHB_DMA_OUT_DONE_CH3_INT_ENA_V << AHB_DMA_OUT_DONE_CH3_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH3_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH3_INT_ENA_M  (AHB_DMA_OUT_EOF_CH3_INT_ENA_V << AHB_DMA_OUT_EOF_CH3_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH3_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH3_REG register
+ *  Interrupt clear bits of TX channel 3
+ */
+#define AHB_DMA_OUT_INT_CLR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x8c)
+/** AHB_DMA_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH3_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH3_INT_CLR_M  (AHB_DMA_OUT_DONE_CH3_INT_CLR_V << AHB_DMA_OUT_DONE_CH3_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH3_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH3_INT_CLR_M  (AHB_DMA_OUT_EOF_CH3_INT_CLR_V << AHB_DMA_OUT_EOF_CH3_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH3_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH3_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH3_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH3_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH3_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH3_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH3_INT_CLR_S  6
+
+/** AHB_DMA_OUT_INT_RAW_CH4_REG register
+ *  Raw interrupt status of TX channel 4
+ */
+#define AHB_DMA_OUT_INT_RAW_CH4_REG (DR_REG_AHB_DMA_BASE + 0x90)
+/** AHB_DMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DONE_CH4_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH4_INT_RAW    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH4_INT_RAW_M  (AHB_DMA_OUT_DONE_CH4_INT_RAW_V << AHB_DMA_OUT_DONE_CH4_INT_RAW_S)
+#define AHB_DMA_OUT_DONE_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH4_INT_RAW_S  0
+/** AHB_DMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH4_INT_RAW    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH4_INT_RAW_M  (AHB_DMA_OUT_EOF_CH4_INT_RAW_V << AHB_DMA_OUT_EOF_CH4_INT_RAW_S)
+#define AHB_DMA_OUT_EOF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH4_INT_RAW_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW_M  (AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V << AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_RAW_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_M  (AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V << AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW_M  (AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW_V << AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_RAW_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW_M  (AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW_V << AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW_S)
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_RAW_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_RAW_S  6
+
+/** AHB_DMA_OUT_INT_ST_CH4_REG register
+ *  Masked interrupt status of TX channel 4
+ */
+#define AHB_DMA_OUT_INT_ST_CH4_REG (DR_REG_AHB_DMA_BASE + 0x94)
+/** AHB_DMA_OUT_DONE_CH4_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DONE_CH4_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH4_INT_ST    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH4_INT_ST_M  (AHB_DMA_OUT_DONE_CH4_INT_ST_V << AHB_DMA_OUT_DONE_CH4_INT_ST_S)
+#define AHB_DMA_OUT_DONE_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH4_INT_ST_S  0
+/** AHB_DMA_OUT_EOF_CH4_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH4_INT_ST    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH4_INT_ST_M  (AHB_DMA_OUT_EOF_CH4_INT_ST_V << AHB_DMA_OUT_EOF_CH4_INT_ST_S)
+#define AHB_DMA_OUT_EOF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH4_INT_ST_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST_M  (AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST_V << AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ST_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST_M  (AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V << AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ST_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH4_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ST    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ST_M  (AHB_DMA_OUTFIFO_OVF_CH4_INT_ST_V << AHB_DMA_OUTFIFO_OVF_CH4_INT_ST_S)
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ST_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH4_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ST    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ST_M  (AHB_DMA_OUTFIFO_UDF_CH4_INT_ST_V << AHB_DMA_OUTFIFO_UDF_CH4_INT_ST_S)
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ST_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ST_S  6
+
+/** AHB_DMA_OUT_INT_ENA_CH4_REG register
+ *  Interrupt enable bits of TX channel 4
+ */
+#define AHB_DMA_OUT_INT_ENA_CH4_REG (DR_REG_AHB_DMA_BASE + 0x98)
+/** AHB_DMA_OUT_DONE_CH4_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DONE_CH4_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH4_INT_ENA    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH4_INT_ENA_M  (AHB_DMA_OUT_DONE_CH4_INT_ENA_V << AHB_DMA_OUT_DONE_CH4_INT_ENA_S)
+#define AHB_DMA_OUT_DONE_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH4_INT_ENA_S  0
+/** AHB_DMA_OUT_EOF_CH4_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH4_INT_ENA    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH4_INT_ENA_M  (AHB_DMA_OUT_EOF_CH4_INT_ENA_V << AHB_DMA_OUT_EOF_CH4_INT_ENA_S)
+#define AHB_DMA_OUT_EOF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH4_INT_ENA_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA_M  (AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V << AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_ENA_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_M  (AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V << AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA_M  (AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA_V << AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_ENA_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA_M  (AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA_V << AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA_S)
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_ENA_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_ENA_S  6
+
+/** AHB_DMA_OUT_INT_CLR_CH4_REG register
+ *  Interrupt clear bits of TX channel 4
+ */
+#define AHB_DMA_OUT_INT_CLR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x9c)
+/** AHB_DMA_OUT_DONE_CH4_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DONE_CH4_INT.
+ */
+#define AHB_DMA_OUT_DONE_CH4_INT_CLR    (BIT(0))
+#define AHB_DMA_OUT_DONE_CH4_INT_CLR_M  (AHB_DMA_OUT_DONE_CH4_INT_CLR_V << AHB_DMA_OUT_DONE_CH4_INT_CLR_S)
+#define AHB_DMA_OUT_DONE_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DONE_CH4_INT_CLR_S  0
+/** AHB_DMA_OUT_EOF_CH4_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_EOF_CH4_INT_CLR    (BIT(1))
+#define AHB_DMA_OUT_EOF_CH4_INT_CLR_M  (AHB_DMA_OUT_EOF_CH4_INT_CLR_V << AHB_DMA_OUT_EOF_CH4_INT_CLR_S)
+#define AHB_DMA_OUT_EOF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_EOF_CH4_INT_CLR_S  1
+/** AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR    (BIT(2))
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR_M  (AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V << AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S)
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_DSCR_ERR_CH4_INT_CLR_S  2
+/** AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CH4_INT.
+ */
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR    (BIT(3))
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_M  (AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V << AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S)
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S  3
+/** AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR    (BIT(4))
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR_M  (AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR_V << AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_OVF_CH4_INT_CLR_S  4
+/** AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CH4_INT.
+ */
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR    (BIT(5))
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR_M  (AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR_V << AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR_S)
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUTFIFO_UDF_CH4_INT_CLR_S  5
+/** AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CH4_INT.
+ */
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR    (BIT(6))
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR_M  (AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR_V << AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR_S)
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR_V  0x00000001U
+#define AHB_DMA_OUT_AHBINF_RESP_ERR_CH4_INT_CLR_S  6
+
+/** AHB_DMA_AHB_TEST_REG register
+ *  reserved
+ */
+#define AHB_DMA_AHB_TEST_REG (DR_REG_AHB_DMA_BASE + 0xa0)
+/** AHB_DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTMODE    0x00000007U
+#define AHB_DMA_AHB_TESTMODE_M  (AHB_DMA_AHB_TESTMODE_V << AHB_DMA_AHB_TESTMODE_S)
+#define AHB_DMA_AHB_TESTMODE_V  0x00000007U
+#define AHB_DMA_AHB_TESTMODE_S  0
+/** AHB_DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_AHB_TESTADDR    0x00000003U
+#define AHB_DMA_AHB_TESTADDR_M  (AHB_DMA_AHB_TESTADDR_V << AHB_DMA_AHB_TESTADDR_S)
+#define AHB_DMA_AHB_TESTADDR_V  0x00000003U
+#define AHB_DMA_AHB_TESTADDR_S  4
+
+/** AHB_DMA_MISC_CONF_REG register
+ *  Miscellaneous register
+ */
+#define AHB_DMA_MISC_CONF_REG (DR_REG_AHB_DMA_BASE + 0xa4)
+/** AHB_DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset the internal AHB FSM.
+ */
+#define AHB_DMA_AHBM_RST_INTER    (BIT(0))
+#define AHB_DMA_AHBM_RST_INTER_M  (AHB_DMA_AHBM_RST_INTER_V << AHB_DMA_AHBM_RST_INTER_S)
+#define AHB_DMA_AHBM_RST_INTER_V  0x00000001U
+#define AHB_DMA_AHBM_RST_INTER_S  0
+/** AHB_DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to disable the fixed-priority channel arbitration.
+ *  0: Enable
+ *  1: Disable
+ */
+#define AHB_DMA_ARB_PRI_DIS    (BIT(2))
+#define AHB_DMA_ARB_PRI_DIS_M  (AHB_DMA_ARB_PRI_DIS_V << AHB_DMA_ARB_PRI_DIS_S)
+#define AHB_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AHB_DMA_ARB_PRI_DIS_S  2
+/** AHB_DMA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures clock gating.
+ *  0: Support clock only when the application writes registers.
+ *  1: Always force the clock on for registers.
+ */
+#define AHB_DMA_CLK_EN    (BIT(3))
+#define AHB_DMA_CLK_EN_M  (AHB_DMA_CLK_EN_V << AHB_DMA_CLK_EN_S)
+#define AHB_DMA_CLK_EN_V  0x00000001U
+#define AHB_DMA_CLK_EN_S  3
+
+/** AHB_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AHB_DMA_DATE_REG (DR_REG_AHB_DMA_BASE + 0xa8)
+/** AHB_DMA_DATE : R/W; bitpos: [31:0]; default: 37778192;
+ *  Version control register.
+ */
+#define AHB_DMA_DATE    0xFFFFFFFFU
+#define AHB_DMA_DATE_M  (AHB_DMA_DATE_V << AHB_DMA_DATE_S)
+#define AHB_DMA_DATE_V  0xFFFFFFFFU
+#define AHB_DMA_DATE_S  0
+
+/** AHB_DMA_IN_CONF0_CH0_REG register
+ *  Configuration register 0 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x100)
+/** AHB_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH0    (BIT(0))
+#define AHB_DMA_IN_RST_CH0_M  (AHB_DMA_IN_RST_CH0_V << AHB_DMA_IN_RST_CH0_S)
+#define AHB_DMA_IN_RST_CH0_V  0x00000001U
+#define AHB_DMA_IN_RST_CH0_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH0_M  (AHB_DMA_IN_LOOP_TEST_CH0_V << AHB_DMA_IN_LOOP_TEST_CH0_S)
+#define AHB_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH0_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 0 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH0    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH0_M  (AHB_DMA_INDSCR_BURST_EN_CH0_V << AHB_DMA_INDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH0_S  2
+/** AHB_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH0    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH0_M  (AHB_DMA_MEM_TRANS_EN_CH0_V << AHB_DMA_MEM_TRANS_EN_CH0_S)
+#define AHB_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH0_S  4
+/** AHB_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH0    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH0_M  (AHB_DMA_IN_ETM_EN_CH0_V << AHB_DMA_IN_ETM_EN_CH0_S)
+#define AHB_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH0_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [7:6]; default: 0;
+ *  Configures max burst size for Rx channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH0_S  6
+
+/** AHB_DMA_IN_CONF1_CH0_REG register
+ *  Configuration register 1 of RX channel 0
+ */
+#define AHB_DMA_IN_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x104)
+/** AHB_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH0_M  (AHB_DMA_IN_CHECK_OWNER_CH0_V << AHB_DMA_IN_CHECK_OWNER_CH0_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of RX channel 0
+ */
+#define AHB_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x108)
+/** AHB_DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH0_M  (AHB_DMA_INFIFO_FULL_CH0_V << AHB_DMA_INFIFO_FULL_CH0_S)
+#define AHB_DMA_INFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH0_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH0_M  (AHB_DMA_INFIFO_EMPTY_CH0_V << AHB_DMA_INFIFO_EMPTY_CH0_S)
+#define AHB_DMA_INFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_INFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 0.
+ */
+#define AHB_DMA_INFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_M  (AHB_DMA_INFIFO_CNT_CH0_V << AHB_DMA_INFIFO_CNT_CH0_S)
+#define AHB_DMA_INFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH0_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH0    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_M  (AHB_DMA_IN_BUF_HUNGRY_CH0_V << AHB_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH0_S  27
+
+/** AHB_DMA_IN_POP_CH0_REG register
+ *  Pop control register of RX channel 0
+ */
+#define AHB_DMA_IN_POP_CH0_REG (DR_REG_AHB_DMA_BASE + 0x10c)
+/** AHB_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_M  (AHB_DMA_INFIFO_RDATA_CH0_V << AHB_DMA_INFIFO_RDATA_CH0_S)
+#define AHB_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH0_S  0
+/** AHB_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH0_M  (AHB_DMA_INFIFO_POP_CH0_V << AHB_DMA_INFIFO_POP_CH0_S)
+#define AHB_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH0_S  12
+
+/** AHB_DMA_IN_LINK_CH0_REG register
+ *  Linked list descriptor configuration and control register of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x110)
+/** AHB_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH0_M  (AHB_DMA_INLINK_AUTO_RET_CH0_V << AHB_DMA_INLINK_AUTO_RET_CH0_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AHB_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 0 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH0_M  (AHB_DMA_INLINK_STOP_CH0_V << AHB_DMA_INLINK_STOP_CH0_S)
+#define AHB_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH0_S  1
+/** AHB_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH0    (BIT(2))
+#define AHB_DMA_INLINK_START_CH0_M  (AHB_DMA_INLINK_START_CH0_V << AHB_DMA_INLINK_START_CH0_S)
+#define AHB_DMA_INLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH0_S  2
+/** AHB_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH0_M  (AHB_DMA_INLINK_RESTART_CH0_V << AHB_DMA_INLINK_RESTART_CH0_S)
+#define AHB_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH0_S  3
+/** AHB_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH0_M  (AHB_DMA_INLINK_PARK_CH0_V << AHB_DMA_INLINK_PARK_CH0_S)
+#define AHB_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH0_S  4
+
+/** AHB_DMA_IN_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of RX channel 0
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x114)
+/** AHB_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_M  (AHB_DMA_INLINK_ADDR_CH0_V << AHB_DMA_INLINK_ADDR_CH0_S)
+#define AHB_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_STATE_CH0_REG register
+ *  Receive status of RX channel 0
+ */
+#define AHB_DMA_IN_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x118)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_M  (AHB_DMA_INLINK_DSCR_ADDR_CH0_V << AHB_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_M  (AHB_DMA_IN_DSCR_STATE_CH0_V << AHB_DMA_IN_DSCR_STATE_CH0_S)
+#define AHB_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH0_S  18
+/** AHB_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_STATE_CH0    0x00000007U
+#define AHB_DMA_IN_STATE_CH0_M  (AHB_DMA_IN_STATE_CH0_V << AHB_DMA_IN_STATE_CH0_S)
+#define AHB_DMA_IN_STATE_CH0_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH0_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 0
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x11c)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Receive descriptor address when errors occur of RX channel 0
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x120)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0_REG register
+ *  RX_done inlink descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x124)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_M  (AHB_DMA_IN_DONE_DES_ADDR_CH0_V << AHB_DMA_IN_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_CH0_REG register
+ *  Current receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x128)
+/** AHB_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_M  (AHB_DMA_INLINK_DSCR_CH0_V << AHB_DMA_INLINK_DSCR_CH0_S)
+#define AHB_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x12c)
+/** AHB_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_M  (AHB_DMA_INLINK_DSCR_BF0_CH0_V << AHB_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last receive descriptor address of RX channel 0
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x130)
+/** AHB_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_M  (AHB_DMA_INLINK_DSCR_BF1_CH0_V << AHB_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_IN_PRI_CH0_REG register
+ *  Priority register of RX channel 0
+ */
+#define AHB_DMA_IN_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x134)
+/** AHB_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 0.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_RX_PRI_CH0    0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_M  (AHB_DMA_RX_PRI_CH0_V << AHB_DMA_RX_PRI_CH0_S)
+#define AHB_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH0_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of RX channel 0
+ */
+#define AHB_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x138)
+/** AHB_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 0.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_M  (AHB_DMA_PERI_IN_SEL_CH0_V << AHB_DMA_PERI_IN_SEL_CH0_S)
+#define AHB_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG register
+ *  RX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x13c)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel0
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH0_V << AHB_DMA_RX_CH_ARB_WEIGH_CH0_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH0_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG register
+ *  RX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x140)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S  0
+
+/** AHB_DMA_OUT_CONF0_CH0_REG register
+ *  Configuration register 0 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x180)
+/** AHB_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH0    (BIT(0))
+#define AHB_DMA_OUT_RST_CH0_M  (AHB_DMA_OUT_RST_CH0_V << AHB_DMA_OUT_RST_CH0_S)
+#define AHB_DMA_OUT_RST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH0_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH0_M  (AHB_DMA_OUT_LOOP_TEST_CH0_V << AHB_DMA_OUT_LOOP_TEST_CH0_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_M  (AHB_DMA_OUT_AUTO_WRBACK_CH0_V << AHB_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH0_M  (AHB_DMA_OUT_EOF_MODE_CH0_V << AHB_DMA_OUT_EOF_MODE_CH0_S)
+#define AHB_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH0_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_M  (AHB_DMA_OUTDSCR_BURST_EN_CH0_V << AHB_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH0_S  4
+/** AHB_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH0    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH0_M  (AHB_DMA_OUT_ETM_EN_CH0_V << AHB_DMA_OUT_ETM_EN_CH0_S)
+#define AHB_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH0_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures max burst size for TX channel0.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH0_S  8
+
+/** AHB_DMA_OUT_CONF1_CH0_REG register
+ *  Configuration register 1 of TX channel 0
+ */
+#define AHB_DMA_OUT_CONF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x184)
+/** AHB_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_M  (AHB_DMA_OUT_CHECK_OWNER_CH0_V << AHB_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Transmit FIFO status of TX channel 0
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AHB_DMA_BASE + 0x188)
+/** AHB_DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH0    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH0_M  (AHB_DMA_OUTFIFO_FULL_CH0_V << AHB_DMA_OUTFIFO_FULL_CH0_S)
+#define AHB_DMA_OUTFIFO_FULL_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH0_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH0    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_M  (AHB_DMA_OUTFIFO_EMPTY_CH0_V << AHB_DMA_OUTFIFO_EMPTY_CH0_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH0_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 0.
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH0    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_M  (AHB_DMA_OUTFIFO_CNT_CH0_V << AHB_DMA_OUTFIFO_CNT_CH0_S)
+#define AHB_DMA_OUTFIFO_CNT_CH0_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH0_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+
+/** AHB_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of TX channel 0
+ */
+#define AHB_DMA_OUT_PUSH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x18c)
+/** AHB_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_M  (AHB_DMA_OUTFIFO_WDATA_CH0_V << AHB_DMA_OUTFIFO_WDATA_CH0_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH0_M  (AHB_DMA_OUTFIFO_PUSH_CH0_V << AHB_DMA_OUTFIFO_PUSH_CH0_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AHB_DMA_OUT_LINK_CH0_REG register
+ *  Linked list descriptor configuration and control register of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_CH0_REG (DR_REG_AHB_DMA_BASE + 0x190)
+/** AHB_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 0 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH0_M  (AHB_DMA_OUTLINK_STOP_CH0_V << AHB_DMA_OUTLINK_STOP_CH0_S)
+#define AHB_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH0_S  0
+/** AHB_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 0 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH0_M  (AHB_DMA_OUTLINK_START_CH0_V << AHB_DMA_OUTLINK_START_CH0_S)
+#define AHB_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH0_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 0 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH0_M  (AHB_DMA_OUTLINK_RESTART_CH0_V << AHB_DMA_OUTLINK_RESTART_CH0_S)
+#define AHB_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH0_S  2
+/** AHB_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH0_M  (AHB_DMA_OUTLINK_PARK_CH0_V << AHB_DMA_OUTLINK_PARK_CH0_S)
+#define AHB_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AHB_DMA_OUT_LINK_ADDR_CH0_REG register
+ *  Link list descriptor address configuration of TX channel 0
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x194)
+/** AHB_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_M  (AHB_DMA_OUTLINK_ADDR_CH0_V << AHB_DMA_OUTLINK_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of TX channel 0
+ */
+#define AHB_DMA_OUT_STATE_CH0_REG (DR_REG_AHB_DMA_BASE + 0x198)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_M  (AHB_DMA_OUT_DSCR_STATE_CH0_V << AHB_DMA_OUT_DSCR_STATE_CH0_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AHB_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH0    0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_M  (AHB_DMA_OUT_STATE_CH0_V << AHB_DMA_OUT_STATE_CH0_S)
+#define AHB_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH0_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x19c)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 0
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1a0)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG register
+ *  TX done outlink descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1a4)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH0_V << AHB_DMA_OUT_DONE_DES_ADDR_CH0_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_CH0_REG register
+ *  Current transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1a8)
+/** AHB_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_M  (AHB_DMA_OUTLINK_DSCR_CH0_V << AHB_DMA_OUTLINK_DSCR_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1ac)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH0_V << AHB_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last transmit descriptor address of TX channel 0
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1b0)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH0_V << AHB_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AHB_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of TX channel 0
+ */
+#define AHB_DMA_OUT_PRI_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1b4)
+/** AHB_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 0.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_TX_PRI_CH0    0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_M  (AHB_DMA_TX_PRI_CH0_V << AHB_DMA_TX_PRI_CH0_S)
+#define AHB_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH0_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection register of TX channel 0
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1b8)
+/** AHB_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 0.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_M  (AHB_DMA_PERI_OUT_SEL_CH0_V << AHB_DMA_PERI_OUT_SEL_CH0_S)
+#define AHB_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG register
+ *  TX channel 0 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1bc)
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel0
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_M  (AHB_DMA_TX_CH_ARB_WEIGH_CH0_V << AHB_DMA_TX_CH_ARB_WEIGH_CH0_S)
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH0_S  0
+
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG register
+ *  TX channel 0 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG (DR_REG_AHB_DMA_BASE + 0x1c0)
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S  0
+
+/** AHB_DMA_IN_CONF0_CH1_REG register
+ *  Configuration register 0 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x200)
+/** AHB_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH1    (BIT(0))
+#define AHB_DMA_IN_RST_CH1_M  (AHB_DMA_IN_RST_CH1_V << AHB_DMA_IN_RST_CH1_S)
+#define AHB_DMA_IN_RST_CH1_V  0x00000001U
+#define AHB_DMA_IN_RST_CH1_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH1_M  (AHB_DMA_IN_LOOP_TEST_CH1_V << AHB_DMA_IN_LOOP_TEST_CH1_S)
+#define AHB_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH1_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 1 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH1    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH1_M  (AHB_DMA_INDSCR_BURST_EN_CH1_V << AHB_DMA_INDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH1_S  2
+/** AHB_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH1    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH1_M  (AHB_DMA_MEM_TRANS_EN_CH1_V << AHB_DMA_MEM_TRANS_EN_CH1_S)
+#define AHB_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH1_S  4
+/** AHB_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH1    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH1_M  (AHB_DMA_IN_ETM_EN_CH1_V << AHB_DMA_IN_ETM_EN_CH1_S)
+#define AHB_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH1_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [7:6]; default: 0;
+ *  Configures max burst size for Rx channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH1_S  6
+
+/** AHB_DMA_IN_CONF1_CH1_REG register
+ *  Configuration register 1 of RX channel 1
+ */
+#define AHB_DMA_IN_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x204)
+/** AHB_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH1_M  (AHB_DMA_IN_CHECK_OWNER_CH1_V << AHB_DMA_IN_CHECK_OWNER_CH1_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of RX channel 1
+ */
+#define AHB_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x208)
+/** AHB_DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH1_M  (AHB_DMA_INFIFO_FULL_CH1_V << AHB_DMA_INFIFO_FULL_CH1_S)
+#define AHB_DMA_INFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH1_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH1_M  (AHB_DMA_INFIFO_EMPTY_CH1_V << AHB_DMA_INFIFO_EMPTY_CH1_S)
+#define AHB_DMA_INFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_INFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 1.
+ */
+#define AHB_DMA_INFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_M  (AHB_DMA_INFIFO_CNT_CH1_V << AHB_DMA_INFIFO_CNT_CH1_S)
+#define AHB_DMA_INFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH1_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH1    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_M  (AHB_DMA_IN_BUF_HUNGRY_CH1_V << AHB_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH1_S  27
+
+/** AHB_DMA_IN_POP_CH1_REG register
+ *  Pop control register of RX channel 1
+ */
+#define AHB_DMA_IN_POP_CH1_REG (DR_REG_AHB_DMA_BASE + 0x20c)
+/** AHB_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_M  (AHB_DMA_INFIFO_RDATA_CH1_V << AHB_DMA_INFIFO_RDATA_CH1_S)
+#define AHB_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH1_S  0
+/** AHB_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH1_M  (AHB_DMA_INFIFO_POP_CH1_V << AHB_DMA_INFIFO_POP_CH1_S)
+#define AHB_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH1_S  12
+
+/** AHB_DMA_IN_LINK_CH1_REG register
+ *  Linked list descriptor configuration and control register of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x210)
+/** AHB_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH1_M  (AHB_DMA_INLINK_AUTO_RET_CH1_V << AHB_DMA_INLINK_AUTO_RET_CH1_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AHB_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 1 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH1_M  (AHB_DMA_INLINK_STOP_CH1_V << AHB_DMA_INLINK_STOP_CH1_S)
+#define AHB_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH1_S  1
+/** AHB_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH1    (BIT(2))
+#define AHB_DMA_INLINK_START_CH1_M  (AHB_DMA_INLINK_START_CH1_V << AHB_DMA_INLINK_START_CH1_S)
+#define AHB_DMA_INLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH1_S  2
+/** AHB_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH1_M  (AHB_DMA_INLINK_RESTART_CH1_V << AHB_DMA_INLINK_RESTART_CH1_S)
+#define AHB_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH1_S  3
+/** AHB_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH1_M  (AHB_DMA_INLINK_PARK_CH1_V << AHB_DMA_INLINK_PARK_CH1_S)
+#define AHB_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH1_S  4
+
+/** AHB_DMA_IN_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of RX channel 1
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x214)
+/** AHB_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_M  (AHB_DMA_INLINK_ADDR_CH1_V << AHB_DMA_INLINK_ADDR_CH1_S)
+#define AHB_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_STATE_CH1_REG register
+ *  Receive status of RX channel 1
+ */
+#define AHB_DMA_IN_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x218)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_M  (AHB_DMA_INLINK_DSCR_ADDR_CH1_V << AHB_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_M  (AHB_DMA_IN_DSCR_STATE_CH1_V << AHB_DMA_IN_DSCR_STATE_CH1_S)
+#define AHB_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH1_S  18
+/** AHB_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_STATE_CH1    0x00000007U
+#define AHB_DMA_IN_STATE_CH1_M  (AHB_DMA_IN_STATE_CH1_V << AHB_DMA_IN_STATE_CH1_S)
+#define AHB_DMA_IN_STATE_CH1_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH1_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 1
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x21c)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Receive descriptor address when errors occur of RX channel 1
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x220)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1_REG register
+ *  RX_done inlink descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x224)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_M  (AHB_DMA_IN_DONE_DES_ADDR_CH1_V << AHB_DMA_IN_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_CH1_REG register
+ *  Current receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x228)
+/** AHB_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_M  (AHB_DMA_INLINK_DSCR_CH1_V << AHB_DMA_INLINK_DSCR_CH1_S)
+#define AHB_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x22c)
+/** AHB_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_M  (AHB_DMA_INLINK_DSCR_BF0_CH1_V << AHB_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last receive descriptor address of RX channel 1
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x230)
+/** AHB_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_M  (AHB_DMA_INLINK_DSCR_BF1_CH1_V << AHB_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_IN_PRI_CH1_REG register
+ *  Priority register of RX channel 1
+ */
+#define AHB_DMA_IN_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x234)
+/** AHB_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 1.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_RX_PRI_CH1    0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_M  (AHB_DMA_RX_PRI_CH1_V << AHB_DMA_RX_PRI_CH1_S)
+#define AHB_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH1_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of RX channel 1
+ */
+#define AHB_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x238)
+/** AHB_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 1.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_M  (AHB_DMA_PERI_IN_SEL_CH1_V << AHB_DMA_PERI_IN_SEL_CH1_S)
+#define AHB_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG register
+ *  RX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x23c)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel1
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH1_V << AHB_DMA_RX_CH_ARB_WEIGH_CH1_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH1_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG register
+ *  RX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x240)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S  0
+
+/** AHB_DMA_OUT_CONF0_CH1_REG register
+ *  Configuration register 0 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x280)
+/** AHB_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 1 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH1    (BIT(0))
+#define AHB_DMA_OUT_RST_CH1_M  (AHB_DMA_OUT_RST_CH1_V << AHB_DMA_OUT_RST_CH1_S)
+#define AHB_DMA_OUT_RST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH1_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH1_M  (AHB_DMA_OUT_LOOP_TEST_CH1_V << AHB_DMA_OUT_LOOP_TEST_CH1_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_M  (AHB_DMA_OUT_AUTO_WRBACK_CH1_V << AHB_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 1 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH1_M  (AHB_DMA_OUT_EOF_MODE_CH1_V << AHB_DMA_OUT_EOF_MODE_CH1_S)
+#define AHB_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH1_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 1 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_M  (AHB_DMA_OUTDSCR_BURST_EN_CH1_V << AHB_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH1_S  4
+/** AHB_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH1    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH1_M  (AHB_DMA_OUT_ETM_EN_CH1_V << AHB_DMA_OUT_ETM_EN_CH1_S)
+#define AHB_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH1_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures max burst size for TX channel1.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH1_S  8
+
+/** AHB_DMA_OUT_CONF1_CH1_REG register
+ *  Configuration register 1 of TX channel 1
+ */
+#define AHB_DMA_OUT_CONF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x284)
+/** AHB_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_M  (AHB_DMA_OUT_CHECK_OWNER_CH1_V << AHB_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Transmit FIFO status of TX channel 1
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AHB_DMA_BASE + 0x288)
+/** AHB_DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH1    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH1_M  (AHB_DMA_OUTFIFO_FULL_CH1_V << AHB_DMA_OUTFIFO_FULL_CH1_S)
+#define AHB_DMA_OUTFIFO_FULL_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH1_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH1    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_M  (AHB_DMA_OUTFIFO_EMPTY_CH1_V << AHB_DMA_OUTFIFO_EMPTY_CH1_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH1_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 1.
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH1    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_M  (AHB_DMA_OUTFIFO_CNT_CH1_V << AHB_DMA_OUTFIFO_CNT_CH1_S)
+#define AHB_DMA_OUTFIFO_CNT_CH1_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH1_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+
+/** AHB_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of TX channel 1
+ */
+#define AHB_DMA_OUT_PUSH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x28c)
+/** AHB_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_M  (AHB_DMA_OUTFIFO_WDATA_CH1_V << AHB_DMA_OUTFIFO_WDATA_CH1_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH1_M  (AHB_DMA_OUTFIFO_PUSH_CH1_V << AHB_DMA_OUTFIFO_PUSH_CH1_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AHB_DMA_OUT_LINK_CH1_REG register
+ *  Linked list descriptor configuration and control register of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_CH1_REG (DR_REG_AHB_DMA_BASE + 0x290)
+/** AHB_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 1 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH1_M  (AHB_DMA_OUTLINK_STOP_CH1_V << AHB_DMA_OUTLINK_STOP_CH1_S)
+#define AHB_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH1_S  0
+/** AHB_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 1 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH1_M  (AHB_DMA_OUTLINK_START_CH1_V << AHB_DMA_OUTLINK_START_CH1_S)
+#define AHB_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH1_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 1 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH1_M  (AHB_DMA_OUTLINK_RESTART_CH1_V << AHB_DMA_OUTLINK_RESTART_CH1_S)
+#define AHB_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH1_S  2
+/** AHB_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH1_M  (AHB_DMA_OUTLINK_PARK_CH1_V << AHB_DMA_OUTLINK_PARK_CH1_S)
+#define AHB_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AHB_DMA_OUT_LINK_ADDR_CH1_REG register
+ *  Link list descriptor address configuration of TX channel 1
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x294)
+/** AHB_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_M  (AHB_DMA_OUTLINK_ADDR_CH1_V << AHB_DMA_OUTLINK_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of TX channel 1
+ */
+#define AHB_DMA_OUT_STATE_CH1_REG (DR_REG_AHB_DMA_BASE + 0x298)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_M  (AHB_DMA_OUT_DSCR_STATE_CH1_V << AHB_DMA_OUT_DSCR_STATE_CH1_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AHB_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH1    0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_M  (AHB_DMA_OUT_STATE_CH1_V << AHB_DMA_OUT_STATE_CH1_S)
+#define AHB_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH1_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x29c)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 1
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2a0)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG register
+ *  TX done outlink descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2a4)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH1_V << AHB_DMA_OUT_DONE_DES_ADDR_CH1_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_CH1_REG register
+ *  Current transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2a8)
+/** AHB_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_M  (AHB_DMA_OUTLINK_DSCR_CH1_V << AHB_DMA_OUTLINK_DSCR_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2ac)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH1_V << AHB_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last transmit descriptor address of TX channel 1
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2b0)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH1_V << AHB_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AHB_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of TX channel 1
+ */
+#define AHB_DMA_OUT_PRI_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2b4)
+/** AHB_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 1.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_TX_PRI_CH1    0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_M  (AHB_DMA_TX_PRI_CH1_V << AHB_DMA_TX_PRI_CH1_S)
+#define AHB_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH1_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection register of TX channel 1
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2b8)
+/** AHB_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 1.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_M  (AHB_DMA_PERI_OUT_SEL_CH1_V << AHB_DMA_PERI_OUT_SEL_CH1_S)
+#define AHB_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG register
+ *  TX channel 1 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2bc)
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel1
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_M  (AHB_DMA_TX_CH_ARB_WEIGH_CH1_V << AHB_DMA_TX_CH_ARB_WEIGH_CH1_S)
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH1_S  0
+
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG register
+ *  TX channel 1 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG (DR_REG_AHB_DMA_BASE + 0x2c0)
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S  0
+
+/** AHB_DMA_IN_CONF0_CH2_REG register
+ *  Configuration register 0 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x300)
+/** AHB_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH2    (BIT(0))
+#define AHB_DMA_IN_RST_CH2_M  (AHB_DMA_IN_RST_CH2_V << AHB_DMA_IN_RST_CH2_S)
+#define AHB_DMA_IN_RST_CH2_V  0x00000001U
+#define AHB_DMA_IN_RST_CH2_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH2_M  (AHB_DMA_IN_LOOP_TEST_CH2_V << AHB_DMA_IN_LOOP_TEST_CH2_S)
+#define AHB_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH2_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 2 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH2    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH2_M  (AHB_DMA_INDSCR_BURST_EN_CH2_V << AHB_DMA_INDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH2_S  2
+/** AHB_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH2    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH2_M  (AHB_DMA_MEM_TRANS_EN_CH2_V << AHB_DMA_MEM_TRANS_EN_CH2_S)
+#define AHB_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH2_S  4
+/** AHB_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH2    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH2_M  (AHB_DMA_IN_ETM_EN_CH2_V << AHB_DMA_IN_ETM_EN_CH2_S)
+#define AHB_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH2_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [7:6]; default: 0;
+ *  Configures max burst size for Rx channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH2_S  6
+
+/** AHB_DMA_IN_CONF1_CH2_REG register
+ *  Configuration register 1 of RX channel 2
+ */
+#define AHB_DMA_IN_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x304)
+/** AHB_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH2_M  (AHB_DMA_IN_CHECK_OWNER_CH2_V << AHB_DMA_IN_CHECK_OWNER_CH2_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of RX channel 2
+ */
+#define AHB_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x308)
+/** AHB_DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH2_M  (AHB_DMA_INFIFO_FULL_CH2_V << AHB_DMA_INFIFO_FULL_CH2_S)
+#define AHB_DMA_INFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH2_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH2_M  (AHB_DMA_INFIFO_EMPTY_CH2_V << AHB_DMA_INFIFO_EMPTY_CH2_S)
+#define AHB_DMA_INFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_INFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 2.
+ */
+#define AHB_DMA_INFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_M  (AHB_DMA_INFIFO_CNT_CH2_V << AHB_DMA_INFIFO_CNT_CH2_S)
+#define AHB_DMA_INFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH2_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH2    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_M  (AHB_DMA_IN_BUF_HUNGRY_CH2_V << AHB_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH2_S  27
+
+/** AHB_DMA_IN_POP_CH2_REG register
+ *  Pop control register of RX channel 2
+ */
+#define AHB_DMA_IN_POP_CH2_REG (DR_REG_AHB_DMA_BASE + 0x30c)
+/** AHB_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_M  (AHB_DMA_INFIFO_RDATA_CH2_V << AHB_DMA_INFIFO_RDATA_CH2_S)
+#define AHB_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH2_S  0
+/** AHB_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH2_M  (AHB_DMA_INFIFO_POP_CH2_V << AHB_DMA_INFIFO_POP_CH2_S)
+#define AHB_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH2_S  12
+
+/** AHB_DMA_IN_LINK_CH2_REG register
+ *  Linked list descriptor configuration and control register of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x310)
+/** AHB_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH2_M  (AHB_DMA_INLINK_AUTO_RET_CH2_V << AHB_DMA_INLINK_AUTO_RET_CH2_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AHB_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 2 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH2_M  (AHB_DMA_INLINK_STOP_CH2_V << AHB_DMA_INLINK_STOP_CH2_S)
+#define AHB_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH2_S  1
+/** AHB_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH2    (BIT(2))
+#define AHB_DMA_INLINK_START_CH2_M  (AHB_DMA_INLINK_START_CH2_V << AHB_DMA_INLINK_START_CH2_S)
+#define AHB_DMA_INLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH2_S  2
+/** AHB_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH2_M  (AHB_DMA_INLINK_RESTART_CH2_V << AHB_DMA_INLINK_RESTART_CH2_S)
+#define AHB_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH2_S  3
+/** AHB_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH2_M  (AHB_DMA_INLINK_PARK_CH2_V << AHB_DMA_INLINK_PARK_CH2_S)
+#define AHB_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH2_S  4
+
+/** AHB_DMA_IN_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of RX channel 2
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x314)
+/** AHB_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_M  (AHB_DMA_INLINK_ADDR_CH2_V << AHB_DMA_INLINK_ADDR_CH2_S)
+#define AHB_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_STATE_CH2_REG register
+ *  Receive status of RX channel 2
+ */
+#define AHB_DMA_IN_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x318)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_M  (AHB_DMA_INLINK_DSCR_ADDR_CH2_V << AHB_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_M  (AHB_DMA_IN_DSCR_STATE_CH2_V << AHB_DMA_IN_DSCR_STATE_CH2_S)
+#define AHB_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH2_S  18
+/** AHB_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_STATE_CH2    0x00000007U
+#define AHB_DMA_IN_STATE_CH2_M  (AHB_DMA_IN_STATE_CH2_V << AHB_DMA_IN_STATE_CH2_S)
+#define AHB_DMA_IN_STATE_CH2_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH2_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 2
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x31c)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Receive descriptor address when errors occur of RX channel 2
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x320)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2_REG register
+ *  RX_done inlink descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x324)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_M  (AHB_DMA_IN_DONE_DES_ADDR_CH2_V << AHB_DMA_IN_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_CH2_REG register
+ *  Current receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x328)
+/** AHB_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_M  (AHB_DMA_INLINK_DSCR_CH2_V << AHB_DMA_INLINK_DSCR_CH2_S)
+#define AHB_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x32c)
+/** AHB_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_M  (AHB_DMA_INLINK_DSCR_BF0_CH2_V << AHB_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last receive descriptor address of RX channel 2
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x330)
+/** AHB_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_M  (AHB_DMA_INLINK_DSCR_BF1_CH2_V << AHB_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_IN_PRI_CH2_REG register
+ *  Priority register of RX channel 2
+ */
+#define AHB_DMA_IN_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x334)
+/** AHB_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 2.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_RX_PRI_CH2    0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_M  (AHB_DMA_RX_PRI_CH2_V << AHB_DMA_RX_PRI_CH2_S)
+#define AHB_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH2_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of RX channel 2
+ */
+#define AHB_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x338)
+/** AHB_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 2.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_M  (AHB_DMA_PERI_IN_SEL_CH2_V << AHB_DMA_PERI_IN_SEL_CH2_S)
+#define AHB_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG register
+ *  RX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x33c)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel2
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH2_V << AHB_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH2_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG register
+ *  RX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x340)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  0
+
+/** AHB_DMA_OUT_CONF0_CH2_REG register
+ *  Configuration register 0 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x380)
+/** AHB_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 2 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH2    (BIT(0))
+#define AHB_DMA_OUT_RST_CH2_M  (AHB_DMA_OUT_RST_CH2_V << AHB_DMA_OUT_RST_CH2_S)
+#define AHB_DMA_OUT_RST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH2_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH2_M  (AHB_DMA_OUT_LOOP_TEST_CH2_V << AHB_DMA_OUT_LOOP_TEST_CH2_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_M  (AHB_DMA_OUT_AUTO_WRBACK_CH2_V << AHB_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 2 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH2_M  (AHB_DMA_OUT_EOF_MODE_CH2_V << AHB_DMA_OUT_EOF_MODE_CH2_S)
+#define AHB_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH2_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 2 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_M  (AHB_DMA_OUTDSCR_BURST_EN_CH2_V << AHB_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH2_S  4
+/** AHB_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH2    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH2_M  (AHB_DMA_OUT_ETM_EN_CH2_V << AHB_DMA_OUT_ETM_EN_CH2_S)
+#define AHB_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH2_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures max burst size for TX channel2.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH2_S  8
+
+/** AHB_DMA_OUT_CONF1_CH2_REG register
+ *  Configuration register 1 of TX channel 2
+ */
+#define AHB_DMA_OUT_CONF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x384)
+/** AHB_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_M  (AHB_DMA_OUT_CHECK_OWNER_CH2_V << AHB_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Transmit FIFO status of TX channel 2
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AHB_DMA_BASE + 0x388)
+/** AHB_DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH2    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH2_M  (AHB_DMA_OUTFIFO_FULL_CH2_V << AHB_DMA_OUTFIFO_FULL_CH2_S)
+#define AHB_DMA_OUTFIFO_FULL_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH2_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH2    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_M  (AHB_DMA_OUTFIFO_EMPTY_CH2_V << AHB_DMA_OUTFIFO_EMPTY_CH2_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH2_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 2.
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH2    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_M  (AHB_DMA_OUTFIFO_CNT_CH2_V << AHB_DMA_OUTFIFO_CNT_CH2_S)
+#define AHB_DMA_OUTFIFO_CNT_CH2_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH2_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+
+/** AHB_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of TX channel 2
+ */
+#define AHB_DMA_OUT_PUSH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x38c)
+/** AHB_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_M  (AHB_DMA_OUTFIFO_WDATA_CH2_V << AHB_DMA_OUTFIFO_WDATA_CH2_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH2_M  (AHB_DMA_OUTFIFO_PUSH_CH2_V << AHB_DMA_OUTFIFO_PUSH_CH2_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AHB_DMA_OUT_LINK_CH2_REG register
+ *  Linked list descriptor configuration and control register of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_CH2_REG (DR_REG_AHB_DMA_BASE + 0x390)
+/** AHB_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 2 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH2_M  (AHB_DMA_OUTLINK_STOP_CH2_V << AHB_DMA_OUTLINK_STOP_CH2_S)
+#define AHB_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH2_S  0
+/** AHB_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 2 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH2_M  (AHB_DMA_OUTLINK_START_CH2_V << AHB_DMA_OUTLINK_START_CH2_S)
+#define AHB_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH2_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 2 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH2_M  (AHB_DMA_OUTLINK_RESTART_CH2_V << AHB_DMA_OUTLINK_RESTART_CH2_S)
+#define AHB_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH2_S  2
+/** AHB_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH2_M  (AHB_DMA_OUTLINK_PARK_CH2_V << AHB_DMA_OUTLINK_PARK_CH2_S)
+#define AHB_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AHB_DMA_OUT_LINK_ADDR_CH2_REG register
+ *  Link list descriptor address configuration of TX channel 2
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x394)
+/** AHB_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_M  (AHB_DMA_OUTLINK_ADDR_CH2_V << AHB_DMA_OUTLINK_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of TX channel 2
+ */
+#define AHB_DMA_OUT_STATE_CH2_REG (DR_REG_AHB_DMA_BASE + 0x398)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_M  (AHB_DMA_OUT_DSCR_STATE_CH2_V << AHB_DMA_OUT_DSCR_STATE_CH2_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AHB_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH2    0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_M  (AHB_DMA_OUT_STATE_CH2_V << AHB_DMA_OUT_STATE_CH2_S)
+#define AHB_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH2_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x39c)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 2
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a0)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG register
+ *  TX done outlink descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a4)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH2_V << AHB_DMA_OUT_DONE_DES_ADDR_CH2_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_CH2_REG register
+ *  Current transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3a8)
+/** AHB_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_M  (AHB_DMA_OUTLINK_DSCR_CH2_V << AHB_DMA_OUTLINK_DSCR_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3ac)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH2_V << AHB_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last transmit descriptor address of TX channel 2
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b0)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH2_V << AHB_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AHB_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of TX channel 2
+ */
+#define AHB_DMA_OUT_PRI_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b4)
+/** AHB_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 2.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_TX_PRI_CH2    0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_M  (AHB_DMA_TX_PRI_CH2_V << AHB_DMA_TX_PRI_CH2_S)
+#define AHB_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH2_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection register of TX channel 2
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3b8)
+/** AHB_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 2.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_M  (AHB_DMA_PERI_OUT_SEL_CH2_V << AHB_DMA_PERI_OUT_SEL_CH2_S)
+#define AHB_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG register
+ *  TX channel 2 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3bc)
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel2
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_M  (AHB_DMA_TX_CH_ARB_WEIGH_CH2_V << AHB_DMA_TX_CH_ARB_WEIGH_CH2_S)
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH2_S  0
+
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG register
+ *  TX channel 2 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG (DR_REG_AHB_DMA_BASE + 0x3c0)
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S  0
+
+/** AHB_DMA_IN_CONF0_CH3_REG register
+ *  Configuration register 0 of RX channel 3
+ */
+#define AHB_DMA_IN_CONF0_CH3_REG (DR_REG_AHB_DMA_BASE + 0x400)
+/** AHB_DMA_IN_RST_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH3    (BIT(0))
+#define AHB_DMA_IN_RST_CH3_M  (AHB_DMA_IN_RST_CH3_V << AHB_DMA_IN_RST_CH3_S)
+#define AHB_DMA_IN_RST_CH3_V  0x00000001U
+#define AHB_DMA_IN_RST_CH3_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH3 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH3    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH3_M  (AHB_DMA_IN_LOOP_TEST_CH3_V << AHB_DMA_IN_LOOP_TEST_CH3_S)
+#define AHB_DMA_IN_LOOP_TEST_CH3_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH3_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 3 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH3    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH3_M  (AHB_DMA_INDSCR_BURST_EN_CH3_V << AHB_DMA_INDSCR_BURST_EN_CH3_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH3_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH3_S  2
+/** AHB_DMA_MEM_TRANS_EN_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH3    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH3_M  (AHB_DMA_MEM_TRANS_EN_CH3_V << AHB_DMA_MEM_TRANS_EN_CH3_S)
+#define AHB_DMA_MEM_TRANS_EN_CH3_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH3_S  4
+/** AHB_DMA_IN_ETM_EN_CH3 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH3    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH3_M  (AHB_DMA_IN_ETM_EN_CH3_V << AHB_DMA_IN_ETM_EN_CH3_S)
+#define AHB_DMA_IN_ETM_EN_CH3_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH3_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3 : R/W; bitpos: [7:6]; default: 0;
+ *  Configures max burst size for Rx channel3.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH3_S  6
+
+/** AHB_DMA_IN_CONF1_CH3_REG register
+ *  Configuration register 1 of RX channel 3
+ */
+#define AHB_DMA_IN_CONF1_CH3_REG (DR_REG_AHB_DMA_BASE + 0x404)
+/** AHB_DMA_IN_CHECK_OWNER_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH3    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH3_M  (AHB_DMA_IN_CHECK_OWNER_CH3_V << AHB_DMA_IN_CHECK_OWNER_CH3_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH3_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH3_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH3_REG register
+ *  Receive FIFO status of RX channel 3
+ */
+#define AHB_DMA_INFIFO_STATUS_CH3_REG (DR_REG_AHB_DMA_BASE + 0x408)
+/** AHB_DMA_INFIFO_FULL_CH3 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH3    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH3_M  (AHB_DMA_INFIFO_FULL_CH3_V << AHB_DMA_INFIFO_FULL_CH3_S)
+#define AHB_DMA_INFIFO_FULL_CH3_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH3_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH3 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH3    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH3_M  (AHB_DMA_INFIFO_EMPTY_CH3_V << AHB_DMA_INFIFO_EMPTY_CH3_S)
+#define AHB_DMA_INFIFO_EMPTY_CH3_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH3_S  1
+/** AHB_DMA_INFIFO_CNT_CH3 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 3.
+ */
+#define AHB_DMA_INFIFO_CNT_CH3    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH3_M  (AHB_DMA_INFIFO_CNT_CH3_V << AHB_DMA_INFIFO_CNT_CH3_S)
+#define AHB_DMA_INFIFO_CNT_CH3_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH3_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH3 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH3    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH3_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH3_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH3_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH3_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH3_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH3 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH3    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH3_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH3_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH3_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH3_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH3_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH3 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH3    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH3_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH3_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH3_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH3_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH3_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH3 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH3    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH3_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH3_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH3_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH3_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH3_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH3 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH3    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH3_M  (AHB_DMA_IN_BUF_HUNGRY_CH3_V << AHB_DMA_IN_BUF_HUNGRY_CH3_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH3_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH3_S  27
+
+/** AHB_DMA_IN_POP_CH3_REG register
+ *  Pop control register of RX channel 3
+ */
+#define AHB_DMA_IN_POP_CH3_REG (DR_REG_AHB_DMA_BASE + 0x40c)
+/** AHB_DMA_INFIFO_RDATA_CH3 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH3    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH3_M  (AHB_DMA_INFIFO_RDATA_CH3_V << AHB_DMA_INFIFO_RDATA_CH3_S)
+#define AHB_DMA_INFIFO_RDATA_CH3_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH3_S  0
+/** AHB_DMA_INFIFO_POP_CH3 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH3    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH3_M  (AHB_DMA_INFIFO_POP_CH3_V << AHB_DMA_INFIFO_POP_CH3_S)
+#define AHB_DMA_INFIFO_POP_CH3_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH3_S  12
+
+/** AHB_DMA_IN_LINK_CH3_REG register
+ *  Linked list descriptor configuration and control register of RX channel 3
+ */
+#define AHB_DMA_IN_LINK_CH3_REG (DR_REG_AHB_DMA_BASE + 0x410)
+/** AHB_DMA_INLINK_AUTO_RET_CH3 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH3    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH3_M  (AHB_DMA_INLINK_AUTO_RET_CH3_V << AHB_DMA_INLINK_AUTO_RET_CH3_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH3_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH3_S  0
+/** AHB_DMA_INLINK_STOP_CH3 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 3 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH3    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH3_M  (AHB_DMA_INLINK_STOP_CH3_V << AHB_DMA_INLINK_STOP_CH3_S)
+#define AHB_DMA_INLINK_STOP_CH3_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH3_S  1
+/** AHB_DMA_INLINK_START_CH3 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 3 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH3    (BIT(2))
+#define AHB_DMA_INLINK_START_CH3_M  (AHB_DMA_INLINK_START_CH3_V << AHB_DMA_INLINK_START_CH3_S)
+#define AHB_DMA_INLINK_START_CH3_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH3_S  2
+/** AHB_DMA_INLINK_RESTART_CH3 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 3 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH3    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH3_M  (AHB_DMA_INLINK_RESTART_CH3_V << AHB_DMA_INLINK_RESTART_CH3_S)
+#define AHB_DMA_INLINK_RESTART_CH3_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH3_S  3
+/** AHB_DMA_INLINK_PARK_CH3 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH3    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH3_M  (AHB_DMA_INLINK_PARK_CH3_V << AHB_DMA_INLINK_PARK_CH3_S)
+#define AHB_DMA_INLINK_PARK_CH3_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH3_S  4
+
+/** AHB_DMA_IN_LINK_ADDR_CH3_REG register
+ *  Link list descriptor address configuration of RX channel 3
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x414)
+/** AHB_DMA_INLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_INLINK_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH3_M  (AHB_DMA_INLINK_ADDR_CH3_V << AHB_DMA_INLINK_ADDR_CH3_S)
+#define AHB_DMA_INLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH3_S  0
+
+/** AHB_DMA_IN_STATE_CH3_REG register
+ *  Receive status of RX channel 3
+ */
+#define AHB_DMA_IN_STATE_CH3_REG (DR_REG_AHB_DMA_BASE + 0x418)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH3_M  (AHB_DMA_INLINK_DSCR_ADDR_CH3_V << AHB_DMA_INLINK_DSCR_ADDR_CH3_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH3_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH3    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH3_M  (AHB_DMA_IN_DSCR_STATE_CH3_V << AHB_DMA_IN_DSCR_STATE_CH3_S)
+#define AHB_DMA_IN_DSCR_STATE_CH3_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH3_S  18
+/** AHB_DMA_IN_STATE_CH3 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_STATE_CH3    0x00000007U
+#define AHB_DMA_IN_STATE_CH3_M  (AHB_DMA_IN_STATE_CH3_V << AHB_DMA_IN_STATE_CH3_S)
+#define AHB_DMA_IN_STATE_CH3_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH3_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 3
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x41c)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG register
+ *  Receive descriptor address when errors occur of RX channel 3
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x420)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH3_REG register
+ *  RX_done inlink descriptor address of RX channel 3
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x424)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH3_M  (AHB_DMA_IN_DONE_DES_ADDR_CH3_V << AHB_DMA_IN_DONE_DES_ADDR_CH3_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_IN_DSCR_CH3_REG register
+ *  Current receive descriptor address of RX channel 3
+ */
+#define AHB_DMA_IN_DSCR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x428)
+/** AHB_DMA_INLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH3    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH3_M  (AHB_DMA_INLINK_DSCR_CH3_V << AHB_DMA_INLINK_DSCR_CH3_S)
+#define AHB_DMA_INLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH3_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH3_REG register
+ *  The last receive descriptor address of RX channel 3
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH3_REG (DR_REG_AHB_DMA_BASE + 0x42c)
+/** AHB_DMA_INLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH3_M  (AHB_DMA_INLINK_DSCR_BF0_CH3_V << AHB_DMA_INLINK_DSCR_BF0_CH3_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH3_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH3_REG register
+ *  The second-to-last receive descriptor address of RX channel 3
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH3_REG (DR_REG_AHB_DMA_BASE + 0x430)
+/** AHB_DMA_INLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH3_M  (AHB_DMA_INLINK_DSCR_BF1_CH3_V << AHB_DMA_INLINK_DSCR_BF1_CH3_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH3_S  0
+
+/** AHB_DMA_IN_PRI_CH3_REG register
+ *  Priority register of RX channel 3
+ */
+#define AHB_DMA_IN_PRI_CH3_REG (DR_REG_AHB_DMA_BASE + 0x434)
+/** AHB_DMA_RX_PRI_CH3 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 3.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_RX_PRI_CH3    0x0000000FU
+#define AHB_DMA_RX_PRI_CH3_M  (AHB_DMA_RX_PRI_CH3_V << AHB_DMA_RX_PRI_CH3_S)
+#define AHB_DMA_RX_PRI_CH3_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH3_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH3_REG register
+ *  Peripheral selection register of RX channel 3
+ */
+#define AHB_DMA_IN_PERI_SEL_CH3_REG (DR_REG_AHB_DMA_BASE + 0x438)
+/** AHB_DMA_PERI_IN_SEL_CH3 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 3.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_IN_SEL_CH3    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH3_M  (AHB_DMA_PERI_IN_SEL_CH3_V << AHB_DMA_PERI_IN_SEL_CH3_S)
+#define AHB_DMA_PERI_IN_SEL_CH3_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH3_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG register
+ *  RX channel 3 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH3_REG (DR_REG_AHB_DMA_BASE + 0x43c)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH3 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel3
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH3    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH3_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH3_V << AHB_DMA_RX_CH_ARB_WEIGH_CH3_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH3_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH3_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG register
+ *  RX channel 3 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x440)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH3_S  0
+
+/** AHB_DMA_OUT_CONF0_CH3_REG register
+ *  Configuration register 0 of TX channel 3
+ */
+#define AHB_DMA_OUT_CONF0_CH3_REG (DR_REG_AHB_DMA_BASE + 0x480)
+/** AHB_DMA_OUT_RST_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 3 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH3    (BIT(0))
+#define AHB_DMA_OUT_RST_CH3_M  (AHB_DMA_OUT_RST_CH3_V << AHB_DMA_OUT_RST_CH3_S)
+#define AHB_DMA_OUT_RST_CH3_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH3_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH3 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH3    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH3_M  (AHB_DMA_OUT_LOOP_TEST_CH3_V << AHB_DMA_OUT_LOOP_TEST_CH3_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH3_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH3_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH3    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH3_M  (AHB_DMA_OUT_AUTO_WRBACK_CH3_V << AHB_DMA_OUT_AUTO_WRBACK_CH3_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH3_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH3 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 3 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 3 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH3    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH3_M  (AHB_DMA_OUT_EOF_MODE_CH3_V << AHB_DMA_OUT_EOF_MODE_CH3_S)
+#define AHB_DMA_OUT_EOF_MODE_CH3_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH3_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 3 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH3    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH3_M  (AHB_DMA_OUTDSCR_BURST_EN_CH3_V << AHB_DMA_OUTDSCR_BURST_EN_CH3_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH3_S  4
+/** AHB_DMA_OUT_ETM_EN_CH3 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH3    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH3_M  (AHB_DMA_OUT_ETM_EN_CH3_V << AHB_DMA_OUT_ETM_EN_CH3_S)
+#define AHB_DMA_OUT_ETM_EN_CH3_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH3_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures max burst size for TX channel3.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH3_S  8
+
+/** AHB_DMA_OUT_CONF1_CH3_REG register
+ *  Configuration register 1 of TX channel 3
+ */
+#define AHB_DMA_OUT_CONF1_CH3_REG (DR_REG_AHB_DMA_BASE + 0x484)
+/** AHB_DMA_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH3    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH3_M  (AHB_DMA_OUT_CHECK_OWNER_CH3_V << AHB_DMA_OUT_CHECK_OWNER_CH3_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH3_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH3_REG register
+ *  Transmit FIFO status of TX channel 3
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH3_REG (DR_REG_AHB_DMA_BASE + 0x488)
+/** AHB_DMA_OUTFIFO_FULL_CH3 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH3    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH3_M  (AHB_DMA_OUTFIFO_FULL_CH3_V << AHB_DMA_OUTFIFO_FULL_CH3_S)
+#define AHB_DMA_OUTFIFO_FULL_CH3_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH3_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH3 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH3    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH3_M  (AHB_DMA_OUTFIFO_EMPTY_CH3_V << AHB_DMA_OUTFIFO_EMPTY_CH3_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH3_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH3_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH3 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 3.
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH3    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH3_M  (AHB_DMA_OUTFIFO_CNT_CH3_V << AHB_DMA_OUTFIFO_CNT_CH3_S)
+#define AHB_DMA_OUTFIFO_CNT_CH3_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH3_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [23]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH3    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH3_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH3_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH3_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH3_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH3_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [24]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH3    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH3_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH3_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH3_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH3_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH3_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [25]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH3    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH3_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH3_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH3_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH3_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH3_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [26]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH3    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH3_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH3_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH3_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH3_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH3_S  26
+
+/** AHB_DMA_OUT_PUSH_CH3_REG register
+ *  Push control register of TX channel 3
+ */
+#define AHB_DMA_OUT_PUSH_CH3_REG (DR_REG_AHB_DMA_BASE + 0x48c)
+/** AHB_DMA_OUTFIFO_WDATA_CH3 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH3    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH3_M  (AHB_DMA_OUTFIFO_WDATA_CH3_V << AHB_DMA_OUTFIFO_WDATA_CH3_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH3_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH3_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH3 : WT; bitpos: [9]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH3    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH3_M  (AHB_DMA_OUTFIFO_PUSH_CH3_V << AHB_DMA_OUTFIFO_PUSH_CH3_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH3_S  9
+
+/** AHB_DMA_OUT_LINK_CH3_REG register
+ *  Linked list descriptor configuration and control register of TX channel 3
+ */
+#define AHB_DMA_OUT_LINK_CH3_REG (DR_REG_AHB_DMA_BASE + 0x490)
+/** AHB_DMA_OUTLINK_STOP_CH3 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 3 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH3    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH3_M  (AHB_DMA_OUTLINK_STOP_CH3_V << AHB_DMA_OUTLINK_STOP_CH3_S)
+#define AHB_DMA_OUTLINK_STOP_CH3_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH3_S  0
+/** AHB_DMA_OUTLINK_START_CH3 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 3 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH3    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH3_M  (AHB_DMA_OUTLINK_START_CH3_V << AHB_DMA_OUTLINK_START_CH3_S)
+#define AHB_DMA_OUTLINK_START_CH3_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH3_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH3 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 3 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH3    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH3_M  (AHB_DMA_OUTLINK_RESTART_CH3_V << AHB_DMA_OUTLINK_RESTART_CH3_S)
+#define AHB_DMA_OUTLINK_RESTART_CH3_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH3_S  2
+/** AHB_DMA_OUTLINK_PARK_CH3 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH3    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH3_M  (AHB_DMA_OUTLINK_PARK_CH3_V << AHB_DMA_OUTLINK_PARK_CH3_S)
+#define AHB_DMA_OUTLINK_PARK_CH3_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH3_S  3
+
+/** AHB_DMA_OUT_LINK_ADDR_CH3_REG register
+ *  Link list descriptor address configuration of TX channel 3
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x494)
+/** AHB_DMA_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH3_M  (AHB_DMA_OUTLINK_ADDR_CH3_V << AHB_DMA_OUTLINK_ADDR_CH3_S)
+#define AHB_DMA_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH3_S  0
+
+/** AHB_DMA_OUT_STATE_CH3_REG register
+ *  Transmit status of TX channel 3
+ */
+#define AHB_DMA_OUT_STATE_CH3_REG (DR_REG_AHB_DMA_BASE + 0x498)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH3_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH3_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH3_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH3_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH3    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH3_M  (AHB_DMA_OUT_DSCR_STATE_CH3_V << AHB_DMA_OUT_DSCR_STATE_CH3_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH3_S  18
+/** AHB_DMA_OUT_STATE_CH3 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH3    0x00000007U
+#define AHB_DMA_OUT_STATE_CH3_M  (AHB_DMA_OUT_STATE_CH3_V << AHB_DMA_OUT_STATE_CH3_S)
+#define AHB_DMA_OUT_STATE_CH3_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH3_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH3_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 3
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x49c)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH3_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH3_V << AHB_DMA_OUT_EOF_DES_ADDR_CH3_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 3
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4a0)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH3_REG register
+ *  TX done outlink descriptor address of TX channel 3
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4a4)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH3_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH3_V << AHB_DMA_OUT_DONE_DES_ADDR_CH3_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH3_S  0
+
+/** AHB_DMA_OUT_DSCR_CH3_REG register
+ *  Current transmit descriptor address of TX channel 3
+ */
+#define AHB_DMA_OUT_DSCR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4a8)
+/** AHB_DMA_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH3_M  (AHB_DMA_OUTLINK_DSCR_CH3_V << AHB_DMA_OUTLINK_DSCR_CH3_S)
+#define AHB_DMA_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH3_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH3_REG register
+ *  The last transmit descriptor address of TX channel 3
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4ac)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH3_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH3_V << AHB_DMA_OUTLINK_DSCR_BF0_CH3_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH3_REG register
+ *  The second-to-last transmit descriptor address of TX channel 3
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4b0)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH3_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH3_V << AHB_DMA_OUTLINK_DSCR_BF1_CH3_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** AHB_DMA_OUT_PRI_CH3_REG register
+ *  Priority register of TX channel 3
+ */
+#define AHB_DMA_OUT_PRI_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4b4)
+/** AHB_DMA_TX_PRI_CH3 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 3.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_TX_PRI_CH3    0x0000000FU
+#define AHB_DMA_TX_PRI_CH3_M  (AHB_DMA_TX_PRI_CH3_V << AHB_DMA_TX_PRI_CH3_S)
+#define AHB_DMA_TX_PRI_CH3_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH3_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH3_REG register
+ *  Peripheral selection register of TX channel 3
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4b8)
+/** AHB_DMA_PERI_OUT_SEL_CH3 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 3.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH3    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH3_M  (AHB_DMA_PERI_OUT_SEL_CH3_V << AHB_DMA_PERI_OUT_SEL_CH3_S)
+#define AHB_DMA_PERI_OUT_SEL_CH3_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH3_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG register
+ *  TX channel 3 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4bc)
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH3 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel3
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH3    0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH3_M  (AHB_DMA_TX_CH_ARB_WEIGH_CH3_V << AHB_DMA_TX_CH_ARB_WEIGH_CH3_S)
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH3_V  0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH3_S  0
+
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG register
+ *  TX channel 3 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_REG (DR_REG_AHB_DMA_BASE + 0x4c0)
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_M  (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_S)
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH3_S  0
+
+/** AHB_DMA_IN_CONF0_CH4_REG register
+ *  Configuration register 0 of RX channel 4
+ */
+#define AHB_DMA_IN_CONF0_CH4_REG (DR_REG_AHB_DMA_BASE + 0x500)
+/** AHB_DMA_IN_RST_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+ */
+#define AHB_DMA_IN_RST_CH4    (BIT(0))
+#define AHB_DMA_IN_RST_CH4_M  (AHB_DMA_IN_RST_CH4_V << AHB_DMA_IN_RST_CH4_S)
+#define AHB_DMA_IN_RST_CH4_V  0x00000001U
+#define AHB_DMA_IN_RST_CH4_S  0
+/** AHB_DMA_IN_LOOP_TEST_CH4 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_IN_LOOP_TEST_CH4    (BIT(1))
+#define AHB_DMA_IN_LOOP_TEST_CH4_M  (AHB_DMA_IN_LOOP_TEST_CH4_V << AHB_DMA_IN_LOOP_TEST_CH4_S)
+#define AHB_DMA_IN_LOOP_TEST_CH4_V  0x00000001U
+#define AHB_DMA_IN_LOOP_TEST_CH4_S  1
+/** AHB_DMA_INDSCR_BURST_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable INCR burst transfer for RX channel 4 to read
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INDSCR_BURST_EN_CH4    (BIT(2))
+#define AHB_DMA_INDSCR_BURST_EN_CH4_M  (AHB_DMA_INDSCR_BURST_EN_CH4_V << AHB_DMA_INDSCR_BURST_EN_CH4_S)
+#define AHB_DMA_INDSCR_BURST_EN_CH4_V  0x00000001U
+#define AHB_DMA_INDSCR_BURST_EN_CH4_S  2
+/** AHB_DMA_MEM_TRANS_EN_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable memory-to-memory data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_MEM_TRANS_EN_CH4    (BIT(4))
+#define AHB_DMA_MEM_TRANS_EN_CH4_M  (AHB_DMA_MEM_TRANS_EN_CH4_V << AHB_DMA_MEM_TRANS_EN_CH4_S)
+#define AHB_DMA_MEM_TRANS_EN_CH4_V  0x00000001U
+#define AHB_DMA_MEM_TRANS_EN_CH4_S  4
+/** AHB_DMA_IN_ETM_EN_CH4 : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable ETM control for RX channel4.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_ETM_EN_CH4    (BIT(5))
+#define AHB_DMA_IN_ETM_EN_CH4_M  (AHB_DMA_IN_ETM_EN_CH4_V << AHB_DMA_IN_ETM_EN_CH4_S)
+#define AHB_DMA_IN_ETM_EN_CH4_V  0x00000001U
+#define AHB_DMA_IN_ETM_EN_CH4_S  5
+/** AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4 : R/W; bitpos: [7:6]; default: 0;
+ *  Configures max burst size for Rx channel4.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4    0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4_M  (AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4_V << AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4_S)
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4_V  0x00000003U
+#define AHB_DMA_IN_DATA_BURST_MODE_SEL_CH4_S  6
+
+/** AHB_DMA_IN_CONF1_CH4_REG register
+ *  Configuration register 1 of RX channel 4
+ */
+#define AHB_DMA_IN_CONF1_CH4_REG (DR_REG_AHB_DMA_BASE + 0x504)
+/** AHB_DMA_IN_CHECK_OWNER_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for RX channel 4.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_IN_CHECK_OWNER_CH4    (BIT(12))
+#define AHB_DMA_IN_CHECK_OWNER_CH4_M  (AHB_DMA_IN_CHECK_OWNER_CH4_V << AHB_DMA_IN_CHECK_OWNER_CH4_S)
+#define AHB_DMA_IN_CHECK_OWNER_CH4_V  0x00000001U
+#define AHB_DMA_IN_CHECK_OWNER_CH4_S  12
+
+/** AHB_DMA_INFIFO_STATUS_CH4_REG register
+ *  Receive FIFO status of RX channel 4
+ */
+#define AHB_DMA_INFIFO_STATUS_CH4_REG (DR_REG_AHB_DMA_BASE + 0x508)
+/** AHB_DMA_INFIFO_FULL_CH4 : RO; bitpos: [0]; default: 1;
+ *  Represents whether L1 RX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_INFIFO_FULL_CH4    (BIT(0))
+#define AHB_DMA_INFIFO_FULL_CH4_M  (AHB_DMA_INFIFO_FULL_CH4_V << AHB_DMA_INFIFO_FULL_CH4_S)
+#define AHB_DMA_INFIFO_FULL_CH4_V  0x00000001U
+#define AHB_DMA_INFIFO_FULL_CH4_S  0
+/** AHB_DMA_INFIFO_EMPTY_CH4 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 RX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_INFIFO_EMPTY_CH4    (BIT(1))
+#define AHB_DMA_INFIFO_EMPTY_CH4_M  (AHB_DMA_INFIFO_EMPTY_CH4_V << AHB_DMA_INFIFO_EMPTY_CH4_S)
+#define AHB_DMA_INFIFO_EMPTY_CH4_V  0x00000001U
+#define AHB_DMA_INFIFO_EMPTY_CH4_S  1
+/** AHB_DMA_INFIFO_CNT_CH4 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 RX FIFO for RX channel 4.
+ */
+#define AHB_DMA_INFIFO_CNT_CH4    0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH4_M  (AHB_DMA_INFIFO_CNT_CH4_V << AHB_DMA_INFIFO_CNT_CH4_S)
+#define AHB_DMA_INFIFO_CNT_CH4_V  0x0000007FU
+#define AHB_DMA_INFIFO_CNT_CH4_S  8
+/** AHB_DMA_IN_REMAIN_UNDER_1B_CH4 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH4    (BIT(23))
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH4_M  (AHB_DMA_IN_REMAIN_UNDER_1B_CH4_V << AHB_DMA_IN_REMAIN_UNDER_1B_CH4_S)
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH4_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_1B_CH4_S  23
+/** AHB_DMA_IN_REMAIN_UNDER_2B_CH4 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH4    (BIT(24))
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH4_M  (AHB_DMA_IN_REMAIN_UNDER_2B_CH4_V << AHB_DMA_IN_REMAIN_UNDER_2B_CH4_S)
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH4_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_2B_CH4_S  24
+/** AHB_DMA_IN_REMAIN_UNDER_3B_CH4 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH4    (BIT(25))
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH4_M  (AHB_DMA_IN_REMAIN_UNDER_3B_CH4_V << AHB_DMA_IN_REMAIN_UNDER_3B_CH4_S)
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH4_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_3B_CH4_S  25
+/** AHB_DMA_IN_REMAIN_UNDER_4B_CH4 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH4    (BIT(26))
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH4_M  (AHB_DMA_IN_REMAIN_UNDER_4B_CH4_V << AHB_DMA_IN_REMAIN_UNDER_4B_CH4_S)
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH4_V  0x00000001U
+#define AHB_DMA_IN_REMAIN_UNDER_4B_CH4_S  26
+/** AHB_DMA_IN_BUF_HUNGRY_CH4 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_BUF_HUNGRY_CH4    (BIT(27))
+#define AHB_DMA_IN_BUF_HUNGRY_CH4_M  (AHB_DMA_IN_BUF_HUNGRY_CH4_V << AHB_DMA_IN_BUF_HUNGRY_CH4_S)
+#define AHB_DMA_IN_BUF_HUNGRY_CH4_V  0x00000001U
+#define AHB_DMA_IN_BUF_HUNGRY_CH4_S  27
+
+/** AHB_DMA_IN_POP_CH4_REG register
+ *  Pop control register of RX channel 4
+ */
+#define AHB_DMA_IN_POP_CH4_REG (DR_REG_AHB_DMA_BASE + 0x50c)
+/** AHB_DMA_INFIFO_RDATA_CH4 : RO; bitpos: [11:0]; default: 2048;
+ *  Represents the data popped from AHB_DMA FIFO.
+ */
+#define AHB_DMA_INFIFO_RDATA_CH4    0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH4_M  (AHB_DMA_INFIFO_RDATA_CH4_V << AHB_DMA_INFIFO_RDATA_CH4_S)
+#define AHB_DMA_INFIFO_RDATA_CH4_V  0x00000FFFU
+#define AHB_DMA_INFIFO_RDATA_CH4_S  0
+/** AHB_DMA_INFIFO_POP_CH4 : WT; bitpos: [12]; default: 0;
+ *  Configures whether to pop data from AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Pop
+ */
+#define AHB_DMA_INFIFO_POP_CH4    (BIT(12))
+#define AHB_DMA_INFIFO_POP_CH4_M  (AHB_DMA_INFIFO_POP_CH4_V << AHB_DMA_INFIFO_POP_CH4_S)
+#define AHB_DMA_INFIFO_POP_CH4_V  0x00000001U
+#define AHB_DMA_INFIFO_POP_CH4_S  12
+
+/** AHB_DMA_IN_LINK_CH4_REG register
+ *  Linked list descriptor configuration and control register of RX channel 4
+ */
+#define AHB_DMA_IN_LINK_CH4_REG (DR_REG_AHB_DMA_BASE + 0x510)
+/** AHB_DMA_INLINK_AUTO_RET_CH4 : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to return to current receive descriptor's address when there are
+ *  some errors in current receiving data.
+ *  0: Not return
+ *  1: Return
+ */
+#define AHB_DMA_INLINK_AUTO_RET_CH4    (BIT(0))
+#define AHB_DMA_INLINK_AUTO_RET_CH4_M  (AHB_DMA_INLINK_AUTO_RET_CH4_V << AHB_DMA_INLINK_AUTO_RET_CH4_S)
+#define AHB_DMA_INLINK_AUTO_RET_CH4_V  0x00000001U
+#define AHB_DMA_INLINK_AUTO_RET_CH4_S  0
+/** AHB_DMA_INLINK_STOP_CH4 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to stop AHB_DMA's RX channel 4 from receiving data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_INLINK_STOP_CH4    (BIT(1))
+#define AHB_DMA_INLINK_STOP_CH4_M  (AHB_DMA_INLINK_STOP_CH4_V << AHB_DMA_INLINK_STOP_CH4_S)
+#define AHB_DMA_INLINK_STOP_CH4_V  0x00000001U
+#define AHB_DMA_INLINK_STOP_CH4_S  1
+/** AHB_DMA_INLINK_START_CH4 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to enable AHB_DMA's RX channel 4 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_INLINK_START_CH4    (BIT(2))
+#define AHB_DMA_INLINK_START_CH4_M  (AHB_DMA_INLINK_START_CH4_V << AHB_DMA_INLINK_START_CH4_S)
+#define AHB_DMA_INLINK_START_CH4_V  0x00000001U
+#define AHB_DMA_INLINK_START_CH4_S  2
+/** AHB_DMA_INLINK_RESTART_CH4 : WT; bitpos: [3]; default: 0;
+ *  Configures whether to restart RX channel 4 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_INLINK_RESTART_CH4    (BIT(3))
+#define AHB_DMA_INLINK_RESTART_CH4_M  (AHB_DMA_INLINK_RESTART_CH4_V << AHB_DMA_INLINK_RESTART_CH4_S)
+#define AHB_DMA_INLINK_RESTART_CH4_V  0x00000001U
+#define AHB_DMA_INLINK_RESTART_CH4_S  3
+/** AHB_DMA_INLINK_PARK_CH4 : RO; bitpos: [4]; default: 1;
+ *  Represents the status of the receive descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_INLINK_PARK_CH4    (BIT(4))
+#define AHB_DMA_INLINK_PARK_CH4_M  (AHB_DMA_INLINK_PARK_CH4_V << AHB_DMA_INLINK_PARK_CH4_S)
+#define AHB_DMA_INLINK_PARK_CH4_V  0x00000001U
+#define AHB_DMA_INLINK_PARK_CH4_S  4
+
+/** AHB_DMA_IN_LINK_ADDR_CH4_REG register
+ *  Link list descriptor address configuration of RX channel 4
+ */
+#define AHB_DMA_IN_LINK_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x514)
+/** AHB_DMA_INLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_INLINK_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH4_M  (AHB_DMA_INLINK_ADDR_CH4_V << AHB_DMA_INLINK_ADDR_CH4_S)
+#define AHB_DMA_INLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_ADDR_CH4_S  0
+
+/** AHB_DMA_IN_STATE_CH4_REG register
+ *  Receive status of RX channel 4
+ */
+#define AHB_DMA_IN_STATE_CH4_REG (DR_REG_AHB_DMA_BASE + 0x518)
+/** AHB_DMA_INLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the address of the lower 18 bits of the next receive descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_INLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH4_M  (AHB_DMA_INLINK_DSCR_ADDR_CH4_V << AHB_DMA_INLINK_DSCR_ADDR_CH4_S)
+#define AHB_DMA_INLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define AHB_DMA_INLINK_DSCR_ADDR_CH4_S  0
+/** AHB_DMA_IN_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_DSCR_STATE_CH4    0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH4_M  (AHB_DMA_IN_DSCR_STATE_CH4_V << AHB_DMA_IN_DSCR_STATE_CH4_S)
+#define AHB_DMA_IN_DSCR_STATE_CH4_V  0x00000003U
+#define AHB_DMA_IN_DSCR_STATE_CH4_S  18
+/** AHB_DMA_IN_STATE_CH4 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_IN_STATE_CH4    0x00000007U
+#define AHB_DMA_IN_STATE_CH4_M  (AHB_DMA_IN_STATE_CH4_V << AHB_DMA_IN_STATE_CH4_S)
+#define AHB_DMA_IN_STATE_CH4_V  0x00000007U
+#define AHB_DMA_IN_STATE_CH4_S  20
+
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG register
+ *  Receive descriptor address when EOF occurs on RX channel 4
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x51c)
+/** AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_M  (AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_V << AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_S)
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_IN_SUC_EOF_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG register
+ *  Receive descriptor address when errors occur of RX channel 4
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x520)
+/** AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the receive descriptor when there are some errors in the
+ *  currently received data.
+ */
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_M  (AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_V << AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_S)
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_IN_ERR_EOF_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_IN_DONE_DES_ADDR_CH4_REG register
+ *  RX_done inlink descriptor address of RX channel 4
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x524)
+/** AHB_DMA_IN_DONE_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the inlink descriptor when  this descriptor is completed .
+ */
+#define AHB_DMA_IN_DONE_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH4_M  (AHB_DMA_IN_DONE_DES_ADDR_CH4_V << AHB_DMA_IN_DONE_DES_ADDR_CH4_S)
+#define AHB_DMA_IN_DONE_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_IN_DONE_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_IN_DSCR_CH4_REG register
+ *  Current receive descriptor address of RX channel 4
+ */
+#define AHB_DMA_IN_DSCR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x528)
+/** AHB_DMA_INLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next receive descriptor x+1 pointed by the current
+ *  receive descriptor that has already been fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_CH4    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH4_M  (AHB_DMA_INLINK_DSCR_CH4_V << AHB_DMA_INLINK_DSCR_CH4_S)
+#define AHB_DMA_INLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_CH4_S  0
+
+/** AHB_DMA_IN_DSCR_BF0_CH4_REG register
+ *  The last receive descriptor address of RX channel 4
+ */
+#define AHB_DMA_IN_DSCR_BF0_CH4_REG (DR_REG_AHB_DMA_BASE + 0x52c)
+/** AHB_DMA_INLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current receive descriptor x that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH4_M  (AHB_DMA_INLINK_DSCR_BF0_CH4_V << AHB_DMA_INLINK_DSCR_BF0_CH4_S)
+#define AHB_DMA_INLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF0_CH4_S  0
+
+/** AHB_DMA_IN_DSCR_BF1_CH4_REG register
+ *  The second-to-last receive descriptor address of RX channel 4
+ */
+#define AHB_DMA_IN_DSCR_BF1_CH4_REG (DR_REG_AHB_DMA_BASE + 0x530)
+/** AHB_DMA_INLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous receive descriptor x-1 that has already been
+ *  fetched.
+ */
+#define AHB_DMA_INLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH4_M  (AHB_DMA_INLINK_DSCR_BF1_CH4_V << AHB_DMA_INLINK_DSCR_BF1_CH4_S)
+#define AHB_DMA_INLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_INLINK_DSCR_BF1_CH4_S  0
+
+/** AHB_DMA_IN_PRI_CH4_REG register
+ *  Priority register of RX channel 4
+ */
+#define AHB_DMA_IN_PRI_CH4_REG (DR_REG_AHB_DMA_BASE + 0x534)
+/** AHB_DMA_RX_PRI_CH4 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of RX channel 4.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_RX_PRI_CH4    0x0000000FU
+#define AHB_DMA_RX_PRI_CH4_M  (AHB_DMA_RX_PRI_CH4_V << AHB_DMA_RX_PRI_CH4_S)
+#define AHB_DMA_RX_PRI_CH4_V  0x0000000FU
+#define AHB_DMA_RX_PRI_CH4_S  0
+
+/** AHB_DMA_IN_PERI_SEL_CH4_REG register
+ *  Peripheral selection register of RX channel 4
+ */
+#define AHB_DMA_IN_PERI_SEL_CH4_REG (DR_REG_AHB_DMA_BASE + 0x538)
+/** AHB_DMA_PERI_IN_SEL_CH4 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to RX channel 4.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_IN_SEL_CH4    0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH4_M  (AHB_DMA_PERI_IN_SEL_CH4_V << AHB_DMA_PERI_IN_SEL_CH4_S)
+#define AHB_DMA_PERI_IN_SEL_CH4_V  0x0000003FU
+#define AHB_DMA_PERI_IN_SEL_CH4_S  0
+
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG register
+ *  RX channel 4 arbitration weight configuration register
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH4_REG (DR_REG_AHB_DMA_BASE + 0x53c)
+/** AHB_DMA_RX_CH_ARB_WEIGH_CH4 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of RX channel4
+ */
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH4    0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH4_M  (AHB_DMA_RX_CH_ARB_WEIGH_CH4_V << AHB_DMA_RX_CH_ARB_WEIGH_CH4_S)
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH4_V  0x0000000FU
+#define AHB_DMA_RX_CH_ARB_WEIGH_CH4_S  0
+
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG register
+ *  RX channel 4 weight arbitration optimization enable register
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x540)
+/** AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4    (BIT(0))
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_M  (AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_V << AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_S)
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_V  0x00000001U
+#define AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH4_S  0
+
+/** AHB_DMA_OUT_CONF0_CH4_REG register
+ *  Configuration register 0 of TX channel 4
+ */
+#define AHB_DMA_OUT_CONF0_CH4_REG (DR_REG_AHB_DMA_BASE + 0x580)
+/** AHB_DMA_OUT_RST_CH4 : R/W; bitpos: [0]; default: 0;
+ *  Configures the reset state of AHB_DMA channel 4 TX FSM and TX FIFO pointer.
+ *  0: Release reset
+ *  1: Reset
+ */
+#define AHB_DMA_OUT_RST_CH4    (BIT(0))
+#define AHB_DMA_OUT_RST_CH4_M  (AHB_DMA_OUT_RST_CH4_V << AHB_DMA_OUT_RST_CH4_S)
+#define AHB_DMA_OUT_RST_CH4_V  0x00000001U
+#define AHB_DMA_OUT_RST_CH4_S  0
+/** AHB_DMA_OUT_LOOP_TEST_CH4 : R/W; bitpos: [1]; default: 0;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_LOOP_TEST_CH4    (BIT(1))
+#define AHB_DMA_OUT_LOOP_TEST_CH4_M  (AHB_DMA_OUT_LOOP_TEST_CH4_V << AHB_DMA_OUT_LOOP_TEST_CH4_S)
+#define AHB_DMA_OUT_LOOP_TEST_CH4_V  0x00000001U
+#define AHB_DMA_OUT_LOOP_TEST_CH4_S  1
+/** AHB_DMA_OUT_AUTO_WRBACK_CH4 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to enable automatic outlink write-back when all the data in TX
+ *  FIFO has been transmitted.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_AUTO_WRBACK_CH4    (BIT(2))
+#define AHB_DMA_OUT_AUTO_WRBACK_CH4_M  (AHB_DMA_OUT_AUTO_WRBACK_CH4_V << AHB_DMA_OUT_AUTO_WRBACK_CH4_S)
+#define AHB_DMA_OUT_AUTO_WRBACK_CH4_V  0x00000001U
+#define AHB_DMA_OUT_AUTO_WRBACK_CH4_S  2
+/** AHB_DMA_OUT_EOF_MODE_CH4 : R/W; bitpos: [3]; default: 1;
+ *  Configures when to generate EOF flag.
+ *  0: EOF flag for TX channel 4 is generated when data to be transmitted has been
+ *  pushed into FIFO in AHB_DMA.
+ *  1: EOF flag for TX channel 4 is generated when data to be transmitted has been
+ *  popped from FIFO in AHB_DMA.
+ */
+#define AHB_DMA_OUT_EOF_MODE_CH4    (BIT(3))
+#define AHB_DMA_OUT_EOF_MODE_CH4_M  (AHB_DMA_OUT_EOF_MODE_CH4_V << AHB_DMA_OUT_EOF_MODE_CH4_S)
+#define AHB_DMA_OUT_EOF_MODE_CH4_V  0x00000001U
+#define AHB_DMA_OUT_EOF_MODE_CH4_S  3
+/** AHB_DMA_OUTDSCR_BURST_EN_CH4 : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable INCR burst transfer for TX channel 4 reading
+ *  descriptors.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTDSCR_BURST_EN_CH4    (BIT(4))
+#define AHB_DMA_OUTDSCR_BURST_EN_CH4_M  (AHB_DMA_OUTDSCR_BURST_EN_CH4_V << AHB_DMA_OUTDSCR_BURST_EN_CH4_S)
+#define AHB_DMA_OUTDSCR_BURST_EN_CH4_V  0x00000001U
+#define AHB_DMA_OUTDSCR_BURST_EN_CH4_S  4
+/** AHB_DMA_OUT_ETM_EN_CH4 : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to enable ETM control for TX channel 4.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_ETM_EN_CH4    (BIT(6))
+#define AHB_DMA_OUT_ETM_EN_CH4_M  (AHB_DMA_OUT_ETM_EN_CH4_V << AHB_DMA_OUT_ETM_EN_CH4_S)
+#define AHB_DMA_OUT_ETM_EN_CH4_V  0x00000001U
+#define AHB_DMA_OUT_ETM_EN_CH4_S  6
+/** AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4 : R/W; bitpos: [9:8]; default: 0;
+ *  Configures max burst size for TX channel4.
+ *  2'b00: single
+ *  2'b01: incr4
+ *  2'b10: incr8
+ *  2'b11: incr16
+ */
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4    0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4_M  (AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4_V << AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4_S)
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4_V  0x00000003U
+#define AHB_DMA_OUT_DATA_BURST_MODE_SEL_CH4_S  8
+
+/** AHB_DMA_OUT_CONF1_CH4_REG register
+ *  Configuration register 1 of TX channel 4
+ */
+#define AHB_DMA_OUT_CONF1_CH4_REG (DR_REG_AHB_DMA_BASE + 0x584)
+/** AHB_DMA_OUT_CHECK_OWNER_CH4 : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable owner bit check for TX channel 4.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUT_CHECK_OWNER_CH4    (BIT(12))
+#define AHB_DMA_OUT_CHECK_OWNER_CH4_M  (AHB_DMA_OUT_CHECK_OWNER_CH4_V << AHB_DMA_OUT_CHECK_OWNER_CH4_S)
+#define AHB_DMA_OUT_CHECK_OWNER_CH4_V  0x00000001U
+#define AHB_DMA_OUT_CHECK_OWNER_CH4_S  12
+
+/** AHB_DMA_OUTFIFO_STATUS_CH4_REG register
+ *  Transmit FIFO status of TX channel 4
+ */
+#define AHB_DMA_OUTFIFO_STATUS_CH4_REG (DR_REG_AHB_DMA_BASE + 0x588)
+/** AHB_DMA_OUTFIFO_FULL_CH4 : RO; bitpos: [0]; default: 0;
+ *  Represents whether L1 TX FIFO is full.
+ *  0: Not Full
+ *  1: Full
+ */
+#define AHB_DMA_OUTFIFO_FULL_CH4    (BIT(0))
+#define AHB_DMA_OUTFIFO_FULL_CH4_M  (AHB_DMA_OUTFIFO_FULL_CH4_V << AHB_DMA_OUTFIFO_FULL_CH4_S)
+#define AHB_DMA_OUTFIFO_FULL_CH4_V  0x00000001U
+#define AHB_DMA_OUTFIFO_FULL_CH4_S  0
+/** AHB_DMA_OUTFIFO_EMPTY_CH4 : RO; bitpos: [1]; default: 1;
+ *  Represents whether L1 TX FIFO is empty.
+ *  0: Not empty
+ *  1: Empty
+ */
+#define AHB_DMA_OUTFIFO_EMPTY_CH4    (BIT(1))
+#define AHB_DMA_OUTFIFO_EMPTY_CH4_M  (AHB_DMA_OUTFIFO_EMPTY_CH4_V << AHB_DMA_OUTFIFO_EMPTY_CH4_S)
+#define AHB_DMA_OUTFIFO_EMPTY_CH4_V  0x00000001U
+#define AHB_DMA_OUTFIFO_EMPTY_CH4_S  1
+/** AHB_DMA_OUTFIFO_CNT_CH4 : RO; bitpos: [14:8]; default: 0;
+ *  Represents the number of data bytes in L1 TX FIFO for TX channel 4.
+ */
+#define AHB_DMA_OUTFIFO_CNT_CH4    0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH4_M  (AHB_DMA_OUTFIFO_CNT_CH4_V << AHB_DMA_OUTFIFO_CNT_CH4_S)
+#define AHB_DMA_OUTFIFO_CNT_CH4_V  0x0000007FU
+#define AHB_DMA_OUTFIFO_CNT_CH4_S  8
+/** AHB_DMA_OUT_REMAIN_UNDER_1B_CH4 : RO; bitpos: [23]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH4    (BIT(23))
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH4_M  (AHB_DMA_OUT_REMAIN_UNDER_1B_CH4_V << AHB_DMA_OUT_REMAIN_UNDER_1B_CH4_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH4_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_1B_CH4_S  23
+/** AHB_DMA_OUT_REMAIN_UNDER_2B_CH4 : RO; bitpos: [24]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH4    (BIT(24))
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH4_M  (AHB_DMA_OUT_REMAIN_UNDER_2B_CH4_V << AHB_DMA_OUT_REMAIN_UNDER_2B_CH4_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH4_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_2B_CH4_S  24
+/** AHB_DMA_OUT_REMAIN_UNDER_3B_CH4 : RO; bitpos: [25]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH4    (BIT(25))
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH4_M  (AHB_DMA_OUT_REMAIN_UNDER_3B_CH4_V << AHB_DMA_OUT_REMAIN_UNDER_3B_CH4_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH4_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_3B_CH4_S  25
+/** AHB_DMA_OUT_REMAIN_UNDER_4B_CH4 : RO; bitpos: [26]; default: 1;
+ *  Reserved.
+ */
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH4    (BIT(26))
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH4_M  (AHB_DMA_OUT_REMAIN_UNDER_4B_CH4_V << AHB_DMA_OUT_REMAIN_UNDER_4B_CH4_S)
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH4_V  0x00000001U
+#define AHB_DMA_OUT_REMAIN_UNDER_4B_CH4_S  26
+
+/** AHB_DMA_OUT_PUSH_CH4_REG register
+ *  Push control register of TX channel 4
+ */
+#define AHB_DMA_OUT_PUSH_CH4_REG (DR_REG_AHB_DMA_BASE + 0x58c)
+/** AHB_DMA_OUTFIFO_WDATA_CH4 : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the data that need to be pushed into AHB_DMA FIFO.
+ */
+#define AHB_DMA_OUTFIFO_WDATA_CH4    0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH4_M  (AHB_DMA_OUTFIFO_WDATA_CH4_V << AHB_DMA_OUTFIFO_WDATA_CH4_S)
+#define AHB_DMA_OUTFIFO_WDATA_CH4_V  0x000001FFU
+#define AHB_DMA_OUTFIFO_WDATA_CH4_S  0
+/** AHB_DMA_OUTFIFO_PUSH_CH4 : WT; bitpos: [9]; default: 0;
+ *  Configures whether to push data into AHB_DMA FIFO.
+ *  0: Invalid. No effect
+ *  1: Push
+ */
+#define AHB_DMA_OUTFIFO_PUSH_CH4    (BIT(9))
+#define AHB_DMA_OUTFIFO_PUSH_CH4_M  (AHB_DMA_OUTFIFO_PUSH_CH4_V << AHB_DMA_OUTFIFO_PUSH_CH4_S)
+#define AHB_DMA_OUTFIFO_PUSH_CH4_V  0x00000001U
+#define AHB_DMA_OUTFIFO_PUSH_CH4_S  9
+
+/** AHB_DMA_OUT_LINK_CH4_REG register
+ *  Linked list descriptor configuration and control register of TX channel 4
+ */
+#define AHB_DMA_OUT_LINK_CH4_REG (DR_REG_AHB_DMA_BASE + 0x590)
+/** AHB_DMA_OUTLINK_STOP_CH4 : WT; bitpos: [0]; default: 0;
+ *  Configures whether to stop AHB_DMA's TX channel 4 from transmitting data.
+ *  0: Invalid. No effect
+ *  1: Stop
+ */
+#define AHB_DMA_OUTLINK_STOP_CH4    (BIT(0))
+#define AHB_DMA_OUTLINK_STOP_CH4_M  (AHB_DMA_OUTLINK_STOP_CH4_V << AHB_DMA_OUTLINK_STOP_CH4_S)
+#define AHB_DMA_OUTLINK_STOP_CH4_V  0x00000001U
+#define AHB_DMA_OUTLINK_STOP_CH4_S  0
+/** AHB_DMA_OUTLINK_START_CH4 : WT; bitpos: [1]; default: 0;
+ *  Configures whether to enable AHB_DMA's TX channel 4 for data transfer.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_OUTLINK_START_CH4    (BIT(1))
+#define AHB_DMA_OUTLINK_START_CH4_M  (AHB_DMA_OUTLINK_START_CH4_V << AHB_DMA_OUTLINK_START_CH4_S)
+#define AHB_DMA_OUTLINK_START_CH4_V  0x00000001U
+#define AHB_DMA_OUTLINK_START_CH4_S  1
+/** AHB_DMA_OUTLINK_RESTART_CH4 : WT; bitpos: [2]; default: 0;
+ *  Configures whether to restart TX channel 4 for AHB_DMA transfer.
+ *  0: Invalid. No effect
+ *  1: Restart
+ */
+#define AHB_DMA_OUTLINK_RESTART_CH4    (BIT(2))
+#define AHB_DMA_OUTLINK_RESTART_CH4_M  (AHB_DMA_OUTLINK_RESTART_CH4_V << AHB_DMA_OUTLINK_RESTART_CH4_S)
+#define AHB_DMA_OUTLINK_RESTART_CH4_V  0x00000001U
+#define AHB_DMA_OUTLINK_RESTART_CH4_S  2
+/** AHB_DMA_OUTLINK_PARK_CH4 : RO; bitpos: [3]; default: 1;
+ *  Represents the status of the transmit descriptor's FSM.
+ *  0: Running
+ *  1: Idle
+ */
+#define AHB_DMA_OUTLINK_PARK_CH4    (BIT(3))
+#define AHB_DMA_OUTLINK_PARK_CH4_M  (AHB_DMA_OUTLINK_PARK_CH4_V << AHB_DMA_OUTLINK_PARK_CH4_S)
+#define AHB_DMA_OUTLINK_PARK_CH4_V  0x00000001U
+#define AHB_DMA_OUTLINK_PARK_CH4_S  3
+
+/** AHB_DMA_OUT_LINK_ADDR_CH4_REG register
+ *  Link list descriptor address configuration of TX channel 4
+ */
+#define AHB_DMA_OUT_LINK_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x594)
+/** AHB_DMA_OUTLINK_ADDR_CH4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 32 bits of the first receive descriptor's address.
+ */
+#define AHB_DMA_OUTLINK_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH4_M  (AHB_DMA_OUTLINK_ADDR_CH4_V << AHB_DMA_OUTLINK_ADDR_CH4_S)
+#define AHB_DMA_OUTLINK_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_ADDR_CH4_S  0
+
+/** AHB_DMA_OUT_STATE_CH4_REG register
+ *  Transmit status of TX channel 4
+ */
+#define AHB_DMA_OUT_STATE_CH4_REG (DR_REG_AHB_DMA_BASE + 0x598)
+/** AHB_DMA_OUTLINK_DSCR_ADDR_CH4 : RO; bitpos: [17:0]; default: 0;
+ *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+ *  processed.
+ */
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH4    0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH4_M  (AHB_DMA_OUTLINK_DSCR_ADDR_CH4_V << AHB_DMA_OUTLINK_DSCR_ADDR_CH4_S)
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH4_V  0x0003FFFFU
+#define AHB_DMA_OUTLINK_DSCR_ADDR_CH4_S  0
+/** AHB_DMA_OUT_DSCR_STATE_CH4 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_DSCR_STATE_CH4    0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH4_M  (AHB_DMA_OUT_DSCR_STATE_CH4_V << AHB_DMA_OUT_DSCR_STATE_CH4_S)
+#define AHB_DMA_OUT_DSCR_STATE_CH4_V  0x00000003U
+#define AHB_DMA_OUT_DSCR_STATE_CH4_S  18
+/** AHB_DMA_OUT_STATE_CH4 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_OUT_STATE_CH4    0x00000007U
+#define AHB_DMA_OUT_STATE_CH4_M  (AHB_DMA_OUT_STATE_CH4_V << AHB_DMA_OUT_STATE_CH4_S)
+#define AHB_DMA_OUT_STATE_CH4_V  0x00000007U
+#define AHB_DMA_OUT_STATE_CH4_S  20
+
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH4_REG register
+ *  Transmit descriptor address when EOF occurs on TX channel 4
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x59c)
+/** AHB_DMA_OUT_EOF_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH4_M  (AHB_DMA_OUT_EOF_DES_ADDR_CH4_V << AHB_DMA_OUT_EOF_DES_ADDR_CH4_S)
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_REG register
+ *  The last transmit descriptor address when EOF occurs on TX channel 4
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5a0)
+/** AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the transmit descriptor before the last transmit
+ *  descriptor.
+ */
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_M  (AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_V << AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_S)
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_EOF_BFR_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH4_REG register
+ *  TX done outlink descriptor address of TX channel 4
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5a4)
+/** AHB_DMA_OUT_DONE_DES_ADDR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the outlink descriptor when this descriptor is completed.
+ */
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH4_M  (AHB_DMA_OUT_DONE_DES_ADDR_CH4_V << AHB_DMA_OUT_DONE_DES_ADDR_CH4_S)
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUT_DONE_DES_ADDR_CH4_S  0
+
+/** AHB_DMA_OUT_DSCR_CH4_REG register
+ *  Current transmit descriptor address of TX channel 4
+ */
+#define AHB_DMA_OUT_DSCR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5a8)
+/** AHB_DMA_OUTLINK_DSCR_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the next transmit descriptor y+1 pointed by the current
+ *  transmit descriptor that has already been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH4_M  (AHB_DMA_OUTLINK_DSCR_CH4_V << AHB_DMA_OUTLINK_DSCR_CH4_S)
+#define AHB_DMA_OUTLINK_DSCR_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_CH4_S  0
+
+/** AHB_DMA_OUT_DSCR_BF0_CH4_REG register
+ *  The last transmit descriptor address of TX channel 4
+ */
+#define AHB_DMA_OUT_DSCR_BF0_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5ac)
+/** AHB_DMA_OUTLINK_DSCR_BF0_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the current transmit descriptor y that has already been
+ *  fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH4_M  (AHB_DMA_OUTLINK_DSCR_BF0_CH4_V << AHB_DMA_OUTLINK_DSCR_BF0_CH4_S)
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF0_CH4_S  0
+
+/** AHB_DMA_OUT_DSCR_BF1_CH4_REG register
+ *  The second-to-last transmit descriptor address of TX channel 4
+ */
+#define AHB_DMA_OUT_DSCR_BF1_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5b0)
+/** AHB_DMA_OUTLINK_DSCR_BF1_CH4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the previous transmit descriptor y-1 that has already
+ *  been fetched.
+ */
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH4    0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH4_M  (AHB_DMA_OUTLINK_DSCR_BF1_CH4_V << AHB_DMA_OUTLINK_DSCR_BF1_CH4_S)
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH4_V  0xFFFFFFFFU
+#define AHB_DMA_OUTLINK_DSCR_BF1_CH4_S  0
+
+/** AHB_DMA_OUT_PRI_CH4_REG register
+ *  Priority register of TX channel 4
+ */
+#define AHB_DMA_OUT_PRI_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5b4)
+/** AHB_DMA_TX_PRI_CH4 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the priority of TX channel 4.The larger of the value, the higher of the
+ *  priority.
+ */
+#define AHB_DMA_TX_PRI_CH4    0x0000000FU
+#define AHB_DMA_TX_PRI_CH4_M  (AHB_DMA_TX_PRI_CH4_V << AHB_DMA_TX_PRI_CH4_S)
+#define AHB_DMA_TX_PRI_CH4_V  0x0000000FU
+#define AHB_DMA_TX_PRI_CH4_S  0
+
+/** AHB_DMA_OUT_PERI_SEL_CH4_REG register
+ *  Peripheral selection register of TX channel 4
+ */
+#define AHB_DMA_OUT_PERI_SEL_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5b8)
+/** AHB_DMA_PERI_OUT_SEL_CH4 : R/W; bitpos: [5:0]; default: 63;
+ *  Configures the peripheral connected to TX channel 4.
+ *  0: UHCI0
+ *  1: I2S0-0
+ *  2: I2S0-1
+ *  3: I2S0-2
+ *  4: I2S0-3
+ *  5: I2S1-0
+ *  6: I2S1-1
+ *  7: I2S1-2
+ *  8: I2S1-3
+ *  9: ADC_DAC
+ *  10: RMT
+ *  11: Sample_rate_convert-0
+ *  12: Sample_rate_convert-1
+ *  13: Cordic
+ *  14: PVT0
+ *  15: DUMMY
+ */
+#define AHB_DMA_PERI_OUT_SEL_CH4    0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH4_M  (AHB_DMA_PERI_OUT_SEL_CH4_V << AHB_DMA_PERI_OUT_SEL_CH4_S)
+#define AHB_DMA_PERI_OUT_SEL_CH4_V  0x0000003FU
+#define AHB_DMA_PERI_OUT_SEL_CH4_S  0
+
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG register
+ *  TX channel 4 arbitration weight configuration register
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5bc)
+/** AHB_DMA_TX_CH_ARB_WEIGH_CH4 : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the weight(i.e the number of tokens) of TX channel4
+ */
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH4    0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH4_M  (AHB_DMA_TX_CH_ARB_WEIGH_CH4_V << AHB_DMA_TX_CH_ARB_WEIGH_CH4_S)
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH4_V  0x0000000FU
+#define AHB_DMA_TX_CH_ARB_WEIGH_CH4_S  0
+
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG register
+ *  TX channel 4 weight arbitration optimization enable register
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_REG (DR_REG_AHB_DMA_BASE + 0x5c0)
+/** AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4 : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4    (BIT(0))
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_M  (AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_V << AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_S)
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_V  0x00000001U
+#define AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH4_S  0
+
+/** AHB_DMA_INTR_MEM_START_ADDR_REG register
+ *  Accessible address space start address configuration register
+ */
+#define AHB_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x600)
+/** AHB_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of accessible address space.
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AHB_DMA_INTR_MEM_END_ADDR_REG register
+ *  Accessible address space end address configuration register
+ */
+#define AHB_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AHB_DMA_BASE + 0x604)
+/** AHB_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the end address of accessible address space.
+ */
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V << AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AHB_DMA_ARB_TIMEOUT_REG register
+ *  TX arbitration timeout configuration register
+ */
+#define AHB_DMA_ARB_TIMEOUT_REG (DR_REG_AHB_DMA_BASE + 0x608)
+/** AHB_DMA_ARB_TIMEOUT : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+ */
+#define AHB_DMA_ARB_TIMEOUT    0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_M  (AHB_DMA_ARB_TIMEOUT_V << AHB_DMA_ARB_TIMEOUT_S)
+#define AHB_DMA_ARB_TIMEOUT_V  0x0000FFFFU
+#define AHB_DMA_ARB_TIMEOUT_S  0
+
+/** AHB_DMA_WEIGHT_EN_REG register
+ *  TX weight arbitration enable register
+ */
+#define AHB_DMA_WEIGHT_EN_REG (DR_REG_AHB_DMA_BASE + 0x610)
+/** AHB_DMA_WEIGHT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable weight arbitration.
+ *  0: Disable
+ *  1: Enable
+ */
+#define AHB_DMA_WEIGHT_EN    (BIT(0))
+#define AHB_DMA_WEIGHT_EN_M  (AHB_DMA_WEIGHT_EN_V << AHB_DMA_WEIGHT_EN_S)
+#define AHB_DMA_WEIGHT_EN_V  0x00000001U
+#define AHB_DMA_WEIGHT_EN_S  0
+
+/** AHB_DMA_MODULE_CLK_EN_REG register
+ *  Module clock force on register
+ */
+#define AHB_DMA_MODULE_CLK_EN_REG (DR_REG_AHB_DMA_BASE + 0x618)
+/** AHB_DMA_AHB_APB_SYNC_CLK_EN : R/W; bitpos: [4:0]; default: 31;
+ *  Configures whether to force on ahb_apb_sync 4~0 module clock. For bit n:
+ *  0 : Not force on ahb_apb_sync n clock
+ *  1 : Force on ahb_apb_sync n clock
+ */
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN    0x0000001FU
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_M  (AHB_DMA_AHB_APB_SYNC_CLK_EN_V << AHB_DMA_AHB_APB_SYNC_CLK_EN_S)
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_V  0x0000001FU
+#define AHB_DMA_AHB_APB_SYNC_CLK_EN_S  0
+/** AHB_DMA_OUT_DSCR_CLK_EN : R/W; bitpos: [9:5]; default: 31;
+ *  Configures whether to force on out_dscr 4~0 module clock. For bit n:
+ *  0 : Not force on out_dscr n clock
+ *  1 : Force on out_dscr n clock
+ */
+#define AHB_DMA_OUT_DSCR_CLK_EN    0x0000001FU
+#define AHB_DMA_OUT_DSCR_CLK_EN_M  (AHB_DMA_OUT_DSCR_CLK_EN_V << AHB_DMA_OUT_DSCR_CLK_EN_S)
+#define AHB_DMA_OUT_DSCR_CLK_EN_V  0x0000001FU
+#define AHB_DMA_OUT_DSCR_CLK_EN_S  5
+/** AHB_DMA_OUT_CTRL_CLK_EN : R/W; bitpos: [14:10]; default: 31;
+ *  Configures whether to force on out_ctrl 4~0 module clock. For bit n:
+ *  0 : Not force on out_ctrl n clock
+ *  1 : Force on out_ctrl n clock
+ */
+#define AHB_DMA_OUT_CTRL_CLK_EN    0x0000001FU
+#define AHB_DMA_OUT_CTRL_CLK_EN_M  (AHB_DMA_OUT_CTRL_CLK_EN_V << AHB_DMA_OUT_CTRL_CLK_EN_S)
+#define AHB_DMA_OUT_CTRL_CLK_EN_V  0x0000001FU
+#define AHB_DMA_OUT_CTRL_CLK_EN_S  10
+/** AHB_DMA_IN_DSCR_CLK_EN : R/W; bitpos: [19:15]; default: 31;
+ *  Configures whether to force on in_dscr 4~0 module clock. For bit n:
+ *  0 : Not force on in_dscr n clock
+ *  1 : Force on in_dscr n clock
+ */
+#define AHB_DMA_IN_DSCR_CLK_EN    0x0000001FU
+#define AHB_DMA_IN_DSCR_CLK_EN_M  (AHB_DMA_IN_DSCR_CLK_EN_V << AHB_DMA_IN_DSCR_CLK_EN_S)
+#define AHB_DMA_IN_DSCR_CLK_EN_V  0x0000001FU
+#define AHB_DMA_IN_DSCR_CLK_EN_S  15
+/** AHB_DMA_IN_CTRL_CLK_EN : R/W; bitpos: [24:20]; default: 31;
+ *  Configures whether to force on in_ctrl 4~0 module clock. For bit n:
+ *  0 : Not force on in_ctrl n clock
+ *  1 : Force on in_ctrl n clock
+ */
+#define AHB_DMA_IN_CTRL_CLK_EN    0x0000001FU
+#define AHB_DMA_IN_CTRL_CLK_EN_M  (AHB_DMA_IN_CTRL_CLK_EN_V << AHB_DMA_IN_CTRL_CLK_EN_S)
+#define AHB_DMA_IN_CTRL_CLK_EN_V  0x0000001FU
+#define AHB_DMA_IN_CTRL_CLK_EN_S  20
+/** AHB_DMA_CMD_ARB_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Configures whether to force on cmd_arb module clock.
+ *  0 : Not force on cmd_arb clock
+ *  1 : Force on cmd_arb clock
+ */
+#define AHB_DMA_CMD_ARB_CLK_EN    (BIT(27))
+#define AHB_DMA_CMD_ARB_CLK_EN_M  (AHB_DMA_CMD_ARB_CLK_EN_V << AHB_DMA_CMD_ARB_CLK_EN_S)
+#define AHB_DMA_CMD_ARB_CLK_EN_V  0x00000001U
+#define AHB_DMA_CMD_ARB_CLK_EN_S  27
+/** AHB_DMA_AHBINF_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Configures whether to force on ahbinf module clock.
+ *  0 : Not force on ahbinf clock
+ *  1 : Force on ahbinf clock
+ */
+#define AHB_DMA_AHBINF_CLK_EN    (BIT(28))
+#define AHB_DMA_AHBINF_CLK_EN_M  (AHB_DMA_AHBINF_CLK_EN_V << AHB_DMA_AHBINF_CLK_EN_S)
+#define AHB_DMA_AHBINF_CLK_EN_V  0x00000001U
+#define AHB_DMA_AHBINF_CLK_EN_S  28
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG register
+ *  AHB response error status 0 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS0_REG (DR_REG_AHB_DMA_BASE + 0x620)
+/** AHB_DMA_AHBINF_RESP_ERR_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address of the AHB response error.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR    0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_M  (AHB_DMA_AHBINF_RESP_ERR_ADDR_V << AHB_DMA_AHBINF_RESP_ERR_ADDR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_V  0xFFFFFFFFU
+#define AHB_DMA_AHBINF_RESP_ERR_ADDR_S  0
+
+/** AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG register
+ *  AHB response error status 1 register
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_STATUS1_REG (DR_REG_AHB_DMA_BASE + 0x624)
+/** AHB_DMA_AHBINF_RESP_ERR_WR : RO; bitpos: [0]; default: 0;
+ *  Represents the AHB response error is write request.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_WR    (BIT(0))
+#define AHB_DMA_AHBINF_RESP_ERR_WR_M  (AHB_DMA_AHBINF_RESP_ERR_WR_V << AHB_DMA_AHBINF_RESP_ERR_WR_S)
+#define AHB_DMA_AHBINF_RESP_ERR_WR_V  0x00000001U
+#define AHB_DMA_AHBINF_RESP_ERR_WR_S  0
+/** AHB_DMA_AHBINF_RESP_ERR_ID : RO; bitpos: [5:1]; default: 31;
+ *  Represents the AHB response error request id.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_ID    0x0000001FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_M  (AHB_DMA_AHBINF_RESP_ERR_ID_V << AHB_DMA_AHBINF_RESP_ERR_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_ID_V  0x0000001FU
+#define AHB_DMA_AHBINF_RESP_ERR_ID_S  1
+/** AHB_DMA_AHBINF_RESP_ERR_CH_ID : RO; bitpos: [9:6]; default: 0;
+ *  Represents the AHB response error request channel id.bit[3]=1:TX channel.
+ *  bit[3]=0:RX channel.
+ */
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID    0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_M  (AHB_DMA_AHBINF_RESP_ERR_CH_ID_V << AHB_DMA_AHBINF_RESP_ERR_CH_ID_S)
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_V  0x0000000FU
+#define AHB_DMA_AHBINF_RESP_ERR_CH_ID_S  6
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ahb_dma_struct.h b/components/soc/esp32s31/register/soc/ahb_dma_struct.h
new file mode 100644
index 00000000000..b9af7445364
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ahb_dma_struct.h
@@ -0,0 +1,1582 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt Registers */
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DONE_CHn_INT.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT.
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT.
+         */
+        uint32_t infifo_ovf_chn_int_raw:1;
+        /** infifo_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT.
+         */
+        uint32_t infifo_udf_chn_int_raw:1;
+        /** in_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT.
+         */
+        uint32_t in_ahbinf_resp_err_chn_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DONE_CHn_INT.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_SUC_EOF_CHn_INT.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_ERR_EOF_CHn_INT.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_ERR_CHn_INT.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_DSCR_EMPTY_CHn_INT.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_OVF_CHn_INT.
+         */
+        uint32_t infifo_ovf_chn_int_st:1;
+        /** infifo_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_INFIFO_UDF_CHn_INT.
+         */
+        uint32_t infifo_udf_chn_int_st:1;
+        /** in_ahbinf_resp_err_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of AHB_DMA_IN_RESP_ERR_CHn_INT.
+         */
+        uint32_t in_ahbinf_resp_err_chn_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DONE_CHn_INT.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_SUC_EOF_CHn_INT.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_ERR_EOF_CHn_INT.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_ERR_CHn_INT.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_DSCR_EMPTY_CHn_INT.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_OVF_CHn_INT.
+         */
+        uint32_t infifo_ovf_chn_int_ena:1;
+        /** infifo_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_INFIFO_UDF_CHn_INT.
+         */
+        uint32_t infifo_udf_chn_int_ena:1;
+        /** in_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable AHB_DMA_IN_RESP_ERR_CHn_INT.
+         */
+        uint32_t in_ahbinf_resp_err_chn_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DONE_CHn_INT.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_SUC_EOF_CHn_INT.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_ERR_EOF_CHn_INT.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_ERR_CHn_INT.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_DSCR_EMPTY_CHn_INT.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_OVF_CHn_INT.
+         */
+        uint32_t infifo_ovf_chn_int_clr:1;
+        /** infifo_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_INFIFO_UDF_CHn_INT.
+         */
+        uint32_t infifo_udf_chn_int_clr:1;
+        /** in_ahbinf_resp_err_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear AHB_DMA_IN_RESP_ERR_CHn_INT.
+         */
+        uint32_t in_ahbinf_resp_err_chn_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_int_clr_chn_reg_t;
+
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DONE_CHn_INT.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_EOF_CHn_INT.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT.
+         */
+        uint32_t outfifo_ovf_chn_int_raw:1;
+        /** outfifo_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT.
+         */
+        uint32_t outfifo_udf_chn_int_raw:1;
+        /** out_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT.
+         */
+        uint32_t out_ahbinf_resp_err_chn_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DONE_CHn_INT.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_EOF_CHn_INT.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_DSCR_ERR_CHn_INT.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_TOTAL_EOF_CHn_INT.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_OVF_CHn_INT.
+         */
+        uint32_t outfifo_ovf_chn_int_st:1;
+        /** outfifo_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUTFIFO_UDF_CHn_INT.
+         */
+        uint32_t outfifo_udf_chn_int_st:1;
+        /** out_ahbinf_resp_err_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CHn_INT.
+         */
+        uint32_t out_ahbinf_resp_err_chn_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DONE_CHn_INT.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_EOF_CHn_INT.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_DSCR_ERR_CHn_INT.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_TOTAL_EOF_CHn_INT.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_OVF_CHn_INT.
+         */
+        uint32_t outfifo_ovf_chn_int_ena:1;
+        /** outfifo_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUTFIFO_UDF_CHn_INT.
+         */
+        uint32_t outfifo_udf_chn_int_ena:1;
+        /** out_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable AHB_DMA_OUT_RESP_ERR_CHn_INT.
+         */
+        uint32_t out_ahbinf_resp_err_chn_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DONE_CHn_INT.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_EOF_CHn_INT.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_DSCR_ERR_CHn_INT.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_TOTAL_EOF_CHn_INT.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_OVF_CHn_INT.
+         */
+        uint32_t outfifo_ovf_chn_int_clr:1;
+        /** outfifo_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUTFIFO_UDF_CHn_INT.
+         */
+        uint32_t outfifo_udf_chn_int_clr:1;
+        /** out_ahbinf_resp_err_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear AHB_DMA_OUT_RESP_ERR_CHn_INT.
+         */
+        uint32_t out_ahbinf_resp_err_chn_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} ahb_dma_out_int_clr_chn_reg_t;
+
+
+/** Group: Debug Registers */
+/** Type of ahb_test register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** ahb_testmode : R/W; bitpos: [2:0]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testmode:3;
+        uint32_t reserved_3:1;
+        /** ahb_testaddr : R/W; bitpos: [5:4]; default: 0;
+         *  reserved
+         */
+        uint32_t ahb_testaddr:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_ahb_test_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of misc_conf register
+ *  Miscellaneous register
+ */
+typedef union {
+    struct {
+        /** ahbm_rst_inter : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset the internal AHB FSM.
+         */
+        uint32_t ahbm_rst_inter:1;
+        uint32_t reserved_1:1;
+        /** arb_pri_dis : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to disable the fixed-priority channel arbitration.
+         *  0: Enable
+         *  1: Disable
+         */
+        uint32_t arb_pri_dis:1;
+        /** clk_en : R/W; bitpos: [3]; default: 0;
+         *  Configures clock gating.
+         *  0: Support clock only when the application writes registers.
+         *  1: Always force the clock on for registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_misc_conf_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configuration register 0 of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  Write 1 and then 0 to reset AHB_DMA channel 0 RX FSM and RX FIFO pointer.
+         */
+        uint32_t in_rst_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t in_loop_test_chn:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable INCR burst transfer for RX channel n to read
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t indscr_burst_en_chn:1;
+        uint32_t reserved_3:1;
+        /** mem_trans_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable memory-to-memory data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t mem_trans_en_chn:1;
+        /** in_etm_en_chn : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable ETM control for RX channeln.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 0;
+         *  Configures max burst size for Rx channeln.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t in_data_burst_mode_sel_chn:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ahb_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configuration register 1 of RX channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for RX channel n.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t in_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_conf1_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of RX channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  Represents the data popped from AHB_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn:12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Configures whether to pop data from AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Pop
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_in_pop_chn_reg_t;
+
+/** Type of in_link_chn register
+ *  Linked list descriptor configuration and control register of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to return to current receive descriptor's address when there are
+         *  some errors in current receiving data.
+         *  0: Not return
+         *  1: Return
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Configures whether to stop AHB_DMA's RX channel n from receiving data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Configures whether to enable AHB_DMA's RX channel n for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Configures whether to restart RX channel n for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  Represents the status of the receive descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} ahb_dma_in_link_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Link list descriptor address configuration of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_link_addr_chn_reg_t;
+
+/** Type of rx_ch_arb_weigh_chn register
+ *  RX channel n arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of RX channeln
+         */
+        uint32_t rx_ch_arb_weigh_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
+
+/** Type of rx_arb_weigh_opt_dir_chn register
+ *  RX channel n weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of out_conf0_ch0 register
+ *  Configuration register 0 of TX channel 0
+ */
+typedef union {
+    struct {
+        /** out_rst_ch0 : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel 0 TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_ch0:1;
+        /** out_loop_test_ch0 : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t out_loop_test_ch0:1;
+        /** out_auto_wrback_ch0 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_ch0:1;
+        /** out_eof_mode_ch0 : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel 0 is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_ch0:1;
+        /** outdscr_burst_en_ch0 : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel 0 reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_ch0:1;
+        uint32_t reserved_5:1;
+        /** out_etm_en_ch0 : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel 0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_ch0:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_ch0 : R/W; bitpos: [9:8]; default: 0;
+         *  Configures max burst size for TX channel0.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_ch0:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_ch0_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configuration register 1 of TX channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable owner bit check for TX channel n.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_check_owner_chn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} ahb_dma_out_conf1_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of TX channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the data that need to be pushed into AHB_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn:9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Configures whether to push data into AHB_DMA FIFO.
+         *  0: Invalid. No effect
+         *  1: Push
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_push_chn_reg_t;
+
+/** Type of out_link_chn register
+ *  Linked list descriptor configuration and control register of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Configures whether to stop AHB_DMA's TX channel n from transmitting data.
+         *  0: Invalid. No effect
+         *  1: Stop
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Configures whether to enable AHB_DMA's TX channel n for data transfer.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Configures whether to restart TX channel n for AHB_DMA transfer.
+         *  0: Invalid. No effect
+         *  1: Restart
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  Represents the status of the transmit descriptor's FSM.
+         *  0: Running
+         *  1: Idle
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_link_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Link list descriptor address configuration of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the 32 bits of the first receive descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_link_addr_chn_reg_t;
+
+/** Type of tx_ch_arb_weigh_chn register
+ *  TX channel n arbitration weight configuration register
+ */
+typedef union {
+    struct {
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the weight(i.e the number of tokens) of TX channeln
+         */
+        uint32_t tx_ch_arb_weigh_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_tx_ch_arb_weigh_chn_reg_t;
+
+/** Type of tx_arb_weigh_opt_dir_chn register
+ *  TX channel n weight arbitration optimization enable register
+ */
+typedef union {
+    struct {
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configuration register 0 of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the reset state of AHB_DMA channel n TX FSM and TX FIFO pointer.
+         *  0: Release reset
+         *  1: Reset
+         */
+        uint32_t out_rst_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  Reserved.
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to enable automatic outlink write-back when all the data in TX
+         *  FIFO has been transmitted.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  Configures when to generate EOF flag.
+         *  0: EOF flag for TX channel n is generated when data to be transmitted has been
+         *  pushed into FIFO in AHB_DMA.
+         *  1: EOF flag for TX channel n is generated when data to be transmitted has been
+         *  popped from FIFO in AHB_DMA.
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable INCR burst transfer for TX channel n reading
+         *  descriptors.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        uint32_t reserved_5:1;
+        /** out_etm_en_chn : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to enable ETM control for TX channel n.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t out_etm_en_chn:1;
+        uint32_t reserved_7:1;
+        /** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 0;
+         *  Configures max burst size for TX channeln.
+         *  2'b00: single
+         *  2'b01: incr4
+         *  2'b10: incr8
+         *  2'b11: incr16
+         */
+        uint32_t out_data_burst_mode_sel_chn:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_out_conf0_chn_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  Accessible address space start address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  Accessible address space end address configuration register
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the end address of accessible address space.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_intr_mem_end_addr_reg_t;
+
+/** Type of arb_timeout register
+ *  TX arbitration timeout configuration register
+ */
+typedef union {
+    struct {
+        /** arb_timeout : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the time slot. Measurement unit: AHB bus clock cycle.
+         */
+        uint32_t arb_timeout:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} ahb_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  TX weight arbitration enable register
+ */
+typedef union {
+    struct {
+        /** weight_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable weight arbitration.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t weight_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ahb_dma_weight_en_reg_t;
+
+/** Type of module_clk_en register
+ *  Module clock force on register
+ */
+typedef union {
+    struct {
+        /** ahb_apb_sync_clk_en : R/W; bitpos: [4:0]; default: 31;
+         *  Configures whether to force on ahb_apb_sync 4~0 module clock. For bit n:
+         *  0 : Not force on ahb_apb_sync n clock
+         *  1 : Force on ahb_apb_sync n clock
+         */
+        uint32_t ahb_apb_sync_clk_en:5;
+        /** out_dscr_clk_en : R/W; bitpos: [9:5]; default: 31;
+         *  Configures whether to force on out_dscr 4~0 module clock. For bit n:
+         *  0 : Not force on out_dscr n clock
+         *  1 : Force on out_dscr n clock
+         */
+        uint32_t out_dscr_clk_en:5;
+        /** out_ctrl_clk_en : R/W; bitpos: [14:10]; default: 31;
+         *  Configures whether to force on out_ctrl 4~0 module clock. For bit n:
+         *  0 : Not force on out_ctrl n clock
+         *  1 : Force on out_ctrl n clock
+         */
+        uint32_t out_ctrl_clk_en:5;
+        /** in_dscr_clk_en : R/W; bitpos: [19:15]; default: 31;
+         *  Configures whether to force on in_dscr 4~0 module clock. For bit n:
+         *  0 : Not force on in_dscr n clock
+         *  1 : Force on in_dscr n clock
+         */
+        uint32_t in_dscr_clk_en:5;
+        /** in_ctrl_clk_en : R/W; bitpos: [24:20]; default: 31;
+         *  Configures whether to force on in_ctrl 4~0 module clock. For bit n:
+         *  0 : Not force on in_ctrl n clock
+         *  1 : Force on in_ctrl n clock
+         */
+        uint32_t in_ctrl_clk_en:5;
+        uint32_t reserved_25:2;
+        /** cmd_arb_clk_en : R/W; bitpos: [27]; default: 1;
+         *  Configures whether to force on cmd_arb module clock.
+         *  0 : Not force on cmd_arb clock
+         *  1 : Force on cmd_arb clock
+         */
+        uint32_t cmd_arb_clk_en:1;
+        /** ahbinf_clk_en : R/W; bitpos: [28]; default: 1;
+         *  Configures whether to force on ahbinf module clock.
+         *  0 : Not force on ahbinf clock
+         *  1 : Force on ahbinf clock
+         */
+        uint32_t ahbinf_clk_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} ahb_dma_module_clk_en_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 37778192;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} ahb_dma_date_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of RX channel n
+ */
+typedef union {
+    struct {
+        /** infifo_full_chn : RO; bitpos: [0]; default: 1;
+         *  Represents whether L1 RX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t infifo_full_chn:1;
+        /** infifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 RX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t infifo_empty_chn:1;
+        uint32_t reserved_2:6;
+        /** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 RX FIFO for RX channel n.
+         */
+        uint32_t infifo_cnt_chn:7;
+        uint32_t reserved_15:8;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_buf_hungry_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ahb_dma_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  Represents the address of the lower 18 bits of the next receive descriptor to be
+         *  processed.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Receive descriptor address when EOF occurs on RX channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Receive descriptor address when errors occur of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the receive descriptor when there are some errors in the
+         *  currently received data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_done_des_addr_chn register
+ *  RX_done inlink descriptor address of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the inlink descriptor when  this descriptor is completed .
+         */
+        uint32_t in_done_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_done_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current receive descriptor address of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next receive descriptor x+1 pointed by the current
+         *  receive descriptor that has already been fetched.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last receive descriptor address of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current receive descriptor x that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last receive descriptor address of RX channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous receive descriptor x-1 that has already been
+         *  fetched.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of TX channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_full_chn : RO; bitpos: [0]; default: 0;
+         *  Represents whether L1 TX FIFO is full.
+         *  0: Not Full
+         *  1: Full
+         */
+        uint32_t outfifo_full_chn:1;
+        /** outfifo_empty_chn : RO; bitpos: [1]; default: 1;
+         *  Represents whether L1 TX FIFO is empty.
+         *  0: Not empty
+         *  1: Empty
+         */
+        uint32_t outfifo_empty_chn:1;
+        uint32_t reserved_2:6;
+        /** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0;
+         *  Represents the number of data bytes in L1 TX FIFO for TX channel n.
+         */
+        uint32_t outfifo_cnt_chn:7;
+        uint32_t reserved_15:8;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  Reserved.
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  Reserved.
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  Reserved.
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  Reserved.
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} ahb_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  Represents the lower 18 bits of the address of the next transmit descriptor to be
+         *  processed.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn:3;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} ahb_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Transmit descriptor address when EOF occurs on TX channel n
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last transmit descriptor address when EOF occurs on TX channel n
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the transmit descriptor before the last transmit
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_done_des_addr_chn register
+ *  TX done outlink descriptor address of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the outlink descriptor when this descriptor is completed.
+         */
+        uint32_t out_done_des_addr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_done_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current transmit descriptor address of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the next transmit descriptor y+1 pointed by the current
+         *  transmit descriptor that has already been fetched.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last transmit descriptor address of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the current transmit descriptor y that has already been
+         *  fetched.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last transmit descriptor address of TX channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the previous transmit descriptor y-1 that has already
+         *  been fetched.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} ahb_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of ahbinf_resp_err_status0 register
+ *  AHB response error status 0 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address of the AHB response error.
+         */
+        uint32_t ahbinf_resp_err_addr:32;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status0_reg_t;
+
+/** Type of ahbinf_resp_err_status1 register
+ *  AHB response error status 1 register
+ */
+typedef union {
+    struct {
+        /** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0;
+         *  Represents the AHB response error is write request.
+         */
+        uint32_t ahbinf_resp_err_wr:1;
+        /** ahbinf_resp_err_id : RO; bitpos: [5:1]; default: 31;
+         *  Represents the AHB response error request id.
+         */
+        uint32_t ahbinf_resp_err_id:5;
+        /** ahbinf_resp_err_ch_id : RO; bitpos: [9:6]; default: 0;
+         *  Represents the AHB response error request channel id.bit[3]=1:TX channel.
+         *  bit[3]=0:RX channel.
+         */
+        uint32_t ahbinf_resp_err_ch_id:4;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} ahb_dma_ahbinf_resp_err_status1_reg_t;
+
+
+/** Group: Priority Registers */
+/** Type of in_pri_chn register
+ *  Priority register of RX channel n
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of RX channel n.The larger of the value, the higher of the
+         *  priority.
+         */
+        uint32_t rx_pri_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_in_pri_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of TX channel n
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the priority of TX channel n.The larger of the value, the higher of the
+         *  priority.
+         */
+        uint32_t tx_pri_chn:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ahb_dma_out_pri_chn_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection register of RX channel n
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to RX channel n.
+         *  0: UHCI0
+         *  1: I2S0-0
+         *  2: I2S0-1
+         *  3: I2S0-2
+         *  4: I2S0-3
+         *  5: I2S1-0
+         *  6: I2S1-1
+         *  7: I2S1-2
+         *  8: I2S1-3
+         *  9: ADC_DAC
+         *  10: RMT
+         *  11: Sample_rate_convert-0
+         *  12: Sample_rate_convert-1
+         *  13: Cordic
+         *  14: PVT0
+         *  15: DUMMY
+         */
+        uint32_t peri_in_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_in_peri_sel_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection register of TX channel n
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  Configures the peripheral connected to TX channel n.
+         *  0: UHCI0
+         *  1: I2S0-0
+         *  2: I2S0-1
+         *  3: I2S0-2
+         *  4: I2S0-3
+         *  5: I2S1-0
+         *  6: I2S1-1
+         *  7: I2S1-2
+         *  8: I2S1-3
+         *  9: ADC_DAC
+         *  10: RMT
+         *  11: Sample_rate_convert-0
+         *  12: Sample_rate_convert-1
+         *  13: Cordic
+         *  14: PVT0
+         *  15: DUMMY
+         */
+        uint32_t peri_out_sel_chn:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} ahb_dma_out_peri_sel_chn_reg_t;
+
+
+typedef struct {
+    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch3;
+    volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch3;
+    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch3;
+    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch3;
+    volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch4;
+    volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch4;
+    volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch4;
+    volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch4;
+    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch3;
+    volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch3;
+    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch3;
+    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch3;
+    volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch4;
+    volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch4;
+    volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch4;
+    volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch4;
+    volatile ahb_dma_ahb_test_reg_t ahb_test;
+    volatile ahb_dma_misc_conf_reg_t misc_conf;
+    volatile ahb_dma_date_reg_t date;
+    uint32_t reserved_0ac[21];
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch0;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop_ch0;
+    volatile ahb_dma_in_link_chn_reg_t in_link_ch0;
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_ch0;
+    volatile ahb_dma_in_state_chn_reg_t in_state_ch0;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch0;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri_ch0;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch0;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch0;
+    uint32_t reserved_144[15];
+    volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch0;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile ahb_dma_out_push_chn_reg_t out_push_ch0;
+    volatile ahb_dma_out_link_chn_reg_t out_link_ch0;
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_ch0;
+    volatile ahb_dma_out_state_chn_reg_t out_state_ch0;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
+    volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch0;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri_ch0;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch0;
+    volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch0;
+    uint32_t reserved_1c4[15];
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch1;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop_ch1;
+    volatile ahb_dma_in_link_chn_reg_t in_link_ch1;
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_ch1;
+    volatile ahb_dma_in_state_chn_reg_t in_state_ch1;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch1;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri_ch1;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch1;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch1;
+    uint32_t reserved_244[15];
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch1;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch1;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile ahb_dma_out_push_chn_reg_t out_push_ch1;
+    volatile ahb_dma_out_link_chn_reg_t out_link_ch1;
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_ch1;
+    volatile ahb_dma_out_state_chn_reg_t out_state_ch1;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
+    volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch1;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri_ch1;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch1;
+    volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch1;
+    uint32_t reserved_2c4[15];
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch2;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop_ch2;
+    volatile ahb_dma_in_link_chn_reg_t in_link_ch2;
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_ch2;
+    volatile ahb_dma_in_state_chn_reg_t in_state_ch2;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch2;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri_ch2;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2;
+    uint32_t reserved_344[15];
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch2;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch2;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile ahb_dma_out_push_chn_reg_t out_push_ch2;
+    volatile ahb_dma_out_link_chn_reg_t out_link_ch2;
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_ch2;
+    volatile ahb_dma_out_state_chn_reg_t out_state_ch2;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2;
+    volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch2;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri_ch2;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch2;
+    volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch2;
+    uint32_t reserved_3c4[15];
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch3;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch3;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch3;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop_ch3;
+    volatile ahb_dma_in_link_chn_reg_t in_link_ch3;
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_ch3;
+    volatile ahb_dma_in_state_chn_reg_t in_state_ch3;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch3;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch3;
+    volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch3;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch3;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch3;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch3;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri_ch3;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch3;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch3;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch3;
+    uint32_t reserved_444[15];
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch3;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch3;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch3;
+    volatile ahb_dma_out_push_chn_reg_t out_push_ch3;
+    volatile ahb_dma_out_link_chn_reg_t out_link_ch3;
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_ch3;
+    volatile ahb_dma_out_state_chn_reg_t out_state_ch3;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch3;
+    volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch3;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch3;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri_ch3;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch3;
+    volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch3;
+    volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch3;
+    uint32_t reserved_4c4[15];
+    volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch4;
+    volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch4;
+    volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch4;
+    volatile ahb_dma_in_pop_chn_reg_t in_pop_ch4;
+    volatile ahb_dma_in_link_chn_reg_t in_link_ch4;
+    volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_ch4;
+    volatile ahb_dma_in_state_chn_reg_t in_state_ch4;
+    volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch4;
+    volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch4;
+    volatile ahb_dma_in_done_des_addr_chn_reg_t in_done_des_addr_ch4;
+    volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch4;
+    volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch4;
+    volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch4;
+    volatile ahb_dma_in_pri_chn_reg_t in_pri_ch4;
+    volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch4;
+    volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch4;
+    volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch4;
+    uint32_t reserved_544[15];
+    volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch4;
+    volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch4;
+    volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch4;
+    volatile ahb_dma_out_push_chn_reg_t out_push_ch4;
+    volatile ahb_dma_out_link_chn_reg_t out_link_ch4;
+    volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_ch4;
+    volatile ahb_dma_out_state_chn_reg_t out_state_ch4;
+    volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch4;
+    volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch4;
+    volatile ahb_dma_out_done_des_addr_chn_reg_t out_done_des_addr_ch4;
+    volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch4;
+    volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch4;
+    volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch4;
+    volatile ahb_dma_out_pri_chn_reg_t out_pri_ch4;
+    volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch4;
+    volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch4;
+    volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch4;
+    uint32_t reserved_5c4[15];
+    volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile ahb_dma_arb_timeout_reg_t arb_timeout;
+    uint32_t reserved_60c;
+    volatile ahb_dma_weight_en_reg_t weight_en;
+    uint32_t reserved_614;
+    volatile ahb_dma_module_clk_en_reg_t module_clk_en;
+    uint32_t reserved_61c;
+    volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0;
+    volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1;
+} ahb_dma_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ahb_dma_dev_t) == 0x628, "Invalid size of ahb_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/asrc_reg.h b/components/soc/esp32s31/register/soc/asrc_reg.h
new file mode 100644
index 00000000000..49cf34ac859
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/asrc_reg.h
@@ -0,0 +1,650 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ASRC_CHNL0_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG0_REG (DR_REG_ASRC_BASE + 0x0)
+/** ASRC_CHNL0_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to bypass stage 1 re-sampler in channel0.
+ */
+#define ASRC_CHNL0_RS2_STG1_BYPASS    (BIT(0))
+#define ASRC_CHNL0_RS2_STG1_BYPASS_M  (ASRC_CHNL0_RS2_STG1_BYPASS_V << ASRC_CHNL0_RS2_STG1_BYPASS_S)
+#define ASRC_CHNL0_RS2_STG1_BYPASS_V  0x00000001U
+#define ASRC_CHNL0_RS2_STG1_BYPASS_S  0
+/** ASRC_CHNL0_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to bypass stage 0 re-sampler in channel0.
+ */
+#define ASRC_CHNL0_RS2_STG0_BYPASS    (BIT(1))
+#define ASRC_CHNL0_RS2_STG0_BYPASS_M  (ASRC_CHNL0_RS2_STG0_BYPASS_V << ASRC_CHNL0_RS2_STG0_BYPASS_S)
+#define ASRC_CHNL0_RS2_STG0_BYPASS_V  0x00000001U
+#define ASRC_CHNL0_RS2_STG0_BYPASS_S  1
+/** ASRC_CHNL0_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to bypass fractional re-sampler in channel0.
+ */
+#define ASRC_CHNL0_FRAC_BYPASS    (BIT(2))
+#define ASRC_CHNL0_FRAC_BYPASS_M  (ASRC_CHNL0_FRAC_BYPASS_V << ASRC_CHNL0_FRAC_BYPASS_S)
+#define ASRC_CHNL0_FRAC_BYPASS_V  0x00000001U
+#define ASRC_CHNL0_FRAC_BYPASS_S  2
+/** ASRC_CHNL0_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
+ *  Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
+ *  by  factor of 2, 1: decimation by  factor of 2.
+ */
+#define ASRC_CHNL0_RS2_STG1_MODE    (BIT(3))
+#define ASRC_CHNL0_RS2_STG1_MODE_M  (ASRC_CHNL0_RS2_STG1_MODE_V << ASRC_CHNL0_RS2_STG1_MODE_S)
+#define ASRC_CHNL0_RS2_STG1_MODE_V  0x00000001U
+#define ASRC_CHNL0_RS2_STG1_MODE_S  3
+/** ASRC_CHNL0_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
+ *  Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
+ *  by  factor of 2, 1: decimation by  factor of 2.
+ */
+#define ASRC_CHNL0_RS2_STG0_MODE    (BIT(4))
+#define ASRC_CHNL0_RS2_STG0_MODE_M  (ASRC_CHNL0_RS2_STG0_MODE_V << ASRC_CHNL0_RS2_STG0_MODE_S)
+#define ASRC_CHNL0_RS2_STG0_MODE_V  0x00000001U
+#define ASRC_CHNL0_RS2_STG0_MODE_S  4
+/** ASRC_CHNL0_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to move fraction re-sampler to the first stage in channel0, it should
+ *  be 1 when input frequency is higher the output.
+ */
+#define ASRC_CHNL0_FRAC_AHEAD    (BIT(5))
+#define ASRC_CHNL0_FRAC_AHEAD_M  (ASRC_CHNL0_FRAC_AHEAD_V << ASRC_CHNL0_FRAC_AHEAD_S)
+#define ASRC_CHNL0_FRAC_AHEAD_V  0x00000001U
+#define ASRC_CHNL0_FRAC_AHEAD_S  5
+/** ASRC_CHNL0_MODE : R/W; bitpos: [8:7]; default: 0;
+ *  Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
+ *  out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
+ */
+#define ASRC_CHNL0_MODE    0x00000003U
+#define ASRC_CHNL0_MODE_M  (ASRC_CHNL0_MODE_V << ASRC_CHNL0_MODE_S)
+#define ASRC_CHNL0_MODE_V  0x00000003U
+#define ASRC_CHNL0_MODE_S  7
+/** ASRC_CHNL0_SEL : R/W; bitpos: [9]; default: 0;
+ *  Write the bit to configure which 16bits data will be processing.
+ */
+#define ASRC_CHNL0_SEL    (BIT(9))
+#define ASRC_CHNL0_SEL_M  (ASRC_CHNL0_SEL_V << ASRC_CHNL0_SEL_S)
+#define ASRC_CHNL0_SEL_V  0x00000001U
+#define ASRC_CHNL0_SEL_S  9
+
+/** ASRC_CHNL0_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG1_REG (DR_REG_ASRC_BASE + 0x4)
+/** ASRC_CHNL0_FRAC_M : R/W; bitpos: [9:0]; default: 0;
+ *  Write the bits to specify the denominator of factor of fraction re-sampler in
+ *  channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
+ */
+#define ASRC_CHNL0_FRAC_M    0x000003FFU
+#define ASRC_CHNL0_FRAC_M_M  (ASRC_CHNL0_FRAC_M_V << ASRC_CHNL0_FRAC_M_S)
+#define ASRC_CHNL0_FRAC_M_V  0x000003FFU
+#define ASRC_CHNL0_FRAC_M_S  0
+/** ASRC_CHNL0_FRAC_L : R/W; bitpos: [19:10]; default: 0;
+ *  Write the bits to specify the nominator of factor of fraction re-sampler in
+ *  channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
+ */
+#define ASRC_CHNL0_FRAC_L    0x000003FFU
+#define ASRC_CHNL0_FRAC_L_M  (ASRC_CHNL0_FRAC_L_V << ASRC_CHNL0_FRAC_L_S)
+#define ASRC_CHNL0_FRAC_L_V  0x000003FFU
+#define ASRC_CHNL0_FRAC_L_S  10
+
+/** ASRC_CHNL0_CFG2_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG2_REG (DR_REG_ASRC_BASE + 0x8)
+/** ASRC_CHNL0_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
+ *  Write the bits with ((2^19+L)/(2L)) round down in channel0.
+ */
+#define ASRC_CHNL0_FRAC_RECIPL    0x000FFFFFU
+#define ASRC_CHNL0_FRAC_RECIPL_M  (ASRC_CHNL0_FRAC_RECIPL_V << ASRC_CHNL0_FRAC_RECIPL_S)
+#define ASRC_CHNL0_FRAC_RECIPL_V  0x000FFFFFU
+#define ASRC_CHNL0_FRAC_RECIPL_S  0
+
+/** ASRC_CHNL0_CFG3_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG3_REG (DR_REG_ASRC_BASE + 0xc)
+/** ASRC_CHNL0_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset channel0.
+ */
+#define ASRC_CHNL0_RESET    (BIT(0))
+#define ASRC_CHNL0_RESET_M  (ASRC_CHNL0_RESET_V << ASRC_CHNL0_RESET_S)
+#define ASRC_CHNL0_RESET_V  0x00000001U
+#define ASRC_CHNL0_RESET_S  0
+
+/** ASRC_CHNL0_CFG4_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG4_REG (DR_REG_ASRC_BASE + 0x10)
+/** ASRC_CHNL0_START : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to start channel0.
+ */
+#define ASRC_CHNL0_START    (BIT(0))
+#define ASRC_CHNL0_START_M  (ASRC_CHNL0_START_V << ASRC_CHNL0_START_S)
+#define ASRC_CHNL0_START_V  0x00000001U
+#define ASRC_CHNL0_START_S  0
+
+/** ASRC_CHNL0_CFG5_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG5_REG (DR_REG_ASRC_BASE + 0x14)
+/** ASRC_CHNL0_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable in data byte counter.
+ */
+#define ASRC_CHNL0_IN_CNT_ENA    (BIT(0))
+#define ASRC_CHNL0_IN_CNT_ENA_M  (ASRC_CHNL0_IN_CNT_ENA_V << ASRC_CHNL0_IN_CNT_ENA_S)
+#define ASRC_CHNL0_IN_CNT_ENA_V  0x00000001U
+#define ASRC_CHNL0_IN_CNT_ENA_S  0
+/** ASRC_CHNL0_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear in data byte counter.
+ */
+#define ASRC_CHNL0_IN_CNT_CLR    (BIT(1))
+#define ASRC_CHNL0_IN_CNT_CLR_M  (ASRC_CHNL0_IN_CNT_CLR_V << ASRC_CHNL0_IN_CNT_CLR_S)
+#define ASRC_CHNL0_IN_CNT_CLR_V  0x00000001U
+#define ASRC_CHNL0_IN_CNT_CLR_S  1
+/** ASRC_CHNL0_IN_LEN : R/W; bitpos: [31:8]; default: 0;
+ *  Write the bits to specify the data byte number of data from the DMA
+ */
+#define ASRC_CHNL0_IN_LEN    0x00FFFFFFU
+#define ASRC_CHNL0_IN_LEN_M  (ASRC_CHNL0_IN_LEN_V << ASRC_CHNL0_IN_LEN_S)
+#define ASRC_CHNL0_IN_LEN_V  0x00FFFFFFU
+#define ASRC_CHNL0_IN_LEN_S  8
+
+/** ASRC_CHNL0_CFG6_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_CFG6_REG (DR_REG_ASRC_BASE + 0x18)
+/** ASRC_CHNL0_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Write the bits to specify the which eof will be written to DMA. 0:  counter eof, 1:
+ *  DMA ineof, 2: both counter eof and DMA ineof, 3 none.
+ */
+#define ASRC_CHNL0_OUT_EOF_GEN_MODE    0x00000003U
+#define ASRC_CHNL0_OUT_EOF_GEN_MODE_M  (ASRC_CHNL0_OUT_EOF_GEN_MODE_V << ASRC_CHNL0_OUT_EOF_GEN_MODE_S)
+#define ASRC_CHNL0_OUT_EOF_GEN_MODE_V  0x00000003U
+#define ASRC_CHNL0_OUT_EOF_GEN_MODE_S  0
+/** ASRC_CHNL0_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable out data byte counter.
+ */
+#define ASRC_CHNL0_OUT_CNT_ENA    (BIT(2))
+#define ASRC_CHNL0_OUT_CNT_ENA_M  (ASRC_CHNL0_OUT_CNT_ENA_V << ASRC_CHNL0_OUT_CNT_ENA_S)
+#define ASRC_CHNL0_OUT_CNT_ENA_V  0x00000001U
+#define ASRC_CHNL0_OUT_CNT_ENA_S  2
+/** ASRC_CHNL0_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear out data byte counter.
+ */
+#define ASRC_CHNL0_OUT_CNT_CLR    (BIT(3))
+#define ASRC_CHNL0_OUT_CNT_CLR_M  (ASRC_CHNL0_OUT_CNT_CLR_V << ASRC_CHNL0_OUT_CNT_CLR_S)
+#define ASRC_CHNL0_OUT_CNT_CLR_V  0x00000001U
+#define ASRC_CHNL0_OUT_CNT_CLR_S  3
+/** ASRC_CHNL0_OUT_LEN_COMP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable out data byte counter compensation when using fractional
+ *  re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
+ *  reg_chnl0_out_len
+ */
+#define ASRC_CHNL0_OUT_LEN_COMP    (BIT(4))
+#define ASRC_CHNL0_OUT_LEN_COMP_M  (ASRC_CHNL0_OUT_LEN_COMP_V << ASRC_CHNL0_OUT_LEN_COMP_S)
+#define ASRC_CHNL0_OUT_LEN_COMP_V  0x00000001U
+#define ASRC_CHNL0_OUT_LEN_COMP_S  4
+/** ASRC_CHNL0_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
+ *  Write the bits to specify the data byte number of data to the DMA, the counter eof
+ *  will be set when the counter approaches.
+ */
+#define ASRC_CHNL0_OUT_LEN    0x00FFFFFFU
+#define ASRC_CHNL0_OUT_LEN_M  (ASRC_CHNL0_OUT_LEN_V << ASRC_CHNL0_OUT_LEN_S)
+#define ASRC_CHNL0_OUT_LEN_V  0x00FFFFFFU
+#define ASRC_CHNL0_OUT_LEN_S  8
+
+/** ASRC_CHNL0_FIFO_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL0_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x1c)
+/** ASRC_CHNL0_INFIFO_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset outfifo.
+ */
+#define ASRC_CHNL0_INFIFO_RESET    (BIT(0))
+#define ASRC_CHNL0_INFIFO_RESET_M  (ASRC_CHNL0_INFIFO_RESET_V << ASRC_CHNL0_INFIFO_RESET_S)
+#define ASRC_CHNL0_INFIFO_RESET_V  0x00000001U
+#define ASRC_CHNL0_INFIFO_RESET_S  0
+/** ASRC_CHNL0_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset infifo.
+ */
+#define ASRC_CHNL0_OUTFIFO_RESET    (BIT(1))
+#define ASRC_CHNL0_OUTFIFO_RESET_M  (ASRC_CHNL0_OUTFIFO_RESET_V << ASRC_CHNL0_OUTFIFO_RESET_S)
+#define ASRC_CHNL0_OUTFIFO_RESET_V  0x00000001U
+#define ASRC_CHNL0_OUTFIFO_RESET_S  1
+
+/** ASRC_CHNL0_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define ASRC_CHNL0_INT_RAW_REG (DR_REG_ASRC_BASE + 0x20)
+/** ASRC_CHNL0_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when the counter approach to reg_out_len.
+ */
+#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW    (BIT(0))
+#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_M  (ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S)
+#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_V  0x00000001U
+#define ASRC_CHNL0_OUTCNT_EOF_INT_RAW_S  0
+
+/** ASRC_CHNL0_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define ASRC_CHNL0_INT_ST_REG (DR_REG_ASRC_BASE + 0x24)
+/** ASRC_CHNL0_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
+ *  set to 1.
+ */
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ST    (BIT(0))
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_M  (ASRC_CHNL0_OUTCNT_EOF_INT_ST_V << ASRC_CHNL0_OUTCNT_EOF_INT_ST_S)
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_V  0x00000001U
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ST_S  0
+
+/** ASRC_CHNL0_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define ASRC_CHNL0_INT_ENA_REG (DR_REG_ASRC_BASE + 0x28)
+/** ASRC_CHNL0_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for reg_out_cnt_eof_int_st register.
+ */
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA    (BIT(0))
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_M  (ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S)
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_V  0x00000001U
+#define ASRC_CHNL0_OUTCNT_EOF_INT_ENA_S  0
+
+/** ASRC_CHNL0_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define ASRC_CHNL0_INT_CLR_REG (DR_REG_ASRC_BASE + 0x2c)
+/** ASRC_CHNL0_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
+ */
+#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR    (BIT(0))
+#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_M  (ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S)
+#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_V  0x00000001U
+#define ASRC_CHNL0_OUTCNT_EOF_INT_CLR_S  0
+
+/** ASRC_CHNL0_OUT_CNT_REG register
+ *  Status Registers
+ */
+#define ASRC_CHNL0_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x30)
+/** ASRC_CHNL0_OUT_CNT : RO; bitpos: [23:0]; default: 0;
+ *  Represents the bytes numbers send to the DMA when EOF occurs.
+ */
+#define ASRC_CHNL0_OUT_CNT    0x00FFFFFFU
+#define ASRC_CHNL0_OUT_CNT_M  (ASRC_CHNL0_OUT_CNT_V << ASRC_CHNL0_OUT_CNT_S)
+#define ASRC_CHNL0_OUT_CNT_V  0x00FFFFFFU
+#define ASRC_CHNL0_OUT_CNT_S  0
+
+/** ASRC_CHNL0_TRACE1_REG register
+ *  Debug Register1
+ */
+#define ASRC_CHNL0_TRACE1_REG (DR_REG_ASRC_BASE + 0x38)
+/** ASRC_CHNL0_OUT_INC : RO; bitpos: [23:0]; default: 0;
+ *  Represents the samples numbers send to the DMA
+ */
+#define ASRC_CHNL0_OUT_INC    0x00FFFFFFU
+#define ASRC_CHNL0_OUT_INC_M  (ASRC_CHNL0_OUT_INC_V << ASRC_CHNL0_OUT_INC_S)
+#define ASRC_CHNL0_OUT_INC_V  0x00FFFFFFU
+#define ASRC_CHNL0_OUT_INC_S  0
+
+/** ASRC_CHNL1_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG0_REG (DR_REG_ASRC_BASE + 0x3c)
+/** ASRC_CHNL1_RS2_STG1_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to bypass stage 1 re-sampler in channel1.
+ */
+#define ASRC_CHNL1_RS2_STG1_BYPASS    (BIT(0))
+#define ASRC_CHNL1_RS2_STG1_BYPASS_M  (ASRC_CHNL1_RS2_STG1_BYPASS_V << ASRC_CHNL1_RS2_STG1_BYPASS_S)
+#define ASRC_CHNL1_RS2_STG1_BYPASS_V  0x00000001U
+#define ASRC_CHNL1_RS2_STG1_BYPASS_S  0
+/** ASRC_CHNL1_RS2_STG0_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  Set this bit to bypass stage 0 re-sampler in channel1.
+ */
+#define ASRC_CHNL1_RS2_STG0_BYPASS    (BIT(1))
+#define ASRC_CHNL1_RS2_STG0_BYPASS_M  (ASRC_CHNL1_RS2_STG0_BYPASS_V << ASRC_CHNL1_RS2_STG0_BYPASS_S)
+#define ASRC_CHNL1_RS2_STG0_BYPASS_V  0x00000001U
+#define ASRC_CHNL1_RS2_STG0_BYPASS_S  1
+/** ASRC_CHNL1_FRAC_BYPASS : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to bypass fractional re-sampler in channel1.
+ */
+#define ASRC_CHNL1_FRAC_BYPASS    (BIT(2))
+#define ASRC_CHNL1_FRAC_BYPASS_M  (ASRC_CHNL1_FRAC_BYPASS_V << ASRC_CHNL1_FRAC_BYPASS_S)
+#define ASRC_CHNL1_FRAC_BYPASS_V  0x00000001U
+#define ASRC_CHNL1_FRAC_BYPASS_S  2
+/** ASRC_CHNL1_RS2_STG1_MODE : R/W; bitpos: [3]; default: 0;
+ *  Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
+ *  by  factor of 2, 1: decimation by  factor of 2.
+ */
+#define ASRC_CHNL1_RS2_STG1_MODE    (BIT(3))
+#define ASRC_CHNL1_RS2_STG1_MODE_M  (ASRC_CHNL1_RS2_STG1_MODE_V << ASRC_CHNL1_RS2_STG1_MODE_S)
+#define ASRC_CHNL1_RS2_STG1_MODE_V  0x00000001U
+#define ASRC_CHNL1_RS2_STG1_MODE_S  3
+/** ASRC_CHNL1_RS2_STG0_MODE : R/W; bitpos: [4]; default: 0;
+ *  Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
+ *  by  factor of 2, 1: decimation by  factor of 2.
+ */
+#define ASRC_CHNL1_RS2_STG0_MODE    (BIT(4))
+#define ASRC_CHNL1_RS2_STG0_MODE_M  (ASRC_CHNL1_RS2_STG0_MODE_V << ASRC_CHNL1_RS2_STG0_MODE_S)
+#define ASRC_CHNL1_RS2_STG0_MODE_V  0x00000001U
+#define ASRC_CHNL1_RS2_STG0_MODE_S  4
+/** ASRC_CHNL1_FRAC_AHEAD : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to move fraction re-sampler to the first stage in channel1, it should
+ *  be 1 when input frequency is higher the output.
+ */
+#define ASRC_CHNL1_FRAC_AHEAD    (BIT(5))
+#define ASRC_CHNL1_FRAC_AHEAD_M  (ASRC_CHNL1_FRAC_AHEAD_V << ASRC_CHNL1_FRAC_AHEAD_S)
+#define ASRC_CHNL1_FRAC_AHEAD_V  0x00000001U
+#define ASRC_CHNL1_FRAC_AHEAD_S  5
+/** ASRC_CHNL1_MODE : R/W; bitpos: [8:7]; default: 0;
+ *  Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
+ *  out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
+ */
+#define ASRC_CHNL1_MODE    0x00000003U
+#define ASRC_CHNL1_MODE_M  (ASRC_CHNL1_MODE_V << ASRC_CHNL1_MODE_S)
+#define ASRC_CHNL1_MODE_V  0x00000003U
+#define ASRC_CHNL1_MODE_S  7
+/** ASRC_CHNL1_SEL : R/W; bitpos: [9]; default: 0;
+ *  Write the bit to configure which 16bits data will be processing.
+ */
+#define ASRC_CHNL1_SEL    (BIT(9))
+#define ASRC_CHNL1_SEL_M  (ASRC_CHNL1_SEL_V << ASRC_CHNL1_SEL_S)
+#define ASRC_CHNL1_SEL_V  0x00000001U
+#define ASRC_CHNL1_SEL_S  9
+
+/** ASRC_CHNL1_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG1_REG (DR_REG_ASRC_BASE + 0x40)
+/** ASRC_CHNL1_FRAC_M : R/W; bitpos: [9:0]; default: 0;
+ *  Write the bits to specify the denominator of factor of fraction re-sampler in
+ *  channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
+ */
+#define ASRC_CHNL1_FRAC_M    0x000003FFU
+#define ASRC_CHNL1_FRAC_M_M  (ASRC_CHNL1_FRAC_M_V << ASRC_CHNL1_FRAC_M_S)
+#define ASRC_CHNL1_FRAC_M_V  0x000003FFU
+#define ASRC_CHNL1_FRAC_M_S  0
+/** ASRC_CHNL1_FRAC_L : R/W; bitpos: [19:10]; default: 0;
+ *  Write the bits to specify the nominator of factor of fraction re-sampler in
+ *  channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
+ */
+#define ASRC_CHNL1_FRAC_L    0x000003FFU
+#define ASRC_CHNL1_FRAC_L_M  (ASRC_CHNL1_FRAC_L_V << ASRC_CHNL1_FRAC_L_S)
+#define ASRC_CHNL1_FRAC_L_V  0x000003FFU
+#define ASRC_CHNL1_FRAC_L_S  10
+
+/** ASRC_CHNL1_CFG2_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG2_REG (DR_REG_ASRC_BASE + 0x44)
+/** ASRC_CHNL1_FRAC_RECIPL : R/W; bitpos: [19:0]; default: 0;
+ *  Write the bits with ((2^19+L)/(2L)) round down in channel1.
+ */
+#define ASRC_CHNL1_FRAC_RECIPL    0x000FFFFFU
+#define ASRC_CHNL1_FRAC_RECIPL_M  (ASRC_CHNL1_FRAC_RECIPL_V << ASRC_CHNL1_FRAC_RECIPL_S)
+#define ASRC_CHNL1_FRAC_RECIPL_V  0x000FFFFFU
+#define ASRC_CHNL1_FRAC_RECIPL_S  0
+
+/** ASRC_CHNL1_CFG3_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG3_REG (DR_REG_ASRC_BASE + 0x48)
+/** ASRC_CHNL1_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset channel1.
+ */
+#define ASRC_CHNL1_RESET    (BIT(0))
+#define ASRC_CHNL1_RESET_M  (ASRC_CHNL1_RESET_V << ASRC_CHNL1_RESET_S)
+#define ASRC_CHNL1_RESET_V  0x00000001U
+#define ASRC_CHNL1_RESET_S  0
+
+/** ASRC_CHNL1_CFG4_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG4_REG (DR_REG_ASRC_BASE + 0x4c)
+/** ASRC_CHNL1_START : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to start channel1.
+ */
+#define ASRC_CHNL1_START    (BIT(0))
+#define ASRC_CHNL1_START_M  (ASRC_CHNL1_START_V << ASRC_CHNL1_START_S)
+#define ASRC_CHNL1_START_V  0x00000001U
+#define ASRC_CHNL1_START_S  0
+
+/** ASRC_CHNL1_CFG5_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG5_REG (DR_REG_ASRC_BASE + 0x50)
+/** ASRC_CHNL1_IN_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable in data byte counter.
+ */
+#define ASRC_CHNL1_IN_CNT_ENA    (BIT(0))
+#define ASRC_CHNL1_IN_CNT_ENA_M  (ASRC_CHNL1_IN_CNT_ENA_V << ASRC_CHNL1_IN_CNT_ENA_S)
+#define ASRC_CHNL1_IN_CNT_ENA_V  0x00000001U
+#define ASRC_CHNL1_IN_CNT_ENA_S  0
+/** ASRC_CHNL1_IN_CNT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear in data byte counter.
+ */
+#define ASRC_CHNL1_IN_CNT_CLR    (BIT(1))
+#define ASRC_CHNL1_IN_CNT_CLR_M  (ASRC_CHNL1_IN_CNT_CLR_V << ASRC_CHNL1_IN_CNT_CLR_S)
+#define ASRC_CHNL1_IN_CNT_CLR_V  0x00000001U
+#define ASRC_CHNL1_IN_CNT_CLR_S  1
+/** ASRC_CHNL1_IN_LEN : R/W; bitpos: [31:8]; default: 0;
+ *  Write the bits to specify the data byte numbers of data from the DMA
+ */
+#define ASRC_CHNL1_IN_LEN    0x00FFFFFFU
+#define ASRC_CHNL1_IN_LEN_M  (ASRC_CHNL1_IN_LEN_V << ASRC_CHNL1_IN_LEN_S)
+#define ASRC_CHNL1_IN_LEN_V  0x00FFFFFFU
+#define ASRC_CHNL1_IN_LEN_S  8
+
+/** ASRC_CHNL1_CFG6_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_CFG6_REG (DR_REG_ASRC_BASE + 0x54)
+/** ASRC_CHNL1_OUT_EOF_GEN_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Write the bits to specify the which eof will be written to DMA. 0:  counter eof, 1:
+ *  DMA ineof, 2: both counter eof and DMA ineof, 3 none.
+ */
+#define ASRC_CHNL1_OUT_EOF_GEN_MODE    0x00000003U
+#define ASRC_CHNL1_OUT_EOF_GEN_MODE_M  (ASRC_CHNL1_OUT_EOF_GEN_MODE_V << ASRC_CHNL1_OUT_EOF_GEN_MODE_S)
+#define ASRC_CHNL1_OUT_EOF_GEN_MODE_V  0x00000003U
+#define ASRC_CHNL1_OUT_EOF_GEN_MODE_S  0
+/** ASRC_CHNL1_OUT_CNT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable out data byte counter.
+ */
+#define ASRC_CHNL1_OUT_CNT_ENA    (BIT(2))
+#define ASRC_CHNL1_OUT_CNT_ENA_M  (ASRC_CHNL1_OUT_CNT_ENA_V << ASRC_CHNL1_OUT_CNT_ENA_S)
+#define ASRC_CHNL1_OUT_CNT_ENA_V  0x00000001U
+#define ASRC_CHNL1_OUT_CNT_ENA_S  2
+/** ASRC_CHNL1_OUT_CNT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear out data byte counter.
+ */
+#define ASRC_CHNL1_OUT_CNT_CLR    (BIT(3))
+#define ASRC_CHNL1_OUT_CNT_CLR_M  (ASRC_CHNL1_OUT_CNT_CLR_V << ASRC_CHNL1_OUT_CNT_CLR_S)
+#define ASRC_CHNL1_OUT_CNT_CLR_V  0x00000001U
+#define ASRC_CHNL1_OUT_CNT_CLR_S  3
+/** ASRC_CHNL1_OUT_SAMPLES_COMP : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable out data byte counter compensation when using fractional
+ *  re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
+ *  reg_chnl1_out_len
+ */
+#define ASRC_CHNL1_OUT_SAMPLES_COMP    (BIT(4))
+#define ASRC_CHNL1_OUT_SAMPLES_COMP_M  (ASRC_CHNL1_OUT_SAMPLES_COMP_V << ASRC_CHNL1_OUT_SAMPLES_COMP_S)
+#define ASRC_CHNL1_OUT_SAMPLES_COMP_V  0x00000001U
+#define ASRC_CHNL1_OUT_SAMPLES_COMP_S  4
+/** ASRC_CHNL1_OUT_LEN : R/W; bitpos: [31:8]; default: 0;
+ *  Write the bits to specify the data byte number of data to the DMA, the counter eof
+ *  will be set when the counter approaches.
+ */
+#define ASRC_CHNL1_OUT_LEN    0x00FFFFFFU
+#define ASRC_CHNL1_OUT_LEN_M  (ASRC_CHNL1_OUT_LEN_V << ASRC_CHNL1_OUT_LEN_S)
+#define ASRC_CHNL1_OUT_LEN_V  0x00FFFFFFU
+#define ASRC_CHNL1_OUT_LEN_S  8
+
+/** ASRC_CHNL1_FIFO_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_CHNL1_FIFO_CTRL_REG (DR_REG_ASRC_BASE + 0x58)
+/** ASRC_CHNL1_INFIFO_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset outfifo.
+ */
+#define ASRC_CHNL1_INFIFO_RESET    (BIT(0))
+#define ASRC_CHNL1_INFIFO_RESET_M  (ASRC_CHNL1_INFIFO_RESET_V << ASRC_CHNL1_INFIFO_RESET_S)
+#define ASRC_CHNL1_INFIFO_RESET_V  0x00000001U
+#define ASRC_CHNL1_INFIFO_RESET_S  0
+/** ASRC_CHNL1_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset infifo.
+ */
+#define ASRC_CHNL1_OUTFIFO_RESET    (BIT(1))
+#define ASRC_CHNL1_OUTFIFO_RESET_M  (ASRC_CHNL1_OUTFIFO_RESET_V << ASRC_CHNL1_OUTFIFO_RESET_S)
+#define ASRC_CHNL1_OUTFIFO_RESET_V  0x00000001U
+#define ASRC_CHNL1_OUTFIFO_RESET_S  1
+
+/** ASRC_CHNL1_INT_RAW_REG register
+ *  Raw interrupt status
+ */
+#define ASRC_CHNL1_INT_RAW_REG (DR_REG_ASRC_BASE + 0x5c)
+/** ASRC_CHNL1_OUTCNT_EOF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  This interrupt raw bit turns to high level when the counter approach to reg_out_len.
+ */
+#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW    (BIT(0))
+#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_M  (ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V << ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S)
+#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_V  0x00000001U
+#define ASRC_CHNL1_OUTCNT_EOF_INT_RAW_S  0
+
+/** ASRC_CHNL1_INT_ST_REG register
+ *  Masked interrupt status
+ */
+#define ASRC_CHNL1_INT_ST_REG (DR_REG_ASRC_BASE + 0x60)
+/** ASRC_CHNL1_OUTCNT_EOF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
+ *  set to 1.
+ */
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ST    (BIT(0))
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_M  (ASRC_CHNL1_OUTCNT_EOF_INT_ST_V << ASRC_CHNL1_OUTCNT_EOF_INT_ST_S)
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_V  0x00000001U
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ST_S  0
+
+/** ASRC_CHNL1_INT_ENA_REG register
+ *  Interrupt enable bits
+ */
+#define ASRC_CHNL1_INT_ENA_REG (DR_REG_ASRC_BASE + 0x64)
+/** ASRC_CHNL1_OUTCNT_EOF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  This is the enable bit for reg_out_cnt_eof_int_st register.
+ */
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA    (BIT(0))
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_M  (ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V << ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S)
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_V  0x00000001U
+#define ASRC_CHNL1_OUTCNT_EOF_INT_ENA_S  0
+
+/** ASRC_CHNL1_INT_CLR_REG register
+ *  Interrupt clear bits
+ */
+#define ASRC_CHNL1_INT_CLR_REG (DR_REG_ASRC_BASE + 0x68)
+/** ASRC_CHNL1_OUTCNT_EOF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
+ */
+#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR    (BIT(0))
+#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_M  (ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V << ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S)
+#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_V  0x00000001U
+#define ASRC_CHNL1_OUTCNT_EOF_INT_CLR_S  0
+
+/** ASRC_CHNL1_OUT_CNT_REG register
+ *  Status Registers
+ */
+#define ASRC_CHNL1_OUT_CNT_REG (DR_REG_ASRC_BASE + 0x6c)
+/** ASRC_CHNL1_OUT_CNT : RO; bitpos: [23:0]; default: 0;
+ *  Represents the data byte numbers send to the DMA when EOF occurs.
+ */
+#define ASRC_CHNL1_OUT_CNT    0x00FFFFFFU
+#define ASRC_CHNL1_OUT_CNT_M  (ASRC_CHNL1_OUT_CNT_V << ASRC_CHNL1_OUT_CNT_S)
+#define ASRC_CHNL1_OUT_CNT_V  0x00FFFFFFU
+#define ASRC_CHNL1_OUT_CNT_S  0
+
+/** ASRC_CHNL1_TRACE1_REG register
+ *  Debug Register1
+ */
+#define ASRC_CHNL1_TRACE1_REG (DR_REG_ASRC_BASE + 0x74)
+/** ASRC_CHNL1_OUT_INC : RO; bitpos: [23:0]; default: 0;
+ *  Represents the data byte numbers send to the DMA
+ */
+#define ASRC_CHNL1_OUT_INC    0x00FFFFFFU
+#define ASRC_CHNL1_OUT_INC_M  (ASRC_CHNL1_OUT_INC_V << ASRC_CHNL1_OUT_INC_S)
+#define ASRC_CHNL1_OUT_INC_V  0x00FFFFFFU
+#define ASRC_CHNL1_OUT_INC_S  0
+
+/** ASRC_SYS_REG register
+ *  Control and configuration
+ */
+#define ASRC_SYS_REG (DR_REG_ASRC_BASE + 0xf8)
+/** ASRC_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Reserved
+ */
+#define ASRC_CLK_EN    (BIT(0))
+#define ASRC_CLK_EN_M  (ASRC_CLK_EN_V << ASRC_CLK_EN_S)
+#define ASRC_CLK_EN_V  0x00000001U
+#define ASRC_CLK_EN_S  0
+/** ASRC_CHNL0_CLK_FO : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to make channel0 clock free run.
+ */
+#define ASRC_CHNL0_CLK_FO    (BIT(1))
+#define ASRC_CHNL0_CLK_FO_M  (ASRC_CHNL0_CLK_FO_V << ASRC_CHNL0_CLK_FO_S)
+#define ASRC_CHNL0_CLK_FO_V  0x00000001U
+#define ASRC_CHNL0_CLK_FO_S  1
+/** ASRC_CHNL1_CLK_FO : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to make channel1 clock free run.
+ */
+#define ASRC_CHNL1_CLK_FO    (BIT(2))
+#define ASRC_CHNL1_CLK_FO_M  (ASRC_CHNL1_CLK_FO_V << ASRC_CHNL1_CLK_FO_S)
+#define ASRC_CHNL1_CLK_FO_V  0x00000001U
+#define ASRC_CHNL1_CLK_FO_S  2
+/** ASRC_CHNL0_OUTFIFO_CLK_FO : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to make channel0 outfifo clock free run.
+ */
+#define ASRC_CHNL0_OUTFIFO_CLK_FO    (BIT(3))
+#define ASRC_CHNL0_OUTFIFO_CLK_FO_M  (ASRC_CHNL0_OUTFIFO_CLK_FO_V << ASRC_CHNL0_OUTFIFO_CLK_FO_S)
+#define ASRC_CHNL0_OUTFIFO_CLK_FO_V  0x00000001U
+#define ASRC_CHNL0_OUTFIFO_CLK_FO_S  3
+/** ASRC_CHNL0_INFIFO_CLK_FO : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to make channel0 infifo clock free run.
+ */
+#define ASRC_CHNL0_INFIFO_CLK_FO    (BIT(4))
+#define ASRC_CHNL0_INFIFO_CLK_FO_M  (ASRC_CHNL0_INFIFO_CLK_FO_V << ASRC_CHNL0_INFIFO_CLK_FO_S)
+#define ASRC_CHNL0_INFIFO_CLK_FO_V  0x00000001U
+#define ASRC_CHNL0_INFIFO_CLK_FO_S  4
+/** ASRC_CHNL1_OUTFIFO_CLK_FO : R/W; bitpos: [5]; default: 0;
+ *  Set this bit to make channel1 outfifo clock free run.
+ */
+#define ASRC_CHNL1_OUTFIFO_CLK_FO    (BIT(5))
+#define ASRC_CHNL1_OUTFIFO_CLK_FO_M  (ASRC_CHNL1_OUTFIFO_CLK_FO_V << ASRC_CHNL1_OUTFIFO_CLK_FO_S)
+#define ASRC_CHNL1_OUTFIFO_CLK_FO_V  0x00000001U
+#define ASRC_CHNL1_OUTFIFO_CLK_FO_S  5
+/** ASRC_CHNL1_INFIFO_CLK_FO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to make channel1 infifo clock free run.
+ */
+#define ASRC_CHNL1_INFIFO_CLK_FO    (BIT(6))
+#define ASRC_CHNL1_INFIFO_CLK_FO_M  (ASRC_CHNL1_INFIFO_CLK_FO_V << ASRC_CHNL1_INFIFO_CLK_FO_S)
+#define ASRC_CHNL1_INFIFO_CLK_FO_V  0x00000001U
+#define ASRC_CHNL1_INFIFO_CLK_FO_S  6
+
+/** ASRC_DATE_REG register
+ *  Control and configuration registers
+ */
+#define ASRC_DATE_REG (DR_REG_ASRC_BASE + 0xfc)
+/** ASRC_DATE : R/W; bitpos: [27:0]; default: 37777984;
+ *  Reserved
+ */
+#define ASRC_DATE    0x0FFFFFFFU
+#define ASRC_DATE_M  (ASRC_DATE_V << ASRC_DATE_S)
+#define ASRC_DATE_V  0x0FFFFFFFU
+#define ASRC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/asrc_struct.h b/components/soc/esp32s31/register/soc/asrc_struct.h
new file mode 100644
index 00000000000..83a9778bd67
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/asrc_struct.h
@@ -0,0 +1,656 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of chnl0_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to bypass stage 1 re-sampler in channel0.
+         */
+        uint32_t chnl0_rs2_stg1_bypass:1;
+        /** chnl0_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to bypass stage 0 re-sampler in channel0.
+         */
+        uint32_t chnl0_rs2_stg0_bypass:1;
+        /** chnl0_frac_bypass : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to bypass fractional re-sampler in channel0.
+         */
+        uint32_t chnl0_frac_bypass:1;
+        /** chnl0_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
+         *  Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
+         *  by  factor of 2, 1: decimation by  factor of 2.
+         */
+        uint32_t chnl0_rs2_stg1_mode:1;
+        /** chnl0_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
+         *  Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
+         *  by  factor of 2, 1: decimation by  factor of 2.
+         */
+        uint32_t chnl0_rs2_stg0_mode:1;
+        /** chnl0_frac_ahead : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to move fraction re-sampler to the first stage in channel0, it should
+         *  be 1 when input frequency is higher the output.
+         */
+        uint32_t chnl0_frac_ahead:1;
+        uint32_t reserved_6:1;
+        /** chnl0_mode : R/W; bitpos: [8:7]; default: 0;
+         *  Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
+         *  out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
+         */
+        uint32_t chnl0_mode:2;
+        /** chnl0_sel : R/W; bitpos: [9]; default: 0;
+         *  Write the bit to configure which 16bits data will be processing.
+         */
+        uint32_t chnl0_sel:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg0_reg_t;
+
+/** Type of chnl0_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_frac_m : R/W; bitpos: [9:0]; default: 0;
+         *  Write the bits to specify the denominator of factor of fraction re-sampler in
+         *  channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
+         */
+        uint32_t chnl0_frac_m:10;
+        /** chnl0_frac_l : R/W; bitpos: [19:10]; default: 0;
+         *  Write the bits to specify the nominator of factor of fraction re-sampler in
+         *  channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
+         */
+        uint32_t chnl0_frac_l:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg1_reg_t;
+
+/** Type of chnl0_cfg2 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_frac_recipl : R/W; bitpos: [19:0]; default: 0;
+         *  Write the bits with ((2^19+L)/(2L)) round down in channel0.
+         */
+        uint32_t chnl0_frac_recipl:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg2_reg_t;
+
+/** Type of chnl0_cfg3 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset channel0.
+         */
+        uint32_t chnl0_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg3_reg_t;
+
+/** Type of chnl0_cfg4 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_start : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to start channel0.
+         */
+        uint32_t chnl0_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg4_reg_t;
+
+/** Type of chnl0_cfg5 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_in_cnt_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable in data byte counter.
+         */
+        uint32_t chnl0_in_cnt_ena:1;
+        /** chnl0_in_cnt_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear in data byte counter.
+         */
+        uint32_t chnl0_in_cnt_clr:1;
+        uint32_t reserved_2:6;
+        /** chnl0_in_len : R/W; bitpos: [31:8]; default: 0;
+         *  Write the bits to specify the data byte number of data from the DMA
+         */
+        uint32_t chnl0_in_len:24;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg5_reg_t;
+
+/** Type of chnl0_cfg6 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Write the bits to specify the which eof will be written to DMA. 0:  counter eof, 1:
+         *  DMA ineof, 2: both counter eof and DMA ineof, 3 none.
+         */
+        uint32_t chnl0_out_eof_gen_mode:2;
+        /** chnl0_out_cnt_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable out data byte counter.
+         */
+        uint32_t chnl0_out_cnt_ena:1;
+        /** chnl0_out_cnt_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear out data byte counter.
+         */
+        uint32_t chnl0_out_cnt_clr:1;
+        /** chnl0_out_len_comp : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable out data byte counter compensation when using fractional
+         *  re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
+         *  reg_chnl0_out_len
+         */
+        uint32_t chnl0_out_len_comp:1;
+        uint32_t reserved_5:3;
+        /** chnl0_out_len : R/W; bitpos: [31:8]; default: 0;
+         *  Write the bits to specify the data byte number of data to the DMA, the counter eof
+         *  will be set when the counter approaches.
+         */
+        uint32_t chnl0_out_len:24;
+    };
+    uint32_t val;
+} asrc_chnl0_cfg6_reg_t;
+
+/** Type of chnl0_fifo_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl0_infifo_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset outfifo.
+         */
+        uint32_t chnl0_infifo_reset:1;
+        /** chnl0_outfifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset infifo.
+         */
+        uint32_t chnl0_outfifo_reset:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} asrc_chnl0_fifo_ctrl_reg_t;
+
+/** Type of chnl1_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to bypass stage 1 re-sampler in channel1.
+         */
+        uint32_t chnl1_rs2_stg1_bypass:1;
+        /** chnl1_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
+         *  Set this bit to bypass stage 0 re-sampler in channel1.
+         */
+        uint32_t chnl1_rs2_stg0_bypass:1;
+        /** chnl1_frac_bypass : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to bypass fractional re-sampler in channel1.
+         */
+        uint32_t chnl1_frac_bypass:1;
+        /** chnl1_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
+         *  Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
+         *  by  factor of 2, 1: decimation by  factor of 2.
+         */
+        uint32_t chnl1_rs2_stg1_mode:1;
+        /** chnl1_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
+         *  Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
+         *  by  factor of 2, 1: decimation by  factor of 2.
+         */
+        uint32_t chnl1_rs2_stg0_mode:1;
+        /** chnl1_frac_ahead : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to move fraction re-sampler to the first stage in channel1, it should
+         *  be 1 when input frequency is higher the output.
+         */
+        uint32_t chnl1_frac_ahead:1;
+        uint32_t reserved_6:1;
+        /** chnl1_mode : R/W; bitpos: [8:7]; default: 0;
+         *  Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
+         *  out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
+         */
+        uint32_t chnl1_mode:2;
+        /** chnl1_sel : R/W; bitpos: [9]; default: 0;
+         *  Write the bit to configure which 16bits data will be processing.
+         */
+        uint32_t chnl1_sel:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg0_reg_t;
+
+/** Type of chnl1_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_frac_m : R/W; bitpos: [9:0]; default: 0;
+         *  Write the bits to specify the denominator of factor of fraction re-sampler in
+         *  channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
+         */
+        uint32_t chnl1_frac_m:10;
+        /** chnl1_frac_l : R/W; bitpos: [19:10]; default: 0;
+         *  Write the bits to specify the nominator of factor of fraction re-sampler in
+         *  channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
+         */
+        uint32_t chnl1_frac_l:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg1_reg_t;
+
+/** Type of chnl1_cfg2 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_frac_recipl : R/W; bitpos: [19:0]; default: 0;
+         *  Write the bits with ((2^19+L)/(2L)) round down in channel1.
+         */
+        uint32_t chnl1_frac_recipl:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg2_reg_t;
+
+/** Type of chnl1_cfg3 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset channel1.
+         */
+        uint32_t chnl1_reset:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg3_reg_t;
+
+/** Type of chnl1_cfg4 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_start : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to start channel1.
+         */
+        uint32_t chnl1_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg4_reg_t;
+
+/** Type of chnl1_cfg5 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_in_cnt_ena : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable in data byte counter.
+         */
+        uint32_t chnl1_in_cnt_ena:1;
+        /** chnl1_in_cnt_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear in data byte counter.
+         */
+        uint32_t chnl1_in_cnt_clr:1;
+        uint32_t reserved_2:6;
+        /** chnl1_in_len : R/W; bitpos: [31:8]; default: 0;
+         *  Write the bits to specify the data byte numbers of data from the DMA
+         */
+        uint32_t chnl1_in_len:24;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg5_reg_t;
+
+/** Type of chnl1_cfg6 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Write the bits to specify the which eof will be written to DMA. 0:  counter eof, 1:
+         *  DMA ineof, 2: both counter eof and DMA ineof, 3 none.
+         */
+        uint32_t chnl1_out_eof_gen_mode:2;
+        /** chnl1_out_cnt_ena : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable out data byte counter.
+         */
+        uint32_t chnl1_out_cnt_ena:1;
+        /** chnl1_out_cnt_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear out data byte counter.
+         */
+        uint32_t chnl1_out_cnt_clr:1;
+        /** chnl1_out_samples_comp : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable out data byte counter compensation when using fractional
+         *  re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
+         *  reg_chnl1_out_len
+         */
+        uint32_t chnl1_out_samples_comp:1;
+        uint32_t reserved_5:3;
+        /** chnl1_out_len : R/W; bitpos: [31:8]; default: 0;
+         *  Write the bits to specify the data byte number of data to the DMA, the counter eof
+         *  will be set when the counter approaches.
+         */
+        uint32_t chnl1_out_len:24;
+    };
+    uint32_t val;
+} asrc_chnl1_cfg6_reg_t;
+
+/** Type of chnl1_fifo_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** chnl1_infifo_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset outfifo.
+         */
+        uint32_t chnl1_infifo_reset:1;
+        /** chnl1_outfifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset infifo.
+         */
+        uint32_t chnl1_outfifo_reset:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} asrc_chnl1_fifo_ctrl_reg_t;
+
+
+/** Group: Interrupt Register */
+/** Type of chnl0_int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** chnl0_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when the counter approach to reg_out_len.
+         */
+        uint32_t chnl0_outcnt_eof_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_int_raw_reg_t;
+
+/** Type of chnl0_int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** chnl0_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
+         *  set to 1.
+         */
+        uint32_t chnl0_outcnt_eof_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_int_st_reg_t;
+
+/** Type of chnl0_int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** chnl0_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for reg_out_cnt_eof_int_st register.
+         */
+        uint32_t chnl0_outcnt_eof_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_int_ena_reg_t;
+
+/** Type of chnl0_int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** chnl0_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
+         */
+        uint32_t chnl0_outcnt_eof_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl0_int_clr_reg_t;
+
+/** Type of chnl1_int_raw register
+ *  Raw interrupt status
+ */
+typedef union {
+    struct {
+        /** chnl1_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  This interrupt raw bit turns to high level when the counter approach to reg_out_len.
+         */
+        uint32_t chnl1_outcnt_eof_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_int_raw_reg_t;
+
+/** Type of chnl1_int_st register
+ *  Masked interrupt status
+ */
+typedef union {
+    struct {
+        /** chnl1_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
+         *  This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
+         *  set to 1.
+         */
+        uint32_t chnl1_outcnt_eof_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_int_st_reg_t;
+
+/** Type of chnl1_int_ena register
+ *  Interrupt enable bits
+ */
+typedef union {
+    struct {
+        /** chnl1_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
+         *  This is the enable bit for reg_out_cnt_eof_int_st register.
+         */
+        uint32_t chnl1_outcnt_eof_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_int_ena_reg_t;
+
+/** Type of chnl1_int_clr register
+ *  Interrupt clear bits
+ */
+typedef union {
+    struct {
+        /** chnl1_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
+         */
+        uint32_t chnl1_outcnt_eof_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} asrc_chnl1_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of chnl0_out_cnt register
+ *  Status Registers
+ */
+typedef union {
+    struct {
+        /** chnl0_out_cnt : RO; bitpos: [23:0]; default: 0;
+         *  Represents the bytes numbers send to the DMA when EOF occurs.
+         */
+        uint32_t chnl0_out_cnt:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} asrc_chnl0_out_cnt_reg_t;
+
+/** Type of chnl1_out_cnt register
+ *  Status Registers
+ */
+typedef union {
+    struct {
+        /** chnl1_out_cnt : RO; bitpos: [23:0]; default: 0;
+         *  Represents the data byte numbers send to the DMA when EOF occurs.
+         */
+        uint32_t chnl1_out_cnt:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} asrc_chnl1_out_cnt_reg_t;
+
+
+/** Group: DEBUG registers */
+/** Type of chnl0_trace1 register
+ *  Debug Register1
+ */
+typedef union {
+    struct {
+        /** chnl0_out_inc : RO; bitpos: [23:0]; default: 0;
+         *  Represents the samples numbers send to the DMA
+         */
+        uint32_t chnl0_out_inc:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} asrc_chnl0_trace1_reg_t;
+
+/** Type of chnl1_trace1 register
+ *  Debug Register1
+ */
+typedef union {
+    struct {
+        /** chnl1_out_inc : RO; bitpos: [23:0]; default: 0;
+         *  Represents the data byte numbers send to the DMA
+         */
+        uint32_t chnl1_out_inc:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} asrc_chnl1_trace1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of sys register
+ *  Control and configuration
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Reserved
+         */
+        uint32_t clk_en:1;
+        /** chnl0_clk_fo : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to make channel0 clock free run.
+         */
+        uint32_t chnl0_clk_fo:1;
+        /** chnl1_clk_fo : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to make channel1 clock free run.
+         */
+        uint32_t chnl1_clk_fo:1;
+        /** chnl0_outfifo_clk_fo : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to make channel0 outfifo clock free run.
+         */
+        uint32_t chnl0_outfifo_clk_fo:1;
+        /** chnl0_infifo_clk_fo : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to make channel0 infifo clock free run.
+         */
+        uint32_t chnl0_infifo_clk_fo:1;
+        /** chnl1_outfifo_clk_fo : R/W; bitpos: [5]; default: 0;
+         *  Set this bit to make channel1 outfifo clock free run.
+         */
+        uint32_t chnl1_outfifo_clk_fo:1;
+        /** chnl1_infifo_clk_fo : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to make channel1 infifo clock free run.
+         */
+        uint32_t chnl1_infifo_clk_fo:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} asrc_sys_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37777984;
+         *  Reserved
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} asrc_date_reg_t;
+
+
+typedef struct {
+    volatile asrc_chnl0_cfg0_reg_t chnl0_cfg0;
+    volatile asrc_chnl0_cfg1_reg_t chnl0_cfg1;
+    volatile asrc_chnl0_cfg2_reg_t chnl0_cfg2;
+    volatile asrc_chnl0_cfg3_reg_t chnl0_cfg3;
+    volatile asrc_chnl0_cfg4_reg_t chnl0_cfg4;
+    volatile asrc_chnl0_cfg5_reg_t chnl0_cfg5;
+    volatile asrc_chnl0_cfg6_reg_t chnl0_cfg6;
+    volatile asrc_chnl0_fifo_ctrl_reg_t chnl0_fifo_ctrl;
+    volatile asrc_chnl0_int_raw_reg_t chnl0_int_raw;
+    volatile asrc_chnl0_int_st_reg_t chnl0_int_st;
+    volatile asrc_chnl0_int_ena_reg_t chnl0_int_ena;
+    volatile asrc_chnl0_int_clr_reg_t chnl0_int_clr;
+    volatile asrc_chnl0_out_cnt_reg_t chnl0_out_cnt;
+    uint32_t reserved_034;
+    volatile asrc_chnl0_trace1_reg_t chnl0_trace1;
+    volatile asrc_chnl1_cfg0_reg_t chnl1_cfg0;
+    volatile asrc_chnl1_cfg1_reg_t chnl1_cfg1;
+    volatile asrc_chnl1_cfg2_reg_t chnl1_cfg2;
+    volatile asrc_chnl1_cfg3_reg_t chnl1_cfg3;
+    volatile asrc_chnl1_cfg4_reg_t chnl1_cfg4;
+    volatile asrc_chnl1_cfg5_reg_t chnl1_cfg5;
+    volatile asrc_chnl1_cfg6_reg_t chnl1_cfg6;
+    volatile asrc_chnl1_fifo_ctrl_reg_t chnl1_fifo_ctrl;
+    volatile asrc_chnl1_int_raw_reg_t chnl1_int_raw;
+    volatile asrc_chnl1_int_st_reg_t chnl1_int_st;
+    volatile asrc_chnl1_int_ena_reg_t chnl1_int_ena;
+    volatile asrc_chnl1_int_clr_reg_t chnl1_int_clr;
+    volatile asrc_chnl1_out_cnt_reg_t chnl1_out_cnt;
+    uint32_t reserved_070;
+    volatile asrc_chnl1_trace1_reg_t chnl1_trace1;
+    uint32_t reserved_078[32];
+    volatile asrc_sys_reg_t sys;
+    volatile asrc_date_reg_t date;
+} asrc_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(asrc_dev_t) == 0x100, "Invalid size of asrc_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/axi_dma_reg.h b/components/soc/esp32s31/register/soc/axi_dma_reg.h
new file mode 100644
index 00000000000..66032624603
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/axi_dma_reg.h
@@ -0,0 +1,5757 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_DMA_IN_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x0)
+/** AXI_DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_M  (AXI_DMA_IN_DONE_CH0_INT_RAW_V << AXI_DMA_IN_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH0_REG register
+ *  Masked interrupt of channel 0
+ */
+#define AXI_DMA_IN_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4)
+/** AXI_DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ST_M  (AXI_DMA_IN_DONE_CH0_INT_ST_V << AXI_DMA_IN_DONE_CH0_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH0_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH0_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel 0
+ */
+#define AXI_DMA_IN_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x8)
+/** AXI_DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_M  (AXI_DMA_IN_DONE_CH0_INT_ENA_V << AXI_DMA_IN_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel 0
+ */
+#define AXI_DMA_IN_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0xc)
+/** AXI_DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_M  (AXI_DMA_IN_DONE_CH0_INT_CLR_V << AXI_DMA_IN_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH0_REG register
+ *  Configure 0 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x10)
+/** AXI_DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH0    (BIT(0))
+#define AXI_DMA_IN_RST_CH0_M  (AXI_DMA_IN_RST_CH0_V << AXI_DMA_IN_RST_CH0_S)
+#define AXI_DMA_IN_RST_CH0_V  0x00000001U
+#define AXI_DMA_IN_RST_CH0_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH0_M  (AXI_DMA_IN_LOOP_TEST_CH0_V << AXI_DMA_IN_LOOP_TEST_CH0_S)
+#define AXI_DMA_IN_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH0_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH0    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH0_M  (AXI_DMA_MEM_TRANS_EN_CH0_V << AXI_DMA_MEM_TRANS_EN_CH0_S)
+#define AXI_DMA_MEM_TRANS_EN_CH0_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH0_S  2
+/** AXI_DMA_IN_ETM_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH0    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH0_M  (AXI_DMA_IN_ETM_EN_CH0_V << AXI_DMA_IN_ETM_EN_CH0_S)
+#define AXI_DMA_IN_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH0_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH0 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH0_V << AXI_DMA_IN_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH0_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH0 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH0    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH0_M  (AXI_DMA_IN_CMD_DISABLE_CH0_V << AXI_DMA_IN_CMD_DISABLE_CH0_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH0_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH0    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_M  (AXI_DMA_IN_ECC_AEC_EN_CH0_V << AXI_DMA_IN_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH0_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH0    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH0_M  (AXI_DMA_INDSCR_BURST_EN_CH0_V << AXI_DMA_INDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH0_S  9
+
+/** AXI_DMA_IN_CONF1_CH0_REG register
+ *  Configure 1 register of Rx channel 0
+ */
+#define AXI_DMA_IN_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14)
+/** AXI_DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH0_M  (AXI_DMA_IN_CHECK_OWNER_CH0_V << AXI_DMA_IN_CHECK_OWNER_CH0_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18)
+/** AXI_DMA_INFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH0_M  (AXI_DMA_INFIFO_L3_FULL_CH0_V << AXI_DMA_INFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_M  (AXI_DMA_INFIFO_L3_EMPTY_CH0_V << AXI_DMA_INFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_M  (AXI_DMA_INFIFO_L3_CNT_CH0_V << AXI_DMA_INFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH0_M  (AXI_DMA_INFIFO_L3_UDF_CH0_V << AXI_DMA_INFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH0_M  (AXI_DMA_INFIFO_L3_OVF_CH0_V << AXI_DMA_INFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH0_M  (AXI_DMA_INFIFO_L1_FULL_CH0_V << AXI_DMA_INFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_M  (AXI_DMA_INFIFO_L1_EMPTY_CH0_V << AXI_DMA_INFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH0_M  (AXI_DMA_INFIFO_L1_UDF_CH0_V << AXI_DMA_INFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH0_M  (AXI_DMA_INFIFO_L1_OVF_CH0_V << AXI_DMA_INFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH0_M  (AXI_DMA_INFIFO_L2_FULL_CH0_V << AXI_DMA_INFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_M  (AXI_DMA_INFIFO_L2_EMPTY_CH0_V << AXI_DMA_INFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH0_M  (AXI_DMA_INFIFO_L2_UDF_CH0_V << AXI_DMA_INFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH0_M  (AXI_DMA_INFIFO_L2_OVF_CH0_V << AXI_DMA_INFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH0_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH0    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_M  (AXI_DMA_IN_BUF_HUNGRY_CH0_V << AXI_DMA_IN_BUF_HUNGRY_CH0_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH0_S  31
+
+/** AXI_DMA_IN_POP_CH0_REG register
+ *  Pop control register of Rx channel 0
+ */
+#define AXI_DMA_IN_POP_CH0_REG (DR_REG_AXI_DMA_BASE + 0x1c)
+/** AXI_DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH0    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_M  (AXI_DMA_INFIFO_RDATA_CH0_V << AXI_DMA_INFIFO_RDATA_CH0_S)
+#define AXI_DMA_INFIFO_RDATA_CH0_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH0_S  0
+/** AXI_DMA_INFIFO_POP_CH0 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH0    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH0_M  (AXI_DMA_INFIFO_POP_CH0_V << AXI_DMA_INFIFO_POP_CH0_S)
+#define AXI_DMA_INFIFO_POP_CH0_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH0_S  12
+
+/** AXI_DMA_IN_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x20)
+/** AXI_DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH0    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH0_M  (AXI_DMA_INLINK_AUTO_RET_CH0_V << AXI_DMA_INLINK_AUTO_RET_CH0_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH0_S  0
+/** AXI_DMA_INLINK_STOP_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH0    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH0_M  (AXI_DMA_INLINK_STOP_CH0_V << AXI_DMA_INLINK_STOP_CH0_S)
+#define AXI_DMA_INLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH0_S  1
+/** AXI_DMA_INLINK_START_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH0    (BIT(2))
+#define AXI_DMA_INLINK_START_CH0_M  (AXI_DMA_INLINK_START_CH0_V << AXI_DMA_INLINK_START_CH0_S)
+#define AXI_DMA_INLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH0_S  2
+/** AXI_DMA_INLINK_RESTART_CH0 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH0    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH0_M  (AXI_DMA_INLINK_RESTART_CH0_V << AXI_DMA_INLINK_RESTART_CH0_S)
+#define AXI_DMA_INLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH0_S  3
+/** AXI_DMA_INLINK_PARK_CH0 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH0    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH0_M  (AXI_DMA_INLINK_PARK_CH0_V << AXI_DMA_INLINK_PARK_CH0_S)
+#define AXI_DMA_INLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH0_S  4
+
+/** AXI_DMA_IN_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+#define AXI_DMA_IN_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x24)
+/** AXI_DMA_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_M  (AXI_DMA_INLINK_ADDR_CH0_V << AXI_DMA_INLINK_ADDR_CH0_S)
+#define AXI_DMA_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_STATE_CH0_REG register
+ *  Receive status of Rx channel 0
+ */
+#define AXI_DMA_IN_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_M  (AXI_DMA_INLINK_DSCR_ADDR_CH0_V << AXI_DMA_INLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_M  (AXI_DMA_IN_DSCR_STATE_CH0_V << AXI_DMA_IN_DSCR_STATE_CH0_S)
+#define AXI_DMA_IN_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH0_S  18
+/** AXI_DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH0    0x00000007U
+#define AXI_DMA_IN_STATE_CH0_M  (AXI_DMA_IN_STATE_CH0_V << AXI_DMA_IN_STATE_CH0_S)
+#define AXI_DMA_IN_STATE_CH0_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH0_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x30)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_CH0_REG register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x34)
+/** AXI_DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_M  (AXI_DMA_INLINK_DSCR_CH0_V << AXI_DMA_INLINK_DSCR_CH0_S)
+#define AXI_DMA_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH0_REG register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x38)
+/** AXI_DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_M  (AXI_DMA_INLINK_DSCR_BF0_CH0_V << AXI_DMA_INLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH0_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x3c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_M  (AXI_DMA_INLINK_DSCR_BF1_CH0_V << AXI_DMA_INLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_IN_PRI_CH0_REG register
+ *  Priority register of Rx channel 0
+ */
+#define AXI_DMA_IN_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x40)
+/** AXI_DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH0    0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_M  (AXI_DMA_RX_PRI_CH0_V << AXI_DMA_RX_PRI_CH0_S)
+#define AXI_DMA_RX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH0_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH0_V << AXI_DMA_RX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Rx channel 0
+ */
+#define AXI_DMA_IN_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x44)
+/** AXI_DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_M  (AXI_DMA_PERI_IN_SEL_CH0_V << AXI_DMA_PERI_IN_SEL_CH0_S)
+#define AXI_DMA_PERI_IN_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH0_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x48)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_M  (AXI_DMA_IN_CRC_INIT_DATA_CH0_V << AXI_DMA_IN_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x4c)
+/** AXI_DMA_RX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_M  (AXI_DMA_RX_CRC_WIDTH_CH0_V << AXI_DMA_RX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH0 register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x50)
+/** AXI_DMA_IN_CRC_CLEAR_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH0_M  (AXI_DMA_IN_CRC_CLEAR_CH0_V << AXI_DMA_IN_CRC_CLEAR_CH0_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x54)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x58)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x5c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x60)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x64)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x68)
+/** AXI_DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_M  (AXI_DMA_IN_DONE_CH1_INT_RAW_V << AXI_DMA_IN_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH1_REG register
+ *  Masked interrupt of channel 1
+ */
+#define AXI_DMA_IN_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x6c)
+/** AXI_DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ST_M  (AXI_DMA_IN_DONE_CH1_INT_ST_V << AXI_DMA_IN_DONE_CH1_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH1_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH1_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel 1
+ */
+#define AXI_DMA_IN_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x70)
+/** AXI_DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_M  (AXI_DMA_IN_DONE_CH1_INT_ENA_V << AXI_DMA_IN_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel 1
+ */
+#define AXI_DMA_IN_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x74)
+/** AXI_DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_M  (AXI_DMA_IN_DONE_CH1_INT_CLR_V << AXI_DMA_IN_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH1_REG register
+ *  Configure 0 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x78)
+/** AXI_DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH1    (BIT(0))
+#define AXI_DMA_IN_RST_CH1_M  (AXI_DMA_IN_RST_CH1_V << AXI_DMA_IN_RST_CH1_S)
+#define AXI_DMA_IN_RST_CH1_V  0x00000001U
+#define AXI_DMA_IN_RST_CH1_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH1_M  (AXI_DMA_IN_LOOP_TEST_CH1_V << AXI_DMA_IN_LOOP_TEST_CH1_S)
+#define AXI_DMA_IN_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH1_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH1    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH1_M  (AXI_DMA_MEM_TRANS_EN_CH1_V << AXI_DMA_MEM_TRANS_EN_CH1_S)
+#define AXI_DMA_MEM_TRANS_EN_CH1_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH1_S  2
+/** AXI_DMA_IN_ETM_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH1    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH1_M  (AXI_DMA_IN_ETM_EN_CH1_V << AXI_DMA_IN_ETM_EN_CH1_S)
+#define AXI_DMA_IN_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH1_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH1 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH1_V << AXI_DMA_IN_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH1_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH1 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH1    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH1_M  (AXI_DMA_IN_CMD_DISABLE_CH1_V << AXI_DMA_IN_CMD_DISABLE_CH1_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH1_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH1    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_M  (AXI_DMA_IN_ECC_AEC_EN_CH1_V << AXI_DMA_IN_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH1_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH1    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH1_M  (AXI_DMA_INDSCR_BURST_EN_CH1_V << AXI_DMA_INDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH1_S  9
+
+/** AXI_DMA_IN_CONF1_CH1_REG register
+ *  Configure 1 register of Rx channel 1
+ */
+#define AXI_DMA_IN_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x7c)
+/** AXI_DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH1_M  (AXI_DMA_IN_CHECK_OWNER_CH1_V << AXI_DMA_IN_CHECK_OWNER_CH1_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x80)
+/** AXI_DMA_INFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH1_M  (AXI_DMA_INFIFO_L3_FULL_CH1_V << AXI_DMA_INFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_M  (AXI_DMA_INFIFO_L3_EMPTY_CH1_V << AXI_DMA_INFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_M  (AXI_DMA_INFIFO_L3_CNT_CH1_V << AXI_DMA_INFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH1_M  (AXI_DMA_INFIFO_L3_UDF_CH1_V << AXI_DMA_INFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH1_M  (AXI_DMA_INFIFO_L3_OVF_CH1_V << AXI_DMA_INFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH1_M  (AXI_DMA_INFIFO_L1_FULL_CH1_V << AXI_DMA_INFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_M  (AXI_DMA_INFIFO_L1_EMPTY_CH1_V << AXI_DMA_INFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH1_M  (AXI_DMA_INFIFO_L1_UDF_CH1_V << AXI_DMA_INFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH1_M  (AXI_DMA_INFIFO_L1_OVF_CH1_V << AXI_DMA_INFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH1_M  (AXI_DMA_INFIFO_L2_FULL_CH1_V << AXI_DMA_INFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_M  (AXI_DMA_INFIFO_L2_EMPTY_CH1_V << AXI_DMA_INFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH1_M  (AXI_DMA_INFIFO_L2_UDF_CH1_V << AXI_DMA_INFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH1_M  (AXI_DMA_INFIFO_L2_OVF_CH1_V << AXI_DMA_INFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH1_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH1    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_M  (AXI_DMA_IN_BUF_HUNGRY_CH1_V << AXI_DMA_IN_BUF_HUNGRY_CH1_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH1_S  31
+
+/** AXI_DMA_IN_POP_CH1_REG register
+ *  Pop control register of Rx channel 1
+ */
+#define AXI_DMA_IN_POP_CH1_REG (DR_REG_AXI_DMA_BASE + 0x84)
+/** AXI_DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH1    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_M  (AXI_DMA_INFIFO_RDATA_CH1_V << AXI_DMA_INFIFO_RDATA_CH1_S)
+#define AXI_DMA_INFIFO_RDATA_CH1_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH1_S  0
+/** AXI_DMA_INFIFO_POP_CH1 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH1    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH1_M  (AXI_DMA_INFIFO_POP_CH1_V << AXI_DMA_INFIFO_POP_CH1_S)
+#define AXI_DMA_INFIFO_POP_CH1_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH1_S  12
+
+/** AXI_DMA_IN_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x88)
+/** AXI_DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH1    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH1_M  (AXI_DMA_INLINK_AUTO_RET_CH1_V << AXI_DMA_INLINK_AUTO_RET_CH1_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH1_S  0
+/** AXI_DMA_INLINK_STOP_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH1    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH1_M  (AXI_DMA_INLINK_STOP_CH1_V << AXI_DMA_INLINK_STOP_CH1_S)
+#define AXI_DMA_INLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH1_S  1
+/** AXI_DMA_INLINK_START_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH1    (BIT(2))
+#define AXI_DMA_INLINK_START_CH1_M  (AXI_DMA_INLINK_START_CH1_V << AXI_DMA_INLINK_START_CH1_S)
+#define AXI_DMA_INLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH1_S  2
+/** AXI_DMA_INLINK_RESTART_CH1 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH1    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH1_M  (AXI_DMA_INLINK_RESTART_CH1_V << AXI_DMA_INLINK_RESTART_CH1_S)
+#define AXI_DMA_INLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH1_S  3
+/** AXI_DMA_INLINK_PARK_CH1 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH1    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH1_M  (AXI_DMA_INLINK_PARK_CH1_V << AXI_DMA_INLINK_PARK_CH1_S)
+#define AXI_DMA_INLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH1_S  4
+
+/** AXI_DMA_IN_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Rx channel 1
+ */
+#define AXI_DMA_IN_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x8c)
+/** AXI_DMA_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_M  (AXI_DMA_INLINK_ADDR_CH1_V << AXI_DMA_INLINK_ADDR_CH1_S)
+#define AXI_DMA_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_STATE_CH1_REG register
+ *  Receive status of Rx channel 1
+ */
+#define AXI_DMA_IN_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x90)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_M  (AXI_DMA_INLINK_DSCR_ADDR_CH1_V << AXI_DMA_INLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_M  (AXI_DMA_IN_DSCR_STATE_CH1_V << AXI_DMA_IN_DSCR_STATE_CH1_S)
+#define AXI_DMA_IN_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH1_S  18
+/** AXI_DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH1    0x00000007U
+#define AXI_DMA_IN_STATE_CH1_M  (AXI_DMA_IN_STATE_CH1_V << AXI_DMA_IN_STATE_CH1_S)
+#define AXI_DMA_IN_STATE_CH1_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH1_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 1
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x94)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 1
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x98)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_CH1_REG register
+ *  Current inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x9c)
+/** AXI_DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_M  (AXI_DMA_INLINK_DSCR_CH1_V << AXI_DMA_INLINK_DSCR_CH1_S)
+#define AXI_DMA_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH1_REG register
+ *  The last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa0)
+/** AXI_DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_M  (AXI_DMA_INLINK_DSCR_BF0_CH1_V << AXI_DMA_INLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH1_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 1
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa4)
+/** AXI_DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_M  (AXI_DMA_INLINK_DSCR_BF1_CH1_V << AXI_DMA_INLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_IN_PRI_CH1_REG register
+ *  Priority register of Rx channel 1
+ */
+#define AXI_DMA_IN_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0xa8)
+/** AXI_DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH1    0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_M  (AXI_DMA_RX_PRI_CH1_V << AXI_DMA_RX_PRI_CH1_S)
+#define AXI_DMA_RX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH1_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH1_V << AXI_DMA_RX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Rx channel 1
+ */
+#define AXI_DMA_IN_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0xac)
+/** AXI_DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_M  (AXI_DMA_PERI_IN_SEL_CH1_V << AXI_DMA_PERI_IN_SEL_CH1_S)
+#define AXI_DMA_PERI_IN_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH1_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb0)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_M  (AXI_DMA_IN_CRC_INIT_DATA_CH1_V << AXI_DMA_IN_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig rx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb4)
+/** AXI_DMA_RX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_M  (AXI_DMA_RX_CRC_WIDTH_CH1_V << AXI_DMA_RX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xb8)
+/** AXI_DMA_IN_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH1_M  (AXI_DMA_IN_CRC_CLEAR_CH1_V << AXI_DMA_IN_CRC_CLEAR_CH1_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0xbc)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc0)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc4)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0xc8)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0xcc)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_IN_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd0)
+/** AXI_DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_M  (AXI_DMA_IN_DONE_CH2_INT_RAW_V << AXI_DMA_IN_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+ *  turns to high level when the last data pointed by one inlink descriptor has been
+ *  received and no data error is detected for Rx channel 0.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V << AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when data error is detected only in the
+ *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+ *  interrupt is reserved.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V << AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+ *  including owner error and the second and third word error of inlink descriptor for
+ *  Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+ *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_RAW_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_RAW_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_RAW_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_RAW_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  overflow.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_RAW_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+ *  underflow.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_RAW_S  10
+
+/** AXI_DMA_IN_INT_ST_CH2_REG register
+ *  Masked interrupt of channel 2
+ */
+#define AXI_DMA_IN_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd4)
+/** AXI_DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ST_M  (AXI_DMA_IN_DONE_CH2_INT_ST_V << AXI_DMA_IN_DONE_CH2_INT_ST_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ST_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ST_S  4
+/** AXI_DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_OVF_CH2_INT_ST_S  5
+/** AXI_DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_UDF_CH2_INT_ST_S  6
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ST_S  7
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ST_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ST_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ST_S  10
+
+/** AXI_DMA_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel 2
+ */
+#define AXI_DMA_IN_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0xd8)
+/** AXI_DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_M  (AXI_DMA_IN_DONE_CH2_INT_ENA_V << AXI_DMA_IN_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V << AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V << AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_ENA_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_ENA_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_ENA_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_ENA_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_ENA_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_ENA_S  10
+
+/** AXI_DMA_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel 2
+ */
+#define AXI_DMA_IN_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xdc)
+/** AXI_DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_M  (AXI_DMA_IN_DONE_CH2_INT_CLR_V << AXI_DMA_IN_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V << AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_M  (AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V << AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M  (AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S  4
+/** AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_INT_CLR_S  5
+/** AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_INT_CLR_S  6
+/** AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_INT_CLR_S  7
+/** AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_INT_CLR_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_INT_CLR_S  9
+/** AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_INT_CLR_S  10
+
+/** AXI_DMA_IN_CONF0_CH2_REG register
+ *  Configure 0 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe0)
+/** AXI_DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+ */
+#define AXI_DMA_IN_RST_CH2    (BIT(0))
+#define AXI_DMA_IN_RST_CH2_M  (AXI_DMA_IN_RST_CH2_V << AXI_DMA_IN_RST_CH2_S)
+#define AXI_DMA_IN_RST_CH2_V  0x00000001U
+#define AXI_DMA_IN_RST_CH2_S  0
+/** AXI_DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_IN_LOOP_TEST_CH2_M  (AXI_DMA_IN_LOOP_TEST_CH2_V << AXI_DMA_IN_LOOP_TEST_CH2_S)
+#define AXI_DMA_IN_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_IN_LOOP_TEST_CH2_S  1
+/** AXI_DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+ *  AXI_DMA.
+ */
+#define AXI_DMA_MEM_TRANS_EN_CH2    (BIT(2))
+#define AXI_DMA_MEM_TRANS_EN_CH2_M  (AXI_DMA_MEM_TRANS_EN_CH2_V << AXI_DMA_MEM_TRANS_EN_CH2_S)
+#define AXI_DMA_MEM_TRANS_EN_CH2_V  0x00000001U
+#define AXI_DMA_MEM_TRANS_EN_CH2_S  2
+/** AXI_DMA_IN_ETM_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_IN_ETM_EN_CH2    (BIT(3))
+#define AXI_DMA_IN_ETM_EN_CH2_M  (AXI_DMA_IN_ETM_EN_CH2_V << AXI_DMA_IN_ETM_EN_CH2_S)
+#define AXI_DMA_IN_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ETM_EN_CH2_S  3
+/** AXI_DMA_IN_BURST_SIZE_SEL_CH2 : R/W; bitpos: [6:4]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_M  (AXI_DMA_IN_BURST_SIZE_SEL_CH2_V << AXI_DMA_IN_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_IN_BURST_SIZE_SEL_CH2_S  4
+/** AXI_DMA_IN_CMD_DISABLE_CH2 : R/W; bitpos: [7]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_IN_CMD_DISABLE_CH2    (BIT(7))
+#define AXI_DMA_IN_CMD_DISABLE_CH2_M  (AXI_DMA_IN_CMD_DISABLE_CH2_V << AXI_DMA_IN_CMD_DISABLE_CH2_S)
+#define AXI_DMA_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_IN_CMD_DISABLE_CH2_S  7
+/** AXI_DMA_IN_ECC_AEC_EN_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_IN_ECC_AEC_EN_CH2    (BIT(8))
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_M  (AXI_DMA_IN_ECC_AEC_EN_CH2_V << AXI_DMA_IN_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_IN_ECC_AEC_EN_CH2_S  8
+/** AXI_DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_INDSCR_BURST_EN_CH2    (BIT(9))
+#define AXI_DMA_INDSCR_BURST_EN_CH2_M  (AXI_DMA_INDSCR_BURST_EN_CH2_V << AXI_DMA_INDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_INDSCR_BURST_EN_CH2_S  9
+
+/** AXI_DMA_IN_CONF1_CH2_REG register
+ *  Configure 1 register of Rx channel 2
+ */
+#define AXI_DMA_IN_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe4)
+/** AXI_DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_IN_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_IN_CHECK_OWNER_CH2_M  (AXI_DMA_IN_CHECK_OWNER_CH2_V << AXI_DMA_IN_CHECK_OWNER_CH2_S)
+#define AXI_DMA_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_IN_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_INFIFO_STATUS_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0xe8)
+/** AXI_DMA_INFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 1;
+ *  L3 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_INFIFO_L3_FULL_CH2_M  (AXI_DMA_INFIFO_L3_FULL_CH2_V << AXI_DMA_INFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_INFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_M  (AXI_DMA_INFIFO_L3_EMPTY_CH2_V << AXI_DMA_INFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_INFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_M  (AXI_DMA_INFIFO_L3_CNT_CH2_V << AXI_DMA_INFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_INFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_INFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_INFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_INFIFO_L3_UDF_CH2_M  (AXI_DMA_INFIFO_L3_UDF_CH2_V << AXI_DMA_INFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_INFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_INFIFO_L3_OVF_CH2_M  (AXI_DMA_INFIFO_L3_OVF_CH2_V << AXI_DMA_INFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_INFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Rx FIFO full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_INFIFO_L1_FULL_CH2_M  (AXI_DMA_INFIFO_L1_FULL_CH2_V << AXI_DMA_INFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_INFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Rx FIFO empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_M  (AXI_DMA_INFIFO_L1_EMPTY_CH2_V << AXI_DMA_INFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_INFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_L1_UDF_CH2_M  (AXI_DMA_INFIFO_L1_UDF_CH2_V << AXI_DMA_INFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_INFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_INFIFO_L1_OVF_CH2_M  (AXI_DMA_INFIFO_L1_OVF_CH2_V << AXI_DMA_INFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_INFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Rx RAM full signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_INFIFO_L2_FULL_CH2_M  (AXI_DMA_INFIFO_L2_FULL_CH2_V << AXI_DMA_INFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_INFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_INFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Rx RAM empty signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_M  (AXI_DMA_INFIFO_L2_EMPTY_CH2_V << AXI_DMA_INFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_INFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Rx FIFO under flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_INFIFO_L2_UDF_CH2_M  (AXI_DMA_INFIFO_L2_UDF_CH2_V << AXI_DMA_INFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_INFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_INFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Rx FIFO over flow signal for Rx channel 0.
+ */
+#define AXI_DMA_INFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_INFIFO_L2_OVF_CH2_M  (AXI_DMA_INFIFO_L2_OVF_CH2_V << AXI_DMA_INFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_INFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V << AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_IN_REMAIN_UNDER_8B_CH2_S  30
+/** AXI_DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [31]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_BUF_HUNGRY_CH2    (BIT(31))
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_M  (AXI_DMA_IN_BUF_HUNGRY_CH2_V << AXI_DMA_IN_BUF_HUNGRY_CH2_S)
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_V  0x00000001U
+#define AXI_DMA_IN_BUF_HUNGRY_CH2_S  31
+
+/** AXI_DMA_IN_POP_CH2_REG register
+ *  Pop control register of Rx channel 2
+ */
+#define AXI_DMA_IN_POP_CH2_REG (DR_REG_AXI_DMA_BASE + 0xec)
+/** AXI_DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048;
+ *  This register stores the data popping from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_RDATA_CH2    0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_M  (AXI_DMA_INFIFO_RDATA_CH2_V << AXI_DMA_INFIFO_RDATA_CH2_S)
+#define AXI_DMA_INFIFO_RDATA_CH2_V  0x00000FFFU
+#define AXI_DMA_INFIFO_RDATA_CH2_S  0
+/** AXI_DMA_INFIFO_POP_CH2 : WT; bitpos: [12]; default: 0;
+ *  Set this bit to pop data from AXI_DMA FIFO.
+ */
+#define AXI_DMA_INFIFO_POP_CH2    (BIT(12))
+#define AXI_DMA_INFIFO_POP_CH2_M  (AXI_DMA_INFIFO_POP_CH2_V << AXI_DMA_INFIFO_POP_CH2_S)
+#define AXI_DMA_INFIFO_POP_CH2_V  0x00000001U
+#define AXI_DMA_INFIFO_POP_CH2_S  12
+
+/** AXI_DMA_IN_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf0)
+/** AXI_DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [0]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address when there are some
+ *  errors in current receiving data.
+ */
+#define AXI_DMA_INLINK_AUTO_RET_CH2    (BIT(0))
+#define AXI_DMA_INLINK_AUTO_RET_CH2_M  (AXI_DMA_INLINK_AUTO_RET_CH2_V << AXI_DMA_INLINK_AUTO_RET_CH2_S)
+#define AXI_DMA_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_AUTO_RET_CH2_S  0
+/** AXI_DMA_INLINK_STOP_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_STOP_CH2    (BIT(1))
+#define AXI_DMA_INLINK_STOP_CH2_M  (AXI_DMA_INLINK_STOP_CH2_V << AXI_DMA_INLINK_STOP_CH2_S)
+#define AXI_DMA_INLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_STOP_CH2_S  1
+/** AXI_DMA_INLINK_START_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define AXI_DMA_INLINK_START_CH2    (BIT(2))
+#define AXI_DMA_INLINK_START_CH2_M  (AXI_DMA_INLINK_START_CH2_V << AXI_DMA_INLINK_START_CH2_S)
+#define AXI_DMA_INLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_START_CH2_S  2
+/** AXI_DMA_INLINK_RESTART_CH2 : WT; bitpos: [3]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define AXI_DMA_INLINK_RESTART_CH2    (BIT(3))
+#define AXI_DMA_INLINK_RESTART_CH2_M  (AXI_DMA_INLINK_RESTART_CH2_V << AXI_DMA_INLINK_RESTART_CH2_S)
+#define AXI_DMA_INLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_RESTART_CH2_S  3
+/** AXI_DMA_INLINK_PARK_CH2 : RO; bitpos: [4]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define AXI_DMA_INLINK_PARK_CH2    (BIT(4))
+#define AXI_DMA_INLINK_PARK_CH2_M  (AXI_DMA_INLINK_PARK_CH2_V << AXI_DMA_INLINK_PARK_CH2_S)
+#define AXI_DMA_INLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_INLINK_PARK_CH2_S  4
+
+/** AXI_DMA_IN_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Rx channel 2
+ */
+#define AXI_DMA_IN_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf4)
+/** AXI_DMA_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 20 least significant bits of the first inlink descriptor's
+ *  address.
+ */
+#define AXI_DMA_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_M  (AXI_DMA_INLINK_ADDR_CH2_V << AXI_DMA_INLINK_ADDR_CH2_S)
+#define AXI_DMA_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_STATE_CH2_REG register
+ *  Receive status of Rx channel 2
+ */
+#define AXI_DMA_IN_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0xf8)
+/** AXI_DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_M  (AXI_DMA_INLINK_DSCR_ADDR_CH2_V << AXI_DMA_INLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_INLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_M  (AXI_DMA_IN_DSCR_STATE_CH2_V << AXI_DMA_IN_DSCR_STATE_CH2_S)
+#define AXI_DMA_IN_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_IN_DSCR_STATE_CH2_S  18
+/** AXI_DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_IN_STATE_CH2    0x00000007U
+#define AXI_DMA_IN_STATE_CH2_M  (AXI_DMA_IN_STATE_CH2_V << AXI_DMA_IN_STATE_CH2_S)
+#define AXI_DMA_IN_STATE_CH2_V  0x00000007U
+#define AXI_DMA_IN_STATE_CH2_S  20
+
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when EOF occurs of Rx channel 2
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0xfc)
+/** AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Inlink descriptor address when errors occur of Rx channel 2
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x100)
+/** AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data. Only used when peripheral is UHCI0.
+ */
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_M  (AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V << AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_CH2_REG register
+ *  Current inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x104)
+/** AXI_DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current inlink descriptor x.
+ */
+#define AXI_DMA_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_M  (AXI_DMA_INLINK_DSCR_CH2_V << AXI_DMA_INLINK_DSCR_CH2_S)
+#define AXI_DMA_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF0_CH2_REG register
+ *  The last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x108)
+/** AXI_DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor x-1.
+ */
+#define AXI_DMA_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_M  (AXI_DMA_INLINK_DSCR_BF0_CH2_V << AXI_DMA_INLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_IN_DSCR_BF1_CH2_REG register
+ *  The second-to-last inlink descriptor address of Rx channel 2
+ */
+#define AXI_DMA_IN_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x10c)
+/** AXI_DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor x-2.
+ */
+#define AXI_DMA_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_M  (AXI_DMA_INLINK_DSCR_BF1_CH2_V << AXI_DMA_INLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_INLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_IN_PRI_CH2_REG register
+ *  Priority register of Rx channel 2
+ */
+#define AXI_DMA_IN_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x110)
+/** AXI_DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_RX_PRI_CH2    0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_M  (AXI_DMA_RX_PRI_CH2_V << AXI_DMA_RX_PRI_CH2_S)
+#define AXI_DMA_RX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_RX_PRI_CH2_S  0
+/** AXI_DMA_RX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Rx channel 0
+ */
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_RX_CH_ARB_WEIGH_CH2_V << AXI_DMA_RX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_RX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_IN_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Rx channel 2
+ */
+#define AXI_DMA_IN_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x114)
+/** AXI_DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_IN_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_M  (AXI_DMA_PERI_IN_SEL_CH2_V << AXI_DMA_PERI_IN_SEL_CH2_S)
+#define AXI_DMA_PERI_IN_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_IN_SEL_CH2_S  0
+
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x118)
+/** AXI_DMA_IN_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of rx crc initial value
+ */
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_M  (AXI_DMA_IN_CRC_INIT_DATA_CH2_V << AXI_DMA_IN_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig rx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x11c)
+/** AXI_DMA_RX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_M  (AXI_DMA_RX_CRC_WIDTH_CH2_V << AXI_DMA_RX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_RX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_RX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_RX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_IN_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x120)
+/** AXI_DMA_IN_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of rx crc result
+ */
+#define AXI_DMA_IN_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_IN_CRC_CLEAR_CH2_M  (AXI_DMA_IN_CRC_CLEAR_CH2_V << AXI_DMA_IN_CRC_CLEAR_CH2_S)
+#define AXI_DMA_IN_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_IN_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x124)
+/** AXI_DMA_IN_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of rx
+ */
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V << AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_IN_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x128)
+/** AXI_DMA_RX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable rx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x12c)
+/** AXI_DMA_RX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x130)
+/** AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x134)
+/** AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_RX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH0_REG register
+ *  Raw status interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_RAW_CH0_REG (DR_REG_AXI_DMA_BASE + 0x138)
+/** AXI_DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_M  (AXI_DMA_OUT_DONE_CH0_INT_RAW_V << AXI_DMA_OUT_DONE_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt of channel0
+ */
+#define AXI_DMA_OUT_INT_ST_CH0_REG (DR_REG_AXI_DMA_BASE + 0x13c)
+/** AXI_DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_M  (AXI_DMA_OUT_DONE_CH0_INT_ST_V << AXI_DMA_OUT_DONE_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_EOF_CH0_INT_ST_V << AXI_DMA_OUT_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH0_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH0_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of channel0
+ */
+#define AXI_DMA_OUT_INT_ENA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x140)
+/** AXI_DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_M  (AXI_DMA_OUT_DONE_CH0_INT_ENA_V << AXI_DMA_OUT_DONE_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of channel0
+ */
+#define AXI_DMA_OUT_INT_CLR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x144)
+/** AXI_DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_M  (AXI_DMA_OUT_DONE_CH0_INT_CLR_V << AXI_DMA_OUT_DONE_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH0_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH0_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH0_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH0_REG register
+ *  Configure 0 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x148)
+/** AXI_DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH0    (BIT(0))
+#define AXI_DMA_OUT_RST_CH0_M  (AXI_DMA_OUT_RST_CH0_V << AXI_DMA_OUT_RST_CH0_S)
+#define AXI_DMA_OUT_RST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH0_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH0    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH0_M  (AXI_DMA_OUT_LOOP_TEST_CH0_V << AXI_DMA_OUT_LOOP_TEST_CH0_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH0_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_M  (AXI_DMA_OUT_AUTO_WRBACK_CH0_V << AXI_DMA_OUT_AUTO_WRBACK_CH0_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH0_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH0    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH0_M  (AXI_DMA_OUT_EOF_MODE_CH0_V << AXI_DMA_OUT_EOF_MODE_CH0_S)
+#define AXI_DMA_OUT_EOF_MODE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH0_S  3
+/** AXI_DMA_OUT_ETM_EN_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH0    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH0_M  (AXI_DMA_OUT_ETM_EN_CH0_V << AXI_DMA_OUT_ETM_EN_CH0_S)
+#define AXI_DMA_OUT_ETM_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH0_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH0 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH0_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch0
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH0    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_M  (AXI_DMA_OUT_CMD_DISABLE_CH0_V << AXI_DMA_OUT_CMD_DISABLE_CH0_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH0_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH0 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_M  (AXI_DMA_OUT_ECC_AEC_EN_CH0_V << AXI_DMA_OUT_ECC_AEC_EN_CH0_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH0_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_M  (AXI_DMA_OUTDSCR_BURST_EN_CH0_V << AXI_DMA_OUTDSCR_BURST_EN_CH0_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH0_S  10
+
+/** AXI_DMA_OUT_CONF1_CH0_REG register
+ *  Configure 1 register of Tx channel0
+ */
+#define AXI_DMA_OUT_CONF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x14c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH0    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_M  (AXI_DMA_OUT_CHECK_OWNER_CH0_V << AXI_DMA_OUT_CHECK_OWNER_CH0_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH0_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH0_REG register
+ *  Transmit FIFO status of Tx channel0
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_AXI_DMA_BASE + 0x150)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH0 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_M  (AXI_DMA_OUTFIFO_L3_FULL_CH0_V << AXI_DMA_OUTFIFO_L3_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH0_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH0 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH0_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH0 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_M  (AXI_DMA_OUTFIFO_L3_CNT_CH0_V << AXI_DMA_OUTFIFO_L3_CNT_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH0_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH0 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_M  (AXI_DMA_OUTFIFO_L3_UDF_CH0_V << AXI_DMA_OUTFIFO_L3_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH0_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH0 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_M  (AXI_DMA_OUTFIFO_L3_OVF_CH0_V << AXI_DMA_OUTFIFO_L3_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH0_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH0 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_M  (AXI_DMA_OUTFIFO_L1_FULL_CH0_V << AXI_DMA_OUTFIFO_L1_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH0_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH0 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH0_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH0 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_M  (AXI_DMA_OUTFIFO_L1_UDF_CH0_V << AXI_DMA_OUTFIFO_L1_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH0_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH0 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_M  (AXI_DMA_OUTFIFO_L1_OVF_CH0_V << AXI_DMA_OUTFIFO_L1_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH0_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH0 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_M  (AXI_DMA_OUTFIFO_L2_FULL_CH0_V << AXI_DMA_OUTFIFO_L2_FULL_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH0_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH0 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH0_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH0 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_M  (AXI_DMA_OUTFIFO_L2_UDF_CH0_V << AXI_DMA_OUTFIFO_L2_UDF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH0_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH0 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_M  (AXI_DMA_OUTFIFO_L2_OVF_CH0_V << AXI_DMA_OUTFIFO_L2_OVF_CH0_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH0_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH0_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH0_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH0_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH0_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH0_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH0_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH0_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH0_S  30
+
+/** AXI_DMA_OUT_PUSH_CH0_REG register
+ *  Push control register of Tx channel0
+ */
+#define AXI_DMA_OUT_PUSH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x154)
+/** AXI_DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH0    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_M  (AXI_DMA_OUTFIFO_WDATA_CH0_V << AXI_DMA_OUTFIFO_WDATA_CH0_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH0_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH0_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH0 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH0    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH0_M  (AXI_DMA_OUTFIFO_PUSH_CH0_V << AXI_DMA_OUTFIFO_PUSH_CH0_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH0_S  9
+
+/** AXI_DMA_OUT_LINK1_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x158)
+/** AXI_DMA_OUTLINK_STOP_CH0 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH0    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH0_M  (AXI_DMA_OUTLINK_STOP_CH0_V << AXI_DMA_OUTLINK_STOP_CH0_S)
+#define AXI_DMA_OUTLINK_STOP_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH0_S  0
+/** AXI_DMA_OUTLINK_START_CH0 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH0    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH0_M  (AXI_DMA_OUTLINK_START_CH0_V << AXI_DMA_OUTLINK_START_CH0_S)
+#define AXI_DMA_OUTLINK_START_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH0_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH0 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH0    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH0_M  (AXI_DMA_OUTLINK_RESTART_CH0_V << AXI_DMA_OUTLINK_RESTART_CH0_S)
+#define AXI_DMA_OUTLINK_RESTART_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH0_S  2
+/** AXI_DMA_OUTLINK_PARK_CH0 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH0    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH0_M  (AXI_DMA_OUTLINK_PARK_CH0_V << AXI_DMA_OUTLINK_PARK_CH0_S)
+#define AXI_DMA_OUTLINK_PARK_CH0_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH0_S  3
+
+/** AXI_DMA_OUT_LINK2_CH0_REG register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+#define AXI_DMA_OUT_LINK2_CH0_REG (DR_REG_AXI_DMA_BASE + 0x15c)
+/** AXI_DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_M  (AXI_DMA_OUTLINK_ADDR_CH0_V << AXI_DMA_OUTLINK_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_STATE_CH0_REG register
+ *  Transmit status of Tx channel0
+ */
+#define AXI_DMA_OUT_STATE_CH0_REG (DR_REG_AXI_DMA_BASE + 0x160)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH0_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH0    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_M  (AXI_DMA_OUT_DSCR_STATE_CH0_V << AXI_DMA_OUT_DSCR_STATE_CH0_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH0_S  18
+/** AXI_DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH0    0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_M  (AXI_DMA_OUT_STATE_CH0_V << AXI_DMA_OUT_STATE_CH0_S)
+#define AXI_DMA_OUT_STATE_CH0_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH0_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x164)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x168)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_CH0_REG register
+ *  Current outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x16c)
+/** AXI_DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_M  (AXI_DMA_OUTLINK_DSCR_CH0_V << AXI_DMA_OUTLINK_DSCR_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH0_REG register
+ *  The last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_AXI_DMA_BASE + 0x170)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH0_V << AXI_DMA_OUTLINK_DSCR_BF0_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH0_REG register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x174)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH0_V << AXI_DMA_OUTLINK_DSCR_BF1_CH0_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** AXI_DMA_OUT_PRI_CH0_REG register
+ *  Priority register of Tx channel0.
+ */
+#define AXI_DMA_OUT_PRI_CH0_REG (DR_REG_AXI_DMA_BASE + 0x178)
+/** AXI_DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH0    0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_M  (AXI_DMA_TX_PRI_CH0_V << AXI_DMA_TX_PRI_CH0_S)
+#define AXI_DMA_TX_PRI_CH0_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH0_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH0_V << AXI_DMA_TX_CH_ARB_WEIGH_CH0_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH0_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH0_REG register
+ *  Peripheral selection of Tx channel0
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x17c)
+/** AXI_DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH0    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_M  (AXI_DMA_PERI_OUT_SEL_CH0_V << AXI_DMA_PERI_OUT_SEL_CH0_S)
+#define AXI_DMA_PERI_OUT_SEL_CH0_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x180)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH0_V << AXI_DMA_OUT_CRC_INIT_DATA_CH0_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH0_REG register
+ *  This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0_REG (DR_REG_AXI_DMA_BASE + 0x184)
+/** AXI_DMA_TX_CRC_WIDTH_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH0    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_M  (AXI_DMA_TX_CRC_WIDTH_CH0_V << AXI_DMA_TX_CRC_WIDTH_CH0_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH0_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH0_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH0_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG register
+ *  This register is used to clear ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x188)
+/** AXI_DMA_OUT_CRC_CLEAR_CH0_REG : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH0    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_M  (AXI_DMA_OUT_CRC_CLEAR_CH0_V << AXI_DMA_OUT_CRC_CLEAR_CH0_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH0_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG register
+ *  This register is used to store ch0 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_REG (DR_REG_AXI_DMA_BASE + 0x18c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x190)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0_REG register
+ *  This register is used to config ch0 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x194)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_REG (DR_REG_AXI_DMA_BASE + 0x198)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH0_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_REG (DR_REG_AXI_DMA_BASE + 0x19c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH0_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH1_REG register
+ *  Raw status interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_RAW_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a0)
+/** AXI_DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_M  (AXI_DMA_OUT_DONE_CH1_INT_RAW_V << AXI_DMA_OUT_DONE_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt of channel1
+ */
+#define AXI_DMA_OUT_INT_ST_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a4)
+/** AXI_DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_M  (AXI_DMA_OUT_DONE_CH1_INT_ST_V << AXI_DMA_OUT_DONE_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_EOF_CH1_INT_ST_V << AXI_DMA_OUT_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH1_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH1_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of channel1
+ */
+#define AXI_DMA_OUT_INT_ENA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1a8)
+/** AXI_DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_M  (AXI_DMA_OUT_DONE_CH1_INT_ENA_V << AXI_DMA_OUT_DONE_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of channel1
+ */
+#define AXI_DMA_OUT_INT_CLR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ac)
+/** AXI_DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_M  (AXI_DMA_OUT_DONE_CH1_INT_CLR_V << AXI_DMA_OUT_DONE_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH1_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH1_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH1_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH1_REG register
+ *  Configure 0 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b0)
+/** AXI_DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel1 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH1    (BIT(0))
+#define AXI_DMA_OUT_RST_CH1_M  (AXI_DMA_OUT_RST_CH1_V << AXI_DMA_OUT_RST_CH1_S)
+#define AXI_DMA_OUT_RST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH1_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH1    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH1_M  (AXI_DMA_OUT_LOOP_TEST_CH1_V << AXI_DMA_OUT_LOOP_TEST_CH1_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH1_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_M  (AXI_DMA_OUT_AUTO_WRBACK_CH1_V << AXI_DMA_OUT_AUTO_WRBACK_CH1_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH1_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel1 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH1    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH1_M  (AXI_DMA_OUT_EOF_MODE_CH1_V << AXI_DMA_OUT_EOF_MODE_CH1_S)
+#define AXI_DMA_OUT_EOF_MODE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH1_S  3
+/** AXI_DMA_OUT_ETM_EN_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel1 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH1    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH1_M  (AXI_DMA_OUT_ETM_EN_CH1_V << AXI_DMA_OUT_ETM_EN_CH1_S)
+#define AXI_DMA_OUT_ETM_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH1_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH1 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH1_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch1
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH1    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_M  (AXI_DMA_OUT_CMD_DISABLE_CH1_V << AXI_DMA_OUT_CMD_DISABLE_CH1_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH1_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH1 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_M  (AXI_DMA_OUT_ECC_AEC_EN_CH1_V << AXI_DMA_OUT_ECC_AEC_EN_CH1_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH1_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel1 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_M  (AXI_DMA_OUTDSCR_BURST_EN_CH1_V << AXI_DMA_OUTDSCR_BURST_EN_CH1_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH1_S  10
+
+/** AXI_DMA_OUT_CONF1_CH1_REG register
+ *  Configure 1 register of Tx channel1
+ */
+#define AXI_DMA_OUT_CONF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b4)
+/** AXI_DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH1    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_M  (AXI_DMA_OUT_CHECK_OWNER_CH1_V << AXI_DMA_OUT_CHECK_OWNER_CH1_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH1_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH1_REG register
+ *  Transmit FIFO status of Tx channel1
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1b8)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH1 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_M  (AXI_DMA_OUTFIFO_L3_FULL_CH1_V << AXI_DMA_OUTFIFO_L3_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH1_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH1 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH1_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH1 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_M  (AXI_DMA_OUTFIFO_L3_CNT_CH1_V << AXI_DMA_OUTFIFO_L3_CNT_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH1_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH1 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_M  (AXI_DMA_OUTFIFO_L3_UDF_CH1_V << AXI_DMA_OUTFIFO_L3_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH1_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH1 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_M  (AXI_DMA_OUTFIFO_L3_OVF_CH1_V << AXI_DMA_OUTFIFO_L3_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH1_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH1 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_M  (AXI_DMA_OUTFIFO_L1_FULL_CH1_V << AXI_DMA_OUTFIFO_L1_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH1_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH1 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH1_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH1 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_M  (AXI_DMA_OUTFIFO_L1_UDF_CH1_V << AXI_DMA_OUTFIFO_L1_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH1_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH1 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_M  (AXI_DMA_OUTFIFO_L1_OVF_CH1_V << AXI_DMA_OUTFIFO_L1_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH1_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH1 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_M  (AXI_DMA_OUTFIFO_L2_FULL_CH1_V << AXI_DMA_OUTFIFO_L2_FULL_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH1_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH1 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH1_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH1 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_M  (AXI_DMA_OUTFIFO_L2_UDF_CH1_V << AXI_DMA_OUTFIFO_L2_UDF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH1_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH1 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_M  (AXI_DMA_OUTFIFO_L2_OVF_CH1_V << AXI_DMA_OUTFIFO_L2_OVF_CH1_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH1_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH1_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH1_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH1_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH1_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH1_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH1_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH1_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH1_S  30
+
+/** AXI_DMA_OUT_PUSH_CH1_REG register
+ *  Push control register of Tx channel1
+ */
+#define AXI_DMA_OUT_PUSH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1bc)
+/** AXI_DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH1    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_M  (AXI_DMA_OUTFIFO_WDATA_CH1_V << AXI_DMA_OUTFIFO_WDATA_CH1_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH1_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH1_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH1 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH1    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH1_M  (AXI_DMA_OUTFIFO_PUSH_CH1_V << AXI_DMA_OUTFIFO_PUSH_CH1_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH1_S  9
+
+/** AXI_DMA_OUT_LINK1_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c0)
+/** AXI_DMA_OUTLINK_STOP_CH1 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH1    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH1_M  (AXI_DMA_OUTLINK_STOP_CH1_V << AXI_DMA_OUTLINK_STOP_CH1_S)
+#define AXI_DMA_OUTLINK_STOP_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH1_S  0
+/** AXI_DMA_OUTLINK_START_CH1 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH1    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH1_M  (AXI_DMA_OUTLINK_START_CH1_V << AXI_DMA_OUTLINK_START_CH1_S)
+#define AXI_DMA_OUTLINK_START_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH1_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH1 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH1    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH1_M  (AXI_DMA_OUTLINK_RESTART_CH1_V << AXI_DMA_OUTLINK_RESTART_CH1_S)
+#define AXI_DMA_OUTLINK_RESTART_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH1_S  2
+/** AXI_DMA_OUTLINK_PARK_CH1 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH1    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH1_M  (AXI_DMA_OUTLINK_PARK_CH1_V << AXI_DMA_OUTLINK_PARK_CH1_S)
+#define AXI_DMA_OUTLINK_PARK_CH1_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH1_S  3
+
+/** AXI_DMA_OUT_LINK2_CH1_REG register
+ *  Link descriptor configure and control register of Tx channel1
+ */
+#define AXI_DMA_OUT_LINK2_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c4)
+/** AXI_DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_M  (AXI_DMA_OUTLINK_ADDR_CH1_V << AXI_DMA_OUTLINK_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_STATE_CH1_REG register
+ *  Transmit status of Tx channel1
+ */
+#define AXI_DMA_OUT_STATE_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1c8)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH1_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH1    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_M  (AXI_DMA_OUT_DSCR_STATE_CH1_V << AXI_DMA_OUT_DSCR_STATE_CH1_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH1_S  18
+/** AXI_DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH1    0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_M  (AXI_DMA_OUT_STATE_CH1_V << AXI_DMA_OUT_STATE_CH1_S)
+#define AXI_DMA_OUT_STATE_CH1_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH1_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1cc)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel1
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d0)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_CH1_REG register
+ *  Current outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d4)
+/** AXI_DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_M  (AXI_DMA_OUTLINK_DSCR_CH1_V << AXI_DMA_OUTLINK_DSCR_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH1_REG register
+ *  The last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1d8)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH1_V << AXI_DMA_OUTLINK_DSCR_BF0_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH1_REG register
+ *  The second-to-last outlink descriptor address of Tx channel1
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1dc)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH1_V << AXI_DMA_OUTLINK_DSCR_BF1_CH1_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** AXI_DMA_OUT_PRI_CH1_REG register
+ *  Priority register of Tx channel1.
+ */
+#define AXI_DMA_OUT_PRI_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e0)
+/** AXI_DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH1    0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_M  (AXI_DMA_TX_PRI_CH1_V << AXI_DMA_TX_PRI_CH1_S)
+#define AXI_DMA_TX_PRI_CH1_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH1_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH1_V << AXI_DMA_TX_CH_ARB_WEIGH_CH1_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH1_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH1_REG register
+ *  Peripheral selection of Tx channel1
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e4)
+/** AXI_DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH1    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_M  (AXI_DMA_PERI_OUT_SEL_CH1_V << AXI_DMA_PERI_OUT_SEL_CH1_S)
+#define AXI_DMA_PERI_OUT_SEL_CH1_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG register
+ *  This register is used to config ch1 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1e8)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH1_V << AXI_DMA_OUT_CRC_INIT_DATA_CH1_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH1_REG register
+ *  This register is used to confiig tx ch1 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1ec)
+/** AXI_DMA_TX_CRC_WIDTH_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH1    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_M  (AXI_DMA_TX_CRC_WIDTH_CH1_V << AXI_DMA_TX_CRC_WIDTH_CH1_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH1_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH1_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH1_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH1_REG register
+ *  This register is used to clear ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f0)
+/** AXI_DMA_OUT_CRC_CLEAR_CH1 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH1    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_M  (AXI_DMA_OUT_CRC_CLEAR_CH1_V << AXI_DMA_OUT_CRC_CLEAR_CH1_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH1_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG register
+ *  This register is used to store ch1 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f4)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG register
+ *  This resister is used to config ch1 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1f8)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1_REG register
+ *  This register is used to config ch1 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x1fc)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_REG (DR_REG_AXI_DMA_BASE + 0x200)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH1_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_REG (DR_REG_AXI_DMA_BASE + 0x204)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH1_S  0
+
+/** AXI_DMA_OUT_INT_RAW_CH2_REG register
+ *  Raw status interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_RAW_CH2_REG (DR_REG_AXI_DMA_BASE + 0x208)
+/** AXI_DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel0.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_M  (AXI_DMA_OUT_DONE_CH2_INT_RAW_V << AXI_DMA_OUT_DONE_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_RAW_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel0.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_RAW_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+ *  including owner error and the second and third word error of outlink descriptor for
+ *  Tx channel0.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_RAW_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_RAW_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_RAW_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_RAW_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  overflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_RAW_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+ *  underflow.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_RAW_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the dma switch to new link for Tx
+ *  channel0.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_RAW_S  10
+
+/** AXI_DMA_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt of channel2
+ */
+#define AXI_DMA_OUT_INT_ST_CH2_REG (DR_REG_AXI_DMA_BASE + 0x20c)
+/** AXI_DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_M  (AXI_DMA_OUT_DONE_CH2_INT_ST_V << AXI_DMA_OUT_DONE_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ST_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_EOF_CH2_INT_ST_V << AXI_DMA_OUT_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ST_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** AXI_DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST    (BIT(4))
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_OVF_CH2_INT_ST_S  4
+/** AXI_DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST    (BIT(5))
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_UDF_CH2_INT_ST_S  5
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST    (BIT(6))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ST_S  6
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST    (BIT(7))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ST_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ST_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ST_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ST_S  10
+
+/** AXI_DMA_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of channel2
+ */
+#define AXI_DMA_OUT_INT_ENA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x210)
+/** AXI_DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_M  (AXI_DMA_OUT_DONE_CH2_INT_ENA_V << AXI_DMA_OUT_DONE_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_ENA_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_ENA_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_ENA_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_ENA_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_ENA_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_ENA_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_ENA_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_ENA_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_ENA_S  10
+
+/** AXI_DMA_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of channel2
+ */
+#define AXI_DMA_OUT_INT_CLR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x214)
+/** AXI_DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_M  (AXI_DMA_OUT_DONE_CH2_INT_CLR_V << AXI_DMA_OUT_DONE_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DONE_CH2_INT_CLR_S  0
+/** AXI_DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_EOF_CH2_INT_CLR_S  1
+/** AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_M  (AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M  (AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR    (BIT(4))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_INT_CLR_S  4
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR    (BIT(5))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_INT_CLR_S  5
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR    (BIT(6))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_INT_CLR_S  6
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR    (BIT(7))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_INT_CLR_S  7
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_INT_CLR_S  8
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_INT_CLR_S  9
+/** AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
+ */
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR    (BIT(10))
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_M  (AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V << AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S)
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_V  0x00000001U
+#define AXI_DMA_OUT_LINK_SWITCH_CH2_INT_CLR_S  10
+
+/** AXI_DMA_OUT_CONF0_CH2_REG register
+ *  Configure 0 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x218)
+/** AXI_DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This bit is used to reset AXI_DMA channel2 Tx FSM and Tx FIFO pointer.
+ */
+#define AXI_DMA_OUT_RST_CH2    (BIT(0))
+#define AXI_DMA_OUT_RST_CH2_M  (AXI_DMA_OUT_RST_CH2_V << AXI_DMA_OUT_RST_CH2_S)
+#define AXI_DMA_OUT_RST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RST_CH2_S  0
+/** AXI_DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_LOOP_TEST_CH2    (BIT(1))
+#define AXI_DMA_OUT_LOOP_TEST_CH2_M  (AXI_DMA_OUT_LOOP_TEST_CH2_V << AXI_DMA_OUT_LOOP_TEST_CH2_S)
+#define AXI_DMA_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define AXI_DMA_OUT_LOOP_TEST_CH2_S  1
+/** AXI_DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+ *  has been transmitted.
+ */
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2    (BIT(2))
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_M  (AXI_DMA_OUT_AUTO_WRBACK_CH2_V << AXI_DMA_OUT_AUTO_WRBACK_CH2_S)
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define AXI_DMA_OUT_AUTO_WRBACK_CH2_S  2
+/** AXI_DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1;
+ *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel2 is
+ *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+ */
+#define AXI_DMA_OUT_EOF_MODE_CH2    (BIT(3))
+#define AXI_DMA_OUT_EOF_MODE_CH2_M  (AXI_DMA_OUT_EOF_MODE_CH2_V << AXI_DMA_OUT_EOF_MODE_CH2_S)
+#define AXI_DMA_OUT_EOF_MODE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_EOF_MODE_CH2_S  3
+/** AXI_DMA_OUT_ETM_EN_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to 1 to enable etm control mode, dma Tx channel2 is triggered by etm
+ *  task.
+ */
+#define AXI_DMA_OUT_ETM_EN_CH2    (BIT(4))
+#define AXI_DMA_OUT_ETM_EN_CH2_M  (AXI_DMA_OUT_ETM_EN_CH2_V << AXI_DMA_OUT_ETM_EN_CH2_S)
+#define AXI_DMA_OUT_ETM_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ETM_EN_CH2_S  4
+/** AXI_DMA_OUT_BURST_SIZE_SEL_CH2 : R/W; bitpos: [7:5]; default: 0;
+ *  3'b000-3'b100:burst length 8byte~128byte
+ */
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2    0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_M  (AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V << AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S)
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_V  0x00000007U
+#define AXI_DMA_OUT_BURST_SIZE_SEL_CH2_S  5
+/** AXI_DMA_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [8]; default: 0;
+ *  1:mean disable cmd of this ch2
+ */
+#define AXI_DMA_OUT_CMD_DISABLE_CH2    (BIT(8))
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_M  (AXI_DMA_OUT_CMD_DISABLE_CH2_V << AXI_DMA_OUT_CMD_DISABLE_CH2_S)
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CMD_DISABLE_CH2_S  8
+/** AXI_DMA_OUT_ECC_AEC_EN_CH2 : R/W; bitpos: [9]; default: 0;
+ *  1: mean access ecc or aes domain,0: mean not
+ */
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2    (BIT(9))
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_M  (AXI_DMA_OUT_ECC_AEC_EN_CH2_V << AXI_DMA_OUT_ECC_AEC_EN_CH2_S)
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUT_ECC_AEC_EN_CH2_S  9
+/** AXI_DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel2 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2    (BIT(10))
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_M  (AXI_DMA_OUTDSCR_BURST_EN_CH2_V << AXI_DMA_OUTDSCR_BURST_EN_CH2_S)
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define AXI_DMA_OUTDSCR_BURST_EN_CH2_S  10
+
+/** AXI_DMA_OUT_CONF1_CH2_REG register
+ *  Configure 1 register of Tx channel2
+ */
+#define AXI_DMA_OUT_CONF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x21c)
+/** AXI_DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define AXI_DMA_OUT_CHECK_OWNER_CH2    (BIT(12))
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_M  (AXI_DMA_OUT_CHECK_OWNER_CH2_V << AXI_DMA_OUT_CHECK_OWNER_CH2_S)
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CHECK_OWNER_CH2_S  12
+
+/** AXI_DMA_OUTFIFO_STATUS_CH2_REG register
+ *  Transmit FIFO status of Tx channel2
+ */
+#define AXI_DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_AXI_DMA_BASE + 0x220)
+/** AXI_DMA_OUTFIFO_L3_FULL_CH2 : RO; bitpos: [0]; default: 0;
+ *  L3 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2    (BIT(0))
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_M  (AXI_DMA_OUTFIFO_L3_FULL_CH2_V << AXI_DMA_OUTFIFO_L3_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_FULL_CH2_S  0
+/** AXI_DMA_OUTFIFO_L3_EMPTY_CH2 : RO; bitpos: [1]; default: 1;
+ *  L3 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2    (BIT(1))
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_EMPTY_CH2_S  1
+/** AXI_DMA_OUTFIFO_L3_CNT_CH2 : RO; bitpos: [7:2]; default: 0;
+ *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2    0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_M  (AXI_DMA_OUTFIFO_L3_CNT_CH2_V << AXI_DMA_OUTFIFO_L3_CNT_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_OUTFIFO_L3_CNT_CH2_S  2
+/** AXI_DMA_OUTFIFO_L3_UDF_CH2 : RO; bitpos: [8]; default: 0;
+ *  L3 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2    (BIT(8))
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_M  (AXI_DMA_OUTFIFO_L3_UDF_CH2_V << AXI_DMA_OUTFIFO_L3_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_UDF_CH2_S  8
+/** AXI_DMA_OUTFIFO_L3_OVF_CH2 : RO; bitpos: [9]; default: 0;
+ *  L3 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_M  (AXI_DMA_OUTFIFO_L3_OVF_CH2_V << AXI_DMA_OUTFIFO_L3_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L3_OVF_CH2_S  9
+/** AXI_DMA_OUTFIFO_L1_FULL_CH2 : RO; bitpos: [10]; default: 0;
+ *  L1 Tx FIFO full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2    (BIT(10))
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_M  (AXI_DMA_OUTFIFO_L1_FULL_CH2_V << AXI_DMA_OUTFIFO_L1_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_FULL_CH2_S  10
+/** AXI_DMA_OUTFIFO_L1_EMPTY_CH2 : RO; bitpos: [11]; default: 1;
+ *  L1 Tx FIFO empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2    (BIT(11))
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_EMPTY_CH2_S  11
+/** AXI_DMA_OUTFIFO_L1_UDF_CH2 : RO; bitpos: [12]; default: 0;
+ *  L1 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2    (BIT(12))
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_M  (AXI_DMA_OUTFIFO_L1_UDF_CH2_V << AXI_DMA_OUTFIFO_L1_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_UDF_CH2_S  12
+/** AXI_DMA_OUTFIFO_L1_OVF_CH2 : RO; bitpos: [13]; default: 0;
+ *  L1 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2    (BIT(13))
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_M  (AXI_DMA_OUTFIFO_L1_OVF_CH2_V << AXI_DMA_OUTFIFO_L1_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L1_OVF_CH2_S  13
+/** AXI_DMA_OUTFIFO_L2_FULL_CH2 : RO; bitpos: [14]; default: 0;
+ *  L2 Tx RAM full signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2    (BIT(14))
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_M  (AXI_DMA_OUTFIFO_L2_FULL_CH2_V << AXI_DMA_OUTFIFO_L2_FULL_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_FULL_CH2_S  14
+/** AXI_DMA_OUTFIFO_L2_EMPTY_CH2 : RO; bitpos: [15]; default: 1;
+ *  L2 Tx RAM empty signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2    (BIT(15))
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_M  (AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V << AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_EMPTY_CH2_S  15
+/** AXI_DMA_OUTFIFO_L2_UDF_CH2 : RO; bitpos: [16]; default: 0;
+ *  L2 Tx FIFO under flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2    (BIT(16))
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_M  (AXI_DMA_OUTFIFO_L2_UDF_CH2_V << AXI_DMA_OUTFIFO_L2_UDF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_UDF_CH2_S  16
+/** AXI_DMA_OUTFIFO_L2_OVF_CH2 : RO; bitpos: [17]; default: 0;
+ *  L2 Tx FIFO over flow signal for Tx channel0.
+ */
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2    (BIT(17))
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_M  (AXI_DMA_OUTFIFO_L2_OVF_CH2_V << AXI_DMA_OUTFIFO_L2_OVF_CH2_S)
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_L2_OVF_CH2_S  17
+/** AXI_DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2    (BIT(23))
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_1B_CH2_S  23
+/** AXI_DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2    (BIT(24))
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_2B_CH2_S  24
+/** AXI_DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2    (BIT(25))
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_3B_CH2_S  25
+/** AXI_DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2    (BIT(26))
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_4B_CH2_S  26
+/** AXI_DMA_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [27]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2    (BIT(27))
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_5B_CH2_S  27
+/** AXI_DMA_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [28]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2    (BIT(28))
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_6B_CH2_S  28
+/** AXI_DMA_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [29]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2    (BIT(29))
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_7B_CH2_S  29
+/** AXI_DMA_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [30]; default: 1;
+ *  reserved
+ */
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2    (BIT(30))
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_M  (AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V << AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S)
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define AXI_DMA_OUT_REMAIN_UNDER_8B_CH2_S  30
+
+/** AXI_DMA_OUT_PUSH_CH2_REG register
+ *  Push control register of Tx channel2
+ */
+#define AXI_DMA_OUT_PUSH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x224)
+/** AXI_DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0;
+ *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_WDATA_CH2    0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_M  (AXI_DMA_OUTFIFO_WDATA_CH2_V << AXI_DMA_OUTFIFO_WDATA_CH2_S)
+#define AXI_DMA_OUTFIFO_WDATA_CH2_V  0x000001FFU
+#define AXI_DMA_OUTFIFO_WDATA_CH2_S  0
+/** AXI_DMA_OUTFIFO_PUSH_CH2 : WT; bitpos: [9]; default: 0;
+ *  Set this bit to push data into AXI_DMA FIFO.
+ */
+#define AXI_DMA_OUTFIFO_PUSH_CH2    (BIT(9))
+#define AXI_DMA_OUTFIFO_PUSH_CH2_M  (AXI_DMA_OUTFIFO_PUSH_CH2_V << AXI_DMA_OUTFIFO_PUSH_CH2_S)
+#define AXI_DMA_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define AXI_DMA_OUTFIFO_PUSH_CH2_S  9
+
+/** AXI_DMA_OUT_LINK1_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x228)
+/** AXI_DMA_OUTLINK_STOP_CH2 : WT; bitpos: [0]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_STOP_CH2    (BIT(0))
+#define AXI_DMA_OUTLINK_STOP_CH2_M  (AXI_DMA_OUTLINK_STOP_CH2_V << AXI_DMA_OUTLINK_STOP_CH2_S)
+#define AXI_DMA_OUTLINK_STOP_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_STOP_CH2_S  0
+/** AXI_DMA_OUTLINK_START_CH2 : WT; bitpos: [1]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define AXI_DMA_OUTLINK_START_CH2    (BIT(1))
+#define AXI_DMA_OUTLINK_START_CH2_M  (AXI_DMA_OUTLINK_START_CH2_V << AXI_DMA_OUTLINK_START_CH2_S)
+#define AXI_DMA_OUTLINK_START_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_START_CH2_S  1
+/** AXI_DMA_OUTLINK_RESTART_CH2 : WT; bitpos: [2]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define AXI_DMA_OUTLINK_RESTART_CH2    (BIT(2))
+#define AXI_DMA_OUTLINK_RESTART_CH2_M  (AXI_DMA_OUTLINK_RESTART_CH2_V << AXI_DMA_OUTLINK_RESTART_CH2_S)
+#define AXI_DMA_OUTLINK_RESTART_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_RESTART_CH2_S  2
+/** AXI_DMA_OUTLINK_PARK_CH2 : RO; bitpos: [3]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define AXI_DMA_OUTLINK_PARK_CH2    (BIT(3))
+#define AXI_DMA_OUTLINK_PARK_CH2_M  (AXI_DMA_OUTLINK_PARK_CH2_V << AXI_DMA_OUTLINK_PARK_CH2_S)
+#define AXI_DMA_OUTLINK_PARK_CH2_V  0x00000001U
+#define AXI_DMA_OUTLINK_PARK_CH2_S  3
+
+/** AXI_DMA_OUT_LINK2_CH2_REG register
+ *  Link descriptor configure and control register of Tx channel2
+ */
+#define AXI_DMA_OUT_LINK2_CH2_REG (DR_REG_AXI_DMA_BASE + 0x22c)
+/** AXI_DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the 32 least significant bits of the first outlink
+ *  descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_M  (AXI_DMA_OUTLINK_ADDR_CH2_V << AXI_DMA_OUTLINK_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_STATE_CH2_REG register
+ *  Transmit status of Tx channel2
+ */
+#define AXI_DMA_OUT_STATE_CH2_REG (DR_REG_AXI_DMA_BASE + 0x230)
+/** AXI_DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_M  (AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V << AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define AXI_DMA_OUTLINK_DSCR_ADDR_CH2_S  0
+/** AXI_DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_DSCR_STATE_CH2    0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_M  (AXI_DMA_OUT_DSCR_STATE_CH2_V << AXI_DMA_OUT_DSCR_STATE_CH2_S)
+#define AXI_DMA_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define AXI_DMA_OUT_DSCR_STATE_CH2_S  18
+/** AXI_DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_OUT_STATE_CH2    0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_M  (AXI_DMA_OUT_STATE_CH2_V << AXI_DMA_OUT_STATE_CH2_S)
+#define AXI_DMA_OUT_STATE_CH2_V  0x00000007U
+#define AXI_DMA_OUT_STATE_CH2_S  20
+
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x234)
+/** AXI_DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register
+ *  The last outlink descriptor address when EOF occurs of Tx channel2
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x238)
+/** AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor before the last outlink
+ *  descriptor.
+ */
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_M  (AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_EOF_BFR_DES_ADDR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_CH2_REG register
+ *  Current outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x23c)
+/** AXI_DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the current outlink descriptor y.
+ */
+#define AXI_DMA_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_M  (AXI_DMA_OUTLINK_DSCR_CH2_V << AXI_DMA_OUTLINK_DSCR_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF0_CH2_REG register
+ *  The last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_AXI_DMA_BASE + 0x240)
+/** AXI_DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor y-1.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF0_CH2_V << AXI_DMA_OUTLINK_DSCR_BF0_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** AXI_DMA_OUT_DSCR_BF1_CH2_REG register
+ *  The second-to-last outlink descriptor address of Tx channel2
+ */
+#define AXI_DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x244)
+/** AXI_DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor x-2.
+ */
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_M  (AXI_DMA_OUTLINK_DSCR_BF1_CH2_V << AXI_DMA_OUTLINK_DSCR_BF1_CH2_S)
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** AXI_DMA_OUT_PRI_CH2_REG register
+ *  Priority register of Tx channel2.
+ */
+#define AXI_DMA_OUT_PRI_CH2_REG (DR_REG_AXI_DMA_BASE + 0x248)
+/** AXI_DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  The priority of Tx channel0. The larger of the value the higher of the priority.
+ */
+#define AXI_DMA_TX_PRI_CH2    0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_M  (AXI_DMA_TX_PRI_CH2_V << AXI_DMA_TX_PRI_CH2_S)
+#define AXI_DMA_TX_PRI_CH2_V  0x0000000FU
+#define AXI_DMA_TX_PRI_CH2_S  0
+/** AXI_DMA_TX_CH_ARB_WEIGH_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  The weight of Tx channel0
+ */
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2    0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_M  (AXI_DMA_TX_CH_ARB_WEIGH_CH2_V << AXI_DMA_TX_CH_ARB_WEIGH_CH2_S)
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_V  0x0000000FU
+#define AXI_DMA_TX_CH_ARB_WEIGH_CH2_S  4
+/** AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2 : R/W; bitpos: [8]; default: 0;
+ *  0: mean not optimization weight function ,1: mean optimization
+ */
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2    (BIT(8))
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_M  (AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V << AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S)
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_V  0x00000001U
+#define AXI_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_S  8
+
+/** AXI_DMA_OUT_PERI_SEL_CH2_REG register
+ *  Peripheral selection of Tx channel2
+ */
+#define AXI_DMA_OUT_PERI_SEL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x24c)
+/** AXI_DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63;
+ *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+ *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+ */
+#define AXI_DMA_PERI_OUT_SEL_CH2    0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_M  (AXI_DMA_PERI_OUT_SEL_CH2_V << AXI_DMA_PERI_OUT_SEL_CH2_S)
+#define AXI_DMA_PERI_OUT_SEL_CH2_V  0x0000003FU
+#define AXI_DMA_PERI_OUT_SEL_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG register
+ *  This register is used to config ch2 crc initial data(max 32 bit)
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x250)
+/** AXI_DMA_OUT_CRC_INIT_DATA_CH2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is used to config ch0 of tx crc initial value
+ */
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_M  (AXI_DMA_OUT_CRC_INIT_DATA_CH2_V << AXI_DMA_OUT_CRC_INIT_DATA_CH2_S)
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_INIT_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_WIDTH_CH2_REG register
+ *  This register is used to confiig tx ch2 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2_REG (DR_REG_AXI_DMA_BASE + 0x254)
+/** AXI_DMA_TX_CRC_WIDTH_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_WIDTH_CH2    0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_M  (AXI_DMA_TX_CRC_WIDTH_CH2_V << AXI_DMA_TX_CRC_WIDTH_CH2_S)
+#define AXI_DMA_TX_CRC_WIDTH_CH2_V  0x00000003U
+#define AXI_DMA_TX_CRC_WIDTH_CH2_S  0
+/** AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2 : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2    (BIT(2))
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_M  (AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V << AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S)
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_V  0x00000001U
+#define AXI_DMA_TX_CRC_LAUTCH_FLGA_CH2_S  2
+
+/** AXI_DMA_OUT_CRC_CLEAR_CH2_REG register
+ *  This register is used to clear ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x258)
+/** AXI_DMA_OUT_CRC_CLEAR_CH2 : R/W; bitpos: [0]; default: 0;
+ *  This register is used to clear ch0 of tx crc result
+ */
+#define AXI_DMA_OUT_CRC_CLEAR_CH2    (BIT(0))
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_M  (AXI_DMA_OUT_CRC_CLEAR_CH2_V << AXI_DMA_OUT_CRC_CLEAR_CH2_S)
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_V  0x00000001U
+#define AXI_DMA_OUT_CRC_CLEAR_CH2_S  0
+
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG register
+ *  This register is used to store ch2 crc result
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_REG (DR_REG_AXI_DMA_BASE + 0x25c)
+/** AXI_DMA_OUT_CRC_FINAL_RESULT_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register is used to store result ch0 of tx
+ */
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2    0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_M  (AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V << AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S)
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_OUT_CRC_FINAL_RESULT_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG register
+ *  This resister is used to config ch2 crc en for every bit
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x260)
+/** AXI_DMA_TX_CRC_EN_WR_DATA_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register is used to enable tx ch0 crc 32bit on/off
+ */
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2_REG register
+ *  This register is used to config ch2 crc en addr
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x264)
+/** AXI_DMA_TX_CRC_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG register
+ *  This register is used to config crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_REG (DR_REG_AXI_DMA_BASE + 0x268)
+/** AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2 : R/W; bitpos: [15:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2    0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V << AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_V  0x0000FFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_WR_DATA_CH2_S  0
+
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG register
+ *  This register is used to config addr of crc data_8bit en
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_REG (DR_REG_AXI_DMA_BASE + 0x26c)
+/** AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2    0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_M  (AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V << AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S)
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_V  0xFFFFFFFFU
+#define AXI_DMA_TX_CRC_DATA_EN_ADDR_CH2_S  0
+
+/** AXI_DMA_ARB_TIMEOUT_REG register
+ *  This retister is used to config arbiter time slice
+ */
+#define AXI_DMA_ARB_TIMEOUT_REG (DR_REG_AXI_DMA_BASE + 0x270)
+/** AXI_DMA_ARB_TIMEOUT_TX : R/W; bitpos: [15:0]; default: 0;
+ *  This register is used to config tx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_TX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_M  (AXI_DMA_ARB_TIMEOUT_TX_V << AXI_DMA_ARB_TIMEOUT_TX_S)
+#define AXI_DMA_ARB_TIMEOUT_TX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_TX_S  0
+/** AXI_DMA_ARB_TIMEOUT_RX : R/W; bitpos: [31:16]; default: 0;
+ *  This register is used to config rx arbiter time out value
+ */
+#define AXI_DMA_ARB_TIMEOUT_RX    0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_M  (AXI_DMA_ARB_TIMEOUT_RX_V << AXI_DMA_ARB_TIMEOUT_RX_S)
+#define AXI_DMA_ARB_TIMEOUT_RX_V  0x0000FFFFU
+#define AXI_DMA_ARB_TIMEOUT_RX_S  16
+
+/** AXI_DMA_WEIGHT_EN_REG register
+ *  This register is used to config arbiter weight function to on or off
+ */
+#define AXI_DMA_WEIGHT_EN_REG (DR_REG_AXI_DMA_BASE + 0x274)
+/** AXI_DMA_WEIGHT_EN_TX : R/W; bitpos: [0]; default: 0;
+ *  This register is used to config tx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_TX    (BIT(0))
+#define AXI_DMA_WEIGHT_EN_TX_M  (AXI_DMA_WEIGHT_EN_TX_V << AXI_DMA_WEIGHT_EN_TX_S)
+#define AXI_DMA_WEIGHT_EN_TX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_TX_S  0
+/** AXI_DMA_WEIGHT_EN_RX : R/W; bitpos: [1]; default: 0;
+ *  This register is used to config rx arbiter weight function  off/on
+ */
+#define AXI_DMA_WEIGHT_EN_RX    (BIT(1))
+#define AXI_DMA_WEIGHT_EN_RX_M  (AXI_DMA_WEIGHT_EN_RX_V << AXI_DMA_WEIGHT_EN_RX_S)
+#define AXI_DMA_WEIGHT_EN_RX_V  0x00000001U
+#define AXI_DMA_WEIGHT_EN_RX_S  1
+
+/** AXI_DMA_IN_MEM_CONF_REG register
+ *  Mem power configure register of Rx channel
+ */
+#define AXI_DMA_IN_MEM_CONF_REG (DR_REG_AXI_DMA_BASE + 0x278)
+/** AXI_DMA_IN_MEM_CLK_FORCE_EN : R/W; bitpos: [0]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN    (BIT(0))
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_M  (AXI_DMA_IN_MEM_CLK_FORCE_EN_V << AXI_DMA_IN_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_IN_MEM_CLK_FORCE_EN_S  0
+/** AXI_DMA_IN_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PU    (BIT(1))
+#define AXI_DMA_IN_MEM_FORCE_PU_M  (AXI_DMA_IN_MEM_FORCE_PU_V << AXI_DMA_IN_MEM_FORCE_PU_S)
+#define AXI_DMA_IN_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PU_S  1
+/** AXI_DMA_IN_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_IN_MEM_FORCE_PD    (BIT(2))
+#define AXI_DMA_IN_MEM_FORCE_PD_M  (AXI_DMA_IN_MEM_FORCE_PD_V << AXI_DMA_IN_MEM_FORCE_PD_S)
+#define AXI_DMA_IN_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_IN_MEM_FORCE_PD_S  2
+/** AXI_DMA_OUT_MEM_CLK_FORCE_EN : R/W; bitpos: [3]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+ *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+ */
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN    (BIT(3))
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_M  (AXI_DMA_OUT_MEM_CLK_FORCE_EN_V << AXI_DMA_OUT_MEM_CLK_FORCE_EN_S)
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_V  0x00000001U
+#define AXI_DMA_OUT_MEM_CLK_FORCE_EN_S  3
+/** AXI_DMA_OUT_MEM_FORCE_PU : R/W; bitpos: [4]; default: 0;
+ *  Force power up ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PU    (BIT(4))
+#define AXI_DMA_OUT_MEM_FORCE_PU_M  (AXI_DMA_OUT_MEM_FORCE_PU_V << AXI_DMA_OUT_MEM_FORCE_PU_S)
+#define AXI_DMA_OUT_MEM_FORCE_PU_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PU_S  4
+/** AXI_DMA_OUT_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  Force power down ram
+ */
+#define AXI_DMA_OUT_MEM_FORCE_PD    (BIT(5))
+#define AXI_DMA_OUT_MEM_FORCE_PD_M  (AXI_DMA_OUT_MEM_FORCE_PD_V << AXI_DMA_OUT_MEM_FORCE_PD_S)
+#define AXI_DMA_OUT_MEM_FORCE_PD_V  0x00000001U
+#define AXI_DMA_OUT_MEM_FORCE_PD_S  5
+
+/** AXI_DMA_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_INTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x27c)
+/** AXI_DMA_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_INTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x280)
+/** AXI_DMA_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_EXTR_MEM_START_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x284)
+/** AXI_DMA_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 806354944;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** AXI_DMA_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_EXTR_MEM_END_ADDR_REG (DR_REG_AXI_DMA_BASE + 0x288)
+/** AXI_DMA_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 2415919103;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_M  (AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V << AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S)
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define AXI_DMA_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH0_REG register
+ *  The rx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x28c)
+/** AXI_DMA_IN_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH0_M  (AXI_DMA_IN_RESET_AVAIL_CH0_V << AXI_DMA_IN_RESET_AVAIL_CH0_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH1_REG register
+ *  The rx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x290)
+/** AXI_DMA_IN_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH1_M  (AXI_DMA_IN_RESET_AVAIL_CH1_V << AXI_DMA_IN_RESET_AVAIL_CH1_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_IN_RESET_AVAIL_CH2_REG register
+ *  The rx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x294)
+/** AXI_DMA_IN_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  rx chan0 reset valid reg.
+ */
+#define AXI_DMA_IN_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_IN_RESET_AVAIL_CH2_M  (AXI_DMA_IN_RESET_AVAIL_CH2_V << AXI_DMA_IN_RESET_AVAIL_CH2_S)
+#define AXI_DMA_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_IN_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH0_REG register
+ *  The tx channel 0 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_REG (DR_REG_AXI_DMA_BASE + 0x298)
+/** AXI_DMA_OUT_RESET_AVAIL_CH0 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH0    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_M  (AXI_DMA_OUT_RESET_AVAIL_CH0_V << AXI_DMA_OUT_RESET_AVAIL_CH0_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH0_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH1_REG register
+ *  The tx channel 1 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_REG (DR_REG_AXI_DMA_BASE + 0x29c)
+/** AXI_DMA_OUT_RESET_AVAIL_CH1 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH1    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_M  (AXI_DMA_OUT_RESET_AVAIL_CH1_V << AXI_DMA_OUT_RESET_AVAIL_CH1_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH1_S  0
+
+/** AXI_DMA_OUT_RESET_AVAIL_CH2_REG register
+ *  The tx channel 2 reset valid_flag register.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2a0)
+/** AXI_DMA_OUT_RESET_AVAIL_CH2 : RO; bitpos: [0]; default: 1;
+ *  tx chan0 reset valid reg.
+ */
+#define AXI_DMA_OUT_RESET_AVAIL_CH2    (BIT(0))
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_M  (AXI_DMA_OUT_RESET_AVAIL_CH2_V << AXI_DMA_OUT_RESET_AVAIL_CH2_S)
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define AXI_DMA_OUT_RESET_AVAIL_CH2_S  0
+
+/** AXI_DMA_MISC_CONF_REG register
+ *  MISC register
+ */
+#define AXI_DMA_MISC_CONF_REG (DR_REG_AXI_DMA_BASE + 0x2a8)
+/** AXI_DMA_AXIM_RST_WR_INTER : R/W; bitpos: [0]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+ */
+#define AXI_DMA_AXIM_RST_WR_INTER    (BIT(0))
+#define AXI_DMA_AXIM_RST_WR_INTER_M  (AXI_DMA_AXIM_RST_WR_INTER_V << AXI_DMA_AXIM_RST_WR_INTER_S)
+#define AXI_DMA_AXIM_RST_WR_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_WR_INTER_S  0
+/** AXI_DMA_AXIM_RST_RD_INTER : R/W; bitpos: [1]; default: 0;
+ *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+ */
+#define AXI_DMA_AXIM_RST_RD_INTER    (BIT(1))
+#define AXI_DMA_AXIM_RST_RD_INTER_M  (AXI_DMA_AXIM_RST_RD_INTER_V << AXI_DMA_AXIM_RST_RD_INTER_S)
+#define AXI_DMA_AXIM_RST_RD_INTER_V  0x00000001U
+#define AXI_DMA_AXIM_RST_RD_INTER_S  1
+/** AXI_DMA_ARB_PRI_DIS : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to disable priority arbitration function.
+ */
+#define AXI_DMA_ARB_PRI_DIS    (BIT(3))
+#define AXI_DMA_ARB_PRI_DIS_M  (AXI_DMA_ARB_PRI_DIS_V << AXI_DMA_ARB_PRI_DIS_S)
+#define AXI_DMA_ARB_PRI_DIS_V  0x00000001U
+#define AXI_DMA_ARB_PRI_DIS_S  3
+/** AXI_DMA_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define AXI_DMA_CLK_EN    (BIT(4))
+#define AXI_DMA_CLK_EN_M  (AXI_DMA_CLK_EN_V << AXI_DMA_CLK_EN_S)
+#define AXI_DMA_CLK_EN_V  0x00000001U
+#define AXI_DMA_CLK_EN_S  4
+
+/** AXI_DMA_RDN_RESULT_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT_REG (DR_REG_AXI_DMA_BASE + 0x2ac)
+/** AXI_DMA_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_ENA    (BIT(0))
+#define AXI_DMA_RDN_ENA_M  (AXI_DMA_RDN_ENA_V << AXI_DMA_RDN_ENA_S)
+#define AXI_DMA_RDN_ENA_V  0x00000001U
+#define AXI_DMA_RDN_ENA_S  0
+/** AXI_DMA_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define AXI_DMA_RDN_RESULT    (BIT(1))
+#define AXI_DMA_RDN_RESULT_M  (AXI_DMA_RDN_RESULT_V << AXI_DMA_RDN_RESULT_S)
+#define AXI_DMA_RDN_RESULT_V  0x00000001U
+#define AXI_DMA_RDN_RESULT_S  1
+
+/** AXI_DMA_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_HIGH_REG (DR_REG_AXI_DMA_BASE + 0x2b0)
+/** AXI_DMA_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_HIGH    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_M  (AXI_DMA_RDN_ECO_HIGH_V << AXI_DMA_RDN_ECO_HIGH_S)
+#define AXI_DMA_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_HIGH_S  0
+
+/** AXI_DMA_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define AXI_DMA_RDN_ECO_LOW_REG (DR_REG_AXI_DMA_BASE + 0x2b4)
+/** AXI_DMA_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define AXI_DMA_RDN_ECO_LOW    0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_M  (AXI_DMA_RDN_ECO_LOW_V << AXI_DMA_RDN_ECO_LOW_S)
+#define AXI_DMA_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define AXI_DMA_RDN_ECO_LOW_S  0
+
+/** AXI_DMA_WRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_WRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2b8)
+/** AXI_DMA_WRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi wr response cnt reg.
+ */
+#define AXI_DMA_WRESP_CNT    0x0000000FU
+#define AXI_DMA_WRESP_CNT_M  (AXI_DMA_WRESP_CNT_V << AXI_DMA_WRESP_CNT_S)
+#define AXI_DMA_WRESP_CNT_V  0x0000000FU
+#define AXI_DMA_WRESP_CNT_S  0
+
+/** AXI_DMA_RRESP_CNT_REG register
+ *  AXI wr response cnt register.
+ */
+#define AXI_DMA_RRESP_CNT_REG (DR_REG_AXI_DMA_BASE + 0x2bc)
+/** AXI_DMA_RRESP_CNT : RO; bitpos: [3:0]; default: 0;
+ *  axi rd response cnt reg.
+ */
+#define AXI_DMA_RRESP_CNT    0x0000000FU
+#define AXI_DMA_RRESP_CNT_M  (AXI_DMA_RRESP_CNT_V << AXI_DMA_RRESP_CNT_S)
+#define AXI_DMA_RRESP_CNT_V  0x0000000FU
+#define AXI_DMA_RRESP_CNT_S  0
+
+/** AXI_DMA_INFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Rx channel 0
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2c0)
+/** AXI_DMA_L1INFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_M  (AXI_DMA_L1INFIFO_CNT_CH0_V << AXI_DMA_L1INFIFO_CNT_CH0_S)
+#define AXI_DMA_L1INFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_M  (AXI_DMA_L2INFIFO_CNT_CH0_V << AXI_DMA_L2INFIFO_CNT_CH0_S)
+#define AXI_DMA_L2INFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Rx channel 1
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2c4)
+/** AXI_DMA_L1INFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_M  (AXI_DMA_L1INFIFO_CNT_CH1_V << AXI_DMA_L1INFIFO_CNT_CH1_S)
+#define AXI_DMA_L1INFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_M  (AXI_DMA_L2INFIFO_CNT_CH1_V << AXI_DMA_L2INFIFO_CNT_CH1_S)
+#define AXI_DMA_L2INFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_INFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Rx channel 2
+ */
+#define AXI_DMA_INFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2c8)
+/** AXI_DMA_L1INFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L1INFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_M  (AXI_DMA_L1INFIFO_CNT_CH2_V << AXI_DMA_L1INFIFO_CNT_CH2_S)
+#define AXI_DMA_L1INFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1INFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2INFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+ */
+#define AXI_DMA_L2INFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_M  (AXI_DMA_L2INFIFO_CNT_CH2_V << AXI_DMA_L2INFIFO_CNT_CH2_S)
+#define AXI_DMA_L2INFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2INFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH0_REG register
+ *  Receive FIFO status of Tx channel 0
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH0_REG (DR_REG_AXI_DMA_BASE + 0x2cc)
+/** AXI_DMA_L1OUTFIFO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH0    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_M  (AXI_DMA_L1OUTFIFO_CNT_CH0_V << AXI_DMA_L1OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH0_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH0 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH0    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_M  (AXI_DMA_L2OUTFIFO_CNT_CH0_V << AXI_DMA_L2OUTFIFO_CNT_CH0_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH0_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH1_REG register
+ *  Receive FIFO status of Tx channel 1
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH1_REG (DR_REG_AXI_DMA_BASE + 0x2d0)
+/** AXI_DMA_L1OUTFIFO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH1    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_M  (AXI_DMA_L1OUTFIFO_CNT_CH1_V << AXI_DMA_L1OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH1_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH1 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH1    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_M  (AXI_DMA_L2OUTFIFO_CNT_CH1_V << AXI_DMA_L2OUTFIFO_CNT_CH1_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH1_S  6
+
+/** AXI_DMA_OUTFIFO_STATUS1_CH2_REG register
+ *  Receive FIFO status of Tx channel 2
+ */
+#define AXI_DMA_OUTFIFO_STATUS1_CH2_REG (DR_REG_AXI_DMA_BASE + 0x2d4)
+/** AXI_DMA_L1OUTFIFO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L1OUTFIFO_CNT_CH2    0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_M  (AXI_DMA_L1OUTFIFO_CNT_CH2_V << AXI_DMA_L1OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_V  0x0000003FU
+#define AXI_DMA_L1OUTFIFO_CNT_CH2_S  0
+/** AXI_DMA_L2OUTFIFO_CNT_CH2 : RO; bitpos: [9:6]; default: 0;
+ *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+ */
+#define AXI_DMA_L2OUTFIFO_CNT_CH2    0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_M  (AXI_DMA_L2OUTFIFO_CNT_CH2_V << AXI_DMA_L2OUTFIFO_CNT_CH2_S)
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_V  0x0000000FU
+#define AXI_DMA_L2OUTFIFO_CNT_CH2_S  6
+
+/** AXI_DMA_DATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_DATE_REG (DR_REG_AXI_DMA_BASE + 0x2d8)
+/** AXI_DMA_DATE : R/W; bitpos: [31:0]; default: 36712768;
+ *  register version.
+ */
+#define AXI_DMA_DATE    0xFFFFFFFFU
+#define AXI_DMA_DATE_M  (AXI_DMA_DATE_V << AXI_DMA_DATE_S)
+#define AXI_DMA_DATE_V  0xFFFFFFFFU
+#define AXI_DMA_DATE_S  0
+
+/** AXI_DMA_LINK_SWITCH_STATE_REG register
+ *  Version control register
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_REG (DR_REG_AXI_DMA_BASE + 0x2dc)
+/** AXI_DMA_LINK_SWITCH_STATE_CH0 : R/W; bitpos: [0]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH0    (BIT(0))
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_M  (AXI_DMA_LINK_SWITCH_STATE_CH0_V << AXI_DMA_LINK_SWITCH_STATE_CH0_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH0_S  0
+/** AXI_DMA_LINK_SWITCH_STATE_CH1 : R/W; bitpos: [1]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH1    (BIT(1))
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_M  (AXI_DMA_LINK_SWITCH_STATE_CH1_V << AXI_DMA_LINK_SWITCH_STATE_CH1_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH1_S  1
+/** AXI_DMA_LINK_SWITCH_STATE_CH2 : R/W; bitpos: [2]; default: 0;
+ *  The register that confirm ch dscr switch success
+ */
+#define AXI_DMA_LINK_SWITCH_STATE_CH2    (BIT(2))
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_M  (AXI_DMA_LINK_SWITCH_STATE_CH2_V << AXI_DMA_LINK_SWITCH_STATE_CH2_S)
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_V  0x00000001U
+#define AXI_DMA_LINK_SWITCH_STATE_CH2_S  2
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/axi_dma_struct.h b/components/soc/esp32s31/register/soc/axi_dma_struct.h
new file mode 100644
index 00000000000..4a5846b4c8c
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/axi_dma_struct.h
@@ -0,0 +1,1822 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: in */
+/** Type of in_int_raw_chn register
+ *  Raw status interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw: 1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit
+         *  turns to high level when the last data pointed by one inlink descriptor has been
+         *  received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw: 1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when data error is detected only in the
+         *  case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw
+         *  interrupt is reserved.
+         */
+        uint32_t in_err_eof_chn_int_raw: 1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error
+         *  including owner error and the second and third word error of inlink descriptor for
+         *  Rx channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw: 1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full
+         *  and receiving data is not completed but there is no more inlink for Rx channel 0.
+         */
+        uint32_t in_dscr_empty_chn_int_raw: 1;
+        /** infifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l1_ovf_chn_int_raw: 1;
+        /** infifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l1_udf_chn_int_raw: 1;
+        /** infifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l2_ovf_chn_int_raw: 1;
+        /** infifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l2_udf_chn_int_raw: 1;
+        /** infifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  overflow.
+         */
+        uint32_t infifo_l3_ovf_chn_int_raw: 1;
+        /** infifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+         *  underflow.
+         */
+        uint32_t infifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_raw_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st: 1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st: 1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st: 1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st: 1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st: 1;
+        /** infifo_l1_ovf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_st: 1;
+        /** infifo_l1_udf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_st: 1;
+        /** infifo_l2_ovf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_st: 1;
+        /** infifo_l2_udf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_st: 1;
+        /** infifo_l3_ovf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_st: 1;
+        /** infifo_l3_udf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_st_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena: 1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena: 1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena: 1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena: 1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena: 1;
+        /** infifo_l1_ovf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_ena: 1;
+        /** infifo_l1_udf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_ena: 1;
+        /** infifo_l2_ovf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_ena: 1;
+        /** infifo_l2_udf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_ena: 1;
+        /** infifo_l3_ovf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_ena: 1;
+        /** infifo_l3_udf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_ena_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of channel 0
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr: 1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr: 1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr: 1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr: 1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr: 1;
+        /** infifo_l1_ovf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_ovf_chn_int_clr: 1;
+        /** infifo_l1_udf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_l1_udf_chn_int_clr: 1;
+        /** infifo_l2_ovf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_ovf_chn_int_clr: 1;
+        /** infifo_l2_udf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_l2_udf_chn_int_clr: 1;
+        /** infifo_l3_ovf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_ovf_chn_int_clr: 1;
+        /** infifo_l3_udf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_in_int_clr_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configure 0 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel 0 Rx FSM and Rx FIFO pointer.
+         */
+        uint32_t in_rst_chn: 1;
+        /** in_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn: 1;
+        /** mem_trans_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit 1 to enable automatic transmitting data from memory to memory via
+         *  AXI_DMA.
+         */
+        uint32_t mem_trans_en_chn: 1;
+        /** in_etm_en_chn : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm
+         *  task.
+         */
+        uint32_t in_etm_en_chn: 1;
+        /** in_burst_size_sel_chn : R/W; bitpos: [6:4]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t in_burst_size_sel_chn: 3;
+        /** in_cmd_disable_chn : R/W; bitpos: [7]; default: 0;
+         *  1:mean disable cmd of this ch0
+         */
+        uint32_t in_cmd_disable_chn: 1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [8]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t in_ecc_aes_en_chn: 1;
+        /** indscr_burst_en_chn : R/W; bitpos: [9]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t indscr_burst_en_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_in_conf0_chn_reg_t;
+
+/** Type of in_conf1_chn register
+ *  Configure 1 register of Rx channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** in_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_conf1_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_l3_full_chn : RO; bitpos: [0]; default: 1;
+         *  L3 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_full_chn: 1;
+        /** infifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_empty_chn: 1;
+        /** infifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_l3_cnt_chn: 6;
+        /** infifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_udf_chn: 1;
+        /** infifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l3_ovf_chn: 1;
+        /** infifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_full_chn: 1;
+        /** infifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_empty_chn: 1;
+        /** infifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_udf_chn: 1;
+        /** infifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l1_ovf_chn: 1;
+        /** infifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Rx RAM full signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_full_chn: 1;
+        /** infifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Rx RAM empty signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_empty_chn: 1;
+        /** infifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Rx FIFO under flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_udf_chn: 1;
+        /** infifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Rx FIFO over flow signal for Rx channel 0.
+         */
+        uint32_t infifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** in_remain_under_1b_chn : RO; bitpos: [23]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn: 1;
+        /** in_remain_under_2b_chn : RO; bitpos: [24]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn: 1;
+        /** in_remain_under_3b_chn : RO; bitpos: [25]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn: 1;
+        /** in_remain_under_4b_chn : RO; bitpos: [26]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn: 1;
+        /** in_remain_under_5b_chn : RO; bitpos: [27]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn: 1;
+        /** in_remain_under_6b_chn : RO; bitpos: [28]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn: 1;
+        /** in_remain_under_7b_chn : RO; bitpos: [29]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn: 1;
+        /** in_remain_under_8b_chn : RO; bitpos: [30]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn: 1;
+        /** in_buf_hungry_chn : RO; bitpos: [31]; default: 0;
+         *  reserved
+         */
+        uint32_t in_buf_hungry_chn: 1;
+    };
+    uint32_t val;
+} axi_dma_infifo_status_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Pop control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [11:0]; default: 2048;
+         *  This register stores the data popping from AXI_DMA FIFO.
+         */
+        uint32_t infifo_rdata_chn: 12;
+        /** infifo_pop_chn : WT; bitpos: [12]; default: 0;
+         *  Set this bit to pop data from AXI_DMA FIFO.
+         */
+        uint32_t infifo_pop_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_in_pop_chn_reg_t;
+
+/** Type of in_link1_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_auto_ret_chn : R/W; bitpos: [0]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn: 1;
+        /** inlink_stop_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn: 1;
+        /** inlink_start_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn: 1;
+        /** inlink_restart_chn : WT; bitpos: [3]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn: 1;
+        /** inlink_park_chn : RO; bitpos: [4]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_in_link1_chn_reg_t;
+
+/** Type of in_link2_chn register
+ *  Link descriptor configure and control register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 20 least significant bits of the first inlink descriptor's
+         *  address.
+         */
+        uint32_t inlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_link2_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Receive status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn: 18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn: 2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Inlink descriptor address when EOF occurs of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Inlink descriptor address when errors occur of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data. Only used when peripheral is UHCI0.
+         */
+        uint32_t in_err_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Current inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current inlink descriptor x.
+         */
+        uint32_t inlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  The last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  The second-to-last inlink descriptor address of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_pri_chn register
+ *  Priority register of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** rx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Rx channel 0. The larger of the value the higher of the priority.
+         */
+        uint32_t rx_pri_chn: 4;
+        /** rx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Rx channel 0
+         */
+        uint32_t rx_ch_arb_weigh_chn: 4;
+        /** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t rx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_in_pri_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Peripheral selection of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Rx channel 0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_in_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_peri_sel_chn_reg_t;
+
+/** Type of in_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** in_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of rx crc initial value
+         */
+        uint32_t in_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_init_data_chn_reg_t;
+
+/** Type of rx_crc_width_chn register
+ *  This register is used to config rx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** rx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_width_chn: 2;
+        /** rx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_width_chn_reg_t;
+
+/** Type of in_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of rx crc result
+         */
+        uint32_t in_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_crc_clear_chn_reg_t;
+
+/** Type of in_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** in_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of rx
+         */
+        uint32_t in_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_in_crc_final_result_chn_reg_t;
+
+/** Type of rx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable rx ch0 crc 32bit on/off
+         */
+        uint32_t rx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** rx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_en_addr_chn_reg_t;
+
+/** Type of rx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of rx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** rx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t rx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_rx_crc_data_en_addr_chn_reg_t;
+
+/** Group: out */
+/** Type of out_int_raw_chn register
+ *  Raw status interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel0.
+         */
+        uint32_t out_done_chn_int_raw: 1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel0.
+         */
+        uint32_t out_eof_chn_int_raw: 1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error
+         *  including owner error and the second and third word error of outlink descriptor for
+         *  Tx channel0.
+         */
+        uint32_t out_dscr_err_chn_int_raw: 1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel0.
+         */
+        uint32_t out_total_eof_chn_int_raw: 1;
+        /** outfifo_l1_ovf_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_raw: 1;
+        /** outfifo_l1_udf_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l1_udf_chn_int_raw: 1;
+        /** outfifo_l2_ovf_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_raw: 1;
+        /** outfifo_l2_udf_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l2_udf_chn_int_raw: 1;
+        /** outfifo_l3_ovf_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  overflow.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_raw: 1;
+        /** outfifo_l3_udf_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  This raw interrupt bit turns to high level when level 1 fifo of Tx channel0 is
+         *  underflow.
+         */
+        uint32_t outfifo_l3_udf_chn_int_raw: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_raw_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st: 1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st: 1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st: 1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st: 1;
+        /** outfifo_l1_ovf_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_st: 1;
+        /** outfifo_l1_udf_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_st: 1;
+        /** outfifo_l2_ovf_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_st: 1;
+        /** outfifo_l2_udf_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_st: 1;
+        /** outfifo_l3_ovf_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_st: 1;
+        /** outfifo_l3_udf_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_st: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_st_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena: 1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena: 1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena: 1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena: 1;
+        /** outfifo_l1_ovf_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_ena: 1;
+        /** outfifo_l1_udf_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_ena: 1;
+        /** outfifo_l2_ovf_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_ena: 1;
+        /** outfifo_l2_udf_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_ena: 1;
+        /** outfifo_l3_ovf_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_ena: 1;
+        /** outfifo_l3_udf_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_ena: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_ena_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of channel0
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr: 1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr: 1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr: 1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr: 1;
+        /** outfifo_l1_ovf_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_ovf_chn_int_clr: 1;
+        /** outfifo_l1_udf_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_l1_udf_chn_int_clr: 1;
+        /** outfifo_l2_ovf_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_ovf_chn_int_clr: 1;
+        /** outfifo_l2_udf_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_l2_udf_chn_int_clr: 1;
+        /** outfifo_l3_ovf_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_ovf_chn_int_clr: 1;
+        /** outfifo_l3_udf_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_l3_udf_chn_int_clr: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_int_clr_chn_reg_t;
+
+/** Type of out_conf0_chn register
+ *  Configure 0 register of Tx channelN
+ */
+typedef union {
+    struct {
+        /** out_rst_chn : R/W; bitpos: [0]; default: 0;
+         *  This bit is used to reset AXI_DMA channel0 Tx FSM and Tx FIFO pointer.
+         */
+        uint32_t out_rst_chn: 1;
+        /** out_loop_test_chn : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn: 1;
+        /** out_auto_wrback_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data in tx buffer
+         *  has been transmitted.
+         */
+        uint32_t out_auto_wrback_chn: 1;
+        /** out_eof_mode_chn : R/W; bitpos: [3]; default: 1;
+         *  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel0 is
+         *  generated when data need to transmit has been popped from FIFO in AXI_DMA
+         */
+        uint32_t out_eof_mode_chn: 1;
+        /** out_etm_en_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to 1 to enable etm control mode, dma Tx channel0 is triggered by etm
+         *  task.
+         */
+        uint32_t out_etm_en_chn: 1;
+        /** out_burst_size_sel_chn : R/W; bitpos: [7:5]; default: 0;
+         *  3'b000-3'b100:burst length 8byte~128byte
+         */
+        uint32_t out_burst_size_sel_chn: 3;
+        /** out_cmd_disable_chn : R/W; bitpos: [8]; default: 0;
+         *  1:mean disable cmd of this chn
+         */
+        uint32_t out_cmd_disable_chn: 1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [9]; default: 0;
+         *  1: mean access ecc or aes domain,0: mean not
+         */
+        uint32_t out_ecc_aes_en_chn: 1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn: 1;
+        uint32_t reserved_11: 21;
+    };
+    uint32_t val;
+} axi_dma_out_conf0_chn_reg_t;
+
+/** Type of out_conf1_chn register
+ *  Configure 1 register of Tx channel0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0: 12;
+        /** out_check_owner_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn: 1;
+        uint32_t reserved_13: 19;
+    };
+    uint32_t val;
+} axi_dma_out_conf1_chn_reg_t;
+
+/** Type of outfifo_status_chn register
+ *  Transmit FIFO status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_l3_full_chn : RO; bitpos: [0]; default: 0;
+         *  L3 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_full_chn: 1;
+        /** outfifo_l3_empty_chn : RO; bitpos: [1]; default: 1;
+         *  L3 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_empty_chn: 1;
+        /** outfifo_l3_cnt_chn : RO; bitpos: [7:2]; default: 0;
+         *  The register stores the byte number of the data in L3 Tx FIFO for Tx channel0.
+         */
+        uint32_t outfifo_l3_cnt_chn: 6;
+        /** outfifo_l3_udf_chn : RO; bitpos: [8]; default: 0;
+         *  L3 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_udf_chn: 1;
+        /** outfifo_l3_ovf_chn : RO; bitpos: [9]; default: 0;
+         *  L3 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l3_ovf_chn: 1;
+        /** outfifo_l1_full_chn : RO; bitpos: [10]; default: 0;
+         *  L1 Tx FIFO full signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_full_chn: 1;
+        /** outfifo_l1_empty_chn : RO; bitpos: [11]; default: 1;
+         *  L1 Tx FIFO empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_empty_chn: 1;
+        /** outfifo_l1_udf_chn : RO; bitpos: [12]; default: 0;
+         *  L1 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_udf_chn: 1;
+        /** outfifo_l1_ovf_chn : RO; bitpos: [13]; default: 0;
+         *  L1 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l1_ovf_chn: 1;
+        /** outfifo_l2_full_chn : RO; bitpos: [14]; default: 0;
+         *  L2 Tx RAM full signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_full_chn: 1;
+        /** outfifo_l2_empty_chn : RO; bitpos: [15]; default: 1;
+         *  L2 Tx RAM empty signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_empty_chn: 1;
+        /** outfifo_l2_udf_chn : RO; bitpos: [16]; default: 0;
+         *  L2 Tx FIFO under flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_udf_chn: 1;
+        /** outfifo_l2_ovf_chn : RO; bitpos: [17]; default: 0;
+         *  L2 Tx FIFO over flow signal for Tx channel0.
+         */
+        uint32_t outfifo_l2_ovf_chn: 1;
+        uint32_t reserved_18: 5;
+        /** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn: 1;
+        /** out_remain_under_2b_chn : RO; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn: 1;
+        /** out_remain_under_3b_chn : RO; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn: 1;
+        /** out_remain_under_4b_chn : RO; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn: 1;
+        /** out_remain_under_5b_chn : RO; bitpos: [27]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn: 1;
+        /** out_remain_under_6b_chn : RO; bitpos: [28]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn: 1;
+        /** out_remain_under_7b_chn : RO; bitpos: [29]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn: 1;
+        /** out_remain_under_8b_chn : RO; bitpos: [30]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn: 1;
+        uint32_t reserved_31: 1;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Push control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [8:0]; default: 0;
+         *  This register stores the data that need to be pushed into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_wdata_chn: 9;
+        /** outfifo_push_chn : WT; bitpos: [9]; default: 0;
+         *  Set this bit to push data into AXI_DMA FIFO.
+         */
+        uint32_t outfifo_push_chn: 1;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_out_push_chn_reg_t;
+
+/** Type of out_link1_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_stop_chn : WT; bitpos: [0]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn: 1;
+        /** outlink_start_chn : WT; bitpos: [1]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn: 1;
+        /** outlink_restart_chn : WT; bitpos: [2]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn: 1;
+        /** outlink_park_chn : RO; bitpos: [3]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn: 1;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_out_link1_chn_reg_t;
+
+/** Type of out_link2_chn register
+ *  Link descriptor configure and control register of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the 32 least significant bits of the first outlink
+         *  descriptor's address.
+         */
+        uint32_t outlink_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_link2_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Transmit status of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn: 18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t out_dscr_state_chn: 2;
+        /** out_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t out_state_chn: 3;
+        uint32_t reserved_23: 9;
+    };
+    uint32_t val;
+} axi_dma_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_eof_bfr_des_addr_chn register
+ *  The last outlink descriptor address when EOF occurs of Tx channel0
+ */
+typedef union {
+    struct {
+        /** out_eof_bfr_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor before the last outlink
+         *  descriptor.
+         */
+        uint32_t out_eof_bfr_des_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Current outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the current outlink descriptor y.
+         */
+        uint32_t outlink_dscr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  The last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  The second-to-last outlink descriptor address of Tx channel0
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor x-2.
+         */
+        uint32_t outlink_dscr_bf1_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_pri_chn register
+ *  Priority register of Tx channel0.
+ */
+typedef union {
+    struct {
+        /** tx_pri_chn : R/W; bitpos: [3:0]; default: 0;
+         *  The priority of Tx channel0. The larger of the value the higher of the priority.
+         */
+        uint32_t tx_pri_chn: 4;
+        /** tx_ch_arb_weigh_chn : R/W; bitpos: [7:4]; default: 0;
+         *  The weight of Tx channel0
+         */
+        uint32_t tx_ch_arb_weigh_chn: 4;
+        /** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [8]; default: 0;
+         *  0: mean not optimization weight function ,1: mean optimization
+         */
+        uint32_t tx_arb_weigh_opt_dir_chn: 1;
+        uint32_t reserved_9: 23;
+    };
+    uint32_t val;
+} axi_dma_out_pri_chn_reg_t;
+
+/** Type of out_peri_sel_chn register
+ *  Peripheral selection of Tx channel0
+ */
+typedef union {
+    struct {
+        /** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
+         *  This register is used to select peripheral for Tx channel0. 0:lcdcam. 1: gpspi_2.
+         *  2: gpspi_3. 3: parl_io. 4: aes. 5: sha. 6~15: Dummy
+         */
+        uint32_t peri_out_sel_chn: 6;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_out_peri_sel_chn_reg_t;
+
+/** Type of out_crc_init_data_chn register
+ *  This register is used to config ch0 crc initial data(max 32 bit)
+ */
+typedef union {
+    struct {
+        /** out_crc_init_data_chn : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is used to config ch0 of tx crc initial value
+         */
+        uint32_t out_crc_init_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_init_data_chn_reg_t;
+
+/** Type of tx_crc_width_chn register
+ *  This register is used to config tx ch0 crc result width,2'b00 mean crc_width
+ *  <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width  <=24,2'b11 mean
+ *  24<crc_width<=32
+ */
+typedef union {
+    struct {
+        /** tx_crc_width_chn : R/W; bitpos: [1:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_width_chn: 2;
+        /** tx_crc_latch_flag_chn : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_latch_flag_chn: 1;
+        uint32_t reserved_3: 29;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_width_chn_reg_t;
+
+/** Type of out_crc_clear_chn register
+ *  This register is used to clear ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_clear_chn_reg : R/W; bitpos: [0]; default: 0;
+         *  This register is used to clear ch0 of tx crc result
+         */
+        uint32_t out_crc_clear_chn_reg: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_crc_clear_chn_reg_t;
+
+/** Type of out_crc_final_result_chn register
+ *  This register is used to store ch0 crc result
+ */
+typedef union {
+    struct {
+        /** out_crc_final_result_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register is used to store result ch0 of tx
+         */
+        uint32_t out_crc_final_result_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_out_crc_final_result_chn_reg_t;
+
+/** Type of tx_crc_en_wr_data_chn register
+ *  This resister is used to config ch0 crc en for every bit
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_wr_data_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register is used to enable tx ch0 crc 32bit on/off
+         */
+        uint32_t tx_crc_en_wr_data_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_en_addr_chn register
+ *  This register is used to config ch0 crc en addr
+ */
+typedef union {
+    struct {
+        /** tx_crc_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_en_addr_chn_reg_t;
+
+/** Type of tx_crc_data_en_wr_data_chn register
+ *  This register is used to config crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_wr_data_chn : R/W; bitpos: [15:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_wr_data_chn: 16;
+        uint32_t reserved_16: 16;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_wr_data_chn_reg_t;
+
+/** Type of tx_crc_data_en_addr_chn register
+ *  This register is used to config addr of crc data_8bit en
+ */
+typedef union {
+    struct {
+        /** tx_crc_data_en_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t tx_crc_data_en_addr_chn: 32;
+    };
+    uint32_t val;
+} axi_dma_tx_crc_data_en_addr_chn_reg_t;
+
+/** Group: Configuration Registers */
+/** Type of arb_timeout register
+ *  This retister is used to config arbiter time slice
+ */
+typedef union {
+    struct {
+        /** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
+         *  This register is used to config tx arbiter time out value
+         */
+        uint32_t arb_timeout_tx: 16;
+        /** arb_timeout_rx : R/W; bitpos: [31:16]; default: 0;
+         *  This register is used to config rx arbiter time out value
+         */
+        uint32_t arb_timeout_rx: 16;
+    };
+    uint32_t val;
+} axi_dma_arb_timeout_reg_t;
+
+/** Type of weight_en register
+ *  This register is used to config arbiter weight function to on or off
+ */
+typedef union {
+    struct {
+        /** weight_en_tx : R/W; bitpos: [0]; default: 0;
+         *  This register is used to config tx arbiter weight function  off/on
+         */
+        uint32_t weight_en_tx: 1;
+        /** weight_en_rx : R/W; bitpos: [1]; default: 0;
+         *  This register is used to config rx arbiter weight function  off/on
+         */
+        uint32_t weight_en_rx: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_weight_en_reg_t;
+
+/** Type of in_mem_conf register
+ *  Mem power configure register of Rx channel
+ */
+typedef union {
+    struct {
+        /** in_mem_clk_force_en : R/W; bitpos: [0]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t in_mem_clk_force_en: 1;
+        /** in_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t in_mem_force_pu: 1;
+        /** in_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t in_mem_force_pd: 1;
+        /** out_mem_clk_force_en : R/W; bitpos: [3]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in
+         *  AXI_DMA. 0: A gate-clock will be used when accessing the RAM in AXI_DMA.
+         */
+        uint32_t out_mem_clk_force_en: 1;
+        /** out_mem_force_pu : R/W; bitpos: [4]; default: 0;
+         *  Force power up ram
+         */
+        uint32_t out_mem_force_pu: 1;
+        /** out_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Force power down ram
+         */
+        uint32_t out_mem_force_pd: 1;
+        uint32_t reserved_6: 26;
+    };
+    uint32_t val;
+} axi_dma_in_mem_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 806354944;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 2415919103;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr: 32;
+    };
+    uint32_t val;
+} axi_dma_extr_mem_end_addr_reg_t;
+
+/** Type of in_reset_avail_chn register
+ *  The rx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** in_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  rx chan0 reset valid reg.
+         */
+        uint32_t in_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_in_reset_avail_chn_reg_t;
+
+/** Type of out_reset_avail_chn register
+ *  The tx channel 0 reset valid_flag register.
+ */
+typedef union {
+    struct {
+        /** out_reset_avail_chn : RO; bitpos: [0]; default: 1;
+         *  tx chan0 reset valid reg.
+         */
+        uint32_t out_reset_avail_chn: 1;
+        uint32_t reserved_1: 31;
+    };
+    uint32_t val;
+} axi_dma_out_reset_avail_chn_reg_t;
+
+/** Type of misc_conf register
+ *  MISC register
+ */
+typedef union {
+    struct {
+        /** axim_rst_wr_inter : R/W; bitpos: [0]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_wr FSM.
+         */
+        uint32_t axim_rst_wr_inter: 1;
+        /** axim_rst_rd_inter : R/W; bitpos: [1]; default: 0;
+         *  Set this bit then clear this bit to reset the internal axi_rd FSM.
+         */
+        uint32_t axim_rst_rd_inter: 1;
+        uint32_t reserved_2: 1;
+        /** arb_pri_dis : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to disable priority arbitration function.
+         */
+        uint32_t arb_pri_dis: 1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en: 1;
+        uint32_t reserved_5: 27;
+    };
+    uint32_t val;
+} axi_dma_misc_conf_reg_t;
+
+/** Group: Debug Registers */
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena: 1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result: 1;
+        uint32_t reserved_2: 30;
+    };
+    uint32_t val;
+} axi_dma_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low: 32;
+    };
+    uint32_t val;
+} axi_dma_rdn_eco_low_reg_t;
+
+/** Group: Status Registers */
+/** Type of wresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** wresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi wr response cnt reg.
+         */
+        uint32_t wresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_wresp_cnt_reg_t;
+
+/** Type of rresp_cnt register
+ *  AXI wr response cnt register.
+ */
+typedef union {
+    struct {
+        /** rresp_cnt : RO; bitpos: [3:0]; default: 0;
+         *  axi rd response cnt reg.
+         */
+        uint32_t rresp_cnt: 4;
+        uint32_t reserved_4: 28;
+    };
+    uint32_t val;
+} axi_dma_rresp_cnt_reg_t;
+
+/** Type of infifo_status1_chn register
+ *  Receive FIFO status of Rx channel 0
+ */
+typedef union {
+    struct {
+        /** l1infifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l1infifo_cnt_chn: 6;
+        /** l2infifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.
+         */
+        uint32_t l2infifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_infifo_status1_chn_reg_t;
+
+/** Type of outfifo_status1_chn register
+ *  Receive FIFO status of Tx channel 0
+ */
+typedef union {
+    struct {
+        /** l1outfifo_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l1outfifo_cnt_chn: 6;
+        /** l2outfifo_cnt_chn : RO; bitpos: [9:6]; default: 0;
+         *  The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.
+         */
+        uint32_t l2outfifo_cnt_chn: 4;
+        uint32_t reserved_10: 22;
+    };
+    uint32_t val;
+} axi_dma_outfifo_status1_chn_reg_t;
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36712768;
+         *  register version.
+         */
+        uint32_t date: 32;
+    };
+    uint32_t val;
+} axi_dma_date_reg_t;
+
+/** Type of link_switch_state register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** link_switch_state_ch0 : R/W; bitpos: [0]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch0:1;
+        /** link_switch_state_ch1 : R/W; bitpos: [1]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch1:1;
+        /** link_switch_state_ch2 : R/W; bitpos: [2]; default: 0;
+         *  The register that confirm ch dscr switch success
+         */
+        uint32_t link_switch_state_ch2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_dma_link_switch_state_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_raw_chn_reg_t raw;
+    volatile axi_dma_in_int_st_chn_reg_t st;
+    volatile axi_dma_in_int_ena_chn_reg_t ena;
+    volatile axi_dma_in_int_clr_chn_reg_t clr;
+} axi_dma_in_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_conf0_chn_reg_t in_conf0;
+    volatile axi_dma_in_conf1_chn_reg_t in_conf1;
+    volatile axi_dma_infifo_status_chn_reg_t infifo_status;
+    volatile axi_dma_in_pop_chn_reg_t in_pop;
+    volatile axi_dma_in_link1_chn_reg_t in_link1;
+    volatile axi_dma_in_link2_chn_reg_t in_link2;
+    volatile axi_dma_in_state_chn_reg_t in_state;
+    volatile axi_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
+    volatile axi_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
+    volatile axi_dma_in_dscr_chn_reg_t in_dscr;
+    volatile axi_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
+    volatile axi_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
+    volatile axi_dma_in_pri_chn_reg_t in_pri;
+    volatile axi_dma_in_peri_sel_chn_reg_t in_peri_sel;
+} axi_dma_in_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_crc_init_data_chn_reg_t in_crc_init_data;
+    volatile axi_dma_rx_crc_width_chn_reg_t rx_crc_width;
+    volatile axi_dma_in_crc_clear_chn_reg_t in_crc_clear;
+    volatile axi_dma_in_crc_final_result_chn_reg_t in_crc_final_result;
+    volatile axi_dma_rx_crc_en_wr_data_chn_reg_t rx_crc_en_wr_data;
+    volatile axi_dma_rx_crc_en_addr_chn_reg_t rx_crc_en_addr;
+    volatile axi_dma_rx_crc_data_en_wr_data_chn_reg_t rx_crc_data_en_wr_data;
+    volatile axi_dma_rx_crc_data_en_addr_chn_reg_t rx_crc_data_en_addr;
+} axi_dma_in_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_int_chn_reg_t intr;
+    volatile axi_dma_in_conf_chn_reg_t conf;
+    volatile axi_dma_in_crc_chn_reg_t crc;
+} axi_dma_in_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_raw_chn_reg_t raw;
+    volatile axi_dma_out_int_st_chn_reg_t st;
+    volatile axi_dma_out_int_ena_chn_reg_t ena;
+    volatile axi_dma_out_int_clr_chn_reg_t clr;
+} axi_dma_out_int_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_conf0_chn_reg_t out_conf0;
+    volatile axi_dma_out_conf1_chn_reg_t out_conf1;
+    volatile axi_dma_outfifo_status_chn_reg_t outfifo_status;
+    volatile axi_dma_out_push_chn_reg_t out_push;
+    volatile axi_dma_out_link1_chn_reg_t out_link1;
+    volatile axi_dma_out_link2_chn_reg_t out_link2;
+    volatile axi_dma_out_state_chn_reg_t out_state;
+    volatile axi_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
+    volatile axi_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
+    volatile axi_dma_out_dscr_chn_reg_t out_dscr;
+    volatile axi_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
+    volatile axi_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
+    volatile axi_dma_out_pri_chn_reg_t out_pri;
+    volatile axi_dma_out_peri_sel_chn_reg_t out_peri_sel;
+} axi_dma_out_conf_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_crc_init_data_chn_reg_t out_crc_init_data;
+    volatile axi_dma_tx_crc_width_chn_reg_t tx_crc_width;
+    volatile axi_dma_out_crc_clear_chn_reg_t out_crc_clear;
+    volatile axi_dma_out_crc_final_result_chn_reg_t out_crc_final_result;
+    volatile axi_dma_tx_crc_en_wr_data_chn_reg_t tx_crc_en_wr_data;
+    volatile axi_dma_tx_crc_en_addr_chn_reg_t tx_crc_en_addr;
+    volatile axi_dma_tx_crc_data_en_wr_data_chn_reg_t tx_crc_data_en_wr_data;
+    volatile axi_dma_tx_crc_data_en_addr_chn_reg_t tx_crc_data_en_addr;
+} axi_dma_out_crc_chn_reg_t;
+
+typedef struct {
+    volatile axi_dma_out_int_chn_reg_t intr;
+    volatile axi_dma_out_conf_chn_reg_t conf;
+    volatile axi_dma_out_crc_chn_reg_t crc;
+} axi_dma_out_reg_t;
+
+typedef struct {
+    volatile axi_dma_in_reg_t in[3];
+    volatile axi_dma_out_reg_t out[3];
+    volatile axi_dma_arb_timeout_reg_t arb_timeout;
+    volatile axi_dma_weight_en_reg_t weight_en;
+    volatile axi_dma_in_mem_conf_reg_t in_mem_conf;
+    volatile axi_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile axi_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile axi_dma_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile axi_dma_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile axi_dma_in_reset_avail_chn_reg_t in_reset_avail_chn[3];
+    volatile axi_dma_out_reset_avail_chn_reg_t out_reset_avail_chn[3];
+    uint32_t reserved_2a4;
+    volatile axi_dma_misc_conf_reg_t misc_conf;
+    volatile axi_dma_rdn_result_reg_t rdn_result;
+    volatile axi_dma_rdn_eco_high_reg_t rdn_eco_high;
+    volatile axi_dma_rdn_eco_low_reg_t rdn_eco_low;
+    volatile axi_dma_wresp_cnt_reg_t wresp_cnt;
+    volatile axi_dma_rresp_cnt_reg_t rresp_cnt;
+    volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
+    volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
+    volatile axi_dma_date_reg_t date;
+    volatile axi_dma_link_switch_state_reg_t link_switch_state;
+} axi_dma_dev_t;
+
+extern axi_dma_dev_t AXI_DMA;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_dma_dev_t) == 0x2e0, "Invalid size of axi_dma_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/axi_perf_mon_reg.h b/components/soc/esp32s31/register/soc/axi_perf_mon_reg.h
new file mode 100644
index 00000000000..23cdb93c8b8
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/axi_perf_mon_reg.h
@@ -0,0 +1,6881 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_PERF_MON_CLK_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x0)
+/** AXI_PERF_MON_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  reserved
+ */
+#define AXI_PERF_MON_CLK_EN    (BIT(0))
+#define AXI_PERF_MON_CLK_EN_M  (AXI_PERF_MON_CLK_EN_V << AXI_PERF_MON_CLK_EN_S)
+#define AXI_PERF_MON_CLK_EN_V  0x00000001U
+#define AXI_PERF_MON_CLK_EN_S  0
+
+/** AXI_PERF_MON_AGENT_SELECT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_AGENT_SELECT_REG (DR_REG_AXI_PERF_MON_BASE + 0x4)
+/** AXI_PERF_MON_AGENT_SELECT : R/W; bitpos: [31:0]; default: 0;
+ *  Select Agent in slot to be monitored, 4 bits means one agent number
+ */
+#define AXI_PERF_MON_AGENT_SELECT    0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_M  (AXI_PERF_MON_AGENT_SELECT_V << AXI_PERF_MON_AGENT_SELECT_S)
+#define AXI_PERF_MON_AGENT_SELECT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_AGENT_SELECT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x8)
+/** AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0xc)
+/** AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x10)
+/** AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x14)
+/** AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x18)
+/** AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c)
+/** AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x20)
+/** AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x24)
+/** AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x28)
+/** AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c)
+/** AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x30)
+/** AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x34)
+/** AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x38)
+/** AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c)
+/** AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x40)
+/** AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x44)
+/** AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x48)
+/** AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c)
+/** AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x50)
+/** AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x54)
+/** AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x58)
+/** AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c)
+/** AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x60)
+/** AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x64)
+/** AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x68)
+/** AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x6c)
+/** AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x70)
+/** AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER3_REG (DR_REG_AXI_PERF_MON_BASE + 0x74)
+/** AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x78)
+/** AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x7c)
+/** AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x80)
+/** AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x84)
+/** AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x88)
+/** AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x8c)
+/** AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER4_REG (DR_REG_AXI_PERF_MON_BASE + 0x90)
+/** AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x94)
+/** AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x98)
+/** AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0x9c)
+/** AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0xa0)
+/** AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0xa4)
+/** AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0xa8)
+/** AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER5_REG (DR_REG_AXI_PERF_MON_BASE + 0xac)
+/** AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xb0)
+/** AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xb4)
+/** AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xb8)
+/** AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xbc)
+/** AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xc0)
+/** AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xc4)
+/** AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER6_REG (DR_REG_AXI_PERF_MON_BASE + 0xc8)
+/** AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xcc)
+/** AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xd0)
+/** AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xd4)
+/** AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xd8)
+/** AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xdc)
+/** AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xe0)
+/** AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_COUNTER7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER7_REG (DR_REG_AXI_PERF_MON_BASE + 0xe4)
+/** AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT : RO; bitpos: [31:0]; default: 0;
+ *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+ *  [31:16] is max result
+ */
+#define AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT_M  (AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT_V << AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_COUNTER7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xe8)
+/** AXI_PERF_MON_SEL_AG0_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xec)
+/** AXI_PERF_MON_SEL_AG1_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xf0)
+/** AXI_PERF_MON_SEL_AG2_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xf4)
+/** AXI_PERF_MON_SEL_AG3_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xf8)
+/** AXI_PERF_MON_SEL_AG4_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0xfc)
+/** AXI_PERF_MON_SEL_AG5_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x100)
+/** AXI_PERF_MON_SEL_AG6_RANGE0_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE0_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE0_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE0_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE0_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE0_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE0_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x104)
+/** AXI_PERF_MON_SEL_AG0_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x108)
+/** AXI_PERF_MON_SEL_AG1_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x10c)
+/** AXI_PERF_MON_SEL_AG2_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x110)
+/** AXI_PERF_MON_SEL_AG3_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x114)
+/** AXI_PERF_MON_SEL_AG4_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x118)
+/** AXI_PERF_MON_SEL_AG5_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x11c)
+/** AXI_PERF_MON_SEL_AG6_RANGE1_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE1_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE1_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE1_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE1_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE1_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE1_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x120)
+/** AXI_PERF_MON_SEL_AG0_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x124)
+/** AXI_PERF_MON_SEL_AG1_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x128)
+/** AXI_PERF_MON_SEL_AG2_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x12c)
+/** AXI_PERF_MON_SEL_AG3_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x130)
+/** AXI_PERF_MON_SEL_AG4_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x134)
+/** AXI_PERF_MON_SEL_AG5_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x138)
+/** AXI_PERF_MON_SEL_AG6_RANGE2_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE2_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE2_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE2_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE2_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE2_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE2_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x13c)
+/** AXI_PERF_MON_SEL_AG0_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x140)
+/** AXI_PERF_MON_SEL_AG1_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x144)
+/** AXI_PERF_MON_SEL_AG2_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x148)
+/** AXI_PERF_MON_SEL_AG3_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x14c)
+/** AXI_PERF_MON_SEL_AG4_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x150)
+/** AXI_PERF_MON_SEL_AG5_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x154)
+/** AXI_PERF_MON_SEL_AG6_RANGE3_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE3_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE3_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE3_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE3_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE3_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE3_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x158)
+/** AXI_PERF_MON_SEL_AG0_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x15c)
+/** AXI_PERF_MON_SEL_AG1_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x160)
+/** AXI_PERF_MON_SEL_AG2_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x164)
+/** AXI_PERF_MON_SEL_AG3_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x168)
+/** AXI_PERF_MON_SEL_AG4_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x16c)
+/** AXI_PERF_MON_SEL_AG5_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x170)
+/** AXI_PERF_MON_SEL_AG6_RANGE4_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE4_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE4_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE4_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE4_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE4_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE4_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x174)
+/** AXI_PERF_MON_SEL_AG0_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x178)
+/** AXI_PERF_MON_SEL_AG1_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x17c)
+/** AXI_PERF_MON_SEL_AG2_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x180)
+/** AXI_PERF_MON_SEL_AG3_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x184)
+/** AXI_PERF_MON_SEL_AG4_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x188)
+/** AXI_PERF_MON_SEL_AG5_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x18c)
+/** AXI_PERF_MON_SEL_AG6_RANGE5_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE5_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE5_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE5_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE5_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE5_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE5_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x190)
+/** AXI_PERF_MON_SEL_AG0_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x194)
+/** AXI_PERF_MON_SEL_AG1_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x198)
+/** AXI_PERF_MON_SEL_AG2_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x19c)
+/** AXI_PERF_MON_SEL_AG3_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a0)
+/** AXI_PERF_MON_SEL_AG4_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a4)
+/** AXI_PERF_MON_SEL_AG5_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x1a8)
+/** AXI_PERF_MON_SEL_AG6_RANGE6_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE6_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE6_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE6_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE6_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE6_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE6_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1ac)
+/** AXI_PERF_MON_SEL_AG0_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG0_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG0_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG0_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b0)
+/** AXI_PERF_MON_SEL_AG1_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG1_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG1_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG1_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b4)
+/** AXI_PERF_MON_SEL_AG2_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG2_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG2_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG2_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1b8)
+/** AXI_PERF_MON_SEL_AG3_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG3_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG3_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG3_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1bc)
+/** AXI_PERF_MON_SEL_AG4_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG4_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG4_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG4_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c0)
+/** AXI_PERF_MON_SEL_AG5_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG5_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG5_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG5_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c4)
+/** AXI_PERF_MON_SEL_AG6_RANGE7_RESULT : RO; bitpos: [15:0]; default: 0;
+ *  The interval statistics results in this counter for sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_RANGE7_RESULT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE7_RESULT_M  (AXI_PERF_MON_SEL_AG6_RANGE7_RESULT_V << AXI_PERF_MON_SEL_AG6_RANGE7_RESULT_S)
+#define AXI_PERF_MON_SEL_AG6_RANGE7_RESULT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RANGE7_RESULT_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1c8)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1cc)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1d0)
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1d4)
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1d8)
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1dc)
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x1e0)
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1e4)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1e8)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1ec)
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1f0)
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1f4)
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1f8)
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x1fc)
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x200)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x204)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x208)
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x20c)
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x210)
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x214)
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x218)
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x21c)
+/** AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x220)
+/** AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x224)
+/** AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x228)
+/** AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x22c)
+/** AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x230)
+/** AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x234)
+/** AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+ *  [23:8] for ARID
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x238)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x23c)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x240)
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x244)
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x248)
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x24c)
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_REG (DR_REG_AXI_PERF_MON_BASE + 0x250)
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_M  (AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_V << AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_S)
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x254)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x258)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x25c)
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x260)
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x264)
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x268)
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_REG (DR_REG_AXI_PERF_MON_BASE + 0x26c)
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_M  (AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_V << AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_S)
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x270)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x274)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x278)
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x27c)
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x280)
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x284)
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_REG (DR_REG_AXI_PERF_MON_BASE + 0x288)
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_M  (AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_V << AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_S)
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x28c)
+/** AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x290)
+/** AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x294)
+/** AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x298)
+/** AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x29c)
+/** AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x2a0)
+/** AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_REG (DR_REG_AXI_PERF_MON_BASE + 0x2a4)
+/** AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3 : RO; bitpos: [15:0]; default: 0;
+ *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+ *  [23:8] for AWID
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_M  (AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_V << AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_S)
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_AXI_INFO_RECORD3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2a8)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2ac)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2b0)
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2b4)
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2b8)
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2bc)
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c0)
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_M  (AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_V << AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_S)
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c4)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2c8)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2cc)
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2d0)
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2d4)
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2d8)
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_REG (DR_REG_AXI_PERF_MON_BASE + 0x2dc)
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_M  (AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_V << AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_S)
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2e0)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2e4)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2e8)
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2ec)
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2f0)
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2f4)
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_REG (DR_REG_AXI_PERF_MON_BASE + 0x2f8)
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_M  (AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_V << AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_S)
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x2fc)
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x300)
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x304)
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x308)
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x30c)
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x310)
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_REG (DR_REG_AXI_PERF_MON_BASE + 0x314)
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+ *  Read and [31:16] for write
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_M  (AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_V << AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_S)
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_DATA3_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x318)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x31c)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x320)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x324)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x328)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x32c)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_REG (DR_REG_AXI_PERF_MON_BASE + 0x330)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE0_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x334)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x338)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x33c)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x340)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x344)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x348)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_REG (DR_REG_AXI_PERF_MON_BASE + 0x34c)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE1_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x350)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x354)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x358)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x35c)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x360)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x364)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_REG (DR_REG_AXI_PERF_MON_BASE + 0x368)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE2_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x36c)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x370)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x374)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x378)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x37c)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x380)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_REG (DR_REG_AXI_PERF_MON_BASE + 0x384)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE3_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x388)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x38c)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x390)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x394)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x398)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x39c)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_REG (DR_REG_AXI_PERF_MON_BASE + 0x3a0)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE4_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3a4)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3a8)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3ac)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3b0)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3b4)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3b8)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_REG (DR_REG_AXI_PERF_MON_BASE + 0x3bc)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE5_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c0)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c4)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3c8)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3cc)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3d0)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3d4)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_REG (DR_REG_AXI_PERF_MON_BASE + 0x3d8)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE6_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3dc)
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3e0)
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3e4)
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3e8)
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3ec)
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3f0)
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_REG (DR_REG_AXI_PERF_MON_BASE + 0x3f4)
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH : R/W; bitpos: [15:0]; default: 0;
+ *  The x Upper limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_HIGH_S  0
+/** AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW : R/W; bitpos: [31:16]; default: 0;
+ *  The x Lower limit of interval statistics for sel metric in sel agent
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW_M  (AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW_V << AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_RANGE7_CNT_LOW_S  16
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x3f8)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x3fc)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x400)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x404)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x408)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x40c)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x410)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x414)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x418)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x41c)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x420)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x424)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x428)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x42c)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x430)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x434)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x438)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x43c)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x440)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x444)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x448)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x44c)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x450)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x454)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x458)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x45c)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x460)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_REG (DR_REG_AXI_PERF_MON_BASE + 0x464)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x468)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x46c)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x470)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x474)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x478)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x47c)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_REG (DR_REG_AXI_PERF_MON_BASE + 0x480)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x484)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x488)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x48c)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x490)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x494)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x498)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_REG (DR_REG_AXI_PERF_MON_BASE + 0x49c)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2 : R/W; bitpos: [31:0]; default: 0;
+ *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+ *  with addr
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_MASK2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4a0)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4a4)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4a8)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4ac)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4b0)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4b4)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4b8)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4bc)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c0)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c4)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4c8)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4cc)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4d0)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x4d4)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4d8)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4dc)
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4e0)
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4e4)
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4e8)
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4ec)
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x4f0)
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4f4)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4f8)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x4fc)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x500)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x504)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x508)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_REG (DR_REG_AXI_PERF_MON_BASE + 0x50c)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER0_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x510)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x514)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x518)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x51c)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x520)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x524)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_REG (DR_REG_AXI_PERF_MON_BASE + 0x528)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x52c)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x530)
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x534)
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x538)
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x53c)
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x540)
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_REG (DR_REG_AXI_PERF_MON_BASE + 0x544)
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2 : R/W; bitpos: [31:0]; default: 0;
+ *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+ *  compare with addr filter, if compare result same will pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER2_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x548)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x54c)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x550)
+/** AXI_PERF_MON_SEL_AG2_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x554)
+/** AXI_PERF_MON_SEL_AG3_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x558)
+/** AXI_PERF_MON_SEL_AG4_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x55c)
+/** AXI_PERF_MON_SEL_AG5_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_REG (DR_REG_AXI_PERF_MON_BASE + 0x560)
+/** AXI_PERF_MON_SEL_AG6_METRIC_SELECT1 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT1    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_M  (AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_V << AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT1_S  0
+
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x564)
+/** AXI_PERF_MON_SEL_AG0_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG0_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x568)
+/** AXI_PERF_MON_SEL_AG1_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG1_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x56c)
+/** AXI_PERF_MON_SEL_AG2_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG2_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x570)
+/** AXI_PERF_MON_SEL_AG3_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG3_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x574)
+/** AXI_PERF_MON_SEL_AG4_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG4_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x578)
+/** AXI_PERF_MON_SEL_AG5_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG5_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_REG (DR_REG_AXI_PERF_MON_BASE + 0x57c)
+/** AXI_PERF_MON_SEL_AG6_METRIC_SELECT2 : R/W; bitpos: [31:0]; default: 0;
+ *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+ *  metric is selected for current counter, high 3 bits means range metric this counter
+ *  measured, a counter can use metric and range measure at the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT2    0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_M  (AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_V << AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_S)
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_V  0xFFFFFFFFU
+#define AXI_PERF_MON_SEL_AG6_METRIC_SELECT2_S  0
+
+/** AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_RD_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x580)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_REGION_SEL_S  3
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_REGION_SEL_S  6
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_REGION_SEL_S  9
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_REGION_SEL_S  12
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL : R/W; bitpos: [17:15]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_REGION_SEL_S  15
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  SW config Read region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_REGION_SEL_S  18
+
+/** AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_WR_ADDR_REGION_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x584)
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_REGION_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL : R/W; bitpos: [5:3]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_REGION_SEL_S  3
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_REGION_SEL_S  6
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL : R/W; bitpos: [11:9]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_REGION_SEL_S  9
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_REGION_SEL_S  12
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL : R/W; bitpos: [17:15]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_REGION_SEL_S  15
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  SW config Write region select, use with mask and filter, only when addr in one
+ *  region and this region has been sel, will measure the transaction data num
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL    0x00000007U
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL_V  0x00000007U
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_REGION_SEL_S  18
+
+/** AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_ADDR_FILTER_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x588)
+/** AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_ADDR_FILTER_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_ADDR_FILTER_EN_S  1
+/** AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RD_ADDR_FILTER_EN_S  2
+/** AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RD_ADDR_FILTER_EN_S  3
+/** AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN : R/W; bitpos: [4]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RD_ADDR_FILTER_EN_S  4
+/** AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN : R/W; bitpos: [5]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RD_ADDR_FILTER_EN_S  5
+/** AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN : R/W; bitpos: [6]; default: 0;
+ *  Enable read addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RD_ADDR_FILTER_EN_S  6
+/** AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN : R/W; bitpos: [7]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN    (BIT(7))
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_ADDR_FILTER_EN_S  7
+/** AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN    (BIT(8))
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_ADDR_FILTER_EN_S  8
+/** AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN    (BIT(9))
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_WR_ADDR_FILTER_EN_S  9
+/** AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN : R/W; bitpos: [10]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN    (BIT(10))
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_WR_ADDR_FILTER_EN_S  10
+/** AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN : R/W; bitpos: [11]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN    (BIT(11))
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_WR_ADDR_FILTER_EN_S  11
+/** AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN : R/W; bitpos: [12]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN    (BIT(12))
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_WR_ADDR_FILTER_EN_S  12
+/** AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN : R/W; bitpos: [13]; default: 0;
+ *  Enable write addr filter function, if 0, all address access will be record
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN    (BIT(13))
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN_M  (AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN_V << AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_WR_ADDR_FILTER_EN_S  13
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x58c)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN : WT; bitpos: [0]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_EN_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN : WT; bitpos: [1]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_EN_S  1
+/** AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN : WT; bitpos: [2]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_EN_S  2
+/** AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN : WT; bitpos: [3]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_EN_S  3
+/** AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN : WT; bitpos: [4]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_EN_S  4
+/** AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN : WT; bitpos: [5]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_EN_S  5
+/** AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN : WT; bitpos: [6]; default: 0;
+ *  SW use to stop event log function, record information will keep
+ */
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN_M  (AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN_V << AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN_S)
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_EN_S  6
+
+/** AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_SW_RECORD_STOP_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x590)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR : WT; bitpos: [0]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR : WT; bitpos: [1]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_CLR_S  1
+/** AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR : WT; bitpos: [2]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_CLR_S  2
+/** AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR : WT; bitpos: [3]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_CLR_S  3
+/** AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR : WT; bitpos: [4]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_CLR_S  4
+/** AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR : WT; bitpos: [5]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_CLR_S  5
+/** AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR : WT; bitpos: [6]; default: 0;
+ *  SW use to clear event log function stop, record new transaction from now
+ */
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR_M  (AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR_V << AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR_S)
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_CLR_S  6
+
+/** AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INS_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x594)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TEST_EN_S  3
+/** AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN : R/W; bitpos: [4]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN    (BIT(4))
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TEST_EN_S  4
+/** AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN : R/W; bitpos: [5]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN    (BIT(5))
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TEST_EN_S  5
+/** AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN : R/W; bitpos: [6]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN    (BIT(6))
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TEST_EN_S  6
+/** AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN : R/W; bitpos: [7]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN    (BIT(7))
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TEST_EN_S  7
+/** AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN : R/W; bitpos: [8]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN    (BIT(8))
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TEST_EN_S  8
+/** AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN    (BIT(9))
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TEST_EN_S  9
+/** AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN : R/W; bitpos: [10]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN    (BIT(10))
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TEST_EN_S  10
+/** AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN : R/W; bitpos: [11]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN    (BIT(11))
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TEST_EN_S  11
+/** AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN : R/W; bitpos: [12]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN    (BIT(12))
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TEST_EN_S  12
+/** AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN : R/W; bitpos: [13]; default: 0;
+ *  Enable Read instantaneous bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN    (BIT(13))
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TEST_EN_S  13
+
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x598)
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x59c)
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x5a0)
+/** AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x5a4)
+/** AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x5a8)
+/** AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x5ac)
+/** AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_DATA_LIMIT_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_DATA_LIMIT_REG (DR_REG_AXI_PERF_MON_BASE + 0x5b0)
+/** AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_RD_DATA_LIMIT_S  0
+/** AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT : R/W; bitpos: [31:16]; default:
+ *  0;
+ *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+ *  enable
+ */
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT_M  (AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT_V << AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT_S)
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_SW_RECORD_STOP_WR_DATA_LIMIT_S  16
+
+/** AXI_PERF_MON_SEL_AG0_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5b4)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG1_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5b8)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG2_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5bc)
+/** AXI_PERF_MON_SEL_AG2_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG2_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG2_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG2_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG2_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG2_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG3_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c0)
+/** AXI_PERF_MON_SEL_AG3_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG3_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG3_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG3_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG3_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG3_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG4_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c4)
+/** AXI_PERF_MON_SEL_AG4_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG4_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG4_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG4_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG4_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG4_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG5_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5c8)
+/** AXI_PERF_MON_SEL_AG5_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG5_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG5_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG5_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG5_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG5_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG6_ID_MASK_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_ID_MASK_REG (DR_REG_AXI_PERF_MON_BASE + 0x5cc)
+/** AXI_PERF_MON_SEL_AG6_RD_ID_MASK : R/W; bitpos: [6:0]; default: 0;
+ *  Read id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_RD_ID_MASK_M  (AXI_PERF_MON_SEL_AG6_RD_ID_MASK_V << AXI_PERF_MON_SEL_AG6_RD_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_RD_ID_MASK_S  0
+/** AXI_PERF_MON_SEL_AG6_WR_ID_MASK : R/W; bitpos: [13:7]; default: 0;
+ *  Write id mask, ignore mask id bits
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ID_MASK    0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_WR_ID_MASK_M  (AXI_PERF_MON_SEL_AG6_WR_ID_MASK_V << AXI_PERF_MON_SEL_AG6_WR_ID_MASK_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ID_MASK_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_WR_ID_MASK_S  7
+
+/** AXI_PERF_MON_SEL_AG0_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5d0)
+/** AXI_PERF_MON_SEL_AG0_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG0_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG1_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5d4)
+/** AXI_PERF_MON_SEL_AG1_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG1_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG2_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5d8)
+/** AXI_PERF_MON_SEL_AG2_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG2_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG2_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG2_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG2_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG2_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG2_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG2_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG2_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG3_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5dc)
+/** AXI_PERF_MON_SEL_AG3_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG3_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG3_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG3_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG3_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG3_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG3_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG3_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG3_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG4_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5e0)
+/** AXI_PERF_MON_SEL_AG4_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG4_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG4_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG4_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG4_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG4_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG4_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG4_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG4_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG5_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5e4)
+/** AXI_PERF_MON_SEL_AG5_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG5_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG5_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG5_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG5_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG5_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG5_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG5_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG5_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG6_ID_FILTER_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_ID_FILTER_REG (DR_REG_AXI_PERF_MON_BASE + 0x5e8)
+/** AXI_PERF_MON_SEL_AG6_RD_ID_FILTER : R/W; bitpos: [6:0]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_RD_ID_FILTER_M  (AXI_PERF_MON_SEL_AG6_RD_ID_FILTER_V << AXI_PERF_MON_SEL_AG6_RD_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG6_RD_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_RD_ID_FILTER_S  0
+/** AXI_PERF_MON_SEL_AG6_WR_ID_FILTER : R/W; bitpos: [13:7]; default: 0;
+ *  Use with mask, no mask bits must same as filter bits, the pass filter
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_ID_FILTER    0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_WR_ID_FILTER_M  (AXI_PERF_MON_SEL_AG6_WR_ID_FILTER_V << AXI_PERF_MON_SEL_AG6_WR_ID_FILTER_S)
+#define AXI_PERF_MON_SEL_AG6_WR_ID_FILTER_V  0x0000007FU
+#define AXI_PERF_MON_SEL_AG6_WR_ID_FILTER_S  7
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_EN_REG (DR_REG_AXI_PERF_MON_BASE + 0x5ec)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_EN_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN : R/W; bitpos: [1]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_EN_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_EN_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN : R/W; bitpos: [3]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_EN_S  3
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN    (BIT(4))
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_EN_S  4
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN : R/W; bitpos: [5]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN    (BIT(5))
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_EN_S  5
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN    (BIT(6))
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_EN_S  6
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN : R/W; bitpos: [7]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN    (BIT(7))
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_EN_S  7
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN    (BIT(8))
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_EN_S  8
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN : R/W; bitpos: [9]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN    (BIT(9))
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_EN_S  9
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN    (BIT(10))
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_EN_S  10
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN : R/W; bitpos: [11]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN    (BIT(11))
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_EN_S  11
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN    (BIT(12))
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_EN_S  12
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN : R/W; bitpos: [13]; default: 0;
+ *  Enable Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN    (BIT(13))
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_EN_S  13
+
+/** AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_BANDW_TEST_STOP_REG (DR_REG_AXI_PERF_MON_BASE + 0x5f0)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TEST_STOP_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP : R/W; bitpos: [1]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP    (BIT(1))
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TEST_STOP_S  1
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP    (BIT(2))
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TEST_STOP_S  2
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP : R/W; bitpos: [3]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP    (BIT(3))
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TEST_STOP_S  3
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP : R/W; bitpos: [4]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP    (BIT(4))
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TEST_STOP_S  4
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP : R/W; bitpos: [5]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP    (BIT(5))
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TEST_STOP_S  5
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP : R/W; bitpos: [6]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP    (BIT(6))
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TEST_STOP_S  6
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP : R/W; bitpos: [7]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP    (BIT(7))
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TEST_STOP_S  7
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP : R/W; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP    (BIT(8))
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TEST_STOP_S  8
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP : R/W; bitpos: [9]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP    (BIT(9))
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TEST_STOP_S  9
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP : R/W; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP    (BIT(10))
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TEST_STOP_S  10
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP : R/W; bitpos: [11]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP    (BIT(11))
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TEST_STOP_S  11
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP : R/W; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP    (BIT(12))
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TEST_STOP_S  12
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP : R/W; bitpos: [13]; default: 0;
+ *  Stop Read average bandwidth test for all select agent in the same time
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP    (BIT(13))
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TEST_STOP_S  13
+
+/** AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x5f4)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x5f8)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG2_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x5fc)
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG3_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x600)
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG4_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x604)
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG5_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x608)
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG6_BANDW_TRIGGER_IN_SEL_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_BANDW_TRIGGER_IN_SEL_REG (DR_REG_AXI_PERF_MON_BASE + 0x60c)
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_EN_SEL_S  0
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [7:4]; default: 0;
+ *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+ *  source
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TRIGGER_STOP_SEL_S  4
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL : R/W; bitpos: [11:8]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_EN_SEL_S  8
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL : R/W; bitpos: [15:12]; default: 0;
+ *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+ *  is one source
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL    0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL_V  0x0000000FU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TRIGGER_STOP_SEL_S  12
+
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x610)
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x614)
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x618)
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x61c)
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x620)
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x624)
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x628)
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_WR_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x62c)
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG0_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x630)
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG1_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x634)
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG2_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x638)
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG3_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x63c)
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG4_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x640)
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG5_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_CNT_VALID_STROBE_NUM_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_CNT_VALID_STROBE_NUM_REG (DR_REG_AXI_PERF_MON_BASE + 0x644)
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM : R/W; bitpos: [7:0];
+ *  default: 0;
+ *  Set this register to configure the time valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_TIME_CNT_VALID_STROBE_NUM_S  0
+/** AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM : R/W; bitpos: [15:8];
+ *  default: 0;
+ *  Set this register to configure the data valid scaling multiplier
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM    0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_M  (AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V << AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S)
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_V  0x000000FFU
+#define AXI_PERF_MON_SEL_AG6_RD_BANDW_DATA_CNT_VALID_STROBE_NUM_S  8
+
+/** AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG0_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x648)
+/** AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG0_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG1_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x64c)
+/** AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG1_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG2_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG2_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x650)
+/** AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG2_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG3_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG3_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x654)
+/** AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG3_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG4_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG4_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x658)
+/** AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG4_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG5_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG5_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x65c)
+/** AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG5_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG6_INS_BANDW_TIME_THR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG6_INS_BANDW_TIME_THR_REG (DR_REG_AXI_PERF_MON_BASE + 0x660)
+/** AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR : R/W; bitpos: [15:0]; default: 0;
+ *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_RD_INS_BANDW_TIME_THR_S  0
+/** AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR : R/W; bitpos: [31:16]; default: 0;
+ *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+ *  and will fresh counter to count again
+ */
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR    0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR_M  (AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR_V << AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR_S)
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR_V  0x0000FFFFU
+#define AXI_PERF_MON_SEL_AG6_WR_INS_BANDW_TIME_THR_S  16
+
+/** AXI_PERF_MON_SEL_AG_INT_RAW_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_RAW_REG (DR_REG_AXI_PERF_MON_BASE + 0x664)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [0];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [1];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  1
+/** AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [2];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  2
+/** AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [3];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  3
+/** AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [4];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  4
+/** AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [5];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  5
+/** AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW : R/WTC/SS; bitpos: [6];
+ *  default: 0;
+ *  The raw interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW_M  (AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW_V << AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW_S)
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_RAW_S  6
+
+/** AXI_PERF_MON_SEL_AG_INT_ST_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ST_REG (DR_REG_AXI_PERF_MON_BASE + 0x668)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ST_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ST_S  1
+/** AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ST_S  2
+/** AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ST_S  3
+/** AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ST_S  4
+/** AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ST_S  5
+/** AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST_M  (AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST_V << AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST_S)
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ST_S  6
+
+/** AXI_PERF_MON_SEL_AG_INT_ENA_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_ENA_REG (DR_REG_AXI_PERF_MON_BASE + 0x66c)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  1
+/** AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  2
+/** AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  3
+/** AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  4
+/** AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  5
+/** AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA_M  (AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA_V << AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA_S)
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_ENA_S  6
+
+/** AXI_PERF_MON_SEL_AG_INT_CLR_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_SEL_AG_INT_CLR_REG (DR_REG_AXI_PERF_MON_BASE + 0x670)
+/** AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(0))
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG0_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  0
+/** AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(1))
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG1_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  1
+/** AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(2))
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG2_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  2
+/** AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(3))
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG3_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  3
+/** AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(4))
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG4_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  4
+/** AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(5))
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG5_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  5
+/** AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear instantaneous bandwidth test data under limit int
+ */
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR    (BIT(6))
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR_M  (AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR_V << AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR_S)
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR_V  0x00000001U
+#define AXI_PERF_MON_SEL_AG6_RECORD_CNT_UNDER_LIMIT_INT_CLR_S  6
+
+/** AXI_PERF_MON_DATE_REG register
+ *  reserved
+ */
+#define AXI_PERF_MON_DATE_REG (DR_REG_AXI_PERF_MON_BASE + 0x674)
+/** AXI_PERF_MON_DATE : R/W; bitpos: [27:0]; default: 2506030;
+ *  reserved
+ */
+#define AXI_PERF_MON_DATE    0x0FFFFFFFU
+#define AXI_PERF_MON_DATE_M  (AXI_PERF_MON_DATE_V << AXI_PERF_MON_DATE_S)
+#define AXI_PERF_MON_DATE_V  0x0FFFFFFFU
+#define AXI_PERF_MON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/axi_perf_mon_struct.h b/components/soc/esp32s31/register/soc/axi_perf_mon_struct.h
new file mode 100644
index 00000000000..83122f1e7b5
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/axi_perf_mon_struct.h
@@ -0,0 +1,7188 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of clk_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  reserved
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_perf_mon_clk_en_reg_t;
+
+/** Type of sel_ag0_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_high:16;
+        /** sel_ag0_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range0_reg_t;
+
+/** Type of sel_ag1_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_high:16;
+        /** sel_ag1_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range0_reg_t;
+
+/** Type of sel_ag2_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range0_cnt_high:16;
+        /** sel_ag2_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range0_reg_t;
+
+/** Type of sel_ag3_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range0_cnt_high:16;
+        /** sel_ag3_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range0_reg_t;
+
+/** Type of sel_ag4_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range0_cnt_high:16;
+        /** sel_ag4_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range0_reg_t;
+
+/** Type of sel_ag5_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range0_cnt_high:16;
+        /** sel_ag5_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range0_reg_t;
+
+/** Type of sel_ag6_metric_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range0_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range0_cnt_high:16;
+        /** sel_ag6_metric_range0_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range0_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range0_reg_t;
+
+/** Type of sel_ag0_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_high:16;
+        /** sel_ag0_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range1_reg_t;
+
+/** Type of sel_ag1_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_high:16;
+        /** sel_ag1_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range1_reg_t;
+
+/** Type of sel_ag2_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range1_cnt_high:16;
+        /** sel_ag2_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range1_reg_t;
+
+/** Type of sel_ag3_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range1_cnt_high:16;
+        /** sel_ag3_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range1_reg_t;
+
+/** Type of sel_ag4_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range1_cnt_high:16;
+        /** sel_ag4_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range1_reg_t;
+
+/** Type of sel_ag5_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range1_cnt_high:16;
+        /** sel_ag5_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range1_reg_t;
+
+/** Type of sel_ag6_metric_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range1_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range1_cnt_high:16;
+        /** sel_ag6_metric_range1_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range1_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range1_reg_t;
+
+/** Type of sel_ag0_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_high:16;
+        /** sel_ag0_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range2_reg_t;
+
+/** Type of sel_ag1_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_high:16;
+        /** sel_ag1_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range2_reg_t;
+
+/** Type of sel_ag2_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range2_cnt_high:16;
+        /** sel_ag2_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range2_reg_t;
+
+/** Type of sel_ag3_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range2_cnt_high:16;
+        /** sel_ag3_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range2_reg_t;
+
+/** Type of sel_ag4_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range2_cnt_high:16;
+        /** sel_ag4_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range2_reg_t;
+
+/** Type of sel_ag5_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range2_cnt_high:16;
+        /** sel_ag5_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range2_reg_t;
+
+/** Type of sel_ag6_metric_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range2_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range2_cnt_high:16;
+        /** sel_ag6_metric_range2_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range2_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range2_reg_t;
+
+/** Type of sel_ag0_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_high:16;
+        /** sel_ag0_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range3_reg_t;
+
+/** Type of sel_ag1_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_high:16;
+        /** sel_ag1_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range3_reg_t;
+
+/** Type of sel_ag2_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range3_cnt_high:16;
+        /** sel_ag2_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range3_reg_t;
+
+/** Type of sel_ag3_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range3_cnt_high:16;
+        /** sel_ag3_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range3_reg_t;
+
+/** Type of sel_ag4_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range3_cnt_high:16;
+        /** sel_ag4_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range3_reg_t;
+
+/** Type of sel_ag5_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range3_cnt_high:16;
+        /** sel_ag5_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range3_reg_t;
+
+/** Type of sel_ag6_metric_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range3_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range3_cnt_high:16;
+        /** sel_ag6_metric_range3_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range3_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range3_reg_t;
+
+/** Type of sel_ag0_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_high:16;
+        /** sel_ag0_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range4_reg_t;
+
+/** Type of sel_ag1_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_high:16;
+        /** sel_ag1_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range4_reg_t;
+
+/** Type of sel_ag2_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range4_cnt_high:16;
+        /** sel_ag2_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range4_reg_t;
+
+/** Type of sel_ag3_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range4_cnt_high:16;
+        /** sel_ag3_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range4_reg_t;
+
+/** Type of sel_ag4_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range4_cnt_high:16;
+        /** sel_ag4_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range4_reg_t;
+
+/** Type of sel_ag5_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range4_cnt_high:16;
+        /** sel_ag5_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range4_reg_t;
+
+/** Type of sel_ag6_metric_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range4_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range4_cnt_high:16;
+        /** sel_ag6_metric_range4_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range4_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range4_reg_t;
+
+/** Type of sel_ag0_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_high:16;
+        /** sel_ag0_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range5_reg_t;
+
+/** Type of sel_ag1_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_high:16;
+        /** sel_ag1_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range5_reg_t;
+
+/** Type of sel_ag2_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range5_cnt_high:16;
+        /** sel_ag2_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range5_reg_t;
+
+/** Type of sel_ag3_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range5_cnt_high:16;
+        /** sel_ag3_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range5_reg_t;
+
+/** Type of sel_ag4_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range5_cnt_high:16;
+        /** sel_ag4_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range5_reg_t;
+
+/** Type of sel_ag5_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range5_cnt_high:16;
+        /** sel_ag5_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range5_reg_t;
+
+/** Type of sel_ag6_metric_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range5_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range5_cnt_high:16;
+        /** sel_ag6_metric_range5_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range5_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range5_reg_t;
+
+/** Type of sel_ag0_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range6_cnt_high:16;
+        /** sel_ag0_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range6_reg_t;
+
+/** Type of sel_ag1_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range6_cnt_high:16;
+        /** sel_ag1_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range6_reg_t;
+
+/** Type of sel_ag2_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range6_cnt_high:16;
+        /** sel_ag2_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range6_reg_t;
+
+/** Type of sel_ag3_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range6_cnt_high:16;
+        /** sel_ag3_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range6_reg_t;
+
+/** Type of sel_ag4_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range6_cnt_high:16;
+        /** sel_ag4_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range6_reg_t;
+
+/** Type of sel_ag5_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range6_cnt_high:16;
+        /** sel_ag5_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range6_reg_t;
+
+/** Type of sel_ag6_metric_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range6_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range6_cnt_high:16;
+        /** sel_ag6_metric_range6_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range6_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range6_reg_t;
+
+/** Type of sel_ag0_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range7_cnt_high:16;
+        /** sel_ag0_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag0_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_range7_reg_t;
+
+/** Type of sel_ag1_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range7_cnt_high:16;
+        /** sel_ag1_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag1_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_range7_reg_t;
+
+/** Type of sel_ag2_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range7_cnt_high:16;
+        /** sel_ag2_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag2_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_range7_reg_t;
+
+/** Type of sel_ag3_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range7_cnt_high:16;
+        /** sel_ag3_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag3_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_range7_reg_t;
+
+/** Type of sel_ag4_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range7_cnt_high:16;
+        /** sel_ag4_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag4_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_range7_reg_t;
+
+/** Type of sel_ag5_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range7_cnt_high:16;
+        /** sel_ag5_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag5_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_range7_reg_t;
+
+/** Type of sel_ag6_metric_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_range7_cnt_high : R/W; bitpos: [15:0]; default: 0;
+         *  The x Upper limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range7_cnt_high:16;
+        /** sel_ag6_metric_range7_cnt_low : R/W; bitpos: [31:16]; default: 0;
+         *  The x Lower limit of interval statistics for sel metric in sel agent
+         */
+        uint32_t sel_ag6_metric_range7_cnt_low:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_range7_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag2_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag3_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag4_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag5_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag6_rd_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_rd_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_mask0_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag2_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag3_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag4_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag5_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag6_rd_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_rd_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_mask1_reg_t;
+
+/** Type of sel_ag0_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag1_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag2_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag3_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag4_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag5_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag6_rd_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_rd_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_mask2_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag2_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag3_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag4_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag5_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag6_wr_addr_mask0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_mask0 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_wr_addr_mask0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_mask0_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag2_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag3_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag4_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag5_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag6_wr_addr_mask1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_mask1 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_wr_addr_mask1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_mask1_reg_t;
+
+/** Type of sel_ag0_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag0_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag1_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag1_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag2_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag2_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag3_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag3_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag4_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag4_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag5_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag5_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag6_wr_addr_mask2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_mask2 : R/W; bitpos: [31:0]; default: 0;
+         *  Write addr mask of addr filter function for sel agent, mask bit will not compare
+         *  with addr
+         */
+        uint32_t sel_ag6_wr_addr_mask2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_mask2_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag2_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag3_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag4_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag5_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag6_rd_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_rd_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_filter0_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag2_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag3_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag4_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag5_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag6_rd_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_rd_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_filter1_reg_t;
+
+/** Type of sel_ag0_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag1_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag2_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag3_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag4_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag5_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag6_rd_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_rd_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_addr_filter2_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag2_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag3_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag4_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag5_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag6_wr_addr_filter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_filter0 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_wr_addr_filter0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_filter0_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag2_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag3_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag4_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag5_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag6_wr_addr_filter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_filter1 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_wr_addr_filter1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_filter1_reg_t;
+
+/** Type of sel_ag0_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag0_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag1_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag1_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag2_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag2_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag3_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag3_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag4_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag4_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag5_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag5_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag6_wr_addr_filter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_addr_filter2 : R/W; bitpos: [31:0]; default: 0;
+         *  Read addr filter of addr filter function for sel agent, no mask bit in addr will
+         *  compare with addr filter, if compare result same will pass filter
+         */
+        uint32_t sel_ag6_wr_addr_filter2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_addr_filter2_reg_t;
+
+/** Type of sel_ag0_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select1_reg_t;
+
+/** Type of sel_ag1_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select1_reg_t;
+
+/** Type of sel_ag2_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag2_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_select1_reg_t;
+
+/** Type of sel_ag3_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag3_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_select1_reg_t;
+
+/** Type of sel_ag4_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag4_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_select1_reg_t;
+
+/** Type of sel_ag5_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag5_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_select1_reg_t;
+
+/** Type of sel_ag6_metric_select1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_select1 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag6_metric_select1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_select1_reg_t;
+
+/** Type of sel_ag0_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag0_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_metric_select2_reg_t;
+
+/** Type of sel_ag1_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag1_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_metric_select2_reg_t;
+
+/** Type of sel_ag2_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag2_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_metric_select2_reg_t;
+
+/** Type of sel_ag3_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag3_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_metric_select2_reg_t;
+
+/** Type of sel_ag4_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag4_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_metric_select2_reg_t;
+
+/** Type of sel_ag5_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag5_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_metric_select2_reg_t;
+
+/** Type of sel_ag6_metric_select2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_metric_select2 : R/W; bitpos: [31:0]; default: 0;
+         *  Metric select Reg for sel agent, each agent use 8 bits, low 5 bits means which
+         *  metric is selected for current counter, high 3 bits means range metric this counter
+         *  measured, a counter can use metric and range measure at the same time
+         */
+        uint32_t sel_ag6_metric_select2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_metric_select2_reg_t;
+
+/** Type of sel_ag_rd_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_rd_addr_region_sel:3;
+        /** sel_ag1_rd_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_rd_addr_region_sel:3;
+        /** sel_ag2_rd_addr_region_sel : R/W; bitpos: [8:6]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag2_rd_addr_region_sel:3;
+        /** sel_ag3_rd_addr_region_sel : R/W; bitpos: [11:9]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag3_rd_addr_region_sel:3;
+        /** sel_ag4_rd_addr_region_sel : R/W; bitpos: [14:12]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag4_rd_addr_region_sel:3;
+        /** sel_ag5_rd_addr_region_sel : R/W; bitpos: [17:15]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag5_rd_addr_region_sel:3;
+        /** sel_ag6_rd_addr_region_sel : R/W; bitpos: [20:18]; default: 0;
+         *  SW config Read region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag6_rd_addr_region_sel:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t;
+
+/** Type of sel_ag_wr_addr_region_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_addr_region_sel : R/W; bitpos: [2:0]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag0_wr_addr_region_sel:3;
+        /** sel_ag1_wr_addr_region_sel : R/W; bitpos: [5:3]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag1_wr_addr_region_sel:3;
+        /** sel_ag2_wr_addr_region_sel : R/W; bitpos: [8:6]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag2_wr_addr_region_sel:3;
+        /** sel_ag3_wr_addr_region_sel : R/W; bitpos: [11:9]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag3_wr_addr_region_sel:3;
+        /** sel_ag4_wr_addr_region_sel : R/W; bitpos: [14:12]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag4_wr_addr_region_sel:3;
+        /** sel_ag5_wr_addr_region_sel : R/W; bitpos: [17:15]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag5_wr_addr_region_sel:3;
+        /** sel_ag6_wr_addr_region_sel : R/W; bitpos: [20:18]; default: 0;
+         *  SW config Write region select, use with mask and filter, only when addr in one
+         *  region and this region has been sel, will measure the transaction data num
+         */
+        uint32_t sel_ag6_wr_addr_region_sel:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t;
+
+/** Type of sel_ag_addr_filter_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_addr_filter_en : R/W; bitpos: [0]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_rd_addr_filter_en:1;
+        /** sel_ag1_rd_addr_filter_en : R/W; bitpos: [1]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_rd_addr_filter_en:1;
+        /** sel_ag2_rd_addr_filter_en : R/W; bitpos: [2]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag2_rd_addr_filter_en:1;
+        /** sel_ag3_rd_addr_filter_en : R/W; bitpos: [3]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag3_rd_addr_filter_en:1;
+        /** sel_ag4_rd_addr_filter_en : R/W; bitpos: [4]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag4_rd_addr_filter_en:1;
+        /** sel_ag5_rd_addr_filter_en : R/W; bitpos: [5]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag5_rd_addr_filter_en:1;
+        /** sel_ag6_rd_addr_filter_en : R/W; bitpos: [6]; default: 0;
+         *  Enable read addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag6_rd_addr_filter_en:1;
+        /** sel_ag0_wr_addr_filter_en : R/W; bitpos: [7]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag0_wr_addr_filter_en:1;
+        /** sel_ag1_wr_addr_filter_en : R/W; bitpos: [8]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag1_wr_addr_filter_en:1;
+        /** sel_ag2_wr_addr_filter_en : R/W; bitpos: [9]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag2_wr_addr_filter_en:1;
+        /** sel_ag3_wr_addr_filter_en : R/W; bitpos: [10]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag3_wr_addr_filter_en:1;
+        /** sel_ag4_wr_addr_filter_en : R/W; bitpos: [11]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag4_wr_addr_filter_en:1;
+        /** sel_ag5_wr_addr_filter_en : R/W; bitpos: [12]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag5_wr_addr_filter_en:1;
+        /** sel_ag6_wr_addr_filter_en : R/W; bitpos: [13]; default: 0;
+         *  Enable write addr filter function, if 0, all address access will be record
+         */
+        uint32_t sel_ag6_wr_addr_filter_en:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_addr_filter_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_en : WT; bitpos: [0]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag0_sw_record_stop_en:1;
+        /** sel_ag1_sw_record_stop_en : WT; bitpos: [1]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag1_sw_record_stop_en:1;
+        /** sel_ag2_sw_record_stop_en : WT; bitpos: [2]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag2_sw_record_stop_en:1;
+        /** sel_ag3_sw_record_stop_en : WT; bitpos: [3]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag3_sw_record_stop_en:1;
+        /** sel_ag4_sw_record_stop_en : WT; bitpos: [4]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag4_sw_record_stop_en:1;
+        /** sel_ag5_sw_record_stop_en : WT; bitpos: [5]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag5_sw_record_stop_en:1;
+        /** sel_ag6_sw_record_stop_en : WT; bitpos: [6]; default: 0;
+         *  SW use to stop event log function, record information will keep
+         */
+        uint32_t sel_ag6_sw_record_stop_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_en_reg_t;
+
+/** Type of sel_ag_sw_record_stop_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_clr : WT; bitpos: [0]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag0_sw_record_stop_clr:1;
+        /** sel_ag1_sw_record_stop_clr : WT; bitpos: [1]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag1_sw_record_stop_clr:1;
+        /** sel_ag2_sw_record_stop_clr : WT; bitpos: [2]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag2_sw_record_stop_clr:1;
+        /** sel_ag3_sw_record_stop_clr : WT; bitpos: [3]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag3_sw_record_stop_clr:1;
+        /** sel_ag4_sw_record_stop_clr : WT; bitpos: [4]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag4_sw_record_stop_clr:1;
+        /** sel_ag5_sw_record_stop_clr : WT; bitpos: [5]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag5_sw_record_stop_clr:1;
+        /** sel_ag6_sw_record_stop_clr : WT; bitpos: [6]; default: 0;
+         *  SW use to clear event log function stop, record new transaction from now
+         */
+        uint32_t sel_ag6_sw_record_stop_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t;
+
+/** Type of sel_ag_ins_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_rd_ins_bandw_test_en:1;
+        /** sel_ag0_wr_ins_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_ins_bandw_test_en:1;
+        /** sel_ag1_rd_ins_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_rd_ins_bandw_test_en:1;
+        /** sel_ag1_wr_ins_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_ins_bandw_test_en:1;
+        /** sel_ag2_rd_ins_bandw_test_en : R/W; bitpos: [4]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag2_rd_ins_bandw_test_en:1;
+        /** sel_ag2_wr_ins_bandw_test_en : R/W; bitpos: [5]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag2_wr_ins_bandw_test_en:1;
+        /** sel_ag3_rd_ins_bandw_test_en : R/W; bitpos: [6]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag3_rd_ins_bandw_test_en:1;
+        /** sel_ag3_wr_ins_bandw_test_en : R/W; bitpos: [7]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag3_wr_ins_bandw_test_en:1;
+        /** sel_ag4_rd_ins_bandw_test_en : R/W; bitpos: [8]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag4_rd_ins_bandw_test_en:1;
+        /** sel_ag4_wr_ins_bandw_test_en : R/W; bitpos: [9]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag4_wr_ins_bandw_test_en:1;
+        /** sel_ag5_rd_ins_bandw_test_en : R/W; bitpos: [10]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag5_rd_ins_bandw_test_en:1;
+        /** sel_ag5_wr_ins_bandw_test_en : R/W; bitpos: [11]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag5_wr_ins_bandw_test_en:1;
+        /** sel_ag6_rd_ins_bandw_test_en : R/W; bitpos: [12]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag6_rd_ins_bandw_test_en:1;
+        /** sel_ag6_wr_ins_bandw_test_en : R/W; bitpos: [13]; default: 0;
+         *  Enable Read instantaneous bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag6_wr_ins_bandw_test_en:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t;
+
+/** Type of sel_ag0_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_rd_data_limit:16;
+        /** sel_ag0_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag0_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag1_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_rd_data_limit:16;
+        /** sel_ag1_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag1_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag2_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag2_sw_record_stop_rd_data_limit:16;
+        /** sel_ag2_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag2_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag3_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag3_sw_record_stop_rd_data_limit:16;
+        /** sel_ag3_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag3_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag4_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag4_sw_record_stop_rd_data_limit:16;
+        /** sel_ag4_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag4_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag5_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag5_sw_record_stop_rd_data_limit:16;
+        /** sel_ag5_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag5_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag6_sw_record_stop_data_limit register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_sw_record_stop_rd_data_limit : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag6_sw_record_stop_rd_data_limit:16;
+        /** sel_ag6_sw_record_stop_wr_data_limit : R/W; bitpos: [31:16]; default: 0;
+         *  Read instantaneous bandwidth test data lower limit, when touch this limit, intr
+         *  enable
+         */
+        uint32_t sel_ag6_sw_record_stop_wr_data_limit:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_sw_record_stop_data_limit_reg_t;
+
+/** Type of sel_ag0_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_rd_id_mask:7;
+        /** sel_ag0_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag0_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_mask_reg_t;
+
+/** Type of sel_ag1_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_rd_id_mask:7;
+        /** sel_ag1_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag1_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_mask_reg_t;
+
+/** Type of sel_ag2_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag2_rd_id_mask:7;
+        /** sel_ag2_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag2_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_id_mask_reg_t;
+
+/** Type of sel_ag3_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag3_rd_id_mask:7;
+        /** sel_ag3_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag3_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_id_mask_reg_t;
+
+/** Type of sel_ag4_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag4_rd_id_mask:7;
+        /** sel_ag4_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag4_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_id_mask_reg_t;
+
+/** Type of sel_ag5_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag5_rd_id_mask:7;
+        /** sel_ag5_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag5_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_id_mask_reg_t;
+
+/** Type of sel_ag6_id_mask register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_id_mask : R/W; bitpos: [6:0]; default: 0;
+         *  Read id mask, ignore mask id bits
+         */
+        uint32_t sel_ag6_rd_id_mask:7;
+        /** sel_ag6_wr_id_mask : R/W; bitpos: [13:7]; default: 0;
+         *  Write id mask, ignore mask id bits
+         */
+        uint32_t sel_ag6_wr_id_mask:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_id_mask_reg_t;
+
+/** Type of sel_ag0_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_rd_id_filter:7;
+        /** sel_ag0_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag0_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_id_filter_reg_t;
+
+/** Type of sel_ag1_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_rd_id_filter:7;
+        /** sel_ag1_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag1_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_id_filter_reg_t;
+
+/** Type of sel_ag2_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag2_rd_id_filter:7;
+        /** sel_ag2_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag2_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_id_filter_reg_t;
+
+/** Type of sel_ag3_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag3_rd_id_filter:7;
+        /** sel_ag3_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag3_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_id_filter_reg_t;
+
+/** Type of sel_ag4_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag4_rd_id_filter:7;
+        /** sel_ag4_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag4_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_id_filter_reg_t;
+
+/** Type of sel_ag5_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag5_rd_id_filter:7;
+        /** sel_ag5_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag5_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_id_filter_reg_t;
+
+/** Type of sel_ag6_id_filter register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_id_filter : R/W; bitpos: [6:0]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag6_rd_id_filter:7;
+        /** sel_ag6_wr_id_filter : R/W; bitpos: [13:7]; default: 0;
+         *  Use with mask, no mask bits must same as filter bits, the pass filter
+         */
+        uint32_t sel_ag6_wr_id_filter:7;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_id_filter_reg_t;
+
+/** Type of sel_ag_bandw_test_en register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_en : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_en:1;
+        /** sel_ag0_wr_bandw_test_en : R/W; bitpos: [1]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_en:1;
+        /** sel_ag1_rd_bandw_test_en : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_en:1;
+        /** sel_ag1_wr_bandw_test_en : R/W; bitpos: [3]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_en:1;
+        /** sel_ag2_rd_bandw_test_en : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag2_rd_bandw_test_en:1;
+        /** sel_ag2_wr_bandw_test_en : R/W; bitpos: [5]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag2_wr_bandw_test_en:1;
+        /** sel_ag3_rd_bandw_test_en : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag3_rd_bandw_test_en:1;
+        /** sel_ag3_wr_bandw_test_en : R/W; bitpos: [7]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag3_wr_bandw_test_en:1;
+        /** sel_ag4_rd_bandw_test_en : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag4_rd_bandw_test_en:1;
+        /** sel_ag4_wr_bandw_test_en : R/W; bitpos: [9]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag4_wr_bandw_test_en:1;
+        /** sel_ag5_rd_bandw_test_en : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag5_rd_bandw_test_en:1;
+        /** sel_ag5_wr_bandw_test_en : R/W; bitpos: [11]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag5_wr_bandw_test_en:1;
+        /** sel_ag6_rd_bandw_test_en : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag6_rd_bandw_test_en:1;
+        /** sel_ag6_wr_bandw_test_en : R/W; bitpos: [13]; default: 0;
+         *  Enable Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag6_wr_bandw_test_en:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_en_reg_t;
+
+/** Type of sel_ag_bandw_test_stop register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_test_stop : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag0_rd_bandw_test_stop:1;
+        /** sel_ag0_wr_bandw_test_stop : R/W; bitpos: [1]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag0_wr_bandw_test_stop:1;
+        /** sel_ag1_rd_bandw_test_stop : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag1_rd_bandw_test_stop:1;
+        /** sel_ag1_wr_bandw_test_stop : R/W; bitpos: [3]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag1_wr_bandw_test_stop:1;
+        /** sel_ag2_rd_bandw_test_stop : R/W; bitpos: [4]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag2_rd_bandw_test_stop:1;
+        /** sel_ag2_wr_bandw_test_stop : R/W; bitpos: [5]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag2_wr_bandw_test_stop:1;
+        /** sel_ag3_rd_bandw_test_stop : R/W; bitpos: [6]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag3_rd_bandw_test_stop:1;
+        /** sel_ag3_wr_bandw_test_stop : R/W; bitpos: [7]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag3_wr_bandw_test_stop:1;
+        /** sel_ag4_rd_bandw_test_stop : R/W; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag4_rd_bandw_test_stop:1;
+        /** sel_ag4_wr_bandw_test_stop : R/W; bitpos: [9]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag4_wr_bandw_test_stop:1;
+        /** sel_ag5_rd_bandw_test_stop : R/W; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag5_rd_bandw_test_stop:1;
+        /** sel_ag5_wr_bandw_test_stop : R/W; bitpos: [11]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag5_wr_bandw_test_stop:1;
+        /** sel_ag6_rd_bandw_test_stop : R/W; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t sel_ag6_rd_bandw_test_stop:1;
+        /** sel_ag6_wr_bandw_test_stop : R/W; bitpos: [13]; default: 0;
+         *  Stop Read average bandwidth test for all select agent in the same time
+         */
+        uint32_t sel_ag6_wr_bandw_test_stop:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_bandw_test_stop_reg_t;
+
+/** Type of sel_ag0_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_en_sel:4;
+        /** sel_ag0_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag0_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag0_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_en_sel:4;
+        /** sel_ag0_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag0_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag1_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_en_sel:4;
+        /** sel_ag1_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag1_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag1_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_en_sel:4;
+        /** sel_ag1_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag1_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag2_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag2_rd_bandw_trigger_en_sel:4;
+        /** sel_ag2_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag2_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag2_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag2_wr_bandw_trigger_en_sel:4;
+        /** sel_ag2_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag2_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag3_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag3_rd_bandw_trigger_en_sel:4;
+        /** sel_ag3_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag3_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag3_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag3_wr_bandw_trigger_en_sel:4;
+        /** sel_ag3_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag3_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag4_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag4_rd_bandw_trigger_en_sel:4;
+        /** sel_ag4_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag4_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag4_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag4_wr_bandw_trigger_en_sel:4;
+        /** sel_ag4_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag4_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag5_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag5_rd_bandw_trigger_en_sel:4;
+        /** sel_ag5_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag5_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag5_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag5_wr_bandw_trigger_en_sel:4;
+        /** sel_ag5_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag5_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag6_bandw_trigger_in_sel register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_bandw_trigger_en_sel : R/W; bitpos: [3:0]; default: 0;
+         *  Read average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag6_rd_bandw_trigger_en_sel:4;
+        /** sel_ag6_rd_bandw_trigger_stop_sel : R/W; bitpos: [7:4]; default: 0;
+         *  Read average bandwidth test, trigger by soc, sel source, SW register config is one
+         *  source
+         */
+        uint32_t sel_ag6_rd_bandw_trigger_stop_sel:4;
+        /** sel_ag6_wr_bandw_trigger_en_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag6_wr_bandw_trigger_en_sel:4;
+        /** sel_ag6_wr_bandw_trigger_stop_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Write average bandwidth test, trigger enable by soc, sel source, SW register config
+         *  is one source
+         */
+        uint32_t sel_ag6_wr_bandw_trigger_stop_sel:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_bandw_trigger_in_sel_reg_t;
+
+/** Type of sel_ag0_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_rd_ins_bandw_time_thr:16;
+        /** sel_ag0_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag0_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag1_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_rd_ins_bandw_time_thr:16;
+        /** sel_ag1_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag1_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag2_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag2_rd_ins_bandw_time_thr:16;
+        /** sel_ag2_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag2_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag3_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag3_rd_ins_bandw_time_thr:16;
+        /** sel_ag3_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag3_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag4_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag4_rd_ins_bandw_time_thr:16;
+        /** sel_ag4_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag4_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag5_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag5_rd_ins_bandw_time_thr:16;
+        /** sel_ag5_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag5_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_ins_bandw_time_thr_reg_t;
+
+/** Type of sel_ag6_ins_bandw_time_thr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_ins_bandw_time_thr : R/W; bitpos: [15:0]; default: 0;
+         *  Read instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag6_rd_ins_bandw_time_thr:16;
+        /** sel_ag6_wr_ins_bandw_time_thr : R/W; bitpos: [31:16]; default: 0;
+         *  Write instantaneous bandwidth test time limit, counter data num in this time unit,
+         *  and will fresh counter to count again
+         */
+        uint32_t sel_ag6_wr_ins_bandw_time_thr:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_ins_bandw_time_thr_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of agent_select register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** agent_select : R/W; bitpos: [31:0]; default: 0;
+         *  Select Agent in slot to be monitored, 4 bits means one agent number
+         */
+        uint32_t agent_select:32;
+    };
+    uint32_t val;
+} axi_perf_mon_agent_select_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of sel_ag0_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter0_reg_t;
+
+/** Type of sel_ag1_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter0_reg_t;
+
+/** Type of sel_ag2_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter0_reg_t;
+
+/** Type of sel_ag3_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter0_reg_t;
+
+/** Type of sel_ag4_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter0_reg_t;
+
+/** Type of sel_ag5_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter0_reg_t;
+
+/** Type of sel_ag6_counter0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter0_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter0_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter0_reg_t;
+
+/** Type of sel_ag0_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter1_reg_t;
+
+/** Type of sel_ag1_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter1_reg_t;
+
+/** Type of sel_ag2_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter1_reg_t;
+
+/** Type of sel_ag3_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter1_reg_t;
+
+/** Type of sel_ag4_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter1_reg_t;
+
+/** Type of sel_ag5_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter1_reg_t;
+
+/** Type of sel_ag6_counter1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter1_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter1_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter1_reg_t;
+
+/** Type of sel_ag0_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter2_reg_t;
+
+/** Type of sel_ag1_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter2_reg_t;
+
+/** Type of sel_ag2_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter2_reg_t;
+
+/** Type of sel_ag3_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter2_reg_t;
+
+/** Type of sel_ag4_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter2_reg_t;
+
+/** Type of sel_ag5_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter2_reg_t;
+
+/** Type of sel_ag6_counter2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter2_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter2_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter2_reg_t;
+
+/** Type of sel_ag0_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter3_reg_t;
+
+/** Type of sel_ag1_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter3_reg_t;
+
+/** Type of sel_ag2_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter3_reg_t;
+
+/** Type of sel_ag3_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter3_reg_t;
+
+/** Type of sel_ag4_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter3_reg_t;
+
+/** Type of sel_ag5_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter3_reg_t;
+
+/** Type of sel_ag6_counter3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter3_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter3_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter3_reg_t;
+
+/** Type of sel_ag0_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter4_reg_t;
+
+/** Type of sel_ag1_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter4_reg_t;
+
+/** Type of sel_ag2_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter4_reg_t;
+
+/** Type of sel_ag3_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter4_reg_t;
+
+/** Type of sel_ag4_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter4_reg_t;
+
+/** Type of sel_ag5_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter4_reg_t;
+
+/** Type of sel_ag6_counter4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter4_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter4_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter4_reg_t;
+
+/** Type of sel_ag0_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter5_reg_t;
+
+/** Type of sel_ag1_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter5_reg_t;
+
+/** Type of sel_ag2_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter5_reg_t;
+
+/** Type of sel_ag3_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter5_reg_t;
+
+/** Type of sel_ag4_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter5_reg_t;
+
+/** Type of sel_ag5_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter5_reg_t;
+
+/** Type of sel_ag6_counter5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter5_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter5_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter5_reg_t;
+
+/** Type of sel_ag0_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter6_reg_t;
+
+/** Type of sel_ag1_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter6_reg_t;
+
+/** Type of sel_ag2_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter6_reg_t;
+
+/** Type of sel_ag3_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter6_reg_t;
+
+/** Type of sel_ag4_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter6_reg_t;
+
+/** Type of sel_ag5_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter6_reg_t;
+
+/** Type of sel_ag6_counter6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter6_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter6_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter6_reg_t;
+
+/** Type of sel_ag0_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag0_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_counter7_reg_t;
+
+/** Type of sel_ag1_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag1_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_counter7_reg_t;
+
+/** Type of sel_ag2_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag2_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_counter7_reg_t;
+
+/** Type of sel_ag3_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag3_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_counter7_reg_t;
+
+/** Type of sel_ag4_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag4_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_counter7_reg_t;
+
+/** Type of sel_ag5_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag5_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_counter7_reg_t;
+
+/** Type of sel_ag6_counter7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_counter7_result : RO; bitpos: [31:0]; default: 0;
+         *  The result for sel agent metric measured in this counter, [15:0] is min result, and
+         *  [31:16] is max result
+         */
+        uint32_t sel_ag6_counter7_result:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_counter7_reg_t;
+
+/** Type of sel_ag0_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range0_reg_t;
+
+/** Type of sel_ag1_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range0_reg_t;
+
+/** Type of sel_ag2_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range0_reg_t;
+
+/** Type of sel_ag3_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range0_reg_t;
+
+/** Type of sel_ag4_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range0_reg_t;
+
+/** Type of sel_ag5_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range0_reg_t;
+
+/** Type of sel_ag6_range0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range0_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range0_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range0_reg_t;
+
+/** Type of sel_ag0_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range1_reg_t;
+
+/** Type of sel_ag1_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range1_reg_t;
+
+/** Type of sel_ag2_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range1_reg_t;
+
+/** Type of sel_ag3_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range1_reg_t;
+
+/** Type of sel_ag4_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range1_reg_t;
+
+/** Type of sel_ag5_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range1_reg_t;
+
+/** Type of sel_ag6_range1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range1_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range1_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range1_reg_t;
+
+/** Type of sel_ag0_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range2_reg_t;
+
+/** Type of sel_ag1_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range2_reg_t;
+
+/** Type of sel_ag2_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range2_reg_t;
+
+/** Type of sel_ag3_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range2_reg_t;
+
+/** Type of sel_ag4_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range2_reg_t;
+
+/** Type of sel_ag5_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range2_reg_t;
+
+/** Type of sel_ag6_range2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range2_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range2_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range2_reg_t;
+
+/** Type of sel_ag0_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range3_reg_t;
+
+/** Type of sel_ag1_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range3_reg_t;
+
+/** Type of sel_ag2_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range3_reg_t;
+
+/** Type of sel_ag3_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range3_reg_t;
+
+/** Type of sel_ag4_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range3_reg_t;
+
+/** Type of sel_ag5_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range3_reg_t;
+
+/** Type of sel_ag6_range3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range3_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range3_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range3_reg_t;
+
+/** Type of sel_ag0_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range4_reg_t;
+
+/** Type of sel_ag1_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range4_reg_t;
+
+/** Type of sel_ag2_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range4_reg_t;
+
+/** Type of sel_ag3_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range4_reg_t;
+
+/** Type of sel_ag4_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range4_reg_t;
+
+/** Type of sel_ag5_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range4_reg_t;
+
+/** Type of sel_ag6_range4 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range4_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range4_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range4_reg_t;
+
+/** Type of sel_ag0_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range5_reg_t;
+
+/** Type of sel_ag1_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range5_reg_t;
+
+/** Type of sel_ag2_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range5_reg_t;
+
+/** Type of sel_ag3_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range5_reg_t;
+
+/** Type of sel_ag4_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range5_reg_t;
+
+/** Type of sel_ag5_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range5_reg_t;
+
+/** Type of sel_ag6_range5 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range5_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range5_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range5_reg_t;
+
+/** Type of sel_ag0_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range6_reg_t;
+
+/** Type of sel_ag1_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range6_reg_t;
+
+/** Type of sel_ag2_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range6_reg_t;
+
+/** Type of sel_ag3_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range6_reg_t;
+
+/** Type of sel_ag4_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range6_reg_t;
+
+/** Type of sel_ag5_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range6_reg_t;
+
+/** Type of sel_ag6_range6 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range6_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range6_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range6_reg_t;
+
+/** Type of sel_ag0_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag0_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_range7_reg_t;
+
+/** Type of sel_ag1_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag1_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_range7_reg_t;
+
+/** Type of sel_ag2_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag2_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_range7_reg_t;
+
+/** Type of sel_ag3_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag3_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_range7_reg_t;
+
+/** Type of sel_ag4_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag4_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_range7_reg_t;
+
+/** Type of sel_ag5_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag5_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_range7_reg_t;
+
+/** Type of sel_ag6_range7 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_range7_result : RO; bitpos: [15:0]; default: 0;
+         *  The interval statistics results in this counter for sel agent
+         */
+        uint32_t sel_ag6_range7_result:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_range7_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag2_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag2_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag3_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag3_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag4_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag4_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag5_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag5_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag6_rd_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag6_rd_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag2_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag2_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag3_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag3_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag4_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag4_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag5_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag5_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag6_rd_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag6_rd_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag2_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag2_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag3_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag3_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag4_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag4_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag5_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag5_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag6_rd_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag6_rd_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag0_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag1_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag2_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag2_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag3_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag3_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag4_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag4_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag5_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag5_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag6_rd_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for ARLEN,
+         *  [23:8] for ARID
+         */
+        uint32_t sel_ag6_rd_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag2_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag2_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag3_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag3_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag4_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag4_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag5_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag5_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag6_wr_axi_info_record0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_axi_info_record0 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag6_wr_axi_info_record0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_axi_info_record0_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag2_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag2_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag3_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag3_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag4_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag4_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag5_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag5_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag6_wr_axi_info_record1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_axi_info_record1 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag6_wr_axi_info_record1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_axi_info_record1_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag2_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag2_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag3_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag3_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag4_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag4_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag5_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag5_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag6_wr_axi_info_record2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_axi_info_record2 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag6_wr_axi_info_record2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_axi_info_record2_reg_t;
+
+/** Type of sel_ag0_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag0_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag1_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag1_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag2_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag2_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag3_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag3_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag4_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag4_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag5_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag5_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag6_wr_axi_info_record3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_axi_info_record3 : RO; bitpos: [15:0]; default: 0;
+         *  The latest x axi transaction information record for sel agent, [7:0] for AWLEN,
+         *  [23:8] for AWID
+         */
+        uint32_t sel_ag6_wr_axi_info_record3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_axi_info_record3_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag2_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag2_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag3_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag3_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag4_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag4_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag5_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag5_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag6_ins_bandw_data0 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_ins_bandw_data0 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag6_ins_bandw_data0:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_ins_bandw_data0_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag2_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag2_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag3_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag3_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag4_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag4_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag5_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag5_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag6_ins_bandw_data1 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_ins_bandw_data1 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag6_ins_bandw_data1:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_ins_bandw_data1_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag2_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag2_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag3_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag3_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag4_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag4_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag5_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag5_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag6_ins_bandw_data2 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_ins_bandw_data2 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag6_ins_bandw_data2:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_ins_bandw_data2_reg_t;
+
+/** Type of sel_ag0_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag0_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag1_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag1_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag2_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag2_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag3_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag3_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag4_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag4_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag5_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag5_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag6_ins_bandw_data3 register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_ins_bandw_data3 : RO; bitpos: [31:0]; default: 0;
+         *  The latest x bandwidth date num in config time record for sel agent, [15:0] for
+         *  Read and [31:16] for write
+         */
+        uint32_t sel_ag6_ins_bandw_data3:32;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_ins_bandw_data3_reg_t;
+
+/** Type of sel_ag0_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag2_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag2_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag2_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag2_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag3_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag3_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag3_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag3_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag4_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag4_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag4_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag4_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag5_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag5_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag5_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag5_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag6_wr_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_wr_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag6_wr_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag6_wr_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag6_wr_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_wr_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag0_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag0_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag0_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag1_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag1_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag1_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag1_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag2_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag2_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag2_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag2_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag2_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag2_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag3_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag3_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag3_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag3_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag3_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag3_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag4_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag4_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag4_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag4_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag4_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag4_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag5_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag5_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag5_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag5_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag5_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag5_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+/** Type of sel_ag6_rd_bandw_cnt_valid_strobe_num register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag6_rd_bandw_time_cnt_valid_strobe_num : R/W; bitpos: [7:0]; default: 0;
+         *  Set this register to configure the time valid scaling multiplier
+         */
+        uint32_t sel_ag6_rd_bandw_time_cnt_valid_strobe_num:8;
+        /** sel_ag6_rd_bandw_data_cnt_valid_strobe_num : R/W; bitpos: [15:8]; default: 0;
+         *  Set this register to configure the data valid scaling multiplier
+         */
+        uint32_t sel_ag6_rd_bandw_data_cnt_valid_strobe_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag6_rd_bandw_cnt_valid_strobe_num_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of sel_ag_int_raw register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_raw:1;
+        /** sel_ag1_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_raw:1;
+        /** sel_ag2_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag2_record_cnt_under_limit_int_raw:1;
+        /** sel_ag3_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag3_record_cnt_under_limit_int_raw:1;
+        /** sel_ag4_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag4_record_cnt_under_limit_int_raw:1;
+        /** sel_ag5_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag5_record_cnt_under_limit_int_raw:1;
+        /** sel_ag6_record_cnt_under_limit_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag6_record_cnt_under_limit_int_raw:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_raw_reg_t;
+
+/** Type of sel_ag_int_st register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_st:1;
+        /** sel_ag1_record_cnt_under_limit_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_st:1;
+        /** sel_ag2_record_cnt_under_limit_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag2_record_cnt_under_limit_int_st:1;
+        /** sel_ag3_record_cnt_under_limit_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag3_record_cnt_under_limit_int_st:1;
+        /** sel_ag4_record_cnt_under_limit_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag4_record_cnt_under_limit_int_st:1;
+        /** sel_ag5_record_cnt_under_limit_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag5_record_cnt_under_limit_int_st:1;
+        /** sel_ag6_record_cnt_under_limit_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag6_record_cnt_under_limit_int_st:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_st_reg_t;
+
+/** Type of sel_ag_int_ena register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_ena:1;
+        /** sel_ag1_record_cnt_under_limit_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_ena:1;
+        /** sel_ag2_record_cnt_under_limit_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag2_record_cnt_under_limit_int_ena:1;
+        /** sel_ag3_record_cnt_under_limit_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag3_record_cnt_under_limit_int_ena:1;
+        /** sel_ag4_record_cnt_under_limit_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag4_record_cnt_under_limit_int_ena:1;
+        /** sel_ag5_record_cnt_under_limit_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag5_record_cnt_under_limit_int_ena:1;
+        /** sel_ag6_record_cnt_under_limit_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag6_record_cnt_under_limit_int_ena:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_ena_reg_t;
+
+/** Type of sel_ag_int_clr register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sel_ag0_record_cnt_under_limit_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag0_record_cnt_under_limit_int_clr:1;
+        /** sel_ag1_record_cnt_under_limit_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag1_record_cnt_under_limit_int_clr:1;
+        /** sel_ag2_record_cnt_under_limit_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag2_record_cnt_under_limit_int_clr:1;
+        /** sel_ag3_record_cnt_under_limit_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag3_record_cnt_under_limit_int_clr:1;
+        /** sel_ag4_record_cnt_under_limit_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag4_record_cnt_under_limit_int_clr:1;
+        /** sel_ag5_record_cnt_under_limit_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag5_record_cnt_under_limit_int_clr:1;
+        /** sel_ag6_record_cnt_under_limit_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear instantaneous bandwidth test data under limit int
+         */
+        uint32_t sel_ag6_record_cnt_under_limit_int_clr:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} axi_perf_mon_sel_ag_int_clr_reg_t;
+
+
+/** Group: Version Control Registers */
+/** Type of date register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 2506030;
+         *  reserved
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} axi_perf_mon_date_reg_t;
+
+
+typedef struct {
+    volatile axi_perf_mon_clk_en_reg_t clk_en;
+    volatile axi_perf_mon_agent_select_reg_t agent_select;
+    volatile axi_perf_mon_sel_ag0_counter0_reg_t sel_ag0_counter0;
+    volatile axi_perf_mon_sel_ag1_counter0_reg_t sel_ag1_counter0;
+    volatile axi_perf_mon_sel_ag2_counter0_reg_t sel_ag2_counter0;
+    volatile axi_perf_mon_sel_ag3_counter0_reg_t sel_ag3_counter0;
+    volatile axi_perf_mon_sel_ag4_counter0_reg_t sel_ag4_counter0;
+    volatile axi_perf_mon_sel_ag5_counter0_reg_t sel_ag5_counter0;
+    volatile axi_perf_mon_sel_ag6_counter0_reg_t sel_ag6_counter0;
+    volatile axi_perf_mon_sel_ag0_counter1_reg_t sel_ag0_counter1;
+    volatile axi_perf_mon_sel_ag1_counter1_reg_t sel_ag1_counter1;
+    volatile axi_perf_mon_sel_ag2_counter1_reg_t sel_ag2_counter1;
+    volatile axi_perf_mon_sel_ag3_counter1_reg_t sel_ag3_counter1;
+    volatile axi_perf_mon_sel_ag4_counter1_reg_t sel_ag4_counter1;
+    volatile axi_perf_mon_sel_ag5_counter1_reg_t sel_ag5_counter1;
+    volatile axi_perf_mon_sel_ag6_counter1_reg_t sel_ag6_counter1;
+    volatile axi_perf_mon_sel_ag0_counter2_reg_t sel_ag0_counter2;
+    volatile axi_perf_mon_sel_ag1_counter2_reg_t sel_ag1_counter2;
+    volatile axi_perf_mon_sel_ag2_counter2_reg_t sel_ag2_counter2;
+    volatile axi_perf_mon_sel_ag3_counter2_reg_t sel_ag3_counter2;
+    volatile axi_perf_mon_sel_ag4_counter2_reg_t sel_ag4_counter2;
+    volatile axi_perf_mon_sel_ag5_counter2_reg_t sel_ag5_counter2;
+    volatile axi_perf_mon_sel_ag6_counter2_reg_t sel_ag6_counter2;
+    volatile axi_perf_mon_sel_ag0_counter3_reg_t sel_ag0_counter3;
+    volatile axi_perf_mon_sel_ag1_counter3_reg_t sel_ag1_counter3;
+    volatile axi_perf_mon_sel_ag2_counter3_reg_t sel_ag2_counter3;
+    volatile axi_perf_mon_sel_ag3_counter3_reg_t sel_ag3_counter3;
+    volatile axi_perf_mon_sel_ag4_counter3_reg_t sel_ag4_counter3;
+    volatile axi_perf_mon_sel_ag5_counter3_reg_t sel_ag5_counter3;
+    volatile axi_perf_mon_sel_ag6_counter3_reg_t sel_ag6_counter3;
+    volatile axi_perf_mon_sel_ag0_counter4_reg_t sel_ag0_counter4;
+    volatile axi_perf_mon_sel_ag1_counter4_reg_t sel_ag1_counter4;
+    volatile axi_perf_mon_sel_ag2_counter4_reg_t sel_ag2_counter4;
+    volatile axi_perf_mon_sel_ag3_counter4_reg_t sel_ag3_counter4;
+    volatile axi_perf_mon_sel_ag4_counter4_reg_t sel_ag4_counter4;
+    volatile axi_perf_mon_sel_ag5_counter4_reg_t sel_ag5_counter4;
+    volatile axi_perf_mon_sel_ag6_counter4_reg_t sel_ag6_counter4;
+    volatile axi_perf_mon_sel_ag0_counter5_reg_t sel_ag0_counter5;
+    volatile axi_perf_mon_sel_ag1_counter5_reg_t sel_ag1_counter5;
+    volatile axi_perf_mon_sel_ag2_counter5_reg_t sel_ag2_counter5;
+    volatile axi_perf_mon_sel_ag3_counter5_reg_t sel_ag3_counter5;
+    volatile axi_perf_mon_sel_ag4_counter5_reg_t sel_ag4_counter5;
+    volatile axi_perf_mon_sel_ag5_counter5_reg_t sel_ag5_counter5;
+    volatile axi_perf_mon_sel_ag6_counter5_reg_t sel_ag6_counter5;
+    volatile axi_perf_mon_sel_ag0_counter6_reg_t sel_ag0_counter6;
+    volatile axi_perf_mon_sel_ag1_counter6_reg_t sel_ag1_counter6;
+    volatile axi_perf_mon_sel_ag2_counter6_reg_t sel_ag2_counter6;
+    volatile axi_perf_mon_sel_ag3_counter6_reg_t sel_ag3_counter6;
+    volatile axi_perf_mon_sel_ag4_counter6_reg_t sel_ag4_counter6;
+    volatile axi_perf_mon_sel_ag5_counter6_reg_t sel_ag5_counter6;
+    volatile axi_perf_mon_sel_ag6_counter6_reg_t sel_ag6_counter6;
+    volatile axi_perf_mon_sel_ag0_counter7_reg_t sel_ag0_counter7;
+    volatile axi_perf_mon_sel_ag1_counter7_reg_t sel_ag1_counter7;
+    volatile axi_perf_mon_sel_ag2_counter7_reg_t sel_ag2_counter7;
+    volatile axi_perf_mon_sel_ag3_counter7_reg_t sel_ag3_counter7;
+    volatile axi_perf_mon_sel_ag4_counter7_reg_t sel_ag4_counter7;
+    volatile axi_perf_mon_sel_ag5_counter7_reg_t sel_ag5_counter7;
+    volatile axi_perf_mon_sel_ag6_counter7_reg_t sel_ag6_counter7;
+    volatile axi_perf_mon_sel_ag0_range0_reg_t sel_ag0_range0;
+    volatile axi_perf_mon_sel_ag1_range0_reg_t sel_ag1_range0;
+    volatile axi_perf_mon_sel_ag2_range0_reg_t sel_ag2_range0;
+    volatile axi_perf_mon_sel_ag3_range0_reg_t sel_ag3_range0;
+    volatile axi_perf_mon_sel_ag4_range0_reg_t sel_ag4_range0;
+    volatile axi_perf_mon_sel_ag5_range0_reg_t sel_ag5_range0;
+    volatile axi_perf_mon_sel_ag6_range0_reg_t sel_ag6_range0;
+    volatile axi_perf_mon_sel_ag0_range1_reg_t sel_ag0_range1;
+    volatile axi_perf_mon_sel_ag1_range1_reg_t sel_ag1_range1;
+    volatile axi_perf_mon_sel_ag2_range1_reg_t sel_ag2_range1;
+    volatile axi_perf_mon_sel_ag3_range1_reg_t sel_ag3_range1;
+    volatile axi_perf_mon_sel_ag4_range1_reg_t sel_ag4_range1;
+    volatile axi_perf_mon_sel_ag5_range1_reg_t sel_ag5_range1;
+    volatile axi_perf_mon_sel_ag6_range1_reg_t sel_ag6_range1;
+    volatile axi_perf_mon_sel_ag0_range2_reg_t sel_ag0_range2;
+    volatile axi_perf_mon_sel_ag1_range2_reg_t sel_ag1_range2;
+    volatile axi_perf_mon_sel_ag2_range2_reg_t sel_ag2_range2;
+    volatile axi_perf_mon_sel_ag3_range2_reg_t sel_ag3_range2;
+    volatile axi_perf_mon_sel_ag4_range2_reg_t sel_ag4_range2;
+    volatile axi_perf_mon_sel_ag5_range2_reg_t sel_ag5_range2;
+    volatile axi_perf_mon_sel_ag6_range2_reg_t sel_ag6_range2;
+    volatile axi_perf_mon_sel_ag0_range3_reg_t sel_ag0_range3;
+    volatile axi_perf_mon_sel_ag1_range3_reg_t sel_ag1_range3;
+    volatile axi_perf_mon_sel_ag2_range3_reg_t sel_ag2_range3;
+    volatile axi_perf_mon_sel_ag3_range3_reg_t sel_ag3_range3;
+    volatile axi_perf_mon_sel_ag4_range3_reg_t sel_ag4_range3;
+    volatile axi_perf_mon_sel_ag5_range3_reg_t sel_ag5_range3;
+    volatile axi_perf_mon_sel_ag6_range3_reg_t sel_ag6_range3;
+    volatile axi_perf_mon_sel_ag0_range4_reg_t sel_ag0_range4;
+    volatile axi_perf_mon_sel_ag1_range4_reg_t sel_ag1_range4;
+    volatile axi_perf_mon_sel_ag2_range4_reg_t sel_ag2_range4;
+    volatile axi_perf_mon_sel_ag3_range4_reg_t sel_ag3_range4;
+    volatile axi_perf_mon_sel_ag4_range4_reg_t sel_ag4_range4;
+    volatile axi_perf_mon_sel_ag5_range4_reg_t sel_ag5_range4;
+    volatile axi_perf_mon_sel_ag6_range4_reg_t sel_ag6_range4;
+    volatile axi_perf_mon_sel_ag0_range5_reg_t sel_ag0_range5;
+    volatile axi_perf_mon_sel_ag1_range5_reg_t sel_ag1_range5;
+    volatile axi_perf_mon_sel_ag2_range5_reg_t sel_ag2_range5;
+    volatile axi_perf_mon_sel_ag3_range5_reg_t sel_ag3_range5;
+    volatile axi_perf_mon_sel_ag4_range5_reg_t sel_ag4_range5;
+    volatile axi_perf_mon_sel_ag5_range5_reg_t sel_ag5_range5;
+    volatile axi_perf_mon_sel_ag6_range5_reg_t sel_ag6_range5;
+    volatile axi_perf_mon_sel_ag0_range6_reg_t sel_ag0_range6;
+    volatile axi_perf_mon_sel_ag1_range6_reg_t sel_ag1_range6;
+    volatile axi_perf_mon_sel_ag2_range6_reg_t sel_ag2_range6;
+    volatile axi_perf_mon_sel_ag3_range6_reg_t sel_ag3_range6;
+    volatile axi_perf_mon_sel_ag4_range6_reg_t sel_ag4_range6;
+    volatile axi_perf_mon_sel_ag5_range6_reg_t sel_ag5_range6;
+    volatile axi_perf_mon_sel_ag6_range6_reg_t sel_ag6_range6;
+    volatile axi_perf_mon_sel_ag0_range7_reg_t sel_ag0_range7;
+    volatile axi_perf_mon_sel_ag1_range7_reg_t sel_ag1_range7;
+    volatile axi_perf_mon_sel_ag2_range7_reg_t sel_ag2_range7;
+    volatile axi_perf_mon_sel_ag3_range7_reg_t sel_ag3_range7;
+    volatile axi_perf_mon_sel_ag4_range7_reg_t sel_ag4_range7;
+    volatile axi_perf_mon_sel_ag5_range7_reg_t sel_ag5_range7;
+    volatile axi_perf_mon_sel_ag6_range7_reg_t sel_ag6_range7;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record0_reg_t sel_ag0_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record0_reg_t sel_ag1_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag2_rd_axi_info_record0_reg_t sel_ag2_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag3_rd_axi_info_record0_reg_t sel_ag3_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag4_rd_axi_info_record0_reg_t sel_ag4_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag5_rd_axi_info_record0_reg_t sel_ag5_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag6_rd_axi_info_record0_reg_t sel_ag6_rd_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record1_reg_t sel_ag0_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record1_reg_t sel_ag1_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag2_rd_axi_info_record1_reg_t sel_ag2_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag3_rd_axi_info_record1_reg_t sel_ag3_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag4_rd_axi_info_record1_reg_t sel_ag4_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag5_rd_axi_info_record1_reg_t sel_ag5_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag6_rd_axi_info_record1_reg_t sel_ag6_rd_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record2_reg_t sel_ag0_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record2_reg_t sel_ag1_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag2_rd_axi_info_record2_reg_t sel_ag2_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag3_rd_axi_info_record2_reg_t sel_ag3_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag4_rd_axi_info_record2_reg_t sel_ag4_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag5_rd_axi_info_record2_reg_t sel_ag5_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag6_rd_axi_info_record2_reg_t sel_ag6_rd_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_rd_axi_info_record3_reg_t sel_ag0_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_rd_axi_info_record3_reg_t sel_ag1_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag2_rd_axi_info_record3_reg_t sel_ag2_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag3_rd_axi_info_record3_reg_t sel_ag3_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag4_rd_axi_info_record3_reg_t sel_ag4_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag5_rd_axi_info_record3_reg_t sel_ag5_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag6_rd_axi_info_record3_reg_t sel_ag6_rd_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record0_reg_t sel_ag0_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record0_reg_t sel_ag1_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag2_wr_axi_info_record0_reg_t sel_ag2_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag3_wr_axi_info_record0_reg_t sel_ag3_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag4_wr_axi_info_record0_reg_t sel_ag4_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag5_wr_axi_info_record0_reg_t sel_ag5_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag6_wr_axi_info_record0_reg_t sel_ag6_wr_axi_info_record0;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record1_reg_t sel_ag0_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record1_reg_t sel_ag1_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag2_wr_axi_info_record1_reg_t sel_ag2_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag3_wr_axi_info_record1_reg_t sel_ag3_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag4_wr_axi_info_record1_reg_t sel_ag4_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag5_wr_axi_info_record1_reg_t sel_ag5_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag6_wr_axi_info_record1_reg_t sel_ag6_wr_axi_info_record1;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record2_reg_t sel_ag0_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record2_reg_t sel_ag1_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag2_wr_axi_info_record2_reg_t sel_ag2_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag3_wr_axi_info_record2_reg_t sel_ag3_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag4_wr_axi_info_record2_reg_t sel_ag4_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag5_wr_axi_info_record2_reg_t sel_ag5_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag6_wr_axi_info_record2_reg_t sel_ag6_wr_axi_info_record2;
+    volatile axi_perf_mon_sel_ag0_wr_axi_info_record3_reg_t sel_ag0_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag1_wr_axi_info_record3_reg_t sel_ag1_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag2_wr_axi_info_record3_reg_t sel_ag2_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag3_wr_axi_info_record3_reg_t sel_ag3_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag4_wr_axi_info_record3_reg_t sel_ag4_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag5_wr_axi_info_record3_reg_t sel_ag5_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag6_wr_axi_info_record3_reg_t sel_ag6_wr_axi_info_record3;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data0_reg_t sel_ag0_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data0_reg_t sel_ag1_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag2_ins_bandw_data0_reg_t sel_ag2_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag3_ins_bandw_data0_reg_t sel_ag3_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag4_ins_bandw_data0_reg_t sel_ag4_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag5_ins_bandw_data0_reg_t sel_ag5_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag6_ins_bandw_data0_reg_t sel_ag6_ins_bandw_data0;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data1_reg_t sel_ag0_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data1_reg_t sel_ag1_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag2_ins_bandw_data1_reg_t sel_ag2_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag3_ins_bandw_data1_reg_t sel_ag3_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag4_ins_bandw_data1_reg_t sel_ag4_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag5_ins_bandw_data1_reg_t sel_ag5_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag6_ins_bandw_data1_reg_t sel_ag6_ins_bandw_data1;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data2_reg_t sel_ag0_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data2_reg_t sel_ag1_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag2_ins_bandw_data2_reg_t sel_ag2_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag3_ins_bandw_data2_reg_t sel_ag3_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag4_ins_bandw_data2_reg_t sel_ag4_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag5_ins_bandw_data2_reg_t sel_ag5_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag6_ins_bandw_data2_reg_t sel_ag6_ins_bandw_data2;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_data3_reg_t sel_ag0_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_data3_reg_t sel_ag1_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag2_ins_bandw_data3_reg_t sel_ag2_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag3_ins_bandw_data3_reg_t sel_ag3_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag4_ins_bandw_data3_reg_t sel_ag4_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag5_ins_bandw_data3_reg_t sel_ag5_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag6_ins_bandw_data3_reg_t sel_ag6_ins_bandw_data3;
+    volatile axi_perf_mon_sel_ag0_metric_range0_reg_t sel_ag0_metric_range0;
+    volatile axi_perf_mon_sel_ag1_metric_range0_reg_t sel_ag1_metric_range0;
+    volatile axi_perf_mon_sel_ag2_metric_range0_reg_t sel_ag2_metric_range0;
+    volatile axi_perf_mon_sel_ag3_metric_range0_reg_t sel_ag3_metric_range0;
+    volatile axi_perf_mon_sel_ag4_metric_range0_reg_t sel_ag4_metric_range0;
+    volatile axi_perf_mon_sel_ag5_metric_range0_reg_t sel_ag5_metric_range0;
+    volatile axi_perf_mon_sel_ag6_metric_range0_reg_t sel_ag6_metric_range0;
+    volatile axi_perf_mon_sel_ag0_metric_range1_reg_t sel_ag0_metric_range1;
+    volatile axi_perf_mon_sel_ag1_metric_range1_reg_t sel_ag1_metric_range1;
+    volatile axi_perf_mon_sel_ag2_metric_range1_reg_t sel_ag2_metric_range1;
+    volatile axi_perf_mon_sel_ag3_metric_range1_reg_t sel_ag3_metric_range1;
+    volatile axi_perf_mon_sel_ag4_metric_range1_reg_t sel_ag4_metric_range1;
+    volatile axi_perf_mon_sel_ag5_metric_range1_reg_t sel_ag5_metric_range1;
+    volatile axi_perf_mon_sel_ag6_metric_range1_reg_t sel_ag6_metric_range1;
+    volatile axi_perf_mon_sel_ag0_metric_range2_reg_t sel_ag0_metric_range2;
+    volatile axi_perf_mon_sel_ag1_metric_range2_reg_t sel_ag1_metric_range2;
+    volatile axi_perf_mon_sel_ag2_metric_range2_reg_t sel_ag2_metric_range2;
+    volatile axi_perf_mon_sel_ag3_metric_range2_reg_t sel_ag3_metric_range2;
+    volatile axi_perf_mon_sel_ag4_metric_range2_reg_t sel_ag4_metric_range2;
+    volatile axi_perf_mon_sel_ag5_metric_range2_reg_t sel_ag5_metric_range2;
+    volatile axi_perf_mon_sel_ag6_metric_range2_reg_t sel_ag6_metric_range2;
+    volatile axi_perf_mon_sel_ag0_metric_range3_reg_t sel_ag0_metric_range3;
+    volatile axi_perf_mon_sel_ag1_metric_range3_reg_t sel_ag1_metric_range3;
+    volatile axi_perf_mon_sel_ag2_metric_range3_reg_t sel_ag2_metric_range3;
+    volatile axi_perf_mon_sel_ag3_metric_range3_reg_t sel_ag3_metric_range3;
+    volatile axi_perf_mon_sel_ag4_metric_range3_reg_t sel_ag4_metric_range3;
+    volatile axi_perf_mon_sel_ag5_metric_range3_reg_t sel_ag5_metric_range3;
+    volatile axi_perf_mon_sel_ag6_metric_range3_reg_t sel_ag6_metric_range3;
+    volatile axi_perf_mon_sel_ag0_metric_range4_reg_t sel_ag0_metric_range4;
+    volatile axi_perf_mon_sel_ag1_metric_range4_reg_t sel_ag1_metric_range4;
+    volatile axi_perf_mon_sel_ag2_metric_range4_reg_t sel_ag2_metric_range4;
+    volatile axi_perf_mon_sel_ag3_metric_range4_reg_t sel_ag3_metric_range4;
+    volatile axi_perf_mon_sel_ag4_metric_range4_reg_t sel_ag4_metric_range4;
+    volatile axi_perf_mon_sel_ag5_metric_range4_reg_t sel_ag5_metric_range4;
+    volatile axi_perf_mon_sel_ag6_metric_range4_reg_t sel_ag6_metric_range4;
+    volatile axi_perf_mon_sel_ag0_metric_range5_reg_t sel_ag0_metric_range5;
+    volatile axi_perf_mon_sel_ag1_metric_range5_reg_t sel_ag1_metric_range5;
+    volatile axi_perf_mon_sel_ag2_metric_range5_reg_t sel_ag2_metric_range5;
+    volatile axi_perf_mon_sel_ag3_metric_range5_reg_t sel_ag3_metric_range5;
+    volatile axi_perf_mon_sel_ag4_metric_range5_reg_t sel_ag4_metric_range5;
+    volatile axi_perf_mon_sel_ag5_metric_range5_reg_t sel_ag5_metric_range5;
+    volatile axi_perf_mon_sel_ag6_metric_range5_reg_t sel_ag6_metric_range5;
+    volatile axi_perf_mon_sel_ag0_metric_range6_reg_t sel_ag0_metric_range6;
+    volatile axi_perf_mon_sel_ag1_metric_range6_reg_t sel_ag1_metric_range6;
+    volatile axi_perf_mon_sel_ag2_metric_range6_reg_t sel_ag2_metric_range6;
+    volatile axi_perf_mon_sel_ag3_metric_range6_reg_t sel_ag3_metric_range6;
+    volatile axi_perf_mon_sel_ag4_metric_range6_reg_t sel_ag4_metric_range6;
+    volatile axi_perf_mon_sel_ag5_metric_range6_reg_t sel_ag5_metric_range6;
+    volatile axi_perf_mon_sel_ag6_metric_range6_reg_t sel_ag6_metric_range6;
+    volatile axi_perf_mon_sel_ag0_metric_range7_reg_t sel_ag0_metric_range7;
+    volatile axi_perf_mon_sel_ag1_metric_range7_reg_t sel_ag1_metric_range7;
+    volatile axi_perf_mon_sel_ag2_metric_range7_reg_t sel_ag2_metric_range7;
+    volatile axi_perf_mon_sel_ag3_metric_range7_reg_t sel_ag3_metric_range7;
+    volatile axi_perf_mon_sel_ag4_metric_range7_reg_t sel_ag4_metric_range7;
+    volatile axi_perf_mon_sel_ag5_metric_range7_reg_t sel_ag5_metric_range7;
+    volatile axi_perf_mon_sel_ag6_metric_range7_reg_t sel_ag6_metric_range7;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask0_reg_t sel_ag0_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask0_reg_t sel_ag1_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag2_rd_addr_mask0_reg_t sel_ag2_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag3_rd_addr_mask0_reg_t sel_ag3_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag4_rd_addr_mask0_reg_t sel_ag4_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag5_rd_addr_mask0_reg_t sel_ag5_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag6_rd_addr_mask0_reg_t sel_ag6_rd_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask1_reg_t sel_ag0_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask1_reg_t sel_ag1_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag2_rd_addr_mask1_reg_t sel_ag2_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag3_rd_addr_mask1_reg_t sel_ag3_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag4_rd_addr_mask1_reg_t sel_ag4_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag5_rd_addr_mask1_reg_t sel_ag5_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag6_rd_addr_mask1_reg_t sel_ag6_rd_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_mask2_reg_t sel_ag0_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_mask2_reg_t sel_ag1_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag2_rd_addr_mask2_reg_t sel_ag2_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag3_rd_addr_mask2_reg_t sel_ag3_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag4_rd_addr_mask2_reg_t sel_ag4_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag5_rd_addr_mask2_reg_t sel_ag5_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag6_rd_addr_mask2_reg_t sel_ag6_rd_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask0_reg_t sel_ag0_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask0_reg_t sel_ag1_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag2_wr_addr_mask0_reg_t sel_ag2_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag3_wr_addr_mask0_reg_t sel_ag3_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag4_wr_addr_mask0_reg_t sel_ag4_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag5_wr_addr_mask0_reg_t sel_ag5_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag6_wr_addr_mask0_reg_t sel_ag6_wr_addr_mask0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask1_reg_t sel_ag0_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask1_reg_t sel_ag1_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag2_wr_addr_mask1_reg_t sel_ag2_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag3_wr_addr_mask1_reg_t sel_ag3_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag4_wr_addr_mask1_reg_t sel_ag4_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag5_wr_addr_mask1_reg_t sel_ag5_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag6_wr_addr_mask1_reg_t sel_ag6_wr_addr_mask1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_mask2_reg_t sel_ag0_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_mask2_reg_t sel_ag1_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag2_wr_addr_mask2_reg_t sel_ag2_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag3_wr_addr_mask2_reg_t sel_ag3_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag4_wr_addr_mask2_reg_t sel_ag4_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag5_wr_addr_mask2_reg_t sel_ag5_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag6_wr_addr_mask2_reg_t sel_ag6_wr_addr_mask2;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter0_reg_t sel_ag0_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter0_reg_t sel_ag1_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag2_rd_addr_filter0_reg_t sel_ag2_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag3_rd_addr_filter0_reg_t sel_ag3_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag4_rd_addr_filter0_reg_t sel_ag4_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag5_rd_addr_filter0_reg_t sel_ag5_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag6_rd_addr_filter0_reg_t sel_ag6_rd_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter1_reg_t sel_ag0_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter1_reg_t sel_ag1_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag2_rd_addr_filter1_reg_t sel_ag2_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag3_rd_addr_filter1_reg_t sel_ag3_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag4_rd_addr_filter1_reg_t sel_ag4_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag5_rd_addr_filter1_reg_t sel_ag5_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag6_rd_addr_filter1_reg_t sel_ag6_rd_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_rd_addr_filter2_reg_t sel_ag0_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_rd_addr_filter2_reg_t sel_ag1_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag2_rd_addr_filter2_reg_t sel_ag2_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag3_rd_addr_filter2_reg_t sel_ag3_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag4_rd_addr_filter2_reg_t sel_ag4_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag5_rd_addr_filter2_reg_t sel_ag5_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag6_rd_addr_filter2_reg_t sel_ag6_rd_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter0_reg_t sel_ag0_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter0_reg_t sel_ag1_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag2_wr_addr_filter0_reg_t sel_ag2_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag3_wr_addr_filter0_reg_t sel_ag3_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag4_wr_addr_filter0_reg_t sel_ag4_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag5_wr_addr_filter0_reg_t sel_ag5_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag6_wr_addr_filter0_reg_t sel_ag6_wr_addr_filter0;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter1_reg_t sel_ag0_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter1_reg_t sel_ag1_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag2_wr_addr_filter1_reg_t sel_ag2_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag3_wr_addr_filter1_reg_t sel_ag3_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag4_wr_addr_filter1_reg_t sel_ag4_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag5_wr_addr_filter1_reg_t sel_ag5_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag6_wr_addr_filter1_reg_t sel_ag6_wr_addr_filter1;
+    volatile axi_perf_mon_sel_ag0_wr_addr_filter2_reg_t sel_ag0_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag1_wr_addr_filter2_reg_t sel_ag1_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag2_wr_addr_filter2_reg_t sel_ag2_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag3_wr_addr_filter2_reg_t sel_ag3_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag4_wr_addr_filter2_reg_t sel_ag4_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag5_wr_addr_filter2_reg_t sel_ag5_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag6_wr_addr_filter2_reg_t sel_ag6_wr_addr_filter2;
+    volatile axi_perf_mon_sel_ag0_metric_select1_reg_t sel_ag0_metric_select1;
+    volatile axi_perf_mon_sel_ag1_metric_select1_reg_t sel_ag1_metric_select1;
+    volatile axi_perf_mon_sel_ag2_metric_select1_reg_t sel_ag2_metric_select1;
+    volatile axi_perf_mon_sel_ag3_metric_select1_reg_t sel_ag3_metric_select1;
+    volatile axi_perf_mon_sel_ag4_metric_select1_reg_t sel_ag4_metric_select1;
+    volatile axi_perf_mon_sel_ag5_metric_select1_reg_t sel_ag5_metric_select1;
+    volatile axi_perf_mon_sel_ag6_metric_select1_reg_t sel_ag6_metric_select1;
+    volatile axi_perf_mon_sel_ag0_metric_select2_reg_t sel_ag0_metric_select2;
+    volatile axi_perf_mon_sel_ag1_metric_select2_reg_t sel_ag1_metric_select2;
+    volatile axi_perf_mon_sel_ag2_metric_select2_reg_t sel_ag2_metric_select2;
+    volatile axi_perf_mon_sel_ag3_metric_select2_reg_t sel_ag3_metric_select2;
+    volatile axi_perf_mon_sel_ag4_metric_select2_reg_t sel_ag4_metric_select2;
+    volatile axi_perf_mon_sel_ag5_metric_select2_reg_t sel_ag5_metric_select2;
+    volatile axi_perf_mon_sel_ag6_metric_select2_reg_t sel_ag6_metric_select2;
+    volatile axi_perf_mon_sel_ag_rd_addr_region_sel_reg_t sel_ag_rd_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_wr_addr_region_sel_reg_t sel_ag_wr_addr_region_sel;
+    volatile axi_perf_mon_sel_ag_addr_filter_en_reg_t sel_ag_addr_filter_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_en_reg_t sel_ag_sw_record_stop_en;
+    volatile axi_perf_mon_sel_ag_sw_record_stop_clr_reg_t sel_ag_sw_record_stop_clr;
+    volatile axi_perf_mon_sel_ag_ins_bandw_test_en_reg_t sel_ag_ins_bandw_test_en;
+    volatile axi_perf_mon_sel_ag0_sw_record_stop_data_limit_reg_t sel_ag0_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag1_sw_record_stop_data_limit_reg_t sel_ag1_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag2_sw_record_stop_data_limit_reg_t sel_ag2_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag3_sw_record_stop_data_limit_reg_t sel_ag3_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag4_sw_record_stop_data_limit_reg_t sel_ag4_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag5_sw_record_stop_data_limit_reg_t sel_ag5_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag6_sw_record_stop_data_limit_reg_t sel_ag6_sw_record_stop_data_limit;
+    volatile axi_perf_mon_sel_ag0_id_mask_reg_t sel_ag0_id_mask;
+    volatile axi_perf_mon_sel_ag1_id_mask_reg_t sel_ag1_id_mask;
+    volatile axi_perf_mon_sel_ag2_id_mask_reg_t sel_ag2_id_mask;
+    volatile axi_perf_mon_sel_ag3_id_mask_reg_t sel_ag3_id_mask;
+    volatile axi_perf_mon_sel_ag4_id_mask_reg_t sel_ag4_id_mask;
+    volatile axi_perf_mon_sel_ag5_id_mask_reg_t sel_ag5_id_mask;
+    volatile axi_perf_mon_sel_ag6_id_mask_reg_t sel_ag6_id_mask;
+    volatile axi_perf_mon_sel_ag0_id_filter_reg_t sel_ag0_id_filter;
+    volatile axi_perf_mon_sel_ag1_id_filter_reg_t sel_ag1_id_filter;
+    volatile axi_perf_mon_sel_ag2_id_filter_reg_t sel_ag2_id_filter;
+    volatile axi_perf_mon_sel_ag3_id_filter_reg_t sel_ag3_id_filter;
+    volatile axi_perf_mon_sel_ag4_id_filter_reg_t sel_ag4_id_filter;
+    volatile axi_perf_mon_sel_ag5_id_filter_reg_t sel_ag5_id_filter;
+    volatile axi_perf_mon_sel_ag6_id_filter_reg_t sel_ag6_id_filter;
+    volatile axi_perf_mon_sel_ag_bandw_test_en_reg_t sel_ag_bandw_test_en;
+    volatile axi_perf_mon_sel_ag_bandw_test_stop_reg_t sel_ag_bandw_test_stop;
+    volatile axi_perf_mon_sel_ag0_bandw_trigger_in_sel_reg_t sel_ag0_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag1_bandw_trigger_in_sel_reg_t sel_ag1_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag2_bandw_trigger_in_sel_reg_t sel_ag2_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag3_bandw_trigger_in_sel_reg_t sel_ag3_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag4_bandw_trigger_in_sel_reg_t sel_ag4_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag5_bandw_trigger_in_sel_reg_t sel_ag5_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag6_bandw_trigger_in_sel_reg_t sel_ag6_bandw_trigger_in_sel;
+    volatile axi_perf_mon_sel_ag0_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag0_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag1_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag2_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag2_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag3_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag3_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag4_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag4_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag5_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag5_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag6_wr_bandw_cnt_valid_strobe_num_reg_t sel_ag6_wr_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag0_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag1_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag1_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag2_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag2_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag3_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag3_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag4_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag4_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag5_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag5_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag6_rd_bandw_cnt_valid_strobe_num_reg_t sel_ag6_rd_bandw_cnt_valid_strobe_num;
+    volatile axi_perf_mon_sel_ag0_ins_bandw_time_thr_reg_t sel_ag0_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag1_ins_bandw_time_thr_reg_t sel_ag1_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag2_ins_bandw_time_thr_reg_t sel_ag2_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag3_ins_bandw_time_thr_reg_t sel_ag3_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag4_ins_bandw_time_thr_reg_t sel_ag4_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag5_ins_bandw_time_thr_reg_t sel_ag5_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag6_ins_bandw_time_thr_reg_t sel_ag6_ins_bandw_time_thr;
+    volatile axi_perf_mon_sel_ag_int_raw_reg_t sel_ag_int_raw;
+    volatile axi_perf_mon_sel_ag_int_st_reg_t sel_ag_int_st;
+    volatile axi_perf_mon_sel_ag_int_ena_reg_t sel_ag_int_ena;
+    volatile axi_perf_mon_sel_ag_int_clr_reg_t sel_ag_int_clr;
+    volatile axi_perf_mon_date_reg_t date;
+} axi_perf_mon_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_perf_mon_dev_t) == 0x678, "Invalid size of axi_perf_mon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/bitscrambler_reg.h b/components/soc/esp32s31/register/soc/bitscrambler_reg.h
new file mode 100644
index 00000000000..abcc78c69cd
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/bitscrambler_reg.h
@@ -0,0 +1,572 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** BITSCRAMBLER_TX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x0)
+/** BITSCRAMBLER_TX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_TX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_M  (BITSCRAMBLER_TX_INST_IDX_V << BITSCRAMBLER_TX_INST_IDX_S)
+#define BITSCRAMBLER_TX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_TX_INST_IDX_S  0
+/** BITSCRAMBLER_TX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_TX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_M  (BITSCRAMBLER_TX_INST_POS_V << BITSCRAMBLER_TX_INST_POS_S)
+#define BITSCRAMBLER_TX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_TX_INST_POS_S  3
+
+/** BITSCRAMBLER_TX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x4)
+/** BITSCRAMBLER_TX_INST : R/W; bitpos: [31:0]; default: 4;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_TX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_M  (BITSCRAMBLER_TX_INST_V << BITSCRAMBLER_TX_INST_S)
+#define BITSCRAMBLER_TX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_INST_S  0
+
+/** BITSCRAMBLER_RX_INST_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x8)
+/** BITSCRAMBLER_RX_INST_IDX : R/W; bitpos: [2:0]; default: 0;
+ *  write this bits to specify the one of 8 instruction
+ */
+#define BITSCRAMBLER_RX_INST_IDX    0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_M  (BITSCRAMBLER_RX_INST_IDX_V << BITSCRAMBLER_RX_INST_IDX_S)
+#define BITSCRAMBLER_RX_INST_IDX_V  0x00000007U
+#define BITSCRAMBLER_RX_INST_IDX_S  0
+/** BITSCRAMBLER_RX_INST_POS : R/W; bitpos: [6:3]; default: 0;
+ *  write this bits to specify the bit position of 257 bit instruction which in units
+ *  of 32 bits
+ */
+#define BITSCRAMBLER_RX_INST_POS    0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_M  (BITSCRAMBLER_RX_INST_POS_V << BITSCRAMBLER_RX_INST_POS_S)
+#define BITSCRAMBLER_RX_INST_POS_V  0x0000000FU
+#define BITSCRAMBLER_RX_INST_POS_S  3
+
+/** BITSCRAMBLER_RX_INST_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_INST_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0xc)
+/** BITSCRAMBLER_RX_INST : R/W; bitpos: [31:0]; default: 12;
+ *  write this bits to update instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+ *  BITSCRAMBLER_RX_INST_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_INST    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_M  (BITSCRAMBLER_RX_INST_V << BITSCRAMBLER_RX_INST_S)
+#define BITSCRAMBLER_RX_INST_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_INST_S  0
+
+/** BITSCRAMBLER_TX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x10)
+/** BITSCRAMBLER_TX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_tx_lut_mode
+ */
+#define BITSCRAMBLER_TX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_M  (BITSCRAMBLER_TX_LUT_IDX_V << BITSCRAMBLER_TX_LUT_IDX_S)
+#define BITSCRAMBLER_TX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_TX_LUT_IDX_S  0
+/** BITSCRAMBLER_TX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_TX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_M  (BITSCRAMBLER_TX_LUT_MODE_V << BITSCRAMBLER_TX_LUT_MODE_S)
+#define BITSCRAMBLER_TX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_TX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_TX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x14)
+/** BITSCRAMBLER_TX_LUT : R/W; bitpos: [31:0]; default: 20;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_TX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_M  (BITSCRAMBLER_TX_LUT_V << BITSCRAMBLER_TX_LUT_S)
+#define BITSCRAMBLER_TX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_TX_LUT_S  0
+
+/** BITSCRAMBLER_RX_LUT_CFG0_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG0_REG (DR_REG_BITSCRAMBLER_BASE + 0x18)
+/** BITSCRAMBLER_RX_LUT_IDX : R/W; bitpos: [10:0]; default: 0;
+ *  write this bits to specify the bytes position of LUT RAM based on
+ *  reg_bitscrambler_rx_lut_mode
+ */
+#define BITSCRAMBLER_RX_LUT_IDX    0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_M  (BITSCRAMBLER_RX_LUT_IDX_V << BITSCRAMBLER_RX_LUT_IDX_S)
+#define BITSCRAMBLER_RX_LUT_IDX_V  0x000007FFU
+#define BITSCRAMBLER_RX_LUT_IDX_S  0
+/** BITSCRAMBLER_RX_LUT_MODE : R/W; bitpos: [12:11]; default: 0;
+ *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+ *  bytes
+ */
+#define BITSCRAMBLER_RX_LUT_MODE    0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_M  (BITSCRAMBLER_RX_LUT_MODE_V << BITSCRAMBLER_RX_LUT_MODE_S)
+#define BITSCRAMBLER_RX_LUT_MODE_V  0x00000003U
+#define BITSCRAMBLER_RX_LUT_MODE_S  11
+
+/** BITSCRAMBLER_RX_LUT_CFG1_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_LUT_CFG1_REG (DR_REG_BITSCRAMBLER_BASE + 0x1c)
+/** BITSCRAMBLER_RX_LUT : R/W; bitpos: [31:0]; default: 28;
+ *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+ *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+ */
+#define BITSCRAMBLER_RX_LUT    0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_M  (BITSCRAMBLER_RX_LUT_V << BITSCRAMBLER_RX_LUT_S)
+#define BITSCRAMBLER_RX_LUT_V  0xFFFFFFFFU
+#define BITSCRAMBLER_RX_LUT_S  0
+
+/** BITSCRAMBLER_TX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x20)
+/** BITSCRAMBLER_TX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_TX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_M  (BITSCRAMBLER_TX_TAILING_BITS_V << BITSCRAMBLER_TX_TAILING_BITS_S)
+#define BITSCRAMBLER_TX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_RX_TAILING_BITS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS_REG (DR_REG_BITSCRAMBLER_BASE + 0x24)
+/** BITSCRAMBLER_RX_TAILING_BITS : R/W; bitpos: [15:0]; default: 0;
+ *  write this bits to specify the extra data bit length after getting EOF
+ */
+#define BITSCRAMBLER_RX_TAILING_BITS    0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_M  (BITSCRAMBLER_RX_TAILING_BITS_V << BITSCRAMBLER_RX_TAILING_BITS_S)
+#define BITSCRAMBLER_RX_TAILING_BITS_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_TAILING_BITS_S  0
+
+/** BITSCRAMBLER_TX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_TX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x28)
+/** BITSCRAMBLER_TX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler tx
+ */
+#define BITSCRAMBLER_TX_ENA    (BIT(0))
+#define BITSCRAMBLER_TX_ENA_M  (BITSCRAMBLER_TX_ENA_V << BITSCRAMBLER_TX_ENA_S)
+#define BITSCRAMBLER_TX_ENA_V  0x00000001U
+#define BITSCRAMBLER_TX_ENA_S  0
+/** BITSCRAMBLER_TX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_TX_PAUSE_M  (BITSCRAMBLER_TX_PAUSE_V << BITSCRAMBLER_TX_PAUSE_S)
+#define BITSCRAMBLER_TX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_PAUSE_S  1
+/** BITSCRAMBLER_TX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_HALT    (BIT(2))
+#define BITSCRAMBLER_TX_HALT_M  (BITSCRAMBLER_TX_HALT_V << BITSCRAMBLER_TX_HALT_S)
+#define BITSCRAMBLER_TX_HALT_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_S  2
+/** BITSCRAMBLER_TX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+ *  counter by write peripheral buffer
+ */
+#define BITSCRAMBLER_TX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_TX_EOF_MODE_M  (BITSCRAMBLER_TX_EOF_MODE_V << BITSCRAMBLER_TX_EOF_MODE_S)
+#define BITSCRAMBLER_TX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_MODE_S  3
+/** BITSCRAMBLER_TX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_TX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_TX_COND_MODE_M  (BITSCRAMBLER_TX_COND_MODE_V << BITSCRAMBLER_TX_COND_MODE_S)
+#define BITSCRAMBLER_TX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_COND_MODE_S  4
+/** BITSCRAMBLER_TX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_TX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_TX_FETCH_MODE_M  (BITSCRAMBLER_TX_FETCH_MODE_V << BITSCRAMBLER_TX_FETCH_MODE_S)
+#define BITSCRAMBLER_TX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_FETCH_MODE_S  5
+/** BITSCRAMBLER_TX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_TX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_TX_HALT_MODE_M  (BITSCRAMBLER_TX_HALT_MODE_V << BITSCRAMBLER_TX_HALT_MODE_S)
+#define BITSCRAMBLER_TX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_TX_HALT_MODE_S  6
+/** BITSCRAMBLER_TX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_TX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_TX_RD_DUMMY_M  (BITSCRAMBLER_TX_RD_DUMMY_V << BITSCRAMBLER_TX_RD_DUMMY_S)
+#define BITSCRAMBLER_TX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_TX_RD_DUMMY_S  7
+/** BITSCRAMBLER_TX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler tx fifo
+ */
+#define BITSCRAMBLER_TX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_TX_FIFO_RST_M  (BITSCRAMBLER_TX_FIFO_RST_V << BITSCRAMBLER_TX_FIFO_RST_S)
+#define BITSCRAMBLER_TX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_RX_CTRL_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_RX_CTRL_REG (DR_REG_BITSCRAMBLER_BASE + 0x2c)
+/** BITSCRAMBLER_RX_ENA : R/W; bitpos: [0]; default: 0;
+ *  write this bit to enable the bitscrambler rx
+ */
+#define BITSCRAMBLER_RX_ENA    (BIT(0))
+#define BITSCRAMBLER_RX_ENA_M  (BITSCRAMBLER_RX_ENA_V << BITSCRAMBLER_RX_ENA_S)
+#define BITSCRAMBLER_RX_ENA_V  0x00000001U
+#define BITSCRAMBLER_RX_ENA_S  0
+/** BITSCRAMBLER_RX_PAUSE : R/W; bitpos: [1]; default: 0;
+ *  write this bit to pause the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_PAUSE    (BIT(1))
+#define BITSCRAMBLER_RX_PAUSE_M  (BITSCRAMBLER_RX_PAUSE_V << BITSCRAMBLER_RX_PAUSE_S)
+#define BITSCRAMBLER_RX_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_PAUSE_S  1
+/** BITSCRAMBLER_RX_HALT : R/W; bitpos: [2]; default: 1;
+ *  write this bit to halt the bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_HALT    (BIT(2))
+#define BITSCRAMBLER_RX_HALT_M  (BITSCRAMBLER_RX_HALT_V << BITSCRAMBLER_RX_HALT_S)
+#define BITSCRAMBLER_RX_HALT_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_S  2
+/** BITSCRAMBLER_RX_EOF_MODE : R/W; bitpos: [3]; default: 0;
+ *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+ *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+ *  buffer, 0 counter by write dma fifo
+ */
+#define BITSCRAMBLER_RX_EOF_MODE    (BIT(3))
+#define BITSCRAMBLER_RX_EOF_MODE_M  (BITSCRAMBLER_RX_EOF_MODE_V << BITSCRAMBLER_RX_EOF_MODE_S)
+#define BITSCRAMBLER_RX_EOF_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_MODE_S  3
+/** BITSCRAMBLER_RX_COND_MODE : R/W; bitpos: [4]; default: 0;
+ *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+ *  core, 0: use the little than operator to get the condition, 1: use not equal
+ *  operator to get the condition
+ */
+#define BITSCRAMBLER_RX_COND_MODE    (BIT(4))
+#define BITSCRAMBLER_RX_COND_MODE_M  (BITSCRAMBLER_RX_COND_MODE_V << BITSCRAMBLER_RX_COND_MODE_S)
+#define BITSCRAMBLER_RX_COND_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_COND_MODE_S  4
+/** BITSCRAMBLER_RX_FETCH_MODE : R/W; bitpos: [5]; default: 0;
+ *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+ *  by reset, 1: fetch by instructions
+ */
+#define BITSCRAMBLER_RX_FETCH_MODE    (BIT(5))
+#define BITSCRAMBLER_RX_FETCH_MODE_M  (BITSCRAMBLER_RX_FETCH_MODE_V << BITSCRAMBLER_RX_FETCH_MODE_S)
+#define BITSCRAMBLER_RX_FETCH_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_FETCH_MODE_S  5
+/** BITSCRAMBLER_RX_HALT_MODE : R/W; bitpos: [6]; default: 0;
+ *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+ *  wait write data back done, , 1: ignore write data back
+ */
+#define BITSCRAMBLER_RX_HALT_MODE    (BIT(6))
+#define BITSCRAMBLER_RX_HALT_MODE_M  (BITSCRAMBLER_RX_HALT_MODE_V << BITSCRAMBLER_RX_HALT_MODE_S)
+#define BITSCRAMBLER_RX_HALT_MODE_V  0x00000001U
+#define BITSCRAMBLER_RX_HALT_MODE_S  6
+/** BITSCRAMBLER_RX_RD_DUMMY : R/W; bitpos: [7]; default: 0;
+ *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+ *  wait read data, 1: ignore read data
+ */
+#define BITSCRAMBLER_RX_RD_DUMMY    (BIT(7))
+#define BITSCRAMBLER_RX_RD_DUMMY_M  (BITSCRAMBLER_RX_RD_DUMMY_V << BITSCRAMBLER_RX_RD_DUMMY_S)
+#define BITSCRAMBLER_RX_RD_DUMMY_V  0x00000001U
+#define BITSCRAMBLER_RX_RD_DUMMY_S  7
+/** BITSCRAMBLER_RX_FIFO_RST : WT; bitpos: [8]; default: 0;
+ *  write this bit to reset the bitscrambler rx fifo
+ */
+#define BITSCRAMBLER_RX_FIFO_RST    (BIT(8))
+#define BITSCRAMBLER_RX_FIFO_RST_M  (BITSCRAMBLER_RX_FIFO_RST_V << BITSCRAMBLER_RX_FIFO_RST_S)
+#define BITSCRAMBLER_RX_FIFO_RST_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_RST_S  8
+
+/** BITSCRAMBLER_TX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_TX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x30)
+/** BITSCRAMBLER_TX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler tx core in halt mode
+ */
+#define BITSCRAMBLER_TX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_TX_IN_IDLE_M  (BITSCRAMBLER_TX_IN_IDLE_V << BITSCRAMBLER_TX_IN_IDLE_S)
+#define BITSCRAMBLER_TX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_IDLE_S  0
+/** BITSCRAMBLER_TX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler tx core in run mode
+ */
+#define BITSCRAMBLER_TX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_TX_IN_RUN_M  (BITSCRAMBLER_TX_IN_RUN_V << BITSCRAMBLER_TX_IN_RUN_S)
+#define BITSCRAMBLER_TX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_RUN_S  1
+/** BITSCRAMBLER_TX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler tx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_TX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_TX_IN_WAIT_M  (BITSCRAMBLER_TX_IN_WAIT_V << BITSCRAMBLER_TX_IN_WAIT_S)
+#define BITSCRAMBLER_TX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_WAIT_S  2
+/** BITSCRAMBLER_TX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler tx core in pause mode
+ */
+#define BITSCRAMBLER_TX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_TX_IN_PAUSE_M  (BITSCRAMBLER_TX_IN_PAUSE_V << BITSCRAMBLER_TX_IN_PAUSE_S)
+#define BITSCRAMBLER_TX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_TX_IN_PAUSE_S  3
+/** BITSCRAMBLER_TX_FIFO_EMPTY : RO; bitpos: [4]; default: 1;
+ *  represents the bitscrambler tx fifo in empty state
+ */
+#define BITSCRAMBLER_TX_FIFO_EMPTY    (BIT(4))
+#define BITSCRAMBLER_TX_FIFO_EMPTY_M  (BITSCRAMBLER_TX_FIFO_EMPTY_V << BITSCRAMBLER_TX_FIFO_EMPTY_S)
+#define BITSCRAMBLER_TX_FIFO_EMPTY_V  0x00000001U
+#define BITSCRAMBLER_TX_FIFO_EMPTY_S  4
+/** BITSCRAMBLER_TX_CRC_RDY : RO; bitpos: [5]; default: 0;
+ *  represents the crc calculate result of bitscrambler tx path is ready
+ */
+#define BITSCRAMBLER_TX_CRC_RDY    (BIT(5))
+#define BITSCRAMBLER_TX_CRC_RDY_M  (BITSCRAMBLER_TX_CRC_RDY_V << BITSCRAMBLER_TX_CRC_RDY_S)
+#define BITSCRAMBLER_TX_CRC_RDY_V  0x00000001U
+#define BITSCRAMBLER_TX_CRC_RDY_S  5
+/** BITSCRAMBLER_TX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler tx core when get EOF
+ */
+#define BITSCRAMBLER_TX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_M  (BITSCRAMBLER_TX_EOF_GET_CNT_V << BITSCRAMBLER_TX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_TX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_TX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_TX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler tx core
+ */
+#define BITSCRAMBLER_TX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_M  (BITSCRAMBLER_TX_EOF_OVERLOAD_V << BITSCRAMBLER_TX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_TX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+ *  reg_bitscrambler_tx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_M  (BITSCRAMBLER_TX_EOF_TRACE_CLR_V << BITSCRAMBLER_TX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_TX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_RX_STATE_REG register
+ *  Status registers
+ */
+#define BITSCRAMBLER_RX_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x34)
+/** BITSCRAMBLER_RX_IN_IDLE : RO; bitpos: [0]; default: 1;
+ *  represents the bitscrambler rx core in halt mode
+ */
+#define BITSCRAMBLER_RX_IN_IDLE    (BIT(0))
+#define BITSCRAMBLER_RX_IN_IDLE_M  (BITSCRAMBLER_RX_IN_IDLE_V << BITSCRAMBLER_RX_IN_IDLE_S)
+#define BITSCRAMBLER_RX_IN_IDLE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_IDLE_S  0
+/** BITSCRAMBLER_RX_IN_RUN : RO; bitpos: [1]; default: 0;
+ *  represents the bitscrambler rx core in run mode
+ */
+#define BITSCRAMBLER_RX_IN_RUN    (BIT(1))
+#define BITSCRAMBLER_RX_IN_RUN_M  (BITSCRAMBLER_RX_IN_RUN_V << BITSCRAMBLER_RX_IN_RUN_S)
+#define BITSCRAMBLER_RX_IN_RUN_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_RUN_S  1
+/** BITSCRAMBLER_RX_IN_WAIT : RO; bitpos: [2]; default: 0;
+ *  represents the bitscrambler rx core in wait mode to wait write back done
+ */
+#define BITSCRAMBLER_RX_IN_WAIT    (BIT(2))
+#define BITSCRAMBLER_RX_IN_WAIT_M  (BITSCRAMBLER_RX_IN_WAIT_V << BITSCRAMBLER_RX_IN_WAIT_S)
+#define BITSCRAMBLER_RX_IN_WAIT_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_WAIT_S  2
+/** BITSCRAMBLER_RX_IN_PAUSE : RO; bitpos: [3]; default: 0;
+ *  represents the bitscrambler rx core in pause mode
+ */
+#define BITSCRAMBLER_RX_IN_PAUSE    (BIT(3))
+#define BITSCRAMBLER_RX_IN_PAUSE_M  (BITSCRAMBLER_RX_IN_PAUSE_V << BITSCRAMBLER_RX_IN_PAUSE_S)
+#define BITSCRAMBLER_RX_IN_PAUSE_V  0x00000001U
+#define BITSCRAMBLER_RX_IN_PAUSE_S  3
+/** BITSCRAMBLER_RX_FIFO_FULL : RO; bitpos: [4]; default: 0;
+ *  represents the bitscrambler rx fifo in full state
+ */
+#define BITSCRAMBLER_RX_FIFO_FULL    (BIT(4))
+#define BITSCRAMBLER_RX_FIFO_FULL_M  (BITSCRAMBLER_RX_FIFO_FULL_V << BITSCRAMBLER_RX_FIFO_FULL_S)
+#define BITSCRAMBLER_RX_FIFO_FULL_V  0x00000001U
+#define BITSCRAMBLER_RX_FIFO_FULL_S  4
+/** BITSCRAMBLER_RX_CRC_RDY : RO; bitpos: [5]; default: 0;
+ *  represents the crc calculate result of bitscrambler rx path is ready
+ */
+#define BITSCRAMBLER_RX_CRC_RDY    (BIT(5))
+#define BITSCRAMBLER_RX_CRC_RDY_M  (BITSCRAMBLER_RX_CRC_RDY_V << BITSCRAMBLER_RX_CRC_RDY_S)
+#define BITSCRAMBLER_RX_CRC_RDY_V  0x00000001U
+#define BITSCRAMBLER_RX_CRC_RDY_S  5
+/** BITSCRAMBLER_RX_EOF_GET_CNT : RO; bitpos: [29:16]; default: 0;
+ *  represents the bytes numbers of bitscrambler rx core when get EOF
+ */
+#define BITSCRAMBLER_RX_EOF_GET_CNT    0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_M  (BITSCRAMBLER_RX_EOF_GET_CNT_V << BITSCRAMBLER_RX_EOF_GET_CNT_S)
+#define BITSCRAMBLER_RX_EOF_GET_CNT_V  0x00003FFFU
+#define BITSCRAMBLER_RX_EOF_GET_CNT_S  16
+/** BITSCRAMBLER_RX_EOF_OVERLOAD : RO; bitpos: [30]; default: 0;
+ *  represents the some EOFs will be lost for bitscrambler rx core
+ */
+#define BITSCRAMBLER_RX_EOF_OVERLOAD    (BIT(30))
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_M  (BITSCRAMBLER_RX_EOF_OVERLOAD_V << BITSCRAMBLER_RX_EOF_OVERLOAD_S)
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_OVERLOAD_S  30
+/** BITSCRAMBLER_RX_EOF_TRACE_CLR : WT; bitpos: [31]; default: 0;
+ *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+ *  reg_bitscrambler_rx_eof_get_cnt registers
+ */
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR    (BIT(31))
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_M  (BITSCRAMBLER_RX_EOF_TRACE_CLR_V << BITSCRAMBLER_RX_EOF_TRACE_CLR_S)
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_V  0x00000001U
+#define BITSCRAMBLER_RX_EOF_TRACE_CLR_S  31
+
+/** BITSCRAMBLER_TX_CNT_CFG_REG register
+ *  TX Counter cfg registers
+ */
+#define BITSCRAMBLER_TX_CNT_CFG_REG (DR_REG_BITSCRAMBLER_BASE + 0x38)
+/** BITSCRAMBLER_RX_CNT_A_CFG_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  config the tx counter a value
+ */
+#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_M  (BITSCRAMBLER_RX_CNT_A_CFG_VALUE_V << BITSCRAMBLER_RX_CNT_A_CFG_VALUE_S)
+#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_A_CFG_VALUE_S  0
+/** BITSCRAMBLER_RX_CNT_B_CFG_VALUE : R/W; bitpos: [31:16]; default: 0;
+ *  config the tx counter b value
+ */
+#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_M  (BITSCRAMBLER_RX_CNT_B_CFG_VALUE_V << BITSCRAMBLER_RX_CNT_B_CFG_VALUE_S)
+#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_B_CFG_VALUE_S  16
+
+/** BITSCRAMBLER_RX_CNT_CFG_REG register
+ *  RX Counter cfg registers
+ */
+#define BITSCRAMBLER_RX_CNT_CFG_REG (DR_REG_BITSCRAMBLER_BASE + 0x3c)
+/** BITSCRAMBLER_TX_CNT_A_CFG_VALUE : R/W; bitpos: [15:0]; default: 0;
+ *  config the rx counter a value
+ */
+#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_M  (BITSCRAMBLER_TX_CNT_A_CFG_VALUE_V << BITSCRAMBLER_TX_CNT_A_CFG_VALUE_S)
+#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_A_CFG_VALUE_S  0
+/** BITSCRAMBLER_TX_CNT_B_CFG_VALUE : R/W; bitpos: [31:16]; default: 0;
+ *  config the rx counter b value
+ */
+#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_M  (BITSCRAMBLER_TX_CNT_B_CFG_VALUE_V << BITSCRAMBLER_TX_CNT_B_CFG_VALUE_S)
+#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_B_CFG_VALUE_S  16
+
+/** BITSCRAMBLER_TX_CNT_STATE_REG register
+ *  TX Counter state registers
+ */
+#define BITSCRAMBLER_TX_CNT_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x40)
+/** BITSCRAMBLER_RX_CNT_A_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  read the tx counter a value
+ */
+#define BITSCRAMBLER_RX_CNT_A_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_A_VALUE_M  (BITSCRAMBLER_RX_CNT_A_VALUE_V << BITSCRAMBLER_RX_CNT_A_VALUE_S)
+#define BITSCRAMBLER_RX_CNT_A_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_A_VALUE_S  0
+/** BITSCRAMBLER_RX_CNT_B_VALUE : RO; bitpos: [31:16]; default: 0;
+ *  read the tx counter b value
+ */
+#define BITSCRAMBLER_RX_CNT_B_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_B_VALUE_M  (BITSCRAMBLER_RX_CNT_B_VALUE_V << BITSCRAMBLER_RX_CNT_B_VALUE_S)
+#define BITSCRAMBLER_RX_CNT_B_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_RX_CNT_B_VALUE_S  16
+
+/** BITSCRAMBLER_RX_CNT_STATE_REG register
+ *  RX Counter state registers
+ */
+#define BITSCRAMBLER_RX_CNT_STATE_REG (DR_REG_BITSCRAMBLER_BASE + 0x44)
+/** BITSCRAMBLER_TX_CNT_A_VALUE : RO; bitpos: [15:0]; default: 0;
+ *  read the rx counter a value
+ */
+#define BITSCRAMBLER_TX_CNT_A_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_A_VALUE_M  (BITSCRAMBLER_TX_CNT_A_VALUE_V << BITSCRAMBLER_TX_CNT_A_VALUE_S)
+#define BITSCRAMBLER_TX_CNT_A_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_A_VALUE_S  0
+/** BITSCRAMBLER_TX_CNT_B_VALUE : RO; bitpos: [31:16]; default: 0;
+ *  read the rx counter b value
+ */
+#define BITSCRAMBLER_TX_CNT_B_VALUE    0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_B_VALUE_M  (BITSCRAMBLER_TX_CNT_B_VALUE_V << BITSCRAMBLER_TX_CNT_B_VALUE_S)
+#define BITSCRAMBLER_TX_CNT_B_VALUE_V  0x0000FFFFU
+#define BITSCRAMBLER_TX_CNT_B_VALUE_S  16
+
+/** BITSCRAMBLER_SYS_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_SYS_REG (DR_REG_BITSCRAMBLER_BASE + 0xf8)
+/** BITSCRAMBLER_LOOP_MODE : R/W; bitpos: [0]; default: 0;
+ *  write this bit to set the bitscrambler tx loop back to DMA rx
+ */
+#define BITSCRAMBLER_LOOP_MODE    (BIT(0))
+#define BITSCRAMBLER_LOOP_MODE_M  (BITSCRAMBLER_LOOP_MODE_V << BITSCRAMBLER_LOOP_MODE_S)
+#define BITSCRAMBLER_LOOP_MODE_V  0x00000001U
+#define BITSCRAMBLER_LOOP_MODE_S  0
+/** BITSCRAMBLER_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Write this bit to enable the configuration register clock to be always-on. 0: turn
+ *  on during access, 1: always-on.
+ */
+#define BITSCRAMBLER_CLK_EN    (BIT(31))
+#define BITSCRAMBLER_CLK_EN_M  (BITSCRAMBLER_CLK_EN_V << BITSCRAMBLER_CLK_EN_S)
+#define BITSCRAMBLER_CLK_EN_V  0x00000001U
+#define BITSCRAMBLER_CLK_EN_S  31
+
+/** BITSCRAMBLER_VERSION_REG register
+ *  Control and configuration registers
+ */
+#define BITSCRAMBLER_VERSION_REG (DR_REG_BITSCRAMBLER_BASE + 0xfc)
+/** BITSCRAMBLER_BITSCRAMBLER_VER : R/W; bitpos: [27:0]; default: 38801776;
+ *  Reserved
+ */
+#define BITSCRAMBLER_BITSCRAMBLER_VER    0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_M  (BITSCRAMBLER_BITSCRAMBLER_VER_V << BITSCRAMBLER_BITSCRAMBLER_VER_S)
+#define BITSCRAMBLER_BITSCRAMBLER_VER_V  0x0FFFFFFFU
+#define BITSCRAMBLER_BITSCRAMBLER_VER_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/bitscrambler_struct.h b/components/soc/esp32s31/register/soc/bitscrambler_struct.h
new file mode 100644
index 00000000000..9e169456007
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/bitscrambler_struct.h
@@ -0,0 +1,525 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of tx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t tx_inst_idx:3;
+        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t tx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg0_reg_t;
+
+/** Type of tx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_TX_INST_CFG0_REG
+         */
+        uint32_t tx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_inst_cfg1_reg_t;
+
+/** Type of rx_inst_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
+         *  write this bits to specify the one of 8 instruction
+         */
+        uint32_t rx_inst_idx:3;
+        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
+         *  write this bits to specify the bit position of 257 bit instruction which in units
+         *  of 32 bits
+         */
+        uint32_t rx_inst_pos:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg0_reg_t;
+
+/** Type of rx_inst_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
+         *  write this bits to update instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
+         *  BITSCRAMBLER_RX_INST_CFG0_REG
+         */
+        uint32_t rx_inst:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_inst_cfg1_reg_t;
+
+/** Type of tx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_tx_lut_mode
+         */
+        uint32_t tx_lut_idx:11;
+        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t tx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg0_reg_t;
+
+/** Type of tx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
+         */
+        uint32_t tx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_tx_lut_cfg1_reg_t;
+
+/** Type of rx_lut_cfg0 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
+         *  write this bits to specify the bytes position of LUT RAM based on
+         *  reg_bitscrambler_rx_lut_mode
+         */
+        uint32_t rx_lut_idx:11;
+        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
+         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
+         *  bytes
+         */
+        uint32_t rx_lut_mode:2;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg0_reg_t;
+
+/** Type of rx_lut_cfg1 register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
+         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
+         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
+         */
+        uint32_t rx_lut:32;
+    };
+    uint32_t val;
+} bitscrambler_rx_lut_cfg1_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of tx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t tx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_tailing_bits_reg_t;
+
+/** Type of rx_tailing_bits register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
+         *  write this bits to specify the extra data bit length after getting EOF
+         */
+        uint32_t rx_tailing_bits:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_tailing_bits_reg_t;
+
+/** Type of tx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** tx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler tx
+         */
+        uint32_t tx_ena:1;
+        /** tx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler tx core
+         */
+        uint32_t tx_pause:1;
+        /** tx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler tx core
+         */
+        uint32_t tx_halt:1;
+        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
+         *  counter by write peripheral buffer
+         */
+        uint32_t tx_eof_mode:1;
+        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t tx_cond_mode:1;
+        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t tx_fetch_mode:1;
+        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t tx_halt_mode:1;
+        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t tx_rd_dummy:1;
+        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler tx fifo
+         */
+        uint32_t tx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_tx_ctrl_reg_t;
+
+/** Type of rx_ctrl register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** rx_ena : R/W; bitpos: [0]; default: 0;
+         *  write this bit to enable the bitscrambler rx
+         */
+        uint32_t rx_ena:1;
+        /** rx_pause : R/W; bitpos: [1]; default: 0;
+         *  write this bit to pause the bitscrambler rx core
+         */
+        uint32_t rx_pause:1;
+        /** rx_halt : R/W; bitpos: [2]; default: 1;
+         *  write this bit to halt the bitscrambler rx core
+         */
+        uint32_t rx_halt:1;
+        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
+         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
+         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
+         *  buffer, 0 counter by write dma fifo
+         */
+        uint32_t rx_eof_mode:1;
+        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
+         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
+         *  core, 0: use the little than operator to get the condition, 1: use not equal
+         *  operator to get the condition
+         */
+        uint32_t rx_cond_mode:1;
+        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
+         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
+         *  by reset, 1: fetch by instructions
+         */
+        uint32_t rx_fetch_mode:1;
+        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
+         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
+         *  wait write data back done, , 1: ignore write data back
+         */
+        uint32_t rx_halt_mode:1;
+        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
+         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
+         *  wait read data, 1: ignore read data
+         */
+        uint32_t rx_rd_dummy:1;
+        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
+         *  write this bit to reset the bitscrambler rx fifo
+         */
+        uint32_t rx_fifo_rst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} bitscrambler_rx_ctrl_reg_t;
+
+/** Type of sys register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** loop_mode : R/W; bitpos: [0]; default: 0;
+         *  write this bit to set the bitscrambler tx loop back to DMA rx
+         */
+        uint32_t loop_mode:1;
+        uint32_t reserved_1:30;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Write this bit to enable the configuration register clock to be always-on. 0: turn
+         *  on during access, 1: always-on.
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} bitscrambler_sys_reg_t;
+
+
+/** Group: Status registers */
+/** Type of tx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** tx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler tx core in halt mode
+         */
+        uint32_t tx_in_idle:1;
+        /** tx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler tx core in run mode
+         */
+        uint32_t tx_in_run:1;
+        /** tx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler tx core in wait mode to wait write back done
+         */
+        uint32_t tx_in_wait:1;
+        /** tx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler tx core in pause mode
+         */
+        uint32_t tx_in_pause:1;
+        /** tx_fifo_empty : RO; bitpos: [4]; default: 1;
+         *  represents the bitscrambler tx fifo in empty state
+         */
+        uint32_t tx_fifo_empty:1;
+        /** tx_crc_rdy : RO; bitpos: [5]; default: 0;
+         *  represents the crc calculate result of bitscrambler tx path is ready
+         */
+        uint32_t tx_crc_rdy:1;
+        uint32_t reserved_6:10;
+        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler tx core when get EOF
+         */
+        uint32_t tx_eof_get_cnt:14;
+        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler tx core
+         */
+        uint32_t tx_eof_overload:1;
+        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
+         *  reg_bitscrambler_tx_eof_get_cnt registers
+         */
+        uint32_t tx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_tx_state_reg_t;
+
+/** Type of rx_state register
+ *  Status registers
+ */
+typedef union {
+    struct {
+        /** rx_in_idle : RO; bitpos: [0]; default: 1;
+         *  represents the bitscrambler rx core in halt mode
+         */
+        uint32_t rx_in_idle:1;
+        /** rx_in_run : RO; bitpos: [1]; default: 0;
+         *  represents the bitscrambler rx core in run mode
+         */
+        uint32_t rx_in_run:1;
+        /** rx_in_wait : RO; bitpos: [2]; default: 0;
+         *  represents the bitscrambler rx core in wait mode to wait write back done
+         */
+        uint32_t rx_in_wait:1;
+        /** rx_in_pause : RO; bitpos: [3]; default: 0;
+         *  represents the bitscrambler rx core in pause mode
+         */
+        uint32_t rx_in_pause:1;
+        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
+         *  represents the bitscrambler rx fifo in full state
+         */
+        uint32_t rx_fifo_full:1;
+        /** rx_crc_rdy : RO; bitpos: [5]; default: 0;
+         *  represents the crc calculate result of bitscrambler rx path is ready
+         */
+        uint32_t rx_crc_rdy:1;
+        uint32_t reserved_6:10;
+        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
+         *  represents the bytes numbers of bitscrambler rx core when get EOF
+         */
+        uint32_t rx_eof_get_cnt:14;
+        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
+         *  represents the some EOFs will be lost for bitscrambler rx core
+         */
+        uint32_t rx_eof_overload:1;
+        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
+         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
+         *  reg_bitscrambler_rx_eof_get_cnt registers
+         */
+        uint32_t rx_eof_trace_clr:1;
+    };
+    uint32_t val;
+} bitscrambler_rx_state_reg_t;
+
+
+/** Group: RX Counter cfg registers */
+/** Type of tx_cnt_cfg register
+ *  TX Counter cfg registers
+ */
+typedef union {
+    struct {
+        /** rx_cnt_a_cfg_value : R/W; bitpos: [15:0]; default: 0;
+         *  config the tx counter a value
+         */
+        uint32_t rx_cnt_a_cfg_value:16;
+        /** rx_cnt_b_cfg_value : R/W; bitpos: [31:16]; default: 0;
+         *  config the tx counter b value
+         */
+        uint32_t rx_cnt_b_cfg_value:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_cnt_cfg_reg_t;
+
+
+/** Group: TX_Counter cfg registers */
+/** Type of rx_cnt_cfg register
+ *  RX Counter cfg registers
+ */
+typedef union {
+    struct {
+        /** tx_cnt_a_cfg_value : R/W; bitpos: [15:0]; default: 0;
+         *  config the rx counter a value
+         */
+        uint32_t tx_cnt_a_cfg_value:16;
+        /** tx_cnt_b_cfg_value : R/W; bitpos: [31:16]; default: 0;
+         *  config the rx counter b value
+         */
+        uint32_t tx_cnt_b_cfg_value:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_cnt_cfg_reg_t;
+
+
+/** Group: RX Counter status registers */
+/** Type of tx_cnt_state register
+ *  TX Counter state registers
+ */
+typedef union {
+    struct {
+        /** rx_cnt_a_value : RO; bitpos: [15:0]; default: 0;
+         *  read the tx counter a value
+         */
+        uint32_t rx_cnt_a_value:16;
+        /** rx_cnt_b_value : RO; bitpos: [31:16]; default: 0;
+         *  read the tx counter b value
+         */
+        uint32_t rx_cnt_b_value:16;
+    };
+    uint32_t val;
+} bitscrambler_tx_cnt_state_reg_t;
+
+
+/** Group: TX_Counter status registers */
+/** Type of rx_cnt_state register
+ *  RX Counter state registers
+ */
+typedef union {
+    struct {
+        /** tx_cnt_a_value : RO; bitpos: [15:0]; default: 0;
+         *  read the rx counter a value
+         */
+        uint32_t tx_cnt_a_value:16;
+        /** tx_cnt_b_value : RO; bitpos: [31:16]; default: 0;
+         *  read the rx counter b value
+         */
+        uint32_t tx_cnt_b_value:16;
+    };
+    uint32_t val;
+} bitscrambler_rx_cnt_state_reg_t;
+
+
+/** Group: Version register */
+/** Type of version register
+ *  Control and configuration registers
+ */
+typedef union {
+    struct {
+        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 38801776;
+         *  Reserved
+         */
+        uint32_t bitscrambler_ver:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bitscrambler_version_reg_t;
+
+
+typedef struct {
+    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
+    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
+    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
+    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
+    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
+    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
+    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
+    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
+    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
+    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
+    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
+    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
+    volatile bitscrambler_tx_state_reg_t tx_state;
+    volatile bitscrambler_rx_state_reg_t rx_state;
+    volatile bitscrambler_tx_cnt_cfg_reg_t tx_cnt_cfg;
+    volatile bitscrambler_rx_cnt_cfg_reg_t rx_cnt_cfg;
+    volatile bitscrambler_tx_cnt_state_reg_t tx_cnt_state;
+    volatile bitscrambler_rx_cnt_state_reg_t rx_cnt_state;
+    uint32_t reserved_048[44];
+    volatile bitscrambler_sys_reg_t sys;
+    volatile bitscrambler_version_reg_t version;
+} bitscrambler_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/bus_monitor_reg.h b/components/soc/esp32s31/register/soc/bus_monitor_reg.h
new file mode 100644
index 00000000000..2d6c30d0cbf
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/bus_monitor_reg.h
@@ -0,0 +1,1389 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** BUS_MONITOR_CORE_0_MONTR_ENA_REG register
+ *  core0 monitor enable configuration register
+ */
+#define BUS_MONITOR_CORE_0_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x0)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Data bus.
+ *  0: Not monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Data bus.
+ *  0: Not monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Data bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Data bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+ *  region.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_M  (BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+ *  region.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_M  (BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_ENA_S  9
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA : R/W; bitpos: [12]; default: 0;
+ *  trace lockup monitor enable
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA    (BIT(12))
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_ENA_S  12
+
+/** BUS_MONITOR_CORE_0_INTR_RAW_REG register
+ *  core0 monitor interrupt status register
+ */
+#define BUS_MONITOR_CORE_0_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x4)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+ *  region.
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_M  (BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+ *  region.
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_M  (BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_RAW_S  9
+
+/** BUS_MONITOR_CORE_0_INTR_ENA_REG register
+ *  core0 monitor interrupt enable register
+ */
+#define BUS_MONITOR_CORE_0_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x8)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core0 dram0 area0 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA    (BIT(0))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S  0
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core0 dram0 area0 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA    (BIT(1))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S  1
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core0 dram0 area1 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA    (BIT(2))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S  2
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core0 dram0 area1 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA    (BIT(3))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S  3
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core0 PIF area0 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA    (BIT(4))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_INTR_ENA_S  4
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core0 PIF area0 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA    (BIT(5))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_INTR_ENA_S  5
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core0 PIF area1 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA    (BIT(6))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_INTR_ENA_S  6
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core0 PIF area1 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA    (BIT(7))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_INTR_ENA_S  7
+/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core0 stackpoint underflow monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA    (BIT(8))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_M  (BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_INTR_ENA_S  8
+/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core0 stackpoint overflow monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA    (BIT(9))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_M  (BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_INTR_ENA_S  9
+
+/** BUS_MONITOR_CORE_0_INTR_CLR_REG register
+ *  core0 monitor interrupt clear register
+ */
+#define BUS_MONITOR_CORE_0_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0xc)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V << BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+ *  monitored region.
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_M  (BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+ *  monitored region.
+ */
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_M  (BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V << BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S)
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_0_SP_SPILL_MAX_CLR_S  9
+
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x10)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 0.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MIN_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x14)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 0.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_0_MAX_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x18)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 1.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MIN_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x1c)
+/** BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 1.
+ */
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_M  (BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V << BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S)
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_DRAM0_1_MAX_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x20)
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 0.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MIN_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x24)
+/** BUS_MONITOR_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 0.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_M  (BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_0_MAX_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x28)
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 1.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MIN_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x2c)
+/** BUS_MONITOR_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 1.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_M  (BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V << BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S)
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PIF_1_MAX_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_PC_REG register
+ *  Region monitoring HP CPU PC status register
+ */
+#define BUS_MONITOR_CORE_0_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x30)
+/** BUS_MONITOR_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value when an interrupt is triggered during region monitoring.
+ */
+#define BUS_MONITOR_CORE_0_AREA_PC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PC_M  (BUS_MONITOR_CORE_0_AREA_PC_V << BUS_MONITOR_CORE_0_AREA_PC_S)
+#define BUS_MONITOR_CORE_0_AREA_PC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_PC_S  0
+
+/** BUS_MONITOR_CORE_0_AREA_SP_REG register
+ *  Region monitoring HP CPU SP status register
+ */
+#define BUS_MONITOR_CORE_0_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0x34)
+/** BUS_MONITOR_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  Represents the SP value when an interrupt is triggered during region monitoring.
+ */
+#define BUS_MONITOR_CORE_0_AREA_SP    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_SP_M  (BUS_MONITOR_CORE_0_AREA_SP_V << BUS_MONITOR_CORE_0_AREA_SP_S)
+#define BUS_MONITOR_CORE_0_AREA_SP_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_AREA_SP_S  0
+
+/** BUS_MONITOR_CORE_0_SP_MIN_REG register
+ *  Configures stack monitoring lower boundary address
+ */
+#define BUS_MONITOR_CORE_0_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x38)
+/** BUS_MONITOR_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the lower bound address of SP.
+ */
+#define BUS_MONITOR_CORE_0_SP_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_MIN_M  (BUS_MONITOR_CORE_0_SP_MIN_V << BUS_MONITOR_CORE_0_SP_MIN_S)
+#define BUS_MONITOR_CORE_0_SP_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_MIN_S  0
+
+/** BUS_MONITOR_CORE_0_SP_MAX_REG register
+ *  Configures stack monitoring upper boundary address
+ */
+#define BUS_MONITOR_CORE_0_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x3c)
+/** BUS_MONITOR_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the upper bound address of SP.
+ */
+#define BUS_MONITOR_CORE_0_SP_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_MAX_M  (BUS_MONITOR_CORE_0_SP_MAX_V << BUS_MONITOR_CORE_0_SP_MAX_S)
+#define BUS_MONITOR_CORE_0_SP_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_MAX_S  0
+
+/** BUS_MONITOR_CORE_0_SP_PC_REG register
+ *  Stack monitoring HP CPU PC status register
+ */
+#define BUS_MONITOR_CORE_0_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0x40)
+/** BUS_MONITOR_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value during stack monitoring.
+ */
+#define BUS_MONITOR_CORE_0_SP_PC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_PC_M  (BUS_MONITOR_CORE_0_SP_PC_V << BUS_MONITOR_CORE_0_SP_PC_S)
+#define BUS_MONITOR_CORE_0_SP_PC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_SP_PC_S  0
+
+/** BUS_MONITOR_CORE_0_RCD_EN_REG register
+ *  HP CPU PC logging enable register
+ */
+#define BUS_MONITOR_CORE_0_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0x44)
+/** BUS_MONITOR_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable PC and SP logging.
+ *  0: Disable
+ *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time,
+ *  BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG starts to record SP in real time
+ */
+#define BUS_MONITOR_CORE_0_RCD_RECORDEN    (BIT(0))
+#define BUS_MONITOR_CORE_0_RCD_RECORDEN_M  (BUS_MONITOR_CORE_0_RCD_RECORDEN_V << BUS_MONITOR_CORE_0_RCD_RECORDEN_S)
+#define BUS_MONITOR_CORE_0_RCD_RECORDEN_V  0x00000001U
+#define BUS_MONITOR_CORE_0_RCD_RECORDEN_S  0
+/** BUS_MONITOR_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable HP CPU debugging.
+ *  0: Disable
+ *  1: HP CPU outputs PC
+ */
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_M  (BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V << BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S)
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGEN_S  1
+
+/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG register
+ *  PC logging register
+ */
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0x48)
+/** BUS_MONITOR_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value at HP CPU reset.
+ */
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_M  (BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V << BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S)
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGPC_S  0
+
+/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG register
+ *  PC logging register
+ */
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0x4c)
+/** BUS_MONITOR_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  Represents SP.
+ */
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_M  (BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V << BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S)
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_RCD_PDEBUGSP_S  0
+
+/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0x60)
+/** BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC of the last command before the HP CPU enters exception.
+ */
+#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_M  (BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V << BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S)
+#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_LASTPC_BEFORE_EXC_S  0
+
+/** BUS_MONITOR_CORE_0_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define BUS_MONITOR_CORE_0_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0x64)
+/** BUS_MONITOR_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.
+ *  1: In debugging mode
+ *  0: Not in debugging mode
+ */
+#define BUS_MONITOR_CORE_0_DEBUG_MODE    (BIT(0))
+#define BUS_MONITOR_CORE_0_DEBUG_MODE_M  (BUS_MONITOR_CORE_0_DEBUG_MODE_V << BUS_MONITOR_CORE_0_DEBUG_MODE_S)
+#define BUS_MONITOR_CORE_0_DEBUG_MODE_V  0x00000001U
+#define BUS_MONITOR_CORE_0_DEBUG_MODE_S  0
+/** BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  Represents the status of the RISC-V CPU (HP CPU) debug module.
+ *  1: Active status
+ *  Other: Inactive status
+ */
+#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_M  (BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V << BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define BUS_MONITOR_CORE_0_DEBUG_MODULE_ACTIVE_S  1
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_0_REG register
+ *  TRACE lockup cause logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_MONITOR_BASE + 0x68)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0 : RO; bitpos: [11:0]; default: 0;
+ *  Represents the latest lockup cause
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0    0x00000FFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0_V  0x00000FFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_0_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_0_REG register
+ *  TRACE lockup tval logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_MONITOR_BASE + 0x6c)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the latest lockup tval
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_0_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_0_REG register
+ *  TRACE lockup iaddr logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x70)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the latest lockup iaddr
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_0_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_0_REG register
+ *  TRACE lockup priv logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_MONITOR_BASE + 0x74)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0 : RO; bitpos: [1:0]; default: 0;
+ *  Represents the latest lockup priv
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0    0x00000003U
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0_V  0x00000003U
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_0_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_1_REG register
+ *  TRACE lockup cause logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_MONITOR_BASE + 0x78)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1 : RO; bitpos: [11:0]; default: 0;
+ *  Represents the last lockup cause
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1    0x00000FFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1_V  0x00000FFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_CAUSE_1_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_1_REG register
+ *  TRACE lockup tval logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_MONITOR_BASE + 0x7c)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the last lockup tval
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_TVAL_1_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_1_REG register
+ *  TRACE lockup iaddr logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x80)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the last lockup iaddr
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_IADDR_1_S  0
+
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_1_REG register
+ *  TRACE lockup priv logging register
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_MONITOR_BASE + 0x84)
+/** BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1 : RO; bitpos: [1:0]; default: 0;
+ *  Represents the last lockup priv
+ */
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1    0x00000003U
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1_M  (BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1_V << BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1_S)
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1_V  0x00000003U
+#define BUS_MONITOR_CORE_0_TRACE_LOCKUP_RECORDING_PRIV_1_S  0
+
+/** BUS_MONITOR_CORE_1_MONTR_ENA_REG register
+ *  core1 monitor enable configuration register
+ */
+#define BUS_MONITOR_CORE_1_MONTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x88)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Data bus.
+ *  0: Not monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA    (BIT(0))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_ENA_S  0
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Data bus.
+ *  0: Not monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_ENA_S  1
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Data bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_ENA_S  2
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Data bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_ENA_S  3
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to monitor read operations in region 0 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA    (BIT(4))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_ENA_S  4
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to monitor write operations in region 0 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA    (BIT(5))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_ENA_S  5
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Configures whether to monitor read operations in region 1 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA    (BIT(6))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_ENA_S  6
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Configures whether to monitor write operations in region 1 by the Peripheral bus.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA    (BIT(7))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_ENA_S  7
+/** BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+ *  region.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA    (BIT(8))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA_M  (BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA_V << BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_ENA_S  8
+/** BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+ *  region.
+ *  0: Not Monitor
+ *  1: Monitor
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA    (BIT(9))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA_M  (BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA_V << BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_ENA_S  9
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA : R/W; bitpos: [12]; default: 0;
+ *  trace lockup monitor enable
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA    (BIT(12))
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_ENA_S  12
+
+/** BUS_MONITOR_CORE_1_INTR_RAW_REG register
+ *  core1 monitor interrupt status register
+ */
+#define BUS_MONITOR_CORE_1_INTR_RAW_REG (DR_REG_BUS_MONITOR_BASE + 0x8c)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW    (BIT(0))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_RAW_S  0
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_RAW_S  1
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_RAW_S  2
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_RAW_S  3
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW    (BIT(4))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW_V << BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_RAW_S  4
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW    (BIT(5))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW_V << BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_RAW_S  5
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW    (BIT(6))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW_V << BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_RAW_S  6
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW    (BIT(7))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW_V << BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_RAW_S  7
+/** BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+ *  region.
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW    (BIT(8))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW_M  (BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW_V << BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_RAW_S  8
+/** BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+ *  region.
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW    (BIT(9))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW_M  (BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW_V << BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_RAW_S  9
+
+/** BUS_MONITOR_CORE_1_INTR_ENA_REG register
+ *  core1 monitor interrupt enable register
+ */
+#define BUS_MONITOR_CORE_1_INTR_ENA_REG (DR_REG_BUS_MONITOR_BASE + 0x90)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0;
+ *  Core1 dram0 area0 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA    (BIT(0))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_INTR_ENA_S  0
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Core1 dram0 area0 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA    (BIT(1))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_INTR_ENA_S  1
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0;
+ *  Core1 dram0 area1 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA    (BIT(2))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_INTR_ENA_S  2
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Core1 dram0 area1 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA    (BIT(3))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_INTR_ENA_S  3
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0;
+ *  Core1 PIF area0 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA    (BIT(4))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_INTR_ENA_S  4
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Core1 PIF area0 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA    (BIT(5))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_INTR_ENA_S  5
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0;
+ *  Core1 PIF area1 read monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA    (BIT(6))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_INTR_ENA_S  6
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Core1 PIF area1 write monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA    (BIT(7))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA_V << BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_INTR_ENA_S  7
+/** BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0;
+ *  Core1 stackpoint underflow monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA    (BIT(8))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA_M  (BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA_V << BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_INTR_ENA_S  8
+/** BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0;
+ *  Core1 stackpoint overflow monitor interrupt enable
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA    (BIT(9))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA_M  (BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA_V << BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_INTR_ENA_S  9
+
+/** BUS_MONITOR_CORE_1_INTR_CLR_REG register
+ *  core1 monitor interrupt clear register
+ */
+#define BUS_MONITOR_CORE_1_INTR_CLR_REG (DR_REG_BUS_MONITOR_BASE + 0x94)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR    (BIT(0))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_RD_CLR_S  0
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_WR_CLR_S  1
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_RD_CLR_S  2
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_WR_CLR_S  3
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR    (BIT(4))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR_V << BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_RD_CLR_S  4
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR    (BIT(5))
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR_V << BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_WR_CLR_S  5
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR    (BIT(6))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR_V << BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_RD_CLR_S  6
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR    (BIT(7))
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR_V << BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_WR_CLR_S  7
+/** BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+ *  monitored region.
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR    (BIT(8))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR_M  (BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR_V << BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MIN_CLR_S  8
+/** BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+ *  monitored region.
+ */
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR    (BIT(9))
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR_M  (BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR_V << BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR_S)
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR_V  0x00000001U
+#define BUS_MONITOR_CORE_1_SP_SPILL_MAX_CLR_S  9
+
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0x98)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 0.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MIN_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0x9c)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 0.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_V << BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_0_MAX_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xa0)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Data bus region 1.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MIN_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xa4)
+/** BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Data bus region 1.
+ */
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_M  (BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_V << BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_S)
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_DRAM0_1_MAX_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_REG register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xa8)
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 0.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_V << BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MIN_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_REG register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xac)
+/** BUS_MONITOR_CORE_1_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 0.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_M  (BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_V << BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_0_MAX_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_REG register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xb0)
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the lower bound address of Peripheral bus region 1.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_V << BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MIN_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_REG register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xb4)
+/** BUS_MONITOR_CORE_1_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the upper bound address of Peripheral bus region 1.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_M  (BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_V << BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_S)
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PIF_1_MAX_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_PC_REG register
+ *  Region monitoring HP CPU PC status register
+ */
+#define BUS_MONITOR_CORE_1_AREA_PC_REG (DR_REG_BUS_MONITOR_BASE + 0xb8)
+/** BUS_MONITOR_CORE_1_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value when an interrupt is triggered during region monitoring.
+ */
+#define BUS_MONITOR_CORE_1_AREA_PC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PC_M  (BUS_MONITOR_CORE_1_AREA_PC_V << BUS_MONITOR_CORE_1_AREA_PC_S)
+#define BUS_MONITOR_CORE_1_AREA_PC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_PC_S  0
+
+/** BUS_MONITOR_CORE_1_AREA_SP_REG register
+ *  Region monitoring HP CPU SP status register
+ */
+#define BUS_MONITOR_CORE_1_AREA_SP_REG (DR_REG_BUS_MONITOR_BASE + 0xbc)
+/** BUS_MONITOR_CORE_1_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  Represents the SP value when an interrupt is triggered during region monitoring.
+ */
+#define BUS_MONITOR_CORE_1_AREA_SP    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_SP_M  (BUS_MONITOR_CORE_1_AREA_SP_V << BUS_MONITOR_CORE_1_AREA_SP_S)
+#define BUS_MONITOR_CORE_1_AREA_SP_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_AREA_SP_S  0
+
+/** BUS_MONITOR_CORE_1_SP_MIN_REG register
+ *  Configures stack monitoring lower boundary address
+ */
+#define BUS_MONITOR_CORE_1_SP_MIN_REG (DR_REG_BUS_MONITOR_BASE + 0xc0)
+/** BUS_MONITOR_CORE_1_SP_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the lower bound address of SP.
+ */
+#define BUS_MONITOR_CORE_1_SP_MIN    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_MIN_M  (BUS_MONITOR_CORE_1_SP_MIN_V << BUS_MONITOR_CORE_1_SP_MIN_S)
+#define BUS_MONITOR_CORE_1_SP_MIN_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_MIN_S  0
+
+/** BUS_MONITOR_CORE_1_SP_MAX_REG register
+ *  Configures stack monitoring upper boundary address
+ */
+#define BUS_MONITOR_CORE_1_SP_MAX_REG (DR_REG_BUS_MONITOR_BASE + 0xc4)
+/** BUS_MONITOR_CORE_1_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures the upper bound address of SP.
+ */
+#define BUS_MONITOR_CORE_1_SP_MAX    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_MAX_M  (BUS_MONITOR_CORE_1_SP_MAX_V << BUS_MONITOR_CORE_1_SP_MAX_S)
+#define BUS_MONITOR_CORE_1_SP_MAX_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_MAX_S  0
+
+/** BUS_MONITOR_CORE_1_SP_PC_REG register
+ *  Stack monitoring HP CPU PC status register
+ */
+#define BUS_MONITOR_CORE_1_SP_PC_REG (DR_REG_BUS_MONITOR_BASE + 0xc8)
+/** BUS_MONITOR_CORE_1_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value during stack monitoring.
+ */
+#define BUS_MONITOR_CORE_1_SP_PC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_PC_M  (BUS_MONITOR_CORE_1_SP_PC_V << BUS_MONITOR_CORE_1_SP_PC_S)
+#define BUS_MONITOR_CORE_1_SP_PC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_SP_PC_S  0
+
+/** BUS_MONITOR_CORE_1_RCD_EN_REG register
+ *  HP CPU PC logging enable register
+ */
+#define BUS_MONITOR_CORE_1_RCD_EN_REG (DR_REG_BUS_MONITOR_BASE + 0xcc)
+/** BUS_MONITOR_CORE_1_RCD_RECORDEN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable PC and SP logging.
+ *  0: Disable
+ *  1: ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG starts to record PC in real time,
+ *  BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG starts to record SP in real time
+ */
+#define BUS_MONITOR_CORE_1_RCD_RECORDEN    (BIT(0))
+#define BUS_MONITOR_CORE_1_RCD_RECORDEN_M  (BUS_MONITOR_CORE_1_RCD_RECORDEN_V << BUS_MONITOR_CORE_1_RCD_RECORDEN_S)
+#define BUS_MONITOR_CORE_1_RCD_RECORDEN_V  0x00000001U
+#define BUS_MONITOR_CORE_1_RCD_RECORDEN_S  0
+/** BUS_MONITOR_CORE_1_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable HP CPU debugging.
+ *  0: Disable
+ *  1: HP CPU outputs PC
+ */
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGEN    (BIT(1))
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGEN_M  (BUS_MONITOR_CORE_1_RCD_PDEBUGEN_V << BUS_MONITOR_CORE_1_RCD_PDEBUGEN_S)
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGEN_V  0x00000001U
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGEN_S  1
+
+/** BUS_MONITOR_CORE_1_RCD_PDEBUGPC_REG register
+ *  PC logging register
+ */
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_REG (DR_REG_BUS_MONITOR_BASE + 0xd0)
+/** BUS_MONITOR_CORE_1_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC value at HP CPU reset.
+ */
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_M  (BUS_MONITOR_CORE_1_RCD_PDEBUGPC_V << BUS_MONITOR_CORE_1_RCD_PDEBUGPC_S)
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGPC_S  0
+
+/** BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG register
+ *  PC logging register
+ */
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG (DR_REG_BUS_MONITOR_BASE + 0xd4)
+/** BUS_MONITOR_CORE_1_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  Represents SP.
+ */
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_M  (BUS_MONITOR_CORE_1_RCD_PDEBUGSP_V << BUS_MONITOR_CORE_1_RCD_PDEBUGSP_S)
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_RCD_PDEBUGSP_S  0
+
+/** BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXCEPTION_REG register
+ *  cpu status register
+ */
+#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_BUS_MONITOR_BASE + 0xe8)
+/** BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  Represents the PC of the last command before the HP CPU enters exception.
+ */
+#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC_M  (BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC_V << BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC_S)
+#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_LASTPC_BEFORE_EXC_S  0
+
+/** BUS_MONITOR_CORE_1_DEBUG_MODE_REG register
+ *  cpu status register
+ */
+#define BUS_MONITOR_CORE_1_DEBUG_MODE_REG (DR_REG_BUS_MONITOR_BASE + 0xec)
+/** BUS_MONITOR_CORE_1_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.
+ *  1: In debugging mode
+ *  0: Not in debugging mode
+ */
+#define BUS_MONITOR_CORE_1_DEBUG_MODE    (BIT(0))
+#define BUS_MONITOR_CORE_1_DEBUG_MODE_M  (BUS_MONITOR_CORE_1_DEBUG_MODE_V << BUS_MONITOR_CORE_1_DEBUG_MODE_S)
+#define BUS_MONITOR_CORE_1_DEBUG_MODE_V  0x00000001U
+#define BUS_MONITOR_CORE_1_DEBUG_MODE_S  0
+/** BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  Represents the status of the RISC-V CPU (HP CPU) debug module.
+ *  1: Active status
+ *  Other: Inactive status
+ */
+#define BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE_M  (BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE_V << BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE_S)
+#define BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define BUS_MONITOR_CORE_1_DEBUG_MODULE_ACTIVE_S  1
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_0_REG register
+ *  TRACE lockup cause logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf0)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0 : RO; bitpos: [11:0]; default: 0;
+ *  Represents the latest lockup cause
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0    0x00000FFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0_V  0x00000FFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_0_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_0_REG register
+ *  TRACE lockup tval logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf4)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the latest lockup tval
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_0_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_0_REG register
+ *  TRACE lockup iaddr logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_0_REG (DR_REG_BUS_MONITOR_BASE + 0xf8)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the latest lockup iaddr
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_0_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_0_REG register
+ *  TRACE lockup priv logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_0_REG (DR_REG_BUS_MONITOR_BASE + 0xfc)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0 : RO; bitpos: [1:0]; default: 0;
+ *  Represents the latest lockup priv
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0    0x00000003U
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0_V  0x00000003U
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_0_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_1_REG register
+ *  TRACE lockup cause logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_CAUSE_1_REG (DR_REG_BUS_MONITOR_BASE + 0x100)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1 : RO; bitpos: [11:0]; default: 0;
+ *  Represents the last lockup cause
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1    0x00000FFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1_V  0x00000FFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_CAUSE_1_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_1_REG register
+ *  TRACE lockup tval logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_TVAL_1_REG (DR_REG_BUS_MONITOR_BASE + 0x104)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the last lockup tval
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_TVAL_1_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_1_REG register
+ *  TRACE lockup iaddr logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_IADDR_1_REG (DR_REG_BUS_MONITOR_BASE + 0x108)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the last lockup iaddr
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1    0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1_V  0xFFFFFFFFU
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_IADDR_1_S  0
+
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_1_REG register
+ *  TRACE lockup priv logging register
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_PRIV_1_REG (DR_REG_BUS_MONITOR_BASE + 0x10c)
+/** BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1 : RO; bitpos: [1:0]; default: 0;
+ *  Represents the last lockup priv
+ */
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1    0x00000003U
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1_M  (BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1_V << BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1_S)
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1_V  0x00000003U
+#define BUS_MONITOR_CORE_1_TRACE_LOCKUP_RECORDING_PRIV_1_S  0
+
+/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  exception monitor status register
+ */
+#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_BUS_MONITOR_BASE + 0x110)
+/** BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  reg_core_x_iram0_dram0_limit_cycle_0
+ */
+#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
+#define BUS_MONITOR_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
+
+/** BUS_MONITOR_CLOCK_GATE_REG register
+ *  Register clock control
+ */
+#define BUS_MONITOR_CLOCK_GATE_REG (DR_REG_BUS_MONITOR_BASE + 0x114)
+/** BUS_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to enable the register clock gating.
+ *  0: Disable
+ *  1: Enable
+ */
+#define BUS_MONITOR_CLK_EN    (BIT(0))
+#define BUS_MONITOR_CLK_EN_M  (BUS_MONITOR_CLK_EN_V << BUS_MONITOR_CLK_EN_S)
+#define BUS_MONITOR_CLK_EN_V  0x00000001U
+#define BUS_MONITOR_CLK_EN_S  0
+
+/** BUS_MONITOR_DATE_REG register
+ *  Version control register
+ */
+#define BUS_MONITOR_DATE_REG (DR_REG_BUS_MONITOR_BASE + 0x3fc)
+/** BUS_MONITOR_DATE : R/W; bitpos: [27:0]; default: 34640176;
+ *  version register
+ */
+#define BUS_MONITOR_DATE    0x0FFFFFFFU
+#define BUS_MONITOR_DATE_M  (BUS_MONITOR_DATE_V << BUS_MONITOR_DATE_S)
+#define BUS_MONITOR_DATE_V  0x0FFFFFFFU
+#define BUS_MONITOR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/bus_monitor_struct.h b/components/soc/esp32s31/register/soc/bus_monitor_struct.h
new file mode 100644
index 00000000000..6253e146f0d
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/bus_monitor_struct.h
@@ -0,0 +1,1333 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: monitor configuration registers */
+/** Type of core_0_montr_ena register
+ *  core0 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Data bus.
+         *  0: Not monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_dram0_0_rd_ena:1;
+        /** core_0_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Data bus.
+         *  0: Not monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_dram0_0_wr_ena:1;
+        /** core_0_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Data bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_dram0_1_rd_ena:1;
+        /** core_0_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Data bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_dram0_1_wr_ena:1;
+        /** core_0_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_pif_0_rd_ena:1;
+        /** core_0_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_pif_0_wr_ena:1;
+        /** core_0_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_pif_1_rd_ena:1;
+        /** core_0_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_area_pif_1_wr_ena:1;
+        /** core_0_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+         *  region.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_sp_spill_min_ena:1;
+        /** core_0_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+         *  region.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_0_sp_spill_max_ena:1;
+        uint32_t reserved_10:2;
+        /** core_0_trace_lockup_ena : R/W; bitpos: [12]; default: 0;
+         *  trace lockup monitor enable
+         */
+        uint32_t core_0_trace_lockup_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bus_monitor_core_0_montr_ena_reg_t;
+
+/** Type of core_0_area_dram0_0_min register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 0.
+         */
+        uint32_t core_0_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_dram0_0_min_reg_t;
+
+/** Type of core_0_area_dram0_0_max register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 0.
+         */
+        uint32_t core_0_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_dram0_0_max_reg_t;
+
+/** Type of core_0_area_dram0_1_min register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 1.
+         */
+        uint32_t core_0_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_dram0_1_min_reg_t;
+
+/** Type of core_0_area_dram0_1_max register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 1.
+         */
+        uint32_t core_0_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_dram0_1_max_reg_t;
+
+/** Type of core_0_area_pif_0_min register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 0.
+         */
+        uint32_t core_0_area_pif_0_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_pif_0_min_reg_t;
+
+/** Type of core_0_area_pif_0_max register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 0.
+         */
+        uint32_t core_0_area_pif_0_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_pif_0_max_reg_t;
+
+/** Type of core_0_area_pif_1_min register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 1.
+         */
+        uint32_t core_0_area_pif_1_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_pif_1_min_reg_t;
+
+/** Type of core_0_area_pif_1_max register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_0_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 1.
+         */
+        uint32_t core_0_area_pif_1_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_pif_1_max_reg_t;
+
+/** Type of core_0_area_pc register
+ *  Region monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_0_area_pc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_pc_reg_t;
+
+/** Type of core_0_area_sp register
+ *  Region monitoring HP CPU SP status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  Represents the SP value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_0_area_sp:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_area_sp_reg_t;
+
+/** Type of core_0_sp_min register
+ *  Configures stack monitoring lower boundary address
+ */
+typedef union {
+    struct {
+        /** core_0_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the lower bound address of SP.
+         */
+        uint32_t core_0_sp_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_sp_min_reg_t;
+
+/** Type of core_0_sp_max register
+ *  Configures stack monitoring upper boundary address
+ */
+typedef union {
+    struct {
+        /** core_0_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the upper bound address of SP.
+         */
+        uint32_t core_0_sp_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_sp_max_reg_t;
+
+/** Type of core_0_sp_pc register
+ *  Stack monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_0_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value during stack monitoring.
+         */
+        uint32_t core_0_sp_pc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_sp_pc_reg_t;
+
+/** Type of core_1_montr_ena register
+ *  core1 monitor enable configuration register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Data bus.
+         *  0: Not monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_dram0_0_rd_ena:1;
+        /** core_1_area_dram0_0_wr_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Data bus.
+         *  0: Not monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_dram0_0_wr_ena:1;
+        /** core_1_area_dram0_1_rd_ena : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Data bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_dram0_1_rd_ena:1;
+        /** core_1_area_dram0_1_wr_ena : R/W; bitpos: [3]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Data bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_dram0_1_wr_ena:1;
+        /** core_1_area_pif_0_rd_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to monitor read operations in region 0 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_pif_0_rd_ena:1;
+        /** core_1_area_pif_0_wr_ena : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to monitor write operations in region 0 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_pif_0_wr_ena:1;
+        /** core_1_area_pif_1_rd_ena : R/W; bitpos: [6]; default: 0;
+         *  Configures whether to monitor read operations in region 1 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_pif_1_rd_ena:1;
+        /** core_1_area_pif_1_wr_ena : R/W; bitpos: [7]; default: 0;
+         *  Configures whether to monitor write operations in region 1 by the Peripheral bus.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_area_pif_1_wr_ena:1;
+        /** core_1_sp_spill_min_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to monitor SP exceeding the lower bound address of SP monitored
+         *  region.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_sp_spill_min_ena:1;
+        /** core_1_sp_spill_max_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to monitor SP exceeding the upper bound address of SP monitored
+         *  region.
+         *  0: Not Monitor
+         *  1: Monitor
+         */
+        uint32_t core_1_sp_spill_max_ena:1;
+        uint32_t reserved_10:2;
+        /** core_1_trace_lockup_ena : R/W; bitpos: [12]; default: 0;
+         *  trace lockup monitor enable
+         */
+        uint32_t core_1_trace_lockup_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} bus_monitor_core_1_montr_ena_reg_t;
+
+/** Type of core_1_area_dram0_0_min register
+ *  Configures lower boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 0.
+         */
+        uint32_t core_1_area_dram0_0_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_dram0_0_min_reg_t;
+
+/** Type of core_1_area_dram0_0_max register
+ *  Configures upper boundary address of region 0 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 0.
+         */
+        uint32_t core_1_area_dram0_0_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_dram0_0_max_reg_t;
+
+/** Type of core_1_area_dram0_1_min register
+ *  Configures lower boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Data bus region 1.
+         */
+        uint32_t core_1_area_dram0_1_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_dram0_1_min_reg_t;
+
+/** Type of core_1_area_dram0_1_max register
+ *  Configures upper boundary address of region 1 monitored on Data bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Data bus region 1.
+         */
+        uint32_t core_1_area_dram0_1_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_dram0_1_max_reg_t;
+
+/** Type of core_1_area_pif_0_min register
+ *  Configures lower boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 0.
+         */
+        uint32_t core_1_area_pif_0_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_pif_0_min_reg_t;
+
+/** Type of core_1_area_pif_0_max register
+ *  Configures upper boundary address of region 0 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_0_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 0.
+         */
+        uint32_t core_1_area_pif_0_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_pif_0_max_reg_t;
+
+/** Type of core_1_area_pif_1_min register
+ *  Configures lower boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_min : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the lower bound address of Peripheral bus region 1.
+         */
+        uint32_t core_1_area_pif_1_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_pif_1_min_reg_t;
+
+/** Type of core_1_area_pif_1_max register
+ *  Configures upper boundary address of region 1 monitored on Peripheral bus
+ */
+typedef union {
+    struct {
+        /** core_1_area_pif_1_max : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the upper bound address of Peripheral bus region 1.
+         */
+        uint32_t core_1_area_pif_1_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_pif_1_max_reg_t;
+
+/** Type of core_1_area_pc register
+ *  Region monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_1_area_pc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_pc_reg_t;
+
+/** Type of core_1_area_sp register
+ *  Region monitoring HP CPU SP status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_sp : RO; bitpos: [31:0]; default: 0;
+         *  Represents the SP value when an interrupt is triggered during region monitoring.
+         */
+        uint32_t core_1_area_sp:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_area_sp_reg_t;
+
+/** Type of core_1_sp_min register
+ *  Configures stack monitoring lower boundary address
+ */
+typedef union {
+    struct {
+        /** core_1_sp_min : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the lower bound address of SP.
+         */
+        uint32_t core_1_sp_min:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_sp_min_reg_t;
+
+/** Type of core_1_sp_max register
+ *  Configures stack monitoring upper boundary address
+ */
+typedef union {
+    struct {
+        /** core_1_sp_max : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures the upper bound address of SP.
+         */
+        uint32_t core_1_sp_max:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_sp_max_reg_t;
+
+/** Type of core_1_sp_pc register
+ *  Stack monitoring HP CPU PC status register
+ */
+typedef union {
+    struct {
+        /** core_1_sp_pc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value during stack monitoring.
+         */
+        uint32_t core_1_sp_pc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_sp_pc_reg_t;
+
+
+/** Group: interrupt configuration register */
+/** Type of core_0_intr_raw register
+ *  core0 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_rd_raw:1;
+        /** core_0_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_wr_raw:1;
+        /** core_0_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_rd_raw:1;
+        /** core_0_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_wr_raw:1;
+        /** core_0_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_rd_raw:1;
+        /** core_0_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_wr_raw:1;
+        /** core_0_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_rd_raw:1;
+        /** core_0_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_wr_raw:1;
+        /** core_0_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_0_sp_spill_min_raw:1;
+        /** core_0_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_0_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_0_intr_raw_reg_t;
+
+/** Type of core_0_intr_ena register
+ *  core0 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Core0 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_rd_intr_ena:1;
+        /** core_0_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core0 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_0_wr_intr_ena:1;
+        /** core_0_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
+         *  Core0 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_rd_intr_ena:1;
+        /** core_0_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core0 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_dram0_1_wr_intr_ena:1;
+        /** core_0_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
+         *  Core0 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_rd_intr_ena:1;
+        /** core_0_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core0 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_0_wr_intr_ena:1;
+        /** core_0_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
+         *  Core0 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_rd_intr_ena:1;
+        /** core_0_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core0 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_0_area_pif_1_wr_intr_ena:1;
+        /** core_0_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
+         *  Core0 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_min_intr_ena:1;
+        /** core_0_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
+         *  Core0 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_0_sp_spill_max_intr_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_0_intr_ena_reg_t;
+
+/** Type of core_0_intr_clr register
+ *  core0 monitor interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core_0_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_rd_clr:1;
+        /** core_0_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+         */
+        uint32_t core_0_area_dram0_0_wr_clr:1;
+        /** core_0_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_rd_clr:1;
+        /** core_0_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+         */
+        uint32_t core_0_area_dram0_1_wr_clr:1;
+        /** core_0_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_rd_clr:1;
+        /** core_0_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_0_wr_clr:1;
+        /** core_0_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_rd_clr:1;
+        /** core_0_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_0_area_pif_1_wr_clr:1;
+        /** core_0_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_0_sp_spill_min_clr:1;
+        /** core_0_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_0_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_0_intr_clr_reg_t;
+
+/** Type of core_1_intr_raw register
+ *  core1 monitor interrupt status register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_raw : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Data bus.
+         */
+        uint32_t core_1_area_dram0_0_rd_raw:1;
+        /** core_1_area_dram0_0_wr_raw : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Data bus.
+         */
+        uint32_t core_1_area_dram0_0_wr_raw:1;
+        /** core_1_area_dram0_1_rd_raw : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Data bus.
+         */
+        uint32_t core_1_area_dram0_1_rd_raw:1;
+        /** core_1_area_dram0_1_wr_raw : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Data bus.
+         */
+        uint32_t core_1_area_dram0_1_wr_raw:1;
+        /** core_1_area_pif_0_rd_raw : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status of read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_0_rd_raw:1;
+        /** core_1_area_pif_0_wr_raw : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status of write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_0_wr_raw:1;
+        /** core_1_area_pif_1_rd_raw : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status of read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_1_rd_raw:1;
+        /** core_1_area_pif_1_wr_raw : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status of write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_1_wr_raw:1;
+        /** core_1_sp_spill_min_raw : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status of SP exceeding the lower bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_1_sp_spill_min_raw:1;
+        /** core_1_sp_spill_max_raw : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status of SP exceeding the upper bound address of SP monitored
+         *  region.
+         */
+        uint32_t core_1_sp_spill_max_raw:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_1_intr_raw_reg_t;
+
+/** Type of core_1_intr_ena register
+ *  core1 monitor interrupt enable register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_intr_ena : R/W; bitpos: [0]; default: 0;
+         *  Core1 dram0 area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_rd_intr_ena:1;
+        /** core_1_area_dram0_0_wr_intr_ena : R/W; bitpos: [1]; default: 0;
+         *  Core1 dram0 area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_0_wr_intr_ena:1;
+        /** core_1_area_dram0_1_rd_intr_ena : R/W; bitpos: [2]; default: 0;
+         *  Core1 dram0 area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_rd_intr_ena:1;
+        /** core_1_area_dram0_1_wr_intr_ena : R/W; bitpos: [3]; default: 0;
+         *  Core1 dram0 area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_dram0_1_wr_intr_ena:1;
+        /** core_1_area_pif_0_rd_intr_ena : R/W; bitpos: [4]; default: 0;
+         *  Core1 PIF area0 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_rd_intr_ena:1;
+        /** core_1_area_pif_0_wr_intr_ena : R/W; bitpos: [5]; default: 0;
+         *  Core1 PIF area0 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_0_wr_intr_ena:1;
+        /** core_1_area_pif_1_rd_intr_ena : R/W; bitpos: [6]; default: 0;
+         *  Core1 PIF area1 read monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_rd_intr_ena:1;
+        /** core_1_area_pif_1_wr_intr_ena : R/W; bitpos: [7]; default: 0;
+         *  Core1 PIF area1 write monitor interrupt enable
+         */
+        uint32_t core_1_area_pif_1_wr_intr_ena:1;
+        /** core_1_sp_spill_min_intr_ena : R/W; bitpos: [8]; default: 0;
+         *  Core1 stackpoint underflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_min_intr_ena:1;
+        /** core_1_sp_spill_max_intr_ena : R/W; bitpos: [9]; default: 0;
+         *  Core1 stackpoint overflow monitor interrupt enable
+         */
+        uint32_t core_1_sp_spill_max_intr_ena:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_1_intr_ena_reg_t;
+
+/** Type of core_1_intr_clr register
+ *  core1 monitor interrupt clear register
+ */
+typedef union {
+    struct {
+        /** core_1_area_dram0_0_rd_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Data bus.
+         */
+        uint32_t core_1_area_dram0_0_rd_clr:1;
+        /** core_1_area_dram0_0_wr_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Data bus.
+         */
+        uint32_t core_1_area_dram0_0_wr_clr:1;
+        /** core_1_area_dram0_1_rd_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Data bus.
+         */
+        uint32_t core_1_area_dram0_1_rd_clr:1;
+        /** core_1_area_dram0_1_wr_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Data bus.
+         */
+        uint32_t core_1_area_dram0_1_wr_clr:1;
+        /** core_1_area_pif_0_rd_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_0_rd_clr:1;
+        /** core_1_area_pif_0_wr_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_0_wr_clr:1;
+        /** core_1_area_pif_1_rd_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_1_rd_clr:1;
+        /** core_1_area_pif_1_wr_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus.
+         */
+        uint32_t core_1_area_pif_1_wr_clr:1;
+        /** core_1_sp_spill_min_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the lower bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_1_sp_spill_min_clr:1;
+        /** core_1_sp_spill_max_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear the interrupt for SP exceeding the upper bound address of SP
+         *  monitored region.
+         */
+        uint32_t core_1_sp_spill_max_clr:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} bus_monitor_core_1_intr_clr_reg_t;
+
+
+/** Group: pc recording configuration register */
+/** Type of core_0_rcd_en register
+ *  HP CPU PC logging enable register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable PC and SP logging.
+         *  0: Disable
+         *  1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time,
+         *  BUS_MONITOR_CORE_0_RCD_PDEBUGSP_REG starts to record SP in real time
+         */
+        uint32_t core_0_rcd_recorden:1;
+        /** core_0_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable HP CPU debugging.
+         *  0: Disable
+         *  1: HP CPU outputs PC
+         */
+        uint32_t core_0_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_0_rcd_en_reg_t;
+
+/** Type of core_1_rcd_en register
+ *  HP CPU PC logging enable register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_recorden : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable PC and SP logging.
+         *  0: Disable
+         *  1: ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG starts to record PC in real time,
+         *  BUS_MONITOR_CORE_1_RCD_PDEBUGSP_REG starts to record SP in real time
+         */
+        uint32_t core_1_rcd_recorden:1;
+        /** core_1_rcd_pdebugen : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable HP CPU debugging.
+         *  0: Disable
+         *  1: HP CPU outputs PC
+         */
+        uint32_t core_1_rcd_pdebugen:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_1_rcd_en_reg_t;
+
+
+/** Group: pc recording status register */
+/** Type of core_0_rcd_pdebugpc register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value at HP CPU reset.
+         */
+        uint32_t core_0_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_rcd_pdebugpc_reg_t;
+
+/** Type of core_0_rcd_pdebugsp register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_0_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  Represents SP.
+         */
+        uint32_t core_0_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_rcd_pdebugsp_reg_t;
+
+/** Type of core_1_rcd_pdebugpc register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugpc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC value at HP CPU reset.
+         */
+        uint32_t core_1_rcd_pdebugpc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_rcd_pdebugpc_reg_t;
+
+/** Type of core_1_rcd_pdebugsp register
+ *  PC logging register
+ */
+typedef union {
+    struct {
+        /** core_1_rcd_pdebugsp : RO; bitpos: [31:0]; default: 0;
+         *  Represents SP.
+         */
+        uint32_t core_1_rcd_pdebugsp:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_rcd_pdebugsp_reg_t;
+
+
+/** Group: exception monitor register */
+/** Type of core_x_iram0_dram0_exception_monitor_0 register
+ *  exception monitor status register
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_limit_cycle_0 : R/W; bitpos: [19:0]; default: 0;
+         *  reg_core_x_iram0_dram0_limit_cycle_0
+         */
+        uint32_t core_x_iram0_dram0_limit_cycle_0:20;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t;
+
+
+/** Group: cpu status registers */
+/** Type of core_0_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC of the last command before the HP CPU enters exception.
+         */
+        uint32_t core_0_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_lastpc_before_exception_reg_t;
+
+/** Type of core_0_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_0_debug_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.
+         *  1: In debugging mode
+         *  0: Not in debugging mode
+         */
+        uint32_t core_0_debug_mode:1;
+        /** core_0_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  Represents the status of the RISC-V CPU (HP CPU) debug module.
+         *  1: Active status
+         *  Other: Inactive status
+         */
+        uint32_t core_0_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_0_debug_mode_reg_t;
+
+/** Type of core_1_lastpc_before_exception register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_lastpc_before_exc : RO; bitpos: [31:0]; default: 0;
+         *  Represents the PC of the last command before the HP CPU enters exception.
+         */
+        uint32_t core_1_lastpc_before_exc:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_lastpc_before_exception_reg_t;
+
+/** Type of core_1_debug_mode register
+ *  cpu status register
+ */
+typedef union {
+    struct {
+        /** core_1_debug_mode : RO; bitpos: [0]; default: 0;
+         *  Represents whether RISC-V CPU (HP CPU) is in debugging mode.
+         *  1: In debugging mode
+         *  0: Not in debugging mode
+         */
+        uint32_t core_1_debug_mode:1;
+        /** core_1_debug_module_active : RO; bitpos: [1]; default: 0;
+         *  Represents the status of the RISC-V CPU (HP CPU) debug module.
+         *  1: Active status
+         *  Other: Inactive status
+         */
+        uint32_t core_1_debug_module_active:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_1_debug_mode_reg_t;
+
+
+/** Group: lockup recording status register */
+/** Type of core_0_trace_lockup_cause_0 register
+ *  TRACE lockup cause logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_cause_0 : RO; bitpos: [11:0]; default: 0;
+         *  Represents the latest lockup cause
+         */
+        uint32_t core_0_trace_lockup_recording_cause_0:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_cause_0_reg_t;
+
+/** Type of core_0_trace_lockup_tval_0 register
+ *  TRACE lockup tval logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_tval_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the latest lockup tval
+         */
+        uint32_t core_0_trace_lockup_recording_tval_0:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_tval_0_reg_t;
+
+/** Type of core_0_trace_lockup_iaddr_0 register
+ *  TRACE lockup iaddr logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_iaddr_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the latest lockup iaddr
+         */
+        uint32_t core_0_trace_lockup_recording_iaddr_0:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_iaddr_0_reg_t;
+
+/** Type of core_0_trace_lockup_priv_0 register
+ *  TRACE lockup priv logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_priv_0 : RO; bitpos: [1:0]; default: 0;
+         *  Represents the latest lockup priv
+         */
+        uint32_t core_0_trace_lockup_recording_priv_0:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_priv_0_reg_t;
+
+/** Type of core_0_trace_lockup_cause_1 register
+ *  TRACE lockup cause logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_cause_1 : RO; bitpos: [11:0]; default: 0;
+         *  Represents the last lockup cause
+         */
+        uint32_t core_0_trace_lockup_recording_cause_1:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_cause_1_reg_t;
+
+/** Type of core_0_trace_lockup_tval_1 register
+ *  TRACE lockup tval logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_tval_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the last lockup tval
+         */
+        uint32_t core_0_trace_lockup_recording_tval_1:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_tval_1_reg_t;
+
+/** Type of core_0_trace_lockup_iaddr_1 register
+ *  TRACE lockup iaddr logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_iaddr_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the last lockup iaddr
+         */
+        uint32_t core_0_trace_lockup_recording_iaddr_1:32;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_iaddr_1_reg_t;
+
+/** Type of core_0_trace_lockup_priv_1 register
+ *  TRACE lockup priv logging register
+ */
+typedef union {
+    struct {
+        /** core_0_trace_lockup_recording_priv_1 : RO; bitpos: [1:0]; default: 0;
+         *  Represents the last lockup priv
+         */
+        uint32_t core_0_trace_lockup_recording_priv_1:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_0_trace_lockup_priv_1_reg_t;
+
+/** Type of core_1_trace_lockup_cause_0 register
+ *  TRACE lockup cause logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_cause_0 : RO; bitpos: [11:0]; default: 0;
+         *  Represents the latest lockup cause
+         */
+        uint32_t core_1_trace_lockup_recording_cause_0:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_cause_0_reg_t;
+
+/** Type of core_1_trace_lockup_tval_0 register
+ *  TRACE lockup tval logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_tval_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the latest lockup tval
+         */
+        uint32_t core_1_trace_lockup_recording_tval_0:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_tval_0_reg_t;
+
+/** Type of core_1_trace_lockup_iaddr_0 register
+ *  TRACE lockup iaddr logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_iaddr_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the latest lockup iaddr
+         */
+        uint32_t core_1_trace_lockup_recording_iaddr_0:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_iaddr_0_reg_t;
+
+/** Type of core_1_trace_lockup_priv_0 register
+ *  TRACE lockup priv logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_priv_0 : RO; bitpos: [1:0]; default: 0;
+         *  Represents the latest lockup priv
+         */
+        uint32_t core_1_trace_lockup_recording_priv_0:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_priv_0_reg_t;
+
+/** Type of core_1_trace_lockup_cause_1 register
+ *  TRACE lockup cause logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_cause_1 : RO; bitpos: [11:0]; default: 0;
+         *  Represents the last lockup cause
+         */
+        uint32_t core_1_trace_lockup_recording_cause_1:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_cause_1_reg_t;
+
+/** Type of core_1_trace_lockup_tval_1 register
+ *  TRACE lockup tval logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_tval_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the last lockup tval
+         */
+        uint32_t core_1_trace_lockup_recording_tval_1:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_tval_1_reg_t;
+
+/** Type of core_1_trace_lockup_iaddr_1 register
+ *  TRACE lockup iaddr logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_iaddr_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the last lockup iaddr
+         */
+        uint32_t core_1_trace_lockup_recording_iaddr_1:32;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_iaddr_1_reg_t;
+
+/** Type of core_1_trace_lockup_priv_1 register
+ *  TRACE lockup priv logging register
+ */
+typedef union {
+    struct {
+        /** core_1_trace_lockup_recording_priv_1 : RO; bitpos: [1:0]; default: 0;
+         *  Represents the last lockup priv
+         */
+        uint32_t core_1_trace_lockup_recording_priv_1:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} bus_monitor_core_1_trace_lockup_priv_1_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of clock_gate register
+ *  Register clock control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to enable the register clock gating.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} bus_monitor_clock_gate_reg_t;
+
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 34640176;
+         *  version register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} bus_monitor_date_reg_t;
+
+
+typedef struct {
+    volatile bus_monitor_core_0_montr_ena_reg_t core_0_montr_ena;
+    volatile bus_monitor_core_0_intr_raw_reg_t core_0_intr_raw;
+    volatile bus_monitor_core_0_intr_ena_reg_t core_0_intr_ena;
+    volatile bus_monitor_core_0_intr_clr_reg_t core_0_intr_clr;
+    volatile bus_monitor_core_0_area_dram0_0_min_reg_t core_0_area_dram0_0_min;
+    volatile bus_monitor_core_0_area_dram0_0_max_reg_t core_0_area_dram0_0_max;
+    volatile bus_monitor_core_0_area_dram0_1_min_reg_t core_0_area_dram0_1_min;
+    volatile bus_monitor_core_0_area_dram0_1_max_reg_t core_0_area_dram0_1_max;
+    volatile bus_monitor_core_0_area_pif_0_min_reg_t core_0_area_pif_0_min;
+    volatile bus_monitor_core_0_area_pif_0_max_reg_t core_0_area_pif_0_max;
+    volatile bus_monitor_core_0_area_pif_1_min_reg_t core_0_area_pif_1_min;
+    volatile bus_monitor_core_0_area_pif_1_max_reg_t core_0_area_pif_1_max;
+    volatile bus_monitor_core_0_area_pc_reg_t core_0_area_pc;
+    volatile bus_monitor_core_0_area_sp_reg_t core_0_area_sp;
+    volatile bus_monitor_core_0_sp_min_reg_t core_0_sp_min;
+    volatile bus_monitor_core_0_sp_max_reg_t core_0_sp_max;
+    volatile bus_monitor_core_0_sp_pc_reg_t core_0_sp_pc;
+    volatile bus_monitor_core_0_rcd_en_reg_t core_0_rcd_en;
+    volatile bus_monitor_core_0_rcd_pdebugpc_reg_t core_0_rcd_pdebugpc;
+    volatile bus_monitor_core_0_rcd_pdebugsp_reg_t core_0_rcd_pdebugsp;
+    uint32_t reserved_050[4];
+    volatile bus_monitor_core_0_lastpc_before_exception_reg_t core_0_lastpc_before_exception;
+    volatile bus_monitor_core_0_debug_mode_reg_t core_0_debug_mode;
+    volatile bus_monitor_core_0_trace_lockup_cause_0_reg_t core_0_trace_lockup_cause_0;
+    volatile bus_monitor_core_0_trace_lockup_tval_0_reg_t core_0_trace_lockup_tval_0;
+    volatile bus_monitor_core_0_trace_lockup_iaddr_0_reg_t core_0_trace_lockup_iaddr_0;
+    volatile bus_monitor_core_0_trace_lockup_priv_0_reg_t core_0_trace_lockup_priv_0;
+    volatile bus_monitor_core_0_trace_lockup_cause_1_reg_t core_0_trace_lockup_cause_1;
+    volatile bus_monitor_core_0_trace_lockup_tval_1_reg_t core_0_trace_lockup_tval_1;
+    volatile bus_monitor_core_0_trace_lockup_iaddr_1_reg_t core_0_trace_lockup_iaddr_1;
+    volatile bus_monitor_core_0_trace_lockup_priv_1_reg_t core_0_trace_lockup_priv_1;
+    volatile bus_monitor_core_1_montr_ena_reg_t core_1_montr_ena;
+    volatile bus_monitor_core_1_intr_raw_reg_t core_1_intr_raw;
+    volatile bus_monitor_core_1_intr_ena_reg_t core_1_intr_ena;
+    volatile bus_monitor_core_1_intr_clr_reg_t core_1_intr_clr;
+    volatile bus_monitor_core_1_area_dram0_0_min_reg_t core_1_area_dram0_0_min;
+    volatile bus_monitor_core_1_area_dram0_0_max_reg_t core_1_area_dram0_0_max;
+    volatile bus_monitor_core_1_area_dram0_1_min_reg_t core_1_area_dram0_1_min;
+    volatile bus_monitor_core_1_area_dram0_1_max_reg_t core_1_area_dram0_1_max;
+    volatile bus_monitor_core_1_area_pif_0_min_reg_t core_1_area_pif_0_min;
+    volatile bus_monitor_core_1_area_pif_0_max_reg_t core_1_area_pif_0_max;
+    volatile bus_monitor_core_1_area_pif_1_min_reg_t core_1_area_pif_1_min;
+    volatile bus_monitor_core_1_area_pif_1_max_reg_t core_1_area_pif_1_max;
+    volatile bus_monitor_core_1_area_pc_reg_t core_1_area_pc;
+    volatile bus_monitor_core_1_area_sp_reg_t core_1_area_sp;
+    volatile bus_monitor_core_1_sp_min_reg_t core_1_sp_min;
+    volatile bus_monitor_core_1_sp_max_reg_t core_1_sp_max;
+    volatile bus_monitor_core_1_sp_pc_reg_t core_1_sp_pc;
+    volatile bus_monitor_core_1_rcd_en_reg_t core_1_rcd_en;
+    volatile bus_monitor_core_1_rcd_pdebugpc_reg_t core_1_rcd_pdebugpc;
+    volatile bus_monitor_core_1_rcd_pdebugsp_reg_t core_1_rcd_pdebugsp;
+    uint32_t reserved_0d8[4];
+    volatile bus_monitor_core_1_lastpc_before_exception_reg_t core_1_lastpc_before_exception;
+    volatile bus_monitor_core_1_debug_mode_reg_t core_1_debug_mode;
+    volatile bus_monitor_core_1_trace_lockup_cause_0_reg_t core_1_trace_lockup_cause_0;
+    volatile bus_monitor_core_1_trace_lockup_tval_0_reg_t core_1_trace_lockup_tval_0;
+    volatile bus_monitor_core_1_trace_lockup_iaddr_0_reg_t core_1_trace_lockup_iaddr_0;
+    volatile bus_monitor_core_1_trace_lockup_priv_0_reg_t core_1_trace_lockup_priv_0;
+    volatile bus_monitor_core_1_trace_lockup_cause_1_reg_t core_1_trace_lockup_cause_1;
+    volatile bus_monitor_core_1_trace_lockup_tval_1_reg_t core_1_trace_lockup_tval_1;
+    volatile bus_monitor_core_1_trace_lockup_iaddr_1_reg_t core_1_trace_lockup_iaddr_1;
+    volatile bus_monitor_core_1_trace_lockup_priv_1_reg_t core_1_trace_lockup_priv_1;
+    volatile bus_monitor_core_x_iram0_dram0_exception_monitor_0_reg_t core_x_iram0_dram0_exception_monitor_0;
+    volatile bus_monitor_clock_gate_reg_t clock_gate;
+    uint32_t reserved_118[185];
+    volatile bus_monitor_date_reg_t date;
+} bus_monitor_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(bus_monitor_dev_t) == 0x400, "Invalid size of bus_monitor_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cache_reg.h b/components/soc/esp32s31/register/soc/cache_reg.h
new file mode 100644
index 00000000000..eb320d2968b
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cache_reg.h
@@ -0,0 +1,6982 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CACHE_L1_ICACHE_CTRL_REG register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+#define CACHE_L1_ICACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x0)
+/** CACHE_L1_ICACHE_SHUT_IBUS0 : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to disable IBUS0 to access icache.
+ *  1: Disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS0    (BIT(0))
+#define CACHE_L1_ICACHE_SHUT_IBUS0_M  (CACHE_L1_ICACHE_SHUT_IBUS0_V << CACHE_L1_ICACHE_SHUT_IBUS0_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS0_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS0_S  0
+/** CACHE_L1_ICACHE_SHUT_IBUS1 : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to disable IBUS1 to access icache.
+ *  1: Disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS1    (BIT(1))
+#define CACHE_L1_ICACHE_SHUT_IBUS1_M  (CACHE_L1_ICACHE_SHUT_IBUS1_V << CACHE_L1_ICACHE_SHUT_IBUS1_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS1_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS1_S  1
+/** CACHE_L1_ICACHE_SHUT_IBUS2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to disable IBUS2 to access ROM cache.
+ *  1: Disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS2    (BIT(2))
+#define CACHE_L1_ICACHE_SHUT_IBUS2_M  (CACHE_L1_ICACHE_SHUT_IBUS2_V << CACHE_L1_ICACHE_SHUT_IBUS2_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS2_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS2_S  2
+/** CACHE_L1_ICACHE_SHUT_IBUS3 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether to disable IBUS3 to access ROM cache.
+ *  1: Disable
+ */
+#define CACHE_L1_ICACHE_SHUT_IBUS3    (BIT(3))
+#define CACHE_L1_ICACHE_SHUT_IBUS3_M  (CACHE_L1_ICACHE_SHUT_IBUS3_V << CACHE_L1_ICACHE_SHUT_IBUS3_S)
+#define CACHE_L1_ICACHE_SHUT_IBUS3_V  0x00000001U
+#define CACHE_L1_ICACHE_SHUT_IBUS3_S  3
+/** CACHE_L1_ICACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L1_ICACHE_UNDEF_OP_M  (CACHE_L1_ICACHE_UNDEF_OP_V << CACHE_L1_ICACHE_UNDEF_OP_S)
+#define CACHE_L1_ICACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L1_ICACHE_UNDEF_OP_S  8
+
+/** CACHE_L1_DCACHE_CTRL_REG register
+ *  L1 data Cache(L1-DCache) control register
+ */
+#define CACHE_L1_DCACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x4)
+/** CACHE_L1_DCACHE_SHUT_DBUS0 : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to disable DBUS0 to access dcache.
+ *  1: Disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS0    (BIT(0))
+#define CACHE_L1_DCACHE_SHUT_DBUS0_M  (CACHE_L1_DCACHE_SHUT_DBUS0_V << CACHE_L1_DCACHE_SHUT_DBUS0_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS0_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS0_S  0
+/** CACHE_L1_DCACHE_SHUT_DBUS1 : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to disable DBUS1 to access dcache.
+ *  1: Disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS1    (BIT(1))
+#define CACHE_L1_DCACHE_SHUT_DBUS1_M  (CACHE_L1_DCACHE_SHUT_DBUS1_V << CACHE_L1_DCACHE_SHUT_DBUS1_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS1_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS1_S  1
+/** CACHE_L1_DCACHE_SHUT_DBUS2 : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to disable DBUS2 to access ROM cache.
+ *  1: Disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS2    (BIT(2))
+#define CACHE_L1_DCACHE_SHUT_DBUS2_M  (CACHE_L1_DCACHE_SHUT_DBUS2_V << CACHE_L1_DCACHE_SHUT_DBUS2_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS2_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS2_S  2
+/** CACHE_L1_DCACHE_SHUT_DBUS3 : R/W; bitpos: [3]; default: 0;
+ *  Configures whether to disable DBUS3 to access ROM cache.
+ *  1: Disable
+ */
+#define CACHE_L1_DCACHE_SHUT_DBUS3    (BIT(3))
+#define CACHE_L1_DCACHE_SHUT_DBUS3_M  (CACHE_L1_DCACHE_SHUT_DBUS3_V << CACHE_L1_DCACHE_SHUT_DBUS3_S)
+#define CACHE_L1_DCACHE_SHUT_DBUS3_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DBUS3_S  3
+/** CACHE_L1_DCACHE_SHUT_DMA : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L1_DCACHE_SHUT_DMA_M  (CACHE_L1_DCACHE_SHUT_DMA_V << CACHE_L1_DCACHE_SHUT_DMA_S)
+#define CACHE_L1_DCACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L1_DCACHE_SHUT_DMA_S  4
+/** CACHE_L1_DCACHE_UNDEF_OP : R/W; bitpos: [15:8]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L1_DCACHE_UNDEF_OP_M  (CACHE_L1_DCACHE_UNDEF_OP_V << CACHE_L1_DCACHE_UNDEF_OP_S)
+#define CACHE_L1_DCACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L1_DCACHE_UNDEF_OP_S  8
+
+/** CACHE_L1_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ */
+#define CACHE_L1_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x8)
+/** CACHE_BYPASS_L1_ICACHE0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures bypass L1-ICache0.
+ *  1: Enable
+ *
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_BYPASS_L1_ICACHE0_EN    (BIT(0))
+#define CACHE_BYPASS_L1_ICACHE0_EN_M  (CACHE_BYPASS_L1_ICACHE0_EN_V << CACHE_BYPASS_L1_ICACHE0_EN_S)
+#define CACHE_BYPASS_L1_ICACHE0_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE0_EN_S  0
+/** CACHE_BYPASS_L1_ICACHE1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures bypass L1-ICache1.
+ *  1: Enable
+ *
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_BYPASS_L1_ICACHE1_EN    (BIT(1))
+#define CACHE_BYPASS_L1_ICACHE1_EN_M  (CACHE_BYPASS_L1_ICACHE1_EN_V << CACHE_BYPASS_L1_ICACHE1_EN_S)
+#define CACHE_BYPASS_L1_ICACHE1_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE1_EN_S  1
+/** CACHE_BYPASS_L1_ICACHE2_EN : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_BYPASS_L1_ICACHE2_EN    (BIT(2))
+#define CACHE_BYPASS_L1_ICACHE2_EN_M  (CACHE_BYPASS_L1_ICACHE2_EN_V << CACHE_BYPASS_L1_ICACHE2_EN_S)
+#define CACHE_BYPASS_L1_ICACHE2_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE2_EN_S  2
+/** CACHE_BYPASS_L1_ICACHE3_EN : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_BYPASS_L1_ICACHE3_EN    (BIT(3))
+#define CACHE_BYPASS_L1_ICACHE3_EN_M  (CACHE_BYPASS_L1_ICACHE3_EN_V << CACHE_BYPASS_L1_ICACHE3_EN_S)
+#define CACHE_BYPASS_L1_ICACHE3_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_ICACHE3_EN_S  3
+/** CACHE_BYPASS_L1_DCACHE_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures bypass L1-DCache.
+ *  1: Enable
+ */
+#define CACHE_BYPASS_L1_DCACHE_EN    (BIT(4))
+#define CACHE_BYPASS_L1_DCACHE_EN_M  (CACHE_BYPASS_L1_DCACHE_EN_V << CACHE_BYPASS_L1_DCACHE_EN_S)
+#define CACHE_BYPASS_L1_DCACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L1_DCACHE_EN_S  4
+
+/** CACHE_L1_CACHE_ATOMIC_CONF_REG register
+ *  L1 Cache atomic feature configure register
+ */
+#define CACHE_L1_CACHE_ATOMIC_CONF_REG (DR_REG_CACHE_BASE + 0xc)
+/** CACHE_L1_DCACHE_ATOMIC_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures atomic feature on L1-DCache when multiple cores access L1-DCache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_ATOMIC_EN    (BIT(0))
+#define CACHE_L1_DCACHE_ATOMIC_EN_M  (CACHE_L1_DCACHE_ATOMIC_EN_V << CACHE_L1_DCACHE_ATOMIC_EN_S)
+#define CACHE_L1_DCACHE_ATOMIC_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_ATOMIC_EN_S  0
+
+/** CACHE_L1_ACACHE_CACHESIZE_CONF_REG register
+ *  L1 Auxiliary Cache CacheSize mode configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x10)
+/** CACHE_L1_ACACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ACACHE_CACHESIZE_256_M  (CACHE_L1_ACACHE_CACHESIZE_256_V << CACHE_L1_ACACHE_CACHESIZE_256_S)
+#define CACHE_L1_ACACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ACACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ACACHE_CACHESIZE_512_M  (CACHE_L1_ACACHE_CACHESIZE_512_V << CACHE_L1_ACACHE_CACHESIZE_512_S)
+#define CACHE_L1_ACACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ACACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ACACHE_CACHESIZE_1K_M  (CACHE_L1_ACACHE_CACHESIZE_1K_V << CACHE_L1_ACACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ACACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ACACHE_CACHESIZE_2K_M  (CACHE_L1_ACACHE_CACHESIZE_2K_V << CACHE_L1_ACACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ACACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 1;
+ *  The field is used to configure cachesize of L1-ACache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ACACHE_CACHESIZE_4K_M  (CACHE_L1_ACACHE_CACHESIZE_4K_V << CACHE_L1_ACACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ACACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ACACHE_CACHESIZE_8K_M  (CACHE_L1_ACACHE_CACHESIZE_8K_V << CACHE_L1_ACACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ACACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ACACHE_CACHESIZE_16K_M  (CACHE_L1_ACACHE_CACHESIZE_16K_V << CACHE_L1_ACACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ACACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ACACHE_CACHESIZE_32K_M  (CACHE_L1_ACACHE_CACHESIZE_32K_V << CACHE_L1_ACACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ACACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ACACHE_CACHESIZE_64K_M  (CACHE_L1_ACACHE_CACHESIZE_64K_V << CACHE_L1_ACACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ACACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ACACHE_CACHESIZE_128K_M  (CACHE_L1_ACACHE_CACHESIZE_128K_V << CACHE_L1_ACACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ACACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ACACHE_CACHESIZE_256K_M  (CACHE_L1_ACACHE_CACHESIZE_256K_V << CACHE_L1_ACACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ACACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ACACHE_CACHESIZE_512K_M  (CACHE_L1_ACACHE_CACHESIZE_512K_V << CACHE_L1_ACACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ACACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ACache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ACACHE_CACHESIZE_1024K_M  (CACHE_L1_ACACHE_CACHESIZE_1024K_V << CACHE_L1_ACACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ACACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ACACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ACACHE_BLOCKSIZE_CONF_REG register
+ *  L1 Auxiliary Cache BlockSize mode configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x14)
+/** CACHE_L1_ACACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ACache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ACACHE_BLOCKSIZE_8_M  (CACHE_L1_ACACHE_BLOCKSIZE_8_V << CACHE_L1_ACACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ACACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ACache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ACACHE_BLOCKSIZE_16_M  (CACHE_L1_ACACHE_BLOCKSIZE_16_V << CACHE_L1_ACACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ACACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ACache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ACACHE_BLOCKSIZE_32_M  (CACHE_L1_ACACHE_BLOCKSIZE_32_V << CACHE_L1_ACACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ACACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-ACache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ACACHE_BLOCKSIZE_64_M  (CACHE_L1_ACACHE_BLOCKSIZE_64_V << CACHE_L1_ACACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ACACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ACache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ACACHE_BLOCKSIZE_128_M  (CACHE_L1_ACACHE_BLOCKSIZE_128_V << CACHE_L1_ACACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ACACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ACache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ACACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ACACHE_BLOCKSIZE_256_M  (CACHE_L1_ACACHE_BLOCKSIZE_256_V << CACHE_L1_ACACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ACACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ACACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_ICACHE_CACHESIZE_CONF_REG register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x18)
+/** CACHE_L1_ICACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_ICACHE_CACHESIZE_256_M  (CACHE_L1_ICACHE_CACHESIZE_256_V << CACHE_L1_ICACHE_CACHESIZE_256_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256_S  0
+/** CACHE_L1_ICACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_ICACHE_CACHESIZE_512_M  (CACHE_L1_ICACHE_CACHESIZE_512_V << CACHE_L1_ICACHE_CACHESIZE_512_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512_S  1
+/** CACHE_L1_ICACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_ICACHE_CACHESIZE_1K_M  (CACHE_L1_ICACHE_CACHESIZE_1K_V << CACHE_L1_ICACHE_CACHESIZE_1K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_ICACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_ICACHE_CACHESIZE_2K_M  (CACHE_L1_ICACHE_CACHESIZE_2K_V << CACHE_L1_ICACHE_CACHESIZE_2K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_ICACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_ICACHE_CACHESIZE_4K_M  (CACHE_L1_ICACHE_CACHESIZE_4K_V << CACHE_L1_ICACHE_CACHESIZE_4K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_ICACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_ICACHE_CACHESIZE_8K_M  (CACHE_L1_ICACHE_CACHESIZE_8K_V << CACHE_L1_ICACHE_CACHESIZE_8K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_ICACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_ICACHE_CACHESIZE_16K_M  (CACHE_L1_ICACHE_CACHESIZE_16K_V << CACHE_L1_ICACHE_CACHESIZE_16K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_ICACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 1;
+ *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_ICACHE_CACHESIZE_32K_M  (CACHE_L1_ICACHE_CACHESIZE_32K_V << CACHE_L1_ICACHE_CACHESIZE_32K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_ICACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_ICACHE_CACHESIZE_64K_M  (CACHE_L1_ICACHE_CACHESIZE_64K_V << CACHE_L1_ICACHE_CACHESIZE_64K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_ICACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_ICACHE_CACHESIZE_128K_M  (CACHE_L1_ICACHE_CACHESIZE_128K_V << CACHE_L1_ICACHE_CACHESIZE_128K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_ICACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_ICACHE_CACHESIZE_256K_M  (CACHE_L1_ICACHE_CACHESIZE_256K_V << CACHE_L1_ICACHE_CACHESIZE_256K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_ICACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_ICACHE_CACHESIZE_512K_M  (CACHE_L1_ICACHE_CACHESIZE_512K_V << CACHE_L1_ICACHE_CACHESIZE_512K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_ICACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_M  (CACHE_L1_ICACHE_CACHESIZE_1024K_V << CACHE_L1_ICACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_ICACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x1c)
+/** CACHE_L1_ICACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_M  (CACHE_L1_ICACHE_BLOCKSIZE_8_V << CACHE_L1_ICACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_ICACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_M  (CACHE_L1_ICACHE_BLOCKSIZE_16_V << CACHE_L1_ICACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_ICACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_M  (CACHE_L1_ICACHE_BLOCKSIZE_32_V << CACHE_L1_ICACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_ICACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_M  (CACHE_L1_ICACHE_BLOCKSIZE_64_V << CACHE_L1_ICACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_ICACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_M  (CACHE_L1_ICACHE_BLOCKSIZE_128_V << CACHE_L1_ICACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_ICACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_M  (CACHE_L1_ICACHE_BLOCKSIZE_256_V << CACHE_L1_ICACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_ICACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_DCACHE_CACHESIZE_CONF_REG register
+ *  L1 data Cache CacheSize mode configure register
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x20)
+/** CACHE_L1_DCACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L1_DCACHE_CACHESIZE_256_M  (CACHE_L1_DCACHE_CACHESIZE_256_V << CACHE_L1_DCACHE_CACHESIZE_256_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256_S  0
+/** CACHE_L1_DCACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L1_DCACHE_CACHESIZE_512_M  (CACHE_L1_DCACHE_CACHESIZE_512_V << CACHE_L1_DCACHE_CACHESIZE_512_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512_S  1
+/** CACHE_L1_DCACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L1_DCACHE_CACHESIZE_1K_M  (CACHE_L1_DCACHE_CACHESIZE_1K_V << CACHE_L1_DCACHE_CACHESIZE_1K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1K_S  2
+/** CACHE_L1_DCACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L1_DCACHE_CACHESIZE_2K_M  (CACHE_L1_DCACHE_CACHESIZE_2K_V << CACHE_L1_DCACHE_CACHESIZE_2K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_2K_S  3
+/** CACHE_L1_DCACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L1_DCACHE_CACHESIZE_4K_M  (CACHE_L1_DCACHE_CACHESIZE_4K_V << CACHE_L1_DCACHE_CACHESIZE_4K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_4K_S  4
+/** CACHE_L1_DCACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L1_DCACHE_CACHESIZE_8K_M  (CACHE_L1_DCACHE_CACHESIZE_8K_V << CACHE_L1_DCACHE_CACHESIZE_8K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_8K_S  5
+/** CACHE_L1_DCACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L1_DCACHE_CACHESIZE_16K_M  (CACHE_L1_DCACHE_CACHESIZE_16K_V << CACHE_L1_DCACHE_CACHESIZE_16K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_16K_S  6
+/** CACHE_L1_DCACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L1_DCACHE_CACHESIZE_32K_M  (CACHE_L1_DCACHE_CACHESIZE_32K_V << CACHE_L1_DCACHE_CACHESIZE_32K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_32K_S  7
+/** CACHE_L1_DCACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 1;
+ *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L1_DCACHE_CACHESIZE_64K_M  (CACHE_L1_DCACHE_CACHESIZE_64K_V << CACHE_L1_DCACHE_CACHESIZE_64K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_64K_S  8
+/** CACHE_L1_DCACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L1_DCACHE_CACHESIZE_128K_M  (CACHE_L1_DCACHE_CACHESIZE_128K_V << CACHE_L1_DCACHE_CACHESIZE_128K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_128K_S  9
+/** CACHE_L1_DCACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L1_DCACHE_CACHESIZE_256K_M  (CACHE_L1_DCACHE_CACHESIZE_256K_V << CACHE_L1_DCACHE_CACHESIZE_256K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_256K_S  10
+/** CACHE_L1_DCACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L1_DCACHE_CACHESIZE_512K_M  (CACHE_L1_DCACHE_CACHESIZE_512K_V << CACHE_L1_DCACHE_CACHESIZE_512K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_512K_S  11
+/** CACHE_L1_DCACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+ *  and all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_M  (CACHE_L1_DCACHE_CACHESIZE_1024K_V << CACHE_L1_DCACHE_CACHESIZE_1024K_S)
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L1_DCACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG register
+ *  L1 data Cache BlockSize mode configure register
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x24)
+/** CACHE_L1_DCACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_M  (CACHE_L1_DCACHE_BLOCKSIZE_8_V << CACHE_L1_DCACHE_BLOCKSIZE_8_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_8_S  0
+/** CACHE_L1_DCACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_M  (CACHE_L1_DCACHE_BLOCKSIZE_16_V << CACHE_L1_DCACHE_BLOCKSIZE_16_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_16_S  1
+/** CACHE_L1_DCACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_M  (CACHE_L1_DCACHE_BLOCKSIZE_32_V << CACHE_L1_DCACHE_BLOCKSIZE_32_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_32_S  2
+/** CACHE_L1_DCACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+ *  all other fields within this register is onehot.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_M  (CACHE_L1_DCACHE_BLOCKSIZE_64_V << CACHE_L1_DCACHE_BLOCKSIZE_64_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_64_S  3
+/** CACHE_L1_DCACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_M  (CACHE_L1_DCACHE_BLOCKSIZE_128_V << CACHE_L1_DCACHE_BLOCKSIZE_128_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_128_S  4
+/** CACHE_L1_DCACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_DCACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_M  (CACHE_L1_DCACHE_BLOCKSIZE_256_V << CACHE_L1_DCACHE_BLOCKSIZE_256_S)
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L1_DCACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x28)
+/** CACHE_L1_ICACHE0_WRAP : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the critical word first function.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_WRAP    (BIT(0))
+#define CACHE_L1_ICACHE0_WRAP_M  (CACHE_L1_ICACHE0_WRAP_V << CACHE_L1_ICACHE0_WRAP_S)
+#define CACHE_L1_ICACHE0_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE0_WRAP_S  0
+/** CACHE_L1_ICACHE1_WRAP : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the critical word first function.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_WRAP    (BIT(1))
+#define CACHE_L1_ICACHE1_WRAP_M  (CACHE_L1_ICACHE1_WRAP_V << CACHE_L1_ICACHE1_WRAP_S)
+#define CACHE_L1_ICACHE1_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE1_WRAP_S  1
+/** CACHE_L1_ICACHE2_WRAP : HRO; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_WRAP    (BIT(2))
+#define CACHE_L1_ICACHE2_WRAP_M  (CACHE_L1_ICACHE2_WRAP_V << CACHE_L1_ICACHE2_WRAP_S)
+#define CACHE_L1_ICACHE2_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE2_WRAP_S  2
+/** CACHE_L1_ICACHE3_WRAP : HRO; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_WRAP    (BIT(3))
+#define CACHE_L1_ICACHE3_WRAP_M  (CACHE_L1_ICACHE3_WRAP_V << CACHE_L1_ICACHE3_WRAP_S)
+#define CACHE_L1_ICACHE3_WRAP_V  0x00000001U
+#define CACHE_L1_ICACHE3_WRAP_S  3
+/** CACHE_L1_DCACHE_WRAP : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable the critical word first function.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_WRAP    (BIT(4))
+#define CACHE_L1_DCACHE_WRAP_M  (CACHE_L1_DCACHE_WRAP_V << CACHE_L1_DCACHE_WRAP_S)
+#define CACHE_L1_DCACHE_WRAP_V  0x00000001U
+#define CACHE_L1_DCACHE_WRAP_S  4
+
+/** CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG register
+ *  Cache wrap around control register
+ */
+#define CACHE_L1_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x2c)
+/** CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable early restart function.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS    (BIT(0))
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE0_MISS_DISABLE_ACCESS_S  0
+/** CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable early restart function.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS    (BIT(1))
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE1_MISS_DISABLE_ACCESS_S  1
+/** CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS    (BIT(2))
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE2_MISS_DISABLE_ACCESS_S  2
+/** CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS    (BIT(3))
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_M  (CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V << CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_ICACHE3_MISS_DISABLE_ACCESS_S  3
+/** CACHE_L1_CACHE_MISS_DISABLE_ACCESS : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable early restart function.
+ *  1: Enable
+ */
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS    (BIT(4))
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S)
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L1_CACHE_MISS_DISABLE_ACCESS_S  4
+
+/** CACHE_L1_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ */
+#define CACHE_L1_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x30)
+/** CACHE_L1_ICACHE0_FREEZE_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable freeze operation. It can be cleared by software.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_FREEZE_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_FREEZE_EN_M  (CACHE_L1_ICACHE0_FREEZE_EN_V << CACHE_L1_ICACHE0_FREEZE_EN_S)
+#define CACHE_L1_ICACHE0_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_EN_S  0
+/** CACHE_L1_ICACHE0_FREEZE_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configures the freeze mode.
+ *  1: Assert hit if a cache miss occurs
+ */
+#define CACHE_L1_ICACHE0_FREEZE_MODE    (BIT(1))
+#define CACHE_L1_ICACHE0_FREEZE_MODE_M  (CACHE_L1_ICACHE0_FREEZE_MODE_V << CACHE_L1_ICACHE0_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE0_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_MODE_S  1
+/** CACHE_L1_ICACHE0_FREEZE_DONE : RO; bitpos: [2]; default: 0;
+ *  Indicates whether the freeze operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE0_FREEZE_DONE    (BIT(2))
+#define CACHE_L1_ICACHE0_FREEZE_DONE_M  (CACHE_L1_ICACHE0_FREEZE_DONE_V << CACHE_L1_ICACHE0_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE0_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_FREEZE_DONE_S  2
+/** CACHE_L1_ICACHE1_FREEZE_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable freeze operation. It can be cleared by software.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_FREEZE_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_FREEZE_EN_M  (CACHE_L1_ICACHE1_FREEZE_EN_V << CACHE_L1_ICACHE1_FREEZE_EN_S)
+#define CACHE_L1_ICACHE1_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_EN_S  4
+/** CACHE_L1_ICACHE1_FREEZE_MODE : R/W; bitpos: [5]; default: 0;
+ *  Configures the freeze mode.
+ *  1: Assert hit if a cache miss occurs
+ */
+#define CACHE_L1_ICACHE1_FREEZE_MODE    (BIT(5))
+#define CACHE_L1_ICACHE1_FREEZE_MODE_M  (CACHE_L1_ICACHE1_FREEZE_MODE_V << CACHE_L1_ICACHE1_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE1_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_MODE_S  5
+/** CACHE_L1_ICACHE1_FREEZE_DONE : RO; bitpos: [6]; default: 0;
+ *  Indicates whether the freeze operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE1_FREEZE_DONE    (BIT(6))
+#define CACHE_L1_ICACHE1_FREEZE_DONE_M  (CACHE_L1_ICACHE1_FREEZE_DONE_V << CACHE_L1_ICACHE1_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE1_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_FREEZE_DONE_S  6
+/** CACHE_L1_ICACHE2_FREEZE_EN : HRO; bitpos: [8]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_FREEZE_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_FREEZE_EN_M  (CACHE_L1_ICACHE2_FREEZE_EN_V << CACHE_L1_ICACHE2_FREEZE_EN_S)
+#define CACHE_L1_ICACHE2_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_EN_S  8
+/** CACHE_L1_ICACHE2_FREEZE_MODE : HRO; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_FREEZE_MODE    (BIT(9))
+#define CACHE_L1_ICACHE2_FREEZE_MODE_M  (CACHE_L1_ICACHE2_FREEZE_MODE_V << CACHE_L1_ICACHE2_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE2_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_MODE_S  9
+/** CACHE_L1_ICACHE2_FREEZE_DONE : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_FREEZE_DONE    (BIT(10))
+#define CACHE_L1_ICACHE2_FREEZE_DONE_M  (CACHE_L1_ICACHE2_FREEZE_DONE_V << CACHE_L1_ICACHE2_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE2_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_FREEZE_DONE_S  10
+/** CACHE_L1_ICACHE3_FREEZE_EN : HRO; bitpos: [12]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_FREEZE_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_FREEZE_EN_M  (CACHE_L1_ICACHE3_FREEZE_EN_V << CACHE_L1_ICACHE3_FREEZE_EN_S)
+#define CACHE_L1_ICACHE3_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_EN_S  12
+/** CACHE_L1_ICACHE3_FREEZE_MODE : HRO; bitpos: [13]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_FREEZE_MODE    (BIT(13))
+#define CACHE_L1_ICACHE3_FREEZE_MODE_M  (CACHE_L1_ICACHE3_FREEZE_MODE_V << CACHE_L1_ICACHE3_FREEZE_MODE_S)
+#define CACHE_L1_ICACHE3_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_MODE_S  13
+/** CACHE_L1_ICACHE3_FREEZE_DONE : RO; bitpos: [14]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_FREEZE_DONE    (BIT(14))
+#define CACHE_L1_ICACHE3_FREEZE_DONE_M  (CACHE_L1_ICACHE3_FREEZE_DONE_V << CACHE_L1_ICACHE3_FREEZE_DONE_S)
+#define CACHE_L1_ICACHE3_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_FREEZE_DONE_S  14
+/** CACHE_L1_DCACHE_FREEZE_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether to enable freeze operation. It can be cleared by software.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_FREEZE_EN    (BIT(16))
+#define CACHE_L1_DCACHE_FREEZE_EN_M  (CACHE_L1_DCACHE_FREEZE_EN_V << CACHE_L1_DCACHE_FREEZE_EN_S)
+#define CACHE_L1_DCACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_EN_S  16
+/** CACHE_L1_DCACHE_FREEZE_MODE : R/W; bitpos: [17]; default: 0;
+ *  Configures the freeze mode.
+ *  1: Assert hit if a cache miss occurs
+ */
+#define CACHE_L1_DCACHE_FREEZE_MODE    (BIT(17))
+#define CACHE_L1_DCACHE_FREEZE_MODE_M  (CACHE_L1_DCACHE_FREEZE_MODE_V << CACHE_L1_DCACHE_FREEZE_MODE_S)
+#define CACHE_L1_DCACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_MODE_S  17
+/** CACHE_L1_DCACHE_FREEZE_DONE : RO; bitpos: [18]; default: 0;
+ *  Indicates whether the freeze operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_DCACHE_FREEZE_DONE    (BIT(18))
+#define CACHE_L1_DCACHE_FREEZE_DONE_M  (CACHE_L1_DCACHE_FREEZE_DONE_V << CACHE_L1_DCACHE_FREEZE_DONE_S)
+#define CACHE_L1_DCACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_FREEZE_DONE_S  18
+
+/** CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ */
+#define CACHE_L1_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x34)
+/** CACHE_L1_ICACHE0_DATA_MEM_RD_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_DATA_MEM_WR_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache data
+ *  memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_DATA_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_DATA_MEM_RD_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_DATA_MEM_WR_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache data
+ *  memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_DATA_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_DATA_MEM_RD_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_DATA_MEM_WR_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_DATA_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_DATA_MEM_RD_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V << CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_DATA_MEM_WR_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_M  (CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V << CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_DATA_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_DATA_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_M  (CACHE_L1_DCACHE_DATA_MEM_RD_EN_V << CACHE_L1_DCACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_DATA_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache data
+ *  memory.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_M  (CACHE_L1_DCACHE_DATA_MEM_WR_EN_V << CACHE_L1_DCACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_DATA_MEM_WR_EN_S  17
+
+/** CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ */
+#define CACHE_L1_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x38)
+/** CACHE_L1_ICACHE0_TAG_MEM_RD_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_RD_EN_S  0
+/** CACHE_L1_ICACHE0_TAG_MEM_WR_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_MEM_WR_EN_S  1
+/** CACHE_L1_ICACHE1_TAG_MEM_RD_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN    (BIT(4))
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_RD_EN_S  4
+/** CACHE_L1_ICACHE1_TAG_MEM_WR_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN    (BIT(5))
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_MEM_WR_EN_S  5
+/** CACHE_L1_ICACHE2_TAG_MEM_RD_EN : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN    (BIT(8))
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_RD_EN_S  8
+/** CACHE_L1_ICACHE2_TAG_MEM_WR_EN : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN    (BIT(9))
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_MEM_WR_EN_S  9
+/** CACHE_L1_ICACHE3_TAG_MEM_RD_EN : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN    (BIT(12))
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V << CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_RD_EN_S  12
+/** CACHE_L1_ICACHE3_TAG_MEM_WR_EN : R/W; bitpos: [13]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN    (BIT(13))
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_M  (CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V << CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S)
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_MEM_WR_EN_S  13
+/** CACHE_L1_DCACHE_TAG_MEM_RD_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN    (BIT(16))
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_M  (CACHE_L1_DCACHE_TAG_MEM_RD_EN_V << CACHE_L1_DCACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_RD_EN_S  16
+/** CACHE_L1_DCACHE_TAG_MEM_WR_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN    (BIT(17))
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_M  (CACHE_L1_DCACHE_TAG_MEM_WR_EN_V << CACHE_L1_DCACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_MEM_WR_EN_S  17
+
+/** CACHE_L1_ICACHE0_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x3c)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 0 of icache.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 1 of icache.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE0_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l1 icache0 prelock.
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_M  (CACHE_L1_ICACHE0_PRELOCK_RGID_V << CACHE_L1_ICACHE0_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x40)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section of prelock on L1-ICache0, which
+ *  should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x44)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L1-ICache0, which
+ *  should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x48)
+/** CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Configures the size of the first section of prelock on L1-ICache0, which should be
+ *  used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Configures the size of the second section of prelock on L1-ICache0, which should be
+ *  used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE1_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x4c)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 0 of icache.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 1 of icache.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE1_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l1 icache1 prelock.
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_M  (CACHE_L1_ICACHE1_PRELOCK_RGID_V << CACHE_L1_ICACHE1_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x50)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are used to configure the start address of the first section of prelock
+ *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x54)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L1-ICache1, which
+ *  should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x58)
+/** CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Configures the size of the first section of prelock on L1-ICache1, which should be
+ *  used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Configures the size of the second section of prelock on L1-ICache1, which should be
+ *  used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE2_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 2 prelock configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x5c)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  Configures the first section of prelock function on L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  Configures the second section of prelock function on L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE2_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l1 icache2 prelock.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_M  (CACHE_L1_ICACHE2_PRELOCK_RGID_V << CACHE_L1_ICACHE2_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x60)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section of prelock on L1-ICache2, which
+ *  should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x64)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L1-ICache2, which
+ *  should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 2 prelock section size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x68)
+/** CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Configures the size of the first section of prelock on L1-ICache2, which should be
+ *  used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Configures the size of the second section of prelock on L1-ICache2, which should be
+ *  used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_ICACHE3_PRELOCK_CONF_REG register
+ *  L1 instruction Cache 3 prelock configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x6c)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  Configures the first section of prelock function on L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  Configures the second section of prelock function on L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_ICACHE3_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l1 icache3 prelock.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_M  (CACHE_L1_ICACHE3_PRELOCK_RGID_V << CACHE_L1_ICACHE3_PRELOCK_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOCK_RGID_S  2
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x70)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section of prelock on L1-ICache3, which
+ *  should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x74)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L1-ICache3, which
+ *  should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG register
+ *  L1 instruction Cache 3 prelock section size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x78)
+/** CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE : HRO; bitpos: [13:0]; default: 16383;
+ *  Configures the size of the first section of prelock on L1-ICache3, which should be
+ *  used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE : HRO; bitpos: [29:16]; default: 16383;
+ *  Configures the size of the second section of prelock on L1-ICache3, which should be
+ *  used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_M  (CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V << CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L1_DCACHE_PRELOCK_CONF_REG register
+ *  L1 data Cache prelock configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x7c)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 0 of dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable the prelocking function in Section 1 of dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V << CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L1_DCACHE_PRELOCK_RGID : R/W; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l1 dcache prelock.
+ */
+#define CACHE_L1_DCACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_M  (CACHE_L1_DCACHE_PRELOCK_RGID_V << CACHE_L1_DCACHE_PRELOCK_RGID_S)
+#define CACHE_L1_DCACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L1 data Cache prelock section0 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x80)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section of prelock on L1-DCache, which
+ *  should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L1 data Cache prelock section1 address configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x84)
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L1-DCache, which
+ *  should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V << CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG register
+ *  L1 data Cache prelock section size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x88)
+/** CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [13:0]; default: 16383;
+ *  Configures the size of the first section of prelock on L1-DCache, which should be
+ *  used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [29:16]; default: 16383;
+ *  Configures the size of the second section of prelock on L1-DCache, which should be
+ *  used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V << CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_LOCK_CTRL_REG register
+ *  Lock-class (manual lock) operation control register
+ */
+#define CACHE_LOCK_CTRL_REG (DR_REG_CACHE_BASE + 0x8c)
+/** CACHE_LOCK_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to enable lock operation. It will be cleared by hardware after
+ *  the locking operation is done.
+ *  1: Enable
+ */
+#define CACHE_LOCK_ENA    (BIT(0))
+#define CACHE_LOCK_ENA_M  (CACHE_LOCK_ENA_V << CACHE_LOCK_ENA_S)
+#define CACHE_LOCK_ENA_V  0x00000001U
+#define CACHE_LOCK_ENA_S  0
+/** CACHE_UNLOCK_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  Configures whether to enable unlock operation. It will be cleared by hardware after
+ *  the unlocking operation is done.
+ *  1: Enable
+ */
+#define CACHE_UNLOCK_ENA    (BIT(1))
+#define CACHE_UNLOCK_ENA_M  (CACHE_UNLOCK_ENA_V << CACHE_UNLOCK_ENA_S)
+#define CACHE_UNLOCK_ENA_V  0x00000001U
+#define CACHE_UNLOCK_ENA_S  1
+/** CACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ *  Indicates whether the unlocking or the locking operation has finished.
+ *  1: Finished
+ */
+#define CACHE_LOCK_DONE    (BIT(2))
+#define CACHE_LOCK_DONE_M  (CACHE_LOCK_DONE_V << CACHE_LOCK_DONE_S)
+#define CACHE_LOCK_DONE_V  0x00000001U
+#define CACHE_LOCK_DONE_S  2
+/** CACHE_LOCK_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  Configures the gid of cache lock/unlock.
+ */
+#define CACHE_LOCK_RGID    0x0000000FU
+#define CACHE_LOCK_RGID_M  (CACHE_LOCK_RGID_V << CACHE_LOCK_RGID_S)
+#define CACHE_LOCK_RGID_V  0x0000000FU
+#define CACHE_LOCK_RGID_S  3
+
+/** CACHE_LOCK_MAP_REG register
+ *  Lock (manual lock) map configure register
+ */
+#define CACHE_LOCK_MAP_REG (DR_REG_CACHE_BASE + 0x90)
+/** CACHE_LOCK_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures caches in the two-level cache structure will apply this lock/unlock
+ *  operation.
+ *  Other bits: Reserved
+ */
+#define CACHE_LOCK_MAP    0x0000003FU
+#define CACHE_LOCK_MAP_M  (CACHE_LOCK_MAP_V << CACHE_LOCK_MAP_S)
+#define CACHE_LOCK_MAP_V  0x0000003FU
+#define CACHE_LOCK_MAP_S  0
+
+/** CACHE_LOCK_ADDR_REG register
+ *  Lock (manual lock) address configure register
+ */
+#define CACHE_LOCK_ADDR_REG (DR_REG_CACHE_BASE + 0x94)
+/** CACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the lock/unlock operation, which should be used
+ *  together with CACHE_LOCK_SIZE_REG
+ */
+#define CACHE_LOCK_ADDR    0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_M  (CACHE_LOCK_ADDR_V << CACHE_LOCK_ADDR_S)
+#define CACHE_LOCK_ADDR_V  0xFFFFFFFFU
+#define CACHE_LOCK_ADDR_S  0
+
+/** CACHE_LOCK_SIZE_REG register
+ *  Lock (manual lock) size configure register
+ */
+#define CACHE_LOCK_SIZE_REG (DR_REG_CACHE_BASE + 0x98)
+/** CACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Configures the size of the lock/unlock operation, which should be used together
+ *  with CACHE_LOCK_ADDR_REG
+ */
+#define CACHE_LOCK_SIZE    0x0000FFFFU
+#define CACHE_LOCK_SIZE_M  (CACHE_LOCK_SIZE_V << CACHE_LOCK_SIZE_S)
+#define CACHE_LOCK_SIZE_V  0x0000FFFFU
+#define CACHE_LOCK_SIZE_S  0
+
+/** CACHE_SYNC_CTRL_REG register
+ *  Sync-class operation control register
+ */
+#define CACHE_SYNC_CTRL_REG (DR_REG_CACHE_BASE + 0x9c)
+/** CACHE_INVALIDATE_ENA : R/W/SC; bitpos: [0]; default: 1;
+ *  Configures whether to enable the invalidation operation. Hardware will clear it
+ *  once the operation has finished.
+ *  Please note that this field, along with the other fields (CLEAN_ENA, WRITEBACK_ENA,
+ *  WRITEBACK_INVALIDATE_ENA), is mutually exclusive. In other words, only one of these
+ *  fields can be set to 1 at any given time.
+ */
+#define CACHE_INVALIDATE_ENA    (BIT(0))
+#define CACHE_INVALIDATE_ENA_M  (CACHE_INVALIDATE_ENA_V << CACHE_INVALIDATE_ENA_S)
+#define CACHE_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_INVALIDATE_ENA_S  0
+/** CACHE_CLEAN_ENA : R/W/SC; bitpos: [1]; default: 0;
+ *  Configures whether to enable the clean operation. Hardware will clear it once the
+ *  operation has finished.
+ *  1: Enable
+ */
+#define CACHE_CLEAN_ENA    (BIT(1))
+#define CACHE_CLEAN_ENA_M  (CACHE_CLEAN_ENA_V << CACHE_CLEAN_ENA_S)
+#define CACHE_CLEAN_ENA_V  0x00000001U
+#define CACHE_CLEAN_ENA_S  1
+/** CACHE_WRITEBACK_ENA : R/W/SC; bitpos: [2]; default: 0;
+ *  Configures whether to enable the write-back operation. Hardware will clear it once
+ *  the operation has finished.
+ *  1: Enable
+ */
+#define CACHE_WRITEBACK_ENA    (BIT(2))
+#define CACHE_WRITEBACK_ENA_M  (CACHE_WRITEBACK_ENA_V << CACHE_WRITEBACK_ENA_S)
+#define CACHE_WRITEBACK_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_ENA_S  2
+/** CACHE_WRITEBACK_INVALIDATE_ENA : R/W/SC; bitpos: [3]; default: 0;
+ *  Configures whether to enable the write-back invalidation operation. Hardware will
+ *  clear it once the operation has finished.
+ *  1: Enable
+ */
+#define CACHE_WRITEBACK_INVALIDATE_ENA    (BIT(3))
+#define CACHE_WRITEBACK_INVALIDATE_ENA_M  (CACHE_WRITEBACK_INVALIDATE_ENA_V << CACHE_WRITEBACK_INVALIDATE_ENA_S)
+#define CACHE_WRITEBACK_INVALIDATE_ENA_V  0x00000001U
+#define CACHE_WRITEBACK_INVALIDATE_ENA_S  3
+/** CACHE_SYNC_DONE : RO; bitpos: [4]; default: 0;
+ *  Indicates whether the synchronization operation has finished.
+ *  1: Finished
+ */
+#define CACHE_SYNC_DONE    (BIT(4))
+#define CACHE_SYNC_DONE_M  (CACHE_SYNC_DONE_V << CACHE_SYNC_DONE_S)
+#define CACHE_SYNC_DONE_V  0x00000001U
+#define CACHE_SYNC_DONE_S  4
+/** CACHE_SYNC_RGID : R/W; bitpos: [8:5]; default: 0;
+ *  Configures the gid of cache sync operation (invalidate, clean, writeback,
+ *  writeback_invalidate)
+ */
+#define CACHE_SYNC_RGID    0x0000000FU
+#define CACHE_SYNC_RGID_M  (CACHE_SYNC_RGID_V << CACHE_SYNC_RGID_S)
+#define CACHE_SYNC_RGID_V  0x0000000FU
+#define CACHE_SYNC_RGID_S  5
+
+/** CACHE_SYNC_MAP_REG register
+ *  Sync map configure register
+ */
+#define CACHE_SYNC_MAP_REG (DR_REG_CACHE_BASE + 0xa0)
+/** CACHE_SYNC_MAP : R/W; bitpos: [5:0]; default: 31;
+ *  Configures which cache to perform the locking or the unlocking operation.
+ *  Other bits: Reserved
+ */
+#define CACHE_SYNC_MAP    0x0000003FU
+#define CACHE_SYNC_MAP_M  (CACHE_SYNC_MAP_V << CACHE_SYNC_MAP_S)
+#define CACHE_SYNC_MAP_V  0x0000003FU
+#define CACHE_SYNC_MAP_S  0
+
+/** CACHE_SYNC_ADDR_REG register
+ *  Sync address configure register
+ */
+#define CACHE_SYNC_ADDR_REG (DR_REG_CACHE_BASE + 0xa4)
+/** CACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the sync operation, which should be used together
+ *  with CACHE_SYNC_SIZE_REG
+ */
+#define CACHE_SYNC_ADDR    0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_M  (CACHE_SYNC_ADDR_V << CACHE_SYNC_ADDR_S)
+#define CACHE_SYNC_ADDR_V  0xFFFFFFFFU
+#define CACHE_SYNC_ADDR_S  0
+
+/** CACHE_SYNC_SIZE_REG register
+ *  Sync size configure register
+ */
+#define CACHE_SYNC_SIZE_REG (DR_REG_CACHE_BASE + 0xa8)
+/** CACHE_SYNC_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the sync operation, which should be used together with
+ *  CACHE_SYNC_ADDR_REG
+ */
+#define CACHE_SYNC_SIZE    0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_M  (CACHE_SYNC_SIZE_V << CACHE_SYNC_SIZE_S)
+#define CACHE_SYNC_SIZE_V  0x0FFFFFFFU
+#define CACHE_SYNC_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xac)
+/** CACHE_L1_ICACHE0_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to enable the preloading operation in icache0. Hardware will
+ *  clear it once the operation has finished.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_M  (CACHE_L1_ICACHE0_PRELOAD_ENA_V << CACHE_L1_ICACHE0_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Represents whether the preloading operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_M  (CACHE_L1_ICACHE0_PRELOAD_DONE_V << CACHE_L1_ICACHE0_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the preloading operation.
+ *  1: Descending
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_M  (CACHE_L1_ICACHE0_PRELOAD_ORDER_V << CACHE_L1_ICACHE0_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l1 icache0 preload.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_M  (CACHE_L1_ICACHE0_PRELOAD_RGID_V << CACHE_L1_ICACHE0_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE0_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_M  (CACHE_L1_ICACHE0_PRELOAD_MODE_V << CACHE_L1_ICACHE0_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR_REG register
+ *  icache0 preload address configuration register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xb0)
+/** CACHE_L1_ICACHE0_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L1-ICache0, which should be used
+ *  together with L1_ICACHE0_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_M  (CACHE_L1_ICACHE0_PRELOAD_ADDR_V << CACHE_L1_ICACHE0_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xb4)
+/** CACHE_L1_ICACHE0_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Configures the size of the first section of prelock on L1-ICache0, which should be
+ *  used together with L1_ICACHE0_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_M  (CACHE_L1_ICACHE0_PRELOAD_SIZE_V << CACHE_L1_ICACHE0_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE0_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xb8)
+/** CACHE_L1_ICACHE1_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to enable the preloading operation in icache1. Hardware will
+ *  clear it once the operation has finished.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_M  (CACHE_L1_ICACHE1_PRELOAD_ENA_V << CACHE_L1_ICACHE1_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Represents whether the preloading operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_M  (CACHE_L1_ICACHE1_PRELOAD_DONE_V << CACHE_L1_ICACHE1_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the preloading operation.
+ *  1: Descending
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_M  (CACHE_L1_ICACHE1_PRELOAD_ORDER_V << CACHE_L1_ICACHE1_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l1 icache1 preload.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_M  (CACHE_L1_ICACHE1_PRELOAD_RGID_V << CACHE_L1_ICACHE1_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE1_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_M  (CACHE_L1_ICACHE1_PRELOAD_MODE_V << CACHE_L1_ICACHE1_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR_REG register
+ *  icache1 preload address configuration register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xbc)
+/** CACHE_L1_ICACHE1_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L1-ICache1, which should be used
+ *  together with L1_ICACHE1_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_M  (CACHE_L1_ICACHE1_PRELOAD_ADDR_V << CACHE_L1_ICACHE1_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xc0)
+/** CACHE_L1_ICACHE1_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Configures the size of the first section of prelock on L1-ICache1, which should be
+ *  used together with L1_ICACHE1_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_M  (CACHE_L1_ICACHE1_PRELOAD_SIZE_V << CACHE_L1_ICACHE1_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE1_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 2 preload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xc4)
+/** CACHE_L1_ICACHE2_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures preload operation on L1-ICache2. It will be cleared by hardware
+ *  automatically after preload operation is done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_M  (CACHE_L1_ICACHE2_PRELOAD_ENA_V << CACHE_L1_ICACHE2_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_M  (CACHE_L1_ICACHE2_PRELOAD_DONE_V << CACHE_L1_ICACHE2_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of preload operation. 0: ascending, 1: descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_M  (CACHE_L1_ICACHE2_PRELOAD_ORDER_V << CACHE_L1_ICACHE2_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l1 icache2 preload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_M  (CACHE_L1_ICACHE2_PRELOAD_RGID_V << CACHE_L1_ICACHE2_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE2_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  Configures the mode of l1 icache2 preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_M  (CACHE_L1_ICACHE2_PRELOAD_MODE_V << CACHE_L1_ICACHE2_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 2 preload address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xc8)
+/** CACHE_L1_ICACHE2_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L1-ICache2, which should be used
+ *  together with L1_ICACHE2_PRELOAD_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_M  (CACHE_L1_ICACHE2_PRELOAD_ADDR_V << CACHE_L1_ICACHE2_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 2 preload size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xcc)
+/** CACHE_L1_ICACHE2_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Configures the size of the first section of prelock on L1-ICache2, which should be
+ *  used together with L1_ICACHE2_PRELOAD_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_M  (CACHE_L1_ICACHE2_PRELOAD_SIZE_V << CACHE_L1_ICACHE2_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE2_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_CTRL_REG register
+ *  L1 instruction Cache 3 preload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xd0)
+/** CACHE_L1_ICACHE3_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures preload operation on L1-ICache3. It will be cleared by hardware
+ *  automatically after preload operation is done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_M  (CACHE_L1_ICACHE3_PRELOAD_ENA_V << CACHE_L1_ICACHE3_PRELOAD_ENA_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_M  (CACHE_L1_ICACHE3_PRELOAD_DONE_V << CACHE_L1_ICACHE3_PRELOAD_DONE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of preload operation. 0: ascending, 1: descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_M  (CACHE_L1_ICACHE3_PRELOAD_ORDER_V << CACHE_L1_ICACHE3_PRELOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l1 icache3 preload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_M  (CACHE_L1_ICACHE3_PRELOAD_RGID_V << CACHE_L1_ICACHE3_PRELOAD_RGID_S)
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_PRELOAD_RGID_S  3
+/** CACHE_L1_ICACHE3_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  Configures the mode of l1 icache3 preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_M  (CACHE_L1_ICACHE3_PRELOAD_MODE_V << CACHE_L1_ICACHE3_PRELOAD_MODE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_PRELOAD_MODE_S  7
+
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR_REG register
+ *  L1 instruction Cache 3 preload address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xd4)
+/** CACHE_L1_ICACHE3_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L1-ICache3, which should be used
+ *  together with L1_ICACHE3_PRELOAD_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_M  (CACHE_L1_ICACHE3_PRELOAD_ADDR_V << CACHE_L1_ICACHE3_PRELOAD_ADDR_S)
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE_REG register
+ *  L1 instruction Cache 3 preload size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xd8)
+/** CACHE_L1_ICACHE3_PRELOAD_SIZE : HRO; bitpos: [13:0]; default: 0;
+ *  Configures the size of the first section of prelock on L1-ICache3, which should be
+ *  used together with L1_ICACHE3_PRELOAD_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_M  (CACHE_L1_ICACHE3_PRELOAD_SIZE_V << CACHE_L1_ICACHE3_PRELOAD_SIZE_S)
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_ICACHE3_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_CTRL_REG register
+ *  L1 data Cache  preload-operation control register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xdc)
+/** CACHE_L1_DCACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to enable the preloading operation in dcache. Hardware will
+ *  clear it once the operation has finished.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_PRELOAD_ENA_M  (CACHE_L1_DCACHE_PRELOAD_ENA_V << CACHE_L1_DCACHE_PRELOAD_ENA_S)
+#define CACHE_L1_DCACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ENA_S  0
+/** CACHE_L1_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Represents whether the preloading operation has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_DCACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_PRELOAD_DONE_M  (CACHE_L1_DCACHE_PRELOAD_DONE_V << CACHE_L1_DCACHE_PRELOAD_DONE_S)
+#define CACHE_L1_DCACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_DONE_S  1
+/** CACHE_L1_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the preloading operation.
+ *  1: Descending
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_M  (CACHE_L1_DCACHE_PRELOAD_ORDER_V << CACHE_L1_DCACHE_PRELOAD_ORDER_S)
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_PRELOAD_RGID : R/W; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l1 dcache preload.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_M  (CACHE_L1_DCACHE_PRELOAD_RGID_V << CACHE_L1_DCACHE_PRELOAD_RGID_S)
+#define CACHE_L1_DCACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_PRELOAD_RGID_S  3
+/** CACHE_L1_DCACHE_PRELOAD_MODE : R/W; bitpos: [7]; default: 0;
+ *  Configures the mode of l1 dcache preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ */
+#define CACHE_L1_DCACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L1_DCACHE_PRELOAD_MODE_M  (CACHE_L1_DCACHE_PRELOAD_MODE_V << CACHE_L1_DCACHE_PRELOAD_MODE_S)
+#define CACHE_L1_DCACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L1_DCACHE_PRELOAD_ADDR_REG register
+ *  dcache preload address configuration register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0xe0)
+/** CACHE_L1_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L1-DCache, which should be used together
+ *  with L1_DCACHE_PRELOAD_SIZE_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_M  (CACHE_L1_DCACHE_PRELOAD_ADDR_V << CACHE_L1_DCACHE_PRELOAD_ADDR_S)
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L1_DCACHE_PRELOAD_SIZE_REG register
+ *  L1 data Cache  preload size configure register
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0xe4)
+/** CACHE_L1_DCACHE_PRELOAD_SIZE : R/W; bitpos: [13:0]; default: 0;
+ *  Configures the size of the first section of prelock on L1-DCache, which should be
+ *  used together with L1_DCACHE_PRELOAD_ADDR_REG
+ */
+#define CACHE_L1_DCACHE_PRELOAD_SIZE    0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_M  (CACHE_L1_DCACHE_PRELOAD_SIZE_V << CACHE_L1_DCACHE_PRELOAD_SIZE_S)
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_V  0x00003FFFU
+#define CACHE_L1_DCACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xe8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the autoloading operation in icache0.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE0_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Indicates whether the autoloading operation in icache0 has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE0_AUTOLOAD_DONE_V << CACHE_L1_ICACHE0_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE0_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the autoloading operation in icache0.
+ *  1: Descending
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the trigger mode of the autoloading operation in icache0.
+ *  2: Triggered by cache miss or hit
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to enable Section 0 for the autoloading operation in icache0.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to enable Section 1 for the autoloading operation in icache0.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE0_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  Configures the gid of l1 icache0 autoload.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE0_AUTOLOAD_RGID_V << CACHE_L1_ICACHE0_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE0_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0xec)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0xf0)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L1-ICache0. Note
+ *  that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0xf4)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0xf8)
+/** CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the second section for autoload operation on L1-ICache0.
+ *  Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE0_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0xfc)
+/** CACHE_L1_ICACHE1_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the autoloading operation in icache1.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE1_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Indicates whether the autoloading operation in icache1 has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE1_AUTOLOAD_DONE_V << CACHE_L1_ICACHE1_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE1_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the autoloading operation in icache1.
+ *  1: Descending
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the trigger mode of the autoloading operation in icache1.
+ *  2: Triggered by cache miss or hit
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to enable Section 0 for the autoloading operation in icache1.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to enable Section 1 for the autoloading operation in icache1.
+ *  1: Enable
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE1_AUTOLOAD_RGID : R/W; bitpos: [13:10]; default: 0;
+ *  Configures the gid of l1 icache1 autoload.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE1_AUTOLOAD_RGID_V << CACHE_L1_ICACHE1_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE1_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x100)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x104)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L1-ICache1. Note
+ *  that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x108)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x10c)
+/** CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the second section for autoload operation on L1-ICache1.
+ *  Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE1_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 2 autoload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x110)
+/** CACHE_L1_ICACHE2_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  Configures and disable autoload operation on L1-ICache2.  1: enable, 0: disable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE2_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+ *  not. 0: not finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE2_AUTOLOAD_DONE_V << CACHE_L1_ICACHE2_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE2_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of autoload operation on L1-ICache2. 0: ascending. 1:
+ *  descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  Configures the first section for autoload operation on L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  Configures the second section for autoload operation on L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE2_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  Configures the gid of l1 icache2 autoload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE2_AUTOLOAD_RGID_V << CACHE_L1_ICACHE2_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE2_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x114)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x118)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L1-ICache2. Note
+ *  that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x11c)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x120)
+/** CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the second section for autoload operation on L1-ICache2.
+ *  Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE2_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG register
+ *  L1 instruction Cache 3 autoload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x124)
+/** CACHE_L1_ICACHE3_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  Configures and disable autoload operation on L1-ICache3.  1: enable, 0: disable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ENA_S  0
+/** CACHE_L1_ICACHE3_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+ *  not. 0: not finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_M  (CACHE_L1_ICACHE3_AUTOLOAD_DONE_V << CACHE_L1_ICACHE3_AUTOLOAD_DONE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_DONE_S  1
+/** CACHE_L1_ICACHE3_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of autoload operation on L1-ICache3. 0: ascending. 1:
+ *  descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_M  (CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V << CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+ *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  Configures the first section for autoload operation on L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  Configures the second section for autoload operation on L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_ICACHE3_AUTOLOAD_RGID : HRO; bitpos: [13:10]; default: 0;
+ *  Configures the gid of l1 icache3 autoload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_M  (CACHE_L1_ICACHE3_AUTOLOAD_RGID_V << CACHE_L1_ICACHE3_AUTOLOAD_RGID_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_ICACHE3_AUTOLOAD_RGID_S  10
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x128)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x12c)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L1-ICache3. Note
+ *  that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and
+ *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x130)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE
+ *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x134)
+/** CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_ICACHE3_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG register
+ *  L1 data Cache autoload-operation control register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x138)
+/** CACHE_L1_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable the autoloading operation in dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L1_DCACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  Indicates whether the autoloading operation in dcache has finished.
+ *  1: Finished
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_M  (CACHE_L1_DCACHE_AUTOLOAD_DONE_V << CACHE_L1_DCACHE_AUTOLOAD_DONE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L1_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ *  Configures the direction of the autoloading operation in dcache.
+ *  1: Descending
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_M  (CACHE_L1_DCACHE_AUTOLOAD_ORDER_V << CACHE_L1_DCACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE : R/W; bitpos: [4:3]; default: 0;
+ *  Configures the trigger mode of the autoloading operation in dcache.
+ *  2: Triggered by cache miss or hit
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L1_DCACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to enable Section 0 for the autoloading operation in dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0;
+ *  Configures whether to enable Section 1 for the autoloading operation in dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA : R/W; bitpos: [10]; default: 0;
+ *  Configures whether to enable Section 2 for the autoloading operation in dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA : R/W; bitpos: [11]; default: 0;
+ *  Configures whether to enable Section 3 for the autoloading operation in dcache.
+ *  1: Enable
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L1_DCACHE_AUTOLOAD_RGID : R/W; bitpos: [15:12]; default: 0;
+ *  Configures the gid of l1 dcache autoload.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_M  (CACHE_L1_DCACHE_AUTOLOAD_RGID_V << CACHE_L1_DCACHE_AUTOLOAD_RGID_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L1_DCACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x13c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE
+ *  and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x140)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L1-DCache. Note
+ *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and
+ *  L1_DCACHE_AUTOLOAD_SCT0_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x144)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE
+ *  and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x148)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the second section for autoload operation on L1-DCache. Note
+ *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and
+ *  L1_DCACHE_AUTOLOAD_SCT1_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x14c)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the third section for autoload operation on
+ *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE
+ *  and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x150)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the third section for autoload operation on L1-DCache. Note
+ *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and
+ *  L1_DCACHE_AUTOLOAD_SCT2_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x154)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the fourth section for autoload operation on
+ *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE
+ *  and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x158)
+/** CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE : R/W; bitpos: [27:0]; default: 0;
+ *  Configures the size of the fourth section for autoload operation on L1-DCache. Note
+ *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and
+ *  L1_DCACHE_AUTOLOAD_SCT3_ENA.
+ */
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L1_DCACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x15c)
+/** CACHE_L1_IBUS0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L1-ICache0 due to
+ *  bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ENA_M  (CACHE_L1_IBUS0_OVF_INT_ENA_V << CACHE_L1_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ENA_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L1-ICache1 due to
+ *  bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ENA_M  (CACHE_L1_IBUS1_OVF_INT_ENA_V << CACHE_L1_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ENA_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ENA_M  (CACHE_L1_IBUS2_OVF_INT_ENA_V << CACHE_L1_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ENA_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ENA_M  (CACHE_L1_IBUS3_OVF_INT_ENA_V << CACHE_L1_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ENA_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L1-DCache due to
+ *  bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ENA_M  (CACHE_L1_DBUS0_OVF_INT_ENA_V << CACHE_L1_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ENA_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L1-DCache due to
+ *  bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ENA_M  (CACHE_L1_DBUS1_OVF_INT_ENA_V << CACHE_L1_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ENA_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ENA_M  (CACHE_L1_DBUS2_OVF_INT_ENA_V << CACHE_L1_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ENA_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ENA_M  (CACHE_L1_DBUS3_OVF_INT_ENA_V << CACHE_L1_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L1_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ENA_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x160)
+/** CACHE_L1_IBUS0_OVF_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+ *  to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_CLR    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_CLR_M  (CACHE_L1_IBUS0_OVF_INT_CLR_V << CACHE_L1_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_CLR_S  0
+/** CACHE_L1_IBUS1_OVF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+ *  to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_CLR    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_CLR_M  (CACHE_L1_IBUS1_OVF_INT_CLR_V << CACHE_L1_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_CLR_S  1
+/** CACHE_L1_IBUS2_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_CLR    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_CLR_M  (CACHE_L1_IBUS2_OVF_INT_CLR_V << CACHE_L1_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_CLR_S  2
+/** CACHE_L1_IBUS3_OVF_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_CLR    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_CLR_M  (CACHE_L1_IBUS3_OVF_INT_CLR_V << CACHE_L1_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_CLR_S  3
+/** CACHE_L1_DBUS0_OVF_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_CLR    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_CLR_M  (CACHE_L1_DBUS0_OVF_INT_CLR_V << CACHE_L1_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_CLR_S  4
+/** CACHE_L1_DBUS1_OVF_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+ *  to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_CLR    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_CLR_M  (CACHE_L1_DBUS1_OVF_INT_CLR_V << CACHE_L1_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_CLR_S  5
+/** CACHE_L1_DBUS2_OVF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_CLR    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_CLR_M  (CACHE_L1_DBUS2_OVF_INT_CLR_V << CACHE_L1_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_CLR_S  6
+/** CACHE_L1_DBUS3_OVF_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_CLR    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_CLR_M  (CACHE_L1_DBUS3_OVF_INT_CLR_V << CACHE_L1_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L1_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_CLR_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x164)
+/** CACHE_L1_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+ *  due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_RAW    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_RAW_M  (CACHE_L1_IBUS0_OVF_INT_RAW_V << CACHE_L1_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_RAW_S  0
+/** CACHE_L1_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+ *  due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_RAW    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_RAW_M  (CACHE_L1_IBUS1_OVF_INT_RAW_V << CACHE_L1_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_RAW_S  1
+/** CACHE_L1_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+ *  due to bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_OVF_INT_RAW    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_RAW_M  (CACHE_L1_IBUS2_OVF_INT_RAW_V << CACHE_L1_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_RAW_S  2
+/** CACHE_L1_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+ *  due to bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_OVF_INT_RAW    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_RAW_M  (CACHE_L1_IBUS3_OVF_INT_RAW_V << CACHE_L1_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_RAW_S  3
+/** CACHE_L1_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_RAW    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_RAW_M  (CACHE_L1_DBUS0_OVF_INT_RAW_V << CACHE_L1_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_RAW_S  4
+/** CACHE_L1_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_RAW    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_RAW_M  (CACHE_L1_DBUS1_OVF_INT_RAW_V << CACHE_L1_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_RAW_S  5
+/** CACHE_L1_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_OVF_INT_RAW    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_RAW_M  (CACHE_L1_DBUS2_OVF_INT_RAW_V << CACHE_L1_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_RAW_S  6
+/** CACHE_L1_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+ *  due to bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_OVF_INT_RAW    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_RAW_M  (CACHE_L1_DBUS3_OVF_INT_RAW_V << CACHE_L1_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L1_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_RAW_S  7
+
+/** CACHE_L1_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x168)
+/** CACHE_L1_IBUS0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache0 due to bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_OVF_INT_ST    (BIT(0))
+#define CACHE_L1_IBUS0_OVF_INT_ST_M  (CACHE_L1_IBUS0_OVF_INT_ST_V << CACHE_L1_IBUS0_OVF_INT_ST_S)
+#define CACHE_L1_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS0_OVF_INT_ST_S  0
+/** CACHE_L1_IBUS1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-ICache1 due to bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_OVF_INT_ST    (BIT(1))
+#define CACHE_L1_IBUS1_OVF_INT_ST_M  (CACHE_L1_IBUS1_OVF_INT_ST_V << CACHE_L1_IBUS1_OVF_INT_ST_S)
+#define CACHE_L1_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS1_OVF_INT_ST_S  1
+/** CACHE_L1_IBUS2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_OVF_INT_ST    (BIT(2))
+#define CACHE_L1_IBUS2_OVF_INT_ST_M  (CACHE_L1_IBUS2_OVF_INT_ST_V << CACHE_L1_IBUS2_OVF_INT_ST_S)
+#define CACHE_L1_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS2_OVF_INT_ST_S  2
+/** CACHE_L1_IBUS3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_OVF_INT_ST    (BIT(3))
+#define CACHE_L1_IBUS3_OVF_INT_ST_M  (CACHE_L1_IBUS3_OVF_INT_ST_V << CACHE_L1_IBUS3_OVF_INT_ST_S)
+#define CACHE_L1_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_IBUS3_OVF_INT_ST_S  3
+/** CACHE_L1_DBUS0_OVF_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_OVF_INT_ST    (BIT(4))
+#define CACHE_L1_DBUS0_OVF_INT_ST_M  (CACHE_L1_DBUS0_OVF_INT_ST_V << CACHE_L1_DBUS0_OVF_INT_ST_S)
+#define CACHE_L1_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS0_OVF_INT_ST_S  4
+/** CACHE_L1_DBUS1_OVF_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L1-DCache due to bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_OVF_INT_ST    (BIT(5))
+#define CACHE_L1_DBUS1_OVF_INT_ST_M  (CACHE_L1_DBUS1_OVF_INT_ST_V << CACHE_L1_DBUS1_OVF_INT_ST_S)
+#define CACHE_L1_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS1_OVF_INT_ST_S  5
+/** CACHE_L1_DBUS2_OVF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_OVF_INT_ST    (BIT(6))
+#define CACHE_L1_DBUS2_OVF_INT_ST_M  (CACHE_L1_DBUS2_OVF_INT_ST_V << CACHE_L1_DBUS2_OVF_INT_ST_S)
+#define CACHE_L1_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS2_OVF_INT_ST_S  6
+/** CACHE_L1_DBUS3_OVF_INT_ST : RO; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_OVF_INT_ST    (BIT(7))
+#define CACHE_L1_DBUS3_OVF_INT_ST_M  (CACHE_L1_DBUS3_OVF_INT_ST_V << CACHE_L1_DBUS3_OVF_INT_ST_S)
+#define CACHE_L1_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L1_DBUS3_OVF_INT_ST_S  7
+
+/** CACHE_L1_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x16c)
+/** CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE : R/W; bitpos: [0]; default: 0;
+ *  Configures l1 icache0 access fail check mode. 0: the access fail is not propagated
+ *  to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE0_ACS_FAIL_CHECK_MODE_S  0
+/** CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configures l1 icache1 access fail check mode. 0: the access fail is not propagated
+ *  to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE    (BIT(1))
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE1_ACS_FAIL_CHECK_MODE_S  1
+/** CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE : R/W; bitpos: [2]; default: 0;
+ *  Configures l1 icache2 access fail check mode. 0: the access fail is not propagated
+ *  to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE    (BIT(2))
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE2_ACS_FAIL_CHECK_MODE_S  2
+/** CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE : R/W; bitpos: [3]; default: 0;
+ *  Configures l1 icache3 access fail check mode. 0: the access fail is not propagated
+ *  to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE    (BIT(3))
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V << CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_ICACHE3_ACS_FAIL_CHECK_MODE_S  3
+/** CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE : R/W; bitpos: [4]; default: 0;
+ *  Configures l1 dcache access fail check mode. 0: the access fail is not propagated
+ *  to the request, 1: the access fail is propagated to the request
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE    (BIT(4))
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L1_DCACHE_ACS_FAIL_CHECK_MODE_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x170)
+/** CACHE_L1_ICACHE0_FAIL_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures interrupt of access fail that occurs in L1-ICache0 due to cpu accesses
+ *  L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_M  (CACHE_L1_ICACHE0_FAIL_INT_ENA_V << CACHE_L1_ICACHE0_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures interrupt of access fail that occurs in L1-ICache1 due to cpu accesses
+ *  L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_M  (CACHE_L1_ICACHE1_FAIL_INT_ENA_V << CACHE_L1_ICACHE1_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_M  (CACHE_L1_ICACHE2_FAIL_INT_ENA_V << CACHE_L1_ICACHE2_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_M  (CACHE_L1_ICACHE3_FAIL_INT_ENA_V << CACHE_L1_ICACHE3_FAIL_INT_ENA_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ENA_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures interrupt of access fail that occurs in L1-DCache due to cpu accesses
+ *  L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_M  (CACHE_L1_DCACHE_FAIL_INT_ENA_V << CACHE_L1_DCACHE_FAIL_INT_ENA_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ENA_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x174)
+/** CACHE_L1_ICACHE0_FAIL_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+ *  cpu accesses L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_M  (CACHE_L1_ICACHE0_FAIL_INT_CLR_V << CACHE_L1_ICACHE0_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+ *  cpu accesses L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_M  (CACHE_L1_ICACHE1_FAIL_INT_CLR_V << CACHE_L1_ICACHE1_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_M  (CACHE_L1_ICACHE2_FAIL_INT_CLR_V << CACHE_L1_ICACHE2_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_M  (CACHE_L1_ICACHE3_FAIL_INT_CLR_V << CACHE_L1_ICACHE3_FAIL_INT_CLR_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_CLR_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+ *  cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_M  (CACHE_L1_DCACHE_FAIL_INT_CLR_V << CACHE_L1_DCACHE_FAIL_INT_CLR_S)
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_CLR_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x178)
+/** CACHE_L1_ICACHE0_FAIL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_M  (CACHE_L1_ICACHE0_FAIL_INT_RAW_V << CACHE_L1_ICACHE0_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_M  (CACHE_L1_ICACHE1_FAIL_INT_RAW_V << CACHE_L1_ICACHE1_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_M  (CACHE_L1_ICACHE2_FAIL_INT_RAW_V << CACHE_L1_ICACHE2_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_M  (CACHE_L1_ICACHE3_FAIL_INT_RAW_V << CACHE_L1_ICACHE3_FAIL_INT_RAW_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_RAW_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_M  (CACHE_L1_DCACHE_FAIL_INT_RAW_V << CACHE_L1_DCACHE_FAIL_INT_RAW_S)
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_RAW_S  4
+
+/** CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x17c)
+/** CACHE_L1_ICACHE0_FAIL_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_M  (CACHE_L1_ICACHE0_FAIL_INT_ST_V << CACHE_L1_ICACHE0_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_FAIL_INT_ST_S  0
+/** CACHE_L1_ICACHE1_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+ *  to cpu accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_M  (CACHE_L1_ICACHE1_FAIL_INT_ST_V << CACHE_L1_ICACHE1_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_FAIL_INT_ST_S  1
+/** CACHE_L1_ICACHE2_FAIL_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE2_FAIL_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_M  (CACHE_L1_ICACHE2_FAIL_INT_ST_V << CACHE_L1_ICACHE2_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_FAIL_INT_ST_S  2
+/** CACHE_L1_ICACHE3_FAIL_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_ICACHE3_FAIL_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_M  (CACHE_L1_ICACHE3_FAIL_INT_ST_V << CACHE_L1_ICACHE3_FAIL_INT_ST_S)
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_FAIL_INT_ST_S  3
+/** CACHE_L1_DCACHE_FAIL_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+ *  to cpu accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_FAIL_INT_ST_M  (CACHE_L1_DCACHE_FAIL_INT_ST_V << CACHE_L1_DCACHE_FAIL_INT_ST_S)
+#define CACHE_L1_DCACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_FAIL_INT_ST_S  4
+
+/** CACHE_L1_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ */
+#define CACHE_L1_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x180)
+/** CACHE_L1_IBUS0_CNT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to enable IBUS0 counter.
+ *  1: Enable
+ */
+#define CACHE_L1_IBUS0_CNT_ENA    (BIT(0))
+#define CACHE_L1_IBUS0_CNT_ENA_M  (CACHE_L1_IBUS0_CNT_ENA_V << CACHE_L1_IBUS0_CNT_ENA_S)
+#define CACHE_L1_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_ENA_S  0
+/** CACHE_L1_IBUS1_CNT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures whether to enable IBUS1 counter.
+ *  1: Enable
+ */
+#define CACHE_L1_IBUS1_CNT_ENA    (BIT(1))
+#define CACHE_L1_IBUS1_CNT_ENA_M  (CACHE_L1_IBUS1_CNT_ENA_V << CACHE_L1_IBUS1_CNT_ENA_S)
+#define CACHE_L1_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_ENA_S  1
+/** CACHE_L1_IBUS2_CNT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_ENA    (BIT(2))
+#define CACHE_L1_IBUS2_CNT_ENA_M  (CACHE_L1_IBUS2_CNT_ENA_V << CACHE_L1_IBUS2_CNT_ENA_S)
+#define CACHE_L1_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_ENA_S  2
+/** CACHE_L1_IBUS3_CNT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_ENA    (BIT(3))
+#define CACHE_L1_IBUS3_CNT_ENA_M  (CACHE_L1_IBUS3_CNT_ENA_V << CACHE_L1_IBUS3_CNT_ENA_S)
+#define CACHE_L1_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_ENA_S  3
+/** CACHE_L1_DBUS0_CNT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures whether to enable DBUS0 counter.
+ *  1: Enable
+ */
+#define CACHE_L1_DBUS0_CNT_ENA    (BIT(4))
+#define CACHE_L1_DBUS0_CNT_ENA_M  (CACHE_L1_DBUS0_CNT_ENA_V << CACHE_L1_DBUS0_CNT_ENA_S)
+#define CACHE_L1_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_ENA_S  4
+/** CACHE_L1_DBUS1_CNT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable DBUS1 counter.
+ *  1: Enable
+ */
+#define CACHE_L1_DBUS1_CNT_ENA    (BIT(5))
+#define CACHE_L1_DBUS1_CNT_ENA_M  (CACHE_L1_DBUS1_CNT_ENA_V << CACHE_L1_DBUS1_CNT_ENA_S)
+#define CACHE_L1_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_ENA_S  5
+/** CACHE_L1_DBUS2_CNT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_ENA    (BIT(6))
+#define CACHE_L1_DBUS2_CNT_ENA_M  (CACHE_L1_DBUS2_CNT_ENA_V << CACHE_L1_DBUS2_CNT_ENA_S)
+#define CACHE_L1_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_ENA_S  6
+/** CACHE_L1_DBUS3_CNT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_ENA    (BIT(7))
+#define CACHE_L1_DBUS3_CNT_ENA_M  (CACHE_L1_DBUS3_CNT_ENA_V << CACHE_L1_DBUS3_CNT_ENA_S)
+#define CACHE_L1_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_ENA_S  7
+/** CACHE_L1_IBUS0_CNT_CLR : WT; bitpos: [16]; default: 0;
+ *  Configures whether to clear IBUS0 counter.
+ *  1: Clear
+ */
+#define CACHE_L1_IBUS0_CNT_CLR    (BIT(16))
+#define CACHE_L1_IBUS0_CNT_CLR_M  (CACHE_L1_IBUS0_CNT_CLR_V << CACHE_L1_IBUS0_CNT_CLR_S)
+#define CACHE_L1_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS0_CNT_CLR_S  16
+/** CACHE_L1_IBUS1_CNT_CLR : WT; bitpos: [17]; default: 0;
+ *  Configures whether to clear IBUS1 counter.
+ *  1: Clear
+ */
+#define CACHE_L1_IBUS1_CNT_CLR    (BIT(17))
+#define CACHE_L1_IBUS1_CNT_CLR_M  (CACHE_L1_IBUS1_CNT_CLR_V << CACHE_L1_IBUS1_CNT_CLR_S)
+#define CACHE_L1_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS1_CNT_CLR_S  17
+/** CACHE_L1_IBUS2_CNT_CLR : WT; bitpos: [18]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS2_CNT_CLR    (BIT(18))
+#define CACHE_L1_IBUS2_CNT_CLR_M  (CACHE_L1_IBUS2_CNT_CLR_V << CACHE_L1_IBUS2_CNT_CLR_S)
+#define CACHE_L1_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS2_CNT_CLR_S  18
+/** CACHE_L1_IBUS3_CNT_CLR : WT; bitpos: [19]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_IBUS3_CNT_CLR    (BIT(19))
+#define CACHE_L1_IBUS3_CNT_CLR_M  (CACHE_L1_IBUS3_CNT_CLR_V << CACHE_L1_IBUS3_CNT_CLR_S)
+#define CACHE_L1_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_IBUS3_CNT_CLR_S  19
+/** CACHE_L1_DBUS0_CNT_CLR : WT; bitpos: [20]; default: 0;
+ *  Configures whether to clear DBUS0 counter.
+ *  1: Clear
+ */
+#define CACHE_L1_DBUS0_CNT_CLR    (BIT(20))
+#define CACHE_L1_DBUS0_CNT_CLR_M  (CACHE_L1_DBUS0_CNT_CLR_V << CACHE_L1_DBUS0_CNT_CLR_S)
+#define CACHE_L1_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS0_CNT_CLR_S  20
+/** CACHE_L1_DBUS1_CNT_CLR : WT; bitpos: [21]; default: 0;
+ *  Configures whether to clear DBUS1 counter.
+ *  1: Clear
+ */
+#define CACHE_L1_DBUS1_CNT_CLR    (BIT(21))
+#define CACHE_L1_DBUS1_CNT_CLR_M  (CACHE_L1_DBUS1_CNT_CLR_V << CACHE_L1_DBUS1_CNT_CLR_S)
+#define CACHE_L1_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS1_CNT_CLR_S  21
+/** CACHE_L1_DBUS2_CNT_CLR : WT; bitpos: [22]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS2_CNT_CLR    (BIT(22))
+#define CACHE_L1_DBUS2_CNT_CLR_M  (CACHE_L1_DBUS2_CNT_CLR_V << CACHE_L1_DBUS2_CNT_CLR_S)
+#define CACHE_L1_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS2_CNT_CLR_S  22
+/** CACHE_L1_DBUS3_CNT_CLR : WT; bitpos: [23]; default: 0;
+ *  Reserved
+ */
+#define CACHE_L1_DBUS3_CNT_CLR    (BIT(23))
+#define CACHE_L1_DBUS3_CNT_CLR_M  (CACHE_L1_DBUS3_CNT_CLR_V << CACHE_L1_DBUS3_CNT_CLR_S)
+#define CACHE_L1_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L1_DBUS3_CNT_CLR_S  23
+
+/** CACHE_L1_IBUS0_ACS_HIT_CNT_REG register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x184)
+/** CACHE_L1_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_M  (CACHE_L1_IBUS0_HIT_CNT_V << CACHE_L1_IBUS0_HIT_CNT_S)
+#define CACHE_L1_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_MISS_CNT_REG register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x188)
+/** CACHE_L1_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_M  (CACHE_L1_IBUS0_MISS_CNT_V << CACHE_L1_IBUS0_MISS_CNT_S)
+#define CACHE_L1_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x18c)
+/** CACHE_L1_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_M  (CACHE_L1_IBUS0_CONFLICT_CNT_V << CACHE_L1_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x190)
+/** CACHE_L1_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ */
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS0_NXTLVL_RD_CNT_V << CACHE_L1_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_HIT_CNT_REG register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x194)
+/** CACHE_L1_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_M  (CACHE_L1_IBUS1_HIT_CNT_V << CACHE_L1_IBUS1_HIT_CNT_S)
+#define CACHE_L1_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_MISS_CNT_REG register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x198)
+/** CACHE_L1_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_M  (CACHE_L1_IBUS1_MISS_CNT_V << CACHE_L1_IBUS1_MISS_CNT_S)
+#define CACHE_L1_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x19c)
+/** CACHE_L1_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_M  (CACHE_L1_IBUS1_CONFLICT_CNT_V << CACHE_L1_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1a0)
+/** CACHE_L1_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ */
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS1_NXTLVL_RD_CNT_V << CACHE_L1_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_HIT_CNT_REG register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1a4)
+/** CACHE_L1_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_M  (CACHE_L1_IBUS2_HIT_CNT_V << CACHE_L1_IBUS2_HIT_CNT_S)
+#define CACHE_L1_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_MISS_CNT_REG register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1a8)
+/** CACHE_L1_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_M  (CACHE_L1_IBUS2_MISS_CNT_V << CACHE_L1_IBUS2_MISS_CNT_S)
+#define CACHE_L1_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1ac)
+/** CACHE_L1_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_M  (CACHE_L1_IBUS2_CONFLICT_CNT_V << CACHE_L1_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1b0)
+/** CACHE_L1_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ */
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS2_NXTLVL_RD_CNT_V << CACHE_L1_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_HIT_CNT_REG register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1b4)
+/** CACHE_L1_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_M  (CACHE_L1_IBUS3_HIT_CNT_V << CACHE_L1_IBUS3_HIT_CNT_S)
+#define CACHE_L1_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_MISS_CNT_REG register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1b8)
+/** CACHE_L1_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_M  (CACHE_L1_IBUS3_MISS_CNT_V << CACHE_L1_IBUS3_MISS_CNT_S)
+#define CACHE_L1_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1bc)
+/** CACHE_L1_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_M  (CACHE_L1_IBUS3_CONFLICT_CNT_V << CACHE_L1_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1c0)
+/** CACHE_L1_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-ICache accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ */
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_IBUS3_NXTLVL_RD_CNT_V << CACHE_L1_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_HIT_CNT_REG register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1c4)
+/** CACHE_L1_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_M  (CACHE_L1_DBUS0_HIT_CNT_V << CACHE_L1_DBUS0_HIT_CNT_S)
+#define CACHE_L1_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_MISS_CNT_REG register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1c8)
+/** CACHE_L1_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_M  (CACHE_L1_DBUS0_MISS_CNT_V << CACHE_L1_DBUS0_MISS_CNT_S)
+#define CACHE_L1_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1cc)
+/** CACHE_L1_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_M  (CACHE_L1_DBUS0_CONFLICT_CNT_V << CACHE_L1_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1d0)
+/** CACHE_L1_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS0_NXTLVL_RD_CNT_V << CACHE_L1_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1d4)
+/** CACHE_L1_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS0_NXTLVL_WR_CNT_V << CACHE_L1_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_HIT_CNT_REG register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1d8)
+/** CACHE_L1_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_M  (CACHE_L1_DBUS1_HIT_CNT_V << CACHE_L1_DBUS1_HIT_CNT_S)
+#define CACHE_L1_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_MISS_CNT_REG register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1dc)
+/** CACHE_L1_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_M  (CACHE_L1_DBUS1_MISS_CNT_V << CACHE_L1_DBUS1_MISS_CNT_S)
+#define CACHE_L1_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1e0)
+/** CACHE_L1_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_M  (CACHE_L1_DBUS1_CONFLICT_CNT_V << CACHE_L1_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1e4)
+/** CACHE_L1_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS1_NXTLVL_RD_CNT_V << CACHE_L1_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1e8)
+/** CACHE_L1_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus1 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS1_NXTLVL_WR_CNT_V << CACHE_L1_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_HIT_CNT_REG register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x1ec)
+/** CACHE_L1_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_M  (CACHE_L1_DBUS2_HIT_CNT_V << CACHE_L1_DBUS2_HIT_CNT_S)
+#define CACHE_L1_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_MISS_CNT_REG register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x1f0)
+/** CACHE_L1_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_M  (CACHE_L1_DBUS2_MISS_CNT_V << CACHE_L1_DBUS2_MISS_CNT_S)
+#define CACHE_L1_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x1f4)
+/** CACHE_L1_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_M  (CACHE_L1_DBUS2_CONFLICT_CNT_V << CACHE_L1_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x1f8)
+/** CACHE_L1_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS2_NXTLVL_RD_CNT_V << CACHE_L1_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x1fc)
+/** CACHE_L1_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus2 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS2_NXTLVL_WR_CNT_V << CACHE_L1_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_HIT_CNT_REG register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x200)
+/** CACHE_L1_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_M  (CACHE_L1_DBUS3_HIT_CNT_V << CACHE_L1_DBUS3_HIT_CNT_S)
+#define CACHE_L1_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_MISS_CNT_REG register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x204)
+/** CACHE_L1_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_M  (CACHE_L1_DBUS3_MISS_CNT_V << CACHE_L1_DBUS3_MISS_CNT_S)
+#define CACHE_L1_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x208)
+/** CACHE_L1_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_M  (CACHE_L1_DBUS3_CONFLICT_CNT_V << CACHE_L1_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L1_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x20c)
+/** CACHE_L1_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L1_DBUS3_NXTLVL_RD_CNT_V << CACHE_L1_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+#define CACHE_L1_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x210)
+/** CACHE_L1_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when bus0 accesses L1-DCache.
+ */
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L1_DBUS3_NXTLVL_WR_CNT_V << CACHE_L1_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L1_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x214)
+/** CACHE_L1_ICACHE0_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_M  (CACHE_L1_ICACHE0_FAIL_ID_V << CACHE_L1_ICACHE0_FAIL_ID_S)
+#define CACHE_L1_ICACHE0_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ID_S  0
+/** CACHE_L1_ICACHE0_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_M  (CACHE_L1_ICACHE0_FAIL_ATTR_V << CACHE_L1_ICACHE0_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE0_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE0_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE0_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x218)
+/** CACHE_L1_ICACHE0_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache0 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE0_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_M  (CACHE_L1_ICACHE0_FAIL_ADDR_V << CACHE_L1_ICACHE0_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE0_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE0_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x21c)
+/** CACHE_L1_ICACHE1_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_M  (CACHE_L1_ICACHE1_FAIL_ID_V << CACHE_L1_ICACHE1_FAIL_ID_S)
+#define CACHE_L1_ICACHE1_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ID_S  0
+/** CACHE_L1_ICACHE1_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_M  (CACHE_L1_ICACHE1_FAIL_ATTR_V << CACHE_L1_ICACHE1_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE1_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE1_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE1_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x220)
+/** CACHE_L1_ICACHE1_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache1 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE1_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_M  (CACHE_L1_ICACHE1_FAIL_ADDR_V << CACHE_L1_ICACHE1_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE1_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE1_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x224)
+/** CACHE_L1_ICACHE2_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_M  (CACHE_L1_ICACHE2_FAIL_ID_V << CACHE_L1_ICACHE2_FAIL_ID_S)
+#define CACHE_L1_ICACHE2_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ID_S  0
+/** CACHE_L1_ICACHE2_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_M  (CACHE_L1_ICACHE2_FAIL_ATTR_V << CACHE_L1_ICACHE2_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE2_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE2_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE2_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x228)
+/** CACHE_L1_ICACHE2_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache2 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE2_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_M  (CACHE_L1_ICACHE2_FAIL_ADDR_V << CACHE_L1_ICACHE2_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE2_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE2_FAIL_ADDR_S  0
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x22c)
+/** CACHE_L1_ICACHE3_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_M  (CACHE_L1_ICACHE3_FAIL_ID_V << CACHE_L1_ICACHE3_FAIL_ID_S)
+#define CACHE_L1_ICACHE3_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ID_S  0
+/** CACHE_L1_ICACHE3_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_M  (CACHE_L1_ICACHE3_FAIL_ATTR_V << CACHE_L1_ICACHE3_FAIL_ATTR_S)
+#define CACHE_L1_ICACHE3_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_ICACHE3_FAIL_ATTR_S  16
+
+/** CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG register
+ *  L1-ICache0 Access Fail Address information register
+ */
+#define CACHE_L1_ICACHE3_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x230)
+/** CACHE_L1_ICACHE3_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache3 accesses L1-ICache.
+ */
+#define CACHE_L1_ICACHE3_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_M  (CACHE_L1_ICACHE3_FAIL_ADDR_V << CACHE_L1_ICACHE3_FAIL_ADDR_S)
+#define CACHE_L1_ICACHE3_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_ICACHE3_FAIL_ADDR_S  0
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x234)
+/** CACHE_L1_DCACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_M  (CACHE_L1_DCACHE_FAIL_ID_V << CACHE_L1_DCACHE_FAIL_ID_S)
+#define CACHE_L1_DCACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ID_S  0
+/** CACHE_L1_DCACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_M  (CACHE_L1_DCACHE_FAIL_ATTR_V << CACHE_L1_DCACHE_FAIL_ATTR_S)
+#define CACHE_L1_DCACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L1_DCACHE_FAIL_ATTR_S  16
+
+/** CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG register
+ *  L1-DCache Access Fail Address information register
+ */
+#define CACHE_L1_DCACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x238)
+/** CACHE_L1_DCACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when cache accesses L1-DCache.
+ */
+#define CACHE_L1_DCACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_M  (CACHE_L1_DCACHE_FAIL_ADDR_V << CACHE_L1_DCACHE_FAIL_ADDR_S)
+#define CACHE_L1_DCACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_DCACHE_FAIL_ADDR_S  0
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x23c)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures interrupt of L1-ICache0 preload-operation. If preload operation is done,
+ *  interrupt occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ENA_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Configures interrupt of L1-ICache1 preload-operation. If preload operation is done,
+ *  interrupt occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ENA_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ENA_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ENA_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Configures interrupt of L1-DCache preload-operation. If preload operation is done,
+ *  interrupt occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V << CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ENA_S  4
+/** CACHE_SYNC_DONE_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Configures interrupt of Cache sync-operation done.
+ */
+#define CACHE_SYNC_DONE_INT_ENA    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ENA_M  (CACHE_SYNC_DONE_INT_ENA_V << CACHE_SYNC_DONE_INT_ENA_S)
+#define CACHE_SYNC_DONE_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ENA_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Configures interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ENA_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Configures interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ENA_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ENA_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ENA_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Configures interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V << CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ENA_S  11
+/** CACHE_SYNC_ERR_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Configures interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ENA    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ENA_M  (CACHE_SYNC_ERR_INT_ENA_V << CACHE_SYNC_ERR_INT_ENA_S)
+#define CACHE_SYNC_ERR_INT_ENA_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ENA_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x240)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_CLR_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_CLR_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_CLR_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V << CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_CLR_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_M  (CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V << CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_CLR_S  4
+/** CACHE_SYNC_DONE_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+ *  done.
+ */
+#define CACHE_SYNC_DONE_INT_CLR    (BIT(6))
+#define CACHE_SYNC_DONE_INT_CLR_M  (CACHE_SYNC_DONE_INT_CLR_V << CACHE_SYNC_DONE_INT_CLR_S)
+#define CACHE_SYNC_DONE_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_CLR_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_CLR_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_CLR_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_CLR_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V << CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_CLR_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_M  (CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V << CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_CLR_S  11
+/** CACHE_SYNC_ERR_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_CLR    (BIT(13))
+#define CACHE_SYNC_ERR_INT_CLR_M  (CACHE_SYNC_ERR_INT_CLR_V << CACHE_SYNC_ERR_INT_CLR_S)
+#define CACHE_SYNC_ERR_INT_CLR_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_CLR_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x244)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_RAW_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+ *  done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_RAW_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_RAW_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V << CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_RAW_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+ *  done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_M  (CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V << CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_RAW_S  4
+/** CACHE_SYNC_DONE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_RAW    (BIT(6))
+#define CACHE_SYNC_DONE_INT_RAW_M  (CACHE_SYNC_DONE_INT_RAW_V << CACHE_SYNC_DONE_INT_RAW_S)
+#define CACHE_SYNC_DONE_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_RAW_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_RAW_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_RAW_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_RAW_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V << CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_RAW_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+ *  error occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_M  (CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V << CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_RAW_S  11
+/** CACHE_SYNC_ERR_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+ *  occurs.
+ */
+#define CACHE_SYNC_ERR_INT_RAW    (BIT(13))
+#define CACHE_SYNC_ERR_INT_RAW_M  (CACHE_SYNC_ERR_INT_RAW_V << CACHE_SYNC_ERR_INT_RAW_S)
+#define CACHE_SYNC_ERR_INT_RAW_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_RAW_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x248)
+/** CACHE_L1_ICACHE0_PLD_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_DONE_INT_ST_S  0
+/** CACHE_L1_ICACHE1_PLD_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+ *  preload-operation is done.
+ */
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_DONE_INT_ST_S  1
+/** CACHE_L1_ICACHE2_PLD_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_DONE_INT_ST_S  2
+/** CACHE_L1_ICACHE3_PLD_DONE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_M  (CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V << CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_DONE_INT_ST_S  3
+/** CACHE_L1_DCACHE_PLD_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+ *  preload-operation is done.
+ */
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_M  (CACHE_L1_DCACHE_PLD_DONE_INT_ST_V << CACHE_L1_DCACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_DONE_INT_ST_S  4
+/** CACHE_SYNC_DONE_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when Cache
+ *  sync-operation is done.
+ */
+#define CACHE_SYNC_DONE_INT_ST    (BIT(6))
+#define CACHE_SYNC_DONE_INT_ST_M  (CACHE_SYNC_DONE_INT_ST_V << CACHE_SYNC_DONE_INT_ST_S)
+#define CACHE_SYNC_DONE_INT_ST_V  0x00000001U
+#define CACHE_SYNC_DONE_INT_ST_S  6
+/** CACHE_L1_ICACHE0_PLD_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST    (BIT(7))
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_ERR_INT_ST_S  7
+/** CACHE_L1_ICACHE1_PLD_ERR_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST    (BIT(8))
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_ERR_INT_ST_S  8
+/** CACHE_L1_ICACHE2_PLD_ERR_INT_ST : RO; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST    (BIT(9))
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_ERR_INT_ST_S  9
+/** CACHE_L1_ICACHE3_PLD_ERR_INT_ST : RO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST    (BIT(10))
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_M  (CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V << CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_ERR_INT_ST_S  10
+/** CACHE_L1_DCACHE_PLD_ERR_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST    (BIT(11))
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_M  (CACHE_L1_DCACHE_PLD_ERR_INT_ST_V << CACHE_L1_DCACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_ERR_INT_ST_S  11
+/** CACHE_SYNC_ERR_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the status of the interrupt of Cache sync-operation error.
+ */
+#define CACHE_SYNC_ERR_INT_ST    (BIT(13))
+#define CACHE_SYNC_ERR_INT_ST_M  (CACHE_SYNC_ERR_INT_ST_V << CACHE_SYNC_ERR_INT_ST_S)
+#define CACHE_SYNC_ERR_INT_ST_V  0x00000001U
+#define CACHE_SYNC_ERR_INT_ST_S  13
+
+/** CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ */
+#define CACHE_L1_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x24c)
+/** CACHE_L1_ICACHE0_PLD_ERR_CODE : RO; bitpos: [1:0]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_M  (CACHE_L1_ICACHE0_PLD_ERR_CODE_V << CACHE_L1_ICACHE0_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE0_PLD_ERR_CODE_S  0
+/** CACHE_L1_ICACHE1_PLD_ERR_CODE : RO; bitpos: [3:2]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_M  (CACHE_L1_ICACHE1_PLD_ERR_CODE_V << CACHE_L1_ICACHE1_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE1_PLD_ERR_CODE_S  2
+/** CACHE_L1_ICACHE2_PLD_ERR_CODE : RO; bitpos: [5:4]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_M  (CACHE_L1_ICACHE2_PLD_ERR_CODE_V << CACHE_L1_ICACHE2_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE2_PLD_ERR_CODE_S  4
+/** CACHE_L1_ICACHE3_PLD_ERR_CODE : RO; bitpos: [7:6]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_M  (CACHE_L1_ICACHE3_PLD_ERR_CODE_V << CACHE_L1_ICACHE3_PLD_ERR_CODE_S)
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_ICACHE3_PLD_ERR_CODE_S  6
+/** CACHE_L1_DCACHE_PLD_ERR_CODE : RO; bitpos: [9:8]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L1-DCache.
+ */
+#define CACHE_L1_DCACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_M  (CACHE_L1_DCACHE_PLD_ERR_CODE_V << CACHE_L1_DCACHE_PLD_ERR_CODE_S)
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L1_DCACHE_PLD_ERR_CODE_S  8
+/** CACHE_SYNC_ERR_CODE : RO; bitpos: [13:12]; default: 0;
+ *  The values 0-2 are available which means sync map, command conflict and size are
+ *  error in Cache System.
+ */
+#define CACHE_SYNC_ERR_CODE    0x00000003U
+#define CACHE_SYNC_ERR_CODE_M  (CACHE_SYNC_ERR_CODE_V << CACHE_SYNC_ERR_CODE_S)
+#define CACHE_SYNC_ERR_CODE_V  0x00000003U
+#define CACHE_SYNC_ERR_CODE_S  12
+
+/** CACHE_L1_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ */
+#define CACHE_L1_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x250)
+/** CACHE_L1_ICACHE0_SYNC_RST : R/W; bitpos: [0]; default: 0;
+ *  Configures reset sync-logic inside L1-ICache0. Recommend that this should only be
+ *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_SYNC_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_SYNC_RST_M  (CACHE_L1_ICACHE0_SYNC_RST_V << CACHE_L1_ICACHE0_SYNC_RST_S)
+#define CACHE_L1_ICACHE0_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_SYNC_RST_S  0
+/** CACHE_L1_ICACHE1_SYNC_RST : R/W; bitpos: [1]; default: 0;
+ *  Configures reset sync-logic inside L1-ICache1. Recommend that this should only be
+ *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_SYNC_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_SYNC_RST_M  (CACHE_L1_ICACHE1_SYNC_RST_V << CACHE_L1_ICACHE1_SYNC_RST_S)
+#define CACHE_L1_ICACHE1_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_SYNC_RST_S  1
+/** CACHE_L1_ICACHE2_SYNC_RST : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_SYNC_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_SYNC_RST_M  (CACHE_L1_ICACHE2_SYNC_RST_V << CACHE_L1_ICACHE2_SYNC_RST_S)
+#define CACHE_L1_ICACHE2_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_SYNC_RST_S  2
+/** CACHE_L1_ICACHE3_SYNC_RST : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_SYNC_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_SYNC_RST_M  (CACHE_L1_ICACHE3_SYNC_RST_V << CACHE_L1_ICACHE3_SYNC_RST_S)
+#define CACHE_L1_ICACHE3_SYNC_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_SYNC_RST_S  3
+/** CACHE_L1_DCACHE_SYNC_RST : R/W; bitpos: [4]; default: 0;
+ *  Configures reset sync-logic inside L1-DCache. Recommend that this should only be
+ *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+ */
+#define CACHE_L1_DCACHE_SYNC_RST    (BIT(4))
+#define CACHE_L1_DCACHE_SYNC_RST_M  (CACHE_L1_DCACHE_SYNC_RST_V << CACHE_L1_DCACHE_SYNC_RST_S)
+#define CACHE_L1_DCACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_SYNC_RST_S  4
+
+/** CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ */
+#define CACHE_L1_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x254)
+/** CACHE_L1_ICACHE0_PLD_RST : R/W; bitpos: [0]; default: 0;
+ *  Configures reset preload-logic inside L1-ICache0. Recommend that this should only
+ *  be used to initialize preload-logic when some fatal error of preload-logic occurs.
+ */
+#define CACHE_L1_ICACHE0_PLD_RST    (BIT(0))
+#define CACHE_L1_ICACHE0_PLD_RST_M  (CACHE_L1_ICACHE0_PLD_RST_V << CACHE_L1_ICACHE0_PLD_RST_S)
+#define CACHE_L1_ICACHE0_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE0_PLD_RST_S  0
+/** CACHE_L1_ICACHE1_PLD_RST : R/W; bitpos: [1]; default: 0;
+ *  Configures reset preload-logic inside L1-ICache1. Recommend that this should only
+ *  be used to initialize preload-logic when some fatal error of preload-logic occurs.
+ */
+#define CACHE_L1_ICACHE1_PLD_RST    (BIT(1))
+#define CACHE_L1_ICACHE1_PLD_RST_M  (CACHE_L1_ICACHE1_PLD_RST_V << CACHE_L1_ICACHE1_PLD_RST_S)
+#define CACHE_L1_ICACHE1_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE1_PLD_RST_S  1
+/** CACHE_L1_ICACHE2_PLD_RST : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_PLD_RST    (BIT(2))
+#define CACHE_L1_ICACHE2_PLD_RST_M  (CACHE_L1_ICACHE2_PLD_RST_V << CACHE_L1_ICACHE2_PLD_RST_S)
+#define CACHE_L1_ICACHE2_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE2_PLD_RST_S  2
+/** CACHE_L1_ICACHE3_PLD_RST : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_PLD_RST    (BIT(3))
+#define CACHE_L1_ICACHE3_PLD_RST_M  (CACHE_L1_ICACHE3_PLD_RST_V << CACHE_L1_ICACHE3_PLD_RST_S)
+#define CACHE_L1_ICACHE3_PLD_RST_V  0x00000001U
+#define CACHE_L1_ICACHE3_PLD_RST_S  3
+/** CACHE_L1_DCACHE_PLD_RST : R/W; bitpos: [4]; default: 0;
+ *  Configures reset preload-logic inside L1-DCache. Recommend that this should only be
+ *  used to initialize preload-logic when some fatal error of preload-logic occurs.
+ */
+#define CACHE_L1_DCACHE_PLD_RST    (BIT(4))
+#define CACHE_L1_DCACHE_PLD_RST_M  (CACHE_L1_DCACHE_PLD_RST_V << CACHE_L1_DCACHE_PLD_RST_S)
+#define CACHE_L1_DCACHE_PLD_RST_V  0x00000001U
+#define CACHE_L1_DCACHE_PLD_RST_S  4
+
+/** CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ */
+#define CACHE_L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x258)
+/** CACHE_L1_ICACHE0_ALD_BUF_CLR : R/W; bitpos: [0]; default: 0;
+ *  Configures clear autoload-buffer inside L1-ICache0. If this bit is active, autoload
+ *  will not work in L1-ICache0. This bit should not be active when autoload works in
+ *  L1-ICache0.
+ */
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_M  (CACHE_L1_ICACHE0_ALD_BUF_CLR_V << CACHE_L1_ICACHE0_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_ALD_BUF_CLR_S  0
+/** CACHE_L1_ICACHE1_ALD_BUF_CLR : R/W; bitpos: [1]; default: 0;
+ *  Configures clear autoload-buffer inside L1-ICache1. If this bit is active, autoload
+ *  will not work in L1-ICache1. This bit should not be active when autoload works in
+ *  L1-ICache1.
+ */
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_M  (CACHE_L1_ICACHE1_ALD_BUF_CLR_V << CACHE_L1_ICACHE1_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_ALD_BUF_CLR_S  1
+/** CACHE_L1_ICACHE2_ALD_BUF_CLR : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_M  (CACHE_L1_ICACHE2_ALD_BUF_CLR_V << CACHE_L1_ICACHE2_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_ALD_BUF_CLR_S  2
+/** CACHE_L1_ICACHE3_ALD_BUF_CLR : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_M  (CACHE_L1_ICACHE3_ALD_BUF_CLR_V << CACHE_L1_ICACHE3_ALD_BUF_CLR_S)
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_ALD_BUF_CLR_S  3
+/** CACHE_L1_DCACHE_ALD_BUF_CLR : R/W; bitpos: [4]; default: 0;
+ *  Configures clear autoload-buffer inside L1-DCache. If this bit is active, autoload
+ *  will not work in L1-DCache. This bit should not be active when autoload works in
+ *  L1-DCache.
+ */
+#define CACHE_L1_DCACHE_ALD_BUF_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_M  (CACHE_L1_DCACHE_ALD_BUF_CLR_V << CACHE_L1_DCACHE_ALD_BUF_CLR_S)
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_ALD_BUF_CLR_S  4
+
+/** CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ */
+#define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x25c)
+/** CACHE_L1_ICACHE0_UNALLOC_CLR : R/W; bitpos: [0]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
+/** CACHE_L1_ICACHE1_UNALLOC_CLR : R/W; bitpos: [1]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE1_UNALLOC_CLR_S  1
+/** CACHE_L1_ICACHE2_UNALLOC_CLR : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_UNALLOC_CLR    (BIT(2))
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_M  (CACHE_L1_ICACHE2_UNALLOC_CLR_V << CACHE_L1_ICACHE2_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE2_UNALLOC_CLR_S  2
+/** CACHE_L1_ICACHE3_UNALLOC_CLR : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_UNALLOC_CLR    (BIT(3))
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_M  (CACHE_L1_ICACHE3_UNALLOC_CLR_V << CACHE_L1_ICACHE3_UNALLOC_CLR_S)
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
+/** CACHE_L1_DCACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+ *  unallocate request is responded but not completed.
+ */
+#define CACHE_L1_DCACHE_UNALLOC_CLR    (BIT(4))
+#define CACHE_L1_DCACHE_UNALLOC_CLR_M  (CACHE_L1_DCACHE_UNALLOC_CLR_V << CACHE_L1_DCACHE_UNALLOC_CLR_S)
+#define CACHE_L1_DCACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L1_DCACHE_UNALLOC_CLR_S  4
+
+/** CACHE_L1_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ */
+#define CACHE_L1_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x260)
+/** CACHE_L1_ICACHE0_TAG_OBJECT : R/W; bitpos: [0]; default: 0;
+ *  Configures set L1-ICache0 tag memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_TAG_OBJECT    (BIT(0))
+#define CACHE_L1_ICACHE0_TAG_OBJECT_M  (CACHE_L1_ICACHE0_TAG_OBJECT_V << CACHE_L1_ICACHE0_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE0_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_TAG_OBJECT_S  0
+/** CACHE_L1_ICACHE1_TAG_OBJECT : R/W; bitpos: [1]; default: 0;
+ *  Configures set L1-ICache1 tag memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_TAG_OBJECT    (BIT(1))
+#define CACHE_L1_ICACHE1_TAG_OBJECT_M  (CACHE_L1_ICACHE1_TAG_OBJECT_V << CACHE_L1_ICACHE1_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE1_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_TAG_OBJECT_S  1
+/** CACHE_L1_ICACHE2_TAG_OBJECT : R/W; bitpos: [2]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_TAG_OBJECT    (BIT(2))
+#define CACHE_L1_ICACHE2_TAG_OBJECT_M  (CACHE_L1_ICACHE2_TAG_OBJECT_V << CACHE_L1_ICACHE2_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE2_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_TAG_OBJECT_S  2
+/** CACHE_L1_ICACHE3_TAG_OBJECT : R/W; bitpos: [3]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_TAG_OBJECT    (BIT(3))
+#define CACHE_L1_ICACHE3_TAG_OBJECT_M  (CACHE_L1_ICACHE3_TAG_OBJECT_V << CACHE_L1_ICACHE3_TAG_OBJECT_S)
+#define CACHE_L1_ICACHE3_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_TAG_OBJECT_S  3
+/** CACHE_L1_DCACHE_TAG_OBJECT : R/W; bitpos: [4]; default: 0;
+ *  Configures set L1-DCache tag memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_TAG_OBJECT    (BIT(4))
+#define CACHE_L1_DCACHE_TAG_OBJECT_M  (CACHE_L1_DCACHE_TAG_OBJECT_V << CACHE_L1_DCACHE_TAG_OBJECT_S)
+#define CACHE_L1_DCACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_TAG_OBJECT_S  4
+/** CACHE_L1_ICACHE0_MEM_OBJECT : R/W; bitpos: [6]; default: 0;
+ *  Configures set L1-ICache0 data memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_ICACHE0_MEM_OBJECT    (BIT(6))
+#define CACHE_L1_ICACHE0_MEM_OBJECT_M  (CACHE_L1_ICACHE0_MEM_OBJECT_V << CACHE_L1_ICACHE0_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE0_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE0_MEM_OBJECT_S  6
+/** CACHE_L1_ICACHE1_MEM_OBJECT : R/W; bitpos: [7]; default: 0;
+ *  Configures set L1-ICache1 data memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_ICACHE1_MEM_OBJECT    (BIT(7))
+#define CACHE_L1_ICACHE1_MEM_OBJECT_M  (CACHE_L1_ICACHE1_MEM_OBJECT_V << CACHE_L1_ICACHE1_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE1_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE1_MEM_OBJECT_S  7
+/** CACHE_L1_ICACHE2_MEM_OBJECT : R/W; bitpos: [8]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE2_MEM_OBJECT    (BIT(8))
+#define CACHE_L1_ICACHE2_MEM_OBJECT_M  (CACHE_L1_ICACHE2_MEM_OBJECT_V << CACHE_L1_ICACHE2_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE2_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE2_MEM_OBJECT_S  8
+/** CACHE_L1_ICACHE3_MEM_OBJECT : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L1_ICACHE3_MEM_OBJECT    (BIT(9))
+#define CACHE_L1_ICACHE3_MEM_OBJECT_M  (CACHE_L1_ICACHE3_MEM_OBJECT_V << CACHE_L1_ICACHE3_MEM_OBJECT_S)
+#define CACHE_L1_ICACHE3_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_ICACHE3_MEM_OBJECT_S  9
+/** CACHE_L1_DCACHE_MEM_OBJECT : R/W; bitpos: [10]; default: 0;
+ *  Configures set L1-DCache data memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ */
+#define CACHE_L1_DCACHE_MEM_OBJECT    (BIT(10))
+#define CACHE_L1_DCACHE_MEM_OBJECT_M  (CACHE_L1_DCACHE_MEM_OBJECT_V << CACHE_L1_DCACHE_MEM_OBJECT_S)
+#define CACHE_L1_DCACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L1_DCACHE_MEM_OBJECT_S  10
+
+/** CACHE_L1_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x264)
+/** CACHE_L1_CACHE_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0;
+ *  Configures way of the tag-object will be accessed.
+ *  1: way1
+ */
+#define CACHE_L1_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_M  (CACHE_L1_CACHE_WAY_OBJECT_V << CACHE_L1_CACHE_WAY_OBJECT_S)
+#define CACHE_L1_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L1_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L1_CACHE_ADDR_REG register
+ *  Cache address register
+ */
+#define CACHE_L1_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x268)
+/** CACHE_L1_CACHE_ADDR : R/W; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the address which will decide where inside the specified tag
+ *  memory object will be accessed.
+ */
+#define CACHE_L1_CACHE_ADDR    0xFFFFFFFFU
+#define CACHE_L1_CACHE_ADDR_M  (CACHE_L1_CACHE_ADDR_V << CACHE_L1_CACHE_ADDR_S)
+#define CACHE_L1_CACHE_ADDR_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_ADDR_S  0
+
+/** CACHE_L1_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x26c)
+/** CACHE_L1_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 620;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ */
+#define CACHE_L1_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_M  (CACHE_L1_CACHE_DEBUG_BUS_V << CACHE_L1_CACHE_DEBUG_BUS_S)
+#define CACHE_L1_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L1_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT0_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_LEVEL_SPLIT0_REG (DR_REG_CACHE_BASE + 0x270)
+/** CACHE_LEVEL_SPLIT0 : HRO; bitpos: [31:0]; default: 624;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_LEVEL_SPLIT0    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_M  (CACHE_LEVEL_SPLIT0_V << CACHE_LEVEL_SPLIT0_S)
+#define CACHE_LEVEL_SPLIT0_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT0_S  0
+
+/** CACHE_L2_CACHE_CTRL_REG register
+ *  L2 Cache(L2-Cache) control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_CTRL_REG (DR_REG_CACHE_BASE + 0x274)
+/** CACHE_L2_CACHE_SHUT_DMA : HRO; bitpos: [4]; default: 1;
+ *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_SHUT_DMA    (BIT(4))
+#define CACHE_L2_CACHE_SHUT_DMA_M  (CACHE_L2_CACHE_SHUT_DMA_V << CACHE_L2_CACHE_SHUT_DMA_S)
+#define CACHE_L2_CACHE_SHUT_DMA_V  0x00000001U
+#define CACHE_L2_CACHE_SHUT_DMA_S  4
+/** CACHE_L2_CACHE_UNDEF_OP : HRO; bitpos: [15:8]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_UNDEF_OP    0x000000FFU
+#define CACHE_L2_CACHE_UNDEF_OP_M  (CACHE_L2_CACHE_UNDEF_OP_V << CACHE_L2_CACHE_UNDEF_OP_S)
+#define CACHE_L2_CACHE_UNDEF_OP_V  0x000000FFU
+#define CACHE_L2_CACHE_UNDEF_OP_S  8
+
+/** CACHE_L2_BYPASS_CACHE_CONF_REG register
+ *  Bypass Cache configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_BYPASS_CACHE_CONF_REG (DR_REG_CACHE_BASE + 0x278)
+/** CACHE_BYPASS_L2_CACHE_EN : HRO; bitpos: [5]; default: 0;
+ *  Configures bypass L2-Cache.
+ *  1: Enable
+ *
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_BYPASS_L2_CACHE_EN    (BIT(5))
+#define CACHE_BYPASS_L2_CACHE_EN_M  (CACHE_BYPASS_L2_CACHE_EN_V << CACHE_BYPASS_L2_CACHE_EN_S)
+#define CACHE_BYPASS_L2_CACHE_EN_V  0x00000001U
+#define CACHE_BYPASS_L2_CACHE_EN_S  5
+
+/** CACHE_L2_CACHE_CACHESIZE_CONF_REG register
+ *  L2 Cache CacheSize mode configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_CONF_REG (DR_REG_CACHE_BASE + 0x27c)
+/** CACHE_L2_CACHE_CACHESIZE_256 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256    (BIT(0))
+#define CACHE_L2_CACHE_CACHESIZE_256_M  (CACHE_L2_CACHE_CACHESIZE_256_V << CACHE_L2_CACHE_CACHESIZE_256_S)
+#define CACHE_L2_CACHE_CACHESIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256_S  0
+/** CACHE_L2_CACHE_CACHESIZE_512 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512    (BIT(1))
+#define CACHE_L2_CACHE_CACHESIZE_512_M  (CACHE_L2_CACHE_CACHESIZE_512_V << CACHE_L2_CACHE_CACHESIZE_512_S)
+#define CACHE_L2_CACHE_CACHESIZE_512_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512_S  1
+/** CACHE_L2_CACHE_CACHESIZE_1K : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1K    (BIT(2))
+#define CACHE_L2_CACHE_CACHESIZE_1K_M  (CACHE_L2_CACHE_CACHESIZE_1K_V << CACHE_L2_CACHE_CACHESIZE_1K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1K_S  2
+/** CACHE_L2_CACHE_CACHESIZE_2K : HRO; bitpos: [3]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_2K    (BIT(3))
+#define CACHE_L2_CACHE_CACHESIZE_2K_M  (CACHE_L2_CACHE_CACHESIZE_2K_V << CACHE_L2_CACHE_CACHESIZE_2K_S)
+#define CACHE_L2_CACHE_CACHESIZE_2K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_2K_S  3
+/** CACHE_L2_CACHE_CACHESIZE_4K : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_4K    (BIT(4))
+#define CACHE_L2_CACHE_CACHESIZE_4K_M  (CACHE_L2_CACHE_CACHESIZE_4K_V << CACHE_L2_CACHE_CACHESIZE_4K_S)
+#define CACHE_L2_CACHE_CACHESIZE_4K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_4K_S  4
+/** CACHE_L2_CACHE_CACHESIZE_8K : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_8K    (BIT(5))
+#define CACHE_L2_CACHE_CACHESIZE_8K_M  (CACHE_L2_CACHE_CACHESIZE_8K_V << CACHE_L2_CACHE_CACHESIZE_8K_S)
+#define CACHE_L2_CACHE_CACHESIZE_8K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_8K_S  5
+/** CACHE_L2_CACHE_CACHESIZE_16K : HRO; bitpos: [6]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_16K    (BIT(6))
+#define CACHE_L2_CACHE_CACHESIZE_16K_M  (CACHE_L2_CACHE_CACHESIZE_16K_V << CACHE_L2_CACHE_CACHESIZE_16K_S)
+#define CACHE_L2_CACHE_CACHESIZE_16K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_16K_S  6
+/** CACHE_L2_CACHE_CACHESIZE_32K : HRO; bitpos: [7]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_32K    (BIT(7))
+#define CACHE_L2_CACHE_CACHESIZE_32K_M  (CACHE_L2_CACHE_CACHESIZE_32K_V << CACHE_L2_CACHE_CACHESIZE_32K_S)
+#define CACHE_L2_CACHE_CACHESIZE_32K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_32K_S  7
+/** CACHE_L2_CACHE_CACHESIZE_64K : HRO; bitpos: [8]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_64K    (BIT(8))
+#define CACHE_L2_CACHE_CACHESIZE_64K_M  (CACHE_L2_CACHE_CACHESIZE_64K_V << CACHE_L2_CACHE_CACHESIZE_64K_S)
+#define CACHE_L2_CACHE_CACHESIZE_64K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_64K_S  8
+/** CACHE_L2_CACHE_CACHESIZE_128K : HRO; bitpos: [9]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_128K    (BIT(9))
+#define CACHE_L2_CACHE_CACHESIZE_128K_M  (CACHE_L2_CACHE_CACHESIZE_128K_V << CACHE_L2_CACHE_CACHESIZE_128K_S)
+#define CACHE_L2_CACHE_CACHESIZE_128K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_128K_S  9
+/** CACHE_L2_CACHE_CACHESIZE_256K : HRO; bitpos: [10]; default: 1;
+ *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_256K    (BIT(10))
+#define CACHE_L2_CACHE_CACHESIZE_256K_M  (CACHE_L2_CACHE_CACHESIZE_256K_V << CACHE_L2_CACHE_CACHESIZE_256K_S)
+#define CACHE_L2_CACHE_CACHESIZE_256K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_256K_S  10
+/** CACHE_L2_CACHE_CACHESIZE_512K : HRO; bitpos: [11]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_512K    (BIT(11))
+#define CACHE_L2_CACHE_CACHESIZE_512K_M  (CACHE_L2_CACHE_CACHESIZE_512K_V << CACHE_L2_CACHE_CACHESIZE_512K_S)
+#define CACHE_L2_CACHE_CACHESIZE_512K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_512K_S  11
+/** CACHE_L2_CACHE_CACHESIZE_1024K : HRO; bitpos: [12]; default: 0;
+ *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_CACHESIZE_1024K    (BIT(12))
+#define CACHE_L2_CACHE_CACHESIZE_1024K_M  (CACHE_L2_CACHE_CACHESIZE_1024K_V << CACHE_L2_CACHE_CACHESIZE_1024K_S)
+#define CACHE_L2_CACHE_CACHESIZE_1024K_V  0x00000001U
+#define CACHE_L2_CACHE_CACHESIZE_1024K_S  12
+
+/** CACHE_L2_CACHE_BLOCKSIZE_CONF_REG register
+ *  L2 Cache BlockSize mode configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_CONF_REG (DR_REG_CACHE_BASE + 0x280)
+/** CACHE_L2_CACHE_BLOCKSIZE_8 : HRO; bitpos: [0]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_8    (BIT(0))
+#define CACHE_L2_CACHE_BLOCKSIZE_8_M  (CACHE_L2_CACHE_BLOCKSIZE_8_V << CACHE_L2_CACHE_BLOCKSIZE_8_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_8_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_8_S  0
+/** CACHE_L2_CACHE_BLOCKSIZE_16 : HRO; bitpos: [1]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_16    (BIT(1))
+#define CACHE_L2_CACHE_BLOCKSIZE_16_M  (CACHE_L2_CACHE_BLOCKSIZE_16_V << CACHE_L2_CACHE_BLOCKSIZE_16_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_16_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_16_S  1
+/** CACHE_L2_CACHE_BLOCKSIZE_32 : HRO; bitpos: [2]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_32    (BIT(2))
+#define CACHE_L2_CACHE_BLOCKSIZE_32_M  (CACHE_L2_CACHE_BLOCKSIZE_32_V << CACHE_L2_CACHE_BLOCKSIZE_32_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_32_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_32_S  2
+/** CACHE_L2_CACHE_BLOCKSIZE_64 : HRO; bitpos: [3]; default: 1;
+ *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+ *  other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_64    (BIT(3))
+#define CACHE_L2_CACHE_BLOCKSIZE_64_M  (CACHE_L2_CACHE_BLOCKSIZE_64_V << CACHE_L2_CACHE_BLOCKSIZE_64_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_64_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_64_S  3
+/** CACHE_L2_CACHE_BLOCKSIZE_128 : HRO; bitpos: [4]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_128    (BIT(4))
+#define CACHE_L2_CACHE_BLOCKSIZE_128_M  (CACHE_L2_CACHE_BLOCKSIZE_128_V << CACHE_L2_CACHE_BLOCKSIZE_128_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_128_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_128_S  4
+/** CACHE_L2_CACHE_BLOCKSIZE_256 : HRO; bitpos: [5]; default: 0;
+ *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+ *  all other fields within this register is onehot.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_BLOCKSIZE_256    (BIT(5))
+#define CACHE_L2_CACHE_BLOCKSIZE_256_M  (CACHE_L2_CACHE_BLOCKSIZE_256_V << CACHE_L2_CACHE_BLOCKSIZE_256_S)
+#define CACHE_L2_CACHE_BLOCKSIZE_256_V  0x00000001U
+#define CACHE_L2_CACHE_BLOCKSIZE_256_S  5
+
+/** CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG register
+ *  Cache wrap around control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_CACHE_BASE + 0x284)
+/** CACHE_L2_CACHE_WRAP : HRO; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to enable L2-Cache wrap around mode.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_WRAP    (BIT(5))
+#define CACHE_L2_CACHE_WRAP_M  (CACHE_L2_CACHE_WRAP_V << CACHE_L2_CACHE_WRAP_S)
+#define CACHE_L2_CACHE_WRAP_V  0x00000001U
+#define CACHE_L2_CACHE_WRAP_S  5
+
+/** CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG register
+ *  Cache wrap around control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_MISS_ACCESS_CTRL_REG (DR_REG_CACHE_BASE + 0x288)
+/** CACHE_L2_CACHE_MISS_DISABLE_ACCESS : HRO; bitpos: [5]; default: 0;
+ *  Set this bit as 1 to disable early restart of  L2-Cache
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS    (BIT(5))
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_M  (CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V << CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S)
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_V  0x00000001U
+#define CACHE_L2_CACHE_MISS_DISABLE_ACCESS_S  5
+
+/** CACHE_L2_CACHE_FREEZE_CTRL_REG register
+ *  Cache Freeze control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_FREEZE_CTRL_REG (DR_REG_CACHE_BASE + 0x28c)
+/** CACHE_L2_CACHE_FREEZE_EN : HRO; bitpos: [20]; default: 0;
+ *  Configures freeze operation on L2-Cache. It can be cleared by software.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FREEZE_EN    (BIT(20))
+#define CACHE_L2_CACHE_FREEZE_EN_M  (CACHE_L2_CACHE_FREEZE_EN_V << CACHE_L2_CACHE_FREEZE_EN_S)
+#define CACHE_L2_CACHE_FREEZE_EN_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_EN_S  20
+/** CACHE_L2_CACHE_FREEZE_MODE : HRO; bitpos: [21]; default: 0;
+ *  Configures mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a
+ *  miss-access will stuck.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FREEZE_MODE    (BIT(21))
+#define CACHE_L2_CACHE_FREEZE_MODE_M  (CACHE_L2_CACHE_FREEZE_MODE_V << CACHE_L2_CACHE_FREEZE_MODE_S)
+#define CACHE_L2_CACHE_FREEZE_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_MODE_S  21
+/** CACHE_L2_CACHE_FREEZE_DONE : RO; bitpos: [22]; default: 0;
+ *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FREEZE_DONE    (BIT(22))
+#define CACHE_L2_CACHE_FREEZE_DONE_M  (CACHE_L2_CACHE_FREEZE_DONE_V << CACHE_L2_CACHE_FREEZE_DONE_S)
+#define CACHE_L2_CACHE_FREEZE_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_FREEZE_DONE_S  22
+
+/** CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG register
+ *  Cache data memory access configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x290)
+/** CACHE_L2_CACHE_DATA_MEM_RD_EN : HRO; bitpos: [20]; default: 1;
+ *  Configures config-bus read L2-Cache data memoryory. 0: disable, 1: enable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_M  (CACHE_L2_CACHE_DATA_MEM_RD_EN_V << CACHE_L2_CACHE_DATA_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_DATA_MEM_WR_EN : HRO; bitpos: [21]; default: 1;
+ *  Configures config-bus write L2-Cache data memoryory. 0: disable, 1: enable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_M  (CACHE_L2_CACHE_DATA_MEM_WR_EN_V << CACHE_L2_CACHE_DATA_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_DATA_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG register
+ *  Cache tag memory access configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_ACS_CONF_REG (DR_REG_CACHE_BASE + 0x294)
+/** CACHE_L2_CACHE_TAG_MEM_RD_EN : HRO; bitpos: [20]; default: 1;
+ *  Configures config-bus read L2-Cache tag memoryory. 0: disable, 1: enable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN    (BIT(20))
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_M  (CACHE_L2_CACHE_TAG_MEM_RD_EN_V << CACHE_L2_CACHE_TAG_MEM_RD_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_RD_EN_S  20
+/** CACHE_L2_CACHE_TAG_MEM_WR_EN : HRO; bitpos: [21]; default: 1;
+ *  Configures config-bus write L2-Cache tag memoryory. 0: disable, 1: enable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN    (BIT(21))
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_M  (CACHE_L2_CACHE_TAG_MEM_WR_EN_V << CACHE_L2_CACHE_TAG_MEM_WR_EN_S)
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_MEM_WR_EN_S  21
+
+/** CACHE_L2_CACHE_PRELOCK_CONF_REG register
+ *  L2 Cache prelock configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_CONF_REG (DR_REG_CACHE_BASE + 0x298)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_EN : HRO; bitpos: [0]; default: 0;
+ *  Configures the first section of prelock function on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN    (BIT(0))
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT0_EN_V << CACHE_L2_CACHE_PRELOCK_SCT0_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT0_EN_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_EN : HRO; bitpos: [1]; default: 0;
+ *  Configures the second section of prelock function on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN    (BIT(1))
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_M  (CACHE_L2_CACHE_PRELOCK_SCT1_EN_V << CACHE_L2_CACHE_PRELOCK_SCT1_EN_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOCK_SCT1_EN_S  1
+/** CACHE_L2_CACHE_PRELOCK_RGID : HRO; bitpos: [5:2]; default: 0;
+ *  Configures the gid of l2 cache prelock.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_M  (CACHE_L2_CACHE_PRELOCK_RGID_V << CACHE_L2_CACHE_PRELOCK_RGID_S)
+#define CACHE_L2_CACHE_PRELOCK_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOCK_RGID_S  2
+
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG register
+ *  L2 Cache prelock section0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x29c)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section of prelock on L2-Cache, which
+ *  should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG register
+ *  L2 Cache prelock section1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2a0)
+/** CACHE_L2_CACHE_PRELOCK_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section of prelock on L2-Cache, which
+ *  should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_M  (CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V << CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG register
+ *  L2 Cache prelock section size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT_SIZE_REG (DR_REG_CACHE_BASE + 0x2a4)
+/** CACHE_L2_CACHE_PRELOCK_SCT0_SIZE : HRO; bitpos: [15:0]; default: 65535;
+ *  Configures the size of the first section of prelock on L2-Cache, which should be
+ *  used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT0_SIZE_S  0
+/** CACHE_L2_CACHE_PRELOCK_SCT1_SIZE : HRO; bitpos: [31:16]; default: 65535;
+ *  Configures the size of the second section of prelock on L2-Cache, which should be
+ *  used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_M  (CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V << CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOCK_SCT1_SIZE_S  16
+
+/** CACHE_L2_CACHE_PRELOAD_CTRL_REG register
+ *  L2 Cache preload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2a8)
+/** CACHE_L2_CACHE_PRELOAD_ENA : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures preload operation on L2-Cache. It will be cleared by hardware
+ *  automatically after preload operation is done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_PRELOAD_ENA_M  (CACHE_L2_CACHE_PRELOAD_ENA_V << CACHE_L2_CACHE_PRELOAD_ENA_S)
+#define CACHE_L2_CACHE_PRELOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ENA_S  0
+/** CACHE_L2_CACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether preload operation is finished or not. 0: not
+ *  finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_PRELOAD_DONE_M  (CACHE_L2_CACHE_PRELOAD_DONE_V << CACHE_L2_CACHE_PRELOAD_DONE_S)
+#define CACHE_L2_CACHE_PRELOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_DONE_S  1
+/** CACHE_L2_CACHE_PRELOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of preload operation. 0: ascending, 1: descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_PRELOAD_ORDER_M  (CACHE_L2_CACHE_PRELOAD_ORDER_V << CACHE_L2_CACHE_PRELOAD_ORDER_S)
+#define CACHE_L2_CACHE_PRELOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_ORDER_S  2
+/** CACHE_L2_CACHE_PRELOAD_RGID : HRO; bitpos: [6:3]; default: 0;
+ *  Configures the gid of l2 cache preload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_M  (CACHE_L2_CACHE_PRELOAD_RGID_V << CACHE_L2_CACHE_PRELOAD_RGID_S)
+#define CACHE_L2_CACHE_PRELOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_PRELOAD_RGID_S  3
+/** CACHE_L2_CACHE_PRELOAD_MODE : HRO; bitpos: [7]; default: 0;
+ *  Configures the mode of l2 cache preload, 0: load data from next level memory, 1:
+ *  not load data from next level memory.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_MODE    (BIT(7))
+#define CACHE_L2_CACHE_PRELOAD_MODE_M  (CACHE_L2_CACHE_PRELOAD_MODE_V << CACHE_L2_CACHE_PRELOAD_MODE_S)
+#define CACHE_L2_CACHE_PRELOAD_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_PRELOAD_MODE_S  7
+
+/** CACHE_L2_CACHE_PRELOAD_ADDR_REG register
+ *  L2 Cache preload address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR_REG (DR_REG_CACHE_BASE + 0x2ac)
+/** CACHE_L2_CACHE_PRELOAD_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of preload on L2-Cache, which should be used together
+ *  with L2_CACHE_PRELOAD_SIZE_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_M  (CACHE_L2_CACHE_PRELOAD_ADDR_V << CACHE_L2_CACHE_PRELOAD_ADDR_S)
+#define CACHE_L2_CACHE_PRELOAD_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_PRELOAD_ADDR_S  0
+
+/** CACHE_L2_CACHE_PRELOAD_SIZE_REG register
+ *  L2 Cache preload size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE_REG (DR_REG_CACHE_BASE + 0x2b0)
+/** CACHE_L2_CACHE_PRELOAD_SIZE : HRO; bitpos: [15:0]; default: 0;
+ *  Configures the size of the first section of prelock on L2-Cache, which should be
+ *  used together with L2_CACHE_PRELOAD_ADDR_REG
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_SIZE    0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_M  (CACHE_L2_CACHE_PRELOAD_SIZE_V << CACHE_L2_CACHE_PRELOAD_SIZE_S)
+#define CACHE_L2_CACHE_PRELOAD_SIZE_V  0x0000FFFFU
+#define CACHE_L2_CACHE_PRELOAD_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_CTRL_REG register
+ *  L2 Cache autoload-operation control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_CTRL_REG (DR_REG_CACHE_BASE + 0x2b4)
+/** CACHE_L2_CACHE_AUTOLOAD_ENA : HRO; bitpos: [0]; default: 0;
+ *  Configures and disable autoload operation on L2-Cache.  1: enable, 0: disable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ENA    (BIT(0))
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_ENA_V << CACHE_L2_CACHE_AUTOLOAD_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ENA_S  0
+/** CACHE_L2_CACHE_AUTOLOAD_DONE : RO; bitpos: [1]; default: 1;
+ *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+ *  not. 0: not finished. 1: finished.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_DONE    (BIT(1))
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_M  (CACHE_L2_CACHE_AUTOLOAD_DONE_V << CACHE_L2_CACHE_AUTOLOAD_DONE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_DONE_S  1
+/** CACHE_L2_CACHE_AUTOLOAD_ORDER : HRO; bitpos: [2]; default: 0;
+ *  Configures the direction of autoload operation on L2-Cache. 0: ascending. 1:
+ *  descending.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER    (BIT(2))
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_M  (CACHE_L2_CACHE_AUTOLOAD_ORDER_V << CACHE_L2_CACHE_AUTOLOAD_ORDER_S)
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_ORDER_S  2
+/** CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE : HRO; bitpos: [4:3]; default: 0;
+ *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+ *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE    0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_M  (CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V << CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_V  0x00000003U
+#define CACHE_L2_CACHE_AUTOLOAD_TRIGGER_MODE_S  3
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA : HRO; bitpos: [8]; default: 0;
+ *  Configures the first section for autoload operation on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA    (BIT(8))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ENA_S  8
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA : HRO; bitpos: [9]; default: 0;
+ *  Configures the second section for autoload operation on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA    (BIT(9))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ENA_S  9
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA : HRO; bitpos: [10]; default: 0;
+ *  Configures the third section for autoload operation on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA    (BIT(10))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ENA_S  10
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA : HRO; bitpos: [11]; default: 0;
+ *  Configures the fourth section for autoload operation on L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA    (BIT(11))
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ENA_S  11
+/** CACHE_L2_CACHE_AUTOLOAD_RGID : HRO; bitpos: [15:12]; default: 0;
+ *  Configures the gid of l2 cache autoload.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_RGID    0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_M  (CACHE_L2_CACHE_AUTOLOAD_RGID_V << CACHE_L2_CACHE_AUTOLOAD_RGID_S)
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_V  0x0000000FU
+#define CACHE_L2_CACHE_AUTOLOAD_RGID_S  12
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG register
+ *  L2 Cache autoload section 0 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_CACHE_BASE + 0x2b8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the first section for autoload operation on
+ *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and
+ *  L2_CACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG register
+ *  L2 Cache autoload section 0 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_CACHE_BASE + 0x2bc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the first section for autoload operation on L2-Cache. Note
+ *  that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and
+ *  L2_CACHE_AUTOLOAD_SCT0_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG register
+ *  L2 Cache autoload section 1 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_CACHE_BASE + 0x2c0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the second section for autoload operation on
+ *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and
+ *  L2_CACHE_AUTOLOAD_SCT1_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG register
+ *  L2 Cache autoload section 1 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_CACHE_BASE + 0x2c4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the second section for autoload operation on L2-Cache. Note
+ *  that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and
+ *  L2_CACHE_AUTOLOAD_SCT1_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG register
+ *  L2 Cache autoload section 2 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_REG (DR_REG_CACHE_BASE + 0x2c8)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the third section for autoload operation on
+ *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and
+ *  L2_CACHE_AUTOLOAD_SCT2_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG register
+ *  L2 Cache autoload section 2 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_REG (DR_REG_CACHE_BASE + 0x2cc)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the third section for autoload operation on L2-Cache. Note
+ *  that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and
+ *  L2_CACHE_AUTOLOAD_SCT2_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT2_SIZE_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG register
+ *  L2 Cache autoload section 3 address configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_REG (DR_REG_CACHE_BASE + 0x2d0)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Configures the start address of the fourth section for autoload operation on
+ *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and
+ *  L2_CACHE_AUTOLOAD_SCT3_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_ADDR_S  0
+
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG register
+ *  L2 Cache autoload section 3 size configure register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_REG (DR_REG_CACHE_BASE + 0x2d4)
+/** CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE : HRO; bitpos: [27:0]; default: 0;
+ *  Configures the size of the fourth section for autoload operation on L2-Cache. Note
+ *  that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and
+ *  L2_CACHE_AUTOLOAD_SCT3_ENA.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE    0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_M  (CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V << CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S)
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_V  0x0FFFFFFFU
+#define CACHE_L2_CACHE_AUTOLOAD_SCT3_SIZE_S  0
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG register
+ *  Cache Access Counter Interrupt enable register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2d8)
+/** CACHE_L2_IBUS0_OVF_INT_ENA : HRO; bitpos: [8]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+ *  bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ENA_M  (CACHE_L2_IBUS0_OVF_INT_ENA_V << CACHE_L2_IBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ENA_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+ *  bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ENA_M  (CACHE_L2_IBUS1_OVF_INT_ENA_V << CACHE_L2_IBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ENA_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ENA_M  (CACHE_L2_IBUS2_OVF_INT_ENA_V << CACHE_L2_IBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ENA_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ENA_M  (CACHE_L2_IBUS3_OVF_INT_ENA_V << CACHE_L2_IBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_IBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ENA_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+ *  bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ENA_M  (CACHE_L2_DBUS0_OVF_INT_ENA_V << CACHE_L2_DBUS0_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS0_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ENA_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ENA : HRO; bitpos: [13]; default: 0;
+ *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+ *  bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ENA_M  (CACHE_L2_DBUS1_OVF_INT_ENA_V << CACHE_L2_DBUS1_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS1_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ENA_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ENA_M  (CACHE_L2_DBUS2_OVF_INT_ENA_V << CACHE_L2_DBUS2_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS2_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ENA_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ENA_M  (CACHE_L2_DBUS3_OVF_INT_ENA_V << CACHE_L2_DBUS3_OVF_INT_ENA_S)
+#define CACHE_L2_DBUS3_OVF_INT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ENA_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG register
+ *  Cache Access Counter Interrupt clear register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2dc)
+/** CACHE_L2_IBUS0_OVF_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_CLR    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_CLR_M  (CACHE_L2_IBUS0_OVF_INT_CLR_V << CACHE_L2_IBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_CLR_S  8
+/** CACHE_L2_IBUS1_OVF_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_CLR    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_CLR_M  (CACHE_L2_IBUS1_OVF_INT_CLR_V << CACHE_L2_IBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_CLR_S  9
+/** CACHE_L2_IBUS2_OVF_INT_CLR : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_CLR    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_CLR_M  (CACHE_L2_IBUS2_OVF_INT_CLR_V << CACHE_L2_IBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_CLR_S  10
+/** CACHE_L2_IBUS3_OVF_INT_CLR : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_CLR    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_CLR_M  (CACHE_L2_IBUS3_OVF_INT_CLR_V << CACHE_L2_IBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_IBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_CLR_S  11
+/** CACHE_L2_DBUS0_OVF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_CLR    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_CLR_M  (CACHE_L2_DBUS0_OVF_INT_CLR_V << CACHE_L2_DBUS0_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS0_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_CLR_S  12
+/** CACHE_L2_DBUS1_OVF_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+ *  to bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_CLR    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_CLR_M  (CACHE_L2_DBUS1_OVF_INT_CLR_V << CACHE_L2_DBUS1_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS1_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_CLR_S  13
+/** CACHE_L2_DBUS2_OVF_INT_CLR : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_CLR    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_CLR_M  (CACHE_L2_DBUS2_OVF_INT_CLR_V << CACHE_L2_DBUS2_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS2_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_CLR_S  14
+/** CACHE_L2_DBUS3_OVF_INT_CLR : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_CLR    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_CLR_M  (CACHE_L2_DBUS3_OVF_INT_CLR_V << CACHE_L2_DBUS3_OVF_INT_CLR_S)
+#define CACHE_L2_DBUS3_OVF_INT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_CLR_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG register
+ *  Cache Access Counter Interrupt raw register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2e0)
+/** CACHE_L2_IBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-ICache0.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_RAW    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_RAW_M  (CACHE_L2_IBUS0_OVF_INT_RAW_V << CACHE_L2_IBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_RAW_S  8
+/** CACHE_L2_IBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-ICache1.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_RAW    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_RAW_M  (CACHE_L2_IBUS1_OVF_INT_RAW_V << CACHE_L2_IBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_RAW_S  9
+/** CACHE_L2_IBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_RAW    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_RAW_M  (CACHE_L2_IBUS2_OVF_INT_RAW_V << CACHE_L2_IBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_RAW_S  10
+/** CACHE_L2_IBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_RAW    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_RAW_M  (CACHE_L2_IBUS3_OVF_INT_RAW_V << CACHE_L2_IBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_IBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_RAW_S  11
+/** CACHE_L2_DBUS0_OVF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus0 accesses L2-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_RAW    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_RAW_M  (CACHE_L2_DBUS0_OVF_INT_RAW_V << CACHE_L2_DBUS0_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS0_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_RAW_S  12
+/** CACHE_L2_DBUS1_OVF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus1 accesses L2-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_RAW    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_RAW_M  (CACHE_L2_DBUS1_OVF_INT_RAW_V << CACHE_L2_DBUS1_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS1_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_RAW_S  13
+/** CACHE_L2_DBUS2_OVF_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus2 accesses L2-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_RAW    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_RAW_M  (CACHE_L2_DBUS2_OVF_INT_RAW_V << CACHE_L2_DBUS2_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS2_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_RAW_S  14
+/** CACHE_L2_DBUS3_OVF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0;
+ *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+ *  due to bus3 accesses L2-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_RAW    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_RAW_M  (CACHE_L2_DBUS3_OVF_INT_RAW_V << CACHE_L2_DBUS3_OVF_INT_RAW_S)
+#define CACHE_L2_DBUS3_OVF_INT_RAW_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_RAW_S  15
+
+/** CACHE_L2_CACHE_ACS_CNT_INT_ST_REG register
+ *  Cache Access Counter Interrupt status register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_CNT_INT_ST_REG (DR_REG_CACHE_BASE + 0x2e4)
+/** CACHE_L2_IBUS0_OVF_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_OVF_INT_ST    (BIT(8))
+#define CACHE_L2_IBUS0_OVF_INT_ST_M  (CACHE_L2_IBUS0_OVF_INT_ST_V << CACHE_L2_IBUS0_OVF_INT_ST_S)
+#define CACHE_L2_IBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS0_OVF_INT_ST_S  8
+/** CACHE_L2_IBUS1_OVF_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_OVF_INT_ST    (BIT(9))
+#define CACHE_L2_IBUS1_OVF_INT_ST_M  (CACHE_L2_IBUS1_OVF_INT_ST_V << CACHE_L2_IBUS1_OVF_INT_ST_S)
+#define CACHE_L2_IBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS1_OVF_INT_ST_S  9
+/** CACHE_L2_IBUS2_OVF_INT_ST : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_OVF_INT_ST    (BIT(10))
+#define CACHE_L2_IBUS2_OVF_INT_ST_M  (CACHE_L2_IBUS2_OVF_INT_ST_V << CACHE_L2_IBUS2_OVF_INT_ST_S)
+#define CACHE_L2_IBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS2_OVF_INT_ST_S  10
+/** CACHE_L2_IBUS3_OVF_INT_ST : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_OVF_INT_ST    (BIT(11))
+#define CACHE_L2_IBUS3_OVF_INT_ST_M  (CACHE_L2_IBUS3_OVF_INT_ST_V << CACHE_L2_IBUS3_OVF_INT_ST_S)
+#define CACHE_L2_IBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_IBUS3_OVF_INT_ST_S  11
+/** CACHE_L2_DBUS0_OVF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus0 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_OVF_INT_ST    (BIT(12))
+#define CACHE_L2_DBUS0_OVF_INT_ST_M  (CACHE_L2_DBUS0_OVF_INT_ST_V << CACHE_L2_DBUS0_OVF_INT_ST_S)
+#define CACHE_L2_DBUS0_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS0_OVF_INT_ST_S  12
+/** CACHE_L2_DBUS1_OVF_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The bit indicates the interrupt status of one of counters overflow that occurs in
+ *  L2-Cache due to bus1 accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_OVF_INT_ST    (BIT(13))
+#define CACHE_L2_DBUS1_OVF_INT_ST_M  (CACHE_L2_DBUS1_OVF_INT_ST_V << CACHE_L2_DBUS1_OVF_INT_ST_S)
+#define CACHE_L2_DBUS1_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS1_OVF_INT_ST_S  13
+/** CACHE_L2_DBUS2_OVF_INT_ST : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_OVF_INT_ST    (BIT(14))
+#define CACHE_L2_DBUS2_OVF_INT_ST_M  (CACHE_L2_DBUS2_OVF_INT_ST_V << CACHE_L2_DBUS2_OVF_INT_ST_S)
+#define CACHE_L2_DBUS2_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS2_OVF_INT_ST_S  14
+/** CACHE_L2_DBUS3_OVF_INT_ST : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_OVF_INT_ST    (BIT(15))
+#define CACHE_L2_DBUS3_OVF_INT_ST_M  (CACHE_L2_DBUS3_OVF_INT_ST_V << CACHE_L2_DBUS3_OVF_INT_ST_S)
+#define CACHE_L2_DBUS3_OVF_INT_ST_V  0x00000001U
+#define CACHE_L2_DBUS3_OVF_INT_ST_S  15
+
+/** CACHE_L2_CACHE_ACS_FAIL_CTRL_REG register
+ *  Cache Access Fail Configuration register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CTRL_REG (DR_REG_CACHE_BASE + 0x2e8)
+/** CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE : HRO; bitpos: [0]; default: 0;
+ *  Configures l2 cache access fail check mode. 0: the access fail is not propagated to
+ *  the request, 1: the access fail is propagated to the request
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE    (BIT(0))
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_M  (CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V << CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S)
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_V  0x00000001U
+#define CACHE_L2_CACHE_ACS_FAIL_CHECK_MODE_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG register
+ *  Cache Access Fail Interrupt enable register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG (DR_REG_CACHE_BASE + 0x2ec)
+/** CACHE_L2_CACHE_FAIL_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  Configures interrupt of access fail that occurs in L2-Cache due to l1 cache
+ *  accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ENA_M  (CACHE_L2_CACHE_FAIL_INT_ENA_V << CACHE_L2_CACHE_FAIL_INT_ENA_S)
+#define CACHE_L2_CACHE_FAIL_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ENA_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG register
+ *  L1-Cache Access Fail Interrupt clear register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG (DR_REG_CACHE_BASE + 0x2f0)
+/** CACHE_L2_CACHE_FAIL_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+ *  cache accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_CLR_M  (CACHE_L2_CACHE_FAIL_INT_CLR_V << CACHE_L2_CACHE_FAIL_INT_CLR_S)
+#define CACHE_L2_CACHE_FAIL_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_CLR_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG register
+ *  Cache Access Fail Interrupt raw register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_RAW_REG (DR_REG_CACHE_BASE + 0x2f4)
+/** CACHE_L2_CACHE_FAIL_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_RAW_M  (CACHE_L2_CACHE_FAIL_INT_RAW_V << CACHE_L2_CACHE_FAIL_INT_RAW_S)
+#define CACHE_L2_CACHE_FAIL_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_RAW_S  5
+
+/** CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG register
+ *  Cache Access Fail Interrupt status register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_INT_ST_REG (DR_REG_CACHE_BASE + 0x2f8)
+/** CACHE_L2_CACHE_FAIL_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+ *  to l1 cache accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_FAIL_INT_ST_M  (CACHE_L2_CACHE_FAIL_INT_ST_V << CACHE_L2_CACHE_FAIL_INT_ST_S)
+#define CACHE_L2_CACHE_FAIL_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_FAIL_INT_ST_S  5
+
+/** CACHE_L2_CACHE_ACS_CNT_CTRL_REG register
+ *  Cache Access Counter enable and clear register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_CNT_CTRL_REG (DR_REG_CACHE_BASE + 0x2fc)
+/** CACHE_L2_IBUS0_CNT_ENA : HRO; bitpos: [8]; default: 0;
+ *  Configures ibus0 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_CNT_ENA    (BIT(8))
+#define CACHE_L2_IBUS0_CNT_ENA_M  (CACHE_L2_IBUS0_CNT_ENA_V << CACHE_L2_IBUS0_CNT_ENA_S)
+#define CACHE_L2_IBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_ENA_S  8
+/** CACHE_L2_IBUS1_CNT_ENA : HRO; bitpos: [9]; default: 0;
+ *  Configures ibus1 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_CNT_ENA    (BIT(9))
+#define CACHE_L2_IBUS1_CNT_ENA_M  (CACHE_L2_IBUS1_CNT_ENA_V << CACHE_L2_IBUS1_CNT_ENA_S)
+#define CACHE_L2_IBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_ENA_S  9
+/** CACHE_L2_IBUS2_CNT_ENA : HRO; bitpos: [10]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_CNT_ENA    (BIT(10))
+#define CACHE_L2_IBUS2_CNT_ENA_M  (CACHE_L2_IBUS2_CNT_ENA_V << CACHE_L2_IBUS2_CNT_ENA_S)
+#define CACHE_L2_IBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_ENA_S  10
+/** CACHE_L2_IBUS3_CNT_ENA : HRO; bitpos: [11]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_CNT_ENA    (BIT(11))
+#define CACHE_L2_IBUS3_CNT_ENA_M  (CACHE_L2_IBUS3_CNT_ENA_V << CACHE_L2_IBUS3_CNT_ENA_S)
+#define CACHE_L2_IBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_ENA_S  11
+/** CACHE_L2_DBUS0_CNT_ENA : HRO; bitpos: [12]; default: 0;
+ *  Configures dbus0 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_CNT_ENA    (BIT(12))
+#define CACHE_L2_DBUS0_CNT_ENA_M  (CACHE_L2_DBUS0_CNT_ENA_V << CACHE_L2_DBUS0_CNT_ENA_S)
+#define CACHE_L2_DBUS0_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_ENA_S  12
+/** CACHE_L2_DBUS1_CNT_ENA : HRO; bitpos: [13]; default: 0;
+ *  Configures dbus1 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_CNT_ENA    (BIT(13))
+#define CACHE_L2_DBUS1_CNT_ENA_M  (CACHE_L2_DBUS1_CNT_ENA_V << CACHE_L2_DBUS1_CNT_ENA_S)
+#define CACHE_L2_DBUS1_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_ENA_S  13
+/** CACHE_L2_DBUS2_CNT_ENA : HRO; bitpos: [14]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_CNT_ENA    (BIT(14))
+#define CACHE_L2_DBUS2_CNT_ENA_M  (CACHE_L2_DBUS2_CNT_ENA_V << CACHE_L2_DBUS2_CNT_ENA_S)
+#define CACHE_L2_DBUS2_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_ENA_S  14
+/** CACHE_L2_DBUS3_CNT_ENA : HRO; bitpos: [15]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_CNT_ENA    (BIT(15))
+#define CACHE_L2_DBUS3_CNT_ENA_M  (CACHE_L2_DBUS3_CNT_ENA_V << CACHE_L2_DBUS3_CNT_ENA_S)
+#define CACHE_L2_DBUS3_CNT_ENA_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_ENA_S  15
+/** CACHE_L2_IBUS0_CNT_CLR : WT; bitpos: [24]; default: 0;
+ *  The bit is used to clear ibus0 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_CNT_CLR    (BIT(24))
+#define CACHE_L2_IBUS0_CNT_CLR_M  (CACHE_L2_IBUS0_CNT_CLR_V << CACHE_L2_IBUS0_CNT_CLR_S)
+#define CACHE_L2_IBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS0_CNT_CLR_S  24
+/** CACHE_L2_IBUS1_CNT_CLR : WT; bitpos: [25]; default: 0;
+ *  The bit is used to clear ibus1 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_CNT_CLR    (BIT(25))
+#define CACHE_L2_IBUS1_CNT_CLR_M  (CACHE_L2_IBUS1_CNT_CLR_V << CACHE_L2_IBUS1_CNT_CLR_S)
+#define CACHE_L2_IBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS1_CNT_CLR_S  25
+/** CACHE_L2_IBUS2_CNT_CLR : HRO; bitpos: [26]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_CNT_CLR    (BIT(26))
+#define CACHE_L2_IBUS2_CNT_CLR_M  (CACHE_L2_IBUS2_CNT_CLR_V << CACHE_L2_IBUS2_CNT_CLR_S)
+#define CACHE_L2_IBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS2_CNT_CLR_S  26
+/** CACHE_L2_IBUS3_CNT_CLR : HRO; bitpos: [27]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_CNT_CLR    (BIT(27))
+#define CACHE_L2_IBUS3_CNT_CLR_M  (CACHE_L2_IBUS3_CNT_CLR_V << CACHE_L2_IBUS3_CNT_CLR_S)
+#define CACHE_L2_IBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_IBUS3_CNT_CLR_S  27
+/** CACHE_L2_DBUS0_CNT_CLR : WT; bitpos: [28]; default: 0;
+ *  The bit is used to clear dbus0 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_CNT_CLR    (BIT(28))
+#define CACHE_L2_DBUS0_CNT_CLR_M  (CACHE_L2_DBUS0_CNT_CLR_V << CACHE_L2_DBUS0_CNT_CLR_S)
+#define CACHE_L2_DBUS0_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS0_CNT_CLR_S  28
+/** CACHE_L2_DBUS1_CNT_CLR : WT; bitpos: [29]; default: 0;
+ *  The bit is used to clear dbus1 counter in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_CNT_CLR    (BIT(29))
+#define CACHE_L2_DBUS1_CNT_CLR_M  (CACHE_L2_DBUS1_CNT_CLR_V << CACHE_L2_DBUS1_CNT_CLR_S)
+#define CACHE_L2_DBUS1_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS1_CNT_CLR_S  29
+/** CACHE_L2_DBUS2_CNT_CLR : HRO; bitpos: [30]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_CNT_CLR    (BIT(30))
+#define CACHE_L2_DBUS2_CNT_CLR_M  (CACHE_L2_DBUS2_CNT_CLR_V << CACHE_L2_DBUS2_CNT_CLR_S)
+#define CACHE_L2_DBUS2_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS2_CNT_CLR_S  30
+/** CACHE_L2_DBUS3_CNT_CLR : HRO; bitpos: [31]; default: 0;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_CNT_CLR    (BIT(31))
+#define CACHE_L2_DBUS3_CNT_CLR_M  (CACHE_L2_DBUS3_CNT_CLR_V << CACHE_L2_DBUS3_CNT_CLR_S)
+#define CACHE_L2_DBUS3_CNT_CLR_V  0x00000001U
+#define CACHE_L2_DBUS3_CNT_CLR_S  31
+
+/** CACHE_L2_IBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x300)
+/** CACHE_L2_IBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_M  (CACHE_L2_IBUS0_HIT_CNT_V << CACHE_L2_IBUS0_HIT_CNT_S)
+#define CACHE_L2_IBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x304)
+/** CACHE_L2_IBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+ *  bus0 accessing L1-ICache0.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_M  (CACHE_L2_IBUS0_MISS_CNT_V << CACHE_L2_IBUS0_MISS_CNT_S)
+#define CACHE_L2_IBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x308)
+/** CACHE_L2_IBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache0 accesses
+ *  L2-Cache due to bus0 accessing L1-ICache0.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_M  (CACHE_L2_IBUS0_CONFLICT_CNT_V << CACHE_L2_IBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x30c)
+/** CACHE_L2_IBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS0_NXTLVL_RD_CNT_V << CACHE_L2_IBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x310)
+/** CACHE_L2_IBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_M  (CACHE_L2_IBUS1_HIT_CNT_V << CACHE_L2_IBUS1_HIT_CNT_S)
+#define CACHE_L2_IBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x314)
+/** CACHE_L2_IBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+ *  bus1 accessing L1-ICache1.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_M  (CACHE_L2_IBUS1_MISS_CNT_V << CACHE_L2_IBUS1_MISS_CNT_S)
+#define CACHE_L2_IBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x318)
+/** CACHE_L2_IBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache1 accesses
+ *  L2-Cache due to bus1 accessing L1-ICache1.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_M  (CACHE_L2_IBUS1_CONFLICT_CNT_V << CACHE_L2_IBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x31c)
+/** CACHE_L2_IBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS1_NXTLVL_RD_CNT_V << CACHE_L2_IBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x320)
+/** CACHE_L2_IBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_M  (CACHE_L2_IBUS2_HIT_CNT_V << CACHE_L2_IBUS2_HIT_CNT_S)
+#define CACHE_L2_IBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x324)
+/** CACHE_L2_IBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+ *  bus2 accessing L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_M  (CACHE_L2_IBUS2_MISS_CNT_V << CACHE_L2_IBUS2_MISS_CNT_S)
+#define CACHE_L2_IBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x328)
+/** CACHE_L2_IBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache2 accesses
+ *  L2-Cache due to bus2 accessing L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_M  (CACHE_L2_IBUS2_CONFLICT_CNT_V << CACHE_L2_IBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x32c)
+/** CACHE_L2_IBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS2_NXTLVL_RD_CNT_V << CACHE_L2_IBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x330)
+/** CACHE_L2_IBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_M  (CACHE_L2_IBUS3_HIT_CNT_V << CACHE_L2_IBUS3_HIT_CNT_S)
+#define CACHE_L2_IBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x334)
+/** CACHE_L2_IBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+ *  bus3 accessing L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_M  (CACHE_L2_IBUS3_MISS_CNT_V << CACHE_L2_IBUS3_MISS_CNT_S)
+#define CACHE_L2_IBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x338)
+/** CACHE_L2_IBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-ICache3 accesses
+ *  L2-Cache due to bus3 accessing L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_M  (CACHE_L2_IBUS3_CONFLICT_CNT_V << CACHE_L2_IBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_IBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_IBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x33c)
+/** CACHE_L2_IBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_IBUS3_NXTLVL_RD_CNT_V << CACHE_L2_IBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_IBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_HIT_CNT_REG register
+ *  L2-Cache bus0 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS0_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x340)
+/** CACHE_L2_DBUS0_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_M  (CACHE_L2_DBUS0_HIT_CNT_V << CACHE_L2_DBUS0_HIT_CNT_S)
+#define CACHE_L2_DBUS0_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_MISS_CNT_REG register
+ *  L2-Cache bus0 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS0_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x344)
+/** CACHE_L2_DBUS0_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus0 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_M  (CACHE_L2_DBUS0_MISS_CNT_V << CACHE_L2_DBUS0_MISS_CNT_S)
+#define CACHE_L2_DBUS0_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS0_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x348)
+/** CACHE_L2_DBUS0_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus0 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_M  (CACHE_L2_DBUS0_CONFLICT_CNT_V << CACHE_L2_DBUS0_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS0_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x34c)
+/** CACHE_L2_DBUS0_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS0_NXTLVL_RD_CNT_V << CACHE_L2_DBUS0_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus0 WB-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS0_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x350)
+/** CACHE_L2_DBUS0_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus0 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS0_NXTLVL_WR_CNT_V << CACHE_L2_DBUS0_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS0_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_HIT_CNT_REG register
+ *  L2-Cache bus1 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS1_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x354)
+/** CACHE_L2_DBUS1_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_M  (CACHE_L2_DBUS1_HIT_CNT_V << CACHE_L2_DBUS1_HIT_CNT_S)
+#define CACHE_L2_DBUS1_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_MISS_CNT_REG register
+ *  L2-Cache bus1 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS1_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x358)
+/** CACHE_L2_DBUS1_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus1 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_M  (CACHE_L2_DBUS1_MISS_CNT_V << CACHE_L2_DBUS1_MISS_CNT_S)
+#define CACHE_L2_DBUS1_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS1_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x35c)
+/** CACHE_L2_DBUS1_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus1 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_M  (CACHE_L2_DBUS1_CONFLICT_CNT_V << CACHE_L2_DBUS1_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS1_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x360)
+/** CACHE_L2_DBUS1_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS1_NXTLVL_RD_CNT_V << CACHE_L2_DBUS1_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus1 WB-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS1_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x364)
+/** CACHE_L2_DBUS1_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus1 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS1_NXTLVL_WR_CNT_V << CACHE_L2_DBUS1_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS1_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_HIT_CNT_REG register
+ *  L2-Cache bus2 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS2_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x368)
+/** CACHE_L2_DBUS2_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_M  (CACHE_L2_DBUS2_HIT_CNT_V << CACHE_L2_DBUS2_HIT_CNT_S)
+#define CACHE_L2_DBUS2_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_MISS_CNT_REG register
+ *  L2-Cache bus2 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS2_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x36c)
+/** CACHE_L2_DBUS2_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus2 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_M  (CACHE_L2_DBUS2_MISS_CNT_V << CACHE_L2_DBUS2_MISS_CNT_S)
+#define CACHE_L2_DBUS2_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS2_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x370)
+/** CACHE_L2_DBUS2_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus2 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_M  (CACHE_L2_DBUS2_CONFLICT_CNT_V << CACHE_L2_DBUS2_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS2_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x374)
+/** CACHE_L2_DBUS2_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS2_NXTLVL_RD_CNT_V << CACHE_L2_DBUS2_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus2 WB-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS2_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x378)
+/** CACHE_L2_DBUS2_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus2 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS2_NXTLVL_WR_CNT_V << CACHE_L2_DBUS2_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS2_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_HIT_CNT_REG register
+ *  L2-Cache bus3 Hit-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS3_ACS_HIT_CNT_REG (DR_REG_CACHE_BASE + 0x37c)
+/** CACHE_L2_DBUS3_HIT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_HIT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_M  (CACHE_L2_DBUS3_HIT_CNT_V << CACHE_L2_DBUS3_HIT_CNT_S)
+#define CACHE_L2_DBUS3_HIT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_HIT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_MISS_CNT_REG register
+ *  L2-Cache bus3 Miss-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS3_ACS_MISS_CNT_REG (DR_REG_CACHE_BASE + 0x380)
+/** CACHE_L2_DBUS3_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+ *  bus3 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_MISS_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_M  (CACHE_L2_DBUS3_MISS_CNT_V << CACHE_L2_DBUS3_MISS_CNT_S)
+#define CACHE_L2_DBUS3_MISS_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_MISS_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS3_ACS_CONFLICT_CNT_REG (DR_REG_CACHE_BASE + 0x384)
+/** CACHE_L2_DBUS3_CONFLICT_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of access-conflicts when L1-DCache accesses
+ *  L2-Cache due to bus3 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_CONFLICT_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_M  (CACHE_L2_DBUS3_CONFLICT_CNT_V << CACHE_L2_DBUS3_CONFLICT_CNT_S)
+#define CACHE_L2_DBUS3_CONFLICT_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_CONFLICT_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_RD_CNT_REG (DR_REG_CACHE_BASE + 0x388)
+/** CACHE_L2_DBUS3_NXTLVL_RD_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of times that L2-Cache accesses external memory due
+ *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_M  (CACHE_L2_DBUS3_NXTLVL_RD_CNT_V << CACHE_L2_DBUS3_NXTLVL_RD_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_RD_CNT_S  0
+
+/** CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG register
+ *  L2-Cache bus3 WB-Access Counter register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_DBUS3_ACS_NXTLVL_WR_CNT_REG (DR_REG_CACHE_BASE + 0x38c)
+/** CACHE_L2_DBUS3_NXTLVL_WR_CNT : RO; bitpos: [31:0]; default: 0;
+ *  The register records the number of write back when L1-DCache accesses L2-Cache due
+ *  to bus3 accessing L1-DCache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT    0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_M  (CACHE_L2_DBUS3_NXTLVL_WR_CNT_V << CACHE_L2_DBUS3_NXTLVL_WR_CNT_S)
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_V  0xFFFFFFFFU
+#define CACHE_L2_DBUS3_NXTLVL_WR_CNT_S  0
+
+/** CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG register
+ *  L2-Cache Access Fail ID/attribution information register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ID_ATTR_REG (DR_REG_CACHE_BASE + 0x390)
+/** CACHE_L2_CACHE_FAIL_ID : RO; bitpos: [15:0]; default: 0;
+ *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_ID    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_M  (CACHE_L2_CACHE_FAIL_ID_V << CACHE_L2_CACHE_FAIL_ID_S)
+#define CACHE_L2_CACHE_FAIL_ID_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ID_S  0
+/** CACHE_L2_CACHE_FAIL_ATTR : RO; bitpos: [31:16]; default: 0;
+ *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+ *  due to cache accessing L1-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_ATTR    0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_M  (CACHE_L2_CACHE_FAIL_ATTR_V << CACHE_L2_CACHE_FAIL_ATTR_S)
+#define CACHE_L2_CACHE_FAIL_ATTR_V  0x0000FFFFU
+#define CACHE_L2_CACHE_FAIL_ATTR_S  16
+
+/** CACHE_L2_CACHE_ACS_FAIL_ADDR_REG register
+ *  L2-Cache Access Fail Address information register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACS_FAIL_ADDR_REG (DR_REG_CACHE_BASE + 0x394)
+/** CACHE_L2_CACHE_FAIL_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_FAIL_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_M  (CACHE_L2_CACHE_FAIL_ADDR_V << CACHE_L2_CACHE_FAIL_ADDR_S)
+#define CACHE_L2_CACHE_FAIL_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_FAIL_ADDR_S  0
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG register
+ *  L1-Cache Access Fail Interrupt enable register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ENA_REG (DR_REG_CACHE_BASE + 0x398)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ENA : HRO; bitpos: [5]; default: 0;
+ *  Configures interrupt of L2-Cache preload-operation done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_M  (CACHE_L2_CACHE_PLD_DONE_INT_ENA_V << CACHE_L2_CACHE_PLD_DONE_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ENA_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ENA : HRO; bitpos: [12]; default: 0;
+ *  Configures interrupt of L2-Cache preload-operation error.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_M  (CACHE_L2_CACHE_PLD_ERR_INT_ENA_V << CACHE_L2_CACHE_PLD_ERR_INT_ENA_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ENA_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG register
+ *  Sync Preload operation Interrupt clear register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_CLR_REG (DR_REG_CACHE_BASE + 0x39c)
+/** CACHE_L2_CACHE_PLD_DONE_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+ *  is done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_M  (CACHE_L2_CACHE_PLD_DONE_INT_CLR_V << CACHE_L2_CACHE_PLD_DONE_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_CLR_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_M  (CACHE_L2_CACHE_PLD_ERR_INT_CLR_V << CACHE_L2_CACHE_PLD_ERR_INT_CLR_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_CLR_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG register
+ *  Sync Preload operation Interrupt raw register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_RAW_REG (DR_REG_CACHE_BASE + 0x3a0)
+/** CACHE_L2_CACHE_PLD_DONE_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+ *  done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_M  (CACHE_L2_CACHE_PLD_DONE_INT_RAW_V << CACHE_L2_CACHE_PLD_DONE_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_RAW_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+ *  occurs.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_M  (CACHE_L2_CACHE_PLD_ERR_INT_RAW_V << CACHE_L2_CACHE_PLD_ERR_INT_RAW_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_RAW_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG register
+ *  L1-Cache Access Fail Interrupt status register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_INT_ST_REG (DR_REG_CACHE_BASE + 0x3a4)
+/** CACHE_L2_CACHE_PLD_DONE_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+ *  preload-operation is done.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_M  (CACHE_L2_CACHE_PLD_DONE_INT_ST_V << CACHE_L2_CACHE_PLD_DONE_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_DONE_INT_ST_S  5
+/** CACHE_L2_CACHE_PLD_ERR_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST    (BIT(12))
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_M  (CACHE_L2_CACHE_PLD_ERR_INT_ST_V << CACHE_L2_CACHE_PLD_ERR_INT_ST_S)
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_ERR_INT_ST_S  12
+
+/** CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG register
+ *  Cache Sync/Preload Operation exception register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_PRELOAD_EXCEPTION_REG (DR_REG_CACHE_BASE + 0x3a8)
+/** CACHE_L2_CACHE_PLD_ERR_CODE : RO; bitpos: [11:10]; default: 0;
+ *  The value 2 is Only available which means preload size is error in L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_ERR_CODE    0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_M  (CACHE_L2_CACHE_PLD_ERR_CODE_V << CACHE_L2_CACHE_PLD_ERR_CODE_S)
+#define CACHE_L2_CACHE_PLD_ERR_CODE_V  0x00000003U
+#define CACHE_L2_CACHE_PLD_ERR_CODE_S  10
+
+/** CACHE_L2_CACHE_SYNC_RST_CTRL_REG register
+ *  Cache Sync Reset control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_SYNC_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3ac)
+/** CACHE_L2_CACHE_SYNC_RST : HRO; bitpos: [5]; default: 0;
+ *  Configures reset sync-logic inside L2-Cache. Recommend that this should only be
+ *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_SYNC_RST    (BIT(5))
+#define CACHE_L2_CACHE_SYNC_RST_M  (CACHE_L2_CACHE_SYNC_RST_V << CACHE_L2_CACHE_SYNC_RST_S)
+#define CACHE_L2_CACHE_SYNC_RST_V  0x00000001U
+#define CACHE_L2_CACHE_SYNC_RST_S  5
+
+/** CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG register
+ *  Cache Preload Reset control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_PRELOAD_RST_CTRL_REG (DR_REG_CACHE_BASE + 0x3b0)
+/** CACHE_L2_CACHE_PLD_RST : HRO; bitpos: [5]; default: 0;
+ *  Configures reset preload-logic inside L2-Cache. Recommend that this should only be
+ *  used to initialize preload-logic when some fatal error of preload-logic occurs.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_PLD_RST    (BIT(5))
+#define CACHE_L2_CACHE_PLD_RST_M  (CACHE_L2_CACHE_PLD_RST_V << CACHE_L2_CACHE_PLD_RST_S)
+#define CACHE_L2_CACHE_PLD_RST_V  0x00000001U
+#define CACHE_L2_CACHE_PLD_RST_S  5
+
+/** CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG register
+ *  Cache Autoload buffer clear control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_REG (DR_REG_CACHE_BASE + 0x3b4)
+/** CACHE_L2_CACHE_ALD_BUF_CLR : HRO; bitpos: [5]; default: 0;
+ *  Configures clear autoload-buffer inside L2-Cache. If this bit is active, autoload
+ *  will not work in L2-Cache. This bit should not be active when autoload works in
+ *  L2-Cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ALD_BUF_CLR    (BIT(5))
+#define CACHE_L2_CACHE_ALD_BUF_CLR_M  (CACHE_L2_CACHE_ALD_BUF_CLR_V << CACHE_L2_CACHE_ALD_BUF_CLR_S)
+#define CACHE_L2_CACHE_ALD_BUF_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_ALD_BUF_CLR_S  5
+
+/** CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG register
+ *  Unallocate request buffer clear registers
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b8)
+/** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
+ *  The bit is used to clear the unallocate request buffer of l2 icache where the
+ *  unallocate request is responded but not completed.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
+#define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)
+#define CACHE_L2_CACHE_UNALLOC_CLR_V  0x00000001U
+#define CACHE_L2_CACHE_UNALLOC_CLR_S  5
+
+/** CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG register
+ *  L2 cache access attribute control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ACCESS_ATTR_CTRL_REG (DR_REG_CACHE_BASE + 0x3bc)
+/** CACHE_L2_CACHE_ACCESS_FORCE_CC : HRO; bitpos: [0]; default: 1;
+ *  Configures force the request to l2 cache with cacheable attribute, otherwise, the
+ *  attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+ *  non-cacheable.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC    (BIT(0))
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_M  (CACHE_L2_CACHE_ACCESS_FORCE_CC_V << CACHE_L2_CACHE_ACCESS_FORCE_CC_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_CC_S  0
+/** CACHE_L2_CACHE_ACCESS_FORCE_WB : HRO; bitpos: [1]; default: 1;
+ *  Configures force the request to l2 cache with write-back attribute, otherwise, the
+ *  attribute is propagated from L1 cache or CPU, it could be one of write-back and
+ *  write-through.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB    (BIT(1))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_M  (CACHE_L2_CACHE_ACCESS_FORCE_WB_V << CACHE_L2_CACHE_ACCESS_FORCE_WB_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WB_S  1
+/** CACHE_L2_CACHE_ACCESS_FORCE_WMA : HRO; bitpos: [2]; default: 1;
+ *  Configures force the request to l2 cache with write-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  write-miss-allocate and write-miss-no-allocate.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA    (BIT(2))
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_WMA_V << CACHE_L2_CACHE_ACCESS_FORCE_WMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_WMA_S  2
+/** CACHE_L2_CACHE_ACCESS_FORCE_RMA : HRO; bitpos: [3]; default: 1;
+ *  Configures force the request to l2 cache with read-miss-allocate attribute,
+ *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+ *  read-miss-allocate and read-miss-no-allocate.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA    (BIT(3))
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_M  (CACHE_L2_CACHE_ACCESS_FORCE_RMA_V << CACHE_L2_CACHE_ACCESS_FORCE_RMA_S)
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_V  0x00000001U
+#define CACHE_L2_CACHE_ACCESS_FORCE_RMA_S  3
+
+/** CACHE_L2_CACHE_OBJECT_CTRL_REG register
+ *  Cache Tag and Data memory Object control register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_OBJECT_CTRL_REG (DR_REG_CACHE_BASE + 0x3c0)
+/** CACHE_L2_CACHE_TAG_OBJECT : HRO; bitpos: [5]; default: 0;
+ *  Configures set L2-Cache tag memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_TAG_OBJECT    (BIT(5))
+#define CACHE_L2_CACHE_TAG_OBJECT_M  (CACHE_L2_CACHE_TAG_OBJECT_V << CACHE_L2_CACHE_TAG_OBJECT_S)
+#define CACHE_L2_CACHE_TAG_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_TAG_OBJECT_S  5
+/** CACHE_L2_CACHE_MEM_OBJECT : HRO; bitpos: [11]; default: 0;
+ *  Configures set L2-Cache data memory as object. This bit should be onehot with the
+ *  others fields inside this register.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_MEM_OBJECT    (BIT(11))
+#define CACHE_L2_CACHE_MEM_OBJECT_M  (CACHE_L2_CACHE_MEM_OBJECT_V << CACHE_L2_CACHE_MEM_OBJECT_S)
+#define CACHE_L2_CACHE_MEM_OBJECT_V  0x00000001U
+#define CACHE_L2_CACHE_MEM_OBJECT_S  11
+
+/** CACHE_L2_CACHE_WAY_OBJECT_REG register
+ *  Cache Tag and Data memory way register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT_REG (DR_REG_CACHE_BASE + 0x3c4)
+/** CACHE_L2_CACHE_WAY_OBJECT : HRO; bitpos: [2:0]; default: 0;
+ *  Configures way of the tag-object will be accessed.
+ *  7: way7
+ *
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_WAY_OBJECT    0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_M  (CACHE_L2_CACHE_WAY_OBJECT_V << CACHE_L2_CACHE_WAY_OBJECT_S)
+#define CACHE_L2_CACHE_WAY_OBJECT_V  0x00000007U
+#define CACHE_L2_CACHE_WAY_OBJECT_S  0
+
+/** CACHE_L2_CACHE_ADDR_REG register
+ *  Cache address register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_ADDR_REG (DR_REG_CACHE_BASE + 0x3c8)
+/** CACHE_L2_CACHE_ADDR : HRO; bitpos: [31:0]; default: 1073741824;
+ *  Those bits stores the address which will decide where inside the specified tag
+ *  memory object will be accessed.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_ADDR    0xFFFFFFFFU
+#define CACHE_L2_CACHE_ADDR_M  (CACHE_L2_CACHE_ADDR_V << CACHE_L2_CACHE_ADDR_S)
+#define CACHE_L2_CACHE_ADDR_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_ADDR_S  0
+
+/** CACHE_L2_CACHE_DEBUG_BUS_REG register
+ *  Cache Tag/data memory content register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS_REG (DR_REG_CACHE_BASE + 0x3cc)
+/** CACHE_L2_CACHE_DEBUG_BUS : R/W; bitpos: [31:0]; default: 972;
+ *  This is a constant place where we can write data to or read data from the tag/data
+ *  memory on the specified cache.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_DEBUG_BUS    0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_M  (CACHE_L2_CACHE_DEBUG_BUS_V << CACHE_L2_CACHE_DEBUG_BUS_S)
+#define CACHE_L2_CACHE_DEBUG_BUS_V  0xFFFFFFFFU
+#define CACHE_L2_CACHE_DEBUG_BUS_S  0
+
+/** CACHE_LEVEL_SPLIT1_REG register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_LEVEL_SPLIT1_REG (DR_REG_CACHE_BASE + 0x3d0)
+/** CACHE_LEVEL_SPLIT1 : HRO; bitpos: [31:0]; default: 976;
+ *  Reserved
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_LEVEL_SPLIT1    0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_M  (CACHE_LEVEL_SPLIT1_V << CACHE_LEVEL_SPLIT1_S)
+#define CACHE_LEVEL_SPLIT1_V  0xFFFFFFFFU
+#define CACHE_LEVEL_SPLIT1_S  0
+
+/** CACHE_CLOCK_GATE_REG register
+ *  Clock gate control register
+ */
+#define CACHE_CLOCK_GATE_REG (DR_REG_CACHE_BASE + 0x3d4)
+/** CACHE_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures clock gate when access all registers in this module.
+ */
+#define CACHE_CLK_EN    (BIT(0))
+#define CACHE_CLK_EN_M  (CACHE_CLK_EN_V << CACHE_CLK_EN_S)
+#define CACHE_CLK_EN_V  0x00000001U
+#define CACHE_CLK_EN_S  0
+
+/** CACHE_TRACE_ENA_REG register
+ *  Clock gate control register
+ */
+#define CACHE_TRACE_ENA_REG (DR_REG_CACHE_BASE + 0x3d8)
+/** CACHE_L1_CACHE_TRACE_ENA : R/W; bitpos: [0]; default: 0;
+ *  Configures L1-Cache trace for the performance counter and fail tracer
+ */
+#define CACHE_L1_CACHE_TRACE_ENA    (BIT(0))
+#define CACHE_L1_CACHE_TRACE_ENA_M  (CACHE_L1_CACHE_TRACE_ENA_V << CACHE_L1_CACHE_TRACE_ENA_S)
+#define CACHE_L1_CACHE_TRACE_ENA_V  0x00000001U
+#define CACHE_L1_CACHE_TRACE_ENA_S  0
+/** CACHE_L2_CACHE_TRACE_ENA : HRO; bitpos: [1]; default: 0;
+ *  Configures L2-Cache trace for the performance counter and fail tracer
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_L2_CACHE_TRACE_ENA    (BIT(1))
+#define CACHE_L2_CACHE_TRACE_ENA_M  (CACHE_L2_CACHE_TRACE_ENA_V << CACHE_L2_CACHE_TRACE_ENA_S)
+#define CACHE_L2_CACHE_TRACE_ENA_V  0x00000001U
+#define CACHE_L2_CACHE_TRACE_ENA_S  1
+
+/** CACHE_REDUNDANCY_SIG0_REG register
+ *  Cache redundancy signal 0 register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_REDUNDANCY_SIG0_REG (DR_REG_CACHE_BASE + 0x3dc)
+/** CACHE_REDCY_SIG0 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_REDCY_SIG0    0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_M  (CACHE_REDCY_SIG0_V << CACHE_REDCY_SIG0_S)
+#define CACHE_REDCY_SIG0_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG0_S  0
+
+/** CACHE_REDUNDANCY_SIG1_REG register
+ *  Cache redundancy signal 1 register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_REDUNDANCY_SIG1_REG (DR_REG_CACHE_BASE + 0x3e0)
+/** CACHE_REDCY_SIG1 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_REDCY_SIG1    0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_M  (CACHE_REDCY_SIG1_V << CACHE_REDCY_SIG1_S)
+#define CACHE_REDCY_SIG1_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG1_S  0
+
+/** CACHE_REDUNDANCY_SIG2_REG register
+ *  Cache redundancy signal 2 register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_REDUNDANCY_SIG2_REG (DR_REG_CACHE_BASE + 0x3e4)
+/** CACHE_REDCY_SIG2 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_REDCY_SIG2    0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_M  (CACHE_REDCY_SIG2_V << CACHE_REDCY_SIG2_S)
+#define CACHE_REDCY_SIG2_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG2_S  0
+
+/** CACHE_REDUNDANCY_SIG3_REG register
+ *  Cache redundancy signal 3 register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_REDUNDANCY_SIG3_REG (DR_REG_CACHE_BASE + 0x3e8)
+/** CACHE_REDCY_SIG3 : R/W; bitpos: [31:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_REDCY_SIG3    0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_M  (CACHE_REDCY_SIG3_V << CACHE_REDCY_SIG3_S)
+#define CACHE_REDCY_SIG3_V  0xFFFFFFFFU
+#define CACHE_REDCY_SIG3_S  0
+
+/** CACHE_REDUNDANCY_SIG4_REG register
+ *  Cache redundancy signal 0 register
+ *  This register is only for internal debugging purposes. Do not use it in
+ *  applications.
+ */
+#define CACHE_REDUNDANCY_SIG4_REG (DR_REG_CACHE_BASE + 0x3ec)
+/** CACHE_REDCY_SIG4 : RO; bitpos: [3:0]; default: 0;
+ *  Those bits are prepared for ECO.
+ *  This field is only for internal debugging purposes. Do not use it in applications.
+ */
+#define CACHE_REDCY_SIG4    0x0000000FU
+#define CACHE_REDCY_SIG4_M  (CACHE_REDCY_SIG4_V << CACHE_REDCY_SIG4_S)
+#define CACHE_REDCY_SIG4_V  0x0000000FU
+#define CACHE_REDCY_SIG4_S  0
+
+/** CACHE_DATE_REG register
+ *  Version control register
+ */
+#define CACHE_DATE_REG (DR_REG_CACHE_BASE + 0x3fc)
+/** CACHE_DATE : R/W; bitpos: [27:0]; default: 38810384;
+ *  version control register. Note that this default value stored is the latest date
+ *  when the hardware logic was updated.
+ */
+#define CACHE_DATE    0x0FFFFFFFU
+#define CACHE_DATE_M  (CACHE_DATE_V << CACHE_DATE_S)
+#define CACHE_DATE_V  0x0FFFFFFFU
+#define CACHE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cache_struct.h b/components/soc/esp32s31/register/soc/cache_struct.h
new file mode 100644
index 00000000000..cccabd1c864
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cache_struct.h
@@ -0,0 +1,6274 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control and configuration registers */
+/** Type of l1_icache_ctrl register
+ *  L1 instruction Cache(L1-ICache) control register
+ */
+typedef union {
+    struct {
+        /** l1_icache_shut_ibus0 : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to disable IBUS0 to access icache.
+         *  1: Disable
+         */
+        uint32_t l1_icache_shut_ibus0:1;
+        /** l1_icache_shut_ibus1 : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to disable IBUS1 to access icache.
+         *  1: Disable
+         */
+        uint32_t l1_icache_shut_ibus1:1;
+        /** l1_icache_shut_ibus2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to disable IBUS2 to access ROM cache.
+         *  1: Disable
+         */
+        uint32_t l1_icache_shut_ibus2:1;
+        /** l1_icache_shut_ibus3 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether to disable IBUS3 to access ROM cache.
+         *  1: Disable
+         */
+        uint32_t l1_icache_shut_ibus3:1;
+        uint32_t reserved_4:4;
+        /** l1_icache_undef_op : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_icache_ctrl_reg_t;
+
+/** Type of l1_dcache_ctrl register
+ *  L1 data Cache(L1-DCache) control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_shut_dbus0 : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to disable DBUS0 to access dcache.
+         *  1: Disable
+         */
+        uint32_t l1_dcache_shut_dbus0:1;
+        /** l1_dcache_shut_dbus1 : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to disable DBUS1 to access dcache.
+         *  1: Disable
+         */
+        uint32_t l1_dcache_shut_dbus1:1;
+        /** l1_dcache_shut_dbus2 : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to disable DBUS2 to access ROM cache.
+         *  1: Disable
+         */
+        uint32_t l1_dcache_shut_dbus2:1;
+        /** l1_dcache_shut_dbus3 : R/W; bitpos: [3]; default: 0;
+         *  Configures whether to disable DBUS3 to access ROM cache.
+         *  1: Disable
+         */
+        uint32_t l1_dcache_shut_dbus3:1;
+        /** l1_dcache_shut_dma : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to disable DMA access L1-DCache, 0: enable, 1: disable
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l1_dcache_undef_op : R/W; bitpos: [15:8]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_ctrl_reg_t;
+
+/** Type of l2_cache_ctrl register
+ *  L2 Cache(L2-Cache) control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** l2_cache_shut_dma : HRO; bitpos: [4]; default: 1;
+         *  The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_shut_dma:1;
+        uint32_t reserved_5:3;
+        /** l2_cache_undef_op : HRO; bitpos: [15:8]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_undef_op:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_ctrl_reg_t;
+
+
+/** Group: Bypass Cache Control and configuration registers */
+/** Type of l1_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        /** bypass_l1_icache0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures bypass L1-ICache0.
+         *  1: Enable
+         *
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t bypass_l1_icache0_en:1;
+        /** bypass_l1_icache1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures bypass L1-ICache1.
+         *  1: Enable
+         *
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t bypass_l1_icache1_en:1;
+        /** bypass_l1_icache2_en : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t bypass_l1_icache2_en:1;
+        /** bypass_l1_icache3_en : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t bypass_l1_icache3_en:1;
+        /** bypass_l1_dcache_en : R/W; bitpos: [4]; default: 0;
+         *  Configures bypass L1-DCache.
+         *  1: Enable
+         */
+        uint32_t bypass_l1_dcache_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_bypass_cache_conf_reg_t;
+
+/** Type of l2_bypass_cache_conf register
+ *  Bypass Cache configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** bypass_l2_cache_en : HRO; bitpos: [5]; default: 0;
+         *  Configures bypass L2-Cache.
+         *  1: Enable
+         *
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t bypass_l2_cache_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_bypass_cache_conf_reg_t;
+
+
+/** Group: Cache Atomic Control and configuration registers */
+/** Type of l1_cache_atomic_conf register
+ *  L1 Cache atomic feature configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_atomic_en : R/W; bitpos: [0]; default: 1;
+         *  Configures atomic feature on L1-DCache when multiple cores access L1-DCache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_atomic_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l1_cache_atomic_conf_reg_t;
+
+
+/** Group: Cache Mode Control and configuration registers */
+/** Type of l1_acache_cachesize_conf register
+ *  L1 Auxiliary Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_acache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_256:1;
+        /** l1_acache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_512:1;
+        /** l1_acache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_1k:1;
+        /** l1_acache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_2k:1;
+        /** l1_acache_cachesize_4k : HRO; bitpos: [4]; default: 1;
+         *  The field is used to configure cachesize of L1-ACache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_acache_cachesize_4k:1;
+        /** l1_acache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_8k:1;
+        /** l1_acache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_16k:1;
+        /** l1_acache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_32k:1;
+        /** l1_acache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_64k:1;
+        /** l1_acache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_128k:1;
+        /** l1_acache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_256k:1;
+        /** l1_acache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_512k:1;
+        /** l1_acache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ACache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_acache_cachesize_conf_reg_t;
+
+/** Type of l1_acache_blocksize_conf register
+ *  L1 Auxiliary Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_acache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ACache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_blocksize_8:1;
+        /** l1_acache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ACache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_blocksize_16:1;
+        /** l1_acache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ACache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_blocksize_32:1;
+        /** l1_acache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-ACache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_acache_blocksize_64:1;
+        /** l1_acache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ACache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_blocksize_128:1;
+        /** l1_acache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ACache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_acache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_acache_blocksize_conf_reg_t;
+
+/** Type of l1_icache_cachesize_conf register
+ *  L1 instruction Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_256:1;
+        /** l1_icache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_512:1;
+        /** l1_icache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_1k:1;
+        /** l1_icache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_2k:1;
+        /** l1_icache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_4k:1;
+        /** l1_icache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_8k:1;
+        /** l1_icache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_16k:1;
+        /** l1_icache_cachesize_32k : HRO; bitpos: [7]; default: 1;
+         *  The field is used to configure cachesize of L1-ICache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_cachesize_32k:1;
+        /** l1_icache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_64k:1;
+        /** l1_icache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_128k:1;
+        /** l1_icache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_256k:1;
+        /** l1_icache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_512k:1;
+        /** l1_icache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-ICache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_icache_cachesize_conf_reg_t;
+
+/** Type of l1_icache_blocksize_conf register
+ *  L1 instruction Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_blocksize_8:1;
+        /** l1_icache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_blocksize_16:1;
+        /** l1_icache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_blocksize_32:1;
+        /** l1_icache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-ICache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_icache_blocksize_64:1;
+        /** l1_icache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_blocksize_128:1;
+        /** l1_icache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-ICache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache_blocksize_conf_reg_t;
+
+/** Type of l1_dcache_cachesize_conf register
+ *  L1 data Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_256:1;
+        /** l1_dcache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_512:1;
+        /** l1_dcache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_1k:1;
+        /** l1_dcache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_2k:1;
+        /** l1_dcache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_4k:1;
+        /** l1_dcache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_8k:1;
+        /** l1_dcache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_16k:1;
+        /** l1_dcache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_32k:1;
+        /** l1_dcache_cachesize_64k : HRO; bitpos: [8]; default: 1;
+         *  The field is used to configure cachesize of L1-DCache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_cachesize_64k:1;
+        /** l1_dcache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_128k:1;
+        /** l1_dcache_cachesize_256k : HRO; bitpos: [10]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_256k:1;
+        /** l1_dcache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_512k:1;
+        /** l1_dcache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L1-DCache as 1024k bytes. This field
+         *  and all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l1_dcache_cachesize_conf_reg_t;
+
+/** Type of l1_dcache_blocksize_conf register
+ *  L1 data Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_blocksize_8:1;
+        /** l1_dcache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 16 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_blocksize_16:1;
+        /** l1_dcache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 32 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_blocksize_32:1;
+        /** l1_dcache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L1-DCache as 64 bytes. This field and
+         *  all other fields within this register is onehot.
+         */
+        uint32_t l1_dcache_blocksize_64:1;
+        /** l1_dcache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_blocksize_128:1;
+        /** l1_dcache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L1-DCache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_dcache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_blocksize_conf_reg_t;
+
+/** Type of l2_cache_cachesize_conf register
+ *  L2 Cache CacheSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_cachesize_256 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_256:1;
+        /** l2_cache_cachesize_512 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_512:1;
+        /** l2_cache_cachesize_1k : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_1k:1;
+        /** l2_cache_cachesize_2k : HRO; bitpos: [3]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 2k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_2k:1;
+        /** l2_cache_cachesize_4k : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 4k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_4k:1;
+        /** l2_cache_cachesize_8k : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 8k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_8k:1;
+        /** l2_cache_cachesize_16k : HRO; bitpos: [6]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 16k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_16k:1;
+        /** l2_cache_cachesize_32k : HRO; bitpos: [7]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 32k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_32k:1;
+        /** l2_cache_cachesize_64k : HRO; bitpos: [8]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 64k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_64k:1;
+        /** l2_cache_cachesize_128k : HRO; bitpos: [9]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 128k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_128k:1;
+        /** l2_cache_cachesize_256k : HRO; bitpos: [10]; default: 1;
+         *  The field is used to configure cachesize of L2-Cache as 256k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_256k:1;
+        /** l2_cache_cachesize_512k : HRO; bitpos: [11]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 512k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_512k:1;
+        /** l2_cache_cachesize_1024k : HRO; bitpos: [12]; default: 0;
+         *  The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_cachesize_1024k:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_cachesize_conf_reg_t;
+
+/** Type of l2_cache_blocksize_conf register
+ *  L2 Cache BlockSize mode configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_blocksize_8 : HRO; bitpos: [0]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_8:1;
+        /** l2_cache_blocksize_16 : HRO; bitpos: [1]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_16:1;
+        /** l2_cache_blocksize_32 : HRO; bitpos: [2]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_32:1;
+        /** l2_cache_blocksize_64 : HRO; bitpos: [3]; default: 1;
+         *  The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all
+         *  other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_64:1;
+        /** l2_cache_blocksize_128 : HRO; bitpos: [4]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 128 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_128:1;
+        /** l2_cache_blocksize_256 : HRO; bitpos: [5]; default: 0;
+         *  The field is used to configureblocksize of L2-Cache as 256 bytes. This field and
+         *  all other fields within this register is onehot.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_blocksize_256:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_blocksize_conf_reg_t;
+
+
+/** Group: Wrap Mode Control and configuration registers */
+/** Type of l1_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_wrap : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the critical word first function.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_wrap:1;
+        /** l1_icache1_wrap : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the critical word first function.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_wrap:1;
+        /** l1_icache2_wrap : HRO; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_wrap:1;
+        /** l1_icache3_wrap : HRO; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_wrap:1;
+        /** l1_dcache_wrap : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable the critical word first function.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_wrap:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_wrap_around_ctrl_reg_t;
+
+/** Type of l2_cache_wrap_around_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_wrap : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to enable L2-Cache wrap around mode.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_wrap:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_wrap_around_ctrl_reg_t;
+
+
+/** Group: Early Restart Control registers */
+/** Type of l1_cache_miss_access_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_miss_disable_access : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable early restart function.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_miss_disable_access:1;
+        /** l1_icache1_miss_disable_access : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable early restart function.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_miss_disable_access:1;
+        /** l1_icache2_miss_disable_access : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_miss_disable_access:1;
+        /** l1_icache3_miss_disable_access : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_miss_disable_access:1;
+        /** l1_cache_miss_disable_access : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable early restart function.
+         *  1: Enable
+         */
+        uint32_t l1_cache_miss_disable_access:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_miss_access_ctrl_reg_t;
+
+/** Type of l2_cache_miss_access_ctrl register
+ *  Cache wrap around control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_miss_disable_access : HRO; bitpos: [5]; default: 0;
+         *  Set this bit as 1 to disable early restart of  L2-Cache
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_miss_disable_access:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_miss_access_ctrl_reg_t;
+
+
+/** Group: Cache Freeze Control registers */
+/** Type of l1_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_freeze_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable freeze operation. It can be cleared by software.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_freeze_en:1;
+        /** l1_icache0_freeze_mode : R/W; bitpos: [1]; default: 0;
+         *  Configures the freeze mode.
+         *  1: Assert hit if a cache miss occurs
+         */
+        uint32_t l1_icache0_freeze_mode:1;
+        /** l1_icache0_freeze_done : RO; bitpos: [2]; default: 0;
+         *  Indicates whether the freeze operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache0_freeze_done:1;
+        uint32_t reserved_3:1;
+        /** l1_icache1_freeze_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable freeze operation. It can be cleared by software.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_freeze_en:1;
+        /** l1_icache1_freeze_mode : R/W; bitpos: [5]; default: 0;
+         *  Configures the freeze mode.
+         *  1: Assert hit if a cache miss occurs
+         */
+        uint32_t l1_icache1_freeze_mode:1;
+        /** l1_icache1_freeze_done : RO; bitpos: [6]; default: 0;
+         *  Indicates whether the freeze operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache1_freeze_done:1;
+        uint32_t reserved_7:1;
+        /** l1_icache2_freeze_en : HRO; bitpos: [8]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_freeze_en:1;
+        /** l1_icache2_freeze_mode : HRO; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_freeze_mode:1;
+        /** l1_icache2_freeze_done : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_freeze_done:1;
+        uint32_t reserved_11:1;
+        /** l1_icache3_freeze_en : HRO; bitpos: [12]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_freeze_en:1;
+        /** l1_icache3_freeze_mode : HRO; bitpos: [13]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_freeze_mode:1;
+        /** l1_icache3_freeze_done : RO; bitpos: [14]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_freeze_done:1;
+        uint32_t reserved_15:1;
+        /** l1_dcache_freeze_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether to enable freeze operation. It can be cleared by software.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_freeze_en:1;
+        /** l1_dcache_freeze_mode : R/W; bitpos: [17]; default: 0;
+         *  Configures the freeze mode.
+         *  1: Assert hit if a cache miss occurs
+         */
+        uint32_t l1_dcache_freeze_mode:1;
+        /** l1_dcache_freeze_done : RO; bitpos: [18]; default: 0;
+         *  Indicates whether the freeze operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_dcache_freeze_done:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} cache_l1_cache_freeze_ctrl_reg_t;
+
+/** Type of l2_cache_freeze_ctrl register
+ *  Cache Freeze control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_freeze_en : HRO; bitpos: [20]; default: 0;
+         *  Configures freeze operation on L2-Cache. It can be cleared by software.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_freeze_en:1;
+        /** l2_cache_freeze_mode : HRO; bitpos: [21]; default: 0;
+         *  Configures mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a
+         *  miss-access will stuck.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_freeze_mode:1;
+        /** l2_cache_freeze_done : RO; bitpos: [22]; default: 0;
+         *  The bit is used to indicate whether freeze operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_freeze_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cache_l2_cache_freeze_ctrl_reg_t;
+
+
+/** Group: Cache Data Memory Access Control and Configuration registers */
+/** Type of l1_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_data_mem_rd_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_data_mem_rd_en:1;
+        /** l1_icache0_data_mem_wr_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache data
+         *  memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_data_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_data_mem_rd_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_data_mem_rd_en:1;
+        /** l1_icache1_data_mem_wr_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache data
+         *  memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_data_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_data_mem_rd_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_rd_en:1;
+        /** l1_icache2_data_mem_wr_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_data_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_data_mem_rd_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_rd_en:1;
+        /** l1_icache3_data_mem_wr_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_data_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_data_mem_rd_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache data memory.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_data_mem_rd_en:1;
+        /** l1_dcache_data_mem_wr_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache data
+         *  memory.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_data_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_data_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_data_mem_acs_conf register
+ *  Cache data memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_data_mem_rd_en : HRO; bitpos: [20]; default: 1;
+         *  Configures config-bus read L2-Cache data memoryory. 0: disable, 1: enable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_data_mem_rd_en:1;
+        /** l2_cache_data_mem_wr_en : HRO; bitpos: [21]; default: 1;
+         *  Configures config-bus write L2-Cache data memoryory. 0: disable, 1: enable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_data_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_data_mem_acs_conf_reg_t;
+
+
+/** Group: Cache Tag Memory Access Control and Configuration registers */
+/** Type of l1_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_mem_rd_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_tag_mem_rd_en:1;
+        /** l1_icache0_tag_mem_wr_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_tag_mem_wr_en:1;
+        uint32_t reserved_2:2;
+        /** l1_icache1_tag_mem_rd_en : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_tag_mem_rd_en:1;
+        /** l1_icache1_tag_mem_wr_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_tag_mem_wr_en:1;
+        uint32_t reserved_6:2;
+        /** l1_icache2_tag_mem_rd_en : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_rd_en:1;
+        /** l1_icache2_tag_mem_wr_en : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_tag_mem_wr_en:1;
+        uint32_t reserved_10:2;
+        /** l1_icache3_tag_mem_rd_en : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_rd_en:1;
+        /** l1_icache3_tag_mem_wr_en : R/W; bitpos: [13]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_tag_mem_wr_en:1;
+        uint32_t reserved_14:2;
+        /** l1_dcache_tag_mem_rd_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether to enable the configuration bus to read the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_tag_mem_rd_en:1;
+        /** l1_dcache_tag_mem_wr_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether to enable the configuration bus to write the L1 cache tag memory.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_tag_mem_wr_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} cache_l1_cache_tag_mem_acs_conf_reg_t;
+
+/** Type of l2_cache_tag_mem_acs_conf register
+ *  Cache tag memory access configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** l2_cache_tag_mem_rd_en : HRO; bitpos: [20]; default: 1;
+         *  Configures config-bus read L2-Cache tag memoryory. 0: disable, 1: enable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_tag_mem_rd_en:1;
+        /** l2_cache_tag_mem_wr_en : HRO; bitpos: [21]; default: 1;
+         *  Configures config-bus write L2-Cache tag memoryory. 0: disable, 1: enable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_tag_mem_wr_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} cache_l2_cache_tag_mem_acs_conf_reg_t;
+
+
+/** Group: Prelock Control and configuration registers */
+/** Type of l1_icache0_prelock_conf register
+ *  L1 instruction Cache 0 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 0 of icache.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_prelock_sct0_en:1;
+        /** l1_icache0_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 1 of icache.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_prelock_sct1_en:1;
+        /** l1_icache0_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l1 icache0 prelock.
+         */
+        uint32_t l1_icache0_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_conf_reg_t;
+
+/** Type of l1_icache0_prelock_sct0_addr register
+ *  L1 instruction Cache 0 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section of prelock on L1-ICache0, which
+         *  should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct1_addr register
+ *  L1 instruction Cache 0 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L1-ICache0, which
+         *  should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache0_prelock_sct_size register
+ *  L1 instruction Cache 0 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Configures the size of the first section of prelock on L1-ICache0, which should be
+         *  used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache0_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Configures the size of the second section of prelock on L1-ICache0, which should be
+         *  used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache0_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache0_prelock_sct_size_reg_t;
+
+/** Type of l1_icache1_prelock_conf register
+ *  L1 instruction Cache 1 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 0 of icache.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_prelock_sct0_en:1;
+        /** l1_icache1_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 1 of icache.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_prelock_sct1_en:1;
+        /** l1_icache1_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l1 icache1 prelock.
+         */
+        uint32_t l1_icache1_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_conf_reg_t;
+
+/** Type of l1_icache1_prelock_sct0_addr register
+ *  L1 instruction Cache 1 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are used to configure the start address of the first section of prelock
+         *  on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct1_addr register
+ *  L1 instruction Cache 1 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L1-ICache1, which
+         *  should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache1_prelock_sct_size register
+ *  L1 instruction Cache 1 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Configures the size of the first section of prelock on L1-ICache1, which should be
+         *  used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache1_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Configures the size of the second section of prelock on L1-ICache1, which should be
+         *  used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_icache1_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache1_prelock_sct_size_reg_t;
+
+/** Type of l1_icache2_prelock_conf register
+ *  L1 instruction Cache 2 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  Configures the first section of prelock function on L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct0_en:1;
+        /** l1_icache2_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  Configures the second section of prelock function on L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct1_en:1;
+        /** l1_icache2_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l1 icache2 prelock.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_conf_reg_t;
+
+/** Type of l1_icache2_prelock_sct0_addr register
+ *  L1 instruction Cache 2 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section of prelock on L1-ICache2, which
+         *  should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct1_addr register
+ *  L1 instruction Cache 2 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L1-ICache2, which
+         *  should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache2_prelock_sct_size register
+ *  L1 instruction Cache 2 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Configures the size of the first section of prelock on L1-ICache2, which should be
+         *  used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache2_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Configures the size of the second section of prelock on L1-ICache2, which should be
+         *  used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache2_prelock_sct_size_reg_t;
+
+/** Type of l1_icache3_prelock_conf register
+ *  L1 instruction Cache 3 prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  Configures the first section of prelock function on L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct0_en:1;
+        /** l1_icache3_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  Configures the second section of prelock function on L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct1_en:1;
+        /** l1_icache3_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l1 icache3 prelock.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_conf_reg_t;
+
+/** Type of l1_icache3_prelock_sct0_addr register
+ *  L1 instruction Cache 3 prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section of prelock on L1-ICache3, which
+         *  should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct0_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct1_addr register
+ *  L1 instruction Cache 3 prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L1-ICache3, which
+         *  should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct1_addr_reg_t;
+
+/** Type of l1_icache3_prelock_sct_size register
+ *  L1 instruction Cache 3 prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_prelock_sct0_size : HRO; bitpos: [13:0]; default: 16383;
+         *  Configures the size of the first section of prelock on L1-ICache3, which should be
+         *  used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_icache3_prelock_sct1_size : HRO; bitpos: [29:16]; default: 16383;
+         *  Configures the size of the second section of prelock on L1-ICache3, which should be
+         *  used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_icache3_prelock_sct_size_reg_t;
+
+/** Type of l1_dcache_prelock_conf register
+ *  L1 data Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 0 of dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_prelock_sct0_en:1;
+        /** l1_dcache_prelock_sct1_en : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable the prelocking function in Section 1 of dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_prelock_sct1_en:1;
+        /** l1_dcache_prelock_rgid : R/W; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l1 dcache prelock.
+         */
+        uint32_t l1_dcache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_conf_reg_t;
+
+/** Type of l1_dcache_prelock_sct0_addr register
+ *  L1 data Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section of prelock on L1-DCache, which
+         *  should be used together with L1_DCACHE_PRELOCK_SCT0_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct0_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct1_addr register
+ *  L1 data Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L1-DCache, which
+         *  should be used together with L1_DCACHE_PRELOCK_SCT1_SIZE_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct1_addr_reg_t;
+
+/** Type of l1_dcache_prelock_sct_size register
+ *  L1 data Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_prelock_sct0_size : R/W; bitpos: [13:0]; default: 16383;
+         *  Configures the size of the first section of prelock on L1-DCache, which should be
+         *  used together with L1_DCACHE_PRELOCK_SCT0_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct0_size:14;
+        uint32_t reserved_14:2;
+        /** l1_dcache_prelock_sct1_size : R/W; bitpos: [29:16]; default: 16383;
+         *  Configures the size of the second section of prelock on L1-DCache, which should be
+         *  used together with L1_DCACHE_PRELOCK_SCT1_ADDR_REG
+         */
+        uint32_t l1_dcache_prelock_sct1_size:14;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} cache_l1_dcache_prelock_sct_size_reg_t;
+
+/** Type of l2_cache_prelock_conf register
+ *  L2 Cache prelock configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_en : HRO; bitpos: [0]; default: 0;
+         *  Configures the first section of prelock function on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct0_en:1;
+        /** l2_cache_prelock_sct1_en : HRO; bitpos: [1]; default: 0;
+         *  Configures the second section of prelock function on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct1_en:1;
+        /** l2_cache_prelock_rgid : HRO; bitpos: [5:2]; default: 0;
+         *  Configures the gid of l2 cache prelock.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_rgid:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_conf_reg_t;
+
+/** Type of l2_cache_prelock_sct0_addr register
+ *  L2 Cache prelock section0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section of prelock on L2-Cache, which
+         *  should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct0_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct1_addr register
+ *  L2 Cache prelock section1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section of prelock on L2-Cache, which
+         *  should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct1_addr_reg_t;
+
+/** Type of l2_cache_prelock_sct_size register
+ *  L2 Cache prelock section size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_prelock_sct0_size : HRO; bitpos: [15:0]; default: 65535;
+         *  Configures the size of the first section of prelock on L2-Cache, which should be
+         *  used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct0_size:16;
+        /** l2_cache_prelock_sct1_size : HRO; bitpos: [31:16]; default: 65535;
+         *  Configures the size of the second section of prelock on L2-Cache, which should be
+         *  used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_prelock_sct1_size:16;
+    };
+    uint32_t val;
+} cache_l2_cache_prelock_sct_size_reg_t;
+
+
+/** Group: Lock Control and configuration registers */
+/** Type of lock_ctrl register
+ *  Lock-class (manual lock) operation control register
+ */
+typedef union {
+    struct {
+        /** lock_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to enable lock operation. It will be cleared by hardware after
+         *  the locking operation is done.
+         *  1: Enable
+         */
+        uint32_t lock_ena:1;
+        /** unlock_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  Configures whether to enable unlock operation. It will be cleared by hardware after
+         *  the unlocking operation is done.
+         *  1: Enable
+         */
+        uint32_t unlock_ena:1;
+        /** lock_done : RO; bitpos: [2]; default: 1;
+         *  Indicates whether the unlocking or the locking operation has finished.
+         *  1: Finished
+         */
+        uint32_t lock_done:1;
+        /** lock_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  Configures the gid of cache lock/unlock.
+         */
+        uint32_t lock_rgid:4;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} cache_lock_ctrl_reg_t;
+
+/** Type of lock_map register
+ *  Lock (manual lock) map configure register
+ */
+typedef union {
+    struct {
+        /** lock_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures caches in the two-level cache structure will apply this lock/unlock
+         *  operation.
+         *  Other bits: Reserved
+         */
+        uint32_t lock_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_lock_map_reg_t;
+
+/** Type of lock_addr register
+ *  Lock (manual lock) address configure register
+ */
+typedef union {
+    struct {
+        /** lock_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the lock/unlock operation, which should be used
+         *  together with CACHE_LOCK_SIZE_REG
+         */
+        uint32_t lock_addr:32;
+    };
+    uint32_t val;
+} cache_lock_addr_reg_t;
+
+/** Type of lock_size register
+ *  Lock (manual lock) size configure register
+ */
+typedef union {
+    struct {
+        /** lock_size : R/W; bitpos: [15:0]; default: 0;
+         *  Configures the size of the lock/unlock operation, which should be used together
+         *  with CACHE_LOCK_ADDR_REG
+         */
+        uint32_t lock_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_lock_size_reg_t;
+
+
+/** Group: Sync Control and configuration registers */
+/** Type of sync_ctrl register
+ *  Sync-class operation control register
+ */
+typedef union {
+    struct {
+        /** invalidate_ena : R/W/SC; bitpos: [0]; default: 1;
+         *  Configures whether to enable the invalidation operation. Hardware will clear it
+         *  once the operation has finished.
+         *  Please note that this field, along with the other fields (CLEAN_ENA, WRITEBACK_ENA,
+         *  WRITEBACK_INVALIDATE_ENA), is mutually exclusive. In other words, only one of these
+         *  fields can be set to 1 at any given time.
+         */
+        uint32_t invalidate_ena:1;
+        /** clean_ena : R/W/SC; bitpos: [1]; default: 0;
+         *  Configures whether to enable the clean operation. Hardware will clear it once the
+         *  operation has finished.
+         *  1: Enable
+         */
+        uint32_t clean_ena:1;
+        /** writeback_ena : R/W/SC; bitpos: [2]; default: 0;
+         *  Configures whether to enable the write-back operation. Hardware will clear it once
+         *  the operation has finished.
+         *  1: Enable
+         */
+        uint32_t writeback_ena:1;
+        /** writeback_invalidate_ena : R/W/SC; bitpos: [3]; default: 0;
+         *  Configures whether to enable the write-back invalidation operation. Hardware will
+         *  clear it once the operation has finished.
+         *  1: Enable
+         */
+        uint32_t writeback_invalidate_ena:1;
+        /** sync_done : RO; bitpos: [4]; default: 0;
+         *  Indicates whether the synchronization operation has finished.
+         *  1: Finished
+         */
+        uint32_t sync_done:1;
+        /** sync_rgid : R/W; bitpos: [8:5]; default: 0;
+         *  Configures the gid of cache sync operation (invalidate, clean, writeback,
+         *  writeback_invalidate)
+         */
+        uint32_t sync_rgid:4;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} cache_sync_ctrl_reg_t;
+
+/** Type of sync_map register
+ *  Sync map configure register
+ */
+typedef union {
+    struct {
+        /** sync_map : R/W; bitpos: [5:0]; default: 31;
+         *  Configures which cache to perform the locking or the unlocking operation.
+         *  Other bits: Reserved
+         */
+        uint32_t sync_map:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_sync_map_reg_t;
+
+/** Type of sync_addr register
+ *  Sync address configure register
+ */
+typedef union {
+    struct {
+        /** sync_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the sync operation, which should be used together
+         *  with CACHE_SYNC_SIZE_REG
+         */
+        uint32_t sync_addr:32;
+    };
+    uint32_t val;
+} cache_sync_addr_reg_t;
+
+/** Type of sync_size register
+ *  Sync size configure register
+ */
+typedef union {
+    struct {
+        /** sync_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the sync operation, which should be used together with
+         *  CACHE_SYNC_ADDR_REG
+         */
+        uint32_t sync_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_sync_size_reg_t;
+
+
+/** Group: Preload Control and configuration registers */
+/** Type of l1_icache0_preload_ctrl register
+ *  L1 instruction Cache 0 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to enable the preloading operation in icache0. Hardware will
+         *  clear it once the operation has finished.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_preload_ena:1;
+        /** l1_icache0_preload_done : RO; bitpos: [1]; default: 1;
+         *  Represents whether the preloading operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache0_preload_done:1;
+        /** l1_icache0_preload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the preloading operation.
+         *  1: Descending
+         */
+        uint32_t l1_icache0_preload_order:1;
+        /** l1_icache0_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l1 icache0 preload.
+         */
+        uint32_t l1_icache0_preload_rgid:4;
+        /** l1_icache0_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  Configures the mode of l1 icache0 preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         */
+        uint32_t l1_icache0_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_ctrl_reg_t;
+
+/** Type of l1_icache0_preload_addr register
+ *  icache0 preload address configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L1-ICache0, which should be used
+         *  together with L1_ICACHE0_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache0_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_addr_reg_t;
+
+/** Type of l1_icache0_preload_size register
+ *  L1 instruction Cache 0 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Configures the size of the first section of prelock on L1-ICache0, which should be
+         *  used together with L1_ICACHE0_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache0_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_preload_size_reg_t;
+
+/** Type of l1_icache1_preload_ctrl register
+ *  L1 instruction Cache 1 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to enable the preloading operation in icache1. Hardware will
+         *  clear it once the operation has finished.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_preload_ena:1;
+        /** l1_icache1_preload_done : RO; bitpos: [1]; default: 1;
+         *  Represents whether the preloading operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache1_preload_done:1;
+        /** l1_icache1_preload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the preloading operation.
+         *  1: Descending
+         */
+        uint32_t l1_icache1_preload_order:1;
+        /** l1_icache1_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l1 icache1 preload.
+         */
+        uint32_t l1_icache1_preload_rgid:4;
+        /** l1_icache1_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  Configures the mode of l1 icache1 preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         */
+        uint32_t l1_icache1_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_ctrl_reg_t;
+
+/** Type of l1_icache1_preload_addr register
+ *  icache1 preload address configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L1-ICache1, which should be used
+         *  together with L1_ICACHE1_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_icache1_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_addr_reg_t;
+
+/** Type of l1_icache1_preload_size register
+ *  L1 instruction Cache 1 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Configures the size of the first section of prelock on L1-ICache1, which should be
+         *  used together with L1_ICACHE1_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_icache1_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_preload_size_reg_t;
+
+/** Type of l1_icache2_preload_ctrl register
+ *  L1 instruction Cache 2 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures preload operation on L1-ICache2. It will be cleared by hardware
+         *  automatically after preload operation is done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_ena:1;
+        /** l1_icache2_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_done:1;
+        /** l1_icache2_preload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of preload operation. 0: ascending, 1: descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_order:1;
+        /** l1_icache2_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l1 icache2 preload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_rgid:4;
+        /** l1_icache2_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  Configures the mode of l1 icache2 preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_ctrl_reg_t;
+
+/** Type of l1_icache2_preload_addr register
+ *  L1 instruction Cache 2 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L1-ICache2, which should be used
+         *  together with L1_ICACHE2_PRELOAD_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_addr_reg_t;
+
+/** Type of l1_icache2_preload_size register
+ *  L1 instruction Cache 2 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Configures the size of the first section of prelock on L1-ICache2, which should be
+         *  used together with L1_ICACHE2_PRELOAD_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_preload_size_reg_t;
+
+/** Type of l1_icache3_preload_ctrl register
+ *  L1 instruction Cache 3 preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures preload operation on L1-ICache3. It will be cleared by hardware
+         *  automatically after preload operation is done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_ena:1;
+        /** l1_icache3_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_done:1;
+        /** l1_icache3_preload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of preload operation. 0: ascending, 1: descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_order:1;
+        /** l1_icache3_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l1 icache3 preload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_rgid:4;
+        /** l1_icache3_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  Configures the mode of l1 icache3 preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_ctrl_reg_t;
+
+/** Type of l1_icache3_preload_addr register
+ *  L1 instruction Cache 3 preload address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L1-ICache3, which should be used
+         *  together with L1_ICACHE3_PRELOAD_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_addr_reg_t;
+
+/** Type of l1_icache3_preload_size register
+ *  L1 instruction Cache 3 preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_preload_size : HRO; bitpos: [13:0]; default: 0;
+         *  Configures the size of the first section of prelock on L1-ICache3, which should be
+         *  used together with L1_ICACHE3_PRELOAD_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_preload_size_reg_t;
+
+/** Type of l1_dcache_preload_ctrl register
+ *  L1 data Cache  preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to enable the preloading operation in dcache. Hardware will
+         *  clear it once the operation has finished.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_preload_ena:1;
+        /** l1_dcache_preload_done : RO; bitpos: [1]; default: 1;
+         *  Represents whether the preloading operation has finished.
+         *  1: Finished
+         */
+        uint32_t l1_dcache_preload_done:1;
+        /** l1_dcache_preload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the preloading operation.
+         *  1: Descending
+         */
+        uint32_t l1_dcache_preload_order:1;
+        /** l1_dcache_preload_rgid : R/W; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l1 dcache preload.
+         */
+        uint32_t l1_dcache_preload_rgid:4;
+        /** l1_dcache_preload_mode : R/W; bitpos: [7]; default: 0;
+         *  Configures the mode of l1 dcache preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         */
+        uint32_t l1_dcache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_ctrl_reg_t;
+
+/** Type of l1_dcache_preload_addr register
+ *  dcache preload address configuration register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L1-DCache, which should be used together
+         *  with L1_DCACHE_PRELOAD_SIZE_REG
+         */
+        uint32_t l1_dcache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_addr_reg_t;
+
+/** Type of l1_dcache_preload_size register
+ *  L1 data Cache  preload size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_preload_size : R/W; bitpos: [13:0]; default: 0;
+         *  Configures the size of the first section of prelock on L1-DCache, which should be
+         *  used together with L1_DCACHE_PRELOAD_ADDR_REG
+         */
+        uint32_t l1_dcache_preload_size:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_dcache_preload_size_reg_t;
+
+/** Type of l2_cache_preload_ctrl register
+ *  L2 Cache preload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_ena : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures preload operation on L2-Cache. It will be cleared by hardware
+         *  automatically after preload operation is done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_ena:1;
+        /** l2_cache_preload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether preload operation is finished or not. 0: not
+         *  finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_done:1;
+        /** l2_cache_preload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of preload operation. 0: ascending, 1: descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_order:1;
+        /** l2_cache_preload_rgid : HRO; bitpos: [6:3]; default: 0;
+         *  Configures the gid of l2 cache preload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_rgid:4;
+        /** l2_cache_preload_mode : HRO; bitpos: [7]; default: 0;
+         *  Configures the mode of l2 cache preload, 0: load data from next level memory, 1:
+         *  not load data from next level memory.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_mode:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_ctrl_reg_t;
+
+/** Type of l2_cache_preload_addr register
+ *  L2 Cache preload address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of preload on L2-Cache, which should be used together
+         *  with L2_CACHE_PRELOAD_SIZE_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_addr_reg_t;
+
+/** Type of l2_cache_preload_size register
+ *  L2 Cache preload size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_preload_size : HRO; bitpos: [15:0]; default: 0;
+         *  Configures the size of the first section of prelock on L2-Cache, which should be
+         *  used together with L2_CACHE_PRELOAD_ADDR_REG
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_preload_size:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_size_reg_t;
+
+
+/** Group: Autoload Control and configuration registers */
+/** Type of l1_icache0_autoload_ctrl register
+ *  L1 instruction Cache 0 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the autoloading operation in icache0.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_autoload_ena:1;
+        /** l1_icache0_autoload_done : RO; bitpos: [1]; default: 1;
+         *  Indicates whether the autoloading operation in icache0 has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache0_autoload_done:1;
+        /** l1_icache0_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the autoloading operation in icache0.
+         *  1: Descending
+         */
+        uint32_t l1_icache0_autoload_order:1;
+        /** l1_icache0_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the trigger mode of the autoloading operation in icache0.
+         *  2: Triggered by cache miss or hit
+         */
+        uint32_t l1_icache0_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache0_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to enable Section 0 for the autoloading operation in icache0.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_autoload_sct0_ena:1;
+        /** l1_icache0_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to enable Section 1 for the autoloading operation in icache0.
+         *  1: Enable
+         */
+        uint32_t l1_icache0_autoload_sct1_ena:1;
+        /** l1_icache0_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  Configures the gid of l1 icache0 autoload.
+         */
+        uint32_t l1_icache0_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_ctrl_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_addr register
+ *  L1 instruction Cache 0 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct0_size register
+ *  L1 instruction Cache 0 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L1-ICache0. Note
+         *  that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_addr register
+ *  L1 instruction Cache 0 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache0_autoload_sct1_size register
+ *  L1 instruction Cache 0 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the second section for autoload operation on L1-ICache0.
+         *  Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache0_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache0_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache1_autoload_ctrl register
+ *  L1 instruction Cache 1 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the autoloading operation in icache1.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_autoload_ena:1;
+        /** l1_icache1_autoload_done : RO; bitpos: [1]; default: 1;
+         *  Indicates whether the autoloading operation in icache1 has finished.
+         *  1: Finished
+         */
+        uint32_t l1_icache1_autoload_done:1;
+        /** l1_icache1_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the autoloading operation in icache1.
+         *  1: Descending
+         */
+        uint32_t l1_icache1_autoload_order:1;
+        /** l1_icache1_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the trigger mode of the autoloading operation in icache1.
+         *  2: Triggered by cache miss or hit
+         */
+        uint32_t l1_icache1_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache1_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to enable Section 0 for the autoloading operation in icache1.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_autoload_sct0_ena:1;
+        /** l1_icache1_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to enable Section 1 for the autoloading operation in icache1.
+         *  1: Enable
+         */
+        uint32_t l1_icache1_autoload_sct1_ena:1;
+        /** l1_icache1_autoload_rgid : R/W; bitpos: [13:10]; default: 0;
+         *  Configures the gid of l1 icache1 autoload.
+         */
+        uint32_t l1_icache1_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_ctrl_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_addr register
+ *  L1 instruction Cache 1 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct0_size register
+ *  L1 instruction Cache 1 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L1-ICache1. Note
+         *  that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_addr register
+ *  L1 instruction Cache 1 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache1_autoload_sct1_size register
+ *  L1 instruction Cache 1 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the second section for autoload operation on L1-ICache1.
+         *  Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_icache1_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache1_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache2_autoload_ctrl register
+ *  L1 instruction Cache 2 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  Configures and disable autoload operation on L1-ICache2.  1: enable, 0: disable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_ena:1;
+        /** l1_icache2_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache2 is finished or
+         *  not. 0: not finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_done:1;
+        /** l1_icache2_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of autoload operation on L1-ICache2. 0: ascending. 1:
+         *  descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_order:1;
+        /** l1_icache2_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache2.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache2_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  Configures the first section for autoload operation on L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct0_ena:1;
+        /** l1_icache2_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  Configures the second section for autoload operation on L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct1_ena:1;
+        /** l1_icache2_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  Configures the gid of l1 icache2 autoload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_ctrl_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_addr register
+ *  L1 instruction Cache 2 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct0_size register
+ *  L1 instruction Cache 2 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L1-ICache2. Note
+         *  that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_addr register
+ *  L1 instruction Cache 2 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache2_autoload_sct1_size register
+ *  L1 instruction Cache 2 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the second section for autoload operation on L1-ICache2.
+         *  Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache2_autoload_sct1_size_reg_t;
+
+/** Type of l1_icache3_autoload_ctrl register
+ *  L1 instruction Cache 3 autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  Configures and disable autoload operation on L1-ICache3.  1: enable, 0: disable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_ena:1;
+        /** l1_icache3_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L1-ICache3 is finished or
+         *  not. 0: not finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_done:1;
+        /** l1_icache3_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of autoload operation on L1-ICache3. 0: ascending. 1:
+         *  descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_order:1;
+        /** l1_icache3_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L1-ICache3.
+         *  0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_icache3_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  Configures the first section for autoload operation on L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct0_ena:1;
+        /** l1_icache3_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  Configures the second section for autoload operation on L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct1_ena:1;
+        /** l1_icache3_autoload_rgid : HRO; bitpos: [13:10]; default: 0;
+         *  Configures the gid of l1 icache3 autoload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_rgid:4;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_ctrl_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_addr register
+ *  L1 instruction Cache 3 autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct0_size register
+ *  L1 instruction Cache 3 autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L1-ICache3. Note
+         *  that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and
+         *  L1_ICACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct0_size_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_addr register
+ *  L1 instruction Cache 3 autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE
+         *  and L1_ICACHE_AUTOLOAD_SCT1_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_addr_reg_t;
+
+/** Type of l1_icache3_autoload_sct1_size register
+ *  L1 instruction Cache 3 autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_icache3_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_ctrl register
+ *  L1 data Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable the autoloading operation in dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_autoload_ena:1;
+        /** l1_dcache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  Indicates whether the autoloading operation in dcache has finished.
+         *  1: Finished
+         */
+        uint32_t l1_dcache_autoload_done:1;
+        /** l1_dcache_autoload_order : R/W; bitpos: [2]; default: 0;
+         *  Configures the direction of the autoloading operation in dcache.
+         *  1: Descending
+         */
+        uint32_t l1_dcache_autoload_order:1;
+        /** l1_dcache_autoload_trigger_mode : R/W; bitpos: [4:3]; default: 0;
+         *  Configures the trigger mode of the autoloading operation in dcache.
+         *  2: Triggered by cache miss or hit
+         */
+        uint32_t l1_dcache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l1_dcache_autoload_sct0_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to enable Section 0 for the autoloading operation in dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_autoload_sct0_ena:1;
+        /** l1_dcache_autoload_sct1_ena : R/W; bitpos: [9]; default: 0;
+         *  Configures whether to enable Section 1 for the autoloading operation in dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_autoload_sct1_ena:1;
+        /** l1_dcache_autoload_sct2_ena : R/W; bitpos: [10]; default: 0;
+         *  Configures whether to enable Section 2 for the autoloading operation in dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_autoload_sct2_ena:1;
+        /** l1_dcache_autoload_sct3_ena : R/W; bitpos: [11]; default: 0;
+         *  Configures whether to enable Section 3 for the autoloading operation in dcache.
+         *  1: Enable
+         */
+        uint32_t l1_dcache_autoload_sct3_ena:1;
+        /** l1_dcache_autoload_rgid : R/W; bitpos: [15:12]; default: 0;
+         *  Configures the gid of l1 dcache autoload.
+         */
+        uint32_t l1_dcache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_ctrl_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_addr register
+ *  L1 data Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_SIZE
+         *  and L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct0_size register
+ *  L1 data Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct0_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L1-DCache. Note
+         *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT0_ADDR and
+         *  L1_DCACHE_AUTOLOAD_SCT0_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct0_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_SIZE
+         *  and L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct1_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct1_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the second section for autoload operation on L1-DCache. Note
+         *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT1_ADDR and
+         *  L1_DCACHE_AUTOLOAD_SCT1_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct1_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_addr register
+ *  L1 data Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the third section for autoload operation on
+         *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_SIZE
+         *  and L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct2_size register
+ *  L1 data Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct2_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the third section for autoload operation on L1-DCache. Note
+         *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT2_ADDR and
+         *  L1_DCACHE_AUTOLOAD_SCT2_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct2_size_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_addr register
+ *  L1 data Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the fourth section for autoload operation on
+         *  L1-DCache. Note that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_SIZE
+         *  and L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_addr_reg_t;
+
+/** Type of l1_dcache_autoload_sct3_size register
+ *  L1 data Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_autoload_sct3_size : R/W; bitpos: [27:0]; default: 0;
+         *  Configures the size of the fourth section for autoload operation on L1-DCache. Note
+         *  that it should be used together with L1_DCACHE_AUTOLOAD_SCT3_ADDR and
+         *  L1_DCACHE_AUTOLOAD_SCT3_ENA.
+         */
+        uint32_t l1_dcache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l1_dcache_autoload_sct3_size_reg_t;
+
+/** Type of l2_cache_autoload_ctrl register
+ *  L2 Cache autoload-operation control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_ena : HRO; bitpos: [0]; default: 0;
+         *  Configures and disable autoload operation on L2-Cache.  1: enable, 0: disable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_ena:1;
+        /** l2_cache_autoload_done : RO; bitpos: [1]; default: 1;
+         *  The bit is used to indicate whether autoload operation on L2-Cache is finished or
+         *  not. 0: not finished. 1: finished.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_done:1;
+        /** l2_cache_autoload_order : HRO; bitpos: [2]; default: 0;
+         *  Configures the direction of autoload operation on L2-Cache. 0: ascending. 1:
+         *  descending.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_order:1;
+        /** l2_cache_autoload_trigger_mode : HRO; bitpos: [4:3]; default: 0;
+         *  The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3:
+         *  miss-trigger, 1: hit-trigger, 2: miss-hit-trigger.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_trigger_mode:2;
+        uint32_t reserved_5:3;
+        /** l2_cache_autoload_sct0_ena : HRO; bitpos: [8]; default: 0;
+         *  Configures the first section for autoload operation on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct0_ena:1;
+        /** l2_cache_autoload_sct1_ena : HRO; bitpos: [9]; default: 0;
+         *  Configures the second section for autoload operation on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct1_ena:1;
+        /** l2_cache_autoload_sct2_ena : HRO; bitpos: [10]; default: 0;
+         *  Configures the third section for autoload operation on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct2_ena:1;
+        /** l2_cache_autoload_sct3_ena : HRO; bitpos: [11]; default: 0;
+         *  Configures the fourth section for autoload operation on L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct3_ena:1;
+        /** l2_cache_autoload_rgid : HRO; bitpos: [15:12]; default: 0;
+         *  Configures the gid of l2 cache autoload.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_rgid:4;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_sct0_addr register
+ *  L2 Cache autoload section 0 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the first section for autoload operation on
+         *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and
+         *  L2_CACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct0_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct0_size register
+ *  L2 Cache autoload section 0 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct0_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the first section for autoload operation on L2-Cache. Note
+         *  that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and
+         *  L2_CACHE_AUTOLOAD_SCT0_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct0_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct0_size_reg_t;
+
+/** Type of l2_cache_autoload_sct1_addr register
+ *  L2 Cache autoload section 1 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the second section for autoload operation on
+         *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and
+         *  L2_CACHE_AUTOLOAD_SCT1_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct1_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct1_size register
+ *  L2 Cache autoload section 1 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct1_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the second section for autoload operation on L2-Cache. Note
+         *  that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and
+         *  L2_CACHE_AUTOLOAD_SCT1_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct1_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct1_size_reg_t;
+
+/** Type of l2_cache_autoload_sct2_addr register
+ *  L2 Cache autoload section 2 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the third section for autoload operation on
+         *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and
+         *  L2_CACHE_AUTOLOAD_SCT2_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct2_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct2_size register
+ *  L2 Cache autoload section 2 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct2_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the third section for autoload operation on L2-Cache. Note
+         *  that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and
+         *  L2_CACHE_AUTOLOAD_SCT2_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct2_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct2_size_reg_t;
+
+/** Type of l2_cache_autoload_sct3_addr register
+ *  L2 Cache autoload section 3 address configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Configures the start address of the fourth section for autoload operation on
+         *  L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and
+         *  L2_CACHE_AUTOLOAD_SCT3_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct3_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_addr_reg_t;
+
+/** Type of l2_cache_autoload_sct3_size register
+ *  L2 Cache autoload section 3 size configure register
+ */
+typedef union {
+    struct {
+        /** l2_cache_autoload_sct3_size : HRO; bitpos: [27:0]; default: 0;
+         *  Configures the size of the fourth section for autoload operation on L2-Cache. Note
+         *  that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and
+         *  L2_CACHE_AUTOLOAD_SCT3_ENA.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_autoload_sct3_size:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_sct3_size_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of l1_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L1-ICache0 due to
+         *  bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_ena:1;
+        /** l1_ibus1_ovf_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L1-ICache1 due to
+         *  bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_ena:1;
+        /** l1_ibus2_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_ena:1;
+        /** l1_ibus3_ovf_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_ena:1;
+        /** l1_dbus0_ovf_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L1-DCache due to
+         *  bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_ena:1;
+        /** l1_dbus1_ovf_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L1-DCache due to
+         *  bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_ena:1;
+        /** l1_dbus2_ovf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_ena:1;
+        /** l1_dbus3_ovf_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_ena:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due
+         *  to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_clr:1;
+        /** l1_ibus1_ovf_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due
+         *  to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_clr:1;
+        /** l1_ibus2_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_clr:1;
+        /** l1_ibus3_ovf_int_clr : WT; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_clr:1;
+        /** l1_dbus0_ovf_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_clr:1;
+        /** l1_dbus1_ovf_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L1-DCache due
+         *  to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_clr:1;
+        /** l1_dbus2_ovf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_clr:1;
+        /** l1_dbus3_ovf_int_clr : WT; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_clr:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0
+         *  due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_raw:1;
+        /** l1_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1
+         *  due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_raw:1;
+        /** l1_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2
+         *  due to bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_ovf_int_raw:1;
+        /** l1_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3
+         *  due to bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_ovf_int_raw:1;
+        /** l1_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_raw:1;
+        /** l1_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_raw:1;
+        /** l1_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_ovf_int_raw:1;
+        /** l1_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache
+         *  due to bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_ovf_int_raw:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l1_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_ovf_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache0 due to bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_ovf_int_st:1;
+        /** l1_ibus1_ovf_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-ICache1 due to bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_ovf_int_st:1;
+        /** l1_ibus2_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_ovf_int_st:1;
+        /** l1_ibus3_ovf_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_ovf_int_st:1;
+        /** l1_dbus0_ovf_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_ovf_int_st:1;
+        /** l1_dbus1_ovf_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L1-DCache due to bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_ovf_int_st:1;
+        /** l1_dbus2_ovf_int_st : RO; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_ovf_int_st:1;
+        /** l1_dbus3_ovf_int_st : RO; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_ovf_int_st:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l1_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures interrupt of access fail that occurs in L1-ICache0 due to cpu accesses
+         *  L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_ena:1;
+        /** l1_icache1_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures interrupt of access fail that occurs in L1-ICache1 due to cpu accesses
+         *  L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_ena:1;
+        /** l1_icache2_fail_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_ena:1;
+        /** l1_icache3_fail_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_ena:1;
+        /** l1_dcache_fail_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures interrupt of access fail that occurs in L1-DCache due to cpu accesses
+         *  L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l1_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to
+         *  cpu accesses L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_clr:1;
+        /** l1_icache1_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to
+         *  cpu accesses L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_clr:1;
+        /** l1_icache2_fail_int_clr : WT; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_clr:1;
+        /** l1_icache3_fail_int_clr : WT; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_clr:1;
+        /** l1_dcache_fail_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L1-DCache due to
+         *  cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l1_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache0.
+         */
+        uint32_t l1_icache0_fail_int_raw:1;
+        /** l1_icache1_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache1.
+         */
+        uint32_t l1_icache1_fail_int_raw:1;
+        /** l1_icache2_fail_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache2.
+         */
+        uint32_t l1_icache2_fail_int_raw:1;
+        /** l1_icache3_fail_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-ICache3.
+         */
+        uint32_t l1_icache3_fail_int_raw:1;
+        /** l1_dcache_fail_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l1_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_int_st:1;
+        /** l1_icache1_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due
+         *  to cpu accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_int_st:1;
+        /** l1_icache2_fail_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache2_fail_int_st:1;
+        /** l1_icache3_fail_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_icache3_fail_int_st:1;
+        /** l1_dcache_fail_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L1-DCache due
+         *  to cpu accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_int_st_reg_t;
+
+/** Type of l1_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures interrupt of L1-ICache0 preload-operation. If preload operation is done,
+         *  interrupt occurs.
+         */
+        uint32_t l1_icache0_pld_done_int_ena:1;
+        /** l1_icache1_pld_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures interrupt of L1-ICache1 preload-operation. If preload operation is done,
+         *  interrupt occurs.
+         */
+        uint32_t l1_icache1_pld_done_int_ena:1;
+        /** l1_icache2_pld_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_done_int_ena:1;
+        /** l1_icache3_pld_done_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_done_int_ena:1;
+        /** l1_dcache_pld_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures interrupt of L1-DCache preload-operation. If preload operation is done,
+         *  interrupt occurs.
+         */
+        uint32_t l1_dcache_pld_done_int_ena:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Configures interrupt of Cache sync-operation done.
+         */
+        uint32_t sync_done_int_ena:1;
+        /** l1_icache0_pld_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Configures interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_ena:1;
+        /** l1_icache1_pld_err_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Configures interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_ena:1;
+        /** l1_icache2_pld_err_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_err_int_ena:1;
+        /** l1_icache3_pld_err_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_err_int_ena:1;
+        /** l1_dcache_pld_err_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Configures interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_ena:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Configures interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l1_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_clr:1;
+        /** l1_icache1_pld_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_clr:1;
+        /** l1_icache2_pld_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_done_int_clr:1;
+        /** l1_icache3_pld_done_int_clr : WT; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_done_int_clr:1;
+        /** l1_dcache_pld_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_clr:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_clr : WT; bitpos: [6]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when Cache sync-operation is
+         *  done.
+         */
+        uint32_t sync_done_int_clr:1;
+        /** l1_icache0_pld_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_clr:1;
+        /** l1_icache1_pld_err_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_clr:1;
+        /** l1_icache2_pld_err_int_clr : WT; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_err_int_clr:1;
+        /** l1_icache3_pld_err_int_clr : WT; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_err_int_clr:1;
+        /** l1_dcache_pld_err_int_clr : WT; bitpos: [11]; default: 0;
+         *  The bit is used to clear interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_clr:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l1_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache0_pld_done_int_raw:1;
+        /** l1_icache1_pld_done_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is
+         *  done.
+         */
+        uint32_t l1_icache1_pld_done_int_raw:1;
+        /** l1_icache2_pld_done_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_done_int_raw:1;
+        /** l1_icache3_pld_done_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_done_int_raw:1;
+        /** l1_dcache_pld_done_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation is
+         *  done.
+         */
+        uint32_t l1_dcache_pld_done_int_raw:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation is done.
+         */
+        uint32_t sync_done_int_raw:1;
+        /** l1_icache0_pld_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache0_pld_err_int_raw:1;
+        /** l1_icache1_pld_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_icache1_pld_err_int_raw:1;
+        /** l1_icache2_pld_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_err_int_raw:1;
+        /** l1_icache3_pld_err_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_err_int_raw:1;
+        /** l1_dcache_pld_err_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L1-DCache preload-operation
+         *  error occurs.
+         */
+        uint32_t l1_dcache_pld_err_int_raw:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt that occurs only when Cache sync-operation error
+         *  occurs.
+         */
+        uint32_t sync_err_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l1_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache0
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache0_pld_done_int_st:1;
+        /** l1_icache1_pld_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-ICache1
+         *  preload-operation is done.
+         */
+        uint32_t l1_icache1_pld_done_int_st:1;
+        /** l1_icache2_pld_done_int_st : RO; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_done_int_st:1;
+        /** l1_icache3_pld_done_int_st : RO; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_done_int_st:1;
+        /** l1_dcache_pld_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L1-DCache
+         *  preload-operation is done.
+         */
+        uint32_t l1_dcache_pld_done_int_st:1;
+        uint32_t reserved_5:1;
+        /** sync_done_int_st : RO; bitpos: [6]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when Cache
+         *  sync-operation is done.
+         */
+        uint32_t sync_done_int_st:1;
+        /** l1_icache0_pld_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache0 preload-operation error.
+         */
+        uint32_t l1_icache0_pld_err_int_st:1;
+        /** l1_icache1_pld_err_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-ICache1 preload-operation error.
+         */
+        uint32_t l1_icache1_pld_err_int_st:1;
+        /** l1_icache2_pld_err_int_st : RO; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_err_int_st:1;
+        /** l1_icache3_pld_err_int_st : RO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_err_int_st:1;
+        /** l1_dcache_pld_err_int_st : RO; bitpos: [11]; default: 0;
+         *  The bit indicates the status of the interrupt of L1-DCache preload-operation error.
+         */
+        uint32_t l1_dcache_pld_err_int_st:1;
+        uint32_t reserved_12:1;
+        /** sync_err_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the status of the interrupt of Cache sync-operation error.
+         */
+        uint32_t sync_err_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_int_st_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_ena register
+ *  Cache Access Counter Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_ena : HRO; bitpos: [8]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+         *  bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_ovf_int_ena:1;
+        /** l2_ibus1_ovf_int_ena : HRO; bitpos: [9]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+         *  bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_ovf_int_ena:1;
+        /** l2_ibus2_ovf_int_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_ovf_int_ena:1;
+        /** l2_ibus3_ovf_int_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_ovf_int_ena:1;
+        /** l2_dbus0_ovf_int_ena : HRO; bitpos: [12]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+         *  bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_ovf_int_ena:1;
+        /** l2_dbus1_ovf_int_ena : HRO; bitpos: [13]; default: 0;
+         *  Configures interrupt of one of counters overflow that occurs in L2-Cache due to
+         *  bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_ovf_int_ena:1;
+        /** l2_dbus2_ovf_int_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_ovf_int_ena:1;
+        /** l2_dbus3_ovf_int_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_ovf_int_ena:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_ena_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_clr register
+ *  Cache Access Counter Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_clr : WT; bitpos: [8]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_ovf_int_clr:1;
+        /** l2_ibus1_ovf_int_clr : WT; bitpos: [9]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_ovf_int_clr:1;
+        /** l2_ibus2_ovf_int_clr : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_ovf_int_clr:1;
+        /** l2_ibus3_ovf_int_clr : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_ovf_int_clr:1;
+        /** l2_dbus0_ovf_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_ovf_int_clr:1;
+        /** l2_dbus1_ovf_int_clr : WT; bitpos: [13]; default: 0;
+         *  The bit is used to clear counters overflow interrupt and counters in L2-Cache due
+         *  to bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_ovf_int_clr:1;
+        /** l2_dbus2_ovf_int_clr : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_ovf_int_clr:1;
+        /** l2_dbus3_ovf_int_clr : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_ovf_int_clr:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_clr_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_raw register
+ *  Cache Access Counter Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-ICache0.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_ovf_int_raw:1;
+        /** l2_ibus1_ovf_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-ICache1.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_ovf_int_raw:1;
+        /** l2_ibus2_ovf_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_ovf_int_raw:1;
+        /** l2_ibus3_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_ovf_int_raw:1;
+        /** l2_dbus0_ovf_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus0 accesses L2-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_ovf_int_raw:1;
+        /** l2_dbus1_ovf_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus1 accesses L2-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_ovf_int_raw:1;
+        /** l2_dbus2_ovf_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus2 accesses L2-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_ovf_int_raw:1;
+        /** l2_dbus3_ovf_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
+         *  The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache
+         *  due to bus3 accesses L2-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_ovf_int_raw:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_raw_reg_t;
+
+/** Type of l2_cache_acs_cnt_int_st register
+ *  Cache Access Counter Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_ovf_int_st : RO; bitpos: [8]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_ovf_int_st:1;
+        /** l2_ibus1_ovf_int_st : RO; bitpos: [9]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_ovf_int_st:1;
+        /** l2_ibus2_ovf_int_st : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_ovf_int_st:1;
+        /** l2_ibus3_ovf_int_st : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_ovf_int_st:1;
+        /** l2_dbus0_ovf_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus0 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_ovf_int_st:1;
+        /** l2_dbus1_ovf_int_st : RO; bitpos: [13]; default: 0;
+         *  The bit indicates the interrupt status of one of counters overflow that occurs in
+         *  L2-Cache due to bus1 accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_ovf_int_st:1;
+        /** l2_dbus2_ovf_int_st : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_ovf_int_st:1;
+        /** l2_dbus3_ovf_int_st : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_ovf_int_st:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_int_st_reg_t;
+
+/** Type of l2_cache_acs_fail_int_ena register
+ *  Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_ena : HRO; bitpos: [5]; default: 0;
+         *  Configures interrupt of access fail that occurs in L2-Cache due to l1 cache
+         *  accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_ena_reg_t;
+
+/** Type of l2_cache_acs_fail_int_clr register
+ *  L1-Cache Access Fail Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1
+         *  cache accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_clr_reg_t;
+
+/** Type of l2_cache_acs_fail_int_raw register
+ *  Cache Access Fail Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt of access fail that occurs in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_raw_reg_t;
+
+/** Type of l2_cache_acs_fail_int_st register
+ *  Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_fail_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the interrupt status of access fail that occurs in L2-Cache due
+         *  to l1 cache accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_int_st_reg_t;
+
+/** Type of l2_cache_sync_preload_int_ena register
+ *  L1-Cache Access Fail Interrupt enable register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_ena : HRO; bitpos: [5]; default: 0;
+         *  Configures interrupt of L2-Cache preload-operation done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_done_int_ena:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_ena : HRO; bitpos: [12]; default: 0;
+         *  Configures interrupt of L2-Cache preload-operation error.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_err_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_ena_reg_t;
+
+/** Type of l2_cache_sync_preload_int_clr register
+ *  Sync Preload operation Interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_clr : WT; bitpos: [5]; default: 0;
+         *  The bit is used to clear interrupt that occurs only when L2-Cache preload-operation
+         *  is done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_done_int_clr:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_clr : WT; bitpos: [12]; default: 0;
+         *  The bit is used to clear interrupt of L2-Cache preload-operation error.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_err_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_clr_reg_t;
+
+/** Type of l2_cache_sync_preload_int_raw register
+ *  Sync Preload operation Interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation is
+         *  done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_done_int_raw:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw bit of the interrupt that occurs only when L2-Cache preload-operation error
+         *  occurs.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_err_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_raw_reg_t;
+
+/** Type of l2_cache_sync_preload_int_st register
+ *  L1-Cache Access Fail Interrupt status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_done_int_st : RO; bitpos: [5]; default: 0;
+         *  The bit indicates the status of the interrupt that occurs only when L2-Cache
+         *  preload-operation is done.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_done_int_st:1;
+        uint32_t reserved_6:6;
+        /** l2_cache_pld_err_int_st : RO; bitpos: [12]; default: 0;
+         *  The bit indicates the status of the interrupt of L2-Cache preload-operation error.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_err_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_int_st_reg_t;
+
+
+/** Group: Cache Access Fail Configuration register */
+/** Type of l1_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_acs_fail_check_mode : R/W; bitpos: [0]; default: 0;
+         *  Configures l1 icache0 access fail check mode. 0: the access fail is not propagated
+         *  to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache0_acs_fail_check_mode:1;
+        /** l1_icache1_acs_fail_check_mode : R/W; bitpos: [1]; default: 0;
+         *  Configures l1 icache1 access fail check mode. 0: the access fail is not propagated
+         *  to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache1_acs_fail_check_mode:1;
+        /** l1_icache2_acs_fail_check_mode : R/W; bitpos: [2]; default: 0;
+         *  Configures l1 icache2 access fail check mode. 0: the access fail is not propagated
+         *  to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache2_acs_fail_check_mode:1;
+        /** l1_icache3_acs_fail_check_mode : R/W; bitpos: [3]; default: 0;
+         *  Configures l1 icache3 access fail check mode. 0: the access fail is not propagated
+         *  to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_icache3_acs_fail_check_mode:1;
+        /** l1_dcache_acs_fail_check_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures l1 dcache access fail check mode. 0: the access fail is not propagated
+         *  to the request, 1: the access fail is propagated to the request
+         */
+        uint32_t l1_dcache_acs_fail_check_mode:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_fail_ctrl_reg_t;
+
+/** Type of l2_cache_acs_fail_ctrl register
+ *  Cache Access Fail Configuration register
+ */
+typedef union {
+    struct {
+        /** l2_cache_acs_fail_check_mode : HRO; bitpos: [0]; default: 0;
+         *  Configures l2 cache access fail check mode. 0: the access fail is not propagated to
+         *  the request, 1: the access fail is propagated to the request
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_acs_fail_check_mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_ctrl_reg_t;
+
+
+/** Group: Access Statistics registers */
+/** Type of l1_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_cnt_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to enable IBUS0 counter.
+         *  1: Enable
+         */
+        uint32_t l1_ibus0_cnt_ena:1;
+        /** l1_ibus1_cnt_ena : R/W; bitpos: [1]; default: 0;
+         *  Configures whether to enable IBUS1 counter.
+         *  1: Enable
+         */
+        uint32_t l1_ibus1_cnt_ena:1;
+        /** l1_ibus2_cnt_ena : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_ena:1;
+        /** l1_ibus3_cnt_ena : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_ena:1;
+        /** l1_dbus0_cnt_ena : R/W; bitpos: [4]; default: 0;
+         *  Configures whether to enable DBUS0 counter.
+         *  1: Enable
+         */
+        uint32_t l1_dbus0_cnt_ena:1;
+        /** l1_dbus1_cnt_ena : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable DBUS1 counter.
+         *  1: Enable
+         */
+        uint32_t l1_dbus1_cnt_ena:1;
+        /** l1_dbus2_cnt_ena : R/W; bitpos: [6]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_ena:1;
+        /** l1_dbus3_cnt_ena : R/W; bitpos: [7]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_ena:1;
+        uint32_t reserved_8:8;
+        /** l1_ibus0_cnt_clr : WT; bitpos: [16]; default: 0;
+         *  Configures whether to clear IBUS0 counter.
+         *  1: Clear
+         */
+        uint32_t l1_ibus0_cnt_clr:1;
+        /** l1_ibus1_cnt_clr : WT; bitpos: [17]; default: 0;
+         *  Configures whether to clear IBUS1 counter.
+         *  1: Clear
+         */
+        uint32_t l1_ibus1_cnt_clr:1;
+        /** l1_ibus2_cnt_clr : WT; bitpos: [18]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus2_cnt_clr:1;
+        /** l1_ibus3_cnt_clr : WT; bitpos: [19]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_ibus3_cnt_clr:1;
+        /** l1_dbus0_cnt_clr : WT; bitpos: [20]; default: 0;
+         *  Configures whether to clear DBUS0 counter.
+         *  1: Clear
+         */
+        uint32_t l1_dbus0_cnt_clr:1;
+        /** l1_dbus1_cnt_clr : WT; bitpos: [21]; default: 0;
+         *  Configures whether to clear DBUS1 counter.
+         *  1: Clear
+         */
+        uint32_t l1_dbus1_cnt_clr:1;
+        /** l1_dbus2_cnt_clr : WT; bitpos: [22]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus2_cnt_clr:1;
+        /** l1_dbus3_cnt_clr : WT; bitpos: [23]; default: 0;
+         *  Reserved
+         */
+        uint32_t l1_dbus3_cnt_clr:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} cache_l1_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l1_ibus0_acs_hit_cnt register
+ *  L1-ICache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_miss_cnt register
+ *  L1-ICache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_conflict_cnt register
+ *  L1-ICache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-ICache0.
+         */
+        uint32_t l1_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus0_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         */
+        uint32_t l1_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_hit_cnt register
+ *  L1-ICache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_miss_cnt register
+ *  L1-ICache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_conflict_cnt register
+ *  L1-ICache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-ICache1.
+         */
+        uint32_t l1_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus1_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         */
+        uint32_t l1_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_hit_cnt register
+ *  L1-ICache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_miss_cnt register
+ *  L1-ICache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_conflict_cnt register
+ *  L1-ICache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-ICache2.
+         */
+        uint32_t l1_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus2_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         */
+        uint32_t l1_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_hit_cnt register
+ *  L1-ICache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_miss_cnt register
+ *  L1-ICache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_conflict_cnt register
+ *  L1-ICache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-ICache3.
+         */
+        uint32_t l1_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_ibus3_acs_nxtlvl_rd_cnt register
+ *  L1-ICache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-ICache accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         */
+        uint32_t l1_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_hit_cnt register
+ *  L1-DCache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_miss_cnt register
+ *  L1-DCache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_conflict_cnt register
+ *  L1-DCache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus0_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_hit_cnt register
+ *  L1-DCache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_miss_cnt register
+ *  L1-DCache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_conflict_cnt register
+ *  L1-DCache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus1_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus1 accesses L1-DCache.
+         */
+        uint32_t l1_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_hit_cnt register
+ *  L1-DCache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_miss_cnt register
+ *  L1-DCache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_conflict_cnt register
+ *  L1-DCache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus2_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus2 accesses L1-DCache.
+         */
+        uint32_t l1_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_hit_cnt register
+ *  L1-DCache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_miss_cnt register
+ *  L1-DCache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_conflict_cnt register
+ *  L1-DCache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when bus3 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_rd_cnt register
+ *  L1-DCache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l1_dbus3_acs_nxtlvl_wr_cnt register
+ *  L1-DCache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l1_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when bus0 accesses L1-DCache.
+         */
+        uint32_t l1_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_cache_acs_cnt_ctrl register
+ *  Cache Access Counter enable and clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** l2_ibus0_cnt_ena : HRO; bitpos: [8]; default: 0;
+         *  Configures ibus0 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_cnt_ena:1;
+        /** l2_ibus1_cnt_ena : HRO; bitpos: [9]; default: 0;
+         *  Configures ibus1 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_cnt_ena:1;
+        /** l2_ibus2_cnt_ena : HRO; bitpos: [10]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_cnt_ena:1;
+        /** l2_ibus3_cnt_ena : HRO; bitpos: [11]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_cnt_ena:1;
+        /** l2_dbus0_cnt_ena : HRO; bitpos: [12]; default: 0;
+         *  Configures dbus0 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_cnt_ena:1;
+        /** l2_dbus1_cnt_ena : HRO; bitpos: [13]; default: 0;
+         *  Configures dbus1 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_cnt_ena:1;
+        /** l2_dbus2_cnt_ena : HRO; bitpos: [14]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_cnt_ena:1;
+        /** l2_dbus3_cnt_ena : HRO; bitpos: [15]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_cnt_ena:1;
+        uint32_t reserved_16:8;
+        /** l2_ibus0_cnt_clr : WT; bitpos: [24]; default: 0;
+         *  The bit is used to clear ibus0 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_cnt_clr:1;
+        /** l2_ibus1_cnt_clr : WT; bitpos: [25]; default: 0;
+         *  The bit is used to clear ibus1 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_cnt_clr:1;
+        /** l2_ibus2_cnt_clr : HRO; bitpos: [26]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_cnt_clr:1;
+        /** l2_ibus3_cnt_clr : HRO; bitpos: [27]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_cnt_clr:1;
+        /** l2_dbus0_cnt_clr : WT; bitpos: [28]; default: 0;
+         *  The bit is used to clear dbus0 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_cnt_clr:1;
+        /** l2_dbus1_cnt_clr : WT; bitpos: [29]; default: 0;
+         *  The bit is used to clear dbus1 counter in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_cnt_clr:1;
+        /** l2_dbus2_cnt_clr : HRO; bitpos: [30]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_cnt_clr:1;
+        /** l2_dbus3_cnt_clr : HRO; bitpos: [31]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_cnt_clr:1;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_cnt_ctrl_reg_t;
+
+/** Type of l2_ibus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache0 accesses L2-Cache due to
+         *  bus0 accessing L1-ICache0.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache0 accesses
+         *  L2-Cache due to bus0 accessing L1-ICache0.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache1 accesses L2-Cache due to
+         *  bus1 accessing L1-ICache1.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache1 accesses
+         *  L2-Cache due to bus1 accessing L1-ICache1.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache2 accesses L2-Cache due to
+         *  bus2 accessing L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache2 accesses
+         *  L2-Cache due to bus2 accessing L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-ICache3 accesses L2-Cache due to
+         *  bus3 accessing L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-ICache3 accesses
+         *  L2-Cache due to bus3 accessing L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_ibus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_ibus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_ibus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_hit_cnt register
+ *  L2-Cache bus0 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_miss_cnt register
+ *  L2-Cache bus0 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus0 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_conflict_cnt register
+ *  L2-Cache bus0 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus0 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus0 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus0_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus0 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus0_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus0 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus0_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_hit_cnt register
+ *  L2-Cache bus1 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_miss_cnt register
+ *  L2-Cache bus1 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus1 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_conflict_cnt register
+ *  L2-Cache bus1 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus1 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus1 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus1_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus1 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus1_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus1 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus1_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_hit_cnt register
+ *  L2-Cache bus2 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_miss_cnt register
+ *  L2-Cache bus2 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus2 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_conflict_cnt register
+ *  L2-Cache bus2 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus2 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus2 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus2_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus2 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus2_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus2 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus2_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_hit_cnt register
+ *  L2-Cache bus3 Hit-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_hit_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of hits when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_hit_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_hit_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_miss_cnt register
+ *  L2-Cache bus3 Miss-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_miss_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of missing when L1-DCache accesses L2-Cache due to
+         *  bus3 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_miss_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_miss_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_conflict_cnt register
+ *  L2-Cache bus3 Conflict-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_conflict_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of access-conflicts when L1-DCache accesses
+         *  L2-Cache due to bus3 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_conflict_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_conflict_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_rd_cnt register
+ *  L2-Cache bus3 Next-Level-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_rd_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of times that L2-Cache accesses external memory due
+         *  to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_nxtlvl_rd_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t;
+
+/** Type of l2_dbus3_acs_nxtlvl_wr_cnt register
+ *  L2-Cache bus3 WB-Access Counter register
+ */
+typedef union {
+    struct {
+        /** l2_dbus3_nxtlvl_wr_cnt : RO; bitpos: [31:0]; default: 0;
+         *  The register records the number of write back when L1-DCache accesses L2-Cache due
+         *  to bus3 accessing L1-DCache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_dbus3_nxtlvl_wr_cnt:32;
+    };
+    uint32_t val;
+} cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t;
+
+
+/** Group: Access Fail Debug registers */
+/** Type of l1_icache0_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_id:16;
+        /** l1_icache0_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache0_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache0 accesses L1-ICache.
+         */
+        uint32_t l1_icache0_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache0_acs_fail_addr_reg_t;
+
+/** Type of l1_icache1_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_id:16;
+        /** l1_icache1_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache1_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache1_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache1 accesses L1-ICache.
+         */
+        uint32_t l1_icache1_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache1_acs_fail_addr_reg_t;
+
+/** Type of l1_icache2_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_id:16;
+        /** l1_icache2_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache2_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache2_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache2 accesses L1-ICache.
+         */
+        uint32_t l1_icache2_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache2_acs_fail_addr_reg_t;
+
+/** Type of l1_icache3_acs_fail_id_attr register
+ *  L1-ICache0 Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_id:16;
+        /** l1_icache3_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_id_attr_reg_t;
+
+/** Type of l1_icache3_acs_fail_addr register
+ *  L1-ICache0 Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_icache3_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache3 accesses L1-ICache.
+         */
+        uint32_t l1_icache3_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_icache3_acs_fail_addr_reg_t;
+
+/** Type of l1_dcache_acs_fail_id_attr register
+ *  L1-DCache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_id:16;
+        /** l1_dcache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_id_attr_reg_t;
+
+/** Type of l1_dcache_acs_fail_addr register
+ *  L1-DCache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l1_dcache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when cache accesses L1-DCache.
+         */
+        uint32_t l1_dcache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l1_dcache_acs_fail_addr_reg_t;
+
+/** Type of l2_cache_acs_fail_id_attr register
+ *  L2-Cache Access Fail ID/attribution information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_id : RO; bitpos: [15:0]; default: 0;
+         *  The register records the ID of fail-access when L1-Cache accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_id:16;
+        /** l2_cache_fail_attr : RO; bitpos: [31:16]; default: 0;
+         *  The register records the attribution of fail-access when L1-Cache accesses L2-Cache
+         *  due to cache accessing L1-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_attr:16;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_id_attr_reg_t;
+
+/** Type of l2_cache_acs_fail_addr register
+ *  L2-Cache Access Fail Address information register
+ */
+typedef union {
+    struct {
+        /** l2_cache_fail_addr : RO; bitpos: [31:0]; default: 0;
+         *  The register records the address of fail-access when L1-Cache accesses L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_fail_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_acs_fail_addr_reg_t;
+
+
+/** Group: Operation Exception registers */
+/** Type of l1_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_err_code : RO; bitpos: [1:0]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache0.
+         */
+        uint32_t l1_icache0_pld_err_code:2;
+        /** l1_icache1_pld_err_code : RO; bitpos: [3:2]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-ICache1.
+         */
+        uint32_t l1_icache1_pld_err_code:2;
+        /** l1_icache2_pld_err_code : RO; bitpos: [5:4]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_err_code:2;
+        /** l1_icache3_pld_err_code : RO; bitpos: [7:6]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_err_code:2;
+        /** l1_dcache_pld_err_code : RO; bitpos: [9:8]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L1-DCache.
+         */
+        uint32_t l1_dcache_pld_err_code:2;
+        uint32_t reserved_10:2;
+        /** sync_err_code : RO; bitpos: [13:12]; default: 0;
+         *  The values 0-2 are available which means sync map, command conflict and size are
+         *  error in Cache System.
+         */
+        uint32_t sync_err_code:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_preload_exception_reg_t;
+
+/** Type of l2_cache_sync_preload_exception register
+ *  Cache Sync/Preload Operation exception register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** l2_cache_pld_err_code : RO; bitpos: [11:10]; default: 0;
+         *  The value 2 is Only available which means preload size is error in L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_err_code:2;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_preload_exception_reg_t;
+
+
+/** Group: Sync Reset control and configuration registers */
+/** Type of l1_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_sync_rst : R/W; bitpos: [0]; default: 0;
+         *  Configures reset sync-logic inside L1-ICache0. Recommend that this should only be
+         *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache0_sync_rst:1;
+        /** l1_icache1_sync_rst : R/W; bitpos: [1]; default: 0;
+         *  Configures reset sync-logic inside L1-ICache1. Recommend that this should only be
+         *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_icache1_sync_rst:1;
+        /** l1_icache2_sync_rst : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_sync_rst:1;
+        /** l1_icache3_sync_rst : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_sync_rst:1;
+        /** l1_dcache_sync_rst : R/W; bitpos: [4]; default: 0;
+         *  Configures reset sync-logic inside L1-DCache. Recommend that this should only be
+         *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+         */
+        uint32_t l1_dcache_sync_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_sync_rst_ctrl_reg_t;
+
+/** Type of l2_cache_sync_rst_ctrl register
+ *  Cache Sync Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_sync_rst : HRO; bitpos: [5]; default: 0;
+         *  Configures reset sync-logic inside L2-Cache. Recommend that this should only be
+         *  used to initialize sync-logic when some fatal error of sync-logic occurs.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_sync_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_sync_rst_ctrl_reg_t;
+
+
+/** Group: Preload Reset control and configuration registers */
+/** Type of l1_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_pld_rst : R/W; bitpos: [0]; default: 0;
+         *  Configures reset preload-logic inside L1-ICache0. Recommend that this should only
+         *  be used to initialize preload-logic when some fatal error of preload-logic occurs.
+         */
+        uint32_t l1_icache0_pld_rst:1;
+        /** l1_icache1_pld_rst : R/W; bitpos: [1]; default: 0;
+         *  Configures reset preload-logic inside L1-ICache1. Recommend that this should only
+         *  be used to initialize preload-logic when some fatal error of preload-logic occurs.
+         */
+        uint32_t l1_icache1_pld_rst:1;
+        /** l1_icache2_pld_rst : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_pld_rst:1;
+        /** l1_icache3_pld_rst : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_pld_rst:1;
+        /** l1_dcache_pld_rst : R/W; bitpos: [4]; default: 0;
+         *  Configures reset preload-logic inside L1-DCache. Recommend that this should only be
+         *  used to initialize preload-logic when some fatal error of preload-logic occurs.
+         */
+        uint32_t l1_dcache_pld_rst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_preload_rst_ctrl_reg_t;
+
+/** Type of l2_cache_preload_rst_ctrl register
+ *  Cache Preload Reset control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_pld_rst : HRO; bitpos: [5]; default: 0;
+         *  Configures reset preload-logic inside L2-Cache. Recommend that this should only be
+         *  used to initialize preload-logic when some fatal error of preload-logic occurs.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_pld_rst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_preload_rst_ctrl_reg_t;
+
+
+/** Group: Autoload buffer clear control and configuration registers */
+/** Type of l1_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_ald_buf_clr : R/W; bitpos: [0]; default: 0;
+         *  Configures clear autoload-buffer inside L1-ICache0. If this bit is active, autoload
+         *  will not work in L1-ICache0. This bit should not be active when autoload works in
+         *  L1-ICache0.
+         */
+        uint32_t l1_icache0_ald_buf_clr:1;
+        /** l1_icache1_ald_buf_clr : R/W; bitpos: [1]; default: 0;
+         *  Configures clear autoload-buffer inside L1-ICache1. If this bit is active, autoload
+         *  will not work in L1-ICache1. This bit should not be active when autoload works in
+         *  L1-ICache1.
+         */
+        uint32_t l1_icache1_ald_buf_clr:1;
+        /** l1_icache2_ald_buf_clr : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_ald_buf_clr:1;
+        /** l1_icache3_ald_buf_clr : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_ald_buf_clr:1;
+        /** l1_dcache_ald_buf_clr : R/W; bitpos: [4]; default: 0;
+         *  Configures clear autoload-buffer inside L1-DCache. If this bit is active, autoload
+         *  will not work in L1-DCache. This bit should not be active when autoload works in
+         *  L1-DCache.
+         */
+        uint32_t l1_dcache_ald_buf_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_cache_autoload_buf_clr_ctrl_reg_t;
+
+/** Type of l2_cache_autoload_buf_clr_ctrl register
+ *  Cache Autoload buffer clear control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_ald_buf_clr : HRO; bitpos: [5]; default: 0;
+         *  Configures clear autoload-buffer inside L2-Cache. If this bit is active, autoload
+         *  will not work in L2-Cache. This bit should not be active when autoload works in
+         *  L2-Cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_ald_buf_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_cache_autoload_buf_clr_ctrl_reg_t;
+
+
+/** Group: Unallocate request buffer clear registers */
+/** Type of l1_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        /** l1_icache0_unalloc_clr : R/W; bitpos: [0]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache0_unalloc_clr:1;
+        /** l1_icache1_unalloc_clr : R/W; bitpos: [1]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_icache1_unalloc_clr:1;
+        /** l1_icache2_unalloc_clr : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_unalloc_clr:1;
+        /** l1_icache3_unalloc_clr : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_unalloc_clr:1;
+        /** l1_dcache_unalloc_clr : R/W; bitpos: [4]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l1 dcache where the
+         *  unallocate request is responded but not completed.
+         */
+        uint32_t l1_dcache_unalloc_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cache_l1_unallocate_buffer_clear_reg_t;
+
+/** Type of l2_unallocate_buffer_clear register
+ *  Unallocate request buffer clear registers
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
+         *  The bit is used to clear the unallocate request buffer of l2 icache where the
+         *  unallocate request is responded but not completed.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_unalloc_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} cache_l2_unallocate_buffer_clear_reg_t;
+
+
+/** Group: Tag and Data Memory Access Control and configuration register */
+/** Type of l1_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        /** l1_icache0_tag_object : R/W; bitpos: [0]; default: 0;
+         *  Configures set L1-ICache0 tag memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_icache0_tag_object:1;
+        /** l1_icache1_tag_object : R/W; bitpos: [1]; default: 0;
+         *  Configures set L1-ICache1 tag memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_icache1_tag_object:1;
+        /** l1_icache2_tag_object : R/W; bitpos: [2]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_tag_object:1;
+        /** l1_icache3_tag_object : R/W; bitpos: [3]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_tag_object:1;
+        /** l1_dcache_tag_object : R/W; bitpos: [4]; default: 0;
+         *  Configures set L1-DCache tag memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_dcache_tag_object:1;
+        uint32_t reserved_5:1;
+        /** l1_icache0_mem_object : R/W; bitpos: [6]; default: 0;
+         *  Configures set L1-ICache0 data memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_icache0_mem_object:1;
+        /** l1_icache1_mem_object : R/W; bitpos: [7]; default: 0;
+         *  Configures set L1-ICache1 data memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_icache1_mem_object:1;
+        /** l1_icache2_mem_object : R/W; bitpos: [8]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache2_mem_object:1;
+        /** l1_icache3_mem_object : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l1_icache3_mem_object:1;
+        /** l1_dcache_mem_object : R/W; bitpos: [10]; default: 0;
+         *  Configures set L1-DCache data memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         */
+        uint32_t l1_dcache_mem_object:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} cache_l1_cache_object_ctrl_reg_t;
+
+/** Type of l1_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l1_cache_way_object : R/W; bitpos: [2:0]; default: 0;
+         *  Configures way of the tag-object will be accessed.
+         *  1: way1
+         */
+        uint32_t l1_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l1_cache_way_object_reg_t;
+
+/** Type of l1_cache_addr register
+ *  Cache address register
+ */
+typedef union {
+    struct {
+        /** l1_cache_addr : R/W; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the address which will decide where inside the specified tag
+         *  memory object will be accessed.
+         */
+        uint32_t l1_cache_addr:32;
+    };
+    uint32_t val;
+} cache_l1_cache_addr_reg_t;
+
+/** Type of l1_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l1_cache_debug_bus : R/W; bitpos: [31:0]; default: 620;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         */
+        uint32_t l1_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l1_cache_debug_bus_reg_t;
+
+/** Type of l2_cache_object_ctrl register
+ *  Cache Tag and Data memory Object control register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** l2_cache_tag_object : HRO; bitpos: [5]; default: 0;
+         *  Configures set L2-Cache tag memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_tag_object:1;
+        uint32_t reserved_6:5;
+        /** l2_cache_mem_object : HRO; bitpos: [11]; default: 0;
+         *  Configures set L2-Cache data memory as object. This bit should be onehot with the
+         *  others fields inside this register.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_mem_object:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} cache_l2_cache_object_ctrl_reg_t;
+
+/** Type of l2_cache_way_object register
+ *  Cache Tag and Data memory way register
+ */
+typedef union {
+    struct {
+        /** l2_cache_way_object : HRO; bitpos: [2:0]; default: 0;
+         *  Configures way of the tag-object will be accessed.
+         *  7: way7
+         *
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_way_object:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cache_l2_cache_way_object_reg_t;
+
+/** Type of l2_cache_addr register
+ *  Cache address register
+ */
+typedef union {
+    struct {
+        /** l2_cache_addr : HRO; bitpos: [31:0]; default: 1073741824;
+         *  Those bits stores the address which will decide where inside the specified tag
+         *  memory object will be accessed.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_addr:32;
+    };
+    uint32_t val;
+} cache_l2_cache_addr_reg_t;
+
+/** Type of l2_cache_debug_bus register
+ *  Cache Tag/data memory content register
+ */
+typedef union {
+    struct {
+        /** l2_cache_debug_bus : R/W; bitpos: [31:0]; default: 972;
+         *  This is a constant place where we can write data to or read data from the tag/data
+         *  memory on the specified cache.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_debug_bus:32;
+    };
+    uint32_t val;
+} cache_l2_cache_debug_bus_reg_t;
+
+
+/** Group: Split L1 and L2 registers */
+/** Type of level_split0 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split0 : HRO; bitpos: [31:0]; default: 624;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t level_split0:32;
+    };
+    uint32_t val;
+} cache_level_split0_reg_t;
+
+/** Type of level_split1 register
+ *  USED TO SPLIT L1 CACHE AND L2 CACHE
+ */
+typedef union {
+    struct {
+        /** level_split1 : HRO; bitpos: [31:0]; default: 976;
+         *  Reserved
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t level_split1:32;
+    };
+    uint32_t val;
+} cache_level_split1_reg_t;
+
+
+/** Group: L2 cache access attribute control register */
+/** Type of l2_cache_access_attr_ctrl register
+ *  L2 cache access attribute control register
+ */
+typedef union {
+    struct {
+        /** l2_cache_access_force_cc : HRO; bitpos: [0]; default: 1;
+         *  Configures force the request to l2 cache with cacheable attribute, otherwise, the
+         *  attribute is propagated from L1 cache or CPU, it could be one of cacheable and
+         *  non-cacheable.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_access_force_cc:1;
+        /** l2_cache_access_force_wb : HRO; bitpos: [1]; default: 1;
+         *  Configures force the request to l2 cache with write-back attribute, otherwise, the
+         *  attribute is propagated from L1 cache or CPU, it could be one of write-back and
+         *  write-through.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_access_force_wb:1;
+        /** l2_cache_access_force_wma : HRO; bitpos: [2]; default: 1;
+         *  Configures force the request to l2 cache with write-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  write-miss-allocate and write-miss-no-allocate.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_access_force_wma:1;
+        /** l2_cache_access_force_rma : HRO; bitpos: [3]; default: 1;
+         *  Configures force the request to l2 cache with read-miss-allocate attribute,
+         *  otherwise, the attribute is propagated from L1 cache or CPU, it could be one of
+         *  read-miss-allocate and read-miss-no-allocate.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_access_force_rma:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_l2_cache_access_attr_ctrl_reg_t;
+
+
+/** Group: Clock Gate Control and configuration register */
+/** Type of clock_gate register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures clock gate when access all registers in this module.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cache_clock_gate_reg_t;
+
+
+/** Group: Cache Trace Control register */
+/** Type of trace_ena register
+ *  Clock gate control register
+ */
+typedef union {
+    struct {
+        /** l1_cache_trace_ena : R/W; bitpos: [0]; default: 0;
+         *  Configures L1-Cache trace for the performance counter and fail tracer
+         */
+        uint32_t l1_cache_trace_ena:1;
+        /** l2_cache_trace_ena : HRO; bitpos: [1]; default: 0;
+         *  Configures L2-Cache trace for the performance counter and fail tracer
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t l2_cache_trace_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cache_trace_ena_reg_t;
+
+
+/** Group: Redundancy  register (Prepare for ECO) */
+/** Type of redundancy_sig0 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig0 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t redcy_sig0:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig0_reg_t;
+
+/** Type of redundancy_sig1 register
+ *  Cache redundancy signal 1 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig1 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t redcy_sig1:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig1_reg_t;
+
+/** Type of redundancy_sig2 register
+ *  Cache redundancy signal 2 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig2 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t redcy_sig2:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig2_reg_t;
+
+/** Type of redundancy_sig3 register
+ *  Cache redundancy signal 3 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig3 : R/W; bitpos: [31:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t redcy_sig3:32;
+    };
+    uint32_t val;
+} cache_redundancy_sig3_reg_t;
+
+/** Type of redundancy_sig4 register
+ *  Cache redundancy signal 0 register
+ */
+typedef union {
+    struct {
+        /** redcy_sig4 : RO; bitpos: [3:0]; default: 0;
+         *  Those bits are prepared for ECO.
+         *  This field is only for internal debugging purposes. Do not use it in applications.
+         */
+        uint32_t redcy_sig4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cache_redundancy_sig4_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38810384;
+         *  version control register. Note that this default value stored is the latest date
+         *  when the hardware logic was updated.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cache_date_reg_t;
+
+
+typedef struct {
+    volatile cache_l1_icache_ctrl_reg_t l1_icache_ctrl;
+    volatile cache_l1_dcache_ctrl_reg_t l1_dcache_ctrl;
+    volatile cache_l1_bypass_cache_conf_reg_t l1_bypass_cache_conf;
+    volatile cache_l1_cache_atomic_conf_reg_t l1_cache_atomic_conf;
+    volatile cache_l1_acache_cachesize_conf_reg_t l1_acache_cachesize_conf;
+    volatile cache_l1_acache_blocksize_conf_reg_t l1_acache_blocksize_conf;
+    volatile cache_l1_icache_cachesize_conf_reg_t l1_icache_cachesize_conf;
+    volatile cache_l1_icache_blocksize_conf_reg_t l1_icache_blocksize_conf;
+    volatile cache_l1_dcache_cachesize_conf_reg_t l1_dcache_cachesize_conf;
+    volatile cache_l1_dcache_blocksize_conf_reg_t l1_dcache_blocksize_conf;
+    volatile cache_l1_cache_wrap_around_ctrl_reg_t l1_cache_wrap_around_ctrl;
+    volatile cache_l1_cache_miss_access_ctrl_reg_t l1_cache_miss_access_ctrl;
+    volatile cache_l1_cache_freeze_ctrl_reg_t l1_cache_freeze_ctrl;
+    volatile cache_l1_cache_data_mem_acs_conf_reg_t l1_cache_data_mem_acs_conf;
+    volatile cache_l1_cache_tag_mem_acs_conf_reg_t l1_cache_tag_mem_acs_conf;
+    volatile cache_l1_icache0_prelock_conf_reg_t l1_icache0_prelock_conf;
+    volatile cache_l1_icache0_prelock_sct0_addr_reg_t l1_icache0_prelock_sct0_addr;
+    volatile cache_l1_icache0_prelock_sct1_addr_reg_t l1_icache0_prelock_sct1_addr;
+    volatile cache_l1_icache0_prelock_sct_size_reg_t l1_icache0_prelock_sct_size;
+    volatile cache_l1_icache1_prelock_conf_reg_t l1_icache1_prelock_conf;
+    volatile cache_l1_icache1_prelock_sct0_addr_reg_t l1_icache1_prelock_sct0_addr;
+    volatile cache_l1_icache1_prelock_sct1_addr_reg_t l1_icache1_prelock_sct1_addr;
+    volatile cache_l1_icache1_prelock_sct_size_reg_t l1_icache1_prelock_sct_size;
+    volatile cache_l1_icache2_prelock_conf_reg_t l1_icache2_prelock_conf;
+    volatile cache_l1_icache2_prelock_sct0_addr_reg_t l1_icache2_prelock_sct0_addr;
+    volatile cache_l1_icache2_prelock_sct1_addr_reg_t l1_icache2_prelock_sct1_addr;
+    volatile cache_l1_icache2_prelock_sct_size_reg_t l1_icache2_prelock_sct_size;
+    volatile cache_l1_icache3_prelock_conf_reg_t l1_icache3_prelock_conf;
+    volatile cache_l1_icache3_prelock_sct0_addr_reg_t l1_icache3_prelock_sct0_addr;
+    volatile cache_l1_icache3_prelock_sct1_addr_reg_t l1_icache3_prelock_sct1_addr;
+    volatile cache_l1_icache3_prelock_sct_size_reg_t l1_icache3_prelock_sct_size;
+    volatile cache_l1_dcache_prelock_conf_reg_t l1_dcache_prelock_conf;
+    volatile cache_l1_dcache_prelock_sct0_addr_reg_t l1_dcache_prelock_sct0_addr;
+    volatile cache_l1_dcache_prelock_sct1_addr_reg_t l1_dcache_prelock_sct1_addr;
+    volatile cache_l1_dcache_prelock_sct_size_reg_t l1_dcache_prelock_sct_size;
+    volatile cache_lock_ctrl_reg_t lock_ctrl;
+    volatile cache_lock_map_reg_t lock_map;
+    volatile cache_lock_addr_reg_t lock_addr;
+    volatile cache_lock_size_reg_t lock_size;
+    volatile cache_sync_ctrl_reg_t sync_ctrl;
+    volatile cache_sync_map_reg_t sync_map;
+    volatile cache_sync_addr_reg_t sync_addr;
+    volatile cache_sync_size_reg_t sync_size;
+    volatile cache_l1_icache0_preload_ctrl_reg_t l1_icache0_preload_ctrl;
+    volatile cache_l1_icache0_preload_addr_reg_t l1_icache0_preload_addr;
+    volatile cache_l1_icache0_preload_size_reg_t l1_icache0_preload_size;
+    volatile cache_l1_icache1_preload_ctrl_reg_t l1_icache1_preload_ctrl;
+    volatile cache_l1_icache1_preload_addr_reg_t l1_icache1_preload_addr;
+    volatile cache_l1_icache1_preload_size_reg_t l1_icache1_preload_size;
+    volatile cache_l1_icache2_preload_ctrl_reg_t l1_icache2_preload_ctrl;
+    volatile cache_l1_icache2_preload_addr_reg_t l1_icache2_preload_addr;
+    volatile cache_l1_icache2_preload_size_reg_t l1_icache2_preload_size;
+    volatile cache_l1_icache3_preload_ctrl_reg_t l1_icache3_preload_ctrl;
+    volatile cache_l1_icache3_preload_addr_reg_t l1_icache3_preload_addr;
+    volatile cache_l1_icache3_preload_size_reg_t l1_icache3_preload_size;
+    volatile cache_l1_dcache_preload_ctrl_reg_t l1_dcache_preload_ctrl;
+    volatile cache_l1_dcache_preload_addr_reg_t l1_dcache_preload_addr;
+    volatile cache_l1_dcache_preload_size_reg_t l1_dcache_preload_size;
+    volatile cache_l1_icache0_autoload_ctrl_reg_t l1_icache0_autoload_ctrl;
+    volatile cache_l1_icache0_autoload_sct0_addr_reg_t l1_icache0_autoload_sct0_addr;
+    volatile cache_l1_icache0_autoload_sct0_size_reg_t l1_icache0_autoload_sct0_size;
+    volatile cache_l1_icache0_autoload_sct1_addr_reg_t l1_icache0_autoload_sct1_addr;
+    volatile cache_l1_icache0_autoload_sct1_size_reg_t l1_icache0_autoload_sct1_size;
+    volatile cache_l1_icache1_autoload_ctrl_reg_t l1_icache1_autoload_ctrl;
+    volatile cache_l1_icache1_autoload_sct0_addr_reg_t l1_icache1_autoload_sct0_addr;
+    volatile cache_l1_icache1_autoload_sct0_size_reg_t l1_icache1_autoload_sct0_size;
+    volatile cache_l1_icache1_autoload_sct1_addr_reg_t l1_icache1_autoload_sct1_addr;
+    volatile cache_l1_icache1_autoload_sct1_size_reg_t l1_icache1_autoload_sct1_size;
+    volatile cache_l1_icache2_autoload_ctrl_reg_t l1_icache2_autoload_ctrl;
+    volatile cache_l1_icache2_autoload_sct0_addr_reg_t l1_icache2_autoload_sct0_addr;
+    volatile cache_l1_icache2_autoload_sct0_size_reg_t l1_icache2_autoload_sct0_size;
+    volatile cache_l1_icache2_autoload_sct1_addr_reg_t l1_icache2_autoload_sct1_addr;
+    volatile cache_l1_icache2_autoload_sct1_size_reg_t l1_icache2_autoload_sct1_size;
+    volatile cache_l1_icache3_autoload_ctrl_reg_t l1_icache3_autoload_ctrl;
+    volatile cache_l1_icache3_autoload_sct0_addr_reg_t l1_icache3_autoload_sct0_addr;
+    volatile cache_l1_icache3_autoload_sct0_size_reg_t l1_icache3_autoload_sct0_size;
+    volatile cache_l1_icache3_autoload_sct1_addr_reg_t l1_icache3_autoload_sct1_addr;
+    volatile cache_l1_icache3_autoload_sct1_size_reg_t l1_icache3_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_ctrl_reg_t l1_dcache_autoload_ctrl;
+    volatile cache_l1_dcache_autoload_sct0_addr_reg_t l1_dcache_autoload_sct0_addr;
+    volatile cache_l1_dcache_autoload_sct0_size_reg_t l1_dcache_autoload_sct0_size;
+    volatile cache_l1_dcache_autoload_sct1_addr_reg_t l1_dcache_autoload_sct1_addr;
+    volatile cache_l1_dcache_autoload_sct1_size_reg_t l1_dcache_autoload_sct1_size;
+    volatile cache_l1_dcache_autoload_sct2_addr_reg_t l1_dcache_autoload_sct2_addr;
+    volatile cache_l1_dcache_autoload_sct2_size_reg_t l1_dcache_autoload_sct2_size;
+    volatile cache_l1_dcache_autoload_sct3_addr_reg_t l1_dcache_autoload_sct3_addr;
+    volatile cache_l1_dcache_autoload_sct3_size_reg_t l1_dcache_autoload_sct3_size;
+    volatile cache_l1_cache_acs_cnt_int_ena_reg_t l1_cache_acs_cnt_int_ena;
+    volatile cache_l1_cache_acs_cnt_int_clr_reg_t l1_cache_acs_cnt_int_clr;
+    volatile cache_l1_cache_acs_cnt_int_raw_reg_t l1_cache_acs_cnt_int_raw;
+    volatile cache_l1_cache_acs_cnt_int_st_reg_t l1_cache_acs_cnt_int_st;
+    volatile cache_l1_cache_acs_fail_ctrl_reg_t l1_cache_acs_fail_ctrl;
+    volatile cache_l1_cache_acs_fail_int_ena_reg_t l1_cache_acs_fail_int_ena;
+    volatile cache_l1_cache_acs_fail_int_clr_reg_t l1_cache_acs_fail_int_clr;
+    volatile cache_l1_cache_acs_fail_int_raw_reg_t l1_cache_acs_fail_int_raw;
+    volatile cache_l1_cache_acs_fail_int_st_reg_t l1_cache_acs_fail_int_st;
+    volatile cache_l1_cache_acs_cnt_ctrl_reg_t l1_cache_acs_cnt_ctrl;
+    volatile cache_l1_ibus0_acs_hit_cnt_reg_t l1_ibus0_acs_hit_cnt;
+    volatile cache_l1_ibus0_acs_miss_cnt_reg_t l1_ibus0_acs_miss_cnt;
+    volatile cache_l1_ibus0_acs_conflict_cnt_reg_t l1_ibus0_acs_conflict_cnt;
+    volatile cache_l1_ibus0_acs_nxtlvl_rd_cnt_reg_t l1_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus1_acs_hit_cnt_reg_t l1_ibus1_acs_hit_cnt;
+    volatile cache_l1_ibus1_acs_miss_cnt_reg_t l1_ibus1_acs_miss_cnt;
+    volatile cache_l1_ibus1_acs_conflict_cnt_reg_t l1_ibus1_acs_conflict_cnt;
+    volatile cache_l1_ibus1_acs_nxtlvl_rd_cnt_reg_t l1_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus2_acs_hit_cnt_reg_t l1_ibus2_acs_hit_cnt;
+    volatile cache_l1_ibus2_acs_miss_cnt_reg_t l1_ibus2_acs_miss_cnt;
+    volatile cache_l1_ibus2_acs_conflict_cnt_reg_t l1_ibus2_acs_conflict_cnt;
+    volatile cache_l1_ibus2_acs_nxtlvl_rd_cnt_reg_t l1_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_ibus3_acs_hit_cnt_reg_t l1_ibus3_acs_hit_cnt;
+    volatile cache_l1_ibus3_acs_miss_cnt_reg_t l1_ibus3_acs_miss_cnt;
+    volatile cache_l1_ibus3_acs_conflict_cnt_reg_t l1_ibus3_acs_conflict_cnt;
+    volatile cache_l1_ibus3_acs_nxtlvl_rd_cnt_reg_t l1_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_hit_cnt_reg_t l1_dbus0_acs_hit_cnt;
+    volatile cache_l1_dbus0_acs_miss_cnt_reg_t l1_dbus0_acs_miss_cnt;
+    volatile cache_l1_dbus0_acs_conflict_cnt_reg_t l1_dbus0_acs_conflict_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_rd_cnt_reg_t l1_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus0_acs_nxtlvl_wr_cnt_reg_t l1_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus1_acs_hit_cnt_reg_t l1_dbus1_acs_hit_cnt;
+    volatile cache_l1_dbus1_acs_miss_cnt_reg_t l1_dbus1_acs_miss_cnt;
+    volatile cache_l1_dbus1_acs_conflict_cnt_reg_t l1_dbus1_acs_conflict_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_rd_cnt_reg_t l1_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus1_acs_nxtlvl_wr_cnt_reg_t l1_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus2_acs_hit_cnt_reg_t l1_dbus2_acs_hit_cnt;
+    volatile cache_l1_dbus2_acs_miss_cnt_reg_t l1_dbus2_acs_miss_cnt;
+    volatile cache_l1_dbus2_acs_conflict_cnt_reg_t l1_dbus2_acs_conflict_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_rd_cnt_reg_t l1_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus2_acs_nxtlvl_wr_cnt_reg_t l1_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_dbus3_acs_hit_cnt_reg_t l1_dbus3_acs_hit_cnt;
+    volatile cache_l1_dbus3_acs_miss_cnt_reg_t l1_dbus3_acs_miss_cnt;
+    volatile cache_l1_dbus3_acs_conflict_cnt_reg_t l1_dbus3_acs_conflict_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_rd_cnt_reg_t l1_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l1_dbus3_acs_nxtlvl_wr_cnt_reg_t l1_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l1_icache0_acs_fail_id_attr_reg_t l1_icache0_acs_fail_id_attr;
+    volatile cache_l1_icache0_acs_fail_addr_reg_t l1_icache0_acs_fail_addr;
+    volatile cache_l1_icache1_acs_fail_id_attr_reg_t l1_icache1_acs_fail_id_attr;
+    volatile cache_l1_icache1_acs_fail_addr_reg_t l1_icache1_acs_fail_addr;
+    volatile cache_l1_icache2_acs_fail_id_attr_reg_t l1_icache2_acs_fail_id_attr;
+    volatile cache_l1_icache2_acs_fail_addr_reg_t l1_icache2_acs_fail_addr;
+    volatile cache_l1_icache3_acs_fail_id_attr_reg_t l1_icache3_acs_fail_id_attr;
+    volatile cache_l1_icache3_acs_fail_addr_reg_t l1_icache3_acs_fail_addr;
+    volatile cache_l1_dcache_acs_fail_id_attr_reg_t l1_dcache_acs_fail_id_attr;
+    volatile cache_l1_dcache_acs_fail_addr_reg_t l1_dcache_acs_fail_addr;
+    volatile cache_l1_cache_sync_preload_int_ena_reg_t l1_cache_sync_preload_int_ena;
+    volatile cache_l1_cache_sync_preload_int_clr_reg_t l1_cache_sync_preload_int_clr;
+    volatile cache_l1_cache_sync_preload_int_raw_reg_t l1_cache_sync_preload_int_raw;
+    volatile cache_l1_cache_sync_preload_int_st_reg_t l1_cache_sync_preload_int_st;
+    volatile cache_l1_cache_sync_preload_exception_reg_t l1_cache_sync_preload_exception;
+    volatile cache_l1_cache_sync_rst_ctrl_reg_t l1_cache_sync_rst_ctrl;
+    volatile cache_l1_cache_preload_rst_ctrl_reg_t l1_cache_preload_rst_ctrl;
+    volatile cache_l1_cache_autoload_buf_clr_ctrl_reg_t l1_cache_autoload_buf_clr_ctrl;
+    volatile cache_l1_unallocate_buffer_clear_reg_t l1_unallocate_buffer_clear;
+    volatile cache_l1_cache_object_ctrl_reg_t l1_cache_object_ctrl;
+    volatile cache_l1_cache_way_object_reg_t l1_cache_way_object;
+    volatile cache_l1_cache_addr_reg_t l1_cache_addr;
+    volatile cache_l1_cache_debug_bus_reg_t l1_cache_debug_bus;
+    volatile cache_level_split0_reg_t level_split0;
+    volatile cache_l2_cache_ctrl_reg_t l2_cache_ctrl;
+    volatile cache_l2_bypass_cache_conf_reg_t l2_bypass_cache_conf;
+    volatile cache_l2_cache_cachesize_conf_reg_t l2_cache_cachesize_conf;
+    volatile cache_l2_cache_blocksize_conf_reg_t l2_cache_blocksize_conf;
+    volatile cache_l2_cache_wrap_around_ctrl_reg_t l2_cache_wrap_around_ctrl;
+    volatile cache_l2_cache_miss_access_ctrl_reg_t l2_cache_miss_access_ctrl;
+    volatile cache_l2_cache_freeze_ctrl_reg_t l2_cache_freeze_ctrl;
+    volatile cache_l2_cache_data_mem_acs_conf_reg_t l2_cache_data_mem_acs_conf;
+    volatile cache_l2_cache_tag_mem_acs_conf_reg_t l2_cache_tag_mem_acs_conf;
+    volatile cache_l2_cache_prelock_conf_reg_t l2_cache_prelock_conf;
+    volatile cache_l2_cache_prelock_sct0_addr_reg_t l2_cache_prelock_sct0_addr;
+    volatile cache_l2_cache_prelock_sct1_addr_reg_t l2_cache_prelock_sct1_addr;
+    volatile cache_l2_cache_prelock_sct_size_reg_t l2_cache_prelock_sct_size;
+    volatile cache_l2_cache_preload_ctrl_reg_t l2_cache_preload_ctrl;
+    volatile cache_l2_cache_preload_addr_reg_t l2_cache_preload_addr;
+    volatile cache_l2_cache_preload_size_reg_t l2_cache_preload_size;
+    volatile cache_l2_cache_autoload_ctrl_reg_t l2_cache_autoload_ctrl;
+    volatile cache_l2_cache_autoload_sct0_addr_reg_t l2_cache_autoload_sct0_addr;
+    volatile cache_l2_cache_autoload_sct0_size_reg_t l2_cache_autoload_sct0_size;
+    volatile cache_l2_cache_autoload_sct1_addr_reg_t l2_cache_autoload_sct1_addr;
+    volatile cache_l2_cache_autoload_sct1_size_reg_t l2_cache_autoload_sct1_size;
+    volatile cache_l2_cache_autoload_sct2_addr_reg_t l2_cache_autoload_sct2_addr;
+    volatile cache_l2_cache_autoload_sct2_size_reg_t l2_cache_autoload_sct2_size;
+    volatile cache_l2_cache_autoload_sct3_addr_reg_t l2_cache_autoload_sct3_addr;
+    volatile cache_l2_cache_autoload_sct3_size_reg_t l2_cache_autoload_sct3_size;
+    volatile cache_l2_cache_acs_cnt_int_ena_reg_t l2_cache_acs_cnt_int_ena;
+    volatile cache_l2_cache_acs_cnt_int_clr_reg_t l2_cache_acs_cnt_int_clr;
+    volatile cache_l2_cache_acs_cnt_int_raw_reg_t l2_cache_acs_cnt_int_raw;
+    volatile cache_l2_cache_acs_cnt_int_st_reg_t l2_cache_acs_cnt_int_st;
+    volatile cache_l2_cache_acs_fail_ctrl_reg_t l2_cache_acs_fail_ctrl;
+    volatile cache_l2_cache_acs_fail_int_ena_reg_t l2_cache_acs_fail_int_ena;
+    volatile cache_l2_cache_acs_fail_int_clr_reg_t l2_cache_acs_fail_int_clr;
+    volatile cache_l2_cache_acs_fail_int_raw_reg_t l2_cache_acs_fail_int_raw;
+    volatile cache_l2_cache_acs_fail_int_st_reg_t l2_cache_acs_fail_int_st;
+    volatile cache_l2_cache_acs_cnt_ctrl_reg_t l2_cache_acs_cnt_ctrl;
+    volatile cache_l2_ibus0_acs_hit_cnt_reg_t l2_ibus0_acs_hit_cnt;
+    volatile cache_l2_ibus0_acs_miss_cnt_reg_t l2_ibus0_acs_miss_cnt;
+    volatile cache_l2_ibus0_acs_conflict_cnt_reg_t l2_ibus0_acs_conflict_cnt;
+    volatile cache_l2_ibus0_acs_nxtlvl_rd_cnt_reg_t l2_ibus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus1_acs_hit_cnt_reg_t l2_ibus1_acs_hit_cnt;
+    volatile cache_l2_ibus1_acs_miss_cnt_reg_t l2_ibus1_acs_miss_cnt;
+    volatile cache_l2_ibus1_acs_conflict_cnt_reg_t l2_ibus1_acs_conflict_cnt;
+    volatile cache_l2_ibus1_acs_nxtlvl_rd_cnt_reg_t l2_ibus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus2_acs_hit_cnt_reg_t l2_ibus2_acs_hit_cnt;
+    volatile cache_l2_ibus2_acs_miss_cnt_reg_t l2_ibus2_acs_miss_cnt;
+    volatile cache_l2_ibus2_acs_conflict_cnt_reg_t l2_ibus2_acs_conflict_cnt;
+    volatile cache_l2_ibus2_acs_nxtlvl_rd_cnt_reg_t l2_ibus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_ibus3_acs_hit_cnt_reg_t l2_ibus3_acs_hit_cnt;
+    volatile cache_l2_ibus3_acs_miss_cnt_reg_t l2_ibus3_acs_miss_cnt;
+    volatile cache_l2_ibus3_acs_conflict_cnt_reg_t l2_ibus3_acs_conflict_cnt;
+    volatile cache_l2_ibus3_acs_nxtlvl_rd_cnt_reg_t l2_ibus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_hit_cnt_reg_t l2_dbus0_acs_hit_cnt;
+    volatile cache_l2_dbus0_acs_miss_cnt_reg_t l2_dbus0_acs_miss_cnt;
+    volatile cache_l2_dbus0_acs_conflict_cnt_reg_t l2_dbus0_acs_conflict_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_rd_cnt_reg_t l2_dbus0_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus0_acs_nxtlvl_wr_cnt_reg_t l2_dbus0_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus1_acs_hit_cnt_reg_t l2_dbus1_acs_hit_cnt;
+    volatile cache_l2_dbus1_acs_miss_cnt_reg_t l2_dbus1_acs_miss_cnt;
+    volatile cache_l2_dbus1_acs_conflict_cnt_reg_t l2_dbus1_acs_conflict_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_rd_cnt_reg_t l2_dbus1_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus1_acs_nxtlvl_wr_cnt_reg_t l2_dbus1_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus2_acs_hit_cnt_reg_t l2_dbus2_acs_hit_cnt;
+    volatile cache_l2_dbus2_acs_miss_cnt_reg_t l2_dbus2_acs_miss_cnt;
+    volatile cache_l2_dbus2_acs_conflict_cnt_reg_t l2_dbus2_acs_conflict_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_rd_cnt_reg_t l2_dbus2_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus2_acs_nxtlvl_wr_cnt_reg_t l2_dbus2_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_dbus3_acs_hit_cnt_reg_t l2_dbus3_acs_hit_cnt;
+    volatile cache_l2_dbus3_acs_miss_cnt_reg_t l2_dbus3_acs_miss_cnt;
+    volatile cache_l2_dbus3_acs_conflict_cnt_reg_t l2_dbus3_acs_conflict_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_rd_cnt_reg_t l2_dbus3_acs_nxtlvl_rd_cnt;
+    volatile cache_l2_dbus3_acs_nxtlvl_wr_cnt_reg_t l2_dbus3_acs_nxtlvl_wr_cnt;
+    volatile cache_l2_cache_acs_fail_id_attr_reg_t l2_cache_acs_fail_id_attr;
+    volatile cache_l2_cache_acs_fail_addr_reg_t l2_cache_acs_fail_addr;
+    volatile cache_l2_cache_sync_preload_int_ena_reg_t l2_cache_sync_preload_int_ena;
+    volatile cache_l2_cache_sync_preload_int_clr_reg_t l2_cache_sync_preload_int_clr;
+    volatile cache_l2_cache_sync_preload_int_raw_reg_t l2_cache_sync_preload_int_raw;
+    volatile cache_l2_cache_sync_preload_int_st_reg_t l2_cache_sync_preload_int_st;
+    volatile cache_l2_cache_sync_preload_exception_reg_t l2_cache_sync_preload_exception;
+    volatile cache_l2_cache_sync_rst_ctrl_reg_t l2_cache_sync_rst_ctrl;
+    volatile cache_l2_cache_preload_rst_ctrl_reg_t l2_cache_preload_rst_ctrl;
+    volatile cache_l2_cache_autoload_buf_clr_ctrl_reg_t l2_cache_autoload_buf_clr_ctrl;
+    volatile cache_l2_unallocate_buffer_clear_reg_t l2_unallocate_buffer_clear;
+    volatile cache_l2_cache_access_attr_ctrl_reg_t l2_cache_access_attr_ctrl;
+    volatile cache_l2_cache_object_ctrl_reg_t l2_cache_object_ctrl;
+    volatile cache_l2_cache_way_object_reg_t l2_cache_way_object;
+    volatile cache_l2_cache_addr_reg_t l2_cache_addr;
+    volatile cache_l2_cache_debug_bus_reg_t l2_cache_debug_bus;
+    volatile cache_level_split1_reg_t level_split1;
+    volatile cache_clock_gate_reg_t clock_gate;
+    volatile cache_trace_ena_reg_t trace_ena;
+    volatile cache_redundancy_sig0_reg_t redundancy_sig0;
+    volatile cache_redundancy_sig1_reg_t redundancy_sig1;
+    volatile cache_redundancy_sig2_reg_t redundancy_sig2;
+    volatile cache_redundancy_sig3_reg_t redundancy_sig3;
+    volatile cache_redundancy_sig4_reg_t redundancy_sig4;
+    uint32_t reserved_3f0[3];
+    volatile cache_date_reg_t date;
+} cache_dev_t;
+
+extern cache_dev_t CACHE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cache_dev_t) == 0x400, "Invalid size of cache_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cnnt_io_mux_reg.h b/components/soc/esp32s31/register/soc/cnnt_io_mux_reg.h
new file mode 100644
index 00000000000..3ab0aeebfa8
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cnnt_io_mux_reg.h
@@ -0,0 +1,1510 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CNNT_IO_MUX_GMAC_RMII_CLK_REG register
+ *  GMAC IO MUX configuration register for GMAC_RMII_CLK
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_REG (DR_REG_CNNT_IO_MUX_BASE + 0x0)
+/** CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_RMII_CLK.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL_M  (CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL_V << CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_RMII_CLK in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD_M  (CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD_V << CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_RMII_CLK during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU_M  (CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU_V << CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_RMII_CLK during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE_M  (CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE_V << CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_RMII_CLK during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV_M  (CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV_V << CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_RMII_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD_M  (CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD_V << CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_RMII_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU_M  (CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU_V << CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_RMII_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE_M  (CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE_V << CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_RMII_CLK.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV_M  (CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV_V << CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN_M  (CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN_V << CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_RMII_CLK.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL_M  (CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL_V << CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_RX_CLK_REG register
+ *  GMAC IO MUX configuration register for GMAC_RX_CLK
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_REG (DR_REG_CNNT_IO_MUX_BASE + 0x4)
+/** CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_RX_CLK.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL_M  (CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL_V << CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_RX_CLK in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD_M  (CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD_V << CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_RX_CLK during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU_M  (CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU_V << CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_RX_CLK during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE_M  (CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE_V << CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_RX_CLK during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV_M  (CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV_V << CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_RX_CLK_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_RX_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD_M  (CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD_V << CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_RX_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU_M  (CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU_V << CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_RX_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE_M  (CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE_V << CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_RX_CLK.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV_M  (CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV_V << CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_RX_CLK_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN_M  (CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN_V << CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_RX_CLK.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL_M  (CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL_V << CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_REG register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXDV
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_REG (DR_REG_CNNT_IO_MUX_BASE + 0x8)
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_PHY_RXDV.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXDV in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXDV during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_PHY_RXDV during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE_V << CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXDV during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXDV.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXDV.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_PHY_RXDV.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE_V << CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXDV.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN_V << CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_PHY_RXDV.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_REG register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD3
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_REG (DR_REG_CNNT_IO_MUX_BASE + 0xc)
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD3.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD3 in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD3 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_PHY_RXD3 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD3 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_PHY_RXD3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD3.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN_V << CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_PHY_RXD3.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_REG register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD2
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_REG (DR_REG_CNNT_IO_MUX_BASE + 0x10)
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD2.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD2 in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD2 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_PHY_RXD2 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD2 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_PHY_RXD2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD2.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN_V << CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_PHY_RXD2.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_REG register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD1
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_REG (DR_REG_CNNT_IO_MUX_BASE + 0x14)
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD1.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD1 in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD1 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_PHY_RXD1 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD1 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_PHY_RXD1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD1.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN_V << CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_PHY_RXD1.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_REG register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD0
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_REG (DR_REG_CNNT_IO_MUX_BASE + 0x18)
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD0.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_SLP_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD0 in sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPD_S  1
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD0 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_WPU_S  2
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of GMAC_PHY_RXD0 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_IE_S  3
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD0 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_MCU_DRV_S  4
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD_V << CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPD_S  6
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU_V << CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_WPU_S  7
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of GMAC_PHY_RXD0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE_V << CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_IE_S  8
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of GMAC_PHY_RXD0.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV_V << CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_FUN_DRV_S  9
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN_V << CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN_S  11
+/** CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  GMAC_PHY_RXD0.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN
+ */
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL_M  (CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL_V << CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL_S)
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_DATA0_REG register
+ *  SDIO IO MUX configuration register for SDIO_DATA0
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_REG (DR_REG_CNNT_IO_MUX_BASE + 0x1c)
+/** CNNT_IO_MUX_SDIO_DATA0_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_DATA0.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_DATA0_SLP_SEL_M  (CNNT_IO_MUX_SDIO_DATA0_SLP_SEL_V << CNNT_IO_MUX_SDIO_DATA0_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA0_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_DATA0_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_DATA0 in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPD_M  (CNNT_IO_MUX_SDIO_DATA0_MCU_WPD_V << CNNT_IO_MUX_SDIO_DATA0_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_DATA0_MCU_WPU : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable pull-up resistor of SDIO_DATA0 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPU_M  (CNNT_IO_MUX_SDIO_DATA0_MCU_WPU_V << CNNT_IO_MUX_SDIO_DATA0_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_DATA0_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_DATA0 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_IE_M  (CNNT_IO_MUX_SDIO_DATA0_MCU_IE_V << CNNT_IO_MUX_SDIO_DATA0_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_DATA0_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_DATA0 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_DRV_M  (CNNT_IO_MUX_SDIO_DATA0_MCU_DRV_V << CNNT_IO_MUX_SDIO_DATA0_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA0_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_DATA0_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_DATA0
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPD_M  (CNNT_IO_MUX_SDIO_DATA0_FUN_WPD_V << CNNT_IO_MUX_SDIO_DATA0_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_DATA0_FUN_WPU : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not enable pull-up resistor of SDIO_DATA0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPU_M  (CNNT_IO_MUX_SDIO_DATA0_FUN_WPU_V << CNNT_IO_MUX_SDIO_DATA0_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_DATA0_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_DATA0.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_IE_M  (CNNT_IO_MUX_SDIO_DATA0_FUN_IE_V << CNNT_IO_MUX_SDIO_DATA0_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_DATA0_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_DATA0.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_DRV_M  (CNNT_IO_MUX_SDIO_DATA0_FUN_DRV_V << CNNT_IO_MUX_SDIO_DATA0_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA0_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_DATA0_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_DATA0_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_EN_M  (CNNT_IO_MUX_SDIO_DATA0_HYS_EN_V << CNNT_IO_MUX_SDIO_DATA0_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_DATA0_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  SDIO_DATA0.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA0_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_SEL_M  (CNNT_IO_MUX_SDIO_DATA0_HYS_SEL_V << CNNT_IO_MUX_SDIO_DATA0_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA0_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_DATA1_REG register
+ *  SDIO IO MUX configuration register for SDIO_DATA1
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_REG (DR_REG_CNNT_IO_MUX_BASE + 0x20)
+/** CNNT_IO_MUX_SDIO_DATA1_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_DATA1.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_DATA1_SLP_SEL_M  (CNNT_IO_MUX_SDIO_DATA1_SLP_SEL_V << CNNT_IO_MUX_SDIO_DATA1_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA1_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_DATA1_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_DATA1 in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPD_M  (CNNT_IO_MUX_SDIO_DATA1_MCU_WPD_V << CNNT_IO_MUX_SDIO_DATA1_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_DATA1_MCU_WPU : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable pull-up resistor of SDIO_DATA1 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPU_M  (CNNT_IO_MUX_SDIO_DATA1_MCU_WPU_V << CNNT_IO_MUX_SDIO_DATA1_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_DATA1_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_DATA1 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_IE_M  (CNNT_IO_MUX_SDIO_DATA1_MCU_IE_V << CNNT_IO_MUX_SDIO_DATA1_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_DATA1_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_DATA1 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_DRV_M  (CNNT_IO_MUX_SDIO_DATA1_MCU_DRV_V << CNNT_IO_MUX_SDIO_DATA1_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA1_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_DATA1_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_DATA1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPD_M  (CNNT_IO_MUX_SDIO_DATA1_FUN_WPD_V << CNNT_IO_MUX_SDIO_DATA1_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_DATA1_FUN_WPU : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not enable pull-up resistor of SDIO_DATA1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPU_M  (CNNT_IO_MUX_SDIO_DATA1_FUN_WPU_V << CNNT_IO_MUX_SDIO_DATA1_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_DATA1_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_DATA1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_IE_M  (CNNT_IO_MUX_SDIO_DATA1_FUN_IE_V << CNNT_IO_MUX_SDIO_DATA1_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_DATA1_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_DATA1.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_DRV_M  (CNNT_IO_MUX_SDIO_DATA1_FUN_DRV_V << CNNT_IO_MUX_SDIO_DATA1_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA1_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_DATA1_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_DATA1_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_EN_M  (CNNT_IO_MUX_SDIO_DATA1_HYS_EN_V << CNNT_IO_MUX_SDIO_DATA1_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_DATA1_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  SDIO_DATA1.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA1_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_SEL_M  (CNNT_IO_MUX_SDIO_DATA1_HYS_SEL_V << CNNT_IO_MUX_SDIO_DATA1_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA1_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_DATA2_REG register
+ *  SDIO IO MUX configuration register for SDIO_DATA2
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_REG (DR_REG_CNNT_IO_MUX_BASE + 0x24)
+/** CNNT_IO_MUX_SDIO_DATA2_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_DATA2.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_DATA2_SLP_SEL_M  (CNNT_IO_MUX_SDIO_DATA2_SLP_SEL_V << CNNT_IO_MUX_SDIO_DATA2_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA2_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_DATA2_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_DATA2 in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPD_M  (CNNT_IO_MUX_SDIO_DATA2_MCU_WPD_V << CNNT_IO_MUX_SDIO_DATA2_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_DATA2_MCU_WPU : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable pull-up resistor of SDIO_DATA2 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPU_M  (CNNT_IO_MUX_SDIO_DATA2_MCU_WPU_V << CNNT_IO_MUX_SDIO_DATA2_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_DATA2_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_DATA2 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_IE_M  (CNNT_IO_MUX_SDIO_DATA2_MCU_IE_V << CNNT_IO_MUX_SDIO_DATA2_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_DATA2_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_DATA2 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_DRV_M  (CNNT_IO_MUX_SDIO_DATA2_MCU_DRV_V << CNNT_IO_MUX_SDIO_DATA2_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA2_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_DATA2_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_DATA2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPD_M  (CNNT_IO_MUX_SDIO_DATA2_FUN_WPD_V << CNNT_IO_MUX_SDIO_DATA2_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_DATA2_FUN_WPU : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not enable pull-up resistor of SDIO_DATA2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPU_M  (CNNT_IO_MUX_SDIO_DATA2_FUN_WPU_V << CNNT_IO_MUX_SDIO_DATA2_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_DATA2_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_DATA2.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_IE_M  (CNNT_IO_MUX_SDIO_DATA2_FUN_IE_V << CNNT_IO_MUX_SDIO_DATA2_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_DATA2_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_DATA2.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_DRV_M  (CNNT_IO_MUX_SDIO_DATA2_FUN_DRV_V << CNNT_IO_MUX_SDIO_DATA2_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA2_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_DATA2_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_DATA2_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_EN_M  (CNNT_IO_MUX_SDIO_DATA2_HYS_EN_V << CNNT_IO_MUX_SDIO_DATA2_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_DATA2_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  SDIO_DATA2.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA2_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_SEL_M  (CNNT_IO_MUX_SDIO_DATA2_HYS_SEL_V << CNNT_IO_MUX_SDIO_DATA2_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA2_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_DATA3_REG register
+ *  SDIO IO MUX configuration register for SDIO_DATA3
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_REG (DR_REG_CNNT_IO_MUX_BASE + 0x28)
+/** CNNT_IO_MUX_SDIO_DATA3_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_DATA3.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_DATA3_SLP_SEL_M  (CNNT_IO_MUX_SDIO_DATA3_SLP_SEL_V << CNNT_IO_MUX_SDIO_DATA3_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA3_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_DATA3_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_DATA3 in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPD_M  (CNNT_IO_MUX_SDIO_DATA3_MCU_WPD_V << CNNT_IO_MUX_SDIO_DATA3_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_DATA3_MCU_WPU : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable pull-up resistor of SDIO_DATA3 during sleep
+ *  mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPU_M  (CNNT_IO_MUX_SDIO_DATA3_MCU_WPU_V << CNNT_IO_MUX_SDIO_DATA3_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_DATA3_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_DATA3 during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_IE_M  (CNNT_IO_MUX_SDIO_DATA3_MCU_IE_V << CNNT_IO_MUX_SDIO_DATA3_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_DATA3_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_DATA3 during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_DRV_M  (CNNT_IO_MUX_SDIO_DATA3_MCU_DRV_V << CNNT_IO_MUX_SDIO_DATA3_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA3_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_DATA3_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_DATA3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPD_M  (CNNT_IO_MUX_SDIO_DATA3_FUN_WPD_V << CNNT_IO_MUX_SDIO_DATA3_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_DATA3_FUN_WPU : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not enable pull-up resistor of SDIO_DATA3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPU_M  (CNNT_IO_MUX_SDIO_DATA3_FUN_WPU_V << CNNT_IO_MUX_SDIO_DATA3_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_DATA3_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_DATA3.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_IE_M  (CNNT_IO_MUX_SDIO_DATA3_FUN_IE_V << CNNT_IO_MUX_SDIO_DATA3_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_DATA3_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_DATA3.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_DRV_M  (CNNT_IO_MUX_SDIO_DATA3_FUN_DRV_V << CNNT_IO_MUX_SDIO_DATA3_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_DATA3_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_DATA3_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_DATA3_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_EN_M  (CNNT_IO_MUX_SDIO_DATA3_HYS_EN_V << CNNT_IO_MUX_SDIO_DATA3_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_DATA3_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for
+ *  SDIO_DATA3.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA3_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_SEL_M  (CNNT_IO_MUX_SDIO_DATA3_HYS_SEL_V << CNNT_IO_MUX_SDIO_DATA3_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_DATA3_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_CLK_REG register
+ *  SDIO IO MUX configuration register for SDIO_CLK
+ */
+#define CNNT_IO_MUX_SDIO_CLK_REG (DR_REG_CNNT_IO_MUX_BASE + 0x2c)
+/** CNNT_IO_MUX_SDIO_CLK_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_CLK.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_CLK_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_CLK_SLP_SEL_M  (CNNT_IO_MUX_SDIO_CLK_SLP_SEL_V << CNNT_IO_MUX_SDIO_CLK_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_CLK_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_CLK_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_CLK in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPD_M  (CNNT_IO_MUX_SDIO_CLK_MCU_WPD_V << CNNT_IO_MUX_SDIO_CLK_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_CLK_MCU_WPU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether or not to enable pull-up resistor of SDIO_CLK during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPU_M  (CNNT_IO_MUX_SDIO_CLK_MCU_WPU_V << CNNT_IO_MUX_SDIO_CLK_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_CLK_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_CLK during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_CLK_MCU_IE_M  (CNNT_IO_MUX_SDIO_CLK_MCU_IE_V << CNNT_IO_MUX_SDIO_CLK_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_CLK_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_CLK_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_CLK during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_CLK_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_CLK_MCU_DRV_M  (CNNT_IO_MUX_SDIO_CLK_MCU_DRV_V << CNNT_IO_MUX_SDIO_CLK_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_CLK_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_CLK_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_CLK_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPD_M  (CNNT_IO_MUX_SDIO_CLK_FUN_WPD_V << CNNT_IO_MUX_SDIO_CLK_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_CLK_FUN_WPU : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not enable pull-up resistor of SDIO_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPU_M  (CNNT_IO_MUX_SDIO_CLK_FUN_WPU_V << CNNT_IO_MUX_SDIO_CLK_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_CLK_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_CLK.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_CLK_FUN_IE_M  (CNNT_IO_MUX_SDIO_CLK_FUN_IE_V << CNNT_IO_MUX_SDIO_CLK_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_CLK_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_CLK_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_CLK.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_CLK_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_CLK_FUN_DRV_M  (CNNT_IO_MUX_SDIO_CLK_FUN_DRV_V << CNNT_IO_MUX_SDIO_CLK_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_CLK_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_CLK_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_CLK_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_CLK_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CLK_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_CLK_HYS_EN_M  (CNNT_IO_MUX_SDIO_CLK_HYS_EN_V << CNNT_IO_MUX_SDIO_CLK_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_CLK_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_CLK_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for SDIO_CLK.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_CLK_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_CLK_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_CLK_HYS_SEL_M  (CNNT_IO_MUX_SDIO_CLK_HYS_SEL_V << CNNT_IO_MUX_SDIO_CLK_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_CLK_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CLK_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_SDIO_CMD_REG register
+ *  SDIO IO MUX configuration register for SDIO_CMD
+ */
+#define CNNT_IO_MUX_SDIO_CMD_REG (DR_REG_CNNT_IO_MUX_BASE + 0x30)
+/** CNNT_IO_MUX_SDIO_CMD_SLP_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enter sleep mode for SDIO_CMD.
+ *  0: Not enter
+ *  1: Enter
+ */
+#define CNNT_IO_MUX_SDIO_CMD_SLP_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_CMD_SLP_SEL_M  (CNNT_IO_MUX_SDIO_CMD_SLP_SEL_V << CNNT_IO_MUX_SDIO_CMD_SLP_SEL_S)
+#define CNNT_IO_MUX_SDIO_CMD_SLP_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_SLP_SEL_S  0
+/** CNNT_IO_MUX_SDIO_CMD_MCU_WPD : R/W; bitpos: [1]; default: 0;
+ *  Configure whether or not to enable pull-down resistor of SDIO_CMD in sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPD    (BIT(1))
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPD_M  (CNNT_IO_MUX_SDIO_CMD_MCU_WPD_V << CNNT_IO_MUX_SDIO_CMD_MCU_WPD_S)
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPD_S  1
+/** CNNT_IO_MUX_SDIO_CMD_MCU_WPU : R/W; bitpos: [2]; default: 1;
+ *  Configures whether or not to enable pull-up resistor of SDIO_CMD during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPU    (BIT(2))
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPU_M  (CNNT_IO_MUX_SDIO_CMD_MCU_WPU_V << CNNT_IO_MUX_SDIO_CMD_MCU_WPU_S)
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_MCU_WPU_S  2
+/** CNNT_IO_MUX_SDIO_CMD_MCU_IE : R/W; bitpos: [3]; default: 1;
+ *  Configures whether or not to enable the input of SDIO_CMD during sleep mode.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_MCU_IE    (BIT(3))
+#define CNNT_IO_MUX_SDIO_CMD_MCU_IE_M  (CNNT_IO_MUX_SDIO_CMD_MCU_IE_V << CNNT_IO_MUX_SDIO_CMD_MCU_IE_S)
+#define CNNT_IO_MUX_SDIO_CMD_MCU_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_MCU_IE_S  3
+/** CNNT_IO_MUX_SDIO_CMD_MCU_DRV : R/W; bitpos: [5:4]; default: 2;
+ *  Configures the drive strength of SDIO_CMD during sleep mode.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_CMD_MCU_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_CMD_MCU_DRV_M  (CNNT_IO_MUX_SDIO_CMD_MCU_DRV_V << CNNT_IO_MUX_SDIO_CMD_MCU_DRV_S)
+#define CNNT_IO_MUX_SDIO_CMD_MCU_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_CMD_MCU_DRV_S  4
+/** CNNT_IO_MUX_SDIO_CMD_FUN_WPD : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to enable pull-down resistor of SDIO_CMD.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPD    (BIT(6))
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPD_M  (CNNT_IO_MUX_SDIO_CMD_FUN_WPD_V << CNNT_IO_MUX_SDIO_CMD_FUN_WPD_S)
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPD_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPD_S  6
+/** CNNT_IO_MUX_SDIO_CMD_FUN_WPU : R/W; bitpos: [7]; default: 1;
+ *  Configures whether or not enable pull-up resistor of SDIO_CMD.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPU    (BIT(7))
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPU_M  (CNNT_IO_MUX_SDIO_CMD_FUN_WPU_V << CNNT_IO_MUX_SDIO_CMD_FUN_WPU_S)
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPU_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_FUN_WPU_S  7
+/** CNNT_IO_MUX_SDIO_CMD_FUN_IE : R/W; bitpos: [8]; default: 1;
+ *  Configures whether or not to enable input of SDIO_CMD.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_FUN_IE    (BIT(8))
+#define CNNT_IO_MUX_SDIO_CMD_FUN_IE_M  (CNNT_IO_MUX_SDIO_CMD_FUN_IE_V << CNNT_IO_MUX_SDIO_CMD_FUN_IE_S)
+#define CNNT_IO_MUX_SDIO_CMD_FUN_IE_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_FUN_IE_S  8
+/** CNNT_IO_MUX_SDIO_CMD_FUN_DRV : R/W; bitpos: [10:9]; default: 2;
+ *  Configures the drive strength of SDIO_CMD.
+ *  0: ~5 mA
+ *  1: ~10 mA
+ *  2: ~20 mA
+ *  3: ~40 mA
+ */
+#define CNNT_IO_MUX_SDIO_CMD_FUN_DRV    0x00000003U
+#define CNNT_IO_MUX_SDIO_CMD_FUN_DRV_M  (CNNT_IO_MUX_SDIO_CMD_FUN_DRV_V << CNNT_IO_MUX_SDIO_CMD_FUN_DRV_S)
+#define CNNT_IO_MUX_SDIO_CMD_FUN_DRV_V  0x00000003U
+#define CNNT_IO_MUX_SDIO_CMD_FUN_DRV_S  9
+/** CNNT_IO_MUX_SDIO_CMD_HYS_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable the hysteresis function of the pin when
+ *  CNNT_IO_MUX_SDIO_CMD_HYS_SEL is set to 1.
+ *  0: Disable
+ *  1: Enable
+ */
+#define CNNT_IO_MUX_SDIO_CMD_HYS_EN    (BIT(11))
+#define CNNT_IO_MUX_SDIO_CMD_HYS_EN_M  (CNNT_IO_MUX_SDIO_CMD_HYS_EN_V << CNNT_IO_MUX_SDIO_CMD_HYS_EN_S)
+#define CNNT_IO_MUX_SDIO_CMD_HYS_EN_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_HYS_EN_S  11
+/** CNNT_IO_MUX_SDIO_CMD_HYS_SEL : R/W; bitpos: [12]; default: 0;
+ *  Configures to choose the signal for enabling the hysteresis function for SDIO_CMD.
+ *  0: Choose the output enable signal of eFuse
+ *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_CMD_HYS_EN
+ */
+#define CNNT_IO_MUX_SDIO_CMD_HYS_SEL    (BIT(12))
+#define CNNT_IO_MUX_SDIO_CMD_HYS_SEL_M  (CNNT_IO_MUX_SDIO_CMD_HYS_SEL_V << CNNT_IO_MUX_SDIO_CMD_HYS_SEL_S)
+#define CNNT_IO_MUX_SDIO_CMD_HYS_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_CMD_HYS_SEL_S  12
+
+/** CNNT_IO_MUX_CTRL_REG register
+ *  SDIO IO MUX configuration register for ctrl sel
+ */
+#define CNNT_IO_MUX_CTRL_REG (DR_REG_CNNT_IO_MUX_BASE + 0x3f4)
+/** CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to use dedicated ctrl signals for SDIO PAD.
+ *  0: Not use dedicated ctrl signals
+ *  1: Use dedicated ctrl signals
+ */
+#define CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL    (BIT(0))
+#define CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL_M  (CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL_V << CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL_S)
+#define CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL_V  0x00000001U
+#define CNNT_IO_MUX_SDIO_PAD_PIN_CTRL_DED_SEL_S  0
+/** CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL : R/W; bitpos: [1]; default: 0;
+ *  Configures whether or not to use dedicated ctrl signals for GMAC PAD.
+ *  0: Not use dedicated ctrl signals
+ *  1: Use dedicated ctrl signals
+ */
+#define CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL    (BIT(1))
+#define CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL_M  (CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL_V << CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL_S)
+#define CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL_V  0x00000001U
+#define CNNT_IO_MUX_GMAC_PAD_PIN_CTRL_DED_SEL_S  1
+
+/** CNNT_IO_MUX_CLOCK_GATE_REG register
+ *  CNNT_IO_MUX clock gate register
+ */
+#define CNNT_IO_MUX_CLOCK_GATE_REG (DR_REG_CNNT_IO_MUX_BASE + 0x3f8)
+/** CNNT_IO_MUX_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable clock gate.
+ *  0: Not enable
+ *  1: Enable, the clock is free running.
+ */
+#define CNNT_IO_MUX_CLK_EN    (BIT(0))
+#define CNNT_IO_MUX_CLK_EN_M  (CNNT_IO_MUX_CLK_EN_V << CNNT_IO_MUX_CLK_EN_S)
+#define CNNT_IO_MUX_CLK_EN_V  0x00000001U
+#define CNNT_IO_MUX_CLK_EN_S  0
+
+/** CNNT_IO_MUX_DATE_REG register
+ *  Version control register
+ */
+#define CNNT_IO_MUX_DATE_REG (DR_REG_CNNT_IO_MUX_BASE + 0x3fc)
+/** CNNT_IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 38834464;
+ *  Version control register
+ */
+#define CNNT_IO_MUX_REG_DATE    0x0FFFFFFFU
+#define CNNT_IO_MUX_REG_DATE_M  (CNNT_IO_MUX_REG_DATE_V << CNNT_IO_MUX_REG_DATE_S)
+#define CNNT_IO_MUX_REG_DATE_V  0x0FFFFFFFU
+#define CNNT_IO_MUX_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cnnt_io_mux_struct.h b/components/soc/esp32s31/register/soc/cnnt_io_mux_struct.h
new file mode 100644
index 00000000000..d41608a571f
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cnnt_io_mux_struct.h
@@ -0,0 +1,1179 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of gmac_rmii_clk register
+ *  GMAC IO MUX configuration register for GMAC_RMII_CLK
+ */
+typedef union {
+    struct {
+        /** gmac_rmii_clk_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_RMII_CLK.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_rmii_clk_slp_sel:1;
+        /** gmac_rmii_clk_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_RMII_CLK in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_mcu_wpd:1;
+        /** gmac_rmii_clk_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_RMII_CLK during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_mcu_wpu:1;
+        /** gmac_rmii_clk_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_RMII_CLK during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_mcu_ie:1;
+        /** gmac_rmii_clk_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_RMII_CLK during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_rmii_clk_mcu_drv:2;
+        /** gmac_rmii_clk_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_RMII_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_fun_wpd:1;
+        /** gmac_rmii_clk_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_RMII_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_fun_wpu:1;
+        /** gmac_rmii_clk_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_RMII_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_fun_ie:1;
+        /** gmac_rmii_clk_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_RMII_CLK.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_rmii_clk_fun_drv:2;
+        /** gmac_rmii_clk_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_RMII_CLK_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rmii_clk_hys_en:1;
+        /** gmac_rmii_clk_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_RMII_CLK.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_RMII_CLK_HYS_EN
+         */
+        uint32_t gmac_rmii_clk_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_rmii_clk_reg_t;
+
+/** Type of gmac_rx_clk register
+ *  GMAC IO MUX configuration register for GMAC_RX_CLK
+ */
+typedef union {
+    struct {
+        /** gmac_rx_clk_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_RX_CLK.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_rx_clk_slp_sel:1;
+        /** gmac_rx_clk_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_RX_CLK in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_mcu_wpd:1;
+        /** gmac_rx_clk_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_RX_CLK during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_mcu_wpu:1;
+        /** gmac_rx_clk_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_RX_CLK during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_mcu_ie:1;
+        /** gmac_rx_clk_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_RX_CLK during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_rx_clk_mcu_drv:2;
+        /** gmac_rx_clk_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_RX_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_fun_wpd:1;
+        /** gmac_rx_clk_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_RX_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_fun_wpu:1;
+        /** gmac_rx_clk_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_RX_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_fun_ie:1;
+        /** gmac_rx_clk_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_RX_CLK.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_rx_clk_fun_drv:2;
+        /** gmac_rx_clk_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_RX_CLK_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_rx_clk_hys_en:1;
+        /** gmac_rx_clk_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_RX_CLK.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_RX_CLK_HYS_EN
+         */
+        uint32_t gmac_rx_clk_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_rx_clk_reg_t;
+
+/** Type of gmac_phy_rxdv register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXDV
+ */
+typedef union {
+    struct {
+        /** gmac_phy_rxdv_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_PHY_RXDV.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_phy_rxdv_slp_sel:1;
+        /** gmac_phy_rxdv_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXDV in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_mcu_wpd:1;
+        /** gmac_phy_rxdv_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXDV during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_mcu_wpu:1;
+        /** gmac_phy_rxdv_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_PHY_RXDV during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_mcu_ie:1;
+        /** gmac_phy_rxdv_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXDV during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxdv_mcu_drv:2;
+        /** gmac_phy_rxdv_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXDV.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_fun_wpd:1;
+        /** gmac_phy_rxdv_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXDV.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_fun_wpu:1;
+        /** gmac_phy_rxdv_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_PHY_RXDV.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_fun_ie:1;
+        /** gmac_phy_rxdv_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXDV.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxdv_fun_drv:2;
+        /** gmac_phy_rxdv_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxdv_hys_en:1;
+        /** gmac_phy_rxdv_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_PHY_RXDV.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXDV_HYS_EN
+         */
+        uint32_t gmac_phy_rxdv_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_phy_rxdv_reg_t;
+
+/** Type of gmac_phy_rxd3 register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD3
+ */
+typedef union {
+    struct {
+        /** gmac_phy_rxd3_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD3.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_phy_rxd3_slp_sel:1;
+        /** gmac_phy_rxd3_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD3 in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_mcu_wpd:1;
+        /** gmac_phy_rxd3_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD3 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_mcu_wpu:1;
+        /** gmac_phy_rxd3_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_PHY_RXD3 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_mcu_ie:1;
+        /** gmac_phy_rxd3_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD3 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd3_mcu_drv:2;
+        /** gmac_phy_rxd3_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_fun_wpd:1;
+        /** gmac_phy_rxd3_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_fun_wpu:1;
+        /** gmac_phy_rxd3_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_PHY_RXD3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_fun_ie:1;
+        /** gmac_phy_rxd3_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD3.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd3_fun_drv:2;
+        /** gmac_phy_rxd3_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd3_hys_en:1;
+        /** gmac_phy_rxd3_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_PHY_RXD3.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD3_HYS_EN
+         */
+        uint32_t gmac_phy_rxd3_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_phy_rxd3_reg_t;
+
+/** Type of gmac_phy_rxd2 register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD2
+ */
+typedef union {
+    struct {
+        /** gmac_phy_rxd2_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD2.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_phy_rxd2_slp_sel:1;
+        /** gmac_phy_rxd2_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD2 in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_mcu_wpd:1;
+        /** gmac_phy_rxd2_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD2 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_mcu_wpu:1;
+        /** gmac_phy_rxd2_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_PHY_RXD2 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_mcu_ie:1;
+        /** gmac_phy_rxd2_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD2 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd2_mcu_drv:2;
+        /** gmac_phy_rxd2_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_fun_wpd:1;
+        /** gmac_phy_rxd2_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_fun_wpu:1;
+        /** gmac_phy_rxd2_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_PHY_RXD2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_fun_ie:1;
+        /** gmac_phy_rxd2_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD2.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd2_fun_drv:2;
+        /** gmac_phy_rxd2_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd2_hys_en:1;
+        /** gmac_phy_rxd2_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_PHY_RXD2.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD2_HYS_EN
+         */
+        uint32_t gmac_phy_rxd2_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_phy_rxd2_reg_t;
+
+/** Type of gmac_phy_rxd1 register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD1
+ */
+typedef union {
+    struct {
+        /** gmac_phy_rxd1_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD1.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_phy_rxd1_slp_sel:1;
+        /** gmac_phy_rxd1_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD1 in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_mcu_wpd:1;
+        /** gmac_phy_rxd1_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD1 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_mcu_wpu:1;
+        /** gmac_phy_rxd1_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_PHY_RXD1 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_mcu_ie:1;
+        /** gmac_phy_rxd1_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD1 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd1_mcu_drv:2;
+        /** gmac_phy_rxd1_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_fun_wpd:1;
+        /** gmac_phy_rxd1_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_fun_wpu:1;
+        /** gmac_phy_rxd1_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_PHY_RXD1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_fun_ie:1;
+        /** gmac_phy_rxd1_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD1.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd1_fun_drv:2;
+        /** gmac_phy_rxd1_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd1_hys_en:1;
+        /** gmac_phy_rxd1_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_PHY_RXD1.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD1_HYS_EN
+         */
+        uint32_t gmac_phy_rxd1_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_phy_rxd1_reg_t;
+
+/** Type of gmac_phy_rxd0 register
+ *  GMAC IO MUX configuration register for GMAC_PHY_RXD0
+ */
+typedef union {
+    struct {
+        /** gmac_phy_rxd0_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for GMAC_PHY_RXD0.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gmac_phy_rxd0_slp_sel:1;
+        /** gmac_phy_rxd0_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GMAC_PHY_RXD0 in sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_mcu_wpd:1;
+        /** gmac_phy_rxd0_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GMAC_PHY_RXD0 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_mcu_wpu:1;
+        /** gmac_phy_rxd0_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of GMAC_PHY_RXD0 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_mcu_ie:1;
+        /** gmac_phy_rxd0_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD0 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd0_mcu_drv:2;
+        /** gmac_phy_rxd0_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GMAC_PHY_RXD0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_fun_wpd:1;
+        /** gmac_phy_rxd0_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GMAC_PHY_RXD0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_fun_wpu:1;
+        /** gmac_phy_rxd0_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of GMAC_PHY_RXD0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_fun_ie:1;
+        /** gmac_phy_rxd0_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of GMAC_PHY_RXD0.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gmac_phy_rxd0_fun_drv:2;
+        /** gmac_phy_rxd0_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gmac_phy_rxd0_hys_en:1;
+        /** gmac_phy_rxd0_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  GMAC_PHY_RXD0.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_GMAC_PHY_RXD0_HYS_EN
+         */
+        uint32_t gmac_phy_rxd0_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_gmac_phy_rxd0_reg_t;
+
+/** Type of sdio_data0 register
+ *  SDIO IO MUX configuration register for SDIO_DATA0
+ */
+typedef union {
+    struct {
+        /** sdio_data0_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_DATA0.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_data0_slp_sel:1;
+        /** sdio_data0_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_DATA0 in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_mcu_wpd:1;
+        /** sdio_data0_mcu_wpu : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable pull-up resistor of SDIO_DATA0 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_mcu_wpu:1;
+        /** sdio_data0_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_DATA0 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_mcu_ie:1;
+        /** sdio_data0_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_DATA0 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data0_mcu_drv:2;
+        /** sdio_data0_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_DATA0
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_fun_wpd:1;
+        /** sdio_data0_fun_wpu : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not enable pull-up resistor of SDIO_DATA0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_fun_wpu:1;
+        /** sdio_data0_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_DATA0.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_fun_ie:1;
+        /** sdio_data0_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_DATA0.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data0_fun_drv:2;
+        /** sdio_data0_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_DATA0_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data0_hys_en:1;
+        /** sdio_data0_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  SDIO_DATA0.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA0_HYS_EN
+         */
+        uint32_t sdio_data0_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_data0_reg_t;
+
+/** Type of sdio_data1 register
+ *  SDIO IO MUX configuration register for SDIO_DATA1
+ */
+typedef union {
+    struct {
+        /** sdio_data1_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_DATA1.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_data1_slp_sel:1;
+        /** sdio_data1_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_DATA1 in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_mcu_wpd:1;
+        /** sdio_data1_mcu_wpu : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable pull-up resistor of SDIO_DATA1 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_mcu_wpu:1;
+        /** sdio_data1_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_DATA1 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_mcu_ie:1;
+        /** sdio_data1_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_DATA1 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data1_mcu_drv:2;
+        /** sdio_data1_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_DATA1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_fun_wpd:1;
+        /** sdio_data1_fun_wpu : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not enable pull-up resistor of SDIO_DATA1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_fun_wpu:1;
+        /** sdio_data1_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_DATA1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_fun_ie:1;
+        /** sdio_data1_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_DATA1.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data1_fun_drv:2;
+        /** sdio_data1_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_DATA1_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data1_hys_en:1;
+        /** sdio_data1_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  SDIO_DATA1.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA1_HYS_EN
+         */
+        uint32_t sdio_data1_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_data1_reg_t;
+
+/** Type of sdio_data2 register
+ *  SDIO IO MUX configuration register for SDIO_DATA2
+ */
+typedef union {
+    struct {
+        /** sdio_data2_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_DATA2.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_data2_slp_sel:1;
+        /** sdio_data2_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_DATA2 in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_mcu_wpd:1;
+        /** sdio_data2_mcu_wpu : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable pull-up resistor of SDIO_DATA2 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_mcu_wpu:1;
+        /** sdio_data2_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_DATA2 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_mcu_ie:1;
+        /** sdio_data2_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_DATA2 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data2_mcu_drv:2;
+        /** sdio_data2_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_DATA2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_fun_wpd:1;
+        /** sdio_data2_fun_wpu : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not enable pull-up resistor of SDIO_DATA2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_fun_wpu:1;
+        /** sdio_data2_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_DATA2.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_fun_ie:1;
+        /** sdio_data2_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_DATA2.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data2_fun_drv:2;
+        /** sdio_data2_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_DATA2_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data2_hys_en:1;
+        /** sdio_data2_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  SDIO_DATA2.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA2_HYS_EN
+         */
+        uint32_t sdio_data2_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_data2_reg_t;
+
+/** Type of sdio_data3 register
+ *  SDIO IO MUX configuration register for SDIO_DATA3
+ */
+typedef union {
+    struct {
+        /** sdio_data3_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_DATA3.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_data3_slp_sel:1;
+        /** sdio_data3_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_DATA3 in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_mcu_wpd:1;
+        /** sdio_data3_mcu_wpu : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable pull-up resistor of SDIO_DATA3 during sleep
+         *  mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_mcu_wpu:1;
+        /** sdio_data3_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_DATA3 during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_mcu_ie:1;
+        /** sdio_data3_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_DATA3 during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data3_mcu_drv:2;
+        /** sdio_data3_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_DATA3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_fun_wpd:1;
+        /** sdio_data3_fun_wpu : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not enable pull-up resistor of SDIO_DATA3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_fun_wpu:1;
+        /** sdio_data3_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_DATA3.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_fun_ie:1;
+        /** sdio_data3_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_DATA3.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_data3_fun_drv:2;
+        /** sdio_data3_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_DATA3_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_data3_hys_en:1;
+        /** sdio_data3_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for
+         *  SDIO_DATA3.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_DATA3_HYS_EN
+         */
+        uint32_t sdio_data3_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_data3_reg_t;
+
+/** Type of sdio_clk register
+ *  SDIO IO MUX configuration register for SDIO_CLK
+ */
+typedef union {
+    struct {
+        /** sdio_clk_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_CLK.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_clk_slp_sel:1;
+        /** sdio_clk_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_CLK in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_mcu_wpd:1;
+        /** sdio_clk_mcu_wpu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of SDIO_CLK during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_mcu_wpu:1;
+        /** sdio_clk_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_CLK during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_mcu_ie:1;
+        /** sdio_clk_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_CLK during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_clk_mcu_drv:2;
+        /** sdio_clk_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_fun_wpd:1;
+        /** sdio_clk_fun_wpu : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not enable pull-up resistor of SDIO_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_fun_wpu:1;
+        /** sdio_clk_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_CLK.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_fun_ie:1;
+        /** sdio_clk_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_CLK.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_clk_fun_drv:2;
+        /** sdio_clk_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_CLK_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_clk_hys_en:1;
+        /** sdio_clk_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for SDIO_CLK.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_CLK_HYS_EN
+         */
+        uint32_t sdio_clk_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_clk_reg_t;
+
+/** Type of sdio_cmd register
+ *  SDIO IO MUX configuration register for SDIO_CMD
+ */
+typedef union {
+    struct {
+        /** sdio_cmd_slp_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enter sleep mode for SDIO_CMD.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t sdio_cmd_slp_sel:1;
+        /** sdio_cmd_mcu_wpd : R/W; bitpos: [1]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of SDIO_CMD in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_mcu_wpd:1;
+        /** sdio_cmd_mcu_wpu : R/W; bitpos: [2]; default: 1;
+         *  Configures whether or not to enable pull-up resistor of SDIO_CMD during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_mcu_wpu:1;
+        /** sdio_cmd_mcu_ie : R/W; bitpos: [3]; default: 1;
+         *  Configures whether or not to enable the input of SDIO_CMD during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_mcu_ie:1;
+        /** sdio_cmd_mcu_drv : R/W; bitpos: [5:4]; default: 2;
+         *  Configures the drive strength of SDIO_CMD during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_cmd_mcu_drv:2;
+        /** sdio_cmd_fun_wpd : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of SDIO_CMD.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_fun_wpd:1;
+        /** sdio_cmd_fun_wpu : R/W; bitpos: [7]; default: 1;
+         *  Configures whether or not enable pull-up resistor of SDIO_CMD.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_fun_wpu:1;
+        /** sdio_cmd_fun_ie : R/W; bitpos: [8]; default: 1;
+         *  Configures whether or not to enable input of SDIO_CMD.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_fun_ie:1;
+        /** sdio_cmd_fun_drv : R/W; bitpos: [10:9]; default: 2;
+         *  Configures the drive strength of SDIO_CMD.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t sdio_cmd_fun_drv:2;
+        /** sdio_cmd_hys_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  CNNT_IO_MUX_SDIO_CMD_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sdio_cmd_hys_en:1;
+        /** sdio_cmd_hys_sel : R/W; bitpos: [12]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for SDIO_CMD.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of CNNT_IO_MUX_SDIO_CMD_HYS_EN
+         */
+        uint32_t sdio_cmd_hys_sel:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_io_mux_sdio_cmd_reg_t;
+
+/** Type of ctrl register
+ *  SDIO IO MUX configuration register for ctrl sel
+ */
+typedef union {
+    struct {
+        /** sdio_pad_pin_ctrl_ded_sel : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to use dedicated ctrl signals for SDIO PAD.
+         *  0: Not use dedicated ctrl signals
+         *  1: Use dedicated ctrl signals
+         */
+        uint32_t sdio_pad_pin_ctrl_ded_sel:1;
+        /** gmac_pad_pin_ctrl_ded_sel : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to use dedicated ctrl signals for GMAC PAD.
+         *  0: Not use dedicated ctrl signals
+         *  1: Use dedicated ctrl signals
+         */
+        uint32_t gmac_pad_pin_ctrl_ded_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cnnt_io_mux_ctrl_reg_t;
+
+
+/** Group: Clock Gate Register */
+/** Type of clock_gate register
+ *  CNNT_IO_MUX clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable clock gate.
+         *  0: Not enable
+         *  1: Enable, the clock is free running.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cnnt_io_mux_clock_gate_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 38834464;
+         *  Version control register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cnnt_io_mux_date_reg_t;
+
+
+typedef struct {
+    volatile cnnt_io_mux_gmac_rmii_clk_reg_t gmac_rmii_clk;
+    volatile cnnt_io_mux_gmac_rx_clk_reg_t gmac_rx_clk;
+    volatile cnnt_io_mux_gmac_phy_rxdv_reg_t gmac_phy_rxdv;
+    volatile cnnt_io_mux_gmac_phy_rxd3_reg_t gmac_phy_rxd3;
+    volatile cnnt_io_mux_gmac_phy_rxd2_reg_t gmac_phy_rxd2;
+    volatile cnnt_io_mux_gmac_phy_rxd1_reg_t gmac_phy_rxd1;
+    volatile cnnt_io_mux_gmac_phy_rxd0_reg_t gmac_phy_rxd0;
+    volatile cnnt_io_mux_sdio_data0_reg_t sdio_data0;
+    volatile cnnt_io_mux_sdio_data1_reg_t sdio_data1;
+    volatile cnnt_io_mux_sdio_data2_reg_t sdio_data2;
+    volatile cnnt_io_mux_sdio_data3_reg_t sdio_data3;
+    volatile cnnt_io_mux_sdio_clk_reg_t sdio_clk;
+    volatile cnnt_io_mux_sdio_cmd_reg_t sdio_cmd;
+    uint32_t reserved_034[240];
+    volatile cnnt_io_mux_ctrl_reg_t ctrl;
+    volatile cnnt_io_mux_clock_gate_reg_t clock_gate;
+    volatile cnnt_io_mux_date_reg_t date;
+} cnnt_io_mux_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cnnt_io_mux_dev_t) == 0x400, "Invalid size of cnnt_io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cnnt_sys_reg.h b/components/soc/esp32s31/register/soc/cnnt_sys_reg.h
new file mode 100644
index 00000000000..17610bd1f6b
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cnnt_sys_reg.h
@@ -0,0 +1,667 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CNNT_SYS_VER_DATE_REG register
+ *  NA
+ */
+#define CNNT_SYS_VER_DATE_REG (DR_REG_CNNT_BASE + 0x0)
+/** CNNT_SYS_VER_DATE : R/W; bitpos: [31:0]; default: 539298086;
+ *  NA
+ */
+#define CNNT_SYS_VER_DATE    0xFFFFFFFFU
+#define CNNT_SYS_VER_DATE_M  (CNNT_SYS_VER_DATE_V << CNNT_SYS_VER_DATE_S)
+#define CNNT_SYS_VER_DATE_V  0xFFFFFFFFU
+#define CNNT_SYS_VER_DATE_S  0
+
+/** CNNT_CLK_EN_REG register
+ *  NA
+ */
+#define CNNT_CLK_EN_REG (DR_REG_CNNT_BASE + 0x4)
+/** CNNT_SYS_DATE : R/W; bitpos: [30:0]; default: 38826240;
+ *  need_des
+ */
+#define CNNT_SYS_DATE    0x7FFFFFFFU
+#define CNNT_SYS_DATE_M  (CNNT_SYS_DATE_V << CNNT_SYS_DATE_S)
+#define CNNT_SYS_DATE_V  0x7FFFFFFFU
+#define CNNT_SYS_DATE_S  0
+/** CNNT_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  NA
+ */
+#define CNNT_SYS_CLK_EN    (BIT(31))
+#define CNNT_SYS_CLK_EN_M  (CNNT_SYS_CLK_EN_V << CNNT_SYS_CLK_EN_S)
+#define CNNT_SYS_CLK_EN_V  0x00000001U
+#define CNNT_SYS_CLK_EN_S  31
+
+/** CNNT_SYS_SDMMC_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define CNNT_SYS_SDMMC_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x10)
+/** CNNT_SYS_SDMMC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures sdmmc memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define CNNT_SYS_SDMMC_MEM_LP_MODE    0x00000003U
+#define CNNT_SYS_SDMMC_MEM_LP_MODE_M  (CNNT_SYS_SDMMC_MEM_LP_MODE_V << CNNT_SYS_SDMMC_MEM_LP_MODE_S)
+#define CNNT_SYS_SDMMC_MEM_LP_MODE_V  0x00000003U
+#define CNNT_SYS_SDMMC_MEM_LP_MODE_S  0
+/** CNNT_SYS_SDMMC_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down sdmmc memory.
+ */
+#define CNNT_SYS_SDMMC_MEM_LP_EN    (BIT(2))
+#define CNNT_SYS_SDMMC_MEM_LP_EN_M  (CNNT_SYS_SDMMC_MEM_LP_EN_V << CNNT_SYS_SDMMC_MEM_LP_EN_S)
+#define CNNT_SYS_SDMMC_MEM_LP_EN_V  0x00000001U
+#define CNNT_SYS_SDMMC_MEM_LP_EN_S  2
+/** CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control sdmmc memory, disable hardware control.
+ */
+#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL    (BIT(3))
+#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_M  (CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_V << CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_S)
+#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define CNNT_SYS_SDMMC_MEM_LP_FORCE_CTRL_S  3
+
+/** CNNT_SYS_USB_OTGHS_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define CNNT_SYS_USB_OTGHS_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x14)
+/** CNNT_SYS_USB_OTGHS_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures usb_otghs memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE    0x00000003U
+#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_M  (CNNT_SYS_USB_OTGHS_MEM_LP_MODE_V << CNNT_SYS_USB_OTGHS_MEM_LP_MODE_S)
+#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_V  0x00000003U
+#define CNNT_SYS_USB_OTGHS_MEM_LP_MODE_S  0
+/** CNNT_SYS_USB_OTGHS_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down usb_otghs memory.
+ */
+#define CNNT_SYS_USB_OTGHS_MEM_LP_EN    (BIT(2))
+#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_M  (CNNT_SYS_USB_OTGHS_MEM_LP_EN_V << CNNT_SYS_USB_OTGHS_MEM_LP_EN_S)
+#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTGHS_MEM_LP_EN_S  2
+/** CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control usb_otghs memory, disable hardware control.
+ */
+#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL    (BIT(3))
+#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_M  (CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_V << CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_S)
+#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define CNNT_SYS_USB_OTGHS_MEM_LP_FORCE_CTRL_S  3
+
+/** CNNT_SYS_USB_DEVICE_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define CNNT_SYS_USB_DEVICE_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x18)
+/** CNNT_SYS_USB_DEVICE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures usb_device memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE    0x00000003U
+#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_M  (CNNT_SYS_USB_DEVICE_MEM_LP_MODE_V << CNNT_SYS_USB_DEVICE_MEM_LP_MODE_S)
+#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_V  0x00000003U
+#define CNNT_SYS_USB_DEVICE_MEM_LP_MODE_S  0
+/** CNNT_SYS_USB_DEVICE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down usb_device memory.
+ */
+#define CNNT_SYS_USB_DEVICE_MEM_LP_EN    (BIT(2))
+#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_M  (CNNT_SYS_USB_DEVICE_MEM_LP_EN_V << CNNT_SYS_USB_DEVICE_MEM_LP_EN_S)
+#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_V  0x00000001U
+#define CNNT_SYS_USB_DEVICE_MEM_LP_EN_S  2
+/** CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control usb_device (serial jtag) memory, disable
+ *  hardware control.
+ */
+#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL    (BIT(3))
+#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_M  (CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_V << CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_S)
+#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define CNNT_SYS_USB_DEVICE_MEM_LP_FORCE_CTRL_S  3
+
+/** CNNT_SYS_GMAC_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define CNNT_SYS_GMAC_MEM_LP_CTRL_REG (DR_REG_CNNT_BASE + 0x1c)
+/** CNNT_SYS_GMAC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures gmac memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define CNNT_SYS_GMAC_MEM_LP_MODE    0x00000003U
+#define CNNT_SYS_GMAC_MEM_LP_MODE_M  (CNNT_SYS_GMAC_MEM_LP_MODE_V << CNNT_SYS_GMAC_MEM_LP_MODE_S)
+#define CNNT_SYS_GMAC_MEM_LP_MODE_V  0x00000003U
+#define CNNT_SYS_GMAC_MEM_LP_MODE_S  0
+/** CNNT_SYS_GMAC_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down gmac memory.
+ */
+#define CNNT_SYS_GMAC_MEM_LP_EN    (BIT(2))
+#define CNNT_SYS_GMAC_MEM_LP_EN_M  (CNNT_SYS_GMAC_MEM_LP_EN_V << CNNT_SYS_GMAC_MEM_LP_EN_S)
+#define CNNT_SYS_GMAC_MEM_LP_EN_V  0x00000001U
+#define CNNT_SYS_GMAC_MEM_LP_EN_S  2
+/** CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control gmac memory, disable hardware control.
+ */
+#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL    (BIT(3))
+#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_M  (CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_V << CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_S)
+#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define CNNT_SYS_GMAC_MEM_LP_FORCE_CTRL_S  3
+
+/** CNNT_SYS_SPRF_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_SPRF_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x20)
+/** CNNT_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define CNNT_SYS_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
+#define CNNT_SYS_SPRF_MEM_AUX_CTRL_M  (CNNT_SYS_SPRF_MEM_AUX_CTRL_V << CNNT_SYS_SPRF_MEM_AUX_CTRL_S)
+#define CNNT_SYS_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define CNNT_SYS_SPRF_MEM_AUX_CTRL_S  0
+
+/** CNNT_SYS_SDPRF_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x24)
+/** CNNT_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define CNNT_SYS_SDPRF_MEM_AUX_CTRL    0xFFFFFFFFU
+#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_M  (CNNT_SYS_SDPRF_MEM_AUX_CTRL_V << CNNT_SYS_SDPRF_MEM_AUX_CTRL_S)
+#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define CNNT_SYS_SDPRF_MEM_AUX_CTRL_S  0
+
+/** CNNT_SYS_HP_PAD_ULPI_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define CNNT_SYS_HP_PAD_ULPI_CTRL_REG (DR_REG_CNNT_BASE + 0x28)
+/** CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN : R/W; bitpos: [30]; default: 0;
+ *  PAD ULPI Clock output inv Enable, valid only when CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN
+ *  is 1.
+ */
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN    (BIT(30))
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_M  (CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_V << CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_S)
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_V  0x00000001U
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_INV_EN_S  30
+/** CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN : R/W; bitpos: [31]; default: 0;
+ *  PAD ULPI Clock output Enable. 0: pad_ulpi_clk is used as input clk, 1: pad_ulpi_clk
+ *  is used as output clk
+ */
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN    (BIT(31))
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_M  (CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_V << CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_S)
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_V  0x00000001U
+#define CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN_S  31
+
+/** CNNT_SYS_USB_CLK_CTRL_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define CNNT_SYS_USB_CLK_CTRL_REG (DR_REG_CNNT_BASE + 0x2c)
+/** CNNT_SYS_USB_48M_DIV_NUM : R/W; bitpos: [15:8]; default: 9;
+ *  usb 480m to 25m divide number.
+ */
+#define CNNT_SYS_USB_48M_DIV_NUM    0x000000FFU
+#define CNNT_SYS_USB_48M_DIV_NUM_M  (CNNT_SYS_USB_48M_DIV_NUM_V << CNNT_SYS_USB_48M_DIV_NUM_S)
+#define CNNT_SYS_USB_48M_DIV_NUM_V  0x000000FFU
+#define CNNT_SYS_USB_48M_DIV_NUM_S  8
+/** CNNT_SYS_USB_25M_DIV_NUM : R/W; bitpos: [23:16]; default: 19;
+ *  usb 500m to 25m divide number.
+ */
+#define CNNT_SYS_USB_25M_DIV_NUM    0x000000FFU
+#define CNNT_SYS_USB_25M_DIV_NUM_M  (CNNT_SYS_USB_25M_DIV_NUM_V << CNNT_SYS_USB_25M_DIV_NUM_S)
+#define CNNT_SYS_USB_25M_DIV_NUM_V  0x000000FFU
+#define CNNT_SYS_USB_25M_DIV_NUM_S  16
+/** CNNT_SYS_USB_12M_DIV_NUM : R/W; bitpos: [31:24]; default: 39;
+ *  usb 480m to 12m divide number.
+ */
+#define CNNT_SYS_USB_12M_DIV_NUM    0x000000FFU
+#define CNNT_SYS_USB_12M_DIV_NUM_M  (CNNT_SYS_USB_12M_DIV_NUM_V << CNNT_SYS_USB_12M_DIV_NUM_S)
+#define CNNT_SYS_USB_12M_DIV_NUM_V  0x000000FFU
+#define CNNT_SYS_USB_12M_DIV_NUM_S  24
+
+/** CNNT_SYS_USB_OTG20_CTRL_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define CNNT_SYS_USB_OTG20_CTRL_REG (DR_REG_CNNT_BASE + 0x30)
+/** CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  usb otg20 utmifs clk enable.
+ */
+#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN    (BIT(23))
+#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_M  (CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_V << CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_S)
+#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_UTMIFS_CLK_EN_S  23
+/** CNNT_SYS_USB_OTG20_ULPI_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  usb otg20 ulpi clk enable.
+ */
+#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN    (BIT(24))
+#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_M  (CNNT_SYS_USB_OTG20_ULPI_CLK_EN_V << CNNT_SYS_USB_OTG20_ULPI_CLK_EN_S)
+#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_ULPI_CLK_EN_S  24
+/** CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL : R/W; bitpos: [26:25]; default: 0;
+ *  usb otg20 hs phy src sel. 2''d0: 12m, 2''d1: 25m, 2''d2: pad_hsphy_refclk.'
+ */
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL    0x00000003U
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_M  (CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_V << CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_S)
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_V  0x00000003U
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_SRC_SEL_S  25
+/** CNNT_SYS_USB_OTG20_PHYREF_CLK_EN : R/W; bitpos: [27]; default: 0;
+ *  usb otg20 hs phy refclk enable.
+ */
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN    (BIT(27))
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_M  (CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_V << CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_S)
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_PHYREF_CLK_EN_S  27
+/** CNNT_SYS_USB_OTG20_PHY_RST_EN : R/W; bitpos: [29]; default: 1;
+ *  usb otg20 phy reset en
+ */
+#define CNNT_SYS_USB_OTG20_PHY_RST_EN    (BIT(29))
+#define CNNT_SYS_USB_OTG20_PHY_RST_EN_M  (CNNT_SYS_USB_OTG20_PHY_RST_EN_V << CNNT_SYS_USB_OTG20_PHY_RST_EN_S)
+#define CNNT_SYS_USB_OTG20_PHY_RST_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_PHY_RST_EN_S  29
+/** CNNT_SYS_USB_OTG20_AHB_RST_EN : R/W; bitpos: [30]; default: 1;
+ *  usb otg20 ahb reset en
+ */
+#define CNNT_SYS_USB_OTG20_AHB_RST_EN    (BIT(30))
+#define CNNT_SYS_USB_OTG20_AHB_RST_EN_M  (CNNT_SYS_USB_OTG20_AHB_RST_EN_V << CNNT_SYS_USB_OTG20_AHB_RST_EN_S)
+#define CNNT_SYS_USB_OTG20_AHB_RST_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_AHB_RST_EN_S  30
+/** CNNT_SYS_USB_OTG20_APB_RST_EN : R/W; bitpos: [31]; default: 1;
+ *  usb otg20 apb reset en
+ */
+#define CNNT_SYS_USB_OTG20_APB_RST_EN    (BIT(31))
+#define CNNT_SYS_USB_OTG20_APB_RST_EN_M  (CNNT_SYS_USB_OTG20_APB_RST_EN_V << CNNT_SYS_USB_OTG20_APB_RST_EN_S)
+#define CNNT_SYS_USB_OTG20_APB_RST_EN_V  0x00000001U
+#define CNNT_SYS_USB_OTG20_APB_RST_EN_S  31
+
+/** CNNT_SYS_HP_USB_DEVICE_CTRL_REG register
+ *  HP USB Clock Reset Control Register.
+ */
+#define CNNT_SYS_HP_USB_DEVICE_CTRL_REG (DR_REG_CNNT_BASE + 0x34)
+/** CNNT_SYS_USB_DEVICE_48M_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  usb device fs phy clock enable.
+ */
+#define CNNT_SYS_USB_DEVICE_48M_CLK_EN    (BIT(30))
+#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_M  (CNNT_SYS_USB_DEVICE_48M_CLK_EN_V << CNNT_SYS_USB_DEVICE_48M_CLK_EN_S)
+#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_V  0x00000001U
+#define CNNT_SYS_USB_DEVICE_48M_CLK_EN_S  30
+/** CNNT_SYS_USB_DEVICE_RST_EN : R/W; bitpos: [31]; default: 0;
+ *  usb device reset en
+ */
+#define CNNT_SYS_USB_DEVICE_RST_EN    (BIT(31))
+#define CNNT_SYS_USB_DEVICE_RST_EN_M  (CNNT_SYS_USB_DEVICE_RST_EN_V << CNNT_SYS_USB_DEVICE_RST_EN_S)
+#define CNNT_SYS_USB_DEVICE_RST_EN_V  0x00000001U
+#define CNNT_SYS_USB_DEVICE_RST_EN_S  31
+
+/** CNNT_SYS_HP_SDMMC_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_SDMMC_CTRL_REG (DR_REG_CNNT_BASE + 0x38)
+/** CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN : R/W; bitpos: [29]; default: 0;
+ *  this reg is used to enable the post_write function of the ahb2axi bridge for sdmmc
+ */
+#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN    (BIT(29))
+#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_M  (CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_V << CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_S)
+#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_V  0x00000001U
+#define CNNT_SYS_SDMMC_AHB2AXI_POST_WRITE_EN_S  29
+/** CNNT_SYS_SDMMC_RST_EN : R/W; bitpos: [30]; default: 0;
+ *  hp sdmmc reset en
+ */
+#define CNNT_SYS_SDMMC_RST_EN    (BIT(30))
+#define CNNT_SYS_SDMMC_RST_EN_M  (CNNT_SYS_SDMMC_RST_EN_V << CNNT_SYS_SDMMC_RST_EN_S)
+#define CNNT_SYS_SDMMC_RST_EN_V  0x00000001U
+#define CNNT_SYS_SDMMC_RST_EN_S  30
+/** CNNT_SYS_SDMMC_FORCE_NORST : R/W; bitpos: [31]; default: 0;
+ *  hp sdmmc force norst
+ */
+#define CNNT_SYS_SDMMC_FORCE_NORST    (BIT(31))
+#define CNNT_SYS_SDMMC_FORCE_NORST_M  (CNNT_SYS_SDMMC_FORCE_NORST_V << CNNT_SYS_SDMMC_FORCE_NORST_S)
+#define CNNT_SYS_SDMMC_FORCE_NORST_V  0x00000001U
+#define CNNT_SYS_SDMMC_FORCE_NORST_S  31
+
+/** CNNT_SYS_HP_EMAC_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_CTRL_REG (DR_REG_CNNT_BASE + 0x3c)
+/** CNNT_SYS_EMAC_USELESS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_USELESS_CLK_EN    (BIT(0))
+#define CNNT_SYS_EMAC_USELESS_CLK_EN_M  (CNNT_SYS_EMAC_USELESS_CLK_EN_V << CNNT_SYS_EMAC_USELESS_CLK_EN_S)
+#define CNNT_SYS_EMAC_USELESS_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_USELESS_CLK_EN_S  0
+/** CNNT_SYS_EMAC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RST_EN    (BIT(1))
+#define CNNT_SYS_EMAC_RST_EN_M  (CNNT_SYS_EMAC_RST_EN_V << CNNT_SYS_EMAC_RST_EN_S)
+#define CNNT_SYS_EMAC_RST_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RST_EN_S  1
+/** CNNT_SYS_EMAC_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_FORCE_NORST    (BIT(2))
+#define CNNT_SYS_EMAC_FORCE_NORST_M  (CNNT_SYS_EMAC_FORCE_NORST_V << CNNT_SYS_EMAC_FORCE_NORST_S)
+#define CNNT_SYS_EMAC_FORCE_NORST_V  0x00000001U
+#define CNNT_SYS_EMAC_FORCE_NORST_S  2
+
+/** CNNT_SYS_HP_EMAC_REF_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_REF_CTRL_REG (DR_REG_CNNT_BASE + 0x40)
+/** CNNT_SYS_EMAC_REF_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  select emac reference clock source. 0: mpll 500MHz, 1: cpll 300MHz.
+ */
+#define CNNT_SYS_EMAC_REF_CLK_SEL    0x00000003U
+#define CNNT_SYS_EMAC_REF_CLK_SEL_M  (CNNT_SYS_EMAC_REF_CLK_SEL_V << CNNT_SYS_EMAC_REF_CLK_SEL_S)
+#define CNNT_SYS_EMAC_REF_CLK_SEL_V  0x00000003U
+#define CNNT_SYS_EMAC_REF_CLK_SEL_S  0
+/** CNNT_SYS_EMAC_REF_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Set as 1 to enable emac reference clock source selection
+ */
+#define CNNT_SYS_EMAC_REF_CLK_EN    (BIT(2))
+#define CNNT_SYS_EMAC_REF_CLK_EN_M  (CNNT_SYS_EMAC_REF_CLK_EN_V << CNNT_SYS_EMAC_REF_CLK_EN_S)
+#define CNNT_SYS_EMAC_REF_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_REF_CLK_EN_S  2
+/** CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN    (BIT(3))
+#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_M  (CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_V << CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_S)
+#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_REF_50M_PAD_OUT_CLK_EN_S  3
+/** CNNT_SYS_EMAC_REF_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Divide number of the divider which is used to divide reference clock source.
+ */
+#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM    0x000000FFU
+#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_M  (CNNT_SYS_EMAC_REF_CLK_DIV_NUM_V << CNNT_SYS_EMAC_REF_CLK_DIV_NUM_S)
+#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_V  0x000000FFU
+#define CNNT_SYS_EMAC_REF_CLK_DIV_NUM_S  8
+
+/** CNNT_SYS_HP_EMAC_RMII_PAD_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_RMII_PAD_CTRL_REG (DR_REG_CNNT_BASE + 0x44)
+/** CNNT_SYS_EMAC_RMII_PAD_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN    (BIT(1))
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_M  (CNNT_SYS_EMAC_RMII_PAD_CLK_EN_V << CNNT_SYS_EMAC_RMII_PAD_CLK_EN_S)
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_EN_S  1
+/** CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN    (BIT(2))
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_M  (CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_S)
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RMII_PAD_CLK_INV_EN_S  2
+
+/** CNNT_SYS_HP_EMAC_RMII_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_RMII_CTRL_REG (DR_REG_CNNT_BASE + 0x48)
+/** CNNT_SYS_EMAC_RMII_CLK_SEL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RMII_CLK_SEL    (BIT(0))
+#define CNNT_SYS_EMAC_RMII_CLK_SEL_M  (CNNT_SYS_EMAC_RMII_CLK_SEL_V << CNNT_SYS_EMAC_RMII_CLK_SEL_S)
+#define CNNT_SYS_EMAC_RMII_CLK_SEL_V  0x00000001U
+#define CNNT_SYS_EMAC_RMII_CLK_SEL_S  0
+/** CNNT_SYS_EMAC_RMII_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RMII_CLK_EN    (BIT(1))
+#define CNNT_SYS_EMAC_RMII_CLK_EN_M  (CNNT_SYS_EMAC_RMII_CLK_EN_V << CNNT_SYS_EMAC_RMII_CLK_EN_S)
+#define CNNT_SYS_EMAC_RMII_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RMII_CLK_EN_S  1
+/** CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN    (BIT(2))
+#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_M  (CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_V << CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_S)
+#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RMII_PAD_OUT_CLK_EN_S  2
+/** CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM : R/W; bitpos: [12:8]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM    0x0000001FU
+#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_M  (CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_V << CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_S)
+#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_V  0x0000001FU
+#define CNNT_SYS_EMAC_RXTX_CLK_DIV_NUM_S  8
+
+/** CNNT_SYS_HP_EMAC_RX_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_RX_CTRL_REG (DR_REG_CNNT_BASE + 0x4c)
+/** CNNT_SYS_EMAC_RX_PAD_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RX_PAD_CLK_EN    (BIT(0))
+#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_M  (CNNT_SYS_EMAC_RX_PAD_CLK_EN_V << CNNT_SYS_EMAC_RX_PAD_CLK_EN_S)
+#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RX_PAD_CLK_EN_S  0
+/** CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN    (BIT(1))
+#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_M  (CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_S)
+#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RX_PAD_CLK_INV_EN_S  1
+/** CNNT_SYS_EMAC_RX_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RX_CLK_SEL    (BIT(2))
+#define CNNT_SYS_EMAC_RX_CLK_SEL_M  (CNNT_SYS_EMAC_RX_CLK_SEL_V << CNNT_SYS_EMAC_RX_CLK_SEL_S)
+#define CNNT_SYS_EMAC_RX_CLK_SEL_V  0x00000001U
+#define CNNT_SYS_EMAC_RX_CLK_SEL_S  2
+/** CNNT_SYS_EMAC_RX_180_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_RX_180_CLK_EN    (BIT(3))
+#define CNNT_SYS_EMAC_RX_180_CLK_EN_M  (CNNT_SYS_EMAC_RX_180_CLK_EN_V << CNNT_SYS_EMAC_RX_180_CLK_EN_S)
+#define CNNT_SYS_EMAC_RX_180_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_RX_180_CLK_EN_S  3
+
+/** CNNT_SYS_HP_EMAC_TX_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_TX_CTRL_REG (DR_REG_CNNT_BASE + 0x50)
+/** CNNT_SYS_EMAC_TX_PAD_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_TX_PAD_CLK_EN    (BIT(0))
+#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_M  (CNNT_SYS_EMAC_TX_PAD_CLK_EN_V << CNNT_SYS_EMAC_TX_PAD_CLK_EN_S)
+#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_TX_PAD_CLK_EN_S  0
+/** CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN    (BIT(1))
+#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_M  (CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_V << CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_S)
+#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_TX_PAD_CLK_INV_EN_S  1
+/** CNNT_SYS_EMAC_TX_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_TX_CLK_SEL    (BIT(2))
+#define CNNT_SYS_EMAC_TX_CLK_SEL_M  (CNNT_SYS_EMAC_TX_CLK_SEL_V << CNNT_SYS_EMAC_TX_CLK_SEL_S)
+#define CNNT_SYS_EMAC_TX_CLK_SEL_V  0x00000001U
+#define CNNT_SYS_EMAC_TX_CLK_SEL_S  2
+/** CNNT_SYS_EMAC_TX_180_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define CNNT_SYS_EMAC_TX_180_CLK_EN    (BIT(3))
+#define CNNT_SYS_EMAC_TX_180_CLK_EN_M  (CNNT_SYS_EMAC_TX_180_CLK_EN_V << CNNT_SYS_EMAC_TX_180_CLK_EN_S)
+#define CNNT_SYS_EMAC_TX_180_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_TX_180_CLK_EN_S  3
+
+/** CNNT_SYS_HP_EMAC_PTP_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_HP_EMAC_PTP_CTRL_REG (DR_REG_CNNT_BASE + 0x54)
+/** CNNT_SYS_EMAC_PTP_REF_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Set as 1 to enable emac PTP clock source selection.
+ */
+#define CNNT_SYS_EMAC_PTP_REF_CLK_EN    (BIT(0))
+#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_M  (CNNT_SYS_EMAC_PTP_REF_CLK_EN_V << CNNT_SYS_EMAC_PTP_REF_CLK_EN_S)
+#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_V  0x00000001U
+#define CNNT_SYS_EMAC_PTP_REF_CLK_EN_S  0
+/** CNNT_SYS_EMAC_PTP_REF_CLK_SEL : R/W; bitpos: [1]; default: 0;
+ *  select emac PTP clock source. 0: xtal clock, 1: 80MHz internal clock.
+ */
+#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL    (BIT(1))
+#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_M  (CNNT_SYS_EMAC_PTP_REF_CLK_SEL_V << CNNT_SYS_EMAC_PTP_REF_CLK_SEL_S)
+#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_V  0x00000001U
+#define CNNT_SYS_EMAC_PTP_REF_CLK_SEL_S  1
+
+/** CNNT_SYS_CNNT_IOMUX_CTRL0_REG register
+ *  need_des
+ */
+#define CNNT_SYS_CNNT_IOMUX_CTRL0_REG (DR_REG_CNNT_BASE + 0x58)
+/** CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN : R/W; bitpos: [0]; default: 0;
+ *  cnnt_iomux rst en
+ */
+#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN    (BIT(0))
+#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_M  (CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_V << CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_S)
+#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_V  0x00000001U
+#define CNNT_SYS_REG_CNNT_IOMUX_APB_RST_EN_S  0
+
+/** CNNT_SYS_SPRAM_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_REG (DR_REG_CNNT_BASE + 0x5c)
+/** CNNT_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define CNNT_SYS_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
+#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_M  (CNNT_SYS_SPRAM_MEM_AUX_CTRL_V << CNNT_SYS_SPRAM_MEM_AUX_CTRL_S)
+#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define CNNT_SYS_SPRAM_MEM_AUX_CTRL_S  0
+
+/** CNNT_SYS_GMAC_CTRL0_REG register
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_CTRL0_REG (DR_REG_CNNT_BASE + 0x60)
+/** CNNT_SYS_PTP_PPS : RO; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_PTP_PPS    (BIT(0))
+#define CNNT_SYS_PTP_PPS_M  (CNNT_SYS_PTP_PPS_V << CNNT_SYS_PTP_PPS_S)
+#define CNNT_SYS_PTP_PPS_V  0x00000001U
+#define CNNT_SYS_PTP_PPS_S  0
+/** CNNT_SYS_SBD_FLOWCTRL : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_SBD_FLOWCTRL    (BIT(1))
+#define CNNT_SYS_SBD_FLOWCTRL_M  (CNNT_SYS_SBD_FLOWCTRL_V << CNNT_SYS_SBD_FLOWCTRL_S)
+#define CNNT_SYS_SBD_FLOWCTRL_V  0x00000001U
+#define CNNT_SYS_SBD_FLOWCTRL_S  1
+/** CNNT_SYS_PHY_INTF_SEL : R/W; bitpos: [4:2]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_PHY_INTF_SEL    0x00000007U
+#define CNNT_SYS_PHY_INTF_SEL_M  (CNNT_SYS_PHY_INTF_SEL_V << CNNT_SYS_PHY_INTF_SEL_S)
+#define CNNT_SYS_PHY_INTF_SEL_V  0x00000007U
+#define CNNT_SYS_PHY_INTF_SEL_S  2
+/** CNNT_SYS_GMAC_MEM_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON    (BIT(5))
+#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_M  (CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_V << CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_S)
+#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_V  0x00000001U
+#define CNNT_SYS_GMAC_MEM_CLK_FORCE_ON_S  5
+/** CNNT_SYS_GMAC_RST_CLK_TX_N : RO; bitpos: [6]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_RST_CLK_TX_N    (BIT(6))
+#define CNNT_SYS_GMAC_RST_CLK_TX_N_M  (CNNT_SYS_GMAC_RST_CLK_TX_N_V << CNNT_SYS_GMAC_RST_CLK_TX_N_S)
+#define CNNT_SYS_GMAC_RST_CLK_TX_N_V  0x00000001U
+#define CNNT_SYS_GMAC_RST_CLK_TX_N_S  6
+/** CNNT_SYS_GMAC_RST_CLK_RX_N : RO; bitpos: [7]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_RST_CLK_RX_N    (BIT(7))
+#define CNNT_SYS_GMAC_RST_CLK_RX_N_M  (CNNT_SYS_GMAC_RST_CLK_RX_N_V << CNNT_SYS_GMAC_RST_CLK_RX_N_S)
+#define CNNT_SYS_GMAC_RST_CLK_RX_N_V  0x00000001U
+#define CNNT_SYS_GMAC_RST_CLK_RX_N_S  7
+/** CNNT_SYS_GMAC_CACTIVE : RO; bitpos: [8]; default: 0;
+ *  this signal indicates that the GMAC-AXI requires its clock signal , 1 : required ,0
+ *  : not required
+ */
+#define CNNT_SYS_GMAC_CACTIVE    (BIT(8))
+#define CNNT_SYS_GMAC_CACTIVE_M  (CNNT_SYS_GMAC_CACTIVE_V << CNNT_SYS_GMAC_CACTIVE_S)
+#define CNNT_SYS_GMAC_CACTIVE_V  0x00000001U
+#define CNNT_SYS_GMAC_CACTIVE_S  8
+/** CNNT_SYS_GMAC_CSYSACK : RO; bitpos: [9]; default: 0;
+ *  this signal is the acknowledgement from the GMAC-AXI to the system for low-power
+ *  request ,active high
+ */
+#define CNNT_SYS_GMAC_CSYSACK    (BIT(9))
+#define CNNT_SYS_GMAC_CSYSACK_M  (CNNT_SYS_GMAC_CSYSACK_V << CNNT_SYS_GMAC_CSYSACK_S)
+#define CNNT_SYS_GMAC_CSYSACK_V  0x00000001U
+#define CNNT_SYS_GMAC_CSYSACK_S  9
+/** CNNT_SYS_GMAC_CSYSREQ : R/W; bitpos: [10]; default: 0;
+ *  clock controller system low-power request , when asserted low ,indicates the
+ *  controller hs requested the GMAX-AXI to enter a lowpower state
+ */
+#define CNNT_SYS_GMAC_CSYSREQ    (BIT(10))
+#define CNNT_SYS_GMAC_CSYSREQ_M  (CNNT_SYS_GMAC_CSYSREQ_V << CNNT_SYS_GMAC_CSYSREQ_S)
+#define CNNT_SYS_GMAC_CSYSREQ_V  0x00000001U
+#define CNNT_SYS_GMAC_CSYSREQ_S  10
+/** CNNT_SYS_GMAC_APB_POSTW_EN : R/W; bitpos: [11]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_APB_POSTW_EN    (BIT(11))
+#define CNNT_SYS_GMAC_APB_POSTW_EN_M  (CNNT_SYS_GMAC_APB_POSTW_EN_V << CNNT_SYS_GMAC_APB_POSTW_EN_S)
+#define CNNT_SYS_GMAC_APB_POSTW_EN_V  0x00000001U
+#define CNNT_SYS_GMAC_APB_POSTW_EN_S  11
+/** CNNT_SYS_GMAC_MEM_PRDYN : RO; bitpos: [12]; default: 1;
+ *  record memory power status
+ */
+#define CNNT_SYS_GMAC_MEM_PRDYN    (BIT(12))
+#define CNNT_SYS_GMAC_MEM_PRDYN_M  (CNNT_SYS_GMAC_MEM_PRDYN_V << CNNT_SYS_GMAC_MEM_PRDYN_S)
+#define CNNT_SYS_GMAC_MEM_PRDYN_V  0x00000001U
+#define CNNT_SYS_GMAC_MEM_PRDYN_S  12
+
+/** CNNT_SYS_GMAC_CTRL1_REG register
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_CTRL1_REG (DR_REG_CNNT_BASE + 0x64)
+/** CNNT_SYS_PTP_TIMESTAMP_L : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_PTP_TIMESTAMP_L    0xFFFFFFFFU
+#define CNNT_SYS_PTP_TIMESTAMP_L_M  (CNNT_SYS_PTP_TIMESTAMP_L_V << CNNT_SYS_PTP_TIMESTAMP_L_S)
+#define CNNT_SYS_PTP_TIMESTAMP_L_V  0xFFFFFFFFU
+#define CNNT_SYS_PTP_TIMESTAMP_L_S  0
+
+/** CNNT_SYS_GMAC_CTRL2_REG register
+ *  N/A
+ */
+#define CNNT_SYS_GMAC_CTRL2_REG (DR_REG_CNNT_BASE + 0x68)
+/** CNNT_SYS_PTP_TIMESTAMP_H : RO; bitpos: [31:0]; default: 0;
+ *  N/A
+ */
+#define CNNT_SYS_PTP_TIMESTAMP_H    0xFFFFFFFFU
+#define CNNT_SYS_PTP_TIMESTAMP_H_M  (CNNT_SYS_PTP_TIMESTAMP_H_V << CNNT_SYS_PTP_TIMESTAMP_H_S)
+#define CNNT_SYS_PTP_TIMESTAMP_H_V  0xFFFFFFFFU
+#define CNNT_SYS_PTP_TIMESTAMP_H_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cnnt_sys_struct.h b/components/soc/esp32s31/register/soc/cnnt_sys_struct.h
new file mode 100644
index 00000000000..276ee05bd07
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cnnt_sys_struct.h
@@ -0,0 +1,618 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: CNNT SYS VER DATE REG */
+/** Type of sys_ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sys_ver_date : R/W; bitpos: [31:0]; default: 539298086;
+         *  NA
+         */
+        uint32_t sys_ver_date:32;
+    };
+    uint32_t val;
+} cnnt_sys_ver_date_reg_t;
+
+
+/** Group: CNNT CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** sys_date : R/W; bitpos: [30:0]; default: 38826240;
+         *  need_des
+         */
+        uint32_t sys_date:31;
+        /** sys_clk_en : R/W; bitpos: [31]; default: 0;
+         *  NA
+         */
+        uint32_t sys_clk_en:1;
+    };
+    uint32_t val;
+} cnnt_clk_en_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of sys_sdmmc_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_sdmmc_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures sdmmc memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_sdmmc_mem_lp_mode:2;
+        /** sys_sdmmc_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down sdmmc memory.
+         */
+        uint32_t sys_sdmmc_mem_lp_en:1;
+        /** sys_sdmmc_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control sdmmc memory, disable hardware control.
+         */
+        uint32_t sys_sdmmc_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_sdmmc_mem_lp_ctrl_reg_t;
+
+/** Type of sys_usb_otghs_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_usb_otghs_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures usb_otghs memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_usb_otghs_mem_lp_mode:2;
+        /** sys_usb_otghs_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down usb_otghs memory.
+         */
+        uint32_t sys_usb_otghs_mem_lp_en:1;
+        /** sys_usb_otghs_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control usb_otghs memory, disable hardware control.
+         */
+        uint32_t sys_usb_otghs_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_usb_otghs_mem_lp_ctrl_reg_t;
+
+/** Type of sys_usb_device_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_usb_device_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures usb_device memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_usb_device_mem_lp_mode:2;
+        /** sys_usb_device_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down usb_device memory.
+         */
+        uint32_t sys_usb_device_mem_lp_en:1;
+        /** sys_usb_device_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control usb_device (serial jtag) memory, disable
+         *  hardware control.
+         */
+        uint32_t sys_usb_device_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_usb_device_mem_lp_ctrl_reg_t;
+
+/** Type of sys_gmac_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_gmac_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures gmac memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_gmac_mem_lp_mode:2;
+        /** sys_gmac_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down gmac memory.
+         */
+        uint32_t sys_gmac_mem_lp_en:1;
+        /** sys_gmac_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control gmac memory, disable hardware control.
+         */
+        uint32_t sys_gmac_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_gmac_mem_lp_ctrl_reg_t;
+
+
+/** Group: configure_register */
+/** Type of sys_sprf_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t sys_sprf_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} cnnt_sys_sprf_mem_aux_ctrl_reg_t;
+
+/** Type of sys_sdprf_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t sys_sdprf_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} cnnt_sys_sdprf_mem_aux_ctrl_reg_t;
+
+/** Type of sys_hp_pad_ulpi_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sys_hp_pad_ulpi_clk_out_inv_en : R/W; bitpos: [30]; default: 0;
+         *  PAD ULPI Clock output inv Enable, valid only when CNNT_SYS_HP_PAD_ULPI_CLK_OUT_EN
+         *  is 1.
+         */
+        uint32_t sys_hp_pad_ulpi_clk_out_inv_en:1;
+        /** sys_hp_pad_ulpi_clk_out_en : R/W; bitpos: [31]; default: 0;
+         *  PAD ULPI Clock output Enable. 0: pad_ulpi_clk is used as input clk, 1: pad_ulpi_clk
+         *  is used as output clk
+         */
+        uint32_t sys_hp_pad_ulpi_clk_out_en:1;
+    };
+    uint32_t val;
+} cnnt_sys_hp_pad_ulpi_ctrl_reg_t;
+
+/** Type of sys_usb_clk_ctrl register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** sys_usb_48m_div_num : R/W; bitpos: [15:8]; default: 9;
+         *  usb 480m to 25m divide number.
+         */
+        uint32_t sys_usb_48m_div_num:8;
+        /** sys_usb_25m_div_num : R/W; bitpos: [23:16]; default: 19;
+         *  usb 500m to 25m divide number.
+         */
+        uint32_t sys_usb_25m_div_num:8;
+        /** sys_usb_12m_div_num : R/W; bitpos: [31:24]; default: 39;
+         *  usb 480m to 12m divide number.
+         */
+        uint32_t sys_usb_12m_div_num:8;
+    };
+    uint32_t val;
+} cnnt_sys_usb_clk_ctrl_reg_t;
+
+/** Type of sys_usb_otg20_ctrl register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** sys_usb_otg20_utmifs_clk_en : R/W; bitpos: [23]; default: 1;
+         *  usb otg20 utmifs clk enable.
+         */
+        uint32_t sys_usb_otg20_utmifs_clk_en:1;
+        /** sys_usb_otg20_ulpi_clk_en : R/W; bitpos: [24]; default: 0;
+         *  usb otg20 ulpi clk enable.
+         */
+        uint32_t sys_usb_otg20_ulpi_clk_en:1;
+        /** sys_usb_otg20_phyref_clk_src_sel : R/W; bitpos: [26:25]; default: 0;
+         *  usb otg20 hs phy src sel. 2''d0: 12m, 2''d1: 25m, 2''d2: pad_hsphy_refclk.'
+         */
+        uint32_t sys_usb_otg20_phyref_clk_src_sel:2;
+        /** sys_usb_otg20_phyref_clk_en : R/W; bitpos: [27]; default: 0;
+         *  usb otg20 hs phy refclk enable.
+         */
+        uint32_t sys_usb_otg20_phyref_clk_en:1;
+        uint32_t reserved_28:1;
+        /** sys_usb_otg20_phy_rst_en : R/W; bitpos: [29]; default: 1;
+         *  usb otg20 phy reset en
+         */
+        uint32_t sys_usb_otg20_phy_rst_en:1;
+        /** sys_usb_otg20_ahb_rst_en : R/W; bitpos: [30]; default: 1;
+         *  usb otg20 ahb reset en
+         */
+        uint32_t sys_usb_otg20_ahb_rst_en:1;
+        /** sys_usb_otg20_apb_rst_en : R/W; bitpos: [31]; default: 1;
+         *  usb otg20 apb reset en
+         */
+        uint32_t sys_usb_otg20_apb_rst_en:1;
+    };
+    uint32_t val;
+} cnnt_sys_usb_otg20_ctrl_reg_t;
+
+/** Type of sys_hp_usb_device_ctrl register
+ *  HP USB Clock Reset Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sys_usb_device_48m_clk_en : R/W; bitpos: [30]; default: 1;
+         *  usb device fs phy clock enable.
+         */
+        uint32_t sys_usb_device_48m_clk_en:1;
+        /** sys_usb_device_rst_en : R/W; bitpos: [31]; default: 0;
+         *  usb device reset en
+         */
+        uint32_t sys_usb_device_rst_en:1;
+    };
+    uint32_t val;
+} cnnt_sys_hp_usb_device_ctrl_reg_t;
+
+/** Type of sys_hp_sdmmc_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** sys_sdmmc_ahb2axi_post_write_en : R/W; bitpos: [29]; default: 0;
+         *  this reg is used to enable the post_write function of the ahb2axi bridge for sdmmc
+         */
+        uint32_t sys_sdmmc_ahb2axi_post_write_en:1;
+        /** sys_sdmmc_rst_en : R/W; bitpos: [30]; default: 0;
+         *  hp sdmmc reset en
+         */
+        uint32_t sys_sdmmc_rst_en:1;
+        /** sys_sdmmc_force_norst : R/W; bitpos: [31]; default: 0;
+         *  hp sdmmc force norst
+         */
+        uint32_t sys_sdmmc_force_norst:1;
+    };
+    uint32_t val;
+} cnnt_sys_hp_sdmmc_ctrl_reg_t;
+
+/** Type of sys_hp_emac_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_useless_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_useless_clk_en:1;
+        /** sys_emac_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rst_en:1;
+        /** sys_emac_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_ctrl_reg_t;
+
+/** Type of sys_hp_emac_ref_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_ref_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  select emac reference clock source. 0: mpll 500MHz, 1: cpll 300MHz.
+         */
+        uint32_t sys_emac_ref_clk_sel:2;
+        /** sys_emac_ref_clk_en : R/W; bitpos: [2]; default: 0;
+         *  Set as 1 to enable emac reference clock source selection
+         */
+        uint32_t sys_emac_ref_clk_en:1;
+        /** sys_emac_ref_50m_pad_out_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_ref_50m_pad_out_clk_en:1;
+        uint32_t reserved_4:4;
+        /** sys_emac_ref_clk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  Divide number of the divider which is used to divide reference clock source.
+         */
+        uint32_t sys_emac_ref_clk_div_num:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_ref_ctrl_reg_t;
+
+/** Type of sys_hp_emac_rmii_pad_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** sys_emac_rmii_pad_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rmii_pad_clk_en:1;
+        /** sys_emac_rmii_pad_clk_inv_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rmii_pad_clk_inv_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_rmii_pad_ctrl_reg_t;
+
+/** Type of sys_hp_emac_rmii_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_rmii_clk_sel : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rmii_clk_sel:1;
+        /** sys_emac_rmii_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rmii_clk_en:1;
+        /** sys_emac_rmii_pad_out_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rmii_pad_out_clk_en:1;
+        uint32_t reserved_3:5;
+        /** sys_emac_rxtx_clk_div_num : R/W; bitpos: [12:8]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rxtx_clk_div_num:5;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_rmii_ctrl_reg_t;
+
+/** Type of sys_hp_emac_rx_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_rx_pad_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rx_pad_clk_en:1;
+        /** sys_emac_rx_pad_clk_inv_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rx_pad_clk_inv_en:1;
+        /** sys_emac_rx_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rx_clk_sel:1;
+        /** sys_emac_rx_180_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_rx_180_clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_rx_ctrl_reg_t;
+
+/** Type of sys_hp_emac_tx_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_tx_pad_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_tx_pad_clk_en:1;
+        /** sys_emac_tx_pad_clk_inv_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_tx_pad_clk_inv_en:1;
+        /** sys_emac_tx_clk_sel : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_tx_clk_sel:1;
+        /** sys_emac_tx_180_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t sys_emac_tx_180_clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_tx_ctrl_reg_t;
+
+/** Type of sys_hp_emac_ptp_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_emac_ptp_ref_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Set as 1 to enable emac PTP clock source selection.
+         */
+        uint32_t sys_emac_ptp_ref_clk_en:1;
+        /** sys_emac_ptp_ref_clk_sel : R/W; bitpos: [1]; default: 0;
+         *  select emac PTP clock source. 0: xtal clock, 1: 80MHz internal clock.
+         */
+        uint32_t sys_emac_ptp_ref_clk_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cnnt_sys_hp_emac_ptp_ctrl_reg_t;
+
+/** Type of sys_spram_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t sys_spram_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} cnnt_sys_spram_mem_aux_ctrl_reg_t;
+
+
+/** Group: cnnt_iomux_ctrl */
+/** Type of sys_cnnt_iomux_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_reg_cnnt_iomux_apb_rst_en : R/W; bitpos: [0]; default: 0;
+         *  cnnt_iomux rst en
+         */
+        uint32_t sys_reg_cnnt_iomux_apb_rst_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cnnt_sys_cnnt_iomux_ctrl0_reg_t;
+
+
+/** Group: GMAC Control Register */
+/** Type of sys_gmac_ctrl0 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_pps : RO; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_pps:1;
+        /** sys_sbd_flowctrl : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_sbd_flowctrl:1;
+        /** sys_phy_intf_sel : R/W; bitpos: [4:2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_phy_intf_sel:3;
+        /** sys_gmac_mem_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_mem_clk_force_on:1;
+        /** sys_gmac_rst_clk_tx_n : RO; bitpos: [6]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_tx_n:1;
+        /** sys_gmac_rst_clk_rx_n : RO; bitpos: [7]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_rst_clk_rx_n:1;
+        /** sys_gmac_cactive : RO; bitpos: [8]; default: 0;
+         *  this signal indicates that the GMAC-AXI requires its clock signal , 1 : required ,0
+         *  : not required
+         */
+        uint32_t sys_gmac_cactive:1;
+        /** sys_gmac_csysack : RO; bitpos: [9]; default: 0;
+         *  this signal is the acknowledgement from the GMAC-AXI to the system for low-power
+         *  request ,active high
+         */
+        uint32_t sys_gmac_csysack:1;
+        /** sys_gmac_csysreq : R/W; bitpos: [10]; default: 0;
+         *  clock controller system low-power request , when asserted low ,indicates the
+         *  controller hs requested the GMAX-AXI to enter a lowpower state
+         */
+        uint32_t sys_gmac_csysreq:1;
+        /** sys_gmac_apb_postw_en : R/W; bitpos: [11]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_gmac_apb_postw_en:1;
+        /** sys_gmac_mem_prdyn : RO; bitpos: [12]; default: 1;
+         *  record memory power status
+         */
+        uint32_t sys_gmac_mem_prdyn:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} cnnt_sys_gmac_ctrl0_reg_t;
+
+/** Type of sys_gmac_ctrl1 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_l : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_l:32;
+    };
+    uint32_t val;
+} cnnt_sys_gmac_ctrl1_reg_t;
+
+/** Type of sys_gmac_ctrl2 register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ptp_timestamp_h : RO; bitpos: [31:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ptp_timestamp_h:32;
+    };
+    uint32_t val;
+} cnnt_sys_gmac_ctrl2_reg_t;
+
+
+typedef struct {
+    volatile cnnt_sys_ver_date_reg_t sys_ver_date;
+    volatile cnnt_clk_en_reg_t clk_en;
+    uint32_t reserved_008[2];
+    volatile cnnt_sys_sdmmc_mem_lp_ctrl_reg_t sys_sdmmc_mem_lp_ctrl;
+    volatile cnnt_sys_usb_otghs_mem_lp_ctrl_reg_t sys_usb_otghs_mem_lp_ctrl;
+    volatile cnnt_sys_usb_device_mem_lp_ctrl_reg_t sys_usb_device_mem_lp_ctrl;
+    volatile cnnt_sys_gmac_mem_lp_ctrl_reg_t sys_gmac_mem_lp_ctrl;
+    volatile cnnt_sys_sprf_mem_aux_ctrl_reg_t sys_sprf_mem_aux_ctrl;
+    volatile cnnt_sys_sdprf_mem_aux_ctrl_reg_t sys_sdprf_mem_aux_ctrl;
+    volatile cnnt_sys_hp_pad_ulpi_ctrl_reg_t sys_hp_pad_ulpi_ctrl;
+    volatile cnnt_sys_usb_clk_ctrl_reg_t sys_usb_clk_ctrl;
+    volatile cnnt_sys_usb_otg20_ctrl_reg_t sys_usb_otg20_ctrl;
+    volatile cnnt_sys_hp_usb_device_ctrl_reg_t sys_hp_usb_device_ctrl;
+    volatile cnnt_sys_hp_sdmmc_ctrl_reg_t sys_hp_sdmmc_ctrl;
+    volatile cnnt_sys_hp_emac_ctrl_reg_t sys_hp_emac_ctrl;
+    volatile cnnt_sys_hp_emac_ref_ctrl_reg_t sys_hp_emac_ref_ctrl;
+    volatile cnnt_sys_hp_emac_rmii_pad_ctrl_reg_t sys_hp_emac_rmii_pad_ctrl;
+    volatile cnnt_sys_hp_emac_rmii_ctrl_reg_t sys_hp_emac_rmii_ctrl;
+    volatile cnnt_sys_hp_emac_rx_ctrl_reg_t sys_hp_emac_rx_ctrl;
+    volatile cnnt_sys_hp_emac_tx_ctrl_reg_t sys_hp_emac_tx_ctrl;
+    volatile cnnt_sys_hp_emac_ptp_ctrl_reg_t sys_hp_emac_ptp_ctrl;
+    volatile cnnt_sys_cnnt_iomux_ctrl0_reg_t sys_cnnt_iomux_ctrl0;
+    volatile cnnt_sys_spram_mem_aux_ctrl_reg_t sys_spram_mem_aux_ctrl;
+    volatile cnnt_sys_gmac_ctrl0_reg_t sys_gmac_ctrl0;
+    volatile cnnt_sys_gmac_ctrl1_reg_t sys_gmac_ctrl1;
+    volatile cnnt_sys_gmac_ctrl2_reg_t sys_gmac_ctrl2;
+} cnnt_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cnnt_dev_t) == 0x6c, "Invalid size of cnnt_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cordic_reg.h b/components/soc/esp32s31/register/soc/cordic_reg.h
new file mode 100644
index 00000000000..f510e18bbb5
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cordic_reg.h
@@ -0,0 +1,351 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CORDIC_CSR_CFG_REG register
+ *  Cordic model config register
+ */
+#define CORDIC_CSR_CFG_REG (DR_REG_CORDIC_BASE + 0x0)
+/** CORDIC_FUNC : R/W; bitpos: [3:0]; default: 0;
+ *  Used to inicate the type of operation currently being performed
+ */
+#define CORDIC_FUNC    0x0000000FU
+#define CORDIC_FUNC_M  (CORDIC_FUNC_V << CORDIC_FUNC_S)
+#define CORDIC_FUNC_V  0x0000000FU
+#define CORDIC_FUNC_S  0
+/** CORDIC_PRES : R/W; bitpos: [7:4]; default: 0;
+ *  Instruct the cordic calculate cycle number
+ */
+#define CORDIC_PRES    0x0000000FU
+#define CORDIC_PRES_M  (CORDIC_PRES_V << CORDIC_PRES_S)
+#define CORDIC_PRES_V  0x0000000FU
+#define CORDIC_PRES_S  4
+/** CORDIC_SCALE : R/W; bitpos: [11:8]; default: 0;
+ *  The scaling of Input argument
+ */
+#define CORDIC_SCALE    0x0000000FU
+#define CORDIC_SCALE_M  (CORDIC_SCALE_V << CORDIC_SCALE_S)
+#define CORDIC_SCALE_V  0x0000000FU
+#define CORDIC_SCALE_S  8
+/** CORDIC_WORK_MODE : R/W; bitpos: [18:17]; default: 0;
+ *  Select Cordic Module data transfer Mode,2'd0: reg_in,reg_out, no zero mode, 2'd1:
+ *  dma_in, reg_out, no zero mode, 2'd2: dma_loop, 2'd3: reg_in, reg_out, zero mode
+ */
+#define CORDIC_WORK_MODE    0x00000003U
+#define CORDIC_WORK_MODE_M  (CORDIC_WORK_MODE_V << CORDIC_WORK_MODE_S)
+#define CORDIC_WORK_MODE_V  0x00000003U
+#define CORDIC_WORK_MODE_S  17
+/** CORDIC_RES_NUM : R/W; bitpos: [19]; default: 0;
+ *  Result number
+ */
+#define CORDIC_RES_NUM    (BIT(19))
+#define CORDIC_RES_NUM_M  (CORDIC_RES_NUM_V << CORDIC_RES_NUM_S)
+#define CORDIC_RES_NUM_V  0x00000001U
+#define CORDIC_RES_NUM_S  19
+/** CORDIC_ARG_NUM : R/W; bitpos: [20]; default: 0;
+ *  Argument number
+ */
+#define CORDIC_ARG_NUM    (BIT(20))
+#define CORDIC_ARG_NUM_M  (CORDIC_ARG_NUM_V << CORDIC_ARG_NUM_S)
+#define CORDIC_ARG_NUM_V  0x00000001U
+#define CORDIC_ARG_NUM_S  20
+/** CORDIC_RES_SIZE : R/W; bitpos: [21]; default: 0;
+ *  Result Size, 0: q1.15, 1: q1.31
+ */
+#define CORDIC_RES_SIZE    (BIT(21))
+#define CORDIC_RES_SIZE_M  (CORDIC_RES_SIZE_V << CORDIC_RES_SIZE_S)
+#define CORDIC_RES_SIZE_V  0x00000001U
+#define CORDIC_RES_SIZE_S  21
+/** CORDIC_ARG_SIZE : R/W; bitpos: [22]; default: 0;
+ *  Argument Size, 0: q1.15, 1: q1.31
+ */
+#define CORDIC_ARG_SIZE    (BIT(22))
+#define CORDIC_ARG_SIZE_M  (CORDIC_ARG_SIZE_V << CORDIC_ARG_SIZE_S)
+#define CORDIC_ARG_SIZE_V  0x00000001U
+#define CORDIC_ARG_SIZE_S  22
+/** CORDIC_UPDATE_FLAG : R/W/SC; bitpos: [29]; default: 0;
+ *  Used to synchronize register data to the computing core and start calculate
+ */
+#define CORDIC_UPDATE_FLAG    (BIT(29))
+#define CORDIC_UPDATE_FLAG_M  (CORDIC_UPDATE_FLAG_V << CORDIC_UPDATE_FLAG_S)
+#define CORDIC_UPDATE_FLAG_V  0x00000001U
+#define CORDIC_UPDATE_FLAG_S  29
+/** CORDIC_RES_ALL_RDY_FLAG : RO/SS/SC; bitpos: [30]; default: 0;
+ *  Used to indicate whether the operation all result has been stored in the result
+ *  register
+ */
+#define CORDIC_RES_ALL_RDY_FLAG    (BIT(30))
+#define CORDIC_RES_ALL_RDY_FLAG_M  (CORDIC_RES_ALL_RDY_FLAG_V << CORDIC_RES_ALL_RDY_FLAG_S)
+#define CORDIC_RES_ALL_RDY_FLAG_V  0x00000001U
+#define CORDIC_RES_ALL_RDY_FLAG_S  30
+/** CORDIC_RES_RDY_FLAG : RO/SS/SC; bitpos: [31]; default: 0;
+ *  Used to indicate whether the operation result has been stored in the result register
+ */
+#define CORDIC_RES_RDY_FLAG    (BIT(31))
+#define CORDIC_RES_RDY_FLAG_M  (CORDIC_RES_RDY_FLAG_V << CORDIC_RES_RDY_FLAG_S)
+#define CORDIC_RES_RDY_FLAG_V  0x00000001U
+#define CORDIC_RES_RDY_FLAG_S  31
+
+/** CORDIC_ARG1_REG register
+ *  Cordic argument 1 config register
+ */
+#define CORDIC_ARG1_REG (DR_REG_CORDIC_BASE + 0x4)
+/** CORDIC_ARG1_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  First argument data for calculate
+ */
+#define CORDIC_ARG1_DATA    0xFFFFFFFFU
+#define CORDIC_ARG1_DATA_M  (CORDIC_ARG1_DATA_V << CORDIC_ARG1_DATA_S)
+#define CORDIC_ARG1_DATA_V  0xFFFFFFFFU
+#define CORDIC_ARG1_DATA_S  0
+
+/** CORDIC_ARG2_REG register
+ *  Cordic argument 2 config register
+ */
+#define CORDIC_ARG2_REG (DR_REG_CORDIC_BASE + 0x8)
+/** CORDIC_ARG2_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  Second argument data for calculate
+ */
+#define CORDIC_ARG2_DATA    0xFFFFFFFFU
+#define CORDIC_ARG2_DATA_M  (CORDIC_ARG2_DATA_V << CORDIC_ARG2_DATA_S)
+#define CORDIC_ARG2_DATA_V  0xFFFFFFFFU
+#define CORDIC_ARG2_DATA_S  0
+
+/** CORDIC_RES1_REG register
+ *  Cordic result 1 receive register
+ */
+#define CORDIC_RES1_REG (DR_REG_CORDIC_BASE + 0xc)
+/** CORDIC_RES1_DATA : RO; bitpos: [31:0]; default: 0;
+ *  First result data from calculate
+ */
+#define CORDIC_RES1_DATA    0xFFFFFFFFU
+#define CORDIC_RES1_DATA_M  (CORDIC_RES1_DATA_V << CORDIC_RES1_DATA_S)
+#define CORDIC_RES1_DATA_V  0xFFFFFFFFU
+#define CORDIC_RES1_DATA_S  0
+
+/** CORDIC_RES2_REG register
+ *  Cordic result 2 receive register
+ */
+#define CORDIC_RES2_REG (DR_REG_CORDIC_BASE + 0x10)
+/** CORDIC_RES2_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Second result data from calculate
+ */
+#define CORDIC_RES2_DATA    0xFFFFFFFFU
+#define CORDIC_RES2_DATA_M  (CORDIC_RES2_DATA_V << CORDIC_RES2_DATA_S)
+#define CORDIC_RES2_DATA_V  0xFFFFFFFFU
+#define CORDIC_RES2_DATA_S  0
+
+/** CORDIC_IO_INT_ENA_REG register
+ *  Cordic interrupt enable signal configuration register.
+ */
+#define CORDIC_IO_INT_ENA_REG (DR_REG_CORDIC_BASE + 0x28)
+/** CORDIC_CAL_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable CAL_DONE_INT.
+ */
+#define CORDIC_CAL_DONE_INT_ENA    (BIT(0))
+#define CORDIC_CAL_DONE_INT_ENA_M  (CORDIC_CAL_DONE_INT_ENA_V << CORDIC_CAL_DONE_INT_ENA_S)
+#define CORDIC_CAL_DONE_INT_ENA_V  0x00000001U
+#define CORDIC_CAL_DONE_INT_ENA_S  0
+/** CORDIC_DMA_ALL_CAL_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable DMA_ALL_CAL_DONE_INT.
+ */
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA    (BIT(1))
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_M  (CORDIC_DMA_ALL_CAL_DONE_INT_ENA_V << CORDIC_DMA_ALL_CAL_DONE_INT_ENA_S)
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_V  0x00000001U
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ENA_S  1
+/** CORDIC_OUT_AFIFO_WOVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable OUT_AFIFO_WOVF_INT.
+ */
+#define CORDIC_OUT_AFIFO_WOVF_INT_ENA    (BIT(2))
+#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_M  (CORDIC_OUT_AFIFO_WOVF_INT_ENA_V << CORDIC_OUT_AFIFO_WOVF_INT_ENA_S)
+#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_V  0x00000001U
+#define CORDIC_OUT_AFIFO_WOVF_INT_ENA_S  2
+/** CORDIC_IN_AFIFO_RUDF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable IN_AFIFO_RUDF_INT.
+ */
+#define CORDIC_IN_AFIFO_RUDF_INT_ENA    (BIT(3))
+#define CORDIC_IN_AFIFO_RUDF_INT_ENA_M  (CORDIC_IN_AFIFO_RUDF_INT_ENA_V << CORDIC_IN_AFIFO_RUDF_INT_ENA_S)
+#define CORDIC_IN_AFIFO_RUDF_INT_ENA_V  0x00000001U
+#define CORDIC_IN_AFIFO_RUDF_INT_ENA_S  3
+/** CORDIC_ARG_NUM_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable ARG_NUM_ERR_INT.
+ */
+#define CORDIC_ARG_NUM_ERR_INT_ENA    (BIT(4))
+#define CORDIC_ARG_NUM_ERR_INT_ENA_M  (CORDIC_ARG_NUM_ERR_INT_ENA_V << CORDIC_ARG_NUM_ERR_INT_ENA_S)
+#define CORDIC_ARG_NUM_ERR_INT_ENA_V  0x00000001U
+#define CORDIC_ARG_NUM_ERR_INT_ENA_S  4
+
+/** CORDIC_IO_INT_RAW_REG register
+ *  Cordic interrupt raw signal status register.
+ */
+#define CORDIC_IO_INT_RAW_REG (DR_REG_CORDIC_BASE + 0x2c)
+/** CORDIC_CAL_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of CAL_DONE_INT.
+ */
+#define CORDIC_CAL_DONE_INT_RAW    (BIT(0))
+#define CORDIC_CAL_DONE_INT_RAW_M  (CORDIC_CAL_DONE_INT_RAW_V << CORDIC_CAL_DONE_INT_RAW_S)
+#define CORDIC_CAL_DONE_INT_RAW_V  0x00000001U
+#define CORDIC_CAL_DONE_INT_RAW_S  0
+/** CORDIC_DMA_ALL_CAL_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status of DMA_ALL_CAL_DONE_INT.
+ */
+#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW    (BIT(1))
+#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_M  (CORDIC_DMA_ALL_CAL_DONE_INT_RAW_V << CORDIC_DMA_ALL_CAL_DONE_INT_RAW_S)
+#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_V  0x00000001U
+#define CORDIC_DMA_ALL_CAL_DONE_INT_RAW_S  1
+/** CORDIC_OUT_AFIFO_WOVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of OUT_AFIFO_WOVF_INT.
+ */
+#define CORDIC_OUT_AFIFO_WOVF_INT_RAW    (BIT(2))
+#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_M  (CORDIC_OUT_AFIFO_WOVF_INT_RAW_V << CORDIC_OUT_AFIFO_WOVF_INT_RAW_S)
+#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_V  0x00000001U
+#define CORDIC_OUT_AFIFO_WOVF_INT_RAW_S  2
+/** CORDIC_IN_AFIFO_RUDF_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt status of IN_AFIFO_RUDF_INT.
+ */
+#define CORDIC_IN_AFIFO_RUDF_INT_RAW    (BIT(3))
+#define CORDIC_IN_AFIFO_RUDF_INT_RAW_M  (CORDIC_IN_AFIFO_RUDF_INT_RAW_V << CORDIC_IN_AFIFO_RUDF_INT_RAW_S)
+#define CORDIC_IN_AFIFO_RUDF_INT_RAW_V  0x00000001U
+#define CORDIC_IN_AFIFO_RUDF_INT_RAW_S  3
+/** CORDIC_ARG_NUM_ERR_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt status of ARG_NUM_ERR_INT.
+ */
+#define CORDIC_ARG_NUM_ERR_INT_RAW    (BIT(4))
+#define CORDIC_ARG_NUM_ERR_INT_RAW_M  (CORDIC_ARG_NUM_ERR_INT_RAW_V << CORDIC_ARG_NUM_ERR_INT_RAW_S)
+#define CORDIC_ARG_NUM_ERR_INT_RAW_V  0x00000001U
+#define CORDIC_ARG_NUM_ERR_INT_RAW_S  4
+
+/** CORDIC_IO_INT_ST_REG register
+ *  Cordic interrupt signal status register.
+ */
+#define CORDIC_IO_INT_ST_REG (DR_REG_CORDIC_BASE + 0x30)
+/** CORDIC_CAL_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of CAL_DONE_INT.
+ */
+#define CORDIC_CAL_DONE_INT_ST    (BIT(0))
+#define CORDIC_CAL_DONE_INT_ST_M  (CORDIC_CAL_DONE_INT_ST_V << CORDIC_CAL_DONE_INT_ST_S)
+#define CORDIC_CAL_DONE_INT_ST_V  0x00000001U
+#define CORDIC_CAL_DONE_INT_ST_S  0
+/** CORDIC_DMA_ALL_CAL_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of DMA_ALL_CAL_DONE_INT.
+ */
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ST    (BIT(1))
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_M  (CORDIC_DMA_ALL_CAL_DONE_INT_ST_V << CORDIC_DMA_ALL_CAL_DONE_INT_ST_S)
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_V  0x00000001U
+#define CORDIC_DMA_ALL_CAL_DONE_INT_ST_S  1
+/** CORDIC_OUT_AFIFO_WOVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of OUT_AFIFO_WOVF_INT.
+ */
+#define CORDIC_OUT_AFIFO_WOVF_INT_ST    (BIT(2))
+#define CORDIC_OUT_AFIFO_WOVF_INT_ST_M  (CORDIC_OUT_AFIFO_WOVF_INT_ST_V << CORDIC_OUT_AFIFO_WOVF_INT_ST_S)
+#define CORDIC_OUT_AFIFO_WOVF_INT_ST_V  0x00000001U
+#define CORDIC_OUT_AFIFO_WOVF_INT_ST_S  2
+/** CORDIC_IN_AFIFO_RUDF_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of IN_AFIFO_RUDF_INT.
+ */
+#define CORDIC_IN_AFIFO_RUDF_INT_ST    (BIT(3))
+#define CORDIC_IN_AFIFO_RUDF_INT_ST_M  (CORDIC_IN_AFIFO_RUDF_INT_ST_V << CORDIC_IN_AFIFO_RUDF_INT_ST_S)
+#define CORDIC_IN_AFIFO_RUDF_INT_ST_V  0x00000001U
+#define CORDIC_IN_AFIFO_RUDF_INT_ST_S  3
+/** CORDIC_ARG_NUM_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of ARG_NUM_ERR_INT.
+ */
+#define CORDIC_ARG_NUM_ERR_INT_ST    (BIT(4))
+#define CORDIC_ARG_NUM_ERR_INT_ST_M  (CORDIC_ARG_NUM_ERR_INT_ST_V << CORDIC_ARG_NUM_ERR_INT_ST_S)
+#define CORDIC_ARG_NUM_ERR_INT_ST_V  0x00000001U
+#define CORDIC_ARG_NUM_ERR_INT_ST_S  4
+
+/** CORDIC_IO_INT_CLR_REG register
+ *  Cordic interrupt  clear signal configuration register.
+ */
+#define CORDIC_IO_INT_CLR_REG (DR_REG_CORDIC_BASE + 0x34)
+/** CORDIC_CAL_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear CAL_DONE_INT.
+ */
+#define CORDIC_CAL_DONE_INT_CLR    (BIT(0))
+#define CORDIC_CAL_DONE_INT_CLR_M  (CORDIC_CAL_DONE_INT_CLR_V << CORDIC_CAL_DONE_INT_CLR_S)
+#define CORDIC_CAL_DONE_INT_CLR_V  0x00000001U
+#define CORDIC_CAL_DONE_INT_CLR_S  0
+/** CORDIC_DMA_ALL_CAL_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear DMA_ALL_CAL_DONE_INT.
+ */
+#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR    (BIT(1))
+#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_M  (CORDIC_DMA_ALL_CAL_DONE_INT_CLR_V << CORDIC_DMA_ALL_CAL_DONE_INT_CLR_S)
+#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_V  0x00000001U
+#define CORDIC_DMA_ALL_CAL_DONE_INT_CLR_S  1
+/** CORDIC_OUT_AFIFO_WOVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear OUT_AFIFO_WOVF_INT.
+ */
+#define CORDIC_OUT_AFIFO_WOVF_INT_CLR    (BIT(2))
+#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_M  (CORDIC_OUT_AFIFO_WOVF_INT_CLR_V << CORDIC_OUT_AFIFO_WOVF_INT_CLR_S)
+#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_V  0x00000001U
+#define CORDIC_OUT_AFIFO_WOVF_INT_CLR_S  2
+/** CORDIC_IN_AFIFO_RUDF_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear IN_AFIFO_RUDF_INT.
+ */
+#define CORDIC_IN_AFIFO_RUDF_INT_CLR    (BIT(3))
+#define CORDIC_IN_AFIFO_RUDF_INT_CLR_M  (CORDIC_IN_AFIFO_RUDF_INT_CLR_V << CORDIC_IN_AFIFO_RUDF_INT_CLR_S)
+#define CORDIC_IN_AFIFO_RUDF_INT_CLR_V  0x00000001U
+#define CORDIC_IN_AFIFO_RUDF_INT_CLR_S  3
+/** CORDIC_ARG_NUM_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear ARG_NUM_ERR_INT.
+ */
+#define CORDIC_ARG_NUM_ERR_INT_CLR    (BIT(4))
+#define CORDIC_ARG_NUM_ERR_INT_CLR_M  (CORDIC_ARG_NUM_ERR_INT_CLR_V << CORDIC_ARG_NUM_ERR_INT_CLR_S)
+#define CORDIC_ARG_NUM_ERR_INT_CLR_V  0x00000001U
+#define CORDIC_ARG_NUM_ERR_INT_CLR_S  4
+
+/** CORDIC_FIFO_CFG_REG register
+ *  Cordic FIFO configuration register.
+ */
+#define CORDIC_FIFO_CFG_REG (DR_REG_CORDIC_BASE + 0x38)
+/** CORDIC_INFIFO_RESET : WT; bitpos: [0]; default: 0;
+ *  infifo_reset_register
+ */
+#define CORDIC_INFIFO_RESET    (BIT(0))
+#define CORDIC_INFIFO_RESET_M  (CORDIC_INFIFO_RESET_V << CORDIC_INFIFO_RESET_S)
+#define CORDIC_INFIFO_RESET_V  0x00000001U
+#define CORDIC_INFIFO_RESET_S  0
+/** CORDIC_OUTFIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  outfifo_reset_register
+ */
+#define CORDIC_OUTFIFO_RESET    (BIT(1))
+#define CORDIC_OUTFIFO_RESET_M  (CORDIC_OUTFIFO_RESET_V << CORDIC_OUTFIFO_RESET_S)
+#define CORDIC_OUTFIFO_RESET_V  0x00000001U
+#define CORDIC_OUTFIFO_RESET_S  1
+
+/** CORDIC_CLK_REG register
+ *  Cordic clk configuration register.
+ */
+#define CORDIC_CLK_REG (DR_REG_CORDIC_BASE + 0x3c)
+/** CORDIC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Force clock on for this register file
+ */
+#define CORDIC_CLK_EN    (BIT(31))
+#define CORDIC_CLK_EN_M  (CORDIC_CLK_EN_V << CORDIC_CLK_EN_S)
+#define CORDIC_CLK_EN_V  0x00000001U
+#define CORDIC_CLK_EN_S  31
+
+/** CORDIC_VERSION_REG register
+ *  Version register.
+ */
+#define CORDIC_VERSION_REG (DR_REG_CORDIC_BASE + 0x40)
+/** CORDIC_DATE : R/W; bitpos: [27:0]; default: 37818960;
+ *  Version of this register file
+ */
+#define CORDIC_DATE    0x0FFFFFFFU
+#define CORDIC_DATE_M  (CORDIC_DATE_V << CORDIC_DATE_S)
+#define CORDIC_DATE_V  0x0FFFFFFFU
+#define CORDIC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cordic_struct.h b/components/soc/esp32s31/register/soc/cordic_struct.h
new file mode 100644
index 00000000000..f49fe434ab1
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cordic_struct.h
@@ -0,0 +1,329 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: CORDIC  Mode Configuration */
+/** Type of csr_cfg register
+ *  Cordic model config register
+ */
+typedef union {
+    struct {
+        /** func : R/W; bitpos: [3:0]; default: 0;
+         *  Used to inicate the type of operation currently being performed
+         */
+        uint32_t func:4;
+        /** press : R/W; bitpos: [7:4]; default: 0;
+         *  Instruct the cordic calculate cycle number
+         */
+        uint32_t press:4;
+        /** scale : R/W; bitpos: [11:8]; default: 0;
+         *  The scaling of Input argument
+         */
+        uint32_t scale:4;
+        uint32_t reserved_12:5;
+        /** work_mode : R/W; bitpos: [18:17]; default: 0;
+         *  Select Cordic Module data transfer Mode,2'd0: reg_in,reg_out, no zero mode, 2'd1:
+         *  dma_in, reg_out, no zero mode, 2'd2: dma_loop, 2'd3: reg_in, reg_out, zero mode
+         */
+        uint32_t work_mode:2;
+        /** res_num : R/W; bitpos: [19]; default: 0;
+         *  Result number
+         */
+        uint32_t res_num:1;
+        /** arg_num : R/W; bitpos: [20]; default: 0;
+         *  Argument number
+         */
+        uint32_t arg_num:1;
+        /** res_size : R/W; bitpos: [21]; default: 0;
+         *  Result Size, 0: q1.15, 1: q1.31
+         */
+        uint32_t res_size:1;
+        /** arg_size : R/W; bitpos: [22]; default: 0;
+         *  Argument Size, 0: q1.15, 1: q1.31
+         */
+        uint32_t arg_size:1;
+        uint32_t reserved_23:6;
+        /** update_flag : R/W/SC; bitpos: [29]; default: 0;
+         *  Used to synchronize register data to the computing core and start calculate
+         */
+        uint32_t update_flag:1;
+        /** res_all_rdy_flag : RO/SS/SC; bitpos: [30]; default: 0;
+         *  Used to indicate whether the operation all result has been stored in the result
+         *  register
+         */
+        uint32_t res_all_rdy_flag:1;
+        /** res_rdy_flag : RO/SS/SC; bitpos: [31]; default: 0;
+         *  Used to indicate whether the operation result has been stored in the result register
+         */
+        uint32_t res_rdy_flag:1;
+    };
+    uint32_t val;
+} cordic_csr_cfg_reg_t;
+
+
+/** Group: CORDIC ARG1 Configuration */
+/** Type of arg1 register
+ *  Cordic argument 1 config register
+ */
+typedef union {
+    struct {
+        /** arg1_data : R/W; bitpos: [31:0]; default: 0;
+         *  First argument data for calculate
+         */
+        uint32_t arg1_data:32;
+    };
+    uint32_t val;
+} cordic_arg1_reg_t;
+
+
+/** Group: CORDIC ARG2 Configuration */
+/** Type of arg2 register
+ *  Cordic argument 2 config register
+ */
+typedef union {
+    struct {
+        /** arg2_data : R/W; bitpos: [31:0]; default: 0;
+         *  Second argument data for calculate
+         */
+        uint32_t arg2_data:32;
+    };
+    uint32_t val;
+} cordic_arg2_reg_t;
+
+
+/** Group: CORDIC RES1 Receive */
+/** Type of res1 register
+ *  Cordic result 1 receive register
+ */
+typedef union {
+    struct {
+        /** res1_data : RO; bitpos: [31:0]; default: 0;
+         *  First result data from calculate
+         */
+        uint32_t res1_data:32;
+    };
+    uint32_t val;
+} cordic_res1_reg_t;
+
+
+/** Group: CORDIC RES2 Receive */
+/** Type of res2 register
+ *  Cordic result 2 receive register
+ */
+typedef union {
+    struct {
+        /** res2_data : RO; bitpos: [31:0]; default: 0;
+         *  Second result data from calculate
+         */
+        uint32_t res2_data:32;
+    };
+    uint32_t val;
+} cordic_res2_reg_t;
+
+
+/** Group: CORDIC Interrupt Configuration and Status */
+/** Type of io_int_ena register
+ *  Cordic interrupt enable signal configuration register.
+ */
+typedef union {
+    struct {
+        /** cal_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable CAL_DONE_INT.
+         */
+        uint32_t cal_done_int_ena:1;
+        /** dma_all_cal_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable DMA_ALL_CAL_DONE_INT.
+         */
+        uint32_t dma_all_cal_done_int_ena:1;
+        /** out_afifo_wovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable OUT_AFIFO_WOVF_INT.
+         */
+        uint32_t out_afifo_wovf_int_ena:1;
+        /** in_afifo_rudf_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable IN_AFIFO_RUDF_INT.
+         */
+        uint32_t in_afifo_rudf_int_ena:1;
+        /** arg_num_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable ARG_NUM_ERR_INT.
+         */
+        uint32_t arg_num_err_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cordic_io_int_ena_reg_t;
+
+/** Type of io_int_raw register
+ *  Cordic interrupt raw signal status register.
+ */
+typedef union {
+    struct {
+        /** cal_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of CAL_DONE_INT.
+         */
+        uint32_t cal_done_int_raw:1;
+        /** dma_all_cal_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status of DMA_ALL_CAL_DONE_INT.
+         */
+        uint32_t dma_all_cal_done_int_raw:1;
+        /** out_afifo_wovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of OUT_AFIFO_WOVF_INT.
+         */
+        uint32_t out_afifo_wovf_int_raw:1;
+        /** in_afifo_rudf_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of IN_AFIFO_RUDF_INT.
+         */
+        uint32_t in_afifo_rudf_int_raw:1;
+        /** arg_num_err_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of ARG_NUM_ERR_INT.
+         */
+        uint32_t arg_num_err_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cordic_io_int_raw_reg_t;
+
+/** Type of io_int_st register
+ *  Cordic interrupt signal status register.
+ */
+typedef union {
+    struct {
+        /** cal_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of CAL_DONE_INT.
+         */
+        uint32_t cal_done_int_st:1;
+        /** dma_all_cal_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of DMA_ALL_CAL_DONE_INT.
+         */
+        uint32_t dma_all_cal_done_int_st:1;
+        /** out_afifo_wovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of OUT_AFIFO_WOVF_INT.
+         */
+        uint32_t out_afifo_wovf_int_st:1;
+        /** in_afifo_rudf_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of IN_AFIFO_RUDF_INT.
+         */
+        uint32_t in_afifo_rudf_int_st:1;
+        /** arg_num_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of ARG_NUM_ERR_INT.
+         */
+        uint32_t arg_num_err_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cordic_io_int_st_reg_t;
+
+/** Type of io_int_clr register
+ *  Cordic interrupt  clear signal configuration register.
+ */
+typedef union {
+    struct {
+        /** cal_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear CAL_DONE_INT.
+         */
+        uint32_t cal_done_int_clr:1;
+        /** dma_all_cal_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear DMA_ALL_CAL_DONE_INT.
+         */
+        uint32_t dma_all_cal_done_int_clr:1;
+        /** out_afifo_wovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear OUT_AFIFO_WOVF_INT.
+         */
+        uint32_t out_afifo_wovf_int_clr:1;
+        /** in_afifo_rudf_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear IN_AFIFO_RUDF_INT.
+         */
+        uint32_t in_afifo_rudf_int_clr:1;
+        /** arg_num_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear ARG_NUM_ERR_INT.
+         */
+        uint32_t arg_num_err_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} cordic_io_int_clr_reg_t;
+
+
+/** Group: CORDIC FIFO Configuration */
+/** Type of fifo_cfg register
+ *  Cordic FIFO configuration register.
+ */
+typedef union {
+    struct {
+        /** infifo_reset : WT; bitpos: [0]; default: 0;
+         *  infifo_reset_register
+         */
+        uint32_t infifo_reset:1;
+        /** outfifo_reset : WT; bitpos: [1]; default: 0;
+         *  outfifo_reset_register
+         */
+        uint32_t outfifo_reset:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cordic_fifo_cfg_reg_t;
+
+
+/** Group: CORDIC Clock Configuration */
+/** Type of clk register
+ *  Cordic clk configuration register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  Force clock on for this register file
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} cordic_clk_reg_t;
+
+
+/** Group: CORDIC Version Register */
+/** Type of version register
+ *  Version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37818960;
+         *  Version of this register file
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cordic_version_reg_t;
+
+
+typedef struct {
+    volatile cordic_csr_cfg_reg_t csr_cfg;
+    volatile cordic_arg1_reg_t arg1;
+    volatile cordic_arg2_reg_t arg2;
+    volatile cordic_res1_reg_t res1;
+    volatile cordic_res2_reg_t res2;
+    uint32_t reserved_014[5];
+    volatile cordic_io_int_ena_reg_t io_int_ena;
+    volatile cordic_io_int_raw_reg_t io_int_raw;
+    volatile cordic_io_int_st_reg_t io_int_st;
+    volatile cordic_io_int_clr_reg_t io_int_clr;
+    volatile cordic_fifo_cfg_reg_t fifo_cfg;
+    volatile cordic_clk_reg_t clk;
+    volatile cordic_version_reg_t version;
+} cordic_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cordic_dev_t) == 0x44, "Invalid size of cordic_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cpu_apm_reg.h b/components/soc/esp32s31/register/soc/cpu_apm_reg.h
new file mode 100644
index 00000000000..da9cad50b92
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cpu_apm_reg.h
@@ -0,0 +1,1584 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** CPU_APM_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0)
+/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
+ *  Configure bit $n (0-7) to enable region $n.
+ *  0: disable
+ *  1: enable
+ */
+#define CPU_APM_REGION_FILTER_EN    0x000000FFU
+#define CPU_APM_REGION_FILTER_EN_M  (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S)
+#define CPU_APM_REGION_FILTER_EN_V  0x000000FFU
+#define CPU_APM_REGION_FILTER_EN_S  0
+
+/** CPU_APM_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4)
+/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION0_ADDR_START_L_M  (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S)
+#define CPU_APM_REGION0_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION0_ADDR_START_L_S  0
+/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION0_ADDR_START_M  (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S)
+#define CPU_APM_REGION0_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION0_ADDR_START_S  13
+/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION0_ADDR_START_H_M  (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S)
+#define CPU_APM_REGION0_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION0_ADDR_START_H_S  29
+
+/** CPU_APM_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x8)
+/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION0_ADDR_END_L_M  (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S)
+#define CPU_APM_REGION0_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION0_ADDR_END_L_S  0
+/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION0_ADDR_END_M  (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S)
+#define CPU_APM_REGION0_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION0_ADDR_END_S  13
+/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 0.
+ */
+#define CPU_APM_REGION0_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION0_ADDR_END_H_M  (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S)
+#define CPU_APM_REGION0_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION0_ADDR_END_H_S  29
+
+/** CPU_APM_REGION0_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc)
+/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 0.
+ */
+#define CPU_APM_REGION0_R0_X    (BIT(0))
+#define CPU_APM_REGION0_R0_X_M  (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S)
+#define CPU_APM_REGION0_R0_X_V  0x00000001U
+#define CPU_APM_REGION0_R0_X_S  0
+/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 0.
+ */
+#define CPU_APM_REGION0_R0_W    (BIT(1))
+#define CPU_APM_REGION0_R0_W_M  (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S)
+#define CPU_APM_REGION0_R0_W_V  0x00000001U
+#define CPU_APM_REGION0_R0_W_S  1
+/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 0.
+ */
+#define CPU_APM_REGION0_R0_R    (BIT(2))
+#define CPU_APM_REGION0_R0_R_M  (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S)
+#define CPU_APM_REGION0_R0_R_V  0x00000001U
+#define CPU_APM_REGION0_R0_R_S  2
+/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 0.
+ */
+#define CPU_APM_REGION0_R1_X    (BIT(4))
+#define CPU_APM_REGION0_R1_X_M  (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S)
+#define CPU_APM_REGION0_R1_X_V  0x00000001U
+#define CPU_APM_REGION0_R1_X_S  4
+/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 0.
+ */
+#define CPU_APM_REGION0_R1_W    (BIT(5))
+#define CPU_APM_REGION0_R1_W_M  (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S)
+#define CPU_APM_REGION0_R1_W_V  0x00000001U
+#define CPU_APM_REGION0_R1_W_S  5
+/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 0.
+ */
+#define CPU_APM_REGION0_R1_R    (BIT(6))
+#define CPU_APM_REGION0_R1_R_M  (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S)
+#define CPU_APM_REGION0_R1_R_V  0x00000001U
+#define CPU_APM_REGION0_R1_R_S  6
+/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 0.
+ */
+#define CPU_APM_REGION0_R2_X    (BIT(8))
+#define CPU_APM_REGION0_R2_X_M  (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S)
+#define CPU_APM_REGION0_R2_X_V  0x00000001U
+#define CPU_APM_REGION0_R2_X_S  8
+/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 0.
+ */
+#define CPU_APM_REGION0_R2_W    (BIT(9))
+#define CPU_APM_REGION0_R2_W_M  (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S)
+#define CPU_APM_REGION0_R2_W_V  0x00000001U
+#define CPU_APM_REGION0_R2_W_S  9
+/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 0.
+ */
+#define CPU_APM_REGION0_R2_R    (BIT(10))
+#define CPU_APM_REGION0_R2_R_M  (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S)
+#define CPU_APM_REGION0_R2_R_V  0x00000001U
+#define CPU_APM_REGION0_R2_R_S  10
+/** CPU_APM_REGION0_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 0.
+ */
+#define CPU_APM_REGION0_TEE_X    (BIT(12))
+#define CPU_APM_REGION0_TEE_X_M  (CPU_APM_REGION0_TEE_X_V << CPU_APM_REGION0_TEE_X_S)
+#define CPU_APM_REGION0_TEE_X_V  0x00000001U
+#define CPU_APM_REGION0_TEE_X_S  12
+/** CPU_APM_REGION0_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 0.
+ */
+#define CPU_APM_REGION0_TEE_W    (BIT(13))
+#define CPU_APM_REGION0_TEE_W_M  (CPU_APM_REGION0_TEE_W_V << CPU_APM_REGION0_TEE_W_S)
+#define CPU_APM_REGION0_TEE_W_V  0x00000001U
+#define CPU_APM_REGION0_TEE_W_S  13
+/** CPU_APM_REGION0_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 0.
+ */
+#define CPU_APM_REGION0_TEE_R    (BIT(14))
+#define CPU_APM_REGION0_TEE_R_M  (CPU_APM_REGION0_TEE_R_V << CPU_APM_REGION0_TEE_R_S)
+#define CPU_APM_REGION0_TEE_R_V  0x00000001U
+#define CPU_APM_REGION0_TEE_R_S  14
+/** CPU_APM_REGION0_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION0_LOCK    (BIT(16))
+#define CPU_APM_REGION0_LOCK_M  (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S)
+#define CPU_APM_REGION0_LOCK_V  0x00000001U
+#define CPU_APM_REGION0_LOCK_S  16
+
+/** CPU_APM_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x10)
+/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION1_ADDR_START_L_M  (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S)
+#define CPU_APM_REGION1_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION1_ADDR_START_L_S  0
+/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION1_ADDR_START_M  (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S)
+#define CPU_APM_REGION1_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION1_ADDR_START_S  13
+/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION1_ADDR_START_H_M  (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S)
+#define CPU_APM_REGION1_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION1_ADDR_START_H_S  29
+
+/** CPU_APM_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x14)
+/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION1_ADDR_END_L_M  (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S)
+#define CPU_APM_REGION1_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION1_ADDR_END_L_S  0
+/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION1_ADDR_END_M  (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S)
+#define CPU_APM_REGION1_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION1_ADDR_END_S  13
+/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 1.
+ */
+#define CPU_APM_REGION1_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION1_ADDR_END_H_M  (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S)
+#define CPU_APM_REGION1_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION1_ADDR_END_H_S  29
+
+/** CPU_APM_REGION1_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18)
+/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 1.
+ */
+#define CPU_APM_REGION1_R0_X    (BIT(0))
+#define CPU_APM_REGION1_R0_X_M  (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S)
+#define CPU_APM_REGION1_R0_X_V  0x00000001U
+#define CPU_APM_REGION1_R0_X_S  0
+/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 1.
+ */
+#define CPU_APM_REGION1_R0_W    (BIT(1))
+#define CPU_APM_REGION1_R0_W_M  (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S)
+#define CPU_APM_REGION1_R0_W_V  0x00000001U
+#define CPU_APM_REGION1_R0_W_S  1
+/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 1.
+ */
+#define CPU_APM_REGION1_R0_R    (BIT(2))
+#define CPU_APM_REGION1_R0_R_M  (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S)
+#define CPU_APM_REGION1_R0_R_V  0x00000001U
+#define CPU_APM_REGION1_R0_R_S  2
+/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 1.
+ */
+#define CPU_APM_REGION1_R1_X    (BIT(4))
+#define CPU_APM_REGION1_R1_X_M  (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S)
+#define CPU_APM_REGION1_R1_X_V  0x00000001U
+#define CPU_APM_REGION1_R1_X_S  4
+/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 1.
+ */
+#define CPU_APM_REGION1_R1_W    (BIT(5))
+#define CPU_APM_REGION1_R1_W_M  (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S)
+#define CPU_APM_REGION1_R1_W_V  0x00000001U
+#define CPU_APM_REGION1_R1_W_S  5
+/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 1.
+ */
+#define CPU_APM_REGION1_R1_R    (BIT(6))
+#define CPU_APM_REGION1_R1_R_M  (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S)
+#define CPU_APM_REGION1_R1_R_V  0x00000001U
+#define CPU_APM_REGION1_R1_R_S  6
+/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 1.
+ */
+#define CPU_APM_REGION1_R2_X    (BIT(8))
+#define CPU_APM_REGION1_R2_X_M  (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S)
+#define CPU_APM_REGION1_R2_X_V  0x00000001U
+#define CPU_APM_REGION1_R2_X_S  8
+/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 1.
+ */
+#define CPU_APM_REGION1_R2_W    (BIT(9))
+#define CPU_APM_REGION1_R2_W_M  (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S)
+#define CPU_APM_REGION1_R2_W_V  0x00000001U
+#define CPU_APM_REGION1_R2_W_S  9
+/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 1.
+ */
+#define CPU_APM_REGION1_R2_R    (BIT(10))
+#define CPU_APM_REGION1_R2_R_M  (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S)
+#define CPU_APM_REGION1_R2_R_V  0x00000001U
+#define CPU_APM_REGION1_R2_R_S  10
+/** CPU_APM_REGION1_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 1.
+ */
+#define CPU_APM_REGION1_TEE_X    (BIT(12))
+#define CPU_APM_REGION1_TEE_X_M  (CPU_APM_REGION1_TEE_X_V << CPU_APM_REGION1_TEE_X_S)
+#define CPU_APM_REGION1_TEE_X_V  0x00000001U
+#define CPU_APM_REGION1_TEE_X_S  12
+/** CPU_APM_REGION1_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 1.
+ */
+#define CPU_APM_REGION1_TEE_W    (BIT(13))
+#define CPU_APM_REGION1_TEE_W_M  (CPU_APM_REGION1_TEE_W_V << CPU_APM_REGION1_TEE_W_S)
+#define CPU_APM_REGION1_TEE_W_V  0x00000001U
+#define CPU_APM_REGION1_TEE_W_S  13
+/** CPU_APM_REGION1_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 1.
+ */
+#define CPU_APM_REGION1_TEE_R    (BIT(14))
+#define CPU_APM_REGION1_TEE_R_M  (CPU_APM_REGION1_TEE_R_V << CPU_APM_REGION1_TEE_R_S)
+#define CPU_APM_REGION1_TEE_R_V  0x00000001U
+#define CPU_APM_REGION1_TEE_R_S  14
+/** CPU_APM_REGION1_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION1_LOCK    (BIT(16))
+#define CPU_APM_REGION1_LOCK_M  (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S)
+#define CPU_APM_REGION1_LOCK_V  0x00000001U
+#define CPU_APM_REGION1_LOCK_S  16
+
+/** CPU_APM_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x1c)
+/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION2_ADDR_START_L_M  (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S)
+#define CPU_APM_REGION2_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION2_ADDR_START_L_S  0
+/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION2_ADDR_START_M  (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S)
+#define CPU_APM_REGION2_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION2_ADDR_START_S  13
+/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION2_ADDR_START_H_M  (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S)
+#define CPU_APM_REGION2_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION2_ADDR_START_H_S  29
+
+/** CPU_APM_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x20)
+/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION2_ADDR_END_L_M  (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S)
+#define CPU_APM_REGION2_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION2_ADDR_END_L_S  0
+/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION2_ADDR_END_M  (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S)
+#define CPU_APM_REGION2_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION2_ADDR_END_S  13
+/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 2.
+ */
+#define CPU_APM_REGION2_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION2_ADDR_END_H_M  (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S)
+#define CPU_APM_REGION2_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION2_ADDR_END_H_S  29
+
+/** CPU_APM_REGION2_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24)
+/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 2.
+ */
+#define CPU_APM_REGION2_R0_X    (BIT(0))
+#define CPU_APM_REGION2_R0_X_M  (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S)
+#define CPU_APM_REGION2_R0_X_V  0x00000001U
+#define CPU_APM_REGION2_R0_X_S  0
+/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 2.
+ */
+#define CPU_APM_REGION2_R0_W    (BIT(1))
+#define CPU_APM_REGION2_R0_W_M  (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S)
+#define CPU_APM_REGION2_R0_W_V  0x00000001U
+#define CPU_APM_REGION2_R0_W_S  1
+/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 2.
+ */
+#define CPU_APM_REGION2_R0_R    (BIT(2))
+#define CPU_APM_REGION2_R0_R_M  (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S)
+#define CPU_APM_REGION2_R0_R_V  0x00000001U
+#define CPU_APM_REGION2_R0_R_S  2
+/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 2.
+ */
+#define CPU_APM_REGION2_R1_X    (BIT(4))
+#define CPU_APM_REGION2_R1_X_M  (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S)
+#define CPU_APM_REGION2_R1_X_V  0x00000001U
+#define CPU_APM_REGION2_R1_X_S  4
+/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 2.
+ */
+#define CPU_APM_REGION2_R1_W    (BIT(5))
+#define CPU_APM_REGION2_R1_W_M  (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S)
+#define CPU_APM_REGION2_R1_W_V  0x00000001U
+#define CPU_APM_REGION2_R1_W_S  5
+/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 2.
+ */
+#define CPU_APM_REGION2_R1_R    (BIT(6))
+#define CPU_APM_REGION2_R1_R_M  (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S)
+#define CPU_APM_REGION2_R1_R_V  0x00000001U
+#define CPU_APM_REGION2_R1_R_S  6
+/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 2.
+ */
+#define CPU_APM_REGION2_R2_X    (BIT(8))
+#define CPU_APM_REGION2_R2_X_M  (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S)
+#define CPU_APM_REGION2_R2_X_V  0x00000001U
+#define CPU_APM_REGION2_R2_X_S  8
+/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 2.
+ */
+#define CPU_APM_REGION2_R2_W    (BIT(9))
+#define CPU_APM_REGION2_R2_W_M  (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S)
+#define CPU_APM_REGION2_R2_W_V  0x00000001U
+#define CPU_APM_REGION2_R2_W_S  9
+/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 2.
+ */
+#define CPU_APM_REGION2_R2_R    (BIT(10))
+#define CPU_APM_REGION2_R2_R_M  (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S)
+#define CPU_APM_REGION2_R2_R_V  0x00000001U
+#define CPU_APM_REGION2_R2_R_S  10
+/** CPU_APM_REGION2_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 2.
+ */
+#define CPU_APM_REGION2_TEE_X    (BIT(12))
+#define CPU_APM_REGION2_TEE_X_M  (CPU_APM_REGION2_TEE_X_V << CPU_APM_REGION2_TEE_X_S)
+#define CPU_APM_REGION2_TEE_X_V  0x00000001U
+#define CPU_APM_REGION2_TEE_X_S  12
+/** CPU_APM_REGION2_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 2.
+ */
+#define CPU_APM_REGION2_TEE_W    (BIT(13))
+#define CPU_APM_REGION2_TEE_W_M  (CPU_APM_REGION2_TEE_W_V << CPU_APM_REGION2_TEE_W_S)
+#define CPU_APM_REGION2_TEE_W_V  0x00000001U
+#define CPU_APM_REGION2_TEE_W_S  13
+/** CPU_APM_REGION2_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 2.
+ */
+#define CPU_APM_REGION2_TEE_R    (BIT(14))
+#define CPU_APM_REGION2_TEE_R_M  (CPU_APM_REGION2_TEE_R_V << CPU_APM_REGION2_TEE_R_S)
+#define CPU_APM_REGION2_TEE_R_V  0x00000001U
+#define CPU_APM_REGION2_TEE_R_S  14
+/** CPU_APM_REGION2_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION2_LOCK    (BIT(16))
+#define CPU_APM_REGION2_LOCK_M  (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S)
+#define CPU_APM_REGION2_LOCK_V  0x00000001U
+#define CPU_APM_REGION2_LOCK_S  16
+
+/** CPU_APM_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x28)
+/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION3_ADDR_START_L_M  (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S)
+#define CPU_APM_REGION3_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION3_ADDR_START_L_S  0
+/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION3_ADDR_START_M  (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S)
+#define CPU_APM_REGION3_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION3_ADDR_START_S  13
+/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION3_ADDR_START_H_M  (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S)
+#define CPU_APM_REGION3_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION3_ADDR_START_H_S  29
+
+/** CPU_APM_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x2c)
+/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION3_ADDR_END_L_M  (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S)
+#define CPU_APM_REGION3_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION3_ADDR_END_L_S  0
+/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION3_ADDR_END_M  (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S)
+#define CPU_APM_REGION3_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION3_ADDR_END_S  13
+/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 3.
+ */
+#define CPU_APM_REGION3_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION3_ADDR_END_H_M  (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S)
+#define CPU_APM_REGION3_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION3_ADDR_END_H_S  29
+
+/** CPU_APM_REGION3_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30)
+/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 3.
+ */
+#define CPU_APM_REGION3_R0_X    (BIT(0))
+#define CPU_APM_REGION3_R0_X_M  (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S)
+#define CPU_APM_REGION3_R0_X_V  0x00000001U
+#define CPU_APM_REGION3_R0_X_S  0
+/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 3.
+ */
+#define CPU_APM_REGION3_R0_W    (BIT(1))
+#define CPU_APM_REGION3_R0_W_M  (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S)
+#define CPU_APM_REGION3_R0_W_V  0x00000001U
+#define CPU_APM_REGION3_R0_W_S  1
+/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 3.
+ */
+#define CPU_APM_REGION3_R0_R    (BIT(2))
+#define CPU_APM_REGION3_R0_R_M  (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S)
+#define CPU_APM_REGION3_R0_R_V  0x00000001U
+#define CPU_APM_REGION3_R0_R_S  2
+/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 3.
+ */
+#define CPU_APM_REGION3_R1_X    (BIT(4))
+#define CPU_APM_REGION3_R1_X_M  (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S)
+#define CPU_APM_REGION3_R1_X_V  0x00000001U
+#define CPU_APM_REGION3_R1_X_S  4
+/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 3.
+ */
+#define CPU_APM_REGION3_R1_W    (BIT(5))
+#define CPU_APM_REGION3_R1_W_M  (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S)
+#define CPU_APM_REGION3_R1_W_V  0x00000001U
+#define CPU_APM_REGION3_R1_W_S  5
+/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 3.
+ */
+#define CPU_APM_REGION3_R1_R    (BIT(6))
+#define CPU_APM_REGION3_R1_R_M  (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S)
+#define CPU_APM_REGION3_R1_R_V  0x00000001U
+#define CPU_APM_REGION3_R1_R_S  6
+/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 3.
+ */
+#define CPU_APM_REGION3_R2_X    (BIT(8))
+#define CPU_APM_REGION3_R2_X_M  (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S)
+#define CPU_APM_REGION3_R2_X_V  0x00000001U
+#define CPU_APM_REGION3_R2_X_S  8
+/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 3.
+ */
+#define CPU_APM_REGION3_R2_W    (BIT(9))
+#define CPU_APM_REGION3_R2_W_M  (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S)
+#define CPU_APM_REGION3_R2_W_V  0x00000001U
+#define CPU_APM_REGION3_R2_W_S  9
+/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 3.
+ */
+#define CPU_APM_REGION3_R2_R    (BIT(10))
+#define CPU_APM_REGION3_R2_R_M  (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S)
+#define CPU_APM_REGION3_R2_R_V  0x00000001U
+#define CPU_APM_REGION3_R2_R_S  10
+/** CPU_APM_REGION3_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 3.
+ */
+#define CPU_APM_REGION3_TEE_X    (BIT(12))
+#define CPU_APM_REGION3_TEE_X_M  (CPU_APM_REGION3_TEE_X_V << CPU_APM_REGION3_TEE_X_S)
+#define CPU_APM_REGION3_TEE_X_V  0x00000001U
+#define CPU_APM_REGION3_TEE_X_S  12
+/** CPU_APM_REGION3_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 3.
+ */
+#define CPU_APM_REGION3_TEE_W    (BIT(13))
+#define CPU_APM_REGION3_TEE_W_M  (CPU_APM_REGION3_TEE_W_V << CPU_APM_REGION3_TEE_W_S)
+#define CPU_APM_REGION3_TEE_W_V  0x00000001U
+#define CPU_APM_REGION3_TEE_W_S  13
+/** CPU_APM_REGION3_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 3.
+ */
+#define CPU_APM_REGION3_TEE_R    (BIT(14))
+#define CPU_APM_REGION3_TEE_R_M  (CPU_APM_REGION3_TEE_R_V << CPU_APM_REGION3_TEE_R_S)
+#define CPU_APM_REGION3_TEE_R_V  0x00000001U
+#define CPU_APM_REGION3_TEE_R_S  14
+/** CPU_APM_REGION3_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION3_LOCK    (BIT(16))
+#define CPU_APM_REGION3_LOCK_M  (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S)
+#define CPU_APM_REGION3_LOCK_V  0x00000001U
+#define CPU_APM_REGION3_LOCK_S  16
+
+/** CPU_APM_REGION4_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x34)
+/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION4_ADDR_START_L_M  (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S)
+#define CPU_APM_REGION4_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION4_ADDR_START_L_S  0
+/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION4_ADDR_START_M  (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S)
+#define CPU_APM_REGION4_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION4_ADDR_START_S  13
+/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION4_ADDR_START_H_M  (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S)
+#define CPU_APM_REGION4_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION4_ADDR_START_H_S  29
+
+/** CPU_APM_REGION4_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x38)
+/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION4_ADDR_END_L_M  (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S)
+#define CPU_APM_REGION4_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION4_ADDR_END_L_S  0
+/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION4_ADDR_END_M  (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S)
+#define CPU_APM_REGION4_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION4_ADDR_END_S  13
+/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 4.
+ */
+#define CPU_APM_REGION4_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION4_ADDR_END_H_M  (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S)
+#define CPU_APM_REGION4_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION4_ADDR_END_H_S  29
+
+/** CPU_APM_REGION4_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c)
+/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 4.
+ */
+#define CPU_APM_REGION4_R0_X    (BIT(0))
+#define CPU_APM_REGION4_R0_X_M  (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S)
+#define CPU_APM_REGION4_R0_X_V  0x00000001U
+#define CPU_APM_REGION4_R0_X_S  0
+/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 4.
+ */
+#define CPU_APM_REGION4_R0_W    (BIT(1))
+#define CPU_APM_REGION4_R0_W_M  (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S)
+#define CPU_APM_REGION4_R0_W_V  0x00000001U
+#define CPU_APM_REGION4_R0_W_S  1
+/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 4.
+ */
+#define CPU_APM_REGION4_R0_R    (BIT(2))
+#define CPU_APM_REGION4_R0_R_M  (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S)
+#define CPU_APM_REGION4_R0_R_V  0x00000001U
+#define CPU_APM_REGION4_R0_R_S  2
+/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 4.
+ */
+#define CPU_APM_REGION4_R1_X    (BIT(4))
+#define CPU_APM_REGION4_R1_X_M  (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S)
+#define CPU_APM_REGION4_R1_X_V  0x00000001U
+#define CPU_APM_REGION4_R1_X_S  4
+/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 4.
+ */
+#define CPU_APM_REGION4_R1_W    (BIT(5))
+#define CPU_APM_REGION4_R1_W_M  (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S)
+#define CPU_APM_REGION4_R1_W_V  0x00000001U
+#define CPU_APM_REGION4_R1_W_S  5
+/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 4.
+ */
+#define CPU_APM_REGION4_R1_R    (BIT(6))
+#define CPU_APM_REGION4_R1_R_M  (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S)
+#define CPU_APM_REGION4_R1_R_V  0x00000001U
+#define CPU_APM_REGION4_R1_R_S  6
+/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 4.
+ */
+#define CPU_APM_REGION4_R2_X    (BIT(8))
+#define CPU_APM_REGION4_R2_X_M  (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S)
+#define CPU_APM_REGION4_R2_X_V  0x00000001U
+#define CPU_APM_REGION4_R2_X_S  8
+/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 4.
+ */
+#define CPU_APM_REGION4_R2_W    (BIT(9))
+#define CPU_APM_REGION4_R2_W_M  (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S)
+#define CPU_APM_REGION4_R2_W_V  0x00000001U
+#define CPU_APM_REGION4_R2_W_S  9
+/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 4.
+ */
+#define CPU_APM_REGION4_R2_R    (BIT(10))
+#define CPU_APM_REGION4_R2_R_M  (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S)
+#define CPU_APM_REGION4_R2_R_V  0x00000001U
+#define CPU_APM_REGION4_R2_R_S  10
+/** CPU_APM_REGION4_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 4.
+ */
+#define CPU_APM_REGION4_TEE_X    (BIT(12))
+#define CPU_APM_REGION4_TEE_X_M  (CPU_APM_REGION4_TEE_X_V << CPU_APM_REGION4_TEE_X_S)
+#define CPU_APM_REGION4_TEE_X_V  0x00000001U
+#define CPU_APM_REGION4_TEE_X_S  12
+/** CPU_APM_REGION4_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 4.
+ */
+#define CPU_APM_REGION4_TEE_W    (BIT(13))
+#define CPU_APM_REGION4_TEE_W_M  (CPU_APM_REGION4_TEE_W_V << CPU_APM_REGION4_TEE_W_S)
+#define CPU_APM_REGION4_TEE_W_V  0x00000001U
+#define CPU_APM_REGION4_TEE_W_S  13
+/** CPU_APM_REGION4_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 4.
+ */
+#define CPU_APM_REGION4_TEE_R    (BIT(14))
+#define CPU_APM_REGION4_TEE_R_M  (CPU_APM_REGION4_TEE_R_V << CPU_APM_REGION4_TEE_R_S)
+#define CPU_APM_REGION4_TEE_R_V  0x00000001U
+#define CPU_APM_REGION4_TEE_R_S  14
+/** CPU_APM_REGION4_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION4_LOCK    (BIT(16))
+#define CPU_APM_REGION4_LOCK_M  (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S)
+#define CPU_APM_REGION4_LOCK_V  0x00000001U
+#define CPU_APM_REGION4_LOCK_S  16
+
+/** CPU_APM_REGION5_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x40)
+/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION5_ADDR_START_L_M  (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S)
+#define CPU_APM_REGION5_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION5_ADDR_START_L_S  0
+/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION5_ADDR_START_M  (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S)
+#define CPU_APM_REGION5_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION5_ADDR_START_S  13
+/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION5_ADDR_START_H_M  (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S)
+#define CPU_APM_REGION5_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION5_ADDR_START_H_S  29
+
+/** CPU_APM_REGION5_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x44)
+/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION5_ADDR_END_L_M  (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S)
+#define CPU_APM_REGION5_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION5_ADDR_END_L_S  0
+/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION5_ADDR_END_M  (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S)
+#define CPU_APM_REGION5_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION5_ADDR_END_S  13
+/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 5.
+ */
+#define CPU_APM_REGION5_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION5_ADDR_END_H_M  (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S)
+#define CPU_APM_REGION5_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION5_ADDR_END_H_S  29
+
+/** CPU_APM_REGION5_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48)
+/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 5.
+ */
+#define CPU_APM_REGION5_R0_X    (BIT(0))
+#define CPU_APM_REGION5_R0_X_M  (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S)
+#define CPU_APM_REGION5_R0_X_V  0x00000001U
+#define CPU_APM_REGION5_R0_X_S  0
+/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 5.
+ */
+#define CPU_APM_REGION5_R0_W    (BIT(1))
+#define CPU_APM_REGION5_R0_W_M  (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S)
+#define CPU_APM_REGION5_R0_W_V  0x00000001U
+#define CPU_APM_REGION5_R0_W_S  1
+/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 5.
+ */
+#define CPU_APM_REGION5_R0_R    (BIT(2))
+#define CPU_APM_REGION5_R0_R_M  (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S)
+#define CPU_APM_REGION5_R0_R_V  0x00000001U
+#define CPU_APM_REGION5_R0_R_S  2
+/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 5.
+ */
+#define CPU_APM_REGION5_R1_X    (BIT(4))
+#define CPU_APM_REGION5_R1_X_M  (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S)
+#define CPU_APM_REGION5_R1_X_V  0x00000001U
+#define CPU_APM_REGION5_R1_X_S  4
+/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 5.
+ */
+#define CPU_APM_REGION5_R1_W    (BIT(5))
+#define CPU_APM_REGION5_R1_W_M  (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S)
+#define CPU_APM_REGION5_R1_W_V  0x00000001U
+#define CPU_APM_REGION5_R1_W_S  5
+/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 5.
+ */
+#define CPU_APM_REGION5_R1_R    (BIT(6))
+#define CPU_APM_REGION5_R1_R_M  (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S)
+#define CPU_APM_REGION5_R1_R_V  0x00000001U
+#define CPU_APM_REGION5_R1_R_S  6
+/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 5.
+ */
+#define CPU_APM_REGION5_R2_X    (BIT(8))
+#define CPU_APM_REGION5_R2_X_M  (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S)
+#define CPU_APM_REGION5_R2_X_V  0x00000001U
+#define CPU_APM_REGION5_R2_X_S  8
+/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 5.
+ */
+#define CPU_APM_REGION5_R2_W    (BIT(9))
+#define CPU_APM_REGION5_R2_W_M  (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S)
+#define CPU_APM_REGION5_R2_W_V  0x00000001U
+#define CPU_APM_REGION5_R2_W_S  9
+/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 5.
+ */
+#define CPU_APM_REGION5_R2_R    (BIT(10))
+#define CPU_APM_REGION5_R2_R_M  (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S)
+#define CPU_APM_REGION5_R2_R_V  0x00000001U
+#define CPU_APM_REGION5_R2_R_S  10
+/** CPU_APM_REGION5_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 5.
+ */
+#define CPU_APM_REGION5_TEE_X    (BIT(12))
+#define CPU_APM_REGION5_TEE_X_M  (CPU_APM_REGION5_TEE_X_V << CPU_APM_REGION5_TEE_X_S)
+#define CPU_APM_REGION5_TEE_X_V  0x00000001U
+#define CPU_APM_REGION5_TEE_X_S  12
+/** CPU_APM_REGION5_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 5.
+ */
+#define CPU_APM_REGION5_TEE_W    (BIT(13))
+#define CPU_APM_REGION5_TEE_W_M  (CPU_APM_REGION5_TEE_W_V << CPU_APM_REGION5_TEE_W_S)
+#define CPU_APM_REGION5_TEE_W_V  0x00000001U
+#define CPU_APM_REGION5_TEE_W_S  13
+/** CPU_APM_REGION5_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 5.
+ */
+#define CPU_APM_REGION5_TEE_R    (BIT(14))
+#define CPU_APM_REGION5_TEE_R_M  (CPU_APM_REGION5_TEE_R_V << CPU_APM_REGION5_TEE_R_S)
+#define CPU_APM_REGION5_TEE_R_V  0x00000001U
+#define CPU_APM_REGION5_TEE_R_S  14
+/** CPU_APM_REGION5_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION5_LOCK    (BIT(16))
+#define CPU_APM_REGION5_LOCK_M  (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S)
+#define CPU_APM_REGION5_LOCK_V  0x00000001U
+#define CPU_APM_REGION5_LOCK_S  16
+
+/** CPU_APM_REGION6_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x4c)
+/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION6_ADDR_START_L_M  (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S)
+#define CPU_APM_REGION6_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION6_ADDR_START_L_S  0
+/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION6_ADDR_START_M  (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S)
+#define CPU_APM_REGION6_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION6_ADDR_START_S  13
+/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION6_ADDR_START_H_M  (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S)
+#define CPU_APM_REGION6_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION6_ADDR_START_H_S  29
+
+/** CPU_APM_REGION6_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x50)
+/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION6_ADDR_END_L_M  (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S)
+#define CPU_APM_REGION6_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION6_ADDR_END_L_S  0
+/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION6_ADDR_END_M  (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S)
+#define CPU_APM_REGION6_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION6_ADDR_END_S  13
+/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 6.
+ */
+#define CPU_APM_REGION6_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION6_ADDR_END_H_M  (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S)
+#define CPU_APM_REGION6_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION6_ADDR_END_H_S  29
+
+/** CPU_APM_REGION6_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54)
+/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 6.
+ */
+#define CPU_APM_REGION6_R0_X    (BIT(0))
+#define CPU_APM_REGION6_R0_X_M  (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S)
+#define CPU_APM_REGION6_R0_X_V  0x00000001U
+#define CPU_APM_REGION6_R0_X_S  0
+/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 6.
+ */
+#define CPU_APM_REGION6_R0_W    (BIT(1))
+#define CPU_APM_REGION6_R0_W_M  (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S)
+#define CPU_APM_REGION6_R0_W_V  0x00000001U
+#define CPU_APM_REGION6_R0_W_S  1
+/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 6.
+ */
+#define CPU_APM_REGION6_R0_R    (BIT(2))
+#define CPU_APM_REGION6_R0_R_M  (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S)
+#define CPU_APM_REGION6_R0_R_V  0x00000001U
+#define CPU_APM_REGION6_R0_R_S  2
+/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 6.
+ */
+#define CPU_APM_REGION6_R1_X    (BIT(4))
+#define CPU_APM_REGION6_R1_X_M  (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S)
+#define CPU_APM_REGION6_R1_X_V  0x00000001U
+#define CPU_APM_REGION6_R1_X_S  4
+/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 6.
+ */
+#define CPU_APM_REGION6_R1_W    (BIT(5))
+#define CPU_APM_REGION6_R1_W_M  (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S)
+#define CPU_APM_REGION6_R1_W_V  0x00000001U
+#define CPU_APM_REGION6_R1_W_S  5
+/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 6.
+ */
+#define CPU_APM_REGION6_R1_R    (BIT(6))
+#define CPU_APM_REGION6_R1_R_M  (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S)
+#define CPU_APM_REGION6_R1_R_V  0x00000001U
+#define CPU_APM_REGION6_R1_R_S  6
+/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 6.
+ */
+#define CPU_APM_REGION6_R2_X    (BIT(8))
+#define CPU_APM_REGION6_R2_X_M  (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S)
+#define CPU_APM_REGION6_R2_X_V  0x00000001U
+#define CPU_APM_REGION6_R2_X_S  8
+/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 6.
+ */
+#define CPU_APM_REGION6_R2_W    (BIT(9))
+#define CPU_APM_REGION6_R2_W_M  (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S)
+#define CPU_APM_REGION6_R2_W_V  0x00000001U
+#define CPU_APM_REGION6_R2_W_S  9
+/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 6.
+ */
+#define CPU_APM_REGION6_R2_R    (BIT(10))
+#define CPU_APM_REGION6_R2_R_M  (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S)
+#define CPU_APM_REGION6_R2_R_V  0x00000001U
+#define CPU_APM_REGION6_R2_R_S  10
+/** CPU_APM_REGION6_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 6.
+ */
+#define CPU_APM_REGION6_TEE_X    (BIT(12))
+#define CPU_APM_REGION6_TEE_X_M  (CPU_APM_REGION6_TEE_X_V << CPU_APM_REGION6_TEE_X_S)
+#define CPU_APM_REGION6_TEE_X_V  0x00000001U
+#define CPU_APM_REGION6_TEE_X_S  12
+/** CPU_APM_REGION6_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 6.
+ */
+#define CPU_APM_REGION6_TEE_W    (BIT(13))
+#define CPU_APM_REGION6_TEE_W_M  (CPU_APM_REGION6_TEE_W_V << CPU_APM_REGION6_TEE_W_S)
+#define CPU_APM_REGION6_TEE_W_V  0x00000001U
+#define CPU_APM_REGION6_TEE_W_S  13
+/** CPU_APM_REGION6_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 6.
+ */
+#define CPU_APM_REGION6_TEE_R    (BIT(14))
+#define CPU_APM_REGION6_TEE_R_M  (CPU_APM_REGION6_TEE_R_V << CPU_APM_REGION6_TEE_R_S)
+#define CPU_APM_REGION6_TEE_R_V  0x00000001U
+#define CPU_APM_REGION6_TEE_R_S  14
+/** CPU_APM_REGION6_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION6_LOCK    (BIT(16))
+#define CPU_APM_REGION6_LOCK_M  (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S)
+#define CPU_APM_REGION6_LOCK_V  0x00000001U
+#define CPU_APM_REGION6_LOCK_S  16
+
+/** CPU_APM_REGION7_ADDR_START_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_BASE + 0x58)
+/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [12:0]; default: 0;
+ *  Low 12 bit, start address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_START_L    0x00001FFFU
+#define CPU_APM_REGION7_ADDR_START_L_M  (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S)
+#define CPU_APM_REGION7_ADDR_START_L_V  0x00001FFFU
+#define CPU_APM_REGION7_ADDR_START_L_S  0
+/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [28:13]; default: 0;
+ *  Configures start address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_START    0x0000FFFFU
+#define CPU_APM_REGION7_ADDR_START_M  (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S)
+#define CPU_APM_REGION7_ADDR_START_V  0x0000FFFFU
+#define CPU_APM_REGION7_ADDR_START_S  13
+/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  start address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_START_H    0x00000007U
+#define CPU_APM_REGION7_ADDR_START_H_M  (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S)
+#define CPU_APM_REGION7_ADDR_START_H_V  0x00000007U
+#define CPU_APM_REGION7_ADDR_START_H_S  29
+
+/** CPU_APM_REGION7_ADDR_END_REG register
+ *  Region address register
+ */
+#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_BASE + 0x5c)
+/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [12:0]; default: 8191;
+ *  Low 12 bit, end address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_END_L    0x00001FFFU
+#define CPU_APM_REGION7_ADDR_END_L_M  (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S)
+#define CPU_APM_REGION7_ADDR_END_L_V  0x00001FFFU
+#define CPU_APM_REGION7_ADDR_END_L_S  0
+/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [28:13]; default: 65535;
+ *  Configures end address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_END    0x0000FFFFU
+#define CPU_APM_REGION7_ADDR_END_M  (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S)
+#define CPU_APM_REGION7_ADDR_END_V  0x0000FFFFU
+#define CPU_APM_REGION7_ADDR_END_S  13
+/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:29]; default: 2;
+ *  High 13 bit,  end address of region 7.
+ */
+#define CPU_APM_REGION7_ADDR_END_H    0x00000007U
+#define CPU_APM_REGION7_ADDR_END_H_M  (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S)
+#define CPU_APM_REGION7_ADDR_END_H_V  0x00000007U
+#define CPU_APM_REGION7_ADDR_END_H_S  29
+
+/** CPU_APM_REGION7_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60)
+/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 7.
+ */
+#define CPU_APM_REGION7_R0_X    (BIT(0))
+#define CPU_APM_REGION7_R0_X_M  (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S)
+#define CPU_APM_REGION7_R0_X_V  0x00000001U
+#define CPU_APM_REGION7_R0_X_S  0
+/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 7.
+ */
+#define CPU_APM_REGION7_R0_W    (BIT(1))
+#define CPU_APM_REGION7_R0_W_M  (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S)
+#define CPU_APM_REGION7_R0_W_V  0x00000001U
+#define CPU_APM_REGION7_R0_W_S  1
+/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 7.
+ */
+#define CPU_APM_REGION7_R0_R    (BIT(2))
+#define CPU_APM_REGION7_R0_R_M  (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S)
+#define CPU_APM_REGION7_R0_R_V  0x00000001U
+#define CPU_APM_REGION7_R0_R_S  2
+/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 7.
+ */
+#define CPU_APM_REGION7_R1_X    (BIT(4))
+#define CPU_APM_REGION7_R1_X_M  (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S)
+#define CPU_APM_REGION7_R1_X_V  0x00000001U
+#define CPU_APM_REGION7_R1_X_S  4
+/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 7.
+ */
+#define CPU_APM_REGION7_R1_W    (BIT(5))
+#define CPU_APM_REGION7_R1_W_M  (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S)
+#define CPU_APM_REGION7_R1_W_V  0x00000001U
+#define CPU_APM_REGION7_R1_W_S  5
+/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 7.
+ */
+#define CPU_APM_REGION7_R1_R    (BIT(6))
+#define CPU_APM_REGION7_R1_R_M  (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S)
+#define CPU_APM_REGION7_R1_R_V  0x00000001U
+#define CPU_APM_REGION7_R1_R_S  6
+/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 7.
+ */
+#define CPU_APM_REGION7_R2_X    (BIT(8))
+#define CPU_APM_REGION7_R2_X_M  (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S)
+#define CPU_APM_REGION7_R2_X_V  0x00000001U
+#define CPU_APM_REGION7_R2_X_S  8
+/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 7.
+ */
+#define CPU_APM_REGION7_R2_W    (BIT(9))
+#define CPU_APM_REGION7_R2_W_M  (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S)
+#define CPU_APM_REGION7_R2_W_V  0x00000001U
+#define CPU_APM_REGION7_R2_W_S  9
+/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 7.
+ */
+#define CPU_APM_REGION7_R2_R    (BIT(10))
+#define CPU_APM_REGION7_R2_R_M  (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S)
+#define CPU_APM_REGION7_R2_R_V  0x00000001U
+#define CPU_APM_REGION7_R2_R_S  10
+/** CPU_APM_REGION7_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 7.
+ */
+#define CPU_APM_REGION7_TEE_X    (BIT(12))
+#define CPU_APM_REGION7_TEE_X_M  (CPU_APM_REGION7_TEE_X_V << CPU_APM_REGION7_TEE_X_S)
+#define CPU_APM_REGION7_TEE_X_V  0x00000001U
+#define CPU_APM_REGION7_TEE_X_S  12
+/** CPU_APM_REGION7_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 7.
+ */
+#define CPU_APM_REGION7_TEE_W    (BIT(13))
+#define CPU_APM_REGION7_TEE_W_M  (CPU_APM_REGION7_TEE_W_V << CPU_APM_REGION7_TEE_W_S)
+#define CPU_APM_REGION7_TEE_W_V  0x00000001U
+#define CPU_APM_REGION7_TEE_W_S  13
+/** CPU_APM_REGION7_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 7.
+ */
+#define CPU_APM_REGION7_TEE_R    (BIT(14))
+#define CPU_APM_REGION7_TEE_R_M  (CPU_APM_REGION7_TEE_R_V << CPU_APM_REGION7_TEE_R_S)
+#define CPU_APM_REGION7_TEE_R_V  0x00000001U
+#define CPU_APM_REGION7_TEE_R_S  14
+/** CPU_APM_REGION7_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define CPU_APM_REGION7_LOCK    (BIT(16))
+#define CPU_APM_REGION7_LOCK_M  (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S)
+#define CPU_APM_REGION7_LOCK_V  0x00000001U
+#define CPU_APM_REGION7_LOCK_S  16
+
+/** CPU_APM_FUNC_CTRL_REG register
+ *  APM function control register
+ */
+#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4)
+/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define CPU_APM_M0_FUNC_EN    (BIT(0))
+#define CPU_APM_M0_FUNC_EN_M  (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S)
+#define CPU_APM_M0_FUNC_EN_V  0x00000001U
+#define CPU_APM_M0_FUNC_EN_S  0
+/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1;
+ *  PMS M1 function enable
+ */
+#define CPU_APM_M1_FUNC_EN    (BIT(1))
+#define CPU_APM_M1_FUNC_EN_M  (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S)
+#define CPU_APM_M1_FUNC_EN_V  0x00000001U
+#define CPU_APM_M1_FUNC_EN_S  1
+/** CPU_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1;
+ *  PMS M2 function enable
+ */
+#define CPU_APM_M2_FUNC_EN    (BIT(2))
+#define CPU_APM_M2_FUNC_EN_M  (CPU_APM_M2_FUNC_EN_V << CPU_APM_M2_FUNC_EN_S)
+#define CPU_APM_M2_FUNC_EN_V  0x00000001U
+#define CPU_APM_M2_FUNC_EN_S  2
+/** CPU_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1;
+ *  PMS M3 function enable
+ */
+#define CPU_APM_M3_FUNC_EN    (BIT(3))
+#define CPU_APM_M3_FUNC_EN_M  (CPU_APM_M3_FUNC_EN_V << CPU_APM_M3_FUNC_EN_S)
+#define CPU_APM_M3_FUNC_EN_V  0x00000001U
+#define CPU_APM_M3_FUNC_EN_S  3
+
+/** CPU_APM_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8)
+/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define CPU_APM_M0_EXCEPTION_STATUS    0x00000003U
+#define CPU_APM_M0_EXCEPTION_STATUS_M  (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S)
+#define CPU_APM_M0_EXCEPTION_STATUS_V  0x00000003U
+#define CPU_APM_M0_EXCEPTION_STATUS_S  0
+
+/** CPU_APM_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc)
+/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define CPU_APM_M0_EXCEPTION_STATUS_CLR    (BIT(0))
+#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M  (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S)
+#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S  0
+
+/** CPU_APM_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0)
+/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define CPU_APM_M0_EXCEPTION_REGION    0x000000FFU
+#define CPU_APM_M0_EXCEPTION_REGION_M  (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S)
+#define CPU_APM_M0_EXCEPTION_REGION_V  0x000000FFU
+#define CPU_APM_M0_EXCEPTION_REGION_S  0
+/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define CPU_APM_M0_EXCEPTION_MODE    0x00000003U
+#define CPU_APM_M0_EXCEPTION_MODE_M  (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S)
+#define CPU_APM_M0_EXCEPTION_MODE_V  0x00000003U
+#define CPU_APM_M0_EXCEPTION_MODE_S  16
+/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define CPU_APM_M0_EXCEPTION_ID    0x0000001FU
+#define CPU_APM_M0_EXCEPTION_ID_M  (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S)
+#define CPU_APM_M0_EXCEPTION_ID_V  0x0000001FU
+#define CPU_APM_M0_EXCEPTION_ID_S  18
+
+/** CPU_APM_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4)
+/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define CPU_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define CPU_APM_M0_EXCEPTION_ADDR_M  (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S)
+#define CPU_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define CPU_APM_M0_EXCEPTION_ADDR_S  0
+
+/** CPU_APM_M1_STATUS_REG register
+ *  M1 status register
+ */
+#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8)
+/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define CPU_APM_M1_EXCEPTION_STATUS    0x00000003U
+#define CPU_APM_M1_EXCEPTION_STATUS_M  (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S)
+#define CPU_APM_M1_EXCEPTION_STATUS_V  0x00000003U
+#define CPU_APM_M1_EXCEPTION_STATUS_S  0
+
+/** CPU_APM_M1_STATUS_CLR_REG register
+ *  M1 status clear register
+ */
+#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc)
+/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define CPU_APM_M1_EXCEPTION_STATUS_CLR    (BIT(0))
+#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M  (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S)
+#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S  0
+
+/** CPU_APM_M1_EXCEPTION_INFO0_REG register
+ *  M1 exception_info0 register
+ */
+#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0)
+/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define CPU_APM_M1_EXCEPTION_REGION    0x000000FFU
+#define CPU_APM_M1_EXCEPTION_REGION_M  (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S)
+#define CPU_APM_M1_EXCEPTION_REGION_V  0x000000FFU
+#define CPU_APM_M1_EXCEPTION_REGION_S  0
+/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define CPU_APM_M1_EXCEPTION_MODE    0x00000003U
+#define CPU_APM_M1_EXCEPTION_MODE_M  (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S)
+#define CPU_APM_M1_EXCEPTION_MODE_V  0x00000003U
+#define CPU_APM_M1_EXCEPTION_MODE_S  16
+/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define CPU_APM_M1_EXCEPTION_ID    0x0000001FU
+#define CPU_APM_M1_EXCEPTION_ID_M  (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S)
+#define CPU_APM_M1_EXCEPTION_ID_V  0x0000001FU
+#define CPU_APM_M1_EXCEPTION_ID_S  18
+
+/** CPU_APM_M1_EXCEPTION_INFO1_REG register
+ *  M1 exception_info1 register
+ */
+#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4)
+/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define CPU_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
+#define CPU_APM_M1_EXCEPTION_ADDR_M  (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S)
+#define CPU_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define CPU_APM_M1_EXCEPTION_ADDR_S  0
+
+/** CPU_APM_M2_STATUS_REG register
+ *  M2 status register
+ */
+#define CPU_APM_M2_STATUS_REG (DR_REG_CPU_APM_BASE + 0xe8)
+/** CPU_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define CPU_APM_M2_EXCEPTION_STATUS    0x00000003U
+#define CPU_APM_M2_EXCEPTION_STATUS_M  (CPU_APM_M2_EXCEPTION_STATUS_V << CPU_APM_M2_EXCEPTION_STATUS_S)
+#define CPU_APM_M2_EXCEPTION_STATUS_V  0x00000003U
+#define CPU_APM_M2_EXCEPTION_STATUS_S  0
+
+/** CPU_APM_M2_STATUS_CLR_REG register
+ *  M2 status clear register
+ */
+#define CPU_APM_M2_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xec)
+/** CPU_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define CPU_APM_M2_EXCEPTION_STATUS_CLR    (BIT(0))
+#define CPU_APM_M2_EXCEPTION_STATUS_CLR_M  (CPU_APM_M2_EXCEPTION_STATUS_CLR_V << CPU_APM_M2_EXCEPTION_STATUS_CLR_S)
+#define CPU_APM_M2_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define CPU_APM_M2_EXCEPTION_STATUS_CLR_S  0
+
+/** CPU_APM_M2_EXCEPTION_INFO0_REG register
+ *  M2 exception_info0 register
+ */
+#define CPU_APM_M2_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xf0)
+/** CPU_APM_M2_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define CPU_APM_M2_EXCEPTION_REGION    0x000000FFU
+#define CPU_APM_M2_EXCEPTION_REGION_M  (CPU_APM_M2_EXCEPTION_REGION_V << CPU_APM_M2_EXCEPTION_REGION_S)
+#define CPU_APM_M2_EXCEPTION_REGION_V  0x000000FFU
+#define CPU_APM_M2_EXCEPTION_REGION_S  0
+/** CPU_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define CPU_APM_M2_EXCEPTION_MODE    0x00000003U
+#define CPU_APM_M2_EXCEPTION_MODE_M  (CPU_APM_M2_EXCEPTION_MODE_V << CPU_APM_M2_EXCEPTION_MODE_S)
+#define CPU_APM_M2_EXCEPTION_MODE_V  0x00000003U
+#define CPU_APM_M2_EXCEPTION_MODE_S  16
+/** CPU_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define CPU_APM_M2_EXCEPTION_ID    0x0000001FU
+#define CPU_APM_M2_EXCEPTION_ID_M  (CPU_APM_M2_EXCEPTION_ID_V << CPU_APM_M2_EXCEPTION_ID_S)
+#define CPU_APM_M2_EXCEPTION_ID_V  0x0000001FU
+#define CPU_APM_M2_EXCEPTION_ID_S  18
+
+/** CPU_APM_M2_EXCEPTION_INFO1_REG register
+ *  M2 exception_info1 register
+ */
+#define CPU_APM_M2_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xf4)
+/** CPU_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define CPU_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
+#define CPU_APM_M2_EXCEPTION_ADDR_M  (CPU_APM_M2_EXCEPTION_ADDR_V << CPU_APM_M2_EXCEPTION_ADDR_S)
+#define CPU_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define CPU_APM_M2_EXCEPTION_ADDR_S  0
+
+/** CPU_APM_M3_STATUS_REG register
+ *  M3 status register
+ */
+#define CPU_APM_M3_STATUS_REG (DR_REG_CPU_APM_BASE + 0xf8)
+/** CPU_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define CPU_APM_M3_EXCEPTION_STATUS    0x00000003U
+#define CPU_APM_M3_EXCEPTION_STATUS_M  (CPU_APM_M3_EXCEPTION_STATUS_V << CPU_APM_M3_EXCEPTION_STATUS_S)
+#define CPU_APM_M3_EXCEPTION_STATUS_V  0x00000003U
+#define CPU_APM_M3_EXCEPTION_STATUS_S  0
+
+/** CPU_APM_M3_STATUS_CLR_REG register
+ *  M3 status clear register
+ */
+#define CPU_APM_M3_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xfc)
+/** CPU_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define CPU_APM_M3_EXCEPTION_STATUS_CLR    (BIT(0))
+#define CPU_APM_M3_EXCEPTION_STATUS_CLR_M  (CPU_APM_M3_EXCEPTION_STATUS_CLR_V << CPU_APM_M3_EXCEPTION_STATUS_CLR_S)
+#define CPU_APM_M3_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define CPU_APM_M3_EXCEPTION_STATUS_CLR_S  0
+
+/** CPU_APM_M3_EXCEPTION_INFO0_REG register
+ *  M3 exception_info0 register
+ */
+#define CPU_APM_M3_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0x100)
+/** CPU_APM_M3_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define CPU_APM_M3_EXCEPTION_REGION    0x000000FFU
+#define CPU_APM_M3_EXCEPTION_REGION_M  (CPU_APM_M3_EXCEPTION_REGION_V << CPU_APM_M3_EXCEPTION_REGION_S)
+#define CPU_APM_M3_EXCEPTION_REGION_V  0x000000FFU
+#define CPU_APM_M3_EXCEPTION_REGION_S  0
+/** CPU_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define CPU_APM_M3_EXCEPTION_MODE    0x00000003U
+#define CPU_APM_M3_EXCEPTION_MODE_M  (CPU_APM_M3_EXCEPTION_MODE_V << CPU_APM_M3_EXCEPTION_MODE_S)
+#define CPU_APM_M3_EXCEPTION_MODE_V  0x00000003U
+#define CPU_APM_M3_EXCEPTION_MODE_S  16
+/** CPU_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define CPU_APM_M3_EXCEPTION_ID    0x0000001FU
+#define CPU_APM_M3_EXCEPTION_ID_M  (CPU_APM_M3_EXCEPTION_ID_V << CPU_APM_M3_EXCEPTION_ID_S)
+#define CPU_APM_M3_EXCEPTION_ID_V  0x0000001FU
+#define CPU_APM_M3_EXCEPTION_ID_S  18
+
+/** CPU_APM_M3_EXCEPTION_INFO1_REG register
+ *  M3 exception_info1 register
+ */
+#define CPU_APM_M3_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0x104)
+/** CPU_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define CPU_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
+#define CPU_APM_M3_EXCEPTION_ADDR_M  (CPU_APM_M3_EXCEPTION_ADDR_V << CPU_APM_M3_EXCEPTION_ADDR_S)
+#define CPU_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define CPU_APM_M3_EXCEPTION_ADDR_S  0
+
+/** CPU_APM_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118)
+/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures to enable APM M0 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define CPU_APM_M0_APM_INT_EN    (BIT(0))
+#define CPU_APM_M0_APM_INT_EN_M  (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S)
+#define CPU_APM_M0_APM_INT_EN_V  0x00000001U
+#define CPU_APM_M0_APM_INT_EN_S  0
+/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures to enable APM M1 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define CPU_APM_M1_APM_INT_EN    (BIT(1))
+#define CPU_APM_M1_APM_INT_EN_M  (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S)
+#define CPU_APM_M1_APM_INT_EN_V  0x00000001U
+#define CPU_APM_M1_APM_INT_EN_S  1
+/** CPU_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures to enable APM M2 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define CPU_APM_M2_APM_INT_EN    (BIT(2))
+#define CPU_APM_M2_APM_INT_EN_M  (CPU_APM_M2_APM_INT_EN_V << CPU_APM_M2_APM_INT_EN_S)
+#define CPU_APM_M2_APM_INT_EN_V  0x00000001U
+#define CPU_APM_M2_APM_INT_EN_S  2
+/** CPU_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures to enable APM M3 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define CPU_APM_M3_APM_INT_EN    (BIT(3))
+#define CPU_APM_M3_APM_INT_EN_M  (CPU_APM_M3_APM_INT_EN_V << CPU_APM_M3_APM_INT_EN_S)
+#define CPU_APM_M3_APM_INT_EN_V  0x00000001U
+#define CPU_APM_M3_APM_INT_EN_S  3
+
+/** CPU_APM_BUS_ERR_CONF_REG register
+ *  APM interrupt enable register
+ */
+#define CPU_APM_BUS_ERR_CONF_REG (DR_REG_CPU_APM_BASE + 0x11c)
+/** CPU_APM_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether return error response to cpu when access blocked
+ *  0: disable error response
+ *  1: enable error response
+ */
+#define CPU_APM_BUS_ERR_RESP_EN    (BIT(0))
+#define CPU_APM_BUS_ERR_RESP_EN_M  (CPU_APM_BUS_ERR_RESP_EN_V << CPU_APM_BUS_ERR_RESP_EN_S)
+#define CPU_APM_BUS_ERR_RESP_EN_V  0x00000001U
+#define CPU_APM_BUS_ERR_RESP_EN_S  0
+
+/** CPU_APM_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x3f8)
+/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: enable automatic clock gating
+ *  1: keep the clock always on
+ */
+#define CPU_APM_CLK_EN    (BIT(0))
+#define CPU_APM_CLK_EN_M  (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S)
+#define CPU_APM_CLK_EN_V  0x00000001U
+#define CPU_APM_CLK_EN_S  0
+
+/** CPU_APM_DATE_REG register
+ *  Version control register
+ */
+#define CPU_APM_DATE_REG (DR_REG_CPU_APM_BASE + 0x3fc)
+/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 38822496;
+ *  Version control register.
+ */
+#define CPU_APM_DATE    0x0FFFFFFFU
+#define CPU_APM_DATE_M  (CPU_APM_DATE_V << CPU_APM_DATE_S)
+#define CPU_APM_DATE_V  0x0FFFFFFFU
+#define CPU_APM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/cpu_apm_struct.h b/components/soc/esp32s31/register/soc/cpu_apm_struct.h
new file mode 100644
index 00000000000..904671354a1
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/cpu_apm_struct.h
@@ -0,0 +1,612 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [7:0]; default: 1;
+         *  Configure bit $n (0-7) to enable region $n.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t region_filter_en:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} cpu_apm_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of regionn_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_start_l : HRO; bitpos: [12:0]; default: 0;
+         *  Low 12 bit, start address of region n.
+         */
+        uint32_t regionn_addr_start_l:13;
+        /** regionn_addr_start : R/W; bitpos: [28:13]; default: 0;
+         *  Configures start address of region n.
+         */
+        uint32_t regionn_addr_start:16;
+        /** regionn_addr_start_h : HRO; bitpos: [31:29]; default: 2;
+         *  High 13 bit,  start address of region n.
+         */
+        uint32_t regionn_addr_start_h:3;
+    };
+    uint32_t val;
+} cpu_apm_regionn_addr_start_reg_t;
+
+/** Type of regionn_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_end_l : HRO; bitpos: [12:0]; default: 8191;
+         *  Low 12 bit, end address of region n.
+         */
+        uint32_t regionn_addr_end_l:13;
+        /** regionn_addr_end : R/W; bitpos: [28:13]; default: 65535;
+         *  Configures end address of region n.
+         */
+        uint32_t regionn_addr_end:16;
+        /** regionn_addr_end_h : HRO; bitpos: [31:29]; default: 2;
+         *  High 13 bit,  end address of region n.
+         */
+        uint32_t regionn_addr_end_h:3;
+    };
+    uint32_t val;
+} cpu_apm_regionn_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of regionn_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** regionn_r0_x : R/W; bitpos: [0]; default: 0;
+         *  Configures the execution authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_x:1;
+        /** regionn_r0_w : R/W; bitpos: [1]; default: 0;
+         *  Configures the write authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_w:1;
+        /** regionn_r0_r : R/W; bitpos: [2]; default: 0;
+         *  Configures the read authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_r:1;
+        uint32_t reserved_3:1;
+        /** regionn_r1_x : R/W; bitpos: [4]; default: 0;
+         *  Configures the execution authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_x:1;
+        /** regionn_r1_w : R/W; bitpos: [5]; default: 0;
+         *  Configures the write authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_w:1;
+        /** regionn_r1_r : R/W; bitpos: [6]; default: 0;
+         *  Configures the read authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_r:1;
+        uint32_t reserved_7:1;
+        /** regionn_r2_x : R/W; bitpos: [8]; default: 0;
+         *  Configures the execution authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_x:1;
+        /** regionn_r2_w : R/W; bitpos: [9]; default: 0;
+         *  Configures the write authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_w:1;
+        /** regionn_r2_r : R/W; bitpos: [10]; default: 0;
+         *  Configures the read authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_r:1;
+        uint32_t reserved_11:1;
+        /** regionn_tee_x : R/W; bitpos: [12]; default: 1;
+         *  Configures the execution authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_x:1;
+        /** regionn_tee_w : R/W; bitpos: [13]; default: 1;
+         *  Configures the write authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_w:1;
+        /** regionn_tee_r : R/W; bitpos: [14]; default: 1;
+         *  Configures the read authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_r:1;
+        uint32_t reserved_15:1;
+        /** regionn_lock : R/W; bitpos: [16]; default: 0;
+         *  Set 1 to lock region0 configuration
+         */
+        uint32_t regionn_lock:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} cpu_apm_regionn_attr_reg_t;
+
+
+/** Group: function control register */
+/** Type of func_ctrl register
+ *  APM function control register
+ */
+typedef union {
+    struct {
+        /** m0_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_func_en:1;
+        /** m1_func_en : R/W; bitpos: [1]; default: 1;
+         *  PMS M1 function enable
+         */
+        uint32_t m1_func_en:1;
+        /** m2_func_en : R/W; bitpos: [2]; default: 1;
+         *  PMS M2 function enable
+         */
+        uint32_t m2_func_en:1;
+        /** m3_func_en : R/W; bitpos: [3]; default: 1;
+         *  PMS M3 function enable
+         */
+        uint32_t m3_func_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cpu_apm_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cpu_apm_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m0_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m0_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m0_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cpu_apm_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} cpu_apm_m0_exception_info1_reg_t;
+
+
+/** Group: M1 status register */
+/** Type of m1_status register
+ *  M1 status register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m1_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cpu_apm_m1_status_reg_t;
+
+
+/** Group: M1 status clear register */
+/** Type of m1_status_clr register
+ *  M1 status clear register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m1_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_m1_status_clr_reg_t;
+
+
+/** Group: M1 exception_info0 register */
+/** Type of m1_exception_info0 register
+ *  M1 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m1_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m1_exception_mode:2;
+        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m1_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cpu_apm_m1_exception_info0_reg_t;
+
+
+/** Group: M1 exception_info1 register */
+/** Type of m1_exception_info1 register
+ *  M1 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m1_exception_addr:32;
+    };
+    uint32_t val;
+} cpu_apm_m1_exception_info1_reg_t;
+
+
+/** Group: M2 status register */
+/** Type of m2_status register
+ *  M2 status register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m2_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cpu_apm_m2_status_reg_t;
+
+
+/** Group: M2 status clear register */
+/** Type of m2_status_clr register
+ *  M2 status clear register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m2_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_m2_status_clr_reg_t;
+
+
+/** Group: M2 exception_info0 register */
+/** Type of m2_exception_info0 register
+ *  M2 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m2_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m2_exception_mode:2;
+        /** m2_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m2_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cpu_apm_m2_exception_info0_reg_t;
+
+
+/** Group: M2 exception_info1 register */
+/** Type of m2_exception_info1 register
+ *  M2 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m2_exception_addr:32;
+    };
+    uint32_t val;
+} cpu_apm_m2_exception_info1_reg_t;
+
+
+/** Group: M3 status register */
+/** Type of m3_status register
+ *  M3 status register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m3_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} cpu_apm_m3_status_reg_t;
+
+
+/** Group: M3 status clear register */
+/** Type of m3_status_clr register
+ *  M3 status clear register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m3_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_m3_status_clr_reg_t;
+
+
+/** Group: M3 exception_info0 register */
+/** Type of m3_exception_info0 register
+ *  M3 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m3_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m3_exception_mode:2;
+        /** m3_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m3_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} cpu_apm_m3_exception_info0_reg_t;
+
+
+/** Group: M3 exception_info1 register */
+/** Type of m3_exception_info1 register
+ *  M3 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m3_exception_addr:32;
+    };
+    uint32_t val;
+} cpu_apm_m3_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  Configures to enable APM M0 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m0_apm_int_en:1;
+        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
+         *  Configures to enable APM M1 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m1_apm_int_en:1;
+        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
+         *  Configures to enable APM M2 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m2_apm_int_en:1;
+        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
+         *  Configures to enable APM M3 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m3_apm_int_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} cpu_apm_int_en_reg_t;
+
+/** Type of bus_err_conf register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether return error response to cpu when access blocked
+         *  0: disable error response
+         *  1: enable error response
+         */
+        uint32_t bus_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_bus_err_conf_reg_t;
+
+
+/** Group: Clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: enable automatic clock gating
+         *  1: keep the clock always on
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} cpu_apm_clock_gate_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38822496;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} cpu_apm_date_reg_t;
+
+
+typedef struct {
+    volatile cpu_apm_region_filter_en_reg_t region_filter_en;
+    volatile cpu_apm_regionn_addr_start_reg_t region0_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region0_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region0_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region1_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region1_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region1_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region2_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region2_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region2_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region3_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region3_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region3_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region4_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region4_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region4_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region5_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region5_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region5_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region6_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region6_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region6_attr;
+    volatile cpu_apm_regionn_addr_start_reg_t region7_addr_start;
+    volatile cpu_apm_regionn_addr_end_reg_t region7_addr_end;
+    volatile cpu_apm_regionn_attr_reg_t region7_attr;
+    uint32_t reserved_064[24];
+    volatile cpu_apm_func_ctrl_reg_t func_ctrl;
+    volatile cpu_apm_m0_status_reg_t m0_status;
+    volatile cpu_apm_m0_status_clr_reg_t m0_status_clr;
+    volatile cpu_apm_m0_exception_info0_reg_t m0_exception_info0;
+    volatile cpu_apm_m0_exception_info1_reg_t m0_exception_info1;
+    volatile cpu_apm_m1_status_reg_t m1_status;
+    volatile cpu_apm_m1_status_clr_reg_t m1_status_clr;
+    volatile cpu_apm_m1_exception_info0_reg_t m1_exception_info0;
+    volatile cpu_apm_m1_exception_info1_reg_t m1_exception_info1;
+    volatile cpu_apm_m2_status_reg_t m2_status;
+    volatile cpu_apm_m2_status_clr_reg_t m2_status_clr;
+    volatile cpu_apm_m2_exception_info0_reg_t m2_exception_info0;
+    volatile cpu_apm_m2_exception_info1_reg_t m2_exception_info1;
+    volatile cpu_apm_m3_status_reg_t m3_status;
+    volatile cpu_apm_m3_status_clr_reg_t m3_status_clr;
+    volatile cpu_apm_m3_exception_info0_reg_t m3_exception_info0;
+    volatile cpu_apm_m3_exception_info1_reg_t m3_exception_info1;
+    uint32_t reserved_108[4];
+    volatile cpu_apm_int_en_reg_t int_en;
+    volatile cpu_apm_bus_err_conf_reg_t bus_err_conf;
+    uint32_t reserved_120[182];
+    volatile cpu_apm_clock_gate_reg_t clock_gate;
+    volatile cpu_apm_date_reg_t date;
+} cpu_apm_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(cpu_apm_dev_t) == 0x400, "Invalid size of cpu_apm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/dac_reg.h b/components/soc/esp32s31/register/soc/dac_reg.h
new file mode 100644
index 00000000000..f38b22a595b
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/dac_reg.h
@@ -0,0 +1,466 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DAC_PAD_CFG_REG register
+ *  configure dac pad register
+ */
+#define DAC_PAD_CFG_REG (DR_REG_DAC_BASE + 0x0)
+/** DAC_HS_MODE_PAD_0 : R/W; bitpos: [0]; default: 0;
+ *  1 to let DAC PAD 0 enter High speed mode
+ */
+#define DAC_HS_MODE_PAD_0    (BIT(0))
+#define DAC_HS_MODE_PAD_0_M  (DAC_HS_MODE_PAD_0_V << DAC_HS_MODE_PAD_0_S)
+#define DAC_HS_MODE_PAD_0_V  0x00000001U
+#define DAC_HS_MODE_PAD_0_S  0
+/** DAC_XPD_PAD_0 : R/W; bitpos: [1]; default: 0;
+ *  1 to power on DAC PAD 0
+ */
+#define DAC_XPD_PAD_0    (BIT(1))
+#define DAC_XPD_PAD_0_M  (DAC_XPD_PAD_0_V << DAC_XPD_PAD_0_S)
+#define DAC_XPD_PAD_0_V  0x00000001U
+#define DAC_XPD_PAD_0_S  1
+/** DAC_EN_ADC_MUX_PAD_0 : R/W; bitpos: [2]; default: 0;
+ *  1 to enable adc mux for DAC PAD 0
+ */
+#define DAC_EN_ADC_MUX_PAD_0    (BIT(2))
+#define DAC_EN_ADC_MUX_PAD_0_M  (DAC_EN_ADC_MUX_PAD_0_V << DAC_EN_ADC_MUX_PAD_0_S)
+#define DAC_EN_ADC_MUX_PAD_0_V  0x00000001U
+#define DAC_EN_ADC_MUX_PAD_0_S  2
+/** DAC_DSAMP_LS_PAD_0 : R/W; bitpos: [3]; default: 0;
+ *  1 to start sample and hold mode for DAC PAD 0
+ */
+#define DAC_DSAMP_LS_PAD_0    (BIT(3))
+#define DAC_DSAMP_LS_PAD_0_M  (DAC_DSAMP_LS_PAD_0_V << DAC_DSAMP_LS_PAD_0_S)
+#define DAC_DSAMP_LS_PAD_0_V  0x00000001U
+#define DAC_DSAMP_LS_PAD_0_S  3
+/** DAC_DCAL_LS_PAD_0 : R/W; bitpos: [4]; default: 0;
+ *  1 to Calibrate the buffer of DAC PAD 0 (DBUF of pad 1 must be 1 during this
+ *  operation)
+ */
+#define DAC_DCAL_LS_PAD_0    (BIT(4))
+#define DAC_DCAL_LS_PAD_0_M  (DAC_DCAL_LS_PAD_0_V << DAC_DCAL_LS_PAD_0_S)
+#define DAC_DCAL_LS_PAD_0_V  0x00000001U
+#define DAC_DCAL_LS_PAD_0_S  4
+/** DAC_DBUF_LS_PAD_0 : R/W; bitpos: [5]; default: 0;
+ *  1 to turn on the buffer of DAC PAD 0
+ */
+#define DAC_DBUF_LS_PAD_0    (BIT(5))
+#define DAC_DBUF_LS_PAD_0_M  (DAC_DBUF_LS_PAD_0_V << DAC_DBUF_LS_PAD_0_S)
+#define DAC_DBUF_LS_PAD_0_V  0x00000001U
+#define DAC_DBUF_LS_PAD_0_S  5
+/** DAC_ON_LS_PAD_0 : R/W; bitpos: [6]; default: 0;
+ *  1 to turn on the DAC PAD 0 during sample and hold mode
+ */
+#define DAC_ON_LS_PAD_0    (BIT(6))
+#define DAC_ON_LS_PAD_0_M  (DAC_ON_LS_PAD_0_V << DAC_ON_LS_PAD_0_S)
+#define DAC_ON_LS_PAD_0_V  0x00000001U
+#define DAC_ON_LS_PAD_0_S  6
+/** DAC_HS_MODE_PAD_1 : R/W; bitpos: [7]; default: 0;
+ *  1 to let DAC PAD 1 enter High speed mode
+ */
+#define DAC_HS_MODE_PAD_1    (BIT(7))
+#define DAC_HS_MODE_PAD_1_M  (DAC_HS_MODE_PAD_1_V << DAC_HS_MODE_PAD_1_S)
+#define DAC_HS_MODE_PAD_1_V  0x00000001U
+#define DAC_HS_MODE_PAD_1_S  7
+/** DAC_XPD_PAD_1 : R/W; bitpos: [8]; default: 0;
+ *  1 to power on DAC PAD 1
+ */
+#define DAC_XPD_PAD_1    (BIT(8))
+#define DAC_XPD_PAD_1_M  (DAC_XPD_PAD_1_V << DAC_XPD_PAD_1_S)
+#define DAC_XPD_PAD_1_V  0x00000001U
+#define DAC_XPD_PAD_1_S  8
+/** DAC_EN_ADC_MUX_PAD_1 : R/W; bitpos: [9]; default: 0;
+ *  1 to enable adc mux for DAC PAD 1
+ */
+#define DAC_EN_ADC_MUX_PAD_1    (BIT(9))
+#define DAC_EN_ADC_MUX_PAD_1_M  (DAC_EN_ADC_MUX_PAD_1_V << DAC_EN_ADC_MUX_PAD_1_S)
+#define DAC_EN_ADC_MUX_PAD_1_V  0x00000001U
+#define DAC_EN_ADC_MUX_PAD_1_S  9
+/** DAC_DSAMP_LS_PAD_1 : R/W; bitpos: [10]; default: 0;
+ *  1 to start sample and hold mode for DAC PAD 1
+ */
+#define DAC_DSAMP_LS_PAD_1    (BIT(10))
+#define DAC_DSAMP_LS_PAD_1_M  (DAC_DSAMP_LS_PAD_1_V << DAC_DSAMP_LS_PAD_1_S)
+#define DAC_DSAMP_LS_PAD_1_V  0x00000001U
+#define DAC_DSAMP_LS_PAD_1_S  10
+/** DAC_DCAL_LS_PAD_1 : R/W; bitpos: [11]; default: 0;
+ *  1 to Calibrate the buffer of DAC PAD 1 (DBUF of pad 1 must be 1 during this
+ *  operation)
+ */
+#define DAC_DCAL_LS_PAD_1    (BIT(11))
+#define DAC_DCAL_LS_PAD_1_M  (DAC_DCAL_LS_PAD_1_V << DAC_DCAL_LS_PAD_1_S)
+#define DAC_DCAL_LS_PAD_1_V  0x00000001U
+#define DAC_DCAL_LS_PAD_1_S  11
+/** DAC_DBUF_LS_PAD_1 : R/W; bitpos: [12]; default: 0;
+ *  1 to turn on the buffer of DAC PAD 1
+ */
+#define DAC_DBUF_LS_PAD_1    (BIT(12))
+#define DAC_DBUF_LS_PAD_1_M  (DAC_DBUF_LS_PAD_1_V << DAC_DBUF_LS_PAD_1_S)
+#define DAC_DBUF_LS_PAD_1_V  0x00000001U
+#define DAC_DBUF_LS_PAD_1_S  12
+/** DAC_ON_LS_PAD_1 : R/W; bitpos: [13]; default: 0;
+ *  1 to turn on the DAC PAD 1 during sample and hold mode
+ */
+#define DAC_ON_LS_PAD_1    (BIT(13))
+#define DAC_ON_LS_PAD_1_M  (DAC_ON_LS_PAD_1_V << DAC_ON_LS_PAD_1_S)
+#define DAC_ON_LS_PAD_1_V  0x00000001U
+#define DAC_ON_LS_PAD_1_S  13
+/** DAC_DIV_NUM : R/W; bitpos: [29:14]; default: 1;
+ *  divide number between clk ls and clk hs
+ */
+#define DAC_DIV_NUM    0x0000FFFFU
+#define DAC_DIV_NUM_M  (DAC_DIV_NUM_V << DAC_DIV_NUM_S)
+#define DAC_DIV_NUM_V  0x0000FFFFU
+#define DAC_DIV_NUM_S  14
+/** DAC_DBUF_RANGE_LS_PAD_0 : R/W; bitpos: [30]; default: 0;
+ *  1:when buffer is activated, allow using full code of maximum bitwidth
+ *  0:when buffer is not activated, should always be 0
+ */
+#define DAC_DBUF_RANGE_LS_PAD_0    (BIT(30))
+#define DAC_DBUF_RANGE_LS_PAD_0_M  (DAC_DBUF_RANGE_LS_PAD_0_V << DAC_DBUF_RANGE_LS_PAD_0_S)
+#define DAC_DBUF_RANGE_LS_PAD_0_V  0x00000001U
+#define DAC_DBUF_RANGE_LS_PAD_0_S  30
+/** DAC_DBUF_RANGE_LS_PAD_1 : R/W; bitpos: [31]; default: 0;
+ *  1:when buffer is activated, allow using full code of maximum bitwidth
+ *  0:when buffer is not activated, should always be 0
+ */
+#define DAC_DBUF_RANGE_LS_PAD_1    (BIT(31))
+#define DAC_DBUF_RANGE_LS_PAD_1_M  (DAC_DBUF_RANGE_LS_PAD_1_V << DAC_DBUF_RANGE_LS_PAD_1_S)
+#define DAC_DBUF_RANGE_LS_PAD_1_V  0x00000001U
+#define DAC_DBUF_RANGE_LS_PAD_1_S  31
+
+/** DAC_CALI_RESULT_REG register
+ *  DAC CALI result register
+ */
+#define DAC_CALI_RESULT_REG (DR_REG_DAC_BASE + 0x4)
+/** DAC_CALI_RESULT_PAD_0 : R/W; bitpos: [11:0]; default: 0;
+ *  cali result register for pad 0 output
+ */
+#define DAC_CALI_RESULT_PAD_0    0x00000FFFU
+#define DAC_CALI_RESULT_PAD_0_M  (DAC_CALI_RESULT_PAD_0_V << DAC_CALI_RESULT_PAD_0_S)
+#define DAC_CALI_RESULT_PAD_0_V  0x00000FFFU
+#define DAC_CALI_RESULT_PAD_0_S  0
+/** DAC_CALI_RESULT_PAD_1 : R/W; bitpos: [23:12]; default: 0;
+ *  cali result register for pad 1 output
+ */
+#define DAC_CALI_RESULT_PAD_1    0x00000FFFU
+#define DAC_CALI_RESULT_PAD_1_M  (DAC_CALI_RESULT_PAD_1_V << DAC_CALI_RESULT_PAD_1_S)
+#define DAC_CALI_RESULT_PAD_1_V  0x00000FFFU
+#define DAC_CALI_RESULT_PAD_1_S  12
+
+/** DAC_PDMA_CFG_REG register
+ *  dac cfg register
+ */
+#define DAC_PDMA_CFG_REG (DR_REG_DAC_BASE + 0x8)
+/** DAC_PDMA_ALTER_MODE : R/W; bitpos: [0]; default: 0;
+ *  1:make rotation between two pads when outputting data of ppdma input path requires
+ *  reg_dac_1/0_data_sel = 1
+ *  0:no change
+ */
+#define DAC_PDMA_ALTER_MODE    (BIT(0))
+#define DAC_PDMA_ALTER_MODE_M  (DAC_PDMA_ALTER_MODE_V << DAC_PDMA_ALTER_MODE_S)
+#define DAC_PDMA_ALTER_MODE_V  0x00000001U
+#define DAC_PDMA_ALTER_MODE_S  0
+/** DAC_PDMA_RESET_FIFO : WT; bitpos: [1]; default: 0;
+ *  1:reset dac fifo
+ *  0:no change
+ */
+#define DAC_PDMA_RESET_FIFO    (BIT(1))
+#define DAC_PDMA_RESET_FIFO_M  (DAC_PDMA_RESET_FIFO_V << DAC_PDMA_RESET_FIFO_S)
+#define DAC_PDMA_RESET_FIFO_V  0x00000001U
+#define DAC_PDMA_RESET_FIFO_S  1
+/** DAC_PDMA_TRANS : R/W; bitpos: [2]; default: 0;
+ *  1:start transaction for pdma path output
+ *  0:stop transaction for pdma path output
+ */
+#define DAC_PDMA_TRANS    (BIT(2))
+#define DAC_PDMA_TRANS_M  (DAC_PDMA_TRANS_V << DAC_PDMA_TRANS_S)
+#define DAC_PDMA_TRANS_V  0x00000001U
+#define DAC_PDMA_TRANS_S  2
+
+/** DAC_PDMA_TIMER_CFG_REG register
+ *  PDMA path timer register
+ */
+#define DAC_PDMA_TIMER_CFG_REG (DR_REG_DAC_BASE + 0xc)
+/** DAC_PDMA_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  1:enables using dac timer to reduce output frequency
+ *  0:no data output
+ */
+#define DAC_PDMA_TIMER_EN    (BIT(0))
+#define DAC_PDMA_TIMER_EN_M  (DAC_PDMA_TIMER_EN_V << DAC_PDMA_TIMER_EN_S)
+#define DAC_PDMA_TIMER_EN_V  0x00000001U
+#define DAC_PDMA_TIMER_EN_S  0
+/** DAC_PDMA_TIMER_TARGET : R/W; bitpos: [24:1]; default: 2;
+ *  dac pdma timer wait target
+ */
+#define DAC_PDMA_TIMER_TARGET    0x00FFFFFFU
+#define DAC_PDMA_TIMER_TARGET_M  (DAC_PDMA_TIMER_TARGET_V << DAC_PDMA_TIMER_TARGET_S)
+#define DAC_PDMA_TIMER_TARGET_V  0x00FFFFFFU
+#define DAC_PDMA_TIMER_TARGET_S  1
+
+/** DAC_DATA_OUTPUT_CFG_REG register
+ *  dac DATA OUTPUT cfg register
+ */
+#define DAC_DATA_OUTPUT_CFG_REG (DR_REG_DAC_BASE + 0x10)
+/** DAC_PAD_0_DATA_SEL : R/W; bitpos: [0]; default: 0;
+ *  1:output pdma data
+ *  0:output sintx data
+ */
+#define DAC_PAD_0_DATA_SEL    (BIT(0))
+#define DAC_PAD_0_DATA_SEL_M  (DAC_PAD_0_DATA_SEL_V << DAC_PAD_0_DATA_SEL_S)
+#define DAC_PAD_0_DATA_SEL_V  0x00000001U
+#define DAC_PAD_0_DATA_SEL_S  0
+/** DAC_PAD_1_DATA_SEL : R/W; bitpos: [1]; default: 0;
+ *  1:output pdma data
+ *  0:output sintx data
+ */
+#define DAC_PAD_1_DATA_SEL    (BIT(1))
+#define DAC_PAD_1_DATA_SEL_M  (DAC_PAD_1_DATA_SEL_V << DAC_PAD_1_DATA_SEL_S)
+#define DAC_PAD_1_DATA_SEL_V  0x00000001U
+#define DAC_PAD_1_DATA_SEL_S  1
+
+/** DAC_SINTX_CFG_REG register
+ *  dac rstn register
+ */
+#define DAC_SINTX_CFG_REG (DR_REG_DAC_BASE + 0x14)
+/** DAC_SW_TONE : R/W; bitpos: [0]; default: 0;
+ *  1:enable software adjusting current sintx output data
+ *  0:disable software adjustment
+ */
+#define DAC_SW_TONE    (BIT(0))
+#define DAC_SW_TONE_M  (DAC_SW_TONE_V << DAC_SW_TONE_S)
+#define DAC_SW_TONE_V  0x00000001U
+#define DAC_SW_TONE_S  0
+/** DAC_SW_FSTEP : R/W; bitpos: [16:1]; default: 1;
+ *  software adjust angle velocity foot step for sintx LUT input
+ */
+#define DAC_SW_FSTEP    0x0000FFFFU
+#define DAC_SW_FSTEP_M  (DAC_SW_FSTEP_V << DAC_SW_FSTEP_S)
+#define DAC_SW_FSTEP_V  0x0000FFFFU
+#define DAC_SW_FSTEP_S  1
+/** DAC_SCALE_1 : R/W; bitpos: [18:17]; default: 0;
+ *  right shift scaling config for LUT output of sintx for pad 0
+ */
+#define DAC_SCALE_1    0x00000003U
+#define DAC_SCALE_1_M  (DAC_SCALE_1_V << DAC_SCALE_1_S)
+#define DAC_SCALE_1_V  0x00000003U
+#define DAC_SCALE_1_S  17
+/** DAC_SCALE_2 : R/W; bitpos: [20:19]; default: 0;
+ *  software adjust angle velocity foot step for sintx LUT input
+ */
+#define DAC_SCALE_2    0x00000003U
+#define DAC_SCALE_2_M  (DAC_SCALE_2_V << DAC_SCALE_2_S)
+#define DAC_SCALE_2_V  0x00000003U
+#define DAC_SCALE_2_S  19
+/** DAC_INV_1 : R/W; bitpos: [22:21]; default: 0;
+ *  bit 1: invert the highest bit of output for pad 0
+ *  Bit 0: invert the entire output for pad 0
+ */
+#define DAC_INV_1    0x00000003U
+#define DAC_INV_1_M  (DAC_INV_1_V << DAC_INV_1_S)
+#define DAC_INV_1_V  0x00000003U
+#define DAC_INV_1_S  21
+/** DAC_INV_2 : R/W; bitpos: [24:23]; default: 0;
+ *  bit 1: invert the highest bit of output for pad 1
+ *  Bit 0: invert the entire output for pad 1
+ */
+#define DAC_INV_2    0x00000003U
+#define DAC_INV_2_M  (DAC_INV_2_V << DAC_INV_2_S)
+#define DAC_INV_2_V  0x00000003U
+#define DAC_INV_2_S  23
+
+/** DAC_SINTX_TIMER_CFG_REG register
+ *  SINTX path timer register
+ */
+#define DAC_SINTX_TIMER_CFG_REG (DR_REG_DAC_BASE + 0x18)
+/** DAC_SINTX_TIMER_EN : R/W; bitpos: [0]; default: 0;
+ *  1:enables using dac timer to reduce output frequency
+ *  0:no data output
+ */
+#define DAC_SINTX_TIMER_EN    (BIT(0))
+#define DAC_SINTX_TIMER_EN_M  (DAC_SINTX_TIMER_EN_V << DAC_SINTX_TIMER_EN_S)
+#define DAC_SINTX_TIMER_EN_V  0x00000001U
+#define DAC_SINTX_TIMER_EN_S  0
+/** DAC_SINTX_TIMER_TARGET : R/W; bitpos: [24:1]; default: 2;
+ *  dac sintx timer wait target
+ */
+#define DAC_SINTX_TIMER_TARGET    0x00FFFFFFU
+#define DAC_SINTX_TIMER_TARGET_M  (DAC_SINTX_TIMER_TARGET_V << DAC_SINTX_TIMER_TARGET_S)
+#define DAC_SINTX_TIMER_TARGET_V  0x00FFFFFFU
+#define DAC_SINTX_TIMER_TARGET_S  1
+
+/** DAC_SINTX_DATA_REG register
+ *  dac output register for sintx path
+ */
+#define DAC_SINTX_DATA_REG (DR_REG_DAC_BASE + 0x1c)
+/** DAC_DC_1 : R/W; bitpos: [11:0]; default: 0;
+ *  the data output for DAC PAD0 for sintx path
+ */
+#define DAC_DC_1    0x00000FFFU
+#define DAC_DC_1_M  (DAC_DC_1_V << DAC_DC_1_S)
+#define DAC_DC_1_V  0x00000FFFU
+#define DAC_DC_1_S  0
+/** DAC_DC_2 : R/W; bitpos: [23:12]; default: 0;
+ *  the data output for DAC PAD1 for sintx path
+ */
+#define DAC_DC_2    0x00000FFFU
+#define DAC_DC_2_M  (DAC_DC_2_V << DAC_DC_2_S)
+#define DAC_DC_2_V  0x00000FFFU
+#define DAC_DC_2_S  12
+
+/** DAC_CALI_REG register
+ *  cali algorithm register for DAC
+ */
+#define DAC_CALI_REG (DR_REG_DAC_BASE + 0x20)
+/** DAC_CALI_OUT_PAD_0 : RO; bitpos: [0]; default: 0;
+ *  cali out from DAC PAD 0
+ */
+#define DAC_CALI_OUT_PAD_0    (BIT(0))
+#define DAC_CALI_OUT_PAD_0_M  (DAC_CALI_OUT_PAD_0_V << DAC_CALI_OUT_PAD_0_S)
+#define DAC_CALI_OUT_PAD_0_V  0x00000001U
+#define DAC_CALI_OUT_PAD_0_S  0
+/** DAC_CALI_OUT_PAD_1 : RO; bitpos: [1]; default: 0;
+ *  cali out from DAC PAD 1
+ */
+#define DAC_CALI_OUT_PAD_1    (BIT(1))
+#define DAC_CALI_OUT_PAD_1_M  (DAC_CALI_OUT_PAD_1_V << DAC_CALI_OUT_PAD_1_S)
+#define DAC_CALI_OUT_PAD_1_V  0x00000001U
+#define DAC_CALI_OUT_PAD_1_S  1
+
+/** DAC_SAMPLE_WAIT_CFG_REG register
+ *  cali sample phase duration register
+ */
+#define DAC_SAMPLE_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x24)
+/** DAC_WAIT_TARGET_SAMPLE_PAD_0 : R/W; bitpos: [15:0]; default: 630;
+ *  sample wait target for DAC PAD 1
+ */
+#define DAC_WAIT_TARGET_SAMPLE_PAD_0    0x0000FFFFU
+#define DAC_WAIT_TARGET_SAMPLE_PAD_0_M  (DAC_WAIT_TARGET_SAMPLE_PAD_0_V << DAC_WAIT_TARGET_SAMPLE_PAD_0_S)
+#define DAC_WAIT_TARGET_SAMPLE_PAD_0_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_SAMPLE_PAD_0_S  0
+/** DAC_WAIT_TARGET_SAMPLE_PAD_1 : R/W; bitpos: [31:16]; default: 630;
+ *  sample wait target for DAC PAD 0
+ */
+#define DAC_WAIT_TARGET_SAMPLE_PAD_1    0x0000FFFFU
+#define DAC_WAIT_TARGET_SAMPLE_PAD_1_M  (DAC_WAIT_TARGET_SAMPLE_PAD_1_V << DAC_WAIT_TARGET_SAMPLE_PAD_1_S)
+#define DAC_WAIT_TARGET_SAMPLE_PAD_1_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_SAMPLE_PAD_1_S  16
+
+/** DAC_HOLD_WAIT_CFG_REG register
+ *  cali hold phase duration register
+ */
+#define DAC_HOLD_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x28)
+/** DAC_WAIT_TARGET_HOLD_PAD_0 : R/W; bitpos: [15:0]; default: 61;
+ *  hold wait target for DAC PAD 0
+ */
+#define DAC_WAIT_TARGET_HOLD_PAD_0    0x0000FFFFU
+#define DAC_WAIT_TARGET_HOLD_PAD_0_M  (DAC_WAIT_TARGET_HOLD_PAD_0_V << DAC_WAIT_TARGET_HOLD_PAD_0_S)
+#define DAC_WAIT_TARGET_HOLD_PAD_0_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_HOLD_PAD_0_S  0
+/** DAC_WAIT_TARGET_HOLD_PAD_1 : R/W; bitpos: [31:16]; default: 61;
+ *  hold wait target for DAC PAD 1
+ */
+#define DAC_WAIT_TARGET_HOLD_PAD_1    0x0000FFFFU
+#define DAC_WAIT_TARGET_HOLD_PAD_1_M  (DAC_WAIT_TARGET_HOLD_PAD_1_V << DAC_WAIT_TARGET_HOLD_PAD_1_S)
+#define DAC_WAIT_TARGET_HOLD_PAD_1_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_HOLD_PAD_1_S  16
+
+/** DAC_REFRESH_WAIT_CFG_REG register
+ *  cali refresh phase duration register
+ */
+#define DAC_REFRESH_WAIT_CFG_REG (DR_REG_DAC_BASE + 0x2c)
+/** DAC_WAIT_TARGET_REFRESH_PAD_0 : R/W; bitpos: [15:0]; default: 8;
+ *  refresh wait target for DAC PAD 0
+ */
+#define DAC_WAIT_TARGET_REFRESH_PAD_0    0x0000FFFFU
+#define DAC_WAIT_TARGET_REFRESH_PAD_0_M  (DAC_WAIT_TARGET_REFRESH_PAD_0_V << DAC_WAIT_TARGET_REFRESH_PAD_0_S)
+#define DAC_WAIT_TARGET_REFRESH_PAD_0_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_REFRESH_PAD_0_S  0
+/** DAC_WAIT_TARGET_REFRESH_PAD_1 : R/W; bitpos: [31:16]; default: 8;
+ *  refresh wait target for DAC PAD 1
+ */
+#define DAC_WAIT_TARGET_REFRESH_PAD_1    0x0000FFFFU
+#define DAC_WAIT_TARGET_REFRESH_PAD_1_M  (DAC_WAIT_TARGET_REFRESH_PAD_1_V << DAC_WAIT_TARGET_REFRESH_PAD_1_S)
+#define DAC_WAIT_TARGET_REFRESH_PAD_1_V  0x0000FFFFU
+#define DAC_WAIT_TARGET_REFRESH_PAD_1_S  16
+
+/** DAC_PDMA_INT_RAW_REG register
+ *  need_des
+ */
+#define DAC_PDMA_INT_RAW_REG (DR_REG_DAC_BASE + 0x30)
+/** DAC_PDMA_EMPTY_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define DAC_PDMA_EMPTY_INT_RAW    (BIT(31))
+#define DAC_PDMA_EMPTY_INT_RAW_M  (DAC_PDMA_EMPTY_INT_RAW_V << DAC_PDMA_EMPTY_INT_RAW_S)
+#define DAC_PDMA_EMPTY_INT_RAW_V  0x00000001U
+#define DAC_PDMA_EMPTY_INT_RAW_S  31
+
+/** DAC_INT_ST_REG register
+ *  need_des
+ */
+#define DAC_INT_ST_REG (DR_REG_DAC_BASE + 0x34)
+/** DAC_PDMA_EMPTY_INT_ST : RO; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define DAC_PDMA_EMPTY_INT_ST    (BIT(31))
+#define DAC_PDMA_EMPTY_INT_ST_M  (DAC_PDMA_EMPTY_INT_ST_V << DAC_PDMA_EMPTY_INT_ST_S)
+#define DAC_PDMA_EMPTY_INT_ST_V  0x00000001U
+#define DAC_PDMA_EMPTY_INT_ST_S  31
+
+/** DAC_INT_ENA_REG register
+ *  need_des
+ */
+#define DAC_INT_ENA_REG (DR_REG_DAC_BASE + 0x38)
+/** DAC_PDMA_EMPTY_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define DAC_PDMA_EMPTY_INT_ENA    (BIT(31))
+#define DAC_PDMA_EMPTY_INT_ENA_M  (DAC_PDMA_EMPTY_INT_ENA_V << DAC_PDMA_EMPTY_INT_ENA_S)
+#define DAC_PDMA_EMPTY_INT_ENA_V  0x00000001U
+#define DAC_PDMA_EMPTY_INT_ENA_S  31
+
+/** DAC_INT_CLR_REG register
+ *  need_des
+ */
+#define DAC_INT_CLR_REG (DR_REG_DAC_BASE + 0x3c)
+/** DAC_PDMA_EMPTY_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define DAC_PDMA_EMPTY_INT_CLR    (BIT(31))
+#define DAC_PDMA_EMPTY_INT_CLR_M  (DAC_PDMA_EMPTY_INT_CLR_V << DAC_PDMA_EMPTY_INT_CLR_S)
+#define DAC_PDMA_EMPTY_INT_CLR_V  0x00000001U
+#define DAC_PDMA_EMPTY_INT_CLR_S  31
+
+/** DAC_DATE_REG register
+ *  need_des
+ */
+#define DAC_DATE_REG (DR_REG_DAC_BASE + 0x3fc)
+/** DAC_DATE : R/W; bitpos: [30:0]; default: 2426393;
+ *  need_des
+ */
+#define DAC_DATE    0x7FFFFFFFU
+#define DAC_DATE_M  (DAC_DATE_V << DAC_DATE_S)
+#define DAC_DATE_V  0x7FFFFFFFU
+#define DAC_DATE_S  0
+/** DAC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define DAC_CLK_EN    (BIT(31))
+#define DAC_CLK_EN_M  (DAC_CLK_EN_V << DAC_CLK_EN_S)
+#define DAC_CLK_EN_V  0x00000001U
+#define DAC_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/dac_struct.h b/components/soc/esp32s31/register/soc/dac_struct.h
new file mode 100644
index 00000000000..610e03b3bbe
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/dac_struct.h
@@ -0,0 +1,423 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of pad_cfg register
+ *  configure dac pad register
+ */
+typedef union {
+    struct {
+        /** hs_mode_pad_0 : R/W; bitpos: [0]; default: 0;
+         *  1 to let DAC PAD 0 enter High speed mode
+         */
+        uint32_t hs_mode_pad_0:1;
+        /** xpd_pad_0 : R/W; bitpos: [1]; default: 0;
+         *  1 to power on DAC PAD 0
+         */
+        uint32_t xpd_pad_0:1;
+        /** en_adc_mux_pad_0 : R/W; bitpos: [2]; default: 0;
+         *  1 to enable adc mux for DAC PAD 0
+         */
+        uint32_t en_adc_mux_pad_0:1;
+        /** dsamp_ls_pad_0 : R/W; bitpos: [3]; default: 0;
+         *  1 to start sample and hold mode for DAC PAD 0
+         */
+        uint32_t dsamp_ls_pad_0:1;
+        /** dcal_ls_pad_0 : R/W; bitpos: [4]; default: 0;
+         *  1 to Calibrate the buffer of DAC PAD 0 (DBUF of pad 1 must be 1 during this
+         *  operation)
+         */
+        uint32_t dcal_ls_pad_0:1;
+        /** dbuf_ls_pad_0 : R/W; bitpos: [5]; default: 0;
+         *  1 to turn on the buffer of DAC PAD 0
+         */
+        uint32_t dbuf_ls_pad_0:1;
+        /** on_ls_pad_0 : R/W; bitpos: [6]; default: 0;
+         *  1 to turn on the DAC PAD 0 during sample and hold mode
+         */
+        uint32_t on_ls_pad_0:1;
+        /** hs_mode_pad_1 : R/W; bitpos: [7]; default: 0;
+         *  1 to let DAC PAD 1 enter High speed mode
+         */
+        uint32_t hs_mode_pad_1:1;
+        /** xpd_pad_1 : R/W; bitpos: [8]; default: 0;
+         *  1 to power on DAC PAD 1
+         */
+        uint32_t xpd_pad_1:1;
+        /** en_adc_mux_pad_1 : R/W; bitpos: [9]; default: 0;
+         *  1 to enable adc mux for DAC PAD 1
+         */
+        uint32_t en_adc_mux_pad_1:1;
+        /** dsamp_ls_pad_1 : R/W; bitpos: [10]; default: 0;
+         *  1 to start sample and hold mode for DAC PAD 1
+         */
+        uint32_t dsamp_ls_pad_1:1;
+        /** dcal_ls_pad_1 : R/W; bitpos: [11]; default: 0;
+         *  1 to Calibrate the buffer of DAC PAD 1 (DBUF of pad 1 must be 1 during this
+         *  operation)
+         */
+        uint32_t dcal_ls_pad_1:1;
+        /** dbuf_ls_pad_1 : R/W; bitpos: [12]; default: 0;
+         *  1 to turn on the buffer of DAC PAD 1
+         */
+        uint32_t dbuf_ls_pad_1:1;
+        /** on_ls_pad_1 : R/W; bitpos: [13]; default: 0;
+         *  1 to turn on the DAC PAD 1 during sample and hold mode
+         */
+        uint32_t on_ls_pad_1:1;
+        /** div_num : R/W; bitpos: [29:14]; default: 1;
+         *  divide number between clk ls and clk hs
+         */
+        uint32_t div_num:16;
+        /** dbuf_range_ls_pad_0 : R/W; bitpos: [30]; default: 0;
+         *  1:when buffer is activated, allow using full code of maximum bitwidth
+         *  0:when buffer is not activated, should always be 0
+         */
+        uint32_t dbuf_range_ls_pad_0:1;
+        /** dbuf_range_ls_pad_1 : R/W; bitpos: [31]; default: 0;
+         *  1:when buffer is activated, allow using full code of maximum bitwidth
+         *  0:when buffer is not activated, should always be 0
+         */
+        uint32_t dbuf_range_ls_pad_1:1;
+    };
+    uint32_t val;
+} dac_pad_cfg_reg_t;
+
+/** Type of cali_result register
+ *  DAC CALI result register
+ */
+typedef union {
+    struct {
+        /** cali_result_pad_0 : R/W; bitpos: [11:0]; default: 0;
+         *  cali result register for pad 0 output
+         */
+        uint32_t cali_result_pad_0:12;
+        /** cali_result_pad_1 : R/W; bitpos: [23:12]; default: 0;
+         *  cali result register for pad 1 output
+         */
+        uint32_t cali_result_pad_1:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dac_cali_result_reg_t;
+
+/** Type of pdma_cfg register
+ *  dac cfg register
+ */
+typedef union {
+    struct {
+        /** pdma_alter_mode : R/W; bitpos: [0]; default: 0;
+         *  1:make rotation between two pads when outputting data of ppdma input path requires
+         *  reg_dac_1/0_data_sel = 1
+         *  0:no change
+         */
+        uint32_t pdma_alter_mode:1;
+        /** pdma_reset_fifo : WT; bitpos: [1]; default: 0;
+         *  1:reset dac fifo
+         *  0:no change
+         */
+        uint32_t pdma_reset_fifo:1;
+        /** pdma_trans : R/W; bitpos: [2]; default: 0;
+         *  1:start transaction for pdma path output
+         *  0:stop transaction for pdma path output
+         */
+        uint32_t pdma_trans:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dac_pdma_cfg_reg_t;
+
+/** Type of pdma_timer_cfg register
+ *  PDMA path timer register
+ */
+typedef union {
+    struct {
+        /** pdma_timer_en : R/W; bitpos: [0]; default: 0;
+         *  1:enables using dac timer to reduce output frequency
+         *  0:no data output
+         */
+        uint32_t pdma_timer_en:1;
+        /** pdma_timer_target : R/W; bitpos: [24:1]; default: 2;
+         *  dac pdma timer wait target
+         */
+        uint32_t pdma_timer_target:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dac_pdma_timer_cfg_reg_t;
+
+/** Type of data_output_cfg register
+ *  dac DATA OUTPUT cfg register
+ */
+typedef union {
+    struct {
+        /** pad_0_data_sel : R/W; bitpos: [0]; default: 0;
+         *  1:output pdma data
+         *  0:output sintx data
+         */
+        uint32_t pad_0_data_sel:1;
+        /** pad_1_data_sel : R/W; bitpos: [1]; default: 0;
+         *  1:output pdma data
+         *  0:output sintx data
+         */
+        uint32_t pad_1_data_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dac_data_output_cfg_reg_t;
+
+/** Type of sintx_cfg register
+ *  dac rstn register
+ */
+typedef union {
+    struct {
+        /** sw_tone : R/W; bitpos: [0]; default: 0;
+         *  1:enable software adjusting current sintx output data
+         *  0:disable software adjustment
+         */
+        uint32_t sw_tone:1;
+        /** sw_fstep : R/W; bitpos: [16:1]; default: 1;
+         *  software adjust angle velocity foot step for sintx LUT input
+         */
+        uint32_t sw_fstep:16;
+        /** scale_1 : R/W; bitpos: [18:17]; default: 0;
+         *  right shift scaling config for LUT output of sintx for pad 0
+         */
+        uint32_t scale_1:2;
+        /** scale_2 : R/W; bitpos: [20:19]; default: 0;
+         *  software adjust angle velocity foot step for sintx LUT input
+         */
+        uint32_t scale_2:2;
+        /** inv_1 : R/W; bitpos: [22:21]; default: 0;
+         *  bit 1: invert the highest bit of output for pad 0
+         *  Bit 0: invert the entire output for pad 0
+         */
+        uint32_t inv_1:2;
+        /** inv_2 : R/W; bitpos: [24:23]; default: 0;
+         *  bit 1: invert the highest bit of output for pad 1
+         *  Bit 0: invert the entire output for pad 1
+         */
+        uint32_t inv_2:2;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dac_sintx_cfg_reg_t;
+
+/** Type of sintx_timer_cfg register
+ *  SINTX path timer register
+ */
+typedef union {
+    struct {
+        /** sintx_timer_en : R/W; bitpos: [0]; default: 0;
+         *  1:enables using dac timer to reduce output frequency
+         *  0:no data output
+         */
+        uint32_t sintx_timer_en:1;
+        /** sintx_timer_target : R/W; bitpos: [24:1]; default: 2;
+         *  dac sintx timer wait target
+         */
+        uint32_t sintx_timer_target:24;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dac_sintx_timer_cfg_reg_t;
+
+/** Type of sintx_data register
+ *  dac output register for sintx path
+ */
+typedef union {
+    struct {
+        /** dc_1 : R/W; bitpos: [11:0]; default: 0;
+         *  the data output for DAC PAD0 for sintx path
+         */
+        uint32_t dc_1:12;
+        /** dc_2 : R/W; bitpos: [23:12]; default: 0;
+         *  the data output for DAC PAD1 for sintx path
+         */
+        uint32_t dc_2:12;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dac_sintx_data_reg_t;
+
+/** Type of cali register
+ *  cali algorithm register for DAC
+ */
+typedef union {
+    struct {
+        /** cali_out_pad_0 : RO; bitpos: [0]; default: 0;
+         *  cali out from DAC PAD 0
+         */
+        uint32_t cali_out_pad_0:1;
+        /** cali_out_pad_1 : RO; bitpos: [1]; default: 0;
+         *  cali out from DAC PAD 1
+         */
+        uint32_t cali_out_pad_1:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dac_cali_reg_t;
+
+/** Type of sample_wait_cfg register
+ *  cali sample phase duration register
+ */
+typedef union {
+    struct {
+        /** wait_target_sample_pad_0 : R/W; bitpos: [15:0]; default: 630;
+         *  sample wait target for DAC PAD 1
+         */
+        uint32_t wait_target_sample_pad_0:16;
+        /** wait_target_sample_pad_1 : R/W; bitpos: [31:16]; default: 630;
+         *  sample wait target for DAC PAD 0
+         */
+        uint32_t wait_target_sample_pad_1:16;
+    };
+    uint32_t val;
+} dac_sample_wait_cfg_reg_t;
+
+/** Type of hold_wait_cfg register
+ *  cali hold phase duration register
+ */
+typedef union {
+    struct {
+        /** wait_target_hold_pad_0 : R/W; bitpos: [15:0]; default: 61;
+         *  hold wait target for DAC PAD 0
+         */
+        uint32_t wait_target_hold_pad_0:16;
+        /** wait_target_hold_pad_1 : R/W; bitpos: [31:16]; default: 61;
+         *  hold wait target for DAC PAD 1
+         */
+        uint32_t wait_target_hold_pad_1:16;
+    };
+    uint32_t val;
+} dac_hold_wait_cfg_reg_t;
+
+/** Type of refresh_wait_cfg register
+ *  cali refresh phase duration register
+ */
+typedef union {
+    struct {
+        /** wait_target_refresh_pad_0 : R/W; bitpos: [15:0]; default: 8;
+         *  refresh wait target for DAC PAD 0
+         */
+        uint32_t wait_target_refresh_pad_0:16;
+        /** wait_target_refresh_pad_1 : R/W; bitpos: [31:16]; default: 8;
+         *  refresh wait target for DAC PAD 1
+         */
+        uint32_t wait_target_refresh_pad_1:16;
+    };
+    uint32_t val;
+} dac_refresh_wait_cfg_reg_t;
+
+/** Type of pdma_int_raw register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** pdma_empty_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pdma_empty_int_raw:1;
+    };
+    uint32_t val;
+} dac_pdma_int_raw_reg_t;
+
+/** Type of int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** pdma_empty_int_st : RO; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pdma_empty_int_st:1;
+    };
+    uint32_t val;
+} dac_int_st_reg_t;
+
+/** Type of int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** pdma_empty_int_ena : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pdma_empty_int_ena:1;
+    };
+    uint32_t val;
+} dac_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** pdma_empty_int_clr : WT; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t pdma_empty_int_clr:1;
+    };
+    uint32_t val;
+} dac_int_clr_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 2426393;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} dac_date_reg_t;
+
+
+typedef struct {
+    volatile dac_pad_cfg_reg_t pad_cfg;
+    volatile dac_cali_result_reg_t cali_result;
+    volatile dac_pdma_cfg_reg_t pdma_cfg;
+    volatile dac_pdma_timer_cfg_reg_t pdma_timer_cfg;
+    volatile dac_data_output_cfg_reg_t data_output_cfg;
+    volatile dac_sintx_cfg_reg_t sintx_cfg;
+    volatile dac_sintx_timer_cfg_reg_t sintx_timer_cfg;
+    volatile dac_sintx_data_reg_t sintx_data;
+    volatile dac_cali_reg_t cali;
+    volatile dac_sample_wait_cfg_reg_t sample_wait_cfg;
+    volatile dac_hold_wait_cfg_reg_t hold_wait_cfg;
+    volatile dac_refresh_wait_cfg_reg_t refresh_wait_cfg;
+    volatile dac_pdma_int_raw_reg_t pdma_int_raw;
+    volatile dac_int_st_reg_t int_st;
+    volatile dac_int_ena_reg_t int_ena;
+    volatile dac_int_clr_reg_t int_clr;
+    uint32_t reserved_040[239];
+    volatile dac_date_reg_t date;
+} dac_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dac_dev_t) == 0x400, "Invalid size of dac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/dma2d_reg.h b/components/soc/esp32s31/register/soc/dma2d_reg.h
new file mode 100644
index 00000000000..cce4ae04ed6
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/dma2d_reg.h
@@ -0,0 +1,7190 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DMA2D_OUT_CONF0_CH0_REG register
+ *  Configures the tx direction of channel 0
+ */
+#define DMA2D_OUT_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x0)
+/** DMA2D_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH0    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH0_M  (DMA2D_OUT_AUTO_WRBACK_CH0_V << DMA2D_OUT_AUTO_WRBACK_CH0_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH0_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH0_S  0
+/** DMA2D_OUT_EOF_MODE_CH0 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH0    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH0_M  (DMA2D_OUT_EOF_MODE_CH0_V << DMA2D_OUT_EOF_MODE_CH0_S)
+#define DMA2D_OUT_EOF_MODE_CH0_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH0_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH0_M  (DMA2D_OUTDSCR_BURST_EN_CH0_V << DMA2D_OUTDSCR_BURST_EN_CH0_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH0_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH0_M  (DMA2D_OUT_ECC_AES_EN_CH0_V << DMA2D_OUT_ECC_AES_EN_CH0_S)
+#define DMA2D_OUT_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH0_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH0_M  (DMA2D_OUT_CHECK_OWNER_CH0_V << DMA2D_OUT_CHECK_OWNER_CH0_S)
+#define DMA2D_OUT_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH0_S  4
+/** DMA2D_OUT_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH0_M  (DMA2D_OUT_LOOP_TEST_CH0_V << DMA2D_OUT_LOOP_TEST_CH0_S)
+#define DMA2D_OUT_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH0_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH0_V << DMA2D_OUT_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_M  (DMA2D_OUT_DSCR_PORT_EN_CH0_V << DMA2D_OUT_DSCR_PORT_EN_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_M  (DMA2D_OUT_PAGE_BOUND_EN_CH0_V << DMA2D_OUT_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_OUT_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH0_M  (DMA2D_OUT_REORDER_EN_CH0_V << DMA2D_OUT_REORDER_EN_CH0_S)
+#define DMA2D_OUT_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH0_S  16
+/** DMA2D_OUT_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH0    (BIT(24))
+#define DMA2D_OUT_RST_CH0_M  (DMA2D_OUT_RST_CH0_V << DMA2D_OUT_RST_CH0_S)
+#define DMA2D_OUT_RST_CH0_V  0x00000001U
+#define DMA2D_OUT_RST_CH0_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH0_M  (DMA2D_OUT_CMD_DISABLE_CH0_V << DMA2D_OUT_CMD_DISABLE_CH0_S)
+#define DMA2D_OUT_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH0_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_OUT_INT_RAW_CH0_REG register
+ *  Raw interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x4)
+/** DMA2D_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_RAW_M  (DMA2D_OUT_DONE_CH0_INT_RAW_V << DMA2D_OUT_DONE_CH0_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_RAW_M  (DMA2D_OUT_EOF_CH0_INT_RAW_V << DMA2D_OUT_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x8)
+/** DMA2D_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ENA_M  (DMA2D_OUT_DONE_CH0_INT_ENA_V << DMA2D_OUT_DONE_CH0_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ENA_M  (DMA2D_OUT_EOF_CH0_INT_ENA_V << DMA2D_OUT_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH0_REG register
+ *  Masked interrupt status of TX channel 0
+ */
+#define DMA2D_OUT_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0xc)
+/** DMA2D_OUT_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_ST_M  (DMA2D_OUT_DONE_CH0_INT_ST_V << DMA2D_OUT_DONE_CH0_INT_ST_S)
+#define DMA2D_OUT_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_ST_M  (DMA2D_OUT_EOF_CH0_INT_ST_V << DMA2D_OUT_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of TX channel 0
+ */
+#define DMA2D_OUT_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x10)
+/** DMA2D_OUT_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH0_INT_CLR_M  (DMA2D_OUT_DONE_CH0_INT_CLR_V << DMA2D_OUT_DONE_CH0_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH0_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH0_INT_CLR_M  (DMA2D_OUT_EOF_CH0_INT_CLR_V << DMA2D_OUT_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH0_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH0_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH0_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH0_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH0_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH0_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH0_REG register
+ *  Represents the status of the tx fifo of channel 0
+ */
+#define DMA2D_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x14)
+/** DMA2D_OUTFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH0_M  (DMA2D_OUTFIFO_FULL_L2_CH0_V << DMA2D_OUTFIFO_FULL_L2_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH0_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_M  (DMA2D_OUTFIFO_EMPTY_L2_CH0_V << DMA2D_OUTFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_M  (DMA2D_OUTFIFO_CNT_L2_CH0_V << DMA2D_OUTFIFO_CNT_L2_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH0_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH0_V << DMA2D_OUT_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH0_V << DMA2D_OUT_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH0_V << DMA2D_OUT_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH0_V << DMA2D_OUT_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH0_V << DMA2D_OUT_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH0_V << DMA2D_OUT_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH0_V << DMA2D_OUT_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH0_V << DMA2D_OUT_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH0_M  (DMA2D_OUTFIFO_FULL_L1_CH0_V << DMA2D_OUTFIFO_FULL_L1_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH0_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_M  (DMA2D_OUTFIFO_EMPTY_L1_CH0_V << DMA2D_OUTFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_M  (DMA2D_OUTFIFO_CNT_L1_CH0_V << DMA2D_OUTFIFO_CNT_L1_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH0_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH0_M  (DMA2D_OUTFIFO_FULL_L3_CH0_V << DMA2D_OUTFIFO_FULL_L3_CH0_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH0_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_M  (DMA2D_OUTFIFO_EMPTY_L3_CH0_V << DMA2D_OUTFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_M  (DMA2D_OUTFIFO_CNT_L3_CH0_V << DMA2D_OUTFIFO_CNT_L3_CH0_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_OUT_PUSH_CH0_REG register
+ *  Configures the tx fifo of channel 0
+ */
+#define DMA2D_OUT_PUSH_CH0_REG (DR_REG_DMA2D_BASE + 0x18)
+/** DMA2D_OUTFIFO_WDATA_CH0 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH0    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_M  (DMA2D_OUTFIFO_WDATA_CH0_V << DMA2D_OUTFIFO_WDATA_CH0_S)
+#define DMA2D_OUTFIFO_WDATA_CH0_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH0_S  0
+/** DMA2D_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH0    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH0_M  (DMA2D_OUTFIFO_PUSH_CH0_V << DMA2D_OUTFIFO_PUSH_CH0_S)
+#define DMA2D_OUTFIFO_PUSH_CH0_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH0_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH0_REG register
+ *  Configures the tx descriptor operations of channel 0
+ */
+#define DMA2D_OUT_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x1c)
+/** DMA2D_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH0    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH0_M  (DMA2D_OUTLINK_STOP_CH0_V << DMA2D_OUTLINK_STOP_CH0_S)
+#define DMA2D_OUTLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH0_S  20
+/** DMA2D_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH0    (BIT(21))
+#define DMA2D_OUTLINK_START_CH0_M  (DMA2D_OUTLINK_START_CH0_V << DMA2D_OUTLINK_START_CH0_S)
+#define DMA2D_OUTLINK_START_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH0_S  21
+/** DMA2D_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH0    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH0_M  (DMA2D_OUTLINK_RESTART_CH0_V << DMA2D_OUTLINK_RESTART_CH0_S)
+#define DMA2D_OUTLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH0_S  22
+/** DMA2D_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH0    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH0_M  (DMA2D_OUTLINK_PARK_CH0_V << DMA2D_OUTLINK_PARK_CH0_S)
+#define DMA2D_OUTLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH0_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH0_REG register
+ *  Configures the tx descriptor address of channel 0
+ */
+#define DMA2D_OUT_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x20)
+/** DMA2D_OUTLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_M  (DMA2D_OUTLINK_ADDR_CH0_V << DMA2D_OUTLINK_ADDR_CH0_S)
+#define DMA2D_OUTLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH0_S  0
+
+/** DMA2D_OUT_STATE_CH0_REG register
+ *  Represents the working status of the tx descriptor of channel 0
+ */
+#define DMA2D_OUT_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x24)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_M  (DMA2D_OUTLINK_DSCR_ADDR_CH0_V << DMA2D_OUTLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_M  (DMA2D_OUT_DSCR_STATE_CH0_V << DMA2D_OUT_DSCR_STATE_CH0_S)
+#define DMA2D_OUT_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH0_S  18
+/** DMA2D_OUT_STATE_CH0 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH0    0x0000000FU
+#define DMA2D_OUT_STATE_CH0_M  (DMA2D_OUT_STATE_CH0_V << DMA2D_OUT_STATE_CH0_S)
+#define DMA2D_OUT_STATE_CH0_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH0_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH0 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH0    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH0_M  (DMA2D_OUT_RESET_AVAIL_CH0_V << DMA2D_OUT_RESET_AVAIL_CH0_S)
+#define DMA2D_OUT_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH0_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x28)
+/** DMA2D_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_M  (DMA2D_OUT_EOF_DES_ADDR_CH0_V << DMA2D_OUT_EOF_DES_ADDR_CH0_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x2c)
+/** DMA2D_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_M  (DMA2D_OUTLINK_DSCR_CH0_V << DMA2D_OUTLINK_DSCR_CH0_S)
+#define DMA2D_OUTLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x30)
+/** DMA2D_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_M  (DMA2D_OUTLINK_DSCR_BF0_CH0_V << DMA2D_OUTLINK_DSCR_BF0_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the outlink descriptor of channel 0
+ */
+#define DMA2D_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x34)
+/** DMA2D_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_M  (DMA2D_OUTLINK_DSCR_BF1_CH0_V << DMA2D_OUTLINK_DSCR_BF1_CH0_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH0_REG register
+ *  Configures the tx peripheral of channel 0
+ */
+#define DMA2D_OUT_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x38)
+/** DMA2D_OUT_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH0    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_M  (DMA2D_OUT_PERI_SEL_CH0_V << DMA2D_OUT_PERI_SEL_CH0_S)
+#define DMA2D_OUT_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH0_S  0
+
+/** DMA2D_OUT_ARB_CH0_REG register
+ *  Configures the tx arbiter of channel 0
+ */
+#define DMA2D_OUT_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x3c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH0_V << DMA2D_OUT_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH0    0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH0_M  (DMA2D_OUT_ARB_PRIORITY_CH0_V << DMA2D_OUT_ARB_PRIORITY_CH0_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH0_V  0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH0_REG register
+ *  Represents the status of the tx reorder module of channel 0
+ */
+#define DMA2D_OUT_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x40)
+/** DMA2D_OUTFIFO_RO_CNT_CH0 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH0    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_M  (DMA2D_OUTFIFO_RO_CNT_CH0_V << DMA2D_OUTFIFO_RO_CNT_CH0_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH0_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH0_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH0 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_M  (DMA2D_OUT_RO_WR_STATE_CH0_V << DMA2D_OUT_RO_WR_STATE_CH0_S)
+#define DMA2D_OUT_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH0_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH0 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_M  (DMA2D_OUT_RO_RD_STATE_CH0_V << DMA2D_OUT_RO_RD_STATE_CH0_S)
+#define DMA2D_OUT_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH0_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH0 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_M  (DMA2D_OUT_PIXEL_BYTE_CH0_V << DMA2D_OUT_PIXEL_BYTE_CH0_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH0_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH0 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH0_V << DMA2D_OUT_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH0_S  14
+
+/** DMA2D_OUT_RO_PD_CONF_CH0_REG register
+ *  Configures the tx reorder memory of channel 0
+ */
+#define DMA2D_OUT_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x44)
+/** DMA2D_OUT_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 1;
+ *  unused! dma reorder ram power down
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_OUT_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 0;
+ *  unused! dma reorder ram power up
+ */
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_M  (DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V << DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_OUT_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_M  (DMA2D_OUT_RO_RAM_CLK_FO_CH0_V << DMA2D_OUT_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_OUT_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_OUT_COLOR_CONVERT_CH0_REG register
+ *  Configures the tx color convert of channel 0
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x48)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH0_V << DMA2D_OUT_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH0_REG register
+ *  Configures the tx scramble of channel 0
+ */
+#define DMA2D_OUT_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x4c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x50)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_M  (DMA2D_OUT_COLOR_PARAM_H0_CH0_V << DMA2D_OUT_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x54)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_M  (DMA2D_OUT_COLOR_PARAM_H1_CH0_V << DMA2D_OUT_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x58)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_M  (DMA2D_OUT_COLOR_PARAM_M0_CH0_V << DMA2D_OUT_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x5c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_M  (DMA2D_OUT_COLOR_PARAM_M1_CH0_V << DMA2D_OUT_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x60)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_M  (DMA2D_OUT_COLOR_PARAM_L0_CH0_V << DMA2D_OUT_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH0_REG register
+ *  Configures the tx color convert parameter of channel 0
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x64)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_M  (DMA2D_OUT_COLOR_PARAM_L1_CH0_V << DMA2D_OUT_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH0_REG register
+ *  Configures the tx etm of channel 0
+ */
+#define DMA2D_OUT_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x68)
+/** DMA2D_OUT_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH0    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH0_M  (DMA2D_OUT_ETM_EN_CH0_V << DMA2D_OUT_ETM_EN_CH0_S)
+#define DMA2D_OUT_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH0_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_M  (DMA2D_OUT_ETM_LOOP_EN_CH0_V << DMA2D_OUT_ETM_LOOP_EN_CH0_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_M  (DMA2D_OUT_DSCR_TASK_MAK_CH0_V << DMA2D_OUT_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH0_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH0_REG (DR_REG_DMA2D_BASE + 0x6c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH0 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH0_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH0 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH0_S  14
+
+/** DMA2D_OUT_CONF0_CH1_REG register
+ *  Configures the tx direction of channel 1
+ */
+#define DMA2D_OUT_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x100)
+/** DMA2D_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH1    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH1_M  (DMA2D_OUT_AUTO_WRBACK_CH1_V << DMA2D_OUT_AUTO_WRBACK_CH1_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH1_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH1_S  0
+/** DMA2D_OUT_EOF_MODE_CH1 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH1    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH1_M  (DMA2D_OUT_EOF_MODE_CH1_V << DMA2D_OUT_EOF_MODE_CH1_S)
+#define DMA2D_OUT_EOF_MODE_CH1_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH1_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH1_M  (DMA2D_OUTDSCR_BURST_EN_CH1_V << DMA2D_OUTDSCR_BURST_EN_CH1_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH1_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH1_M  (DMA2D_OUT_ECC_AES_EN_CH1_V << DMA2D_OUT_ECC_AES_EN_CH1_S)
+#define DMA2D_OUT_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH1_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH1_M  (DMA2D_OUT_CHECK_OWNER_CH1_V << DMA2D_OUT_CHECK_OWNER_CH1_S)
+#define DMA2D_OUT_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH1_S  4
+/** DMA2D_OUT_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH1_M  (DMA2D_OUT_LOOP_TEST_CH1_V << DMA2D_OUT_LOOP_TEST_CH1_S)
+#define DMA2D_OUT_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH1_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH1_V << DMA2D_OUT_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_M  (DMA2D_OUT_DSCR_PORT_EN_CH1_V << DMA2D_OUT_DSCR_PORT_EN_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_M  (DMA2D_OUT_PAGE_BOUND_EN_CH1_V << DMA2D_OUT_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_OUT_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH1_M  (DMA2D_OUT_REORDER_EN_CH1_V << DMA2D_OUT_REORDER_EN_CH1_S)
+#define DMA2D_OUT_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH1_S  16
+/** DMA2D_OUT_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH1    (BIT(24))
+#define DMA2D_OUT_RST_CH1_M  (DMA2D_OUT_RST_CH1_V << DMA2D_OUT_RST_CH1_S)
+#define DMA2D_OUT_RST_CH1_V  0x00000001U
+#define DMA2D_OUT_RST_CH1_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH1_M  (DMA2D_OUT_CMD_DISABLE_CH1_V << DMA2D_OUT_CMD_DISABLE_CH1_S)
+#define DMA2D_OUT_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH1_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_OUT_INT_RAW_CH1_REG register
+ *  Raw interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x104)
+/** DMA2D_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_RAW_M  (DMA2D_OUT_DONE_CH1_INT_RAW_V << DMA2D_OUT_DONE_CH1_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_RAW_M  (DMA2D_OUT_EOF_CH1_INT_RAW_V << DMA2D_OUT_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x108)
+/** DMA2D_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ENA_M  (DMA2D_OUT_DONE_CH1_INT_ENA_V << DMA2D_OUT_DONE_CH1_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ENA_M  (DMA2D_OUT_EOF_CH1_INT_ENA_V << DMA2D_OUT_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH1_REG register
+ *  Masked interrupt status of TX channel 1
+ */
+#define DMA2D_OUT_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x10c)
+/** DMA2D_OUT_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_ST_M  (DMA2D_OUT_DONE_CH1_INT_ST_V << DMA2D_OUT_DONE_CH1_INT_ST_S)
+#define DMA2D_OUT_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_ST_M  (DMA2D_OUT_EOF_CH1_INT_ST_V << DMA2D_OUT_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of TX channel 1
+ */
+#define DMA2D_OUT_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x110)
+/** DMA2D_OUT_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH1_INT_CLR_M  (DMA2D_OUT_DONE_CH1_INT_CLR_V << DMA2D_OUT_DONE_CH1_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH1_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH1_INT_CLR_M  (DMA2D_OUT_EOF_CH1_INT_CLR_V << DMA2D_OUT_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH1_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH1_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH1_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH1_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH1_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH1_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH1_REG register
+ *  Represents the status of the tx fifo of channel 1
+ */
+#define DMA2D_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x114)
+/** DMA2D_OUTFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH1_M  (DMA2D_OUTFIFO_FULL_L2_CH1_V << DMA2D_OUTFIFO_FULL_L2_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH1_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_M  (DMA2D_OUTFIFO_EMPTY_L2_CH1_V << DMA2D_OUTFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_M  (DMA2D_OUTFIFO_CNT_L2_CH1_V << DMA2D_OUTFIFO_CNT_L2_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH1_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH1_V << DMA2D_OUT_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH1_V << DMA2D_OUT_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH1_V << DMA2D_OUT_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH1_V << DMA2D_OUT_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH1_V << DMA2D_OUT_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH1_V << DMA2D_OUT_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH1_V << DMA2D_OUT_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH1_V << DMA2D_OUT_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH1_M  (DMA2D_OUTFIFO_FULL_L1_CH1_V << DMA2D_OUTFIFO_FULL_L1_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH1_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_M  (DMA2D_OUTFIFO_EMPTY_L1_CH1_V << DMA2D_OUTFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_M  (DMA2D_OUTFIFO_CNT_L1_CH1_V << DMA2D_OUTFIFO_CNT_L1_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH1_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH1_M  (DMA2D_OUTFIFO_FULL_L3_CH1_V << DMA2D_OUTFIFO_FULL_L3_CH1_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH1_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_M  (DMA2D_OUTFIFO_EMPTY_L3_CH1_V << DMA2D_OUTFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_M  (DMA2D_OUTFIFO_CNT_L3_CH1_V << DMA2D_OUTFIFO_CNT_L3_CH1_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_OUT_PUSH_CH1_REG register
+ *  Configures the tx fifo of channel 1
+ */
+#define DMA2D_OUT_PUSH_CH1_REG (DR_REG_DMA2D_BASE + 0x118)
+/** DMA2D_OUTFIFO_WDATA_CH1 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH1    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_M  (DMA2D_OUTFIFO_WDATA_CH1_V << DMA2D_OUTFIFO_WDATA_CH1_S)
+#define DMA2D_OUTFIFO_WDATA_CH1_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH1_S  0
+/** DMA2D_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH1    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH1_M  (DMA2D_OUTFIFO_PUSH_CH1_V << DMA2D_OUTFIFO_PUSH_CH1_S)
+#define DMA2D_OUTFIFO_PUSH_CH1_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH1_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH1_REG register
+ *  Configures the tx descriptor operations of channel 1
+ */
+#define DMA2D_OUT_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x11c)
+/** DMA2D_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH1    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH1_M  (DMA2D_OUTLINK_STOP_CH1_V << DMA2D_OUTLINK_STOP_CH1_S)
+#define DMA2D_OUTLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH1_S  20
+/** DMA2D_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH1    (BIT(21))
+#define DMA2D_OUTLINK_START_CH1_M  (DMA2D_OUTLINK_START_CH1_V << DMA2D_OUTLINK_START_CH1_S)
+#define DMA2D_OUTLINK_START_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH1_S  21
+/** DMA2D_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH1    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH1_M  (DMA2D_OUTLINK_RESTART_CH1_V << DMA2D_OUTLINK_RESTART_CH1_S)
+#define DMA2D_OUTLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH1_S  22
+/** DMA2D_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH1    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH1_M  (DMA2D_OUTLINK_PARK_CH1_V << DMA2D_OUTLINK_PARK_CH1_S)
+#define DMA2D_OUTLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH1_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH1_REG register
+ *  Configures the tx descriptor address of channel 1
+ */
+#define DMA2D_OUT_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x120)
+/** DMA2D_OUTLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_M  (DMA2D_OUTLINK_ADDR_CH1_V << DMA2D_OUTLINK_ADDR_CH1_S)
+#define DMA2D_OUTLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH1_S  0
+
+/** DMA2D_OUT_STATE_CH1_REG register
+ *  Represents the working status of the tx descriptor of channel 1
+ */
+#define DMA2D_OUT_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x124)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_M  (DMA2D_OUTLINK_DSCR_ADDR_CH1_V << DMA2D_OUTLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_M  (DMA2D_OUT_DSCR_STATE_CH1_V << DMA2D_OUT_DSCR_STATE_CH1_S)
+#define DMA2D_OUT_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH1_S  18
+/** DMA2D_OUT_STATE_CH1 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH1    0x0000000FU
+#define DMA2D_OUT_STATE_CH1_M  (DMA2D_OUT_STATE_CH1_V << DMA2D_OUT_STATE_CH1_S)
+#define DMA2D_OUT_STATE_CH1_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH1_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH1 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH1    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH1_M  (DMA2D_OUT_RESET_AVAIL_CH1_V << DMA2D_OUT_RESET_AVAIL_CH1_S)
+#define DMA2D_OUT_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH1_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x128)
+/** DMA2D_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_M  (DMA2D_OUT_EOF_DES_ADDR_CH1_V << DMA2D_OUT_EOF_DES_ADDR_CH1_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x12c)
+/** DMA2D_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_M  (DMA2D_OUTLINK_DSCR_CH1_V << DMA2D_OUTLINK_DSCR_CH1_S)
+#define DMA2D_OUTLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x130)
+/** DMA2D_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_M  (DMA2D_OUTLINK_DSCR_BF0_CH1_V << DMA2D_OUTLINK_DSCR_BF0_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the outlink descriptor of channel 1
+ */
+#define DMA2D_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x134)
+/** DMA2D_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_M  (DMA2D_OUTLINK_DSCR_BF1_CH1_V << DMA2D_OUTLINK_DSCR_BF1_CH1_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH1_REG register
+ *  Configures the tx peripheral of channel 1
+ */
+#define DMA2D_OUT_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x138)
+/** DMA2D_OUT_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH1    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_M  (DMA2D_OUT_PERI_SEL_CH1_V << DMA2D_OUT_PERI_SEL_CH1_S)
+#define DMA2D_OUT_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH1_S  0
+
+/** DMA2D_OUT_ARB_CH1_REG register
+ *  Configures the tx arbiter of channel 1
+ */
+#define DMA2D_OUT_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x13c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH1_V << DMA2D_OUT_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH1    0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH1_M  (DMA2D_OUT_ARB_PRIORITY_CH1_V << DMA2D_OUT_ARB_PRIORITY_CH1_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH1_V  0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH1_REG register
+ *  Represents the status of the tx reorder module of channel 1
+ */
+#define DMA2D_OUT_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x140)
+/** DMA2D_OUTFIFO_RO_CNT_CH1 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH1    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_M  (DMA2D_OUTFIFO_RO_CNT_CH1_V << DMA2D_OUTFIFO_RO_CNT_CH1_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH1_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH1_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH1 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_M  (DMA2D_OUT_RO_WR_STATE_CH1_V << DMA2D_OUT_RO_WR_STATE_CH1_S)
+#define DMA2D_OUT_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH1_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH1 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_M  (DMA2D_OUT_RO_RD_STATE_CH1_V << DMA2D_OUT_RO_RD_STATE_CH1_S)
+#define DMA2D_OUT_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH1_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH1 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_M  (DMA2D_OUT_PIXEL_BYTE_CH1_V << DMA2D_OUT_PIXEL_BYTE_CH1_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH1_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH1 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH1_V << DMA2D_OUT_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH1_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH1_REG register
+ *  Configures the tx color convert of channel 1
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH1_REG (DR_REG_DMA2D_BASE + 0x148)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH1_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH1_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH1 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH1_V << DMA2D_OUT_COLOR_INPUT_SEL_CH1_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH1_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH1_REG register
+ *  Configures the tx scramble of channel 1
+ */
+#define DMA2D_OUT_SCRAMBLE_CH1_REG (DR_REG_DMA2D_BASE + 0x14c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH1_REG (DR_REG_DMA2D_BASE + 0x150)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH1 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_M  (DMA2D_OUT_COLOR_PARAM_H0_CH1_V << DMA2D_OUT_COLOR_PARAM_H0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH1_REG (DR_REG_DMA2D_BASE + 0x154)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH1 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_M  (DMA2D_OUT_COLOR_PARAM_H1_CH1_V << DMA2D_OUT_COLOR_PARAM_H1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH1_REG (DR_REG_DMA2D_BASE + 0x158)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH1 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_M  (DMA2D_OUT_COLOR_PARAM_M0_CH1_V << DMA2D_OUT_COLOR_PARAM_M0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH1_REG (DR_REG_DMA2D_BASE + 0x15c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH1 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_M  (DMA2D_OUT_COLOR_PARAM_M1_CH1_V << DMA2D_OUT_COLOR_PARAM_M1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH1_REG (DR_REG_DMA2D_BASE + 0x160)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH1 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_M  (DMA2D_OUT_COLOR_PARAM_L0_CH1_V << DMA2D_OUT_COLOR_PARAM_L0_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH1_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH1_REG register
+ *  Configures the tx color convert parameter of channel 1
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH1_REG (DR_REG_DMA2D_BASE + 0x164)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH1 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_M  (DMA2D_OUT_COLOR_PARAM_L1_CH1_V << DMA2D_OUT_COLOR_PARAM_L1_CH1_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH1_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH1_REG register
+ *  Configures the tx etm of channel 1
+ */
+#define DMA2D_OUT_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x168)
+/** DMA2D_OUT_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH1    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH1_M  (DMA2D_OUT_ETM_EN_CH1_V << DMA2D_OUT_ETM_EN_CH1_S)
+#define DMA2D_OUT_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH1_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_M  (DMA2D_OUT_ETM_LOOP_EN_CH1_V << DMA2D_OUT_ETM_LOOP_EN_CH1_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_M  (DMA2D_OUT_DSCR_TASK_MAK_CH1_V << DMA2D_OUT_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH1_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH1_REG (DR_REG_DMA2D_BASE + 0x16c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH1 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH1_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH1 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH1_S  14
+
+/** DMA2D_OUT_CONF0_CH2_REG register
+ *  Configures the tx direction of channel 2
+ */
+#define DMA2D_OUT_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x200)
+/** DMA2D_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH2    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH2_M  (DMA2D_OUT_AUTO_WRBACK_CH2_V << DMA2D_OUT_AUTO_WRBACK_CH2_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH2_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH2_S  0
+/** DMA2D_OUT_EOF_MODE_CH2 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH2    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH2_M  (DMA2D_OUT_EOF_MODE_CH2_V << DMA2D_OUT_EOF_MODE_CH2_S)
+#define DMA2D_OUT_EOF_MODE_CH2_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH2_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH2_M  (DMA2D_OUTDSCR_BURST_EN_CH2_V << DMA2D_OUTDSCR_BURST_EN_CH2_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH2_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH2_M  (DMA2D_OUT_ECC_AES_EN_CH2_V << DMA2D_OUT_ECC_AES_EN_CH2_S)
+#define DMA2D_OUT_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH2_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH2_M  (DMA2D_OUT_CHECK_OWNER_CH2_V << DMA2D_OUT_CHECK_OWNER_CH2_S)
+#define DMA2D_OUT_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH2_S  4
+/** DMA2D_OUT_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH2_M  (DMA2D_OUT_LOOP_TEST_CH2_V << DMA2D_OUT_LOOP_TEST_CH2_S)
+#define DMA2D_OUT_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH2_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH2_V << DMA2D_OUT_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_M  (DMA2D_OUT_DSCR_PORT_EN_CH2_V << DMA2D_OUT_DSCR_PORT_EN_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_M  (DMA2D_OUT_PAGE_BOUND_EN_CH2_V << DMA2D_OUT_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_OUT_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH2_M  (DMA2D_OUT_REORDER_EN_CH2_V << DMA2D_OUT_REORDER_EN_CH2_S)
+#define DMA2D_OUT_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH2_S  16
+/** DMA2D_OUT_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH2    (BIT(24))
+#define DMA2D_OUT_RST_CH2_M  (DMA2D_OUT_RST_CH2_V << DMA2D_OUT_RST_CH2_S)
+#define DMA2D_OUT_RST_CH2_V  0x00000001U
+#define DMA2D_OUT_RST_CH2_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH2_M  (DMA2D_OUT_CMD_DISABLE_CH2_V << DMA2D_OUT_CMD_DISABLE_CH2_S)
+#define DMA2D_OUT_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH2_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_OUT_INT_RAW_CH2_REG register
+ *  Raw interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x204)
+/** DMA2D_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_RAW_M  (DMA2D_OUT_DONE_CH2_INT_RAW_V << DMA2D_OUT_DONE_CH2_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_RAW_M  (DMA2D_OUT_EOF_CH2_INT_RAW_V << DMA2D_OUT_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x208)
+/** DMA2D_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ENA_M  (DMA2D_OUT_DONE_CH2_INT_ENA_V << DMA2D_OUT_DONE_CH2_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ENA_M  (DMA2D_OUT_EOF_CH2_INT_ENA_V << DMA2D_OUT_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH2_REG register
+ *  Masked interrupt status of TX channel 2
+ */
+#define DMA2D_OUT_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x20c)
+/** DMA2D_OUT_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_ST_M  (DMA2D_OUT_DONE_CH2_INT_ST_V << DMA2D_OUT_DONE_CH2_INT_ST_S)
+#define DMA2D_OUT_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_ST_M  (DMA2D_OUT_EOF_CH2_INT_ST_V << DMA2D_OUT_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of TX channel 2
+ */
+#define DMA2D_OUT_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x210)
+/** DMA2D_OUT_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH2_INT_CLR_M  (DMA2D_OUT_DONE_CH2_INT_CLR_V << DMA2D_OUT_DONE_CH2_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH2_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH2_INT_CLR_M  (DMA2D_OUT_EOF_CH2_INT_CLR_V << DMA2D_OUT_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH2_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH2_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH2_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH2_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH2_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH2_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH2_REG register
+ *  Represents the status of the tx fifo of channel 2
+ */
+#define DMA2D_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x214)
+/** DMA2D_OUTFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH2_M  (DMA2D_OUTFIFO_FULL_L2_CH2_V << DMA2D_OUTFIFO_FULL_L2_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH2_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_M  (DMA2D_OUTFIFO_EMPTY_L2_CH2_V << DMA2D_OUTFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_M  (DMA2D_OUTFIFO_CNT_L2_CH2_V << DMA2D_OUTFIFO_CNT_L2_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH2_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH2_V << DMA2D_OUT_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH2_V << DMA2D_OUT_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH2_V << DMA2D_OUT_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH2_V << DMA2D_OUT_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH2_V << DMA2D_OUT_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH2_V << DMA2D_OUT_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH2_V << DMA2D_OUT_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH2_V << DMA2D_OUT_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH2_M  (DMA2D_OUTFIFO_FULL_L1_CH2_V << DMA2D_OUTFIFO_FULL_L1_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH2_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_M  (DMA2D_OUTFIFO_EMPTY_L1_CH2_V << DMA2D_OUTFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_M  (DMA2D_OUTFIFO_CNT_L1_CH2_V << DMA2D_OUTFIFO_CNT_L1_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH2_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH2_M  (DMA2D_OUTFIFO_FULL_L3_CH2_V << DMA2D_OUTFIFO_FULL_L3_CH2_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH2_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_M  (DMA2D_OUTFIFO_EMPTY_L3_CH2_V << DMA2D_OUTFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_M  (DMA2D_OUTFIFO_CNT_L3_CH2_V << DMA2D_OUTFIFO_CNT_L3_CH2_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_OUT_PUSH_CH2_REG register
+ *  Configures the tx fifo of channel 2
+ */
+#define DMA2D_OUT_PUSH_CH2_REG (DR_REG_DMA2D_BASE + 0x218)
+/** DMA2D_OUTFIFO_WDATA_CH2 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH2    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_M  (DMA2D_OUTFIFO_WDATA_CH2_V << DMA2D_OUTFIFO_WDATA_CH2_S)
+#define DMA2D_OUTFIFO_WDATA_CH2_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH2_S  0
+/** DMA2D_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH2    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH2_M  (DMA2D_OUTFIFO_PUSH_CH2_V << DMA2D_OUTFIFO_PUSH_CH2_S)
+#define DMA2D_OUTFIFO_PUSH_CH2_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH2_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH2_REG register
+ *  Configures the tx descriptor operations of channel 2
+ */
+#define DMA2D_OUT_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x21c)
+/** DMA2D_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH2    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH2_M  (DMA2D_OUTLINK_STOP_CH2_V << DMA2D_OUTLINK_STOP_CH2_S)
+#define DMA2D_OUTLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH2_S  20
+/** DMA2D_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH2    (BIT(21))
+#define DMA2D_OUTLINK_START_CH2_M  (DMA2D_OUTLINK_START_CH2_V << DMA2D_OUTLINK_START_CH2_S)
+#define DMA2D_OUTLINK_START_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH2_S  21
+/** DMA2D_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH2    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH2_M  (DMA2D_OUTLINK_RESTART_CH2_V << DMA2D_OUTLINK_RESTART_CH2_S)
+#define DMA2D_OUTLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH2_S  22
+/** DMA2D_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH2    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH2_M  (DMA2D_OUTLINK_PARK_CH2_V << DMA2D_OUTLINK_PARK_CH2_S)
+#define DMA2D_OUTLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH2_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH2_REG register
+ *  Configures the tx descriptor address of channel 2
+ */
+#define DMA2D_OUT_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x220)
+/** DMA2D_OUTLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_M  (DMA2D_OUTLINK_ADDR_CH2_V << DMA2D_OUTLINK_ADDR_CH2_S)
+#define DMA2D_OUTLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH2_S  0
+
+/** DMA2D_OUT_STATE_CH2_REG register
+ *  Represents the working status of the tx descriptor of channel 2
+ */
+#define DMA2D_OUT_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x224)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_M  (DMA2D_OUTLINK_DSCR_ADDR_CH2_V << DMA2D_OUTLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_M  (DMA2D_OUT_DSCR_STATE_CH2_V << DMA2D_OUT_DSCR_STATE_CH2_S)
+#define DMA2D_OUT_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH2_S  18
+/** DMA2D_OUT_STATE_CH2 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH2    0x0000000FU
+#define DMA2D_OUT_STATE_CH2_M  (DMA2D_OUT_STATE_CH2_V << DMA2D_OUT_STATE_CH2_S)
+#define DMA2D_OUT_STATE_CH2_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH2_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH2 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH2    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH2_M  (DMA2D_OUT_RESET_AVAIL_CH2_V << DMA2D_OUT_RESET_AVAIL_CH2_S)
+#define DMA2D_OUT_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH2_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x228)
+/** DMA2D_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_M  (DMA2D_OUT_EOF_DES_ADDR_CH2_V << DMA2D_OUT_EOF_DES_ADDR_CH2_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x22c)
+/** DMA2D_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_M  (DMA2D_OUTLINK_DSCR_CH2_V << DMA2D_OUTLINK_DSCR_CH2_S)
+#define DMA2D_OUTLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x230)
+/** DMA2D_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_M  (DMA2D_OUTLINK_DSCR_BF0_CH2_V << DMA2D_OUTLINK_DSCR_BF0_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the outlink descriptor of channel 2
+ */
+#define DMA2D_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x234)
+/** DMA2D_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_M  (DMA2D_OUTLINK_DSCR_BF1_CH2_V << DMA2D_OUTLINK_DSCR_BF1_CH2_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH2_REG register
+ *  Configures the tx peripheral of channel 2
+ */
+#define DMA2D_OUT_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x238)
+/** DMA2D_OUT_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH2    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_M  (DMA2D_OUT_PERI_SEL_CH2_V << DMA2D_OUT_PERI_SEL_CH2_S)
+#define DMA2D_OUT_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH2_S  0
+
+/** DMA2D_OUT_ARB_CH2_REG register
+ *  Configures the tx arbiter of channel 2
+ */
+#define DMA2D_OUT_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x23c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH2_V << DMA2D_OUT_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH2    0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH2_M  (DMA2D_OUT_ARB_PRIORITY_CH2_V << DMA2D_OUT_ARB_PRIORITY_CH2_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH2_V  0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH2_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH2_REG register
+ *  Represents the status of the tx reorder module of channel 2
+ */
+#define DMA2D_OUT_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x240)
+/** DMA2D_OUTFIFO_RO_CNT_CH2 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH2    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_M  (DMA2D_OUTFIFO_RO_CNT_CH2_V << DMA2D_OUTFIFO_RO_CNT_CH2_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH2_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH2_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH2 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_M  (DMA2D_OUT_RO_WR_STATE_CH2_V << DMA2D_OUT_RO_WR_STATE_CH2_S)
+#define DMA2D_OUT_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH2_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH2 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_M  (DMA2D_OUT_RO_RD_STATE_CH2_V << DMA2D_OUT_RO_RD_STATE_CH2_S)
+#define DMA2D_OUT_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH2_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH2 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_M  (DMA2D_OUT_PIXEL_BYTE_CH2_V << DMA2D_OUT_PIXEL_BYTE_CH2_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH2_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH2 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH2_V << DMA2D_OUT_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH2_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH2_REG register
+ *  Configures the tx color convert of channel 2
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH2_REG (DR_REG_DMA2D_BASE + 0x248)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH2_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH2_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH2 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH2_V << DMA2D_OUT_COLOR_INPUT_SEL_CH2_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH2_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH2_REG register
+ *  Configures the tx scramble of channel 2
+ */
+#define DMA2D_OUT_SCRAMBLE_CH2_REG (DR_REG_DMA2D_BASE + 0x24c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH2_REG (DR_REG_DMA2D_BASE + 0x250)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH2 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_M  (DMA2D_OUT_COLOR_PARAM_H0_CH2_V << DMA2D_OUT_COLOR_PARAM_H0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH2_REG (DR_REG_DMA2D_BASE + 0x254)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH2 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_M  (DMA2D_OUT_COLOR_PARAM_H1_CH2_V << DMA2D_OUT_COLOR_PARAM_H1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH2_REG (DR_REG_DMA2D_BASE + 0x258)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH2 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_M  (DMA2D_OUT_COLOR_PARAM_M0_CH2_V << DMA2D_OUT_COLOR_PARAM_M0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH2_REG (DR_REG_DMA2D_BASE + 0x25c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH2 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_M  (DMA2D_OUT_COLOR_PARAM_M1_CH2_V << DMA2D_OUT_COLOR_PARAM_M1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH2_REG (DR_REG_DMA2D_BASE + 0x260)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH2 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_M  (DMA2D_OUT_COLOR_PARAM_L0_CH2_V << DMA2D_OUT_COLOR_PARAM_L0_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH2_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH2_REG register
+ *  Configures the tx color convert parameter of channel 2
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH2_REG (DR_REG_DMA2D_BASE + 0x264)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH2 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_M  (DMA2D_OUT_COLOR_PARAM_L1_CH2_V << DMA2D_OUT_COLOR_PARAM_L1_CH2_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH2_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH2_REG register
+ *  Configures the tx etm of channel 2
+ */
+#define DMA2D_OUT_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x268)
+/** DMA2D_OUT_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH2    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH2_M  (DMA2D_OUT_ETM_EN_CH2_V << DMA2D_OUT_ETM_EN_CH2_S)
+#define DMA2D_OUT_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH2_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_M  (DMA2D_OUT_ETM_LOOP_EN_CH2_V << DMA2D_OUT_ETM_LOOP_EN_CH2_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_M  (DMA2D_OUT_DSCR_TASK_MAK_CH2_V << DMA2D_OUT_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH2_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH2_REG (DR_REG_DMA2D_BASE + 0x26c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH2 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH2_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH2 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH2_S  14
+
+/** DMA2D_OUT_CONF0_CH3_REG register
+ *  Configures the tx direction of channel 3
+ */
+#define DMA2D_OUT_CONF0_CH3_REG (DR_REG_DMA2D_BASE + 0x300)
+/** DMA2D_OUT_AUTO_WRBACK_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+ *  outlink descriptor has been received.
+ */
+#define DMA2D_OUT_AUTO_WRBACK_CH3    (BIT(0))
+#define DMA2D_OUT_AUTO_WRBACK_CH3_M  (DMA2D_OUT_AUTO_WRBACK_CH3_V << DMA2D_OUT_AUTO_WRBACK_CH3_S)
+#define DMA2D_OUT_AUTO_WRBACK_CH3_V  0x00000001U
+#define DMA2D_OUT_AUTO_WRBACK_CH3_S  0
+/** DMA2D_OUT_EOF_MODE_CH3 : R/W; bitpos: [1]; default: 1;
+ *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+ *  generated when data need to read has been popped from FIFO in DMA
+ */
+#define DMA2D_OUT_EOF_MODE_CH3    (BIT(1))
+#define DMA2D_OUT_EOF_MODE_CH3_M  (DMA2D_OUT_EOF_MODE_CH3_V << DMA2D_OUT_EOF_MODE_CH3_S)
+#define DMA2D_OUT_EOF_MODE_CH3_V  0x00000001U
+#define DMA2D_OUT_EOF_MODE_CH3_S  1
+/** DMA2D_OUTDSCR_BURST_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+ *  descriptor when accessing internal SRAM.
+ */
+#define DMA2D_OUTDSCR_BURST_EN_CH3    (BIT(2))
+#define DMA2D_OUTDSCR_BURST_EN_CH3_M  (DMA2D_OUTDSCR_BURST_EN_CH3_V << DMA2D_OUTDSCR_BURST_EN_CH3_S)
+#define DMA2D_OUTDSCR_BURST_EN_CH3_V  0x00000001U
+#define DMA2D_OUTDSCR_BURST_EN_CH3_S  2
+/** DMA2D_OUT_ECC_AES_EN_CH3 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_OUT_ECC_AES_EN_CH3    (BIT(3))
+#define DMA2D_OUT_ECC_AES_EN_CH3_M  (DMA2D_OUT_ECC_AES_EN_CH3_V << DMA2D_OUT_ECC_AES_EN_CH3_S)
+#define DMA2D_OUT_ECC_AES_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ECC_AES_EN_CH3_S  3
+/** DMA2D_OUT_CHECK_OWNER_CH3 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_OUT_CHECK_OWNER_CH3    (BIT(4))
+#define DMA2D_OUT_CHECK_OWNER_CH3_M  (DMA2D_OUT_CHECK_OWNER_CH3_V << DMA2D_OUT_CHECK_OWNER_CH3_S)
+#define DMA2D_OUT_CHECK_OWNER_CH3_V  0x00000001U
+#define DMA2D_OUT_CHECK_OWNER_CH3_S  4
+/** DMA2D_OUT_LOOP_TEST_CH3 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_LOOP_TEST_CH3    (BIT(5))
+#define DMA2D_OUT_LOOP_TEST_CH3_M  (DMA2D_OUT_LOOP_TEST_CH3_V << DMA2D_OUT_LOOP_TEST_CH3_S)
+#define DMA2D_OUT_LOOP_TEST_CH3_V  0x00000001U
+#define DMA2D_OUT_LOOP_TEST_CH3_S  5
+/** DMA2D_OUT_MEM_BURST_LENGTH_CH3 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3    0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_M  (DMA2D_OUT_MEM_BURST_LENGTH_CH3_V << DMA2D_OUT_MEM_BURST_LENGTH_CH3_S)
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_V  0x00000007U
+#define DMA2D_OUT_MEM_BURST_LENGTH_CH3_S  6
+/** DMA2D_OUT_MACRO_BLOCK_SIZE_CH3 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3    0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_M  (DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V << DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S)
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_V  0x00000003U
+#define DMA2D_OUT_MACRO_BLOCK_SIZE_CH3_S  9
+/** DMA2D_OUT_DSCR_PORT_EN_CH3 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_OUT_DSCR_PORT_EN_CH3    (BIT(11))
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_M  (DMA2D_OUT_DSCR_PORT_EN_CH3_V << DMA2D_OUT_DSCR_PORT_EN_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_DSCR_PORT_EN_CH3_S  11
+/** DMA2D_OUT_PAGE_BOUND_EN_CH3 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+ *  define by mem_burst_length
+ */
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3    (BIT(12))
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_M  (DMA2D_OUT_PAGE_BOUND_EN_CH3_V << DMA2D_OUT_PAGE_BOUND_EN_CH3_S)
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_PAGE_BOUND_EN_CH3_S  12
+/** DMA2D_OUT_REORDER_EN_CH3 : R/W; bitpos: [16]; default: 0;
+ *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_OUT_REORDER_EN_CH3    (BIT(16))
+#define DMA2D_OUT_REORDER_EN_CH3_M  (DMA2D_OUT_REORDER_EN_CH3_V << DMA2D_OUT_REORDER_EN_CH3_S)
+#define DMA2D_OUT_REORDER_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_REORDER_EN_CH3_S  16
+/** DMA2D_OUT_RST_CH3 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset TX channel
+ */
+#define DMA2D_OUT_RST_CH3    (BIT(24))
+#define DMA2D_OUT_RST_CH3_M  (DMA2D_OUT_RST_CH3_V << DMA2D_OUT_RST_CH3_S)
+#define DMA2D_OUT_RST_CH3_V  0x00000001U
+#define DMA2D_OUT_RST_CH3_S  24
+/** DMA2D_OUT_CMD_DISABLE_CH3 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_OUT_CMD_DISABLE_CH3    (BIT(25))
+#define DMA2D_OUT_CMD_DISABLE_CH3_M  (DMA2D_OUT_CMD_DISABLE_CH3_V << DMA2D_OUT_CMD_DISABLE_CH3_S)
+#define DMA2D_OUT_CMD_DISABLE_CH3_V  0x00000001U
+#define DMA2D_OUT_CMD_DISABLE_CH3_S  25
+/** DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3    (BIT(26))
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_M  (DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V << DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S)
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_V  0x00000001U
+#define DMA2D_OUT_ARB_WEIGHT_OPT_DIS_CH3_S  26
+
+/** DMA2D_OUT_INT_RAW_CH3_REG register
+ *  Raw interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_RAW_CH3_REG (DR_REG_DMA2D_BASE + 0x304)
+/** DMA2D_OUT_DONE_CH3_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been transmitted to peripherals for Tx channel 0.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_RAW    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_RAW_M  (DMA2D_OUT_DONE_CH3_INT_RAW_V << DMA2D_OUT_DONE_CH3_INT_RAW_S)
+#define DMA2D_OUT_DONE_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_RAW_S  0
+/** DMA2D_OUT_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+ *  descriptor has been read from memory for Tx channel 0.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_RAW    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_RAW_M  (DMA2D_OUT_EOF_CH3_INT_RAW_V << DMA2D_OUT_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_RAW_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+ *  including owner error, the second and third word error of outlink descriptor for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V << DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_RAW_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when data corresponding a outlink
+ *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+ *  channel 0.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_RAW_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_RAW_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_RAW_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_RAW_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_RAW_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_RAW_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_RAW_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_RAW_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_RAW_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_RAW_S  12
+
+/** DMA2D_OUT_INT_ENA_CH3_REG register
+ *  Interrupt enable bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_ENA_CH3_REG (DR_REG_DMA2D_BASE + 0x308)
+/** DMA2D_OUT_DONE_CH3_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ENA    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ENA_M  (DMA2D_OUT_DONE_CH3_INT_ENA_V << DMA2D_OUT_DONE_CH3_INT_ENA_S)
+#define DMA2D_OUT_DONE_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ENA_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ENA    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ENA_M  (DMA2D_OUT_EOF_CH3_INT_ENA_V << DMA2D_OUT_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ENA_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ENA_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ENA_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ENA_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ENA_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ENA_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ENA_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ENA_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ENA_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ENA_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ENA_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ENA_S  12
+
+/** DMA2D_OUT_INT_ST_CH3_REG register
+ *  Masked interrupt status of TX channel 3
+ */
+#define DMA2D_OUT_INT_ST_CH3_REG (DR_REG_DMA2D_BASE + 0x30c)
+/** DMA2D_OUT_DONE_CH3_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_ST    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_ST_M  (DMA2D_OUT_DONE_CH3_INT_ST_V << DMA2D_OUT_DONE_CH3_INT_ST_S)
+#define DMA2D_OUT_DONE_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_ST_S  0
+/** DMA2D_OUT_EOF_CH3_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_ST    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_ST_M  (DMA2D_OUT_EOF_CH3_INT_ST_V << DMA2D_OUT_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_ST_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V << DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_ST_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_ST_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_ST_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_ST_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_ST_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_ST_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_ST_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_ST_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_ST_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_ST_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_ST_S  12
+
+/** DMA2D_OUT_INT_CLR_CH3_REG register
+ *  Interrupt clear bits of TX channel 3
+ */
+#define DMA2D_OUT_INT_CLR_CH3_REG (DR_REG_DMA2D_BASE + 0x310)
+/** DMA2D_OUT_DONE_CH3_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DONE_CH3_INT_CLR    (BIT(0))
+#define DMA2D_OUT_DONE_CH3_INT_CLR_M  (DMA2D_OUT_DONE_CH3_INT_CLR_V << DMA2D_OUT_DONE_CH3_INT_CLR_S)
+#define DMA2D_OUT_DONE_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DONE_CH3_INT_CLR_S  0
+/** DMA2D_OUT_EOF_CH3_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_EOF_CH3_INT_CLR    (BIT(1))
+#define DMA2D_OUT_EOF_CH3_INT_CLR_M  (DMA2D_OUT_EOF_CH3_INT_CLR_V << DMA2D_OUT_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_EOF_CH3_INT_CLR_S  1
+/** DMA2D_OUT_DSCR_ERR_CH3_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR    (BIT(2))
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V << DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_ERR_CH3_INT_CLR_S  2
+/** DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR    (BIT(3))
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_M  (DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V << DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S)
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_TOTAL_EOF_CH3_INT_CLR_S  3
+/** DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR    (BIT(4))
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L1_CH3_INT_CLR_S  4
+/** DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR    (BIT(5))
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L1_CH3_INT_CLR_S  5
+/** DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR    (BIT(6))
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L2_CH3_INT_CLR_S  6
+/** DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR    (BIT(7))
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L2_CH3_INT_CLR_S  7
+/** DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR    (BIT(8))
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_OVF_L3_CH3_INT_CLR_S  8
+/** DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR    (BIT(9))
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_M  (DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V << DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_UDF_L3_CH3_INT_CLR_S  9
+/** DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR    (BIT(10))
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_OVF_CH3_INT_CLR_S  10
+/** DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR    (BIT(11))
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_M  (DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V << DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S)
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUTFIFO_RO_UDF_CH3_INT_CLR_S  11
+/** DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR    (BIT(12))
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_M  (DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V << DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S)
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_V  0x00000001U
+#define DMA2D_OUT_DSCR_TASK_OVF_CH3_INT_CLR_S  12
+
+/** DMA2D_OUTFIFO_STATUS_CH3_REG register
+ *  Represents the status of the tx fifo of channel 3
+ */
+#define DMA2D_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x314)
+/** DMA2D_OUTFIFO_FULL_L2_CH3 : RO; bitpos: [0]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L2_CH3    (BIT(0))
+#define DMA2D_OUTFIFO_FULL_L2_CH3_M  (DMA2D_OUTFIFO_FULL_L2_CH3_V << DMA2D_OUTFIFO_FULL_L2_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L2_CH3_S  0
+/** DMA2D_OUTFIFO_EMPTY_L2_CH3 : RO; bitpos: [1]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3    (BIT(1))
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_M  (DMA2D_OUTFIFO_EMPTY_L2_CH3_V << DMA2D_OUTFIFO_EMPTY_L2_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L2_CH3_S  1
+/** DMA2D_OUTFIFO_CNT_L2_CH3 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L2_CH3    0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_M  (DMA2D_OUTFIFO_CNT_L2_CH3_V << DMA2D_OUTFIFO_CNT_L2_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L2_CH3_V  0x0000000FU
+#define DMA2D_OUTFIFO_CNT_L2_CH3_S  2
+/** DMA2D_OUT_REMAIN_UNDER_1B_CH3 : RO; bitpos: [7]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3    (BIT(7))
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_1B_CH3_V << DMA2D_OUT_REMAIN_UNDER_1B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_1B_CH3_S  7
+/** DMA2D_OUT_REMAIN_UNDER_2B_CH3 : RO; bitpos: [8]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3    (BIT(8))
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_2B_CH3_V << DMA2D_OUT_REMAIN_UNDER_2B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_2B_CH3_S  8
+/** DMA2D_OUT_REMAIN_UNDER_3B_CH3 : RO; bitpos: [9]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3    (BIT(9))
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_3B_CH3_V << DMA2D_OUT_REMAIN_UNDER_3B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_3B_CH3_S  9
+/** DMA2D_OUT_REMAIN_UNDER_4B_CH3 : RO; bitpos: [10]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3    (BIT(10))
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_4B_CH3_V << DMA2D_OUT_REMAIN_UNDER_4B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_4B_CH3_S  10
+/** DMA2D_OUT_REMAIN_UNDER_5B_CH3 : RO; bitpos: [11]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3    (BIT(11))
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_5B_CH3_V << DMA2D_OUT_REMAIN_UNDER_5B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_5B_CH3_S  11
+/** DMA2D_OUT_REMAIN_UNDER_6B_CH3 : RO; bitpos: [12]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3    (BIT(12))
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_6B_CH3_V << DMA2D_OUT_REMAIN_UNDER_6B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_6B_CH3_S  12
+/** DMA2D_OUT_REMAIN_UNDER_7B_CH3 : RO; bitpos: [13]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3    (BIT(13))
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_7B_CH3_V << DMA2D_OUT_REMAIN_UNDER_7B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_7B_CH3_S  13
+/** DMA2D_OUT_REMAIN_UNDER_8B_CH3 : RO; bitpos: [14]; default: 1;
+ *  reserved
+ */
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3    (BIT(14))
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_M  (DMA2D_OUT_REMAIN_UNDER_8B_CH3_V << DMA2D_OUT_REMAIN_UNDER_8B_CH3_S)
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_V  0x00000001U
+#define DMA2D_OUT_REMAIN_UNDER_8B_CH3_S  14
+/** DMA2D_OUTFIFO_FULL_L1_CH3 : RO; bitpos: [15]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L1_CH3    (BIT(15))
+#define DMA2D_OUTFIFO_FULL_L1_CH3_M  (DMA2D_OUTFIFO_FULL_L1_CH3_V << DMA2D_OUTFIFO_FULL_L1_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L1_CH3_S  15
+/** DMA2D_OUTFIFO_EMPTY_L1_CH3 : RO; bitpos: [16]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3    (BIT(16))
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_M  (DMA2D_OUTFIFO_EMPTY_L1_CH3_V << DMA2D_OUTFIFO_EMPTY_L1_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L1_CH3_S  16
+/** DMA2D_OUTFIFO_CNT_L1_CH3 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L1_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_M  (DMA2D_OUTFIFO_CNT_L1_CH3_V << DMA2D_OUTFIFO_CNT_L1_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L1_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L1_CH3_S  17
+/** DMA2D_OUTFIFO_FULL_L3_CH3 : RO; bitpos: [22]; default: 0;
+ *  Tx FIFO full signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_FULL_L3_CH3    (BIT(22))
+#define DMA2D_OUTFIFO_FULL_L3_CH3_M  (DMA2D_OUTFIFO_FULL_L3_CH3_V << DMA2D_OUTFIFO_FULL_L3_CH3_S)
+#define DMA2D_OUTFIFO_FULL_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_FULL_L3_CH3_S  22
+/** DMA2D_OUTFIFO_EMPTY_L3_CH3 : RO; bitpos: [23]; default: 1;
+ *  Tx FIFO empty signal for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3    (BIT(23))
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_M  (DMA2D_OUTFIFO_EMPTY_L3_CH3_V << DMA2D_OUTFIFO_EMPTY_L3_CH3_S)
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_EMPTY_L3_CH3_S  23
+/** DMA2D_OUTFIFO_CNT_L3_CH3 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+ */
+#define DMA2D_OUTFIFO_CNT_L3_CH3    0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_M  (DMA2D_OUTFIFO_CNT_L3_CH3_V << DMA2D_OUTFIFO_CNT_L3_CH3_S)
+#define DMA2D_OUTFIFO_CNT_L3_CH3_V  0x0000001FU
+#define DMA2D_OUTFIFO_CNT_L3_CH3_S  24
+
+/** DMA2D_OUT_PUSH_CH3_REG register
+ *  Configures the tx fifo of channel 3
+ */
+#define DMA2D_OUT_PUSH_CH3_REG (DR_REG_DMA2D_BASE + 0x318)
+/** DMA2D_OUTFIFO_WDATA_CH3 : R/W; bitpos: [9:0]; default: 0;
+ *  This register stores the data that need to be pushed into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_WDATA_CH3    0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_M  (DMA2D_OUTFIFO_WDATA_CH3_V << DMA2D_OUTFIFO_WDATA_CH3_S)
+#define DMA2D_OUTFIFO_WDATA_CH3_V  0x000003FFU
+#define DMA2D_OUTFIFO_WDATA_CH3_S  0
+/** DMA2D_OUTFIFO_PUSH_CH3 : R/W/SC; bitpos: [10]; default: 0;
+ *  Set this bit to push data into DMA Tx FIFO.
+ */
+#define DMA2D_OUTFIFO_PUSH_CH3    (BIT(10))
+#define DMA2D_OUTFIFO_PUSH_CH3_M  (DMA2D_OUTFIFO_PUSH_CH3_V << DMA2D_OUTFIFO_PUSH_CH3_S)
+#define DMA2D_OUTFIFO_PUSH_CH3_V  0x00000001U
+#define DMA2D_OUTFIFO_PUSH_CH3_S  10
+
+/** DMA2D_OUT_LINK_CONF_CH3_REG register
+ *  Configures the tx descriptor operations of channel 3
+ */
+#define DMA2D_OUT_LINK_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x31c)
+/** DMA2D_OUTLINK_STOP_CH3 : R/W/SC; bitpos: [20]; default: 0;
+ *  Set this bit to stop dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_STOP_CH3    (BIT(20))
+#define DMA2D_OUTLINK_STOP_CH3_M  (DMA2D_OUTLINK_STOP_CH3_V << DMA2D_OUTLINK_STOP_CH3_S)
+#define DMA2D_OUTLINK_STOP_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_STOP_CH3_S  20
+/** DMA2D_OUTLINK_START_CH3 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to start dealing with the outlink descriptors.
+ */
+#define DMA2D_OUTLINK_START_CH3    (BIT(21))
+#define DMA2D_OUTLINK_START_CH3_M  (DMA2D_OUTLINK_START_CH3_V << DMA2D_OUTLINK_START_CH3_S)
+#define DMA2D_OUTLINK_START_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_START_CH3_S  21
+/** DMA2D_OUTLINK_RESTART_CH3 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to restart a new outlink from the last address.
+ */
+#define DMA2D_OUTLINK_RESTART_CH3    (BIT(22))
+#define DMA2D_OUTLINK_RESTART_CH3_M  (DMA2D_OUTLINK_RESTART_CH3_V << DMA2D_OUTLINK_RESTART_CH3_S)
+#define DMA2D_OUTLINK_RESTART_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_RESTART_CH3_S  22
+/** DMA2D_OUTLINK_PARK_CH3 : RO; bitpos: [23]; default: 1;
+ *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+ *  is working.
+ */
+#define DMA2D_OUTLINK_PARK_CH3    (BIT(23))
+#define DMA2D_OUTLINK_PARK_CH3_M  (DMA2D_OUTLINK_PARK_CH3_V << DMA2D_OUTLINK_PARK_CH3_S)
+#define DMA2D_OUTLINK_PARK_CH3_V  0x00000001U
+#define DMA2D_OUTLINK_PARK_CH3_S  23
+
+/** DMA2D_OUT_LINK_ADDR_CH3_REG register
+ *  Configures the tx descriptor address of channel 3
+ */
+#define DMA2D_OUT_LINK_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x320)
+/** DMA2D_OUTLINK_ADDR_CH3 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_M  (DMA2D_OUTLINK_ADDR_CH3_V << DMA2D_OUTLINK_ADDR_CH3_S)
+#define DMA2D_OUTLINK_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_ADDR_CH3_S  0
+
+/** DMA2D_OUT_STATE_CH3_REG register
+ *  Represents the working status of the tx descriptor of channel 3
+ */
+#define DMA2D_OUT_STATE_CH3_REG (DR_REG_DMA2D_BASE + 0x324)
+/** DMA2D_OUTLINK_DSCR_ADDR_CH3 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current outlink descriptor's address.
+ */
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3    0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_M  (DMA2D_OUTLINK_DSCR_ADDR_CH3_V << DMA2D_OUTLINK_DSCR_ADDR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_V  0x0003FFFFU
+#define DMA2D_OUTLINK_DSCR_ADDR_CH3_S  0
+/** DMA2D_OUT_DSCR_STATE_CH3 : RO; bitpos: [19:18]; default: 0;
+ *  This register stores the current descriptor state machine state.
+ */
+#define DMA2D_OUT_DSCR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_M  (DMA2D_OUT_DSCR_STATE_CH3_V << DMA2D_OUT_DSCR_STATE_CH3_S)
+#define DMA2D_OUT_DSCR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_STATE_CH3_S  18
+/** DMA2D_OUT_STATE_CH3 : RO; bitpos: [23:20]; default: 0;
+ *  This register stores the current control module state machine state.
+ */
+#define DMA2D_OUT_STATE_CH3    0x0000000FU
+#define DMA2D_OUT_STATE_CH3_M  (DMA2D_OUT_STATE_CH3_V << DMA2D_OUT_STATE_CH3_S)
+#define DMA2D_OUT_STATE_CH3_V  0x0000000FU
+#define DMA2D_OUT_STATE_CH3_S  20
+/** DMA2D_OUT_RESET_AVAIL_CH3 : RO; bitpos: [24]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_OUT_RESET_AVAIL_CH3    (BIT(24))
+#define DMA2D_OUT_RESET_AVAIL_CH3_M  (DMA2D_OUT_RESET_AVAIL_CH3_V << DMA2D_OUT_RESET_AVAIL_CH3_S)
+#define DMA2D_OUT_RESET_AVAIL_CH3_V  0x00000001U
+#define DMA2D_OUT_RESET_AVAIL_CH3_S  24
+
+/** DMA2D_OUT_EOF_DES_ADDR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA2D_BASE + 0x328)
+/** DMA2D_OUT_EOF_DES_ADDR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the outlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_OUT_EOF_DES_ADDR_CH3    0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_M  (DMA2D_OUT_EOF_DES_ADDR_CH3_V << DMA2D_OUT_EOF_DES_ADDR_CH3_S)
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUT_EOF_DES_ADDR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_CH3_REG (DR_REG_DMA2D_BASE + 0x32c)
+/** DMA2D_OUTLINK_DSCR_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next outlink descriptor address y.
+ */
+#define DMA2D_OUTLINK_DSCR_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_M  (DMA2D_OUTLINK_DSCR_CH3_V << DMA2D_OUTLINK_DSCR_CH3_S)
+#define DMA2D_OUTLINK_DSCR_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF0_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA2D_BASE + 0x330)
+/** DMA2D_OUTLINK_DSCR_BF0_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last outlink descriptor's next address y-1.
+ */
+#define DMA2D_OUTLINK_DSCR_BF0_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_M  (DMA2D_OUTLINK_DSCR_BF0_CH3_V << DMA2D_OUTLINK_DSCR_BF0_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF0_CH3_S  0
+
+/** DMA2D_OUT_DSCR_BF1_CH3_REG register
+ *  Represents the address associated with the outlink descriptor of channel 3
+ */
+#define DMA2D_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA2D_BASE + 0x334)
+/** DMA2D_OUTLINK_DSCR_BF1_CH3 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last outlink descriptor's next address y-2.
+ */
+#define DMA2D_OUTLINK_DSCR_BF1_CH3    0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_M  (DMA2D_OUTLINK_DSCR_BF1_CH3_V << DMA2D_OUTLINK_DSCR_BF1_CH3_S)
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_V  0xFFFFFFFFU
+#define DMA2D_OUTLINK_DSCR_BF1_CH3_S  0
+
+/** DMA2D_OUT_PERI_SEL_CH3_REG register
+ *  Configures the tx peripheral of channel 3
+ */
+#define DMA2D_OUT_PERI_SEL_CH3_REG (DR_REG_DMA2D_BASE + 0x338)
+/** DMA2D_OUT_PERI_SEL_CH3 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+ *  display-1     2: display-2     3: display-3      7: no choose
+ */
+#define DMA2D_OUT_PERI_SEL_CH3    0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_M  (DMA2D_OUT_PERI_SEL_CH3_V << DMA2D_OUT_PERI_SEL_CH3_S)
+#define DMA2D_OUT_PERI_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_PERI_SEL_CH3_S  0
+
+/** DMA2D_OUT_ARB_CH3_REG register
+ *  Configures the tx arbiter of channel 3
+ */
+#define DMA2D_OUT_ARB_CH3_REG (DR_REG_DMA2D_BASE + 0x33c)
+/** DMA2D_OUT_ARB_TOKEN_NUM_CH3 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_M  (DMA2D_OUT_ARB_TOKEN_NUM_CH3_V << DMA2D_OUT_ARB_TOKEN_NUM_CH3_S)
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_ARB_TOKEN_NUM_CH3_S  0
+/** DMA2D_OUT_ARB_PRIORITY_CH3 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_OUT_ARB_PRIORITY_CH3    0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH3_M  (DMA2D_OUT_ARB_PRIORITY_CH3_V << DMA2D_OUT_ARB_PRIORITY_CH3_S)
+#define DMA2D_OUT_ARB_PRIORITY_CH3_V  0x0000000FU
+#define DMA2D_OUT_ARB_PRIORITY_CH3_S  4
+
+/** DMA2D_OUT_RO_STATUS_CH3_REG register
+ *  Represents the status of the tx reorder module of channel 3
+ */
+#define DMA2D_OUT_RO_STATUS_CH3_REG (DR_REG_DMA2D_BASE + 0x340)
+/** DMA2D_OUTFIFO_RO_CNT_CH3 : RO; bitpos: [5:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Tx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_OUTFIFO_RO_CNT_CH3    0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_M  (DMA2D_OUTFIFO_RO_CNT_CH3_V << DMA2D_OUTFIFO_RO_CNT_CH3_S)
+#define DMA2D_OUTFIFO_RO_CNT_CH3_V  0x0000003FU
+#define DMA2D_OUTFIFO_RO_CNT_CH3_S  0
+/** DMA2D_OUT_RO_WR_STATE_CH3 : RO; bitpos: [7:6]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_OUT_RO_WR_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_M  (DMA2D_OUT_RO_WR_STATE_CH3_V << DMA2D_OUT_RO_WR_STATE_CH3_S)
+#define DMA2D_OUT_RO_WR_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_WR_STATE_CH3_S  6
+/** DMA2D_OUT_RO_RD_STATE_CH3 : RO; bitpos: [9:8]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_OUT_RO_RD_STATE_CH3    0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_M  (DMA2D_OUT_RO_RD_STATE_CH3_V << DMA2D_OUT_RO_RD_STATE_CH3_S)
+#define DMA2D_OUT_RO_RD_STATE_CH3_V  0x00000003U
+#define DMA2D_OUT_RO_RD_STATE_CH3_S  8
+/** DMA2D_OUT_PIXEL_BYTE_CH3 : RO; bitpos: [13:10]; default: 0;
+ *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_OUT_PIXEL_BYTE_CH3    0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_M  (DMA2D_OUT_PIXEL_BYTE_CH3_V << DMA2D_OUT_PIXEL_BYTE_CH3_S)
+#define DMA2D_OUT_PIXEL_BYTE_CH3_V  0x0000000FU
+#define DMA2D_OUT_PIXEL_BYTE_CH3_S  10
+/** DMA2D_OUT_BURST_BLOCK_NUM_CH3 : RO; bitpos: [17:14]; default: 0;
+ *  the number of macro blocks contained in a burst of data at TX channel
+ */
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3    0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_M  (DMA2D_OUT_BURST_BLOCK_NUM_CH3_V << DMA2D_OUT_BURST_BLOCK_NUM_CH3_S)
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_V  0x0000000FU
+#define DMA2D_OUT_BURST_BLOCK_NUM_CH3_S  14
+
+/** DMA2D_OUT_COLOR_CONVERT_CH3_REG register
+ *  Configures the tx color convert of channel 3
+ */
+#define DMA2D_OUT_COLOR_CONVERT_CH3_REG (DR_REG_DMA2D_BASE + 0x348)
+/** DMA2D_OUT_COLOR_OUTPUT_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  YUV444 to YUV422     2: output directly
+ */
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3    0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V << DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_V  0x00000003U
+#define DMA2D_OUT_COLOR_OUTPUT_SEL_CH3_S  0
+/** DMA2D_OUT_COLOR_3B_PROC_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3    (BIT(2))
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_M  (DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V << DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S)
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_COLOR_3B_PROC_EN_CH3_S  2
+/** DMA2D_OUT_COLOR_INPUT_SEL_CH3 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+ *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+ *  disable color space convert
+ */
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3    0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_M  (DMA2D_OUT_COLOR_INPUT_SEL_CH3_V << DMA2D_OUT_COLOR_INPUT_SEL_CH3_S)
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_V  0x00000007U
+#define DMA2D_OUT_COLOR_INPUT_SEL_CH3_S  3
+
+/** DMA2D_OUT_SCRAMBLE_CH3_REG register
+ *  Configures the tx scramble of channel 3
+ */
+#define DMA2D_OUT_SCRAMBLE_CH3_REG (DR_REG_DMA2D_BASE + 0x34c)
+/** DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3    0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_M  (DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V << DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S)
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_V  0x00000007U
+#define DMA2D_OUT_SCRAMBLE_SEL_PRE_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM0_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM0_CH3_REG (DR_REG_DMA2D_BASE + 0x350)
+/** DMA2D_OUT_COLOR_PARAM_H0_CH3 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_M  (DMA2D_OUT_COLOR_PARAM_H0_CH3_V << DMA2D_OUT_COLOR_PARAM_H0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM1_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM1_CH3_REG (DR_REG_DMA2D_BASE + 0x354)
+/** DMA2D_OUT_COLOR_PARAM_H1_CH3 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_M  (DMA2D_OUT_COLOR_PARAM_H1_CH3_V << DMA2D_OUT_COLOR_PARAM_H1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_H1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM2_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM2_CH3_REG (DR_REG_DMA2D_BASE + 0x358)
+/** DMA2D_OUT_COLOR_PARAM_M0_CH3 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_M  (DMA2D_OUT_COLOR_PARAM_M0_CH3_V << DMA2D_OUT_COLOR_PARAM_M0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM3_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM3_CH3_REG (DR_REG_DMA2D_BASE + 0x35c)
+/** DMA2D_OUT_COLOR_PARAM_M1_CH3 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_M  (DMA2D_OUT_COLOR_PARAM_M1_CH3_V << DMA2D_OUT_COLOR_PARAM_M1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_M1_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM4_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM4_CH3_REG (DR_REG_DMA2D_BASE + 0x360)
+/** DMA2D_OUT_COLOR_PARAM_L0_CH3 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3    0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_M  (DMA2D_OUT_COLOR_PARAM_L0_CH3_V << DMA2D_OUT_COLOR_PARAM_L0_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_V  0x001FFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L0_CH3_S  0
+
+/** DMA2D_OUT_COLOR_PARAM5_CH3_REG register
+ *  Configures the tx color convert parameter of channel 3
+ */
+#define DMA2D_OUT_COLOR_PARAM5_CH3_REG (DR_REG_DMA2D_BASE + 0x364)
+/** DMA2D_OUT_COLOR_PARAM_L1_CH3 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3    0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_M  (DMA2D_OUT_COLOR_PARAM_L1_CH3_V << DMA2D_OUT_COLOR_PARAM_L1_CH3_S)
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_V  0x0FFFFFFFU
+#define DMA2D_OUT_COLOR_PARAM_L1_CH3_S  0
+
+/** DMA2D_OUT_ETM_CONF_CH3_REG register
+ *  Configures the tx etm of channel 3
+ */
+#define DMA2D_OUT_ETM_CONF_CH3_REG (DR_REG_DMA2D_BASE + 0x368)
+/** DMA2D_OUT_ETM_EN_CH3 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_EN_CH3    (BIT(0))
+#define DMA2D_OUT_ETM_EN_CH3_M  (DMA2D_OUT_ETM_EN_CH3_V << DMA2D_OUT_ETM_EN_CH3_S)
+#define DMA2D_OUT_ETM_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_EN_CH3_S  0
+/** DMA2D_OUT_ETM_LOOP_EN_CH3 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_OUT_ETM_LOOP_EN_CH3    (BIT(1))
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_M  (DMA2D_OUT_ETM_LOOP_EN_CH3_V << DMA2D_OUT_ETM_LOOP_EN_CH3_S)
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_V  0x00000001U
+#define DMA2D_OUT_ETM_LOOP_EN_CH3_S  1
+/** DMA2D_OUT_DSCR_TASK_MAK_CH3 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3    0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_M  (DMA2D_OUT_DSCR_TASK_MAK_CH3_V << DMA2D_OUT_DSCR_TASK_MAK_CH3_S)
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_V  0x00000003U
+#define DMA2D_OUT_DSCR_TASK_MAK_CH3_S  2
+
+/** DMA2D_OUT_DSCR_PORT_BLK_CH3_REG register
+ *  Configures the tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_CH3_REG (DR_REG_DMA2D_BASE + 0x36c)
+/** DMA2D_OUT_DSCR_PORT_BLK_H_CH3 : R/W; bitpos: [13:0]; default: 18;
+ *  Set the vertical height of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_H_CH3_S  0
+/** DMA2D_OUT_DSCR_PORT_BLK_V_CH3 : R/W; bitpos: [27:14]; default: 18;
+ *  Set the horizontal width of tx block size in dscr port mode
+ */
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3    0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_M  (DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V << DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S)
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_V  0x00003FFFU
+#define DMA2D_OUT_DSCR_PORT_BLK_V_CH3_S  14
+
+/** DMA2D_IN_CONF0_CH0_REG register
+ *  Configures the rx direction of channel 0
+ */
+#define DMA2D_IN_CONF0_CH0_REG (DR_REG_DMA2D_BASE + 0x500)
+/** DMA2D_IN_MEM_TRANS_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH0    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH0_M  (DMA2D_IN_MEM_TRANS_EN_CH0_V << DMA2D_IN_MEM_TRANS_EN_CH0_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH0_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH0_S  0
+/** DMA2D_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH0    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH0_M  (DMA2D_INDSCR_BURST_EN_CH0_V << DMA2D_INDSCR_BURST_EN_CH0_S)
+#define DMA2D_INDSCR_BURST_EN_CH0_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH0_S  2
+/** DMA2D_IN_ECC_AES_EN_CH0 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH0    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH0_M  (DMA2D_IN_ECC_AES_EN_CH0_V << DMA2D_IN_ECC_AES_EN_CH0_S)
+#define DMA2D_IN_ECC_AES_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH0_S  3
+/** DMA2D_IN_CHECK_OWNER_CH0 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH0    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH0_M  (DMA2D_IN_CHECK_OWNER_CH0_V << DMA2D_IN_CHECK_OWNER_CH0_S)
+#define DMA2D_IN_CHECK_OWNER_CH0_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH0_S  4
+/** DMA2D_IN_LOOP_TEST_CH0 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH0    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH0_M  (DMA2D_IN_LOOP_TEST_CH0_V << DMA2D_IN_LOOP_TEST_CH0_S)
+#define DMA2D_IN_LOOP_TEST_CH0_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH0_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH0 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_M  (DMA2D_IN_MEM_BURST_LENGTH_CH0_V << DMA2D_IN_MEM_BURST_LENGTH_CH0_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH0_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH0 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH0_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH0 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH0    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH0_M  (DMA2D_IN_DSCR_PORT_EN_CH0_V << DMA2D_IN_DSCR_PORT_EN_CH0_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH0_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH0_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH0 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH0    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_M  (DMA2D_IN_PAGE_BOUND_EN_CH0_V << DMA2D_IN_PAGE_BOUND_EN_CH0_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH0_S  12
+/** DMA2D_IN_REORDER_EN_CH0 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH0    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH0_M  (DMA2D_IN_REORDER_EN_CH0_V << DMA2D_IN_REORDER_EN_CH0_S)
+#define DMA2D_IN_REORDER_EN_CH0_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH0_S  16
+/** DMA2D_IN_RST_CH0 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH0    (BIT(24))
+#define DMA2D_IN_RST_CH0_M  (DMA2D_IN_RST_CH0_V << DMA2D_IN_RST_CH0_S)
+#define DMA2D_IN_RST_CH0_V  0x00000001U
+#define DMA2D_IN_RST_CH0_S  24
+/** DMA2D_IN_CMD_DISABLE_CH0 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH0    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH0_M  (DMA2D_IN_CMD_DISABLE_CH0_V << DMA2D_IN_CMD_DISABLE_CH0_S)
+#define DMA2D_IN_CMD_DISABLE_CH0_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH0_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH0_S  26
+
+/** DMA2D_IN_INT_RAW_CH0_REG register
+ *  Raw interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_RAW_CH0_REG (DR_REG_DMA2D_BASE + 0x504)
+/** DMA2D_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH0_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_RAW_M  (DMA2D_IN_DONE_CH0_INT_RAW_V << DMA2D_IN_DONE_CH0_INT_RAW_S)
+#define DMA2D_IN_DONE_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH0_INT_RAW_V << DMA2D_IN_SUC_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH0_INT_RAW_V << DMA2D_IN_ERR_EOF_CH0_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH0_REG register
+ *  Interrupt enable bits of RX channel 0
+ */
+#define DMA2D_IN_INT_ENA_CH0_REG (DR_REG_DMA2D_BASE + 0x508)
+/** DMA2D_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ENA_M  (DMA2D_IN_DONE_CH0_INT_ENA_V << DMA2D_IN_DONE_CH0_INT_ENA_S)
+#define DMA2D_IN_DONE_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH0_INT_ENA_V << DMA2D_IN_SUC_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH0_INT_ENA_V << DMA2D_IN_ERR_EOF_CH0_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH0_REG register
+ *  Masked interrupt status of RX channel 0
+ */
+#define DMA2D_IN_INT_ST_CH0_REG (DR_REG_DMA2D_BASE + 0x50c)
+/** DMA2D_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_ST_M  (DMA2D_IN_DONE_CH0_INT_ST_V << DMA2D_IN_DONE_CH0_INT_ST_S)
+#define DMA2D_IN_DONE_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_M  (DMA2D_IN_SUC_EOF_CH0_INT_ST_V << DMA2D_IN_SUC_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_M  (DMA2D_IN_ERR_EOF_CH0_INT_ST_V << DMA2D_IN_ERR_EOF_CH0_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH0_INT_ST_V << DMA2D_IN_DSCR_ERR_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH0_REG register
+ *  Interrupt clear bits of RX channel 0
+ */
+#define DMA2D_IN_INT_CLR_CH0_REG (DR_REG_DMA2D_BASE + 0x510)
+/** DMA2D_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH0_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH0_INT_CLR_M  (DMA2D_IN_DONE_CH0_INT_CLR_V << DMA2D_IN_DONE_CH0_INT_CLR_S)
+#define DMA2D_IN_DONE_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH0_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH0_INT_CLR_V << DMA2D_IN_SUC_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH0_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH0_INT_CLR_V << DMA2D_IN_ERR_EOF_CH0_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH0_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH0_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH0_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH0_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH0_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH0_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH0_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH0_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH0_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH0_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH0_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH0_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH0_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH0_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH0_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH0_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH0_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH0_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH0_REG register
+ *  Represents the status of the rx fifo of channel 0
+ */
+#define DMA2D_INFIFO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x514)
+/** DMA2D_INFIFO_FULL_L2_CH0 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH0    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH0_M  (DMA2D_INFIFO_FULL_L2_CH0_V << DMA2D_INFIFO_FULL_L2_CH0_S)
+#define DMA2D_INFIFO_FULL_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH0_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH0 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH0    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH0_M  (DMA2D_INFIFO_EMPTY_L2_CH0_V << DMA2D_INFIFO_EMPTY_L2_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH0_S  1
+/** DMA2D_INFIFO_CNT_L2_CH0 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH0    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_M  (DMA2D_INFIFO_CNT_L2_CH0_V << DMA2D_INFIFO_CNT_L2_CH0_S)
+#define DMA2D_INFIFO_CNT_L2_CH0_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH0_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_M  (DMA2D_IN_REMAIN_UNDER_1B_CH0_V << DMA2D_IN_REMAIN_UNDER_1B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH0_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_M  (DMA2D_IN_REMAIN_UNDER_2B_CH0_V << DMA2D_IN_REMAIN_UNDER_2B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH0_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_M  (DMA2D_IN_REMAIN_UNDER_3B_CH0_V << DMA2D_IN_REMAIN_UNDER_3B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH0_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_M  (DMA2D_IN_REMAIN_UNDER_4B_CH0_V << DMA2D_IN_REMAIN_UNDER_4B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH0_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH0 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_M  (DMA2D_IN_REMAIN_UNDER_5B_CH0_V << DMA2D_IN_REMAIN_UNDER_5B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH0_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH0 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_M  (DMA2D_IN_REMAIN_UNDER_6B_CH0_V << DMA2D_IN_REMAIN_UNDER_6B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH0_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH0 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_M  (DMA2D_IN_REMAIN_UNDER_7B_CH0_V << DMA2D_IN_REMAIN_UNDER_7B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH0_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH0 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_M  (DMA2D_IN_REMAIN_UNDER_8B_CH0_V << DMA2D_IN_REMAIN_UNDER_8B_CH0_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH0_S  14
+/** DMA2D_INFIFO_FULL_L1_CH0 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH0    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH0_M  (DMA2D_INFIFO_FULL_L1_CH0_V << DMA2D_INFIFO_FULL_L1_CH0_S)
+#define DMA2D_INFIFO_FULL_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH0_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH0 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH0    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH0_M  (DMA2D_INFIFO_EMPTY_L1_CH0_V << DMA2D_INFIFO_EMPTY_L1_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH0_S  16
+/** DMA2D_INFIFO_CNT_L1_CH0 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_M  (DMA2D_INFIFO_CNT_L1_CH0_V << DMA2D_INFIFO_CNT_L1_CH0_S)
+#define DMA2D_INFIFO_CNT_L1_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH0_S  17
+/** DMA2D_INFIFO_FULL_L3_CH0 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH0    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH0_M  (DMA2D_INFIFO_FULL_L3_CH0_V << DMA2D_INFIFO_FULL_L3_CH0_S)
+#define DMA2D_INFIFO_FULL_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH0_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH0 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH0    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH0_M  (DMA2D_INFIFO_EMPTY_L3_CH0_V << DMA2D_INFIFO_EMPTY_L3_CH0_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH0_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH0_S  23
+/** DMA2D_INFIFO_CNT_L3_CH0 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH0    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_M  (DMA2D_INFIFO_CNT_L3_CH0_V << DMA2D_INFIFO_CNT_L3_CH0_S)
+#define DMA2D_INFIFO_CNT_L3_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH0_S  24
+
+/** DMA2D_IN_POP_CH0_REG register
+ *  Configures the rx fifo of channel 0
+ */
+#define DMA2D_IN_POP_CH0_REG (DR_REG_DMA2D_BASE + 0x518)
+/** DMA2D_INFIFO_RDATA_CH0 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH0    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_M  (DMA2D_INFIFO_RDATA_CH0_V << DMA2D_INFIFO_RDATA_CH0_S)
+#define DMA2D_INFIFO_RDATA_CH0_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH0_S  0
+/** DMA2D_INFIFO_POP_CH0 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH0    (BIT(11))
+#define DMA2D_INFIFO_POP_CH0_M  (DMA2D_INFIFO_POP_CH0_V << DMA2D_INFIFO_POP_CH0_S)
+#define DMA2D_INFIFO_POP_CH0_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH0_S  11
+
+/** DMA2D_IN_LINK_CONF_CH0_REG register
+ *  Configures the rx descriptor operations of channel 0
+ */
+#define DMA2D_IN_LINK_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x51c)
+/** DMA2D_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH0    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH0_M  (DMA2D_INLINK_AUTO_RET_CH0_V << DMA2D_INLINK_AUTO_RET_CH0_S)
+#define DMA2D_INLINK_AUTO_RET_CH0_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH0_S  20
+/** DMA2D_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH0    (BIT(21))
+#define DMA2D_INLINK_STOP_CH0_M  (DMA2D_INLINK_STOP_CH0_V << DMA2D_INLINK_STOP_CH0_S)
+#define DMA2D_INLINK_STOP_CH0_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH0_S  21
+/** DMA2D_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH0    (BIT(22))
+#define DMA2D_INLINK_START_CH0_M  (DMA2D_INLINK_START_CH0_V << DMA2D_INLINK_START_CH0_S)
+#define DMA2D_INLINK_START_CH0_V  0x00000001U
+#define DMA2D_INLINK_START_CH0_S  22
+/** DMA2D_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH0    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH0_M  (DMA2D_INLINK_RESTART_CH0_V << DMA2D_INLINK_RESTART_CH0_S)
+#define DMA2D_INLINK_RESTART_CH0_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH0_S  23
+/** DMA2D_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH0    (BIT(24))
+#define DMA2D_INLINK_PARK_CH0_M  (DMA2D_INLINK_PARK_CH0_V << DMA2D_INLINK_PARK_CH0_S)
+#define DMA2D_INLINK_PARK_CH0_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH0_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH0_REG register
+ *  Configures the rx descriptor address of channel 0
+ */
+#define DMA2D_IN_LINK_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x520)
+/** DMA2D_INLINK_ADDR_CH0 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_M  (DMA2D_INLINK_ADDR_CH0_V << DMA2D_INLINK_ADDR_CH0_S)
+#define DMA2D_INLINK_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH0_S  0
+
+/** DMA2D_IN_STATE_CH0_REG register
+ *  Represents the working status of the rx descriptor of channel 0
+ */
+#define DMA2D_IN_STATE_CH0_REG (DR_REG_DMA2D_BASE + 0x524)
+/** DMA2D_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH0    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_M  (DMA2D_INLINK_DSCR_ADDR_CH0_V << DMA2D_INLINK_DSCR_ADDR_CH0_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH0_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH0_S  0
+/** DMA2D_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH0    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_M  (DMA2D_IN_DSCR_STATE_CH0_V << DMA2D_IN_DSCR_STATE_CH0_S)
+#define DMA2D_IN_DSCR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH0_S  18
+/** DMA2D_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH0    0x00000007U
+#define DMA2D_IN_STATE_CH0_M  (DMA2D_IN_STATE_CH0_V << DMA2D_IN_STATE_CH0_S)
+#define DMA2D_IN_STATE_CH0_V  0x00000007U
+#define DMA2D_IN_STATE_CH0_S  20
+/** DMA2D_IN_RESET_AVAIL_CH0 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH0    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH0_M  (DMA2D_IN_RESET_AVAIL_CH0_V << DMA2D_IN_RESET_AVAIL_CH0_S)
+#define DMA2D_IN_RESET_AVAIL_CH0_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH0_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x528)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA2D_BASE + 0x52c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH0_S  0
+
+/** DMA2D_IN_DSCR_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_CH0_REG (DR_REG_DMA2D_BASE + 0x530)
+/** DMA2D_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_M  (DMA2D_INLINK_DSCR_CH0_V << DMA2D_INLINK_DSCR_CH0_S)
+#define DMA2D_INLINK_DSCR_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF0_CH0_REG (DR_REG_DMA2D_BASE + 0x534)
+/** DMA2D_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_M  (DMA2D_INLINK_DSCR_BF0_CH0_V << DMA2D_INLINK_DSCR_BF0_CH0_S)
+#define DMA2D_INLINK_DSCR_BF0_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH0_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH0_REG register
+ *  Represents the address associated with the inlink descriptor of channel 0
+ */
+#define DMA2D_IN_DSCR_BF1_CH0_REG (DR_REG_DMA2D_BASE + 0x538)
+/** DMA2D_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH0    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_M  (DMA2D_INLINK_DSCR_BF1_CH0_V << DMA2D_INLINK_DSCR_BF1_CH0_S)
+#define DMA2D_INLINK_DSCR_BF1_CH0_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH0_S  0
+
+/** DMA2D_IN_PERI_SEL_CH0_REG register
+ *  Configures the rx peripheral of channel 0
+ */
+#define DMA2D_IN_PERI_SEL_CH0_REG (DR_REG_DMA2D_BASE + 0x53c)
+/** DMA2D_IN_PERI_SEL_CH0 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH0    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_M  (DMA2D_IN_PERI_SEL_CH0_V << DMA2D_IN_PERI_SEL_CH0_S)
+#define DMA2D_IN_PERI_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH0_S  0
+
+/** DMA2D_IN_ARB_CH0_REG register
+ *  Configures the rx arbiter of channel 0
+ */
+#define DMA2D_IN_ARB_CH0_REG (DR_REG_DMA2D_BASE + 0x540)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH0 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_M  (DMA2D_IN_ARB_TOKEN_NUM_CH0_V << DMA2D_IN_ARB_TOKEN_NUM_CH0_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH0_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH0 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH0    0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH0_M  (DMA2D_IN_ARB_PRIORITY_CH0_V << DMA2D_IN_ARB_PRIORITY_CH0_S)
+#define DMA2D_IN_ARB_PRIORITY_CH0_V  0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH0_S  4
+
+/** DMA2D_IN_RO_STATUS_CH0_REG register
+ *  Represents the status of the rx reorder module of channel 0
+ */
+#define DMA2D_IN_RO_STATUS_CH0_REG (DR_REG_DMA2D_BASE + 0x544)
+/** DMA2D_INFIFO_RO_CNT_CH0 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH0    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_M  (DMA2D_INFIFO_RO_CNT_CH0_V << DMA2D_INFIFO_RO_CNT_CH0_S)
+#define DMA2D_INFIFO_RO_CNT_CH0_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH0_S  0
+/** DMA2D_IN_RO_WR_STATE_CH0 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_M  (DMA2D_IN_RO_WR_STATE_CH0_V << DMA2D_IN_RO_WR_STATE_CH0_S)
+#define DMA2D_IN_RO_WR_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH0_S  5
+/** DMA2D_IN_RO_RD_STATE_CH0 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH0    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_M  (DMA2D_IN_RO_RD_STATE_CH0_V << DMA2D_IN_RO_RD_STATE_CH0_S)
+#define DMA2D_IN_RO_RD_STATE_CH0_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH0_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH0 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH0    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_M  (DMA2D_IN_PIXEL_BYTE_CH0_V << DMA2D_IN_PIXEL_BYTE_CH0_S)
+#define DMA2D_IN_PIXEL_BYTE_CH0_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH0_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH0 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_M  (DMA2D_IN_BURST_BLOCK_NUM_CH0_V << DMA2D_IN_BURST_BLOCK_NUM_CH0_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH0_S  13
+
+/** DMA2D_IN_RO_PD_CONF_CH0_REG register
+ *  Configures the rx reorder memory of channel 0
+ */
+#define DMA2D_IN_RO_PD_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x548)
+/** DMA2D_IN_RO_RAM_FORCE_PD_CH0 : R/W; bitpos: [4]; default: 1;
+ *  unused! dma reorder ram power down
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0    (BIT(4))
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PD_CH0_V << DMA2D_IN_RO_RAM_FORCE_PD_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PD_CH0_S  4
+/** DMA2D_IN_RO_RAM_FORCE_PU_CH0 : R/W; bitpos: [5]; default: 0;
+ *  unused! dma reorder ram power up
+ */
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0    (BIT(5))
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_M  (DMA2D_IN_RO_RAM_FORCE_PU_CH0_V << DMA2D_IN_RO_RAM_FORCE_PU_CH0_S)
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_FORCE_PU_CH0_S  5
+/** DMA2D_IN_RO_RAM_CLK_FO_CH0 : R/W; bitpos: [6]; default: 0;
+ *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+ *  0: A gate-clock will be used when accessing the RAM in DMA.
+ */
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0    (BIT(6))
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_M  (DMA2D_IN_RO_RAM_CLK_FO_CH0_V << DMA2D_IN_RO_RAM_CLK_FO_CH0_S)
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_V  0x00000001U
+#define DMA2D_IN_RO_RAM_CLK_FO_CH0_S  6
+
+/** DMA2D_IN_COLOR_CONVERT_CH0_REG register
+ *  Configures the Rx color convert of channel 0
+ */
+#define DMA2D_IN_COLOR_CONVERT_CH0_REG (DR_REG_DMA2D_BASE + 0x54c)
+/** DMA2D_IN_COLOR_OUTPUT_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+ *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+ */
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0    0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_M  (DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V << DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_V  0x00000003U
+#define DMA2D_IN_COLOR_OUTPUT_SEL_CH0_S  0
+/** DMA2D_IN_COLOR_3B_PROC_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ *  Enable generic color convert module between color input & color output, need to
+ *  configure parameter.
+ */
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0    (BIT(2))
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_M  (DMA2D_IN_COLOR_3B_PROC_EN_CH0_V << DMA2D_IN_COLOR_3B_PROC_EN_CH0_S)
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_V  0x00000001U
+#define DMA2D_IN_COLOR_3B_PROC_EN_CH0_S  2
+/** DMA2D_IN_COLOR_INPUT_SEL_CH0 : R/W; bitpos: [5:3]; default: 7;
+ *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+ *  1: YUV422      2: YUV444/420      7: disable color space convert
+ */
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0    0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_M  (DMA2D_IN_COLOR_INPUT_SEL_CH0_V << DMA2D_IN_COLOR_INPUT_SEL_CH0_S)
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_V  0x00000007U
+#define DMA2D_IN_COLOR_INPUT_SEL_CH0_S  3
+
+/** DMA2D_IN_SCRAMBLE_CH0_REG register
+ *  Configures the rx scramble of channel 0
+ */
+#define DMA2D_IN_SCRAMBLE_CH0_REG (DR_REG_DMA2D_BASE + 0x550)
+/** DMA2D_IN_SCRAMBLE_SEL_PRE_CH0 : R/W; bitpos: [2:0]; default: 0;
+ *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+ *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V << DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_PRE_CH0_S  0
+/** DMA2D_IN_SCRAMBLE_SEL_POST_CH0 : R/W; bitpos: [5:3]; default: 0;
+ *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+ *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+ */
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0    0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_M  (DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V << DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S)
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_V  0x00000007U
+#define DMA2D_IN_SCRAMBLE_SEL_POST_CH0_S  3
+
+/** DMA2D_IN_COLOR_PARAM0_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM0_CH0_REG (DR_REG_DMA2D_BASE + 0x554)
+/** DMA2D_IN_COLOR_PARAM_H0_CH0 : R/W; bitpos: [20:0]; default: 298;
+ *  Set first 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_M  (DMA2D_IN_COLOR_PARAM_H0_CH0_V << DMA2D_IN_COLOR_PARAM_H0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_H0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM1_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM1_CH0_REG (DR_REG_DMA2D_BASE + 0x558)
+/** DMA2D_IN_COLOR_PARAM_H1_CH0 : R/W; bitpos: [27:0]; default: 210164121;
+ *  Set last 2 parameter of most significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_H1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_M  (DMA2D_IN_COLOR_PARAM_H1_CH0_V << DMA2D_IN_COLOR_PARAM_H1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_H1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM2_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM2_CH0_REG (DR_REG_DMA2D_BASE + 0x55c)
+/** DMA2D_IN_COLOR_PARAM_M0_CH0 : R/W; bitpos: [20:0]; default: 1995050;
+ *  Set first 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_M  (DMA2D_IN_COLOR_PARAM_M0_CH0_V << DMA2D_IN_COLOR_PARAM_M0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_M0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM3_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM3_CH0_REG (DR_REG_DMA2D_BASE + 0x560)
+/** DMA2D_IN_COLOR_PARAM_M1_CH0 : R/W; bitpos: [27:0]; default: 35540784;
+ *  Set last 2 parameter of midium significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_M1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_M  (DMA2D_IN_COLOR_PARAM_M1_CH0_V << DMA2D_IN_COLOR_PARAM_M1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_M1_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM4_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM4_CH0_REG (DR_REG_DMA2D_BASE + 0x564)
+/** DMA2D_IN_COLOR_PARAM_L0_CH0 : R/W; bitpos: [20:0]; default: 528682;
+ *  Set first 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L0_CH0    0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_M  (DMA2D_IN_COLOR_PARAM_L0_CH0_V << DMA2D_IN_COLOR_PARAM_L0_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_V  0x001FFFFFU
+#define DMA2D_IN_COLOR_PARAM_L0_CH0_S  0
+
+/** DMA2D_IN_COLOR_PARAM5_CH0_REG register
+ *  Configures the rx color convert parameter of channel 0
+ */
+#define DMA2D_IN_COLOR_PARAM5_CH0_REG (DR_REG_DMA2D_BASE + 0x568)
+/** DMA2D_IN_COLOR_PARAM_L1_CH0 : R/W; bitpos: [27:0]; default: 195899392;
+ *  Set last 2 parameter of least significant byte of pending 3 bytes
+ */
+#define DMA2D_IN_COLOR_PARAM_L1_CH0    0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_M  (DMA2D_IN_COLOR_PARAM_L1_CH0_V << DMA2D_IN_COLOR_PARAM_L1_CH0_S)
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_V  0x0FFFFFFFU
+#define DMA2D_IN_COLOR_PARAM_L1_CH0_S  0
+
+/** DMA2D_IN_ETM_CONF_CH0_REG register
+ *  Configures the rx etm of channel 0
+ */
+#define DMA2D_IN_ETM_CONF_CH0_REG (DR_REG_DMA2D_BASE + 0x56c)
+/** DMA2D_IN_ETM_EN_CH0 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH0    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH0_M  (DMA2D_IN_ETM_EN_CH0_V << DMA2D_IN_ETM_EN_CH0_S)
+#define DMA2D_IN_ETM_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH0_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH0 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH0    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH0_M  (DMA2D_IN_ETM_LOOP_EN_CH0_V << DMA2D_IN_ETM_LOOP_EN_CH0_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH0_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH0_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH0 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH0    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_M  (DMA2D_IN_DSCR_TASK_MAK_CH0_V << DMA2D_IN_DSCR_TASK_MAK_CH0_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH0_S  2
+
+/** DMA2D_IN_CONF0_CH1_REG register
+ *  Configures the rx direction of channel 1
+ */
+#define DMA2D_IN_CONF0_CH1_REG (DR_REG_DMA2D_BASE + 0x600)
+/** DMA2D_IN_MEM_TRANS_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH1    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH1_M  (DMA2D_IN_MEM_TRANS_EN_CH1_V << DMA2D_IN_MEM_TRANS_EN_CH1_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH1_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH1_S  0
+/** DMA2D_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH1    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH1_M  (DMA2D_INDSCR_BURST_EN_CH1_V << DMA2D_INDSCR_BURST_EN_CH1_S)
+#define DMA2D_INDSCR_BURST_EN_CH1_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH1_S  2
+/** DMA2D_IN_ECC_AES_EN_CH1 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH1    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH1_M  (DMA2D_IN_ECC_AES_EN_CH1_V << DMA2D_IN_ECC_AES_EN_CH1_S)
+#define DMA2D_IN_ECC_AES_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH1_S  3
+/** DMA2D_IN_CHECK_OWNER_CH1 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH1    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH1_M  (DMA2D_IN_CHECK_OWNER_CH1_V << DMA2D_IN_CHECK_OWNER_CH1_S)
+#define DMA2D_IN_CHECK_OWNER_CH1_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH1_S  4
+/** DMA2D_IN_LOOP_TEST_CH1 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH1    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH1_M  (DMA2D_IN_LOOP_TEST_CH1_V << DMA2D_IN_LOOP_TEST_CH1_S)
+#define DMA2D_IN_LOOP_TEST_CH1_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH1_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH1 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_M  (DMA2D_IN_MEM_BURST_LENGTH_CH1_V << DMA2D_IN_MEM_BURST_LENGTH_CH1_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH1_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH1 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH1_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH1 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH1    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH1_M  (DMA2D_IN_DSCR_PORT_EN_CH1_V << DMA2D_IN_DSCR_PORT_EN_CH1_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH1_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH1_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH1 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH1    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_M  (DMA2D_IN_PAGE_BOUND_EN_CH1_V << DMA2D_IN_PAGE_BOUND_EN_CH1_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH1_S  12
+/** DMA2D_IN_REORDER_EN_CH1 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH1    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH1_M  (DMA2D_IN_REORDER_EN_CH1_V << DMA2D_IN_REORDER_EN_CH1_S)
+#define DMA2D_IN_REORDER_EN_CH1_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH1_S  16
+/** DMA2D_IN_RST_CH1 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH1    (BIT(24))
+#define DMA2D_IN_RST_CH1_M  (DMA2D_IN_RST_CH1_V << DMA2D_IN_RST_CH1_S)
+#define DMA2D_IN_RST_CH1_V  0x00000001U
+#define DMA2D_IN_RST_CH1_S  24
+/** DMA2D_IN_CMD_DISABLE_CH1 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH1    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH1_M  (DMA2D_IN_CMD_DISABLE_CH1_V << DMA2D_IN_CMD_DISABLE_CH1_S)
+#define DMA2D_IN_CMD_DISABLE_CH1_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH1_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH1_S  26
+
+/** DMA2D_IN_INT_RAW_CH1_REG register
+ *  Raw interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_RAW_CH1_REG (DR_REG_DMA2D_BASE + 0x604)
+/** DMA2D_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH1_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_RAW_M  (DMA2D_IN_DONE_CH1_INT_RAW_V << DMA2D_IN_DONE_CH1_INT_RAW_S)
+#define DMA2D_IN_DONE_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH1_INT_RAW_V << DMA2D_IN_SUC_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH1_INT_RAW_V << DMA2D_IN_ERR_EOF_CH1_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH1_REG register
+ *  Interrupt enable bits of RX channel 1
+ */
+#define DMA2D_IN_INT_ENA_CH1_REG (DR_REG_DMA2D_BASE + 0x608)
+/** DMA2D_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ENA_M  (DMA2D_IN_DONE_CH1_INT_ENA_V << DMA2D_IN_DONE_CH1_INT_ENA_S)
+#define DMA2D_IN_DONE_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH1_INT_ENA_V << DMA2D_IN_SUC_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH1_INT_ENA_V << DMA2D_IN_ERR_EOF_CH1_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH1_REG register
+ *  Masked interrupt status of RX channel 1
+ */
+#define DMA2D_IN_INT_ST_CH1_REG (DR_REG_DMA2D_BASE + 0x60c)
+/** DMA2D_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_ST_M  (DMA2D_IN_DONE_CH1_INT_ST_V << DMA2D_IN_DONE_CH1_INT_ST_S)
+#define DMA2D_IN_DONE_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_M  (DMA2D_IN_SUC_EOF_CH1_INT_ST_V << DMA2D_IN_SUC_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_M  (DMA2D_IN_ERR_EOF_CH1_INT_ST_V << DMA2D_IN_ERR_EOF_CH1_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH1_INT_ST_V << DMA2D_IN_DSCR_ERR_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH1_REG register
+ *  Interrupt clear bits of RX channel 1
+ */
+#define DMA2D_IN_INT_CLR_CH1_REG (DR_REG_DMA2D_BASE + 0x610)
+/** DMA2D_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH1_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH1_INT_CLR_M  (DMA2D_IN_DONE_CH1_INT_CLR_V << DMA2D_IN_DONE_CH1_INT_CLR_S)
+#define DMA2D_IN_DONE_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH1_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH1_INT_CLR_V << DMA2D_IN_SUC_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH1_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH1_INT_CLR_V << DMA2D_IN_ERR_EOF_CH1_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH1_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH1_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH1_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH1_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH1_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH1_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH1_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH1_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH1_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH1_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH1_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH1_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH1_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH1_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH1_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH1_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH1_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH1_REG register
+ *  Represents the status of the rx fifo of channel 1
+ */
+#define DMA2D_INFIFO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x614)
+/** DMA2D_INFIFO_FULL_L2_CH1 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH1    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH1_M  (DMA2D_INFIFO_FULL_L2_CH1_V << DMA2D_INFIFO_FULL_L2_CH1_S)
+#define DMA2D_INFIFO_FULL_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH1_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH1 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH1    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH1_M  (DMA2D_INFIFO_EMPTY_L2_CH1_V << DMA2D_INFIFO_EMPTY_L2_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH1_S  1
+/** DMA2D_INFIFO_CNT_L2_CH1 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH1    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_M  (DMA2D_INFIFO_CNT_L2_CH1_V << DMA2D_INFIFO_CNT_L2_CH1_S)
+#define DMA2D_INFIFO_CNT_L2_CH1_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH1_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_M  (DMA2D_IN_REMAIN_UNDER_1B_CH1_V << DMA2D_IN_REMAIN_UNDER_1B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH1_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_M  (DMA2D_IN_REMAIN_UNDER_2B_CH1_V << DMA2D_IN_REMAIN_UNDER_2B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH1_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_M  (DMA2D_IN_REMAIN_UNDER_3B_CH1_V << DMA2D_IN_REMAIN_UNDER_3B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH1_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_M  (DMA2D_IN_REMAIN_UNDER_4B_CH1_V << DMA2D_IN_REMAIN_UNDER_4B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH1_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH1 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_M  (DMA2D_IN_REMAIN_UNDER_5B_CH1_V << DMA2D_IN_REMAIN_UNDER_5B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH1_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH1 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_M  (DMA2D_IN_REMAIN_UNDER_6B_CH1_V << DMA2D_IN_REMAIN_UNDER_6B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH1_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH1 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_M  (DMA2D_IN_REMAIN_UNDER_7B_CH1_V << DMA2D_IN_REMAIN_UNDER_7B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH1_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH1 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_M  (DMA2D_IN_REMAIN_UNDER_8B_CH1_V << DMA2D_IN_REMAIN_UNDER_8B_CH1_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH1_S  14
+/** DMA2D_INFIFO_FULL_L1_CH1 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH1    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH1_M  (DMA2D_INFIFO_FULL_L1_CH1_V << DMA2D_INFIFO_FULL_L1_CH1_S)
+#define DMA2D_INFIFO_FULL_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH1_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH1 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH1    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH1_M  (DMA2D_INFIFO_EMPTY_L1_CH1_V << DMA2D_INFIFO_EMPTY_L1_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH1_S  16
+/** DMA2D_INFIFO_CNT_L1_CH1 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_M  (DMA2D_INFIFO_CNT_L1_CH1_V << DMA2D_INFIFO_CNT_L1_CH1_S)
+#define DMA2D_INFIFO_CNT_L1_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH1_S  17
+/** DMA2D_INFIFO_FULL_L3_CH1 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH1    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH1_M  (DMA2D_INFIFO_FULL_L3_CH1_V << DMA2D_INFIFO_FULL_L3_CH1_S)
+#define DMA2D_INFIFO_FULL_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH1_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH1 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH1    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH1_M  (DMA2D_INFIFO_EMPTY_L3_CH1_V << DMA2D_INFIFO_EMPTY_L3_CH1_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH1_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH1_S  23
+/** DMA2D_INFIFO_CNT_L3_CH1 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH1    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_M  (DMA2D_INFIFO_CNT_L3_CH1_V << DMA2D_INFIFO_CNT_L3_CH1_S)
+#define DMA2D_INFIFO_CNT_L3_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH1_S  24
+
+/** DMA2D_IN_POP_CH1_REG register
+ *  Configures the rx fifo of channel 1
+ */
+#define DMA2D_IN_POP_CH1_REG (DR_REG_DMA2D_BASE + 0x618)
+/** DMA2D_INFIFO_RDATA_CH1 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH1    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_M  (DMA2D_INFIFO_RDATA_CH1_V << DMA2D_INFIFO_RDATA_CH1_S)
+#define DMA2D_INFIFO_RDATA_CH1_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH1_S  0
+/** DMA2D_INFIFO_POP_CH1 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH1    (BIT(11))
+#define DMA2D_INFIFO_POP_CH1_M  (DMA2D_INFIFO_POP_CH1_V << DMA2D_INFIFO_POP_CH1_S)
+#define DMA2D_INFIFO_POP_CH1_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH1_S  11
+
+/** DMA2D_IN_LINK_CONF_CH1_REG register
+ *  Configures the rx descriptor operations of channel 1
+ */
+#define DMA2D_IN_LINK_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x61c)
+/** DMA2D_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH1    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH1_M  (DMA2D_INLINK_AUTO_RET_CH1_V << DMA2D_INLINK_AUTO_RET_CH1_S)
+#define DMA2D_INLINK_AUTO_RET_CH1_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH1_S  20
+/** DMA2D_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH1    (BIT(21))
+#define DMA2D_INLINK_STOP_CH1_M  (DMA2D_INLINK_STOP_CH1_V << DMA2D_INLINK_STOP_CH1_S)
+#define DMA2D_INLINK_STOP_CH1_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH1_S  21
+/** DMA2D_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH1    (BIT(22))
+#define DMA2D_INLINK_START_CH1_M  (DMA2D_INLINK_START_CH1_V << DMA2D_INLINK_START_CH1_S)
+#define DMA2D_INLINK_START_CH1_V  0x00000001U
+#define DMA2D_INLINK_START_CH1_S  22
+/** DMA2D_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH1    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH1_M  (DMA2D_INLINK_RESTART_CH1_V << DMA2D_INLINK_RESTART_CH1_S)
+#define DMA2D_INLINK_RESTART_CH1_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH1_S  23
+/** DMA2D_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH1    (BIT(24))
+#define DMA2D_INLINK_PARK_CH1_M  (DMA2D_INLINK_PARK_CH1_V << DMA2D_INLINK_PARK_CH1_S)
+#define DMA2D_INLINK_PARK_CH1_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH1_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH1_REG register
+ *  Configures the rx descriptor address of channel 1
+ */
+#define DMA2D_IN_LINK_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x620)
+/** DMA2D_INLINK_ADDR_CH1 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_M  (DMA2D_INLINK_ADDR_CH1_V << DMA2D_INLINK_ADDR_CH1_S)
+#define DMA2D_INLINK_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH1_S  0
+
+/** DMA2D_IN_STATE_CH1_REG register
+ *  Represents the working status of the rx descriptor of channel 1
+ */
+#define DMA2D_IN_STATE_CH1_REG (DR_REG_DMA2D_BASE + 0x624)
+/** DMA2D_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH1    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_M  (DMA2D_INLINK_DSCR_ADDR_CH1_V << DMA2D_INLINK_DSCR_ADDR_CH1_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH1_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH1_S  0
+/** DMA2D_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH1    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_M  (DMA2D_IN_DSCR_STATE_CH1_V << DMA2D_IN_DSCR_STATE_CH1_S)
+#define DMA2D_IN_DSCR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH1_S  18
+/** DMA2D_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH1    0x00000007U
+#define DMA2D_IN_STATE_CH1_M  (DMA2D_IN_STATE_CH1_V << DMA2D_IN_STATE_CH1_S)
+#define DMA2D_IN_STATE_CH1_V  0x00000007U
+#define DMA2D_IN_STATE_CH1_S  20
+/** DMA2D_IN_RESET_AVAIL_CH1 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH1    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH1_M  (DMA2D_IN_RESET_AVAIL_CH1_V << DMA2D_IN_RESET_AVAIL_CH1_S)
+#define DMA2D_IN_RESET_AVAIL_CH1_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH1_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x628)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA2D_BASE + 0x62c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH1_S  0
+
+/** DMA2D_IN_DSCR_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_CH1_REG (DR_REG_DMA2D_BASE + 0x630)
+/** DMA2D_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_M  (DMA2D_INLINK_DSCR_CH1_V << DMA2D_INLINK_DSCR_CH1_S)
+#define DMA2D_INLINK_DSCR_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF0_CH1_REG (DR_REG_DMA2D_BASE + 0x634)
+/** DMA2D_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_M  (DMA2D_INLINK_DSCR_BF0_CH1_V << DMA2D_INLINK_DSCR_BF0_CH1_S)
+#define DMA2D_INLINK_DSCR_BF0_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH1_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH1_REG register
+ *  Represents the address associated with the inlink descriptor of channel 1
+ */
+#define DMA2D_IN_DSCR_BF1_CH1_REG (DR_REG_DMA2D_BASE + 0x638)
+/** DMA2D_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH1    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_M  (DMA2D_INLINK_DSCR_BF1_CH1_V << DMA2D_INLINK_DSCR_BF1_CH1_S)
+#define DMA2D_INLINK_DSCR_BF1_CH1_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH1_S  0
+
+/** DMA2D_IN_PERI_SEL_CH1_REG register
+ *  Configures the rx peripheral of channel 1
+ */
+#define DMA2D_IN_PERI_SEL_CH1_REG (DR_REG_DMA2D_BASE + 0x63c)
+/** DMA2D_IN_PERI_SEL_CH1 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH1    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_M  (DMA2D_IN_PERI_SEL_CH1_V << DMA2D_IN_PERI_SEL_CH1_S)
+#define DMA2D_IN_PERI_SEL_CH1_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH1_S  0
+
+/** DMA2D_IN_ARB_CH1_REG register
+ *  Configures the rx arbiter of channel 1
+ */
+#define DMA2D_IN_ARB_CH1_REG (DR_REG_DMA2D_BASE + 0x640)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH1 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_M  (DMA2D_IN_ARB_TOKEN_NUM_CH1_V << DMA2D_IN_ARB_TOKEN_NUM_CH1_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH1_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH1 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH1    0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH1_M  (DMA2D_IN_ARB_PRIORITY_CH1_V << DMA2D_IN_ARB_PRIORITY_CH1_S)
+#define DMA2D_IN_ARB_PRIORITY_CH1_V  0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH1_S  4
+
+/** DMA2D_IN_RO_STATUS_CH1_REG register
+ *  Represents the status of the rx reorder module of channel 1
+ */
+#define DMA2D_IN_RO_STATUS_CH1_REG (DR_REG_DMA2D_BASE + 0x644)
+/** DMA2D_INFIFO_RO_CNT_CH1 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH1    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_M  (DMA2D_INFIFO_RO_CNT_CH1_V << DMA2D_INFIFO_RO_CNT_CH1_S)
+#define DMA2D_INFIFO_RO_CNT_CH1_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH1_S  0
+/** DMA2D_IN_RO_WR_STATE_CH1 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_M  (DMA2D_IN_RO_WR_STATE_CH1_V << DMA2D_IN_RO_WR_STATE_CH1_S)
+#define DMA2D_IN_RO_WR_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH1_S  5
+/** DMA2D_IN_RO_RD_STATE_CH1 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH1    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_M  (DMA2D_IN_RO_RD_STATE_CH1_V << DMA2D_IN_RO_RD_STATE_CH1_S)
+#define DMA2D_IN_RO_RD_STATE_CH1_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH1_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH1 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH1    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_M  (DMA2D_IN_PIXEL_BYTE_CH1_V << DMA2D_IN_PIXEL_BYTE_CH1_S)
+#define DMA2D_IN_PIXEL_BYTE_CH1_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH1_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH1 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_M  (DMA2D_IN_BURST_BLOCK_NUM_CH1_V << DMA2D_IN_BURST_BLOCK_NUM_CH1_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH1_S  13
+
+/** DMA2D_IN_ETM_CONF_CH1_REG register
+ *  Configures the rx etm of channel 1
+ */
+#define DMA2D_IN_ETM_CONF_CH1_REG (DR_REG_DMA2D_BASE + 0x66c)
+/** DMA2D_IN_ETM_EN_CH1 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH1    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH1_M  (DMA2D_IN_ETM_EN_CH1_V << DMA2D_IN_ETM_EN_CH1_S)
+#define DMA2D_IN_ETM_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH1_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH1 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH1    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH1_M  (DMA2D_IN_ETM_LOOP_EN_CH1_V << DMA2D_IN_ETM_LOOP_EN_CH1_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH1_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH1_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH1 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH1    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_M  (DMA2D_IN_DSCR_TASK_MAK_CH1_V << DMA2D_IN_DSCR_TASK_MAK_CH1_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH1_S  2
+
+/** DMA2D_IN_CONF0_CH2_REG register
+ *  Configures the rx direction of channel 2
+ */
+#define DMA2D_IN_CONF0_CH2_REG (DR_REG_DMA2D_BASE + 0x700)
+/** DMA2D_IN_MEM_TRANS_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  enable memory trans of the same channel
+ */
+#define DMA2D_IN_MEM_TRANS_EN_CH2    (BIT(0))
+#define DMA2D_IN_MEM_TRANS_EN_CH2_M  (DMA2D_IN_MEM_TRANS_EN_CH2_V << DMA2D_IN_MEM_TRANS_EN_CH2_S)
+#define DMA2D_IN_MEM_TRANS_EN_CH2_V  0x00000001U
+#define DMA2D_IN_MEM_TRANS_EN_CH2_S  0
+/** DMA2D_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+ *  when accessing SRAM.
+ */
+#define DMA2D_INDSCR_BURST_EN_CH2    (BIT(2))
+#define DMA2D_INDSCR_BURST_EN_CH2_M  (DMA2D_INDSCR_BURST_EN_CH2_V << DMA2D_INDSCR_BURST_EN_CH2_S)
+#define DMA2D_INDSCR_BURST_EN_CH2_V  0x00000001U
+#define DMA2D_INDSCR_BURST_EN_CH2_S  2
+/** DMA2D_IN_ECC_AES_EN_CH2 : R/W; bitpos: [3]; default: 0;
+ *  When access address space is ecc/aes area, this bit should be set to 1. In this
+ *  case, the start address of square should be 16-bit aligned. The width of square
+ *  multiply byte number of one pixel should be 16-bit aligned.
+ */
+#define DMA2D_IN_ECC_AES_EN_CH2    (BIT(3))
+#define DMA2D_IN_ECC_AES_EN_CH2_M  (DMA2D_IN_ECC_AES_EN_CH2_V << DMA2D_IN_ECC_AES_EN_CH2_S)
+#define DMA2D_IN_ECC_AES_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ECC_AES_EN_CH2_S  3
+/** DMA2D_IN_CHECK_OWNER_CH2 : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable checking the owner attribute of the link descriptor.
+ */
+#define DMA2D_IN_CHECK_OWNER_CH2    (BIT(4))
+#define DMA2D_IN_CHECK_OWNER_CH2_M  (DMA2D_IN_CHECK_OWNER_CH2_V << DMA2D_IN_CHECK_OWNER_CH2_S)
+#define DMA2D_IN_CHECK_OWNER_CH2_V  0x00000001U
+#define DMA2D_IN_CHECK_OWNER_CH2_S  4
+/** DMA2D_IN_LOOP_TEST_CH2 : R/W; bitpos: [5]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_LOOP_TEST_CH2    (BIT(5))
+#define DMA2D_IN_LOOP_TEST_CH2_M  (DMA2D_IN_LOOP_TEST_CH2_V << DMA2D_IN_LOOP_TEST_CH2_S)
+#define DMA2D_IN_LOOP_TEST_CH2_V  0x00000001U
+#define DMA2D_IN_LOOP_TEST_CH2_S  5
+/** DMA2D_IN_MEM_BURST_LENGTH_CH2 : R/W; bitpos: [8:6]; default: 0;
+ *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+ *  bytes    4: 128 bytes
+ */
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2    0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_M  (DMA2D_IN_MEM_BURST_LENGTH_CH2_V << DMA2D_IN_MEM_BURST_LENGTH_CH2_S)
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_V  0x00000007U
+#define DMA2D_IN_MEM_BURST_LENGTH_CH2_S  6
+/** DMA2D_IN_MACRO_BLOCK_SIZE_CH2 : R/W; bitpos: [10:9]; default: 0;
+ *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+ *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+ *  descriptor
+ */
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2    0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_M  (DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V << DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S)
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_V  0x00000003U
+#define DMA2D_IN_MACRO_BLOCK_SIZE_CH2_S  9
+/** DMA2D_IN_DSCR_PORT_EN_CH2 : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to 1 to obtain descriptor from IP port
+ */
+#define DMA2D_IN_DSCR_PORT_EN_CH2    (BIT(11))
+#define DMA2D_IN_DSCR_PORT_EN_CH2_M  (DMA2D_IN_DSCR_PORT_EN_CH2_V << DMA2D_IN_DSCR_PORT_EN_CH2_S)
+#define DMA2D_IN_DSCR_PORT_EN_CH2_V  0x00000001U
+#define DMA2D_IN_DSCR_PORT_EN_CH2_S  11
+/** DMA2D_IN_PAGE_BOUND_EN_CH2 : R/W; bitpos: [12]; default: 0;
+ *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+ *  which define by mem_burst_length
+ */
+#define DMA2D_IN_PAGE_BOUND_EN_CH2    (BIT(12))
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_M  (DMA2D_IN_PAGE_BOUND_EN_CH2_V << DMA2D_IN_PAGE_BOUND_EN_CH2_S)
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_V  0x00000001U
+#define DMA2D_IN_PAGE_BOUND_EN_CH2_S  12
+/** DMA2D_IN_REORDER_EN_CH2 : R/W; bitpos: [16]; default: 0;
+ *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+ *  selection
+ */
+#define DMA2D_IN_REORDER_EN_CH2    (BIT(16))
+#define DMA2D_IN_REORDER_EN_CH2_M  (DMA2D_IN_REORDER_EN_CH2_V << DMA2D_IN_REORDER_EN_CH2_S)
+#define DMA2D_IN_REORDER_EN_CH2_V  0x00000001U
+#define DMA2D_IN_REORDER_EN_CH2_S  16
+/** DMA2D_IN_RST_CH2 : R/W; bitpos: [24]; default: 0;
+ *  Write 1 then write 0 to this bit to reset Rx channel
+ */
+#define DMA2D_IN_RST_CH2    (BIT(24))
+#define DMA2D_IN_RST_CH2_M  (DMA2D_IN_RST_CH2_V << DMA2D_IN_RST_CH2_S)
+#define DMA2D_IN_RST_CH2_V  0x00000001U
+#define DMA2D_IN_RST_CH2_S  24
+/** DMA2D_IN_CMD_DISABLE_CH2 : R/W; bitpos: [25]; default: 0;
+ *  Write 1 before reset and write 0 after reset
+ */
+#define DMA2D_IN_CMD_DISABLE_CH2    (BIT(25))
+#define DMA2D_IN_CMD_DISABLE_CH2_M  (DMA2D_IN_CMD_DISABLE_CH2_V << DMA2D_IN_CMD_DISABLE_CH2_S)
+#define DMA2D_IN_CMD_DISABLE_CH2_V  0x00000001U
+#define DMA2D_IN_CMD_DISABLE_CH2_S  25
+/** DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2 : R/W; bitpos: [26]; default: 0;
+ *  Set this bit to 1 to disable arbiter optimum weight function.
+ */
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2    (BIT(26))
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_M  (DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V << DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S)
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_V  0x00000001U
+#define DMA2D_IN_ARB_WEIGHT_OPT_DIS_CH2_S  26
+
+/** DMA2D_IN_INT_RAW_CH2_REG register
+ *  Raw interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_RAW_CH2_REG (DR_REG_DMA2D_BASE + 0x704)
+/** DMA2D_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been transmitted to peripherals for Rx channel 0.
+ */
+#define DMA2D_IN_DONE_CH2_INT_RAW    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_RAW_M  (DMA2D_IN_DONE_CH2_INT_RAW_V << DMA2D_IN_DONE_CH2_INT_RAW_S)
+#define DMA2D_IN_DONE_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_RAW_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and no data error is detected for Rx channel 0.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_M  (DMA2D_IN_SUC_EOF_CH2_INT_RAW_V << DMA2D_IN_SUC_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_RAW_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+ *  descriptor has been received and data error is detected
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_M  (DMA2D_IN_ERR_EOF_CH2_INT_RAW_V << DMA2D_IN_ERR_EOF_CH2_INT_RAW_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_RAW_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+ *  including owner error, the second and third word error of inlink descriptor for Rx
+ *  channel 0.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_M  (DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V << DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_RAW_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_RAW_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_RAW_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_RAW_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_RAW_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_RAW_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V << DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_RAW_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+ *  also remain data.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_RAW_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_RAW_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0;
+ *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V << DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_RAW_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0;
+ *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_RAW_S  13
+
+/** DMA2D_IN_INT_ENA_CH2_REG register
+ *  Interrupt enable bits of RX channel 2
+ */
+#define DMA2D_IN_INT_ENA_CH2_REG (DR_REG_DMA2D_BASE + 0x708)
+/** DMA2D_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ENA    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ENA_M  (DMA2D_IN_DONE_CH2_INT_ENA_V << DMA2D_IN_DONE_CH2_INT_ENA_S)
+#define DMA2D_IN_DONE_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ENA_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_M  (DMA2D_IN_SUC_EOF_CH2_INT_ENA_V << DMA2D_IN_SUC_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ENA_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_M  (DMA2D_IN_ERR_EOF_CH2_INT_ENA_V << DMA2D_IN_ERR_EOF_CH2_INT_ENA_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ENA_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V << DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ENA_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ENA_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ENA_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ENA_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ENA_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ENA_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ENA_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ENA_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ENA_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ENA_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ENA_S  13
+
+/** DMA2D_IN_INT_ST_CH2_REG register
+ *  Masked interrupt status of RX channel 2
+ */
+#define DMA2D_IN_INT_ST_CH2_REG (DR_REG_DMA2D_BASE + 0x70c)
+/** DMA2D_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_ST    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_ST_M  (DMA2D_IN_DONE_CH2_INT_ST_V << DMA2D_IN_DONE_CH2_INT_ST_S)
+#define DMA2D_IN_DONE_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_ST_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_M  (DMA2D_IN_SUC_EOF_CH2_INT_ST_V << DMA2D_IN_SUC_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_ST_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_M  (DMA2D_IN_ERR_EOF_CH2_INT_ST_V << DMA2D_IN_ERR_EOF_CH2_INT_ST_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_ST_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_M  (DMA2D_IN_DSCR_ERR_CH2_INT_ST_V << DMA2D_IN_DSCR_ERR_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_ST_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_ST_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_ST_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_ST_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_ST_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V << DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_ST_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V << DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_ST_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_ST_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V << DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_ST_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V << DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_ST_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_ST_S  13
+
+/** DMA2D_IN_INT_CLR_CH2_REG register
+ *  Interrupt clear bits of RX channel 2
+ */
+#define DMA2D_IN_INT_CLR_CH2_REG (DR_REG_DMA2D_BASE + 0x710)
+/** DMA2D_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+ */
+#define DMA2D_IN_DONE_CH2_INT_CLR    (BIT(0))
+#define DMA2D_IN_DONE_CH2_INT_CLR_M  (DMA2D_IN_DONE_CH2_INT_CLR_V << DMA2D_IN_DONE_CH2_INT_CLR_S)
+#define DMA2D_IN_DONE_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DONE_CH2_INT_CLR_S  0
+/** DMA2D_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR    (BIT(1))
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_M  (DMA2D_IN_SUC_EOF_CH2_INT_CLR_V << DMA2D_IN_SUC_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_SUC_EOF_CH2_INT_CLR_S  1
+/** DMA2D_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+ */
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR    (BIT(2))
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_M  (DMA2D_IN_ERR_EOF_CH2_INT_CLR_V << DMA2D_IN_ERR_EOF_CH2_INT_CLR_S)
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_ERR_EOF_CH2_INT_CLR_S  2
+/** DMA2D_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR    (BIT(3))
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_M  (DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V << DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_ERR_CH2_INT_CLR_S  3
+/** DMA2D_INFIFO_OVF_L1_CH2_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR    (BIT(4))
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L1_CH2_INT_CLR_S  4
+/** DMA2D_INFIFO_UDF_L1_CH2_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR    (BIT(5))
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L1_CH2_INT_CLR_S  5
+/** DMA2D_INFIFO_OVF_L2_CH2_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR    (BIT(6))
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L2_CH2_INT_CLR_S  6
+/** DMA2D_INFIFO_UDF_L2_CH2_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR    (BIT(7))
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L2_CH2_INT_CLR_S  7
+/** DMA2D_INFIFO_OVF_L3_CH2_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR    (BIT(8))
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_OVF_L3_CH2_INT_CLR_S  8
+/** DMA2D_INFIFO_UDF_L3_CH2_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR    (BIT(9))
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_M  (DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V << DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_UDF_L3_CH2_INT_CLR_S  9
+/** DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR    (BIT(10))
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_M  (DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_EMPTY_CH2_INT_CLR_S  10
+/** DMA2D_INFIFO_RO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR    (BIT(11))
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_OVF_CH2_INT_CLR_S  11
+/** DMA2D_INFIFO_RO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+ */
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR    (BIT(12))
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_M  (DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V << DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S)
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_INFIFO_RO_UDF_CH2_INT_CLR_S  12
+/** DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+ */
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR    (BIT(13))
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_M  (DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V << DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S)
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_V  0x00000001U
+#define DMA2D_IN_DSCR_TASK_OVF_CH2_INT_CLR_S  13
+
+/** DMA2D_INFIFO_STATUS_CH2_REG register
+ *  Represents the status of the rx fifo of channel 2
+ */
+#define DMA2D_INFIFO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x714)
+/** DMA2D_INFIFO_FULL_L2_CH2 : RO; bitpos: [0]; default: 0;
+ *  Rx FIFO full signal for Rx channel.
+ */
+#define DMA2D_INFIFO_FULL_L2_CH2    (BIT(0))
+#define DMA2D_INFIFO_FULL_L2_CH2_M  (DMA2D_INFIFO_FULL_L2_CH2_V << DMA2D_INFIFO_FULL_L2_CH2_S)
+#define DMA2D_INFIFO_FULL_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L2_CH2_S  0
+/** DMA2D_INFIFO_EMPTY_L2_CH2 : RO; bitpos: [1]; default: 1;
+ *  Rx FIFO empty signal for Rx channel.
+ */
+#define DMA2D_INFIFO_EMPTY_L2_CH2    (BIT(1))
+#define DMA2D_INFIFO_EMPTY_L2_CH2_M  (DMA2D_INFIFO_EMPTY_L2_CH2_V << DMA2D_INFIFO_EMPTY_L2_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L2_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L2_CH2_S  1
+/** DMA2D_INFIFO_CNT_L2_CH2 : RO; bitpos: [5:2]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+ */
+#define DMA2D_INFIFO_CNT_L2_CH2    0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_M  (DMA2D_INFIFO_CNT_L2_CH2_V << DMA2D_INFIFO_CNT_L2_CH2_S)
+#define DMA2D_INFIFO_CNT_L2_CH2_V  0x0000000FU
+#define DMA2D_INFIFO_CNT_L2_CH2_S  2
+/** DMA2D_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [7]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2    (BIT(7))
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_M  (DMA2D_IN_REMAIN_UNDER_1B_CH2_V << DMA2D_IN_REMAIN_UNDER_1B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_1B_CH2_S  7
+/** DMA2D_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [8]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2    (BIT(8))
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_M  (DMA2D_IN_REMAIN_UNDER_2B_CH2_V << DMA2D_IN_REMAIN_UNDER_2B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_2B_CH2_S  8
+/** DMA2D_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [9]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2    (BIT(9))
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_M  (DMA2D_IN_REMAIN_UNDER_3B_CH2_V << DMA2D_IN_REMAIN_UNDER_3B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_3B_CH2_S  9
+/** DMA2D_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [10]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2    (BIT(10))
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_M  (DMA2D_IN_REMAIN_UNDER_4B_CH2_V << DMA2D_IN_REMAIN_UNDER_4B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_4B_CH2_S  10
+/** DMA2D_IN_REMAIN_UNDER_5B_CH2 : RO; bitpos: [11]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2    (BIT(11))
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_M  (DMA2D_IN_REMAIN_UNDER_5B_CH2_V << DMA2D_IN_REMAIN_UNDER_5B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_5B_CH2_S  11
+/** DMA2D_IN_REMAIN_UNDER_6B_CH2 : RO; bitpos: [12]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2    (BIT(12))
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_M  (DMA2D_IN_REMAIN_UNDER_6B_CH2_V << DMA2D_IN_REMAIN_UNDER_6B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_6B_CH2_S  12
+/** DMA2D_IN_REMAIN_UNDER_7B_CH2 : RO; bitpos: [13]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2    (BIT(13))
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_M  (DMA2D_IN_REMAIN_UNDER_7B_CH2_V << DMA2D_IN_REMAIN_UNDER_7B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_7B_CH2_S  13
+/** DMA2D_IN_REMAIN_UNDER_8B_CH2 : RO; bitpos: [14]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2    (BIT(14))
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_M  (DMA2D_IN_REMAIN_UNDER_8B_CH2_V << DMA2D_IN_REMAIN_UNDER_8B_CH2_S)
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_V  0x00000001U
+#define DMA2D_IN_REMAIN_UNDER_8B_CH2_S  14
+/** DMA2D_INFIFO_FULL_L1_CH2 : RO; bitpos: [15]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L1_CH2    (BIT(15))
+#define DMA2D_INFIFO_FULL_L1_CH2_M  (DMA2D_INFIFO_FULL_L1_CH2_V << DMA2D_INFIFO_FULL_L1_CH2_S)
+#define DMA2D_INFIFO_FULL_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L1_CH2_S  15
+/** DMA2D_INFIFO_EMPTY_L1_CH2 : RO; bitpos: [16]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L1_CH2    (BIT(16))
+#define DMA2D_INFIFO_EMPTY_L1_CH2_M  (DMA2D_INFIFO_EMPTY_L1_CH2_V << DMA2D_INFIFO_EMPTY_L1_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L1_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L1_CH2_S  16
+/** DMA2D_INFIFO_CNT_L1_CH2 : RO; bitpos: [21:17]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L1_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_M  (DMA2D_INFIFO_CNT_L1_CH2_V << DMA2D_INFIFO_CNT_L1_CH2_S)
+#define DMA2D_INFIFO_CNT_L1_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L1_CH2_S  17
+/** DMA2D_INFIFO_FULL_L3_CH2 : RO; bitpos: [22]; default: 0;
+ *  Rx FIFO full signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_FULL_L3_CH2    (BIT(22))
+#define DMA2D_INFIFO_FULL_L3_CH2_M  (DMA2D_INFIFO_FULL_L3_CH2_V << DMA2D_INFIFO_FULL_L3_CH2_S)
+#define DMA2D_INFIFO_FULL_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_FULL_L3_CH2_S  22
+/** DMA2D_INFIFO_EMPTY_L3_CH2 : RO; bitpos: [23]; default: 1;
+ *  Rx FIFO empty signal for Rx channel 0.
+ */
+#define DMA2D_INFIFO_EMPTY_L3_CH2    (BIT(23))
+#define DMA2D_INFIFO_EMPTY_L3_CH2_M  (DMA2D_INFIFO_EMPTY_L3_CH2_V << DMA2D_INFIFO_EMPTY_L3_CH2_S)
+#define DMA2D_INFIFO_EMPTY_L3_CH2_V  0x00000001U
+#define DMA2D_INFIFO_EMPTY_L3_CH2_S  23
+/** DMA2D_INFIFO_CNT_L3_CH2 : RO; bitpos: [28:24]; default: 0;
+ *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+ */
+#define DMA2D_INFIFO_CNT_L3_CH2    0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_M  (DMA2D_INFIFO_CNT_L3_CH2_V << DMA2D_INFIFO_CNT_L3_CH2_S)
+#define DMA2D_INFIFO_CNT_L3_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_CNT_L3_CH2_S  24
+
+/** DMA2D_IN_POP_CH2_REG register
+ *  Configures the rx fifo of channel 2
+ */
+#define DMA2D_IN_POP_CH2_REG (DR_REG_DMA2D_BASE + 0x718)
+/** DMA2D_INFIFO_RDATA_CH2 : RO; bitpos: [10:0]; default: 1024;
+ *  This register stores the data popping from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_RDATA_CH2    0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_M  (DMA2D_INFIFO_RDATA_CH2_V << DMA2D_INFIFO_RDATA_CH2_S)
+#define DMA2D_INFIFO_RDATA_CH2_V  0x000007FFU
+#define DMA2D_INFIFO_RDATA_CH2_S  0
+/** DMA2D_INFIFO_POP_CH2 : R/W/SC; bitpos: [11]; default: 0;
+ *  Set this bit to pop data from DMA Rx FIFO.
+ */
+#define DMA2D_INFIFO_POP_CH2    (BIT(11))
+#define DMA2D_INFIFO_POP_CH2_M  (DMA2D_INFIFO_POP_CH2_V << DMA2D_INFIFO_POP_CH2_S)
+#define DMA2D_INFIFO_POP_CH2_V  0x00000001U
+#define DMA2D_INFIFO_POP_CH2_S  11
+
+/** DMA2D_IN_LINK_CONF_CH2_REG register
+ *  Configures the rx descriptor operations of channel 2
+ */
+#define DMA2D_IN_LINK_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x71c)
+/** DMA2D_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1;
+ *  Set this bit to return to current inlink descriptor's address, when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_INLINK_AUTO_RET_CH2    (BIT(20))
+#define DMA2D_INLINK_AUTO_RET_CH2_M  (DMA2D_INLINK_AUTO_RET_CH2_V << DMA2D_INLINK_AUTO_RET_CH2_S)
+#define DMA2D_INLINK_AUTO_RET_CH2_V  0x00000001U
+#define DMA2D_INLINK_AUTO_RET_CH2_S  20
+/** DMA2D_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0;
+ *  Set this bit to stop dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_STOP_CH2    (BIT(21))
+#define DMA2D_INLINK_STOP_CH2_M  (DMA2D_INLINK_STOP_CH2_V << DMA2D_INLINK_STOP_CH2_S)
+#define DMA2D_INLINK_STOP_CH2_V  0x00000001U
+#define DMA2D_INLINK_STOP_CH2_S  21
+/** DMA2D_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0;
+ *  Set this bit to start dealing with the inlink descriptors.
+ */
+#define DMA2D_INLINK_START_CH2    (BIT(22))
+#define DMA2D_INLINK_START_CH2_M  (DMA2D_INLINK_START_CH2_V << DMA2D_INLINK_START_CH2_S)
+#define DMA2D_INLINK_START_CH2_V  0x00000001U
+#define DMA2D_INLINK_START_CH2_S  22
+/** DMA2D_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0;
+ *  Set this bit to mount a new inlink descriptor.
+ */
+#define DMA2D_INLINK_RESTART_CH2    (BIT(23))
+#define DMA2D_INLINK_RESTART_CH2_M  (DMA2D_INLINK_RESTART_CH2_V << DMA2D_INLINK_RESTART_CH2_S)
+#define DMA2D_INLINK_RESTART_CH2_V  0x00000001U
+#define DMA2D_INLINK_RESTART_CH2_S  23
+/** DMA2D_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1;
+ *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+ *  working.
+ */
+#define DMA2D_INLINK_PARK_CH2    (BIT(24))
+#define DMA2D_INLINK_PARK_CH2_M  (DMA2D_INLINK_PARK_CH2_V << DMA2D_INLINK_PARK_CH2_S)
+#define DMA2D_INLINK_PARK_CH2_V  0x00000001U
+#define DMA2D_INLINK_PARK_CH2_S  24
+
+/** DMA2D_IN_LINK_ADDR_CH2_REG register
+ *  Configures the rx descriptor address of channel 2
+ */
+#define DMA2D_IN_LINK_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x720)
+/** DMA2D_INLINK_ADDR_CH2 : R/W; bitpos: [31:0]; default: 0;
+ *  This register stores the first inlink descriptor's address.
+ */
+#define DMA2D_INLINK_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_M  (DMA2D_INLINK_ADDR_CH2_V << DMA2D_INLINK_ADDR_CH2_S)
+#define DMA2D_INLINK_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_ADDR_CH2_S  0
+
+/** DMA2D_IN_STATE_CH2_REG register
+ *  Represents the working status of the rx descriptor of channel 2
+ */
+#define DMA2D_IN_STATE_CH2_REG (DR_REG_DMA2D_BASE + 0x724)
+/** DMA2D_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0;
+ *  This register stores the current inlink descriptor's address.
+ */
+#define DMA2D_INLINK_DSCR_ADDR_CH2    0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_M  (DMA2D_INLINK_DSCR_ADDR_CH2_V << DMA2D_INLINK_DSCR_ADDR_CH2_S)
+#define DMA2D_INLINK_DSCR_ADDR_CH2_V  0x0003FFFFU
+#define DMA2D_INLINK_DSCR_ADDR_CH2_S  0
+/** DMA2D_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_DSCR_STATE_CH2    0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_M  (DMA2D_IN_DSCR_STATE_CH2_V << DMA2D_IN_DSCR_STATE_CH2_S)
+#define DMA2D_IN_DSCR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_STATE_CH2_S  18
+/** DMA2D_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_STATE_CH2    0x00000007U
+#define DMA2D_IN_STATE_CH2_M  (DMA2D_IN_STATE_CH2_V << DMA2D_IN_STATE_CH2_S)
+#define DMA2D_IN_STATE_CH2_V  0x00000007U
+#define DMA2D_IN_STATE_CH2_S  20
+/** DMA2D_IN_RESET_AVAIL_CH2 : RO; bitpos: [23]; default: 1;
+ *  This register indicate that if the channel reset is safety.
+ */
+#define DMA2D_IN_RESET_AVAIL_CH2    (BIT(23))
+#define DMA2D_IN_RESET_AVAIL_CH2_M  (DMA2D_IN_RESET_AVAIL_CH2_V << DMA2D_IN_RESET_AVAIL_CH2_S)
+#define DMA2D_IN_RESET_AVAIL_CH2_V  0x00000001U
+#define DMA2D_IN_RESET_AVAIL_CH2_S  23
+
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x728)
+/** DMA2D_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when the EOF bit in this
+ *  descriptor is 1.
+ */
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_M  (DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V << DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_SUC_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA2D_BASE + 0x72c)
+/** DMA2D_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  This register stores the address of the inlink descriptor when there are some
+ *  errors in current receiving data.
+ */
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2    0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_M  (DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V << DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S)
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_V  0xFFFFFFFFU
+#define DMA2D_IN_ERR_EOF_DES_ADDR_CH2_S  0
+
+/** DMA2D_IN_DSCR_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_CH2_REG (DR_REG_DMA2D_BASE + 0x730)
+/** DMA2D_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the next inlink descriptor address x.
+ */
+#define DMA2D_INLINK_DSCR_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_M  (DMA2D_INLINK_DSCR_CH2_V << DMA2D_INLINK_DSCR_CH2_S)
+#define DMA2D_INLINK_DSCR_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF0_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF0_CH2_REG (DR_REG_DMA2D_BASE + 0x734)
+/** DMA2D_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the last inlink descriptor's next address x-1.
+ */
+#define DMA2D_INLINK_DSCR_BF0_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_M  (DMA2D_INLINK_DSCR_BF0_CH2_V << DMA2D_INLINK_DSCR_BF0_CH2_S)
+#define DMA2D_INLINK_DSCR_BF0_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF0_CH2_S  0
+
+/** DMA2D_IN_DSCR_BF1_CH2_REG register
+ *  Represents the address associated with the inlink descriptor of channel 2
+ */
+#define DMA2D_IN_DSCR_BF1_CH2_REG (DR_REG_DMA2D_BASE + 0x738)
+/** DMA2D_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0;
+ *  The address of the second-to-last inlink descriptor's next address x-2.
+ */
+#define DMA2D_INLINK_DSCR_BF1_CH2    0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_M  (DMA2D_INLINK_DSCR_BF1_CH2_V << DMA2D_INLINK_DSCR_BF1_CH2_S)
+#define DMA2D_INLINK_DSCR_BF1_CH2_V  0xFFFFFFFFU
+#define DMA2D_INLINK_DSCR_BF1_CH2_S  0
+
+/** DMA2D_IN_PERI_SEL_CH2_REG register
+ *  Configures the rx peripheral of channel 2
+ */
+#define DMA2D_IN_PERI_SEL_CH2_REG (DR_REG_DMA2D_BASE + 0x73c)
+/** DMA2D_IN_PERI_SEL_CH2 : R/W; bitpos: [2:0]; default: 7;
+ *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+ *  display-1     2: display-2        7: no choose
+ */
+#define DMA2D_IN_PERI_SEL_CH2    0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_M  (DMA2D_IN_PERI_SEL_CH2_V << DMA2D_IN_PERI_SEL_CH2_S)
+#define DMA2D_IN_PERI_SEL_CH2_V  0x00000007U
+#define DMA2D_IN_PERI_SEL_CH2_S  0
+
+/** DMA2D_IN_ARB_CH2_REG register
+ *  Configures the rx arbiter of channel 2
+ */
+#define DMA2D_IN_ARB_CH2_REG (DR_REG_DMA2D_BASE + 0x740)
+/** DMA2D_IN_ARB_TOKEN_NUM_CH2 : R/W; bitpos: [3:0]; default: 0;
+ *  Set the max number of token count of arbiter
+ */
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2    0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_M  (DMA2D_IN_ARB_TOKEN_NUM_CH2_V << DMA2D_IN_ARB_TOKEN_NUM_CH2_S)
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_ARB_TOKEN_NUM_CH2_S  0
+/** DMA2D_IN_ARB_PRIORITY_CH2 : R/W; bitpos: [7:4]; default: 0;
+ *  Set the priority of channel
+ */
+#define DMA2D_IN_ARB_PRIORITY_CH2    0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH2_M  (DMA2D_IN_ARB_PRIORITY_CH2_V << DMA2D_IN_ARB_PRIORITY_CH2_S)
+#define DMA2D_IN_ARB_PRIORITY_CH2_V  0x0000000FU
+#define DMA2D_IN_ARB_PRIORITY_CH2_S  4
+
+/** DMA2D_IN_RO_STATUS_CH2_REG register
+ *  Represents the status of the rx reorder module of channel 2
+ */
+#define DMA2D_IN_RO_STATUS_CH2_REG (DR_REG_DMA2D_BASE + 0x744)
+/** DMA2D_INFIFO_RO_CNT_CH2 : RO; bitpos: [4:0]; default: 0;
+ *  The register stores the byte number of the data in color convert Rx FIFO for
+ *  channel 0.
+ */
+#define DMA2D_INFIFO_RO_CNT_CH2    0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_M  (DMA2D_INFIFO_RO_CNT_CH2_V << DMA2D_INFIFO_RO_CNT_CH2_S)
+#define DMA2D_INFIFO_RO_CNT_CH2_V  0x0000001FU
+#define DMA2D_INFIFO_RO_CNT_CH2_S  0
+/** DMA2D_IN_RO_WR_STATE_CH2 : RO; bitpos: [6:5]; default: 0;
+ *  The register stores the state of read ram of reorder
+ */
+#define DMA2D_IN_RO_WR_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_M  (DMA2D_IN_RO_WR_STATE_CH2_V << DMA2D_IN_RO_WR_STATE_CH2_S)
+#define DMA2D_IN_RO_WR_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_WR_STATE_CH2_S  5
+/** DMA2D_IN_RO_RD_STATE_CH2 : RO; bitpos: [8:7]; default: 0;
+ *  The register stores the state of write ram of reorder
+ */
+#define DMA2D_IN_RO_RD_STATE_CH2    0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_M  (DMA2D_IN_RO_RD_STATE_CH2_V << DMA2D_IN_RO_RD_STATE_CH2_S)
+#define DMA2D_IN_RO_RD_STATE_CH2_V  0x00000003U
+#define DMA2D_IN_RO_RD_STATE_CH2_S  7
+/** DMA2D_IN_PIXEL_BYTE_CH2 : RO; bitpos: [12:9]; default: 0;
+ *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+ *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+ */
+#define DMA2D_IN_PIXEL_BYTE_CH2    0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_M  (DMA2D_IN_PIXEL_BYTE_CH2_V << DMA2D_IN_PIXEL_BYTE_CH2_S)
+#define DMA2D_IN_PIXEL_BYTE_CH2_V  0x0000000FU
+#define DMA2D_IN_PIXEL_BYTE_CH2_S  9
+/** DMA2D_IN_BURST_BLOCK_NUM_CH2 : RO; bitpos: [16:13]; default: 0;
+ *  the number of macro blocks contained in a burst of data at RX channel
+ */
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2    0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_M  (DMA2D_IN_BURST_BLOCK_NUM_CH2_V << DMA2D_IN_BURST_BLOCK_NUM_CH2_S)
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_V  0x0000000FU
+#define DMA2D_IN_BURST_BLOCK_NUM_CH2_S  13
+
+/** DMA2D_IN_ETM_CONF_CH2_REG register
+ *  Configures the rx etm of channel 2
+ */
+#define DMA2D_IN_ETM_CONF_CH2_REG (DR_REG_DMA2D_BASE + 0x76c)
+/** DMA2D_IN_ETM_EN_CH2 : R/W; bitpos: [0]; default: 0;
+ *  Configures the enable of the etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_EN_CH2    (BIT(0))
+#define DMA2D_IN_ETM_EN_CH2_M  (DMA2D_IN_ETM_EN_CH2_V << DMA2D_IN_ETM_EN_CH2_S)
+#define DMA2D_IN_ETM_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_EN_CH2_S  0
+/** DMA2D_IN_ETM_LOOP_EN_CH2 : R/W; bitpos: [1]; default: 0;
+ *  Configures the enable of the descriptors loop etm function, 1 is enable.
+ */
+#define DMA2D_IN_ETM_LOOP_EN_CH2    (BIT(1))
+#define DMA2D_IN_ETM_LOOP_EN_CH2_M  (DMA2D_IN_ETM_LOOP_EN_CH2_V << DMA2D_IN_ETM_LOOP_EN_CH2_S)
+#define DMA2D_IN_ETM_LOOP_EN_CH2_V  0x00000001U
+#define DMA2D_IN_ETM_LOOP_EN_CH2_S  1
+/** DMA2D_IN_DSCR_TASK_MAK_CH2 : R/W; bitpos: [3:2]; default: 1;
+ *  Configures the maximum number of cacheable descriptors.
+ */
+#define DMA2D_IN_DSCR_TASK_MAK_CH2    0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_M  (DMA2D_IN_DSCR_TASK_MAK_CH2_V << DMA2D_IN_DSCR_TASK_MAK_CH2_S)
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_V  0x00000003U
+#define DMA2D_IN_DSCR_TASK_MAK_CH2_S  2
+
+/** DMA2D_AXI_ERR_REG register
+ *  Represents the status of th axi bus
+ */
+#define DMA2D_AXI_ERR_REG (DR_REG_DMA2D_BASE + 0xa00)
+/** DMA2D_RID_ERR_CNT : RO; bitpos: [3:0]; default: 0;
+ *  AXI read id err cnt
+ */
+#define DMA2D_RID_ERR_CNT    0x0000000FU
+#define DMA2D_RID_ERR_CNT_M  (DMA2D_RID_ERR_CNT_V << DMA2D_RID_ERR_CNT_S)
+#define DMA2D_RID_ERR_CNT_V  0x0000000FU
+#define DMA2D_RID_ERR_CNT_S  0
+/** DMA2D_RRESP_ERR_CNT : RO; bitpos: [7:4]; default: 0;
+ *  AXI read resp err cnt
+ */
+#define DMA2D_RRESP_ERR_CNT    0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_M  (DMA2D_RRESP_ERR_CNT_V << DMA2D_RRESP_ERR_CNT_S)
+#define DMA2D_RRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_RRESP_ERR_CNT_S  4
+/** DMA2D_WRESP_ERR_CNT : RO; bitpos: [11:8]; default: 0;
+ *  AXI write resp err cnt
+ */
+#define DMA2D_WRESP_ERR_CNT    0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_M  (DMA2D_WRESP_ERR_CNT_V << DMA2D_WRESP_ERR_CNT_S)
+#define DMA2D_WRESP_ERR_CNT_V  0x0000000FU
+#define DMA2D_WRESP_ERR_CNT_S  8
+/** DMA2D_RD_FIFO_CNT : RO; bitpos: [14:12]; default: 0;
+ *  AXI read cmd fifo remain cmd count
+ */
+#define DMA2D_RD_FIFO_CNT    0x00000007U
+#define DMA2D_RD_FIFO_CNT_M  (DMA2D_RD_FIFO_CNT_V << DMA2D_RD_FIFO_CNT_S)
+#define DMA2D_RD_FIFO_CNT_V  0x00000007U
+#define DMA2D_RD_FIFO_CNT_S  12
+/** DMA2D_RD_BAK_FIFO_CNT : RO; bitpos: [18:15]; default: 0;
+ *  AXI read backup cmd fifo remain cmd count
+ */
+#define DMA2D_RD_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_M  (DMA2D_RD_BAK_FIFO_CNT_V << DMA2D_RD_BAK_FIFO_CNT_S)
+#define DMA2D_RD_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_RD_BAK_FIFO_CNT_S  15
+/** DMA2D_WR_FIFO_CNT : RO; bitpos: [21:19]; default: 0;
+ *  AXI write cmd fifo remain cmd count
+ */
+#define DMA2D_WR_FIFO_CNT    0x00000007U
+#define DMA2D_WR_FIFO_CNT_M  (DMA2D_WR_FIFO_CNT_V << DMA2D_WR_FIFO_CNT_S)
+#define DMA2D_WR_FIFO_CNT_V  0x00000007U
+#define DMA2D_WR_FIFO_CNT_S  19
+/** DMA2D_WR_BAK_FIFO_CNT : RO; bitpos: [25:22]; default: 0;
+ *  AXI write backup cmd fifo remain cmd count
+ */
+#define DMA2D_WR_BAK_FIFO_CNT    0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_M  (DMA2D_WR_BAK_FIFO_CNT_V << DMA2D_WR_BAK_FIFO_CNT_S)
+#define DMA2D_WR_BAK_FIFO_CNT_V  0x0000000FU
+#define DMA2D_WR_BAK_FIFO_CNT_S  22
+
+/** DMA2D_RST_CONF_REG register
+ *  Configures the reset of axi
+ */
+#define DMA2D_RST_CONF_REG (DR_REG_DMA2D_BASE + 0xa04)
+/** DMA2D_AXIM_RD_RST : R/W; bitpos: [0]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+ */
+#define DMA2D_AXIM_RD_RST    (BIT(0))
+#define DMA2D_AXIM_RD_RST_M  (DMA2D_AXIM_RD_RST_V << DMA2D_AXIM_RD_RST_S)
+#define DMA2D_AXIM_RD_RST_V  0x00000001U
+#define DMA2D_AXIM_RD_RST_S  0
+/** DMA2D_AXIM_WR_RST : R/W; bitpos: [1]; default: 0;
+ *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+ */
+#define DMA2D_AXIM_WR_RST    (BIT(1))
+#define DMA2D_AXIM_WR_RST_M  (DMA2D_AXIM_WR_RST_V << DMA2D_AXIM_WR_RST_S)
+#define DMA2D_AXIM_WR_RST_V  0x00000001U
+#define DMA2D_AXIM_WR_RST_S  1
+/** DMA2D_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define DMA2D_CLK_EN    (BIT(2))
+#define DMA2D_CLK_EN_M  (DMA2D_CLK_EN_V << DMA2D_CLK_EN_S)
+#define DMA2D_CLK_EN_V  0x00000001U
+#define DMA2D_CLK_EN_S  2
+
+/** DMA2D_INTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa08)
+/** DMA2D_ACCESS_INTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_M  (DMA2D_ACCESS_INTR_MEM_START_ADDR_V << DMA2D_ACCESS_INTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_START_ADDR_S  0
+
+/** DMA2D_INTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_INTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa0c)
+/** DMA2D_ACCESS_INTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_M  (DMA2D_ACCESS_INTR_MEM_END_ADDR_V << DMA2D_ACCESS_INTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_INTR_MEM_END_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_START_ADDR_REG register
+ *  The start address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_START_ADDR_REG (DR_REG_DMA2D_BASE + 0xa10)
+/** DMA2D_ACCESS_EXTR_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_START_ADDR_V << DMA2D_ACCESS_EXTR_MEM_START_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_START_ADDR_S  0
+
+/** DMA2D_EXTR_MEM_END_ADDR_REG register
+ *  The end address of accessible address space.
+ */
+#define DMA2D_EXTR_MEM_END_ADDR_REG (DR_REG_DMA2D_BASE + 0xa14)
+/** DMA2D_ACCESS_EXTR_MEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The end address of accessible address space. The access address beyond this range
+ *  would lead to descriptor error.
+ */
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR    0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_M  (DMA2D_ACCESS_EXTR_MEM_END_ADDR_V << DMA2D_ACCESS_EXTR_MEM_END_ADDR_S)
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_V  0xFFFFFFFFU
+#define DMA2D_ACCESS_EXTR_MEM_END_ADDR_S  0
+
+/** DMA2D_OUT_ARB_CONFIG_REG register
+ *  Configures the tx arbiter
+ */
+#define DMA2D_OUT_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa18)
+/** DMA2D_OUT_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_OUT_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_M  (DMA2D_OUT_ARB_TIMEOUT_NUM_V << DMA2D_OUT_ARB_TIMEOUT_NUM_S)
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_OUT_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_OUT_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_OUT_WEIGHT_EN    (BIT(16))
+#define DMA2D_OUT_WEIGHT_EN_M  (DMA2D_OUT_WEIGHT_EN_V << DMA2D_OUT_WEIGHT_EN_S)
+#define DMA2D_OUT_WEIGHT_EN_V  0x00000001U
+#define DMA2D_OUT_WEIGHT_EN_S  16
+
+/** DMA2D_IN_ARB_CONFIG_REG register
+ *  Configures the rx arbiter
+ */
+#define DMA2D_IN_ARB_CONFIG_REG (DR_REG_DMA2D_BASE + 0xa1c)
+/** DMA2D_IN_ARB_TIMEOUT_NUM : R/W; bitpos: [15:0]; default: 0;
+ *  Set the max number of timeout count of arbiter
+ */
+#define DMA2D_IN_ARB_TIMEOUT_NUM    0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_M  (DMA2D_IN_ARB_TIMEOUT_NUM_V << DMA2D_IN_ARB_TIMEOUT_NUM_S)
+#define DMA2D_IN_ARB_TIMEOUT_NUM_V  0x0000FFFFU
+#define DMA2D_IN_ARB_TIMEOUT_NUM_S  0
+/** DMA2D_IN_WEIGHT_EN : R/W; bitpos: [16]; default: 0;
+ *  reserved
+ */
+#define DMA2D_IN_WEIGHT_EN    (BIT(16))
+#define DMA2D_IN_WEIGHT_EN_M  (DMA2D_IN_WEIGHT_EN_V << DMA2D_IN_WEIGHT_EN_S)
+#define DMA2D_IN_WEIGHT_EN_V  0x00000001U
+#define DMA2D_IN_WEIGHT_EN_S  16
+
+/** DMA2D_RDN_RESULT_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT_REG (DR_REG_DMA2D_BASE + 0xa20)
+/** DMA2D_RDN_ENA : R/W; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_ENA    (BIT(0))
+#define DMA2D_RDN_ENA_M  (DMA2D_RDN_ENA_V << DMA2D_RDN_ENA_S)
+#define DMA2D_RDN_ENA_V  0x00000001U
+#define DMA2D_RDN_ENA_S  0
+/** DMA2D_RDN_RESULT : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define DMA2D_RDN_RESULT    (BIT(1))
+#define DMA2D_RDN_RESULT_M  (DMA2D_RDN_RESULT_V << DMA2D_RDN_RESULT_S)
+#define DMA2D_RDN_RESULT_V  0x00000001U
+#define DMA2D_RDN_RESULT_S  1
+
+/** DMA2D_RDN_ECO_HIGH_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_HIGH_REG (DR_REG_DMA2D_BASE + 0xa24)
+/** DMA2D_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_HIGH    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_M  (DMA2D_RDN_ECO_HIGH_V << DMA2D_RDN_ECO_HIGH_S)
+#define DMA2D_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_HIGH_S  0
+
+/** DMA2D_RDN_ECO_LOW_REG register
+ *  reserved
+ */
+#define DMA2D_RDN_ECO_LOW_REG (DR_REG_DMA2D_BASE + 0xa28)
+/** DMA2D_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  The start address of accessible address space.
+ */
+#define DMA2D_RDN_ECO_LOW    0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_M  (DMA2D_RDN_ECO_LOW_V << DMA2D_RDN_ECO_LOW_S)
+#define DMA2D_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define DMA2D_RDN_ECO_LOW_S  0
+
+/** DMA2D_DATE_REG register
+ *  register version.
+ */
+#define DMA2D_DATE_REG (DR_REG_DMA2D_BASE + 0xa2c)
+/** DMA2D_DATE : R/W; bitpos: [31:0]; default: 36725136;
+ *  register version.
+ */
+#define DMA2D_DATE    0xFFFFFFFFU
+#define DMA2D_DATE_M  (DMA2D_DATE_V << DMA2D_DATE_S)
+#define DMA2D_DATE_V  0xFFFFFFFFU
+#define DMA2D_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/dma2d_struct.h b/components/soc/esp32s31/register/soc/dma2d_struct.h
new file mode 100644
index 00000000000..3f89f6a8ccf
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/dma2d_struct.h
@@ -0,0 +1,2060 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of out_conf0_chn register
+ *  Configures the tx direction of channel n
+ */
+typedef union {
+    struct {
+        /** out_auto_wrback_chn : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable automatic outlink-writeback when all the data pointed by
+         *  outlink descriptor has been received.
+         */
+        uint32_t out_auto_wrback_chn:1;
+        /** out_eof_mode_chn : R/W; bitpos: [1]; default: 1;
+         *  EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is
+         *  generated when data need to read has been popped from FIFO in DMA
+         */
+        uint32_t out_eof_mode_chn:1;
+        /** outdscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+         *  descriptor when accessing internal SRAM.
+         */
+        uint32_t outdscr_burst_en_chn:1;
+        /** out_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t out_ecc_aes_en_chn:1;
+        /** out_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t out_check_owner_chn:1;
+        /** out_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t out_loop_test_chn:1;
+        /** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Tx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t out_mem_burst_length_chn:3;
+        /** out_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel TX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t out_macro_block_size_chn:2;
+        /** out_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t out_dscr_port_en_chn:1;
+        /** out_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI read data don't cross the address boundary which
+         *  define by mem_burst_length
+         */
+        uint32_t out_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** out_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable TX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t out_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** out_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset TX channel
+         */
+        uint32_t out_rst_chn:1;
+        /** out_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t out_cmd_disable_chn:1;
+        /** out_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t out_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_out_conf0_chn_reg_t;
+
+/** Type of out_push_chn register
+ *  Configures the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_wdata_chn : R/W; bitpos: [9:0]; default: 0;
+         *  This register stores the data that need to be pushed into DMA Tx FIFO.
+         */
+        uint32_t outfifo_wdata_chn:10;
+        /** outfifo_push_chn : R/W/SC; bitpos: [10]; default: 0;
+         *  Set this bit to push data into DMA Tx FIFO.
+         */
+        uint32_t outfifo_push_chn:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} dma2d_out_push_chn_reg_t;
+
+/** Type of out_link_conf_chn register
+ *  Configures the tx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** outlink_stop_chn : R/W/SC; bitpos: [20]; default: 0;
+         *  Set this bit to stop dealing with the outlink descriptors.
+         */
+        uint32_t outlink_stop_chn:1;
+        /** outlink_start_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to start dealing with the outlink descriptors.
+         */
+        uint32_t outlink_start_chn:1;
+        /** outlink_restart_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to restart a new outlink from the last address.
+         */
+        uint32_t outlink_restart_chn:1;
+        /** outlink_park_chn : RO; bitpos: [23]; default: 1;
+         *  1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM
+         *  is working.
+         */
+        uint32_t outlink_park_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_out_link_conf_chn_reg_t;
+
+/** Type of out_link_addr_chn register
+ *  Configures the tx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first outlink descriptor's address.
+         */
+        uint32_t outlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_link_addr_chn_reg_t;
+
+/** Type of out_arb_chn register
+ *  Configures the tx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** out_arb_token_num_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t out_arb_token_num_chn:4;
+        /** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t out_arb_priority_chn:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_out_arb_chn_reg_t;
+
+/** Type of out_ro_pd_conf_chn register
+ *  Configures the tx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** out_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 1;
+         *  unused! dma reorder ram power down
+         */
+        uint32_t out_ro_ram_force_pd_chn:1;
+        /** out_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 0;
+         *  unused! dma reorder ram power up
+         */
+        uint32_t out_ro_ram_force_pu_chn:1;
+        /** out_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t out_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_out_ro_pd_conf_chn_reg_t;
+
+/** Type of out_color_convert_chn register
+ *  Configures the tx color convert of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  YUV444 to YUV422     2: output directly
+         */
+        uint32_t out_color_output_sel_chn:2;
+        /** out_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t out_color_3b_proc_en_chn:1;
+        /** out_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: RGB565 to RGB888     1:
+         *  YUV422 to YUV444      2: Other 2byte/pixel type    3: Other 3byte/pixel type    7:
+         *  disable color space convert
+         */
+        uint32_t out_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_out_color_convert_chn_reg_t;
+
+/** Type of out_scramble_chn register
+ *  Configures the tx scramble of channel n
+ */
+typedef union {
+    struct {
+        /** out_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t out_scramble_sel_pre_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_scramble_chn_reg_t;
+
+/** Type of out_color_param0_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param0_chn_reg_t;
+
+/** Type of out_color_param1_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param1_chn_reg_t;
+
+/** Type of out_color_param2_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param2_chn_reg_t;
+
+/** Type of out_color_param3_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param3_chn_reg_t;
+
+/** Type of out_color_param4_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_out_color_param4_chn_reg_t;
+
+/** Type of out_color_param5_chn register
+ *  Configures the tx color convert parameter of channel n
+ */
+typedef union {
+    struct {
+        /** out_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t out_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_color_param5_chn_reg_t;
+
+/** Type of out_etm_conf_chn register
+ *  Configures the tx etm of channel n
+ */
+typedef union {
+    struct {
+        /** out_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t out_etm_en_chn:1;
+        /** out_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t out_etm_loop_en_chn:1;
+        /** out_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t out_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_out_etm_conf_chn_reg_t;
+
+/** Type of out_dscr_port_blk_chn register
+ *  Configures the tx block size in dscr port mode
+ */
+typedef union {
+    struct {
+        /** out_dscr_port_blk_h_chn : R/W; bitpos: [13:0]; default: 18;
+         *  Set the vertical height of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_h_chn:14;
+        /** out_dscr_port_blk_v_chn : R/W; bitpos: [27:14]; default: 18;
+         *  Set the horizontal width of tx block size in dscr port mode
+         */
+        uint32_t out_dscr_port_blk_v_chn:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_out_dscr_port_blk_chn_reg_t;
+
+/** Type of in_conf0_chn register
+ *  Configures the rx direction of channel n
+ */
+typedef union {
+    struct {
+        /** in_mem_trans_en_chn : R/W; bitpos: [0]; default: 0;
+         *  enable memory trans of the same channel
+         */
+        uint32_t in_mem_trans_en_chn:1;
+        uint32_t reserved_1:1;
+        /** indscr_burst_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor
+         *  when accessing SRAM.
+         */
+        uint32_t indscr_burst_en_chn:1;
+        /** in_ecc_aes_en_chn : R/W; bitpos: [3]; default: 0;
+         *  When access address space is ecc/aes area, this bit should be set to 1. In this
+         *  case, the start address of square should be 16-bit aligned. The width of square
+         *  multiply byte number of one pixel should be 16-bit aligned.
+         */
+        uint32_t in_ecc_aes_en_chn:1;
+        /** in_check_owner_chn : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable checking the owner attribute of the link descriptor.
+         */
+        uint32_t in_check_owner_chn:1;
+        /** in_loop_test_chn : R/W; bitpos: [5]; default: 0;
+         *  reserved
+         */
+        uint32_t in_loop_test_chn:1;
+        /** in_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
+         *  Block size of Rx channel 0. 0: single      1: 16 bytes      2: 32 bytes    3: 64
+         *  bytes    4: 128 bytes
+         */
+        uint32_t in_mem_burst_length_chn:3;
+        /** in_macro_block_size_chn : R/W; bitpos: [10:9]; default: 0;
+         *  Sel RX macro-block size 0: 8pixel*8pixel     1: 8pixel*16pixel     2:
+         *  16pixel*16pixel     3: no macro-block     , only useful in mode 1 of the link
+         *  descriptor
+         */
+        uint32_t in_macro_block_size_chn:2;
+        /** in_dscr_port_en_chn : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to 1 to obtain descriptor from IP port
+         */
+        uint32_t in_dscr_port_en_chn:1;
+        /** in_page_bound_en_chn : R/W; bitpos: [12]; default: 0;
+         *  Set this bit to 1 to make sure AXI write data don't cross the address boundary
+         *  which define by mem_burst_length
+         */
+        uint32_t in_page_bound_en_chn:1;
+        uint32_t reserved_13:3;
+        /** in_reorder_en_chn : R/W; bitpos: [16]; default: 0;
+         *  Enable RX channel 0 macro block reorder when set to 1, only channel0 have this
+         *  selection
+         */
+        uint32_t in_reorder_en_chn:1;
+        uint32_t reserved_17:7;
+        /** in_rst_chn : R/W; bitpos: [24]; default: 0;
+         *  Write 1 then write 0 to this bit to reset Rx channel
+         */
+        uint32_t in_rst_chn:1;
+        /** in_cmd_disable_chn : R/W; bitpos: [25]; default: 0;
+         *  Write 1 before reset and write 0 after reset
+         */
+        uint32_t in_cmd_disable_chn:1;
+        /** in_arb_weight_opt_dis_chn : R/W; bitpos: [26]; default: 0;
+         *  Set this bit to 1 to disable arbiter optimum weight function.
+         */
+        uint32_t in_arb_weight_opt_dis_chn:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} dma2d_in_conf0_chn_reg_t;
+
+/** Type of in_pop_chn register
+ *  Configures the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_rdata_chn : RO; bitpos: [10:0]; default: 1024;
+         *  This register stores the data popping from DMA Rx FIFO.
+         */
+        uint32_t infifo_rdata_chn:11;
+        /** infifo_pop_chn : R/W/SC; bitpos: [11]; default: 0;
+         *  Set this bit to pop data from DMA Rx FIFO.
+         */
+        uint32_t infifo_pop_chn:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} dma2d_in_pop_chn_reg_t;
+
+/** Type of in_link_conf_chn register
+ *  Configures the rx descriptor operations of channel n
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** inlink_auto_ret_chn : R/W; bitpos: [20]; default: 1;
+         *  Set this bit to return to current inlink descriptor's address, when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t inlink_auto_ret_chn:1;
+        /** inlink_stop_chn : R/W/SC; bitpos: [21]; default: 0;
+         *  Set this bit to stop dealing with the inlink descriptors.
+         */
+        uint32_t inlink_stop_chn:1;
+        /** inlink_start_chn : R/W/SC; bitpos: [22]; default: 0;
+         *  Set this bit to start dealing with the inlink descriptors.
+         */
+        uint32_t inlink_start_chn:1;
+        /** inlink_restart_chn : R/W/SC; bitpos: [23]; default: 0;
+         *  Set this bit to mount a new inlink descriptor.
+         */
+        uint32_t inlink_restart_chn:1;
+        /** inlink_park_chn : RO; bitpos: [24]; default: 1;
+         *  1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is
+         *  working.
+         */
+        uint32_t inlink_park_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_in_link_conf_chn_reg_t;
+
+/** Type of in_link_addr_chn register
+ *  Configures the rx descriptor address of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_addr_chn : R/W; bitpos: [31:0]; default: 0;
+         *  This register stores the first inlink descriptor's address.
+         */
+        uint32_t inlink_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_link_addr_chn_reg_t;
+
+/** Type of in_arb_chn register
+ *  Configures the rx arbiter of channel n
+ */
+typedef union {
+    struct {
+        /** in_arb_token_num_chn : R/W; bitpos: [3:0]; default: 0;
+         *  Set the max number of token count of arbiter
+         */
+        uint32_t in_arb_token_num_chn:4;
+        /** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 0;
+         *  Set the priority of channel
+         */
+        uint32_t in_arb_priority_chn:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} dma2d_in_arb_chn_reg_t;
+
+/** Type of in_ro_pd_conf_chn register
+ *  Configures the rx reorder memory of channel 0
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** in_ro_ram_force_pd_chn : R/W; bitpos: [4]; default: 1;
+         *  unused! dma reorder ram power down
+         */
+        uint32_t in_ro_ram_force_pd_chn:1;
+        /** in_ro_ram_force_pu_chn : R/W; bitpos: [5]; default: 0;
+         *  unused! dma reorder ram power up
+         */
+        uint32_t in_ro_ram_force_pu_chn:1;
+        /** in_ro_ram_clk_fo_chn : R/W; bitpos: [6]; default: 0;
+         *  1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA.
+         *  0: A gate-clock will be used when accessing the RAM in DMA.
+         */
+        uint32_t in_ro_ram_clk_fo_chn:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} dma2d_in_ro_pd_conf_chn_reg_t;
+
+/** Type of in_color_convert_chn register
+ *  Configures the Rx color convert of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
+         *  Set final color convert process and output type    0: RGB888 to RGB565     1:
+         *  output directly     2: YUV444 to YUV422    3: YUV444 to YUV420
+         */
+        uint32_t in_color_output_sel_chn:2;
+        /** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
+         *  Enable generic color convert module between color input & color output, need to
+         *  configure parameter.
+         */
+        uint32_t in_color_3b_proc_en_chn:1;
+        /** in_color_input_sel_chn : R/W; bitpos: [5:3]; default: 7;
+         *  Set first color convert process and input color type    0: YUV422/420 to YUV444
+         *  1: YUV422      2: YUV444/420      7: disable color space convert
+         */
+        uint32_t in_color_input_sel_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_color_convert_chn_reg_t;
+
+/** Type of in_scramble_chn register
+ *  Configures the rx scramble of channel 0
+ */
+typedef union {
+    struct {
+        /** in_scramble_sel_pre_chn : R/W; bitpos: [2:0]; default: 0;
+         *  Scramble data before color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 :
+         *  BYTE1-0-2    3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_pre_chn:3;
+        /** in_scramble_sel_post_chn : R/W; bitpos: [5:3]; default: 0;
+         *  Scramble data after color convert :  0 : BYTE2-1-0   1 : BYTE2-0-1    2 : BYTE1-0-2
+         *  3 : BYTE1-2-0    4 : BYTE0-2-1    5 : BYTE0-1-2
+         */
+        uint32_t in_scramble_sel_post_chn:3;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} dma2d_in_scramble_chn_reg_t;
+
+/** Type of in_color_param0_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_h0_chn : R/W; bitpos: [20:0]; default: 298;
+         *  Set first 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param0_chn_reg_t;
+
+/** Type of in_color_param1_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_h1_chn : R/W; bitpos: [27:0]; default: 210164121;
+         *  Set last 2 parameter of most significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_h1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param1_chn_reg_t;
+
+/** Type of in_color_param2_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_m0_chn : R/W; bitpos: [20:0]; default: 1995050;
+         *  Set first 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param2_chn_reg_t;
+
+/** Type of in_color_param3_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_m1_chn : R/W; bitpos: [27:0]; default: 35540784;
+         *  Set last 2 parameter of midium significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_m1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param3_chn_reg_t;
+
+/** Type of in_color_param4_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_l0_chn : R/W; bitpos: [20:0]; default: 528682;
+         *  Set first 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l0_chn:21;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} dma2d_in_color_param4_chn_reg_t;
+
+/** Type of in_color_param5_chn register
+ *  Configures the rx color convert parameter of channel 0
+ */
+typedef union {
+    struct {
+        /** in_color_param_l1_chn : R/W; bitpos: [27:0]; default: 195899392;
+         *  Set last 2 parameter of least significant byte of pending 3 bytes
+         */
+        uint32_t in_color_param_l1_chn:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} dma2d_in_color_param5_chn_reg_t;
+
+/** Type of in_etm_conf_chn register
+ *  Configures the rx etm of channel n
+ */
+typedef union {
+    struct {
+        /** in_etm_en_chn : R/W; bitpos: [0]; default: 0;
+         *  Configures the enable of the etm function, 1 is enable.
+         */
+        uint32_t in_etm_en_chn:1;
+        /** in_etm_loop_en_chn : R/W; bitpos: [1]; default: 0;
+         *  Configures the enable of the descriptors loop etm function, 1 is enable.
+         */
+        uint32_t in_etm_loop_en_chn:1;
+        /** in_dscr_task_mak_chn : R/W; bitpos: [3:2]; default: 1;
+         *  Configures the maximum number of cacheable descriptors.
+         */
+        uint32_t in_dscr_task_mak_chn:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} dma2d_in_etm_conf_chn_reg_t;
+
+/** Type of rst_conf register
+ *  Configures the reset of axi
+ */
+typedef union {
+    struct {
+        /** axim_rd_rst : R/W; bitpos: [0]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master read data FIFO.
+         */
+        uint32_t axim_rd_rst:1;
+        /** axim_wr_rst : R/W; bitpos: [1]; default: 0;
+         *  Write 1 then write 0  to this bit to reset axi master write data FIFO.
+         */
+        uint32_t axim_wr_rst:1;
+        /** clk_en : R/W; bitpos: [2]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_rst_conf_reg_t;
+
+/** Type of intr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_intr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_start_addr_reg_t;
+
+/** Type of intr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_intr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_intr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_intr_mem_end_addr_reg_t;
+
+/** Type of extr_mem_start_addr register
+ *  The start address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t access_extr_mem_start_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_start_addr_reg_t;
+
+/** Type of extr_mem_end_addr register
+ *  The end address of accessible address space.
+ */
+typedef union {
+    struct {
+        /** access_extr_mem_end_addr : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The end address of accessible address space. The access address beyond this range
+         *  would lead to descriptor error.
+         */
+        uint32_t access_extr_mem_end_addr:32;
+    };
+    uint32_t val;
+} dma2d_extr_mem_end_addr_reg_t;
+
+/** Type of out_arb_config register
+ *  Configures the tx arbiter
+ */
+typedef union {
+    struct {
+        /** out_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t out_arb_timeout_num:16;
+        /** out_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t out_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_out_arb_config_reg_t;
+
+/** Type of in_arb_config register
+ *  Configures the rx arbiter
+ */
+typedef union {
+    struct {
+        /** in_arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
+         *  Set the max number of timeout count of arbiter
+         */
+        uint32_t in_arb_timeout_num:16;
+        /** in_weight_en : R/W; bitpos: [16]; default: 0;
+         *  reserved
+         */
+        uint32_t in_weight_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_arb_config_reg_t;
+
+/** Type of rdn_result register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_ena : R/W; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_ena:1;
+        /** rdn_result : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t rdn_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} dma2d_rdn_result_reg_t;
+
+/** Type of rdn_eco_high register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_high:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_high_reg_t;
+
+/** Type of rdn_eco_low register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  The start address of accessible address space.
+         */
+        uint32_t rdn_eco_low:32;
+    };
+    uint32_t val;
+} dma2d_rdn_eco_low_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of out_int_raw_chn register
+ *  Raw interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been transmitted to peripherals for Tx channel 0.
+         */
+        uint32_t out_done_chn_int_raw:1;
+        /** out_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one outlink
+         *  descriptor has been read from memory for Tx channel 0.
+         */
+        uint32_t out_eof_chn_int_raw:1;
+        /** out_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting outlink descriptor error,
+         *  including owner error, the second and third word error of outlink descriptor for Tx
+         *  channel 0.
+         */
+        uint32_t out_dscr_err_chn_int_raw:1;
+        /** out_total_eof_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when data corresponding a outlink
+         *  (includes one link descriptor or few link descriptors) is transmitted out for Tx
+         *  channel 0.
+         */
+        uint32_t out_total_eof_chn_int_raw:1;
+        /** outfifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_raw:1;
+        /** outfifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l1_chn_int_raw:1;
+        /** outfifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_raw:1;
+        /** outfifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l2_chn_int_raw:1;
+        /** outfifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is overflow.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_raw:1;
+        /** outfifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo is underflow.
+         */
+        uint32_t outfifo_udf_l3_chn_int_raw:1;
+        /** outfifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_raw:1;
+        /** outfifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t outfifo_ro_udf_chn_int_raw:1;
+        /** out_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_raw_chn_reg_t;
+
+/** Type of out_int_ena_chn register
+ *  Interrupt enable bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_ena:1;
+        /** out_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_ena:1;
+        /** out_dscr_err_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_ena:1;
+        /** out_total_eof_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_ena:1;
+        /** outfifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_ena:1;
+        /** outfifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_ena:1;
+        /** outfifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_ena:1;
+        /** outfifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_ena:1;
+        /** outfifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_ena:1;
+        /** outfifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_ena:1;
+        /** outfifo_ro_ovf_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_ena:1;
+        /** outfifo_ro_udf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_ena:1;
+        /** out_dscr_task_ovf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_ena_chn_reg_t;
+
+/** Type of out_int_st_chn register
+ *  Masked interrupt status of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_st:1;
+        /** out_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_st:1;
+        /** out_dscr_err_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_st:1;
+        /** out_total_eof_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_st:1;
+        /** outfifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_st:1;
+        /** outfifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_st:1;
+        /** outfifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_st:1;
+        /** outfifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_st:1;
+        /** outfifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_st:1;
+        /** outfifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_st:1;
+        /** outfifo_ro_ovf_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_st:1;
+        /** outfifo_ro_udf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_st:1;
+        /** out_dscr_task_ovf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_st_chn_reg_t;
+
+/** Type of out_int_clr_chn register
+ *  Interrupt clear bits of TX channel n
+ */
+typedef union {
+    struct {
+        /** out_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+         */
+        uint32_t out_done_chn_int_clr:1;
+        /** out_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+         */
+        uint32_t out_eof_chn_int_clr:1;
+        /** out_dscr_err_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t out_dscr_err_chn_int_clr:1;
+        /** out_total_eof_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+         */
+        uint32_t out_total_eof_chn_int_clr:1;
+        /** outfifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l1_chn_int_clr:1;
+        /** outfifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l1_chn_int_clr:1;
+        /** outfifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l2_chn_int_clr:1;
+        /** outfifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l2_chn_int_clr:1;
+        /** outfifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_ovf_l3_chn_int_clr:1;
+        /** outfifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t outfifo_udf_l3_chn_int_clr:1;
+        /** outfifo_ro_ovf_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_ovf_chn_int_clr:1;
+        /** outfifo_ro_udf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the OUTFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t outfifo_ro_udf_chn_int_clr:1;
+        /** out_dscr_task_ovf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t out_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} dma2d_out_int_clr_chn_reg_t;
+
+/** Type of in_int_raw_chn register
+ *  Raw interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been transmitted to peripherals for Rx channel 0.
+         */
+        uint32_t in_done_chn_int_raw:1;
+        /** in_suc_eof_chn_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and no data error is detected for Rx channel 0.
+         */
+        uint32_t in_suc_eof_chn_int_raw:1;
+        /** in_err_eof_chn_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when the last data pointed by one inlink
+         *  descriptor has been received and data error is detected
+         */
+        uint32_t in_err_eof_chn_int_raw:1;
+        /** in_dscr_err_chn_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt bit turns to high level when detecting inlink descriptor error,
+         *  including owner error, the second and third word error of inlink descriptor for Rx
+         *  channel 0.
+         */
+        uint32_t in_dscr_err_chn_int_raw:1;
+        /** infifo_ovf_l1_chn_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l1_chn_int_raw:1;
+        /** infifo_udf_l1_chn_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l1_chn_int_raw:1;
+        /** infifo_ovf_l2_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l2_chn_int_raw:1;
+        /** infifo_udf_l2_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l2_chn_int_raw:1;
+        /** infifo_ovf_l3_chn_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is overflow.
+         */
+        uint32_t infifo_ovf_l3_chn_int_raw:1;
+        /** infifo_udf_l3_chn_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when fifo of Rx channel is underflow.
+         */
+        uint32_t infifo_udf_l3_chn_int_raw:1;
+        /** in_dscr_empty_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when the last descriptor is done but fifo
+         *  also remain data.
+         */
+        uint32_t in_dscr_empty_chn_int_raw:1;
+        /** infifo_ro_ovf_chn_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is overflow.
+         */
+        uint32_t infifo_ro_ovf_chn_int_raw:1;
+        /** infifo_ro_udf_chn_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
+         *  The raw interrupt bit turns to high level when reorder fifo is underflow.
+         */
+        uint32_t infifo_ro_udf_chn_int_raw:1;
+        /** in_dscr_task_ovf_chn_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
+         *  The raw interrupt bit turns to high level when dscr ready task fifo is overflow.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_raw:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_raw_chn_reg_t;
+
+/** Type of in_int_ena_chn register
+ *  Interrupt enable bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_ena:1;
+        /** in_suc_eof_chn_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_ena:1;
+        /** in_err_eof_chn_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_ena:1;
+        /** in_dscr_err_chn_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_ena:1;
+        /** infifo_ovf_l1_chn_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_ena:1;
+        /** infifo_udf_l1_chn_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_ena:1;
+        /** infifo_ovf_l2_chn_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_ena:1;
+        /** infifo_udf_l2_chn_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_ena:1;
+        /** infifo_ovf_l3_chn_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_ena:1;
+        /** infifo_udf_l3_chn_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_ena:1;
+        /** in_dscr_empty_chn_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_ena:1;
+        /** infifo_ro_ovf_chn_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_ena:1;
+        /** infifo_ro_udf_chn_int_ena : R/W; bitpos: [12]; default: 0;
+         *  The interrupt enable bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_ena:1;
+        /** in_dscr_task_ovf_chn_int_ena : R/W; bitpos: [13]; default: 0;
+         *  The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_ena:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_ena_chn_reg_t;
+
+/** Type of in_int_st_chn register
+ *  Masked interrupt status of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_st:1;
+        /** in_suc_eof_chn_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_st:1;
+        /** in_err_eof_chn_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_st:1;
+        /** in_dscr_err_chn_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_st:1;
+        /** infifo_ovf_l1_chn_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_st:1;
+        /** infifo_udf_l1_chn_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_st:1;
+        /** infifo_ovf_l2_chn_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_st:1;
+        /** infifo_udf_l2_chn_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_st:1;
+        /** infifo_ovf_l3_chn_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_st:1;
+        /** infifo_udf_l3_chn_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_st:1;
+        /** in_dscr_empty_chn_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_st:1;
+        /** infifo_ro_ovf_chn_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_st:1;
+        /** infifo_ro_udf_chn_int_st : RO; bitpos: [12]; default: 0;
+         *  The raw interrupt status bit for the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_st:1;
+        /** in_dscr_task_ovf_chn_int_st : RO; bitpos: [13]; default: 0;
+         *  The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_st:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_st_chn_reg_t;
+
+/** Type of in_int_clr_chn register
+ *  Interrupt clear bits of RX channel n
+ */
+typedef union {
+    struct {
+        /** in_done_chn_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the IN_DONE_CH_INT interrupt.
+         */
+        uint32_t in_done_chn_int_clr:1;
+        /** in_suc_eof_chn_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+         */
+        uint32_t in_suc_eof_chn_int_clr:1;
+        /** in_err_eof_chn_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+         */
+        uint32_t in_err_eof_chn_int_clr:1;
+        /** in_dscr_err_chn_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the INDSCR_ERR_CH_INT interrupt.
+         */
+        uint32_t in_dscr_err_chn_int_clr:1;
+        /** infifo_ovf_l1_chn_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l1_chn_int_clr:1;
+        /** infifo_udf_l1_chn_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l1_chn_int_clr:1;
+        /** infifo_ovf_l2_chn_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l2_chn_int_clr:1;
+        /** infifo_udf_l2_chn_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l2_chn_int_clr:1;
+        /** infifo_ovf_l3_chn_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_ovf_l3_chn_int_clr:1;
+        /** infifo_udf_l3_chn_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.
+         */
+        uint32_t infifo_udf_l3_chn_int_clr:1;
+        /** in_dscr_empty_chn_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+         */
+        uint32_t in_dscr_empty_chn_int_clr:1;
+        /** infifo_ro_ovf_chn_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_OVF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_ovf_chn_int_clr:1;
+        /** infifo_ro_udf_chn_int_clr : WT; bitpos: [12]; default: 0;
+         *  Set this bit to clear the INFIFO_RO_UDF_CH_INT interrupt.
+         */
+        uint32_t infifo_ro_udf_chn_int_clr:1;
+        /** in_dscr_task_ovf_chn_int_clr : WT; bitpos: [13]; default: 0;
+         *  Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt.
+         */
+        uint32_t in_dscr_task_ovf_chn_int_clr:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} dma2d_in_int_clr_chn_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of outfifo_status_chn register
+ *  Represents the status of the tx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l2_chn:1;
+        /** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l2_chn:1;
+        /** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** out_remain_under_1b_chn : RO; bitpos: [7]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_1b_chn:1;
+        /** out_remain_under_2b_chn : RO; bitpos: [8]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_2b_chn:1;
+        /** out_remain_under_3b_chn : RO; bitpos: [9]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_3b_chn:1;
+        /** out_remain_under_4b_chn : RO; bitpos: [10]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_4b_chn:1;
+        /** out_remain_under_5b_chn : RO; bitpos: [11]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_5b_chn:1;
+        /** out_remain_under_6b_chn : RO; bitpos: [12]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_6b_chn:1;
+        /** out_remain_under_7b_chn : RO; bitpos: [13]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_7b_chn:1;
+        /** out_remain_under_8b_chn : RO; bitpos: [14]; default: 1;
+         *  reserved
+         */
+        uint32_t out_remain_under_8b_chn:1;
+        /** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l1_chn:1;
+        /** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l1_chn:1;
+        /** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l1_chn:5;
+        /** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Tx FIFO full signal for Tx channel 0.
+         */
+        uint32_t outfifo_full_l3_chn:1;
+        /** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Tx FIFO empty signal for Tx channel 0.
+         */
+        uint32_t outfifo_empty_l3_chn:1;
+        /** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Tx FIFO for Tx channel 0.
+         */
+        uint32_t outfifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_outfifo_status_chn_reg_t;
+
+/** Type of out_state_chn register
+ *  Represents the working status of the tx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current outlink descriptor's address.
+         */
+        uint32_t outlink_dscr_addr_chn:18;
+        /** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  This register stores the current descriptor state machine state.
+         */
+        uint32_t out_dscr_state_chn:2;
+        /** out_state_chn : RO; bitpos: [23:20]; default: 0;
+         *  This register stores the current control module state machine state.
+         */
+        uint32_t out_state_chn:4;
+        /** out_reset_avail_chn : RO; bitpos: [24]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t out_reset_avail_chn:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} dma2d_out_state_chn_reg_t;
+
+/** Type of out_eof_des_addr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** out_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the outlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t out_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_eof_des_addr_chn_reg_t;
+
+/** Type of out_dscr_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next outlink descriptor address y.
+         */
+        uint32_t outlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_chn_reg_t;
+
+/** Type of out_dscr_bf0_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last outlink descriptor's next address y-1.
+         */
+        uint32_t outlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf0_chn_reg_t;
+
+/** Type of out_dscr_bf1_chn register
+ *  Represents the address associated with the outlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last outlink descriptor's next address y-2.
+         */
+        uint32_t outlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_out_dscr_bf1_chn_reg_t;
+
+/** Type of out_ro_status_chn register
+ *  Represents the status of the tx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** outfifo_ro_cnt_chn : RO; bitpos: [5:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Tx FIFO for
+         *  channel 0.
+         */
+        uint32_t outfifo_ro_cnt_chn:6;
+        /** out_ro_wr_state_chn : RO; bitpos: [7:6]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t out_ro_wr_state_chn:2;
+        /** out_ro_rd_state_chn : RO; bitpos: [9:8]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t out_ro_rd_state_chn:2;
+        /** out_pixel_byte_chn : RO; bitpos: [13:10]; default: 0;
+         *  the number of bytes contained in a pixel at TX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t out_pixel_byte_chn:4;
+        /** out_burst_block_num_chn : RO; bitpos: [17:14]; default: 0;
+         *  the number of macro blocks contained in a burst of data at TX channel
+         */
+        uint32_t out_burst_block_num_chn:4;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} dma2d_out_ro_status_chn_reg_t;
+
+/** Type of infifo_status_chn register
+ *  Represents the status of the rx fifo of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
+         *  Rx FIFO full signal for Rx channel.
+         */
+        uint32_t infifo_full_l2_chn:1;
+        /** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
+         *  Rx FIFO empty signal for Rx channel.
+         */
+        uint32_t infifo_empty_l2_chn:1;
+        /** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel.
+         */
+        uint32_t infifo_cnt_l2_chn:4;
+        uint32_t reserved_6:1;
+        /** in_remain_under_1b_chn : RO; bitpos: [7]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_1b_chn:1;
+        /** in_remain_under_2b_chn : RO; bitpos: [8]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_2b_chn:1;
+        /** in_remain_under_3b_chn : RO; bitpos: [9]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_3b_chn:1;
+        /** in_remain_under_4b_chn : RO; bitpos: [10]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_4b_chn:1;
+        /** in_remain_under_5b_chn : RO; bitpos: [11]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_5b_chn:1;
+        /** in_remain_under_6b_chn : RO; bitpos: [12]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_6b_chn:1;
+        /** in_remain_under_7b_chn : RO; bitpos: [13]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_7b_chn:1;
+        /** in_remain_under_8b_chn : RO; bitpos: [14]; default: 0;
+         *  reserved
+         */
+        uint32_t in_remain_under_8b_chn:1;
+        /** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l1_chn:1;
+        /** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l1_chn:1;
+        /** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l1_chn:5;
+        /** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
+         *  Rx FIFO full signal for Rx channel 0.
+         */
+        uint32_t infifo_full_l3_chn:1;
+        /** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
+         *  Rx FIFO empty signal for Rx channel 0.
+         */
+        uint32_t infifo_empty_l3_chn:1;
+        /** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
+         *  The register stores the byte number of the data in Rx FIFO for Rx channel 0.
+         */
+        uint32_t infifo_cnt_l3_chn:5;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} dma2d_infifo_status_chn_reg_t;
+
+/** Type of in_state_chn register
+ *  Represents the working status of the rx descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
+         *  This register stores the current inlink descriptor's address.
+         */
+        uint32_t inlink_dscr_addr_chn:18;
+        /** in_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
+         *  reserved
+         */
+        uint32_t in_dscr_state_chn:2;
+        /** in_state_chn : RO; bitpos: [22:20]; default: 0;
+         *  reserved
+         */
+        uint32_t in_state_chn:3;
+        /** in_reset_avail_chn : RO; bitpos: [23]; default: 1;
+         *  This register indicate that if the channel reset is safety.
+         */
+        uint32_t in_reset_avail_chn:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} dma2d_in_state_chn_reg_t;
+
+/** Type of in_suc_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_suc_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when the EOF bit in this
+         *  descriptor is 1.
+         */
+        uint32_t in_suc_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_suc_eof_des_addr_chn_reg_t;
+
+/** Type of in_err_eof_des_addr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** in_err_eof_des_addr_chn : RO; bitpos: [31:0]; default: 0;
+         *  This register stores the address of the inlink descriptor when there are some
+         *  errors in current receiving data.
+         */
+        uint32_t in_err_eof_des_addr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_err_eof_des_addr_chn_reg_t;
+
+/** Type of in_dscr_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the next inlink descriptor address x.
+         */
+        uint32_t inlink_dscr_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_chn_reg_t;
+
+/** Type of in_dscr_bf0_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the last inlink descriptor's next address x-1.
+         */
+        uint32_t inlink_dscr_bf0_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf0_chn_reg_t;
+
+/** Type of in_dscr_bf1_chn register
+ *  Represents the address associated with the inlink descriptor of channel n
+ */
+typedef union {
+    struct {
+        /** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
+         *  The address of the second-to-last inlink descriptor's next address x-2.
+         */
+        uint32_t inlink_dscr_bf1_chn:32;
+    };
+    uint32_t val;
+} dma2d_in_dscr_bf1_chn_reg_t;
+
+/** Type of in_ro_status_chn register
+ *  Represents the status of the rx reorder module of channel n
+ */
+typedef union {
+    struct {
+        /** infifo_ro_cnt_chn : RO; bitpos: [4:0]; default: 0;
+         *  The register stores the byte number of the data in color convert Rx FIFO for
+         *  channel 0.
+         */
+        uint32_t infifo_ro_cnt_chn:5;
+        /** in_ro_wr_state_chn : RO; bitpos: [6:5]; default: 0;
+         *  The register stores the state of read ram of reorder
+         */
+        uint32_t in_ro_wr_state_chn:2;
+        /** in_ro_rd_state_chn : RO; bitpos: [8:7]; default: 0;
+         *  The register stores the state of write ram of reorder
+         */
+        uint32_t in_ro_rd_state_chn:2;
+        /** in_pixel_byte_chn : RO; bitpos: [12:9]; default: 0;
+         *  the number of bytes contained in a pixel at RX channel     0: 1byte     1: 1.5bytes
+         *  2 : 2bytes     3: 2.5bytes     4: 3bytes     5: 4bytes
+         */
+        uint32_t in_pixel_byte_chn:4;
+        /** in_burst_block_num_chn : RO; bitpos: [16:13]; default: 0;
+         *  the number of macro blocks contained in a burst of data at RX channel
+         */
+        uint32_t in_burst_block_num_chn:4;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} dma2d_in_ro_status_chn_reg_t;
+
+/** Type of axi_err register
+ *  Represents the status of th axi bus
+ */
+typedef union {
+    struct {
+        /** rid_err_cnt : RO; bitpos: [3:0]; default: 0;
+         *  AXI read id err cnt
+         */
+        uint32_t rid_err_cnt:4;
+        /** rresp_err_cnt : RO; bitpos: [7:4]; default: 0;
+         *  AXI read resp err cnt
+         */
+        uint32_t rresp_err_cnt:4;
+        /** wresp_err_cnt : RO; bitpos: [11:8]; default: 0;
+         *  AXI write resp err cnt
+         */
+        uint32_t wresp_err_cnt:4;
+        /** rd_fifo_cnt : RO; bitpos: [14:12]; default: 0;
+         *  AXI read cmd fifo remain cmd count
+         */
+        uint32_t rd_fifo_cnt:3;
+        /** rd_bak_fifo_cnt : RO; bitpos: [18:15]; default: 0;
+         *  AXI read backup cmd fifo remain cmd count
+         */
+        uint32_t rd_bak_fifo_cnt:4;
+        /** wr_fifo_cnt : RO; bitpos: [21:19]; default: 0;
+         *  AXI write cmd fifo remain cmd count
+         */
+        uint32_t wr_fifo_cnt:3;
+        /** wr_bak_fifo_cnt : RO; bitpos: [25:22]; default: 0;
+         *  AXI write backup cmd fifo remain cmd count
+         */
+        uint32_t wr_bak_fifo_cnt:4;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} dma2d_axi_err_reg_t;
+
+/** Type of date register
+ *  register version.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 36725136;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} dma2d_date_reg_t;
+
+
+/** Group: Peripheral Select Registers */
+/** Type of out_peri_sel_chn register
+ *  Configures the tx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** out_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Tx channel   0:  jpeg     1:
+         *  display-1     2: display-2     3: display-3      7: no choose
+         */
+        uint32_t out_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_out_peri_sel_chn_reg_t;
+
+/** Type of in_peri_sel_chn register
+ *  Configures the rx peripheral of channel n
+ */
+typedef union {
+    struct {
+        /** in_peri_sel_chn : R/W; bitpos: [2:0]; default: 7;
+         *  This register is used to select peripheral for Rx channel   0:  jpeg     1:
+         *  display-1     2: display-2        7: no choose
+         */
+        uint32_t in_peri_sel_chn:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} dma2d_in_peri_sel_chn_reg_t;
+
+
+typedef struct {
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0;
+    volatile dma2d_out_push_chn_reg_t out_push_ch0;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0;
+    volatile dma2d_out_state_chn_reg_t out_state_ch0;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch0;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0;
+    volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0;
+    uint32_t reserved_070[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1;
+    volatile dma2d_out_push_chn_reg_t out_push_ch1;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1;
+    volatile dma2d_out_state_chn_reg_t out_state_ch1;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch1;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1;
+    uint32_t reserved_144;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1;
+    uint32_t reserved_170[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2;
+    volatile dma2d_out_push_chn_reg_t out_push_ch2;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2;
+    volatile dma2d_out_state_chn_reg_t out_state_ch2;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch2;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2;
+    uint32_t reserved_244;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2;
+    uint32_t reserved_270[36];
+    volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3;
+    volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3;
+    volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3;
+    volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3;
+    volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3;
+    volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3;
+    volatile dma2d_out_push_chn_reg_t out_push_ch3;
+    volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3;
+    volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3;
+    volatile dma2d_out_state_chn_reg_t out_state_ch3;
+    volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3;
+    volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3;
+    volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3;
+    volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3;
+    volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3;
+    volatile dma2d_out_arb_chn_reg_t out_arb_ch3;
+    volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3;
+    uint32_t reserved_344;
+    volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3;
+    volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3;
+    volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3;
+    volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3;
+    volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3;
+    volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3;
+    volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3;
+    volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3;
+    volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3;
+    volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3;
+    uint32_t reserved_370[100];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch0;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0;
+    volatile dma2d_in_state_chn_reg_t in_state_ch0;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch0;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0;
+    volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0;
+    volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0;
+    volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0;
+    volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0;
+    volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0;
+    volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0;
+    volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0;
+    volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0;
+    volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0;
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0;
+    uint32_t reserved_570[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch1;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1;
+    volatile dma2d_in_state_chn_reg_t in_state_ch1;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch1;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1;
+    uint32_t reserved_648[9];
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1;
+    uint32_t reserved_670[36];
+    volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2;
+    volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2;
+    volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2;
+    volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2;
+    volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2;
+    volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2;
+    volatile dma2d_in_pop_chn_reg_t in_pop_ch2;
+    volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2;
+    volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2;
+    volatile dma2d_in_state_chn_reg_t in_state_ch2;
+    volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
+    volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
+    volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2;
+    volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
+    volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
+    volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2;
+    volatile dma2d_in_arb_chn_reg_t in_arb_ch2;
+    volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2;
+    uint32_t reserved_748[9];
+    volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2;
+    uint32_t reserved_770[164];
+    volatile dma2d_axi_err_reg_t axi_err;
+    volatile dma2d_rst_conf_reg_t rst_conf;
+    volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
+    volatile dma2d_intr_mem_end_addr_reg_t intr_mem_end_addr;
+    volatile dma2d_extr_mem_start_addr_reg_t extr_mem_start_addr;
+    volatile dma2d_extr_mem_end_addr_reg_t extr_mem_end_addr;
+    volatile dma2d_out_arb_config_reg_t out_arb_config;
+    volatile dma2d_in_arb_config_reg_t in_arb_config;
+    volatile dma2d_rdn_result_reg_t rdn_result;
+    volatile dma2d_rdn_eco_high_reg_t rdn_eco_high;
+    volatile dma2d_rdn_eco_low_reg_t rdn_eco_low;
+    volatile dma2d_date_reg_t date;
+} dma2d_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ds_reg.h b/components/soc/esp32s31/register/soc/ds_reg.h
new file mode 100644
index 00000000000..afad4e81230
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ds_reg.h
@@ -0,0 +1,197 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** DS_Y_MEM register
+ *  memory that stores Y
+ */
+#define DS_Y_MEM (DR_REG_DS_BASE + 0x0)
+#define DS_Y_MEM_SIZE_BYTES 512
+
+/** DS_M_MEM register
+ *  memory that stores M
+ */
+#define DS_M_MEM (DR_REG_DS_BASE + 0x200)
+#define DS_M_MEM_SIZE_BYTES 512
+
+/** DS_RB_MEM register
+ *  memory that stores Rb
+ */
+#define DS_RB_MEM (DR_REG_DS_BASE + 0x400)
+#define DS_RB_MEM_SIZE_BYTES 512
+
+/** DS_BOX_MEM register
+ *  memory that stores BOX
+ */
+#define DS_BOX_MEM (DR_REG_DS_BASE + 0x600)
+#define DS_BOX_MEM_SIZE_BYTES 48
+
+/** DS_IV_MEM register
+ *  memory that stores IV
+ */
+#define DS_IV_MEM (DR_REG_DS_BASE + 0x630)
+#define DS_IV_MEM_SIZE_BYTES 16
+
+/** DS_X_MEM register
+ *  memory that stores X
+ */
+#define DS_X_MEM (DR_REG_DS_BASE + 0x800)
+#define DS_X_MEM_SIZE_BYTES 512
+
+/** DS_Z_MEM register
+ *  memory that stores Z
+ */
+#define DS_Z_MEM (DR_REG_DS_BASE + 0xa00)
+#define DS_Z_MEM_SIZE_BYTES 512
+
+/** DS_SET_START_REG register
+ *  Activates the DS module
+ */
+#define DS_SET_START_REG (DR_REG_DS_BASE + 0xe00)
+/** DS_SET_START : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to activate the DS peripheral.
+ *  0: Invalid
+ *  1: Activate the DS peripheral
+ */
+#define DS_SET_START    (BIT(0))
+#define DS_SET_START_M  (DS_SET_START_V << DS_SET_START_S)
+#define DS_SET_START_V  0x00000001U
+#define DS_SET_START_S  0
+
+/** DS_SET_CONTINUE_REG register
+ *  DS continue control register
+ */
+#define DS_SET_CONTINUE_REG (DR_REG_DS_BASE + 0xe04)
+/** DS_SET_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  set this bit to continue DS operation.
+ */
+#define DS_SET_CONTINUE    (BIT(0))
+#define DS_SET_CONTINUE_M  (DS_SET_CONTINUE_V << DS_SET_CONTINUE_S)
+#define DS_SET_CONTINUE_V  0x00000001U
+#define DS_SET_CONTINUE_S  0
+
+/** DS_SET_FINISH_REG register
+ *  Ends DS operation
+ */
+#define DS_SET_FINISH_REG (DR_REG_DS_BASE + 0xe08)
+/** DS_SET_FINISH : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to end DS operation.
+ *  0: Invalid
+ *  1: End DS operation
+ */
+#define DS_SET_FINISH    (BIT(0))
+#define DS_SET_FINISH_M  (DS_SET_FINISH_V << DS_SET_FINISH_S)
+#define DS_SET_FINISH_V  0x00000001U
+#define DS_SET_FINISH_S  0
+
+/** DS_QUERY_BUSY_REG register
+ *  Status of the DS module
+ */
+#define DS_QUERY_BUSY_REG (DR_REG_DS_BASE + 0xe0c)
+/** DS_QUERY_BUSY : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the DS module is idle.
+ *  0: The DS module is idle
+ *  1: The DS module is busy
+ */
+#define DS_QUERY_BUSY    (BIT(0))
+#define DS_QUERY_BUSY_M  (DS_QUERY_BUSY_V << DS_QUERY_BUSY_S)
+#define DS_QUERY_BUSY_V  0x00000001U
+#define DS_QUERY_BUSY_S  0
+
+/** DS_QUERY_KEY_WRONG_REG register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+#define DS_QUERY_KEY_WRONG_REG (DR_REG_DS_BASE + 0xe10)
+/** DS_QUERY_KEY_WRONG : RO; bitpos: [3:0]; default: 0;
+ *  Represents the specific problem with HMAC initialization.
+ *  0: HMAC is not called
+ *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+ *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+ */
+#define DS_QUERY_KEY_WRONG    0x0000000FU
+#define DS_QUERY_KEY_WRONG_M  (DS_QUERY_KEY_WRONG_V << DS_QUERY_KEY_WRONG_S)
+#define DS_QUERY_KEY_WRONG_V  0x0000000FU
+#define DS_QUERY_KEY_WRONG_S  0
+
+/** DS_QUERY_CHECK_REG register
+ *  Queries DS check result
+ */
+#define DS_QUERY_CHECK_REG (DR_REG_DS_BASE + 0xe14)
+/** DS_MD_ERROR : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not the MD check passes.
+ *  0: The MD check passes
+ *  1: The MD check fails
+ */
+#define DS_MD_ERROR    (BIT(0))
+#define DS_MD_ERROR_M  (DS_MD_ERROR_V << DS_MD_ERROR_S)
+#define DS_MD_ERROR_V  0x00000001U
+#define DS_MD_ERROR_S  0
+/** DS_PADDING_BAD : RO; bitpos: [1]; default: 0;
+ *  Represents whether or not the padding check passes.
+ *  0: The padding check passes
+ *  1: The padding check fails
+ */
+#define DS_PADDING_BAD    (BIT(1))
+#define DS_PADDING_BAD_M  (DS_PADDING_BAD_V << DS_PADDING_BAD_S)
+#define DS_PADDING_BAD_V  0x00000001U
+#define DS_PADDING_BAD_S  1
+
+/** DS_STATIC_REG register
+ *  DS configure key source register
+ */
+#define DS_STATIC_REG (DR_REG_DS_BASE + 0xe18)
+/** DS_KEY_SOURCE : R/W; bitpos: [0]; default: 0;
+ *  digital signature key source bit.
+ *  1'b0: key is from hmac.
+ *  1'b1: key is from key manager.
+ */
+#define DS_KEY_SOURCE    (BIT(0))
+#define DS_KEY_SOURCE_M  (DS_KEY_SOURCE_V << DS_KEY_SOURCE_S)
+#define DS_KEY_SOURCE_V  0x00000001U
+#define DS_KEY_SOURCE_S  0
+/** DS_SKIP_PADDING_CHECK : R/W; bitpos: [1]; default: 0;
+ *  digital signature padding check bypass bit.
+ *  1'b0: padding check enabled.
+ *  1'b1: padding check skipped.
+ */
+#define DS_SKIP_PADDING_CHECK    (BIT(1))
+#define DS_SKIP_PADDING_CHECK_M  (DS_SKIP_PADDING_CHECK_V << DS_SKIP_PADDING_CHECK_S)
+#define DS_SKIP_PADDING_CHECK_V  0x00000001U
+#define DS_SKIP_PADDING_CHECK_S  1
+
+/** DS_DATE_REG register
+ *  DS version control register
+ */
+#define DS_DATE_REG (DR_REG_DS_BASE + 0xe20)
+/** DS_DATE : R/W; bitpos: [29:0]; default: 539297817;
+ *  ds version information
+ */
+#define DS_DATE    0x3FFFFFFFU
+#define DS_DATE_M  (DS_DATE_V << DS_DATE_S)
+#define DS_DATE_V  0x3FFFFFFFU
+#define DS_DATE_S  0
+
+/** DS_TIMEOUT_LIMIT_REG register
+ *  DS timeout limit configure register
+ */
+#define DS_TIMEOUT_LIMIT_REG (DR_REG_DS_BASE + 0xe24)
+/** DS_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The timeout limitation for waiting sub-IP.
+ */
+#define DS_TIMEOUT_LIMIT    0xFFFFFFFFU
+#define DS_TIMEOUT_LIMIT_M  (DS_TIMEOUT_LIMIT_V << DS_TIMEOUT_LIMIT_S)
+#define DS_TIMEOUT_LIMIT_V  0xFFFFFFFFU
+#define DS_TIMEOUT_LIMIT_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ds_struct.h b/components/soc/esp32s31/register/soc/ds_struct.h
new file mode 100644
index 00000000000..99fa5e07fcb
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ds_struct.h
@@ -0,0 +1,200 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: memory type */
+
+/** Group: Control/Status registers */
+/** Type of set_start register
+ *  Activates the DS module
+ */
+typedef union {
+    struct {
+        /** set_start : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to activate the DS peripheral.
+         *  0: Invalid
+         *  1: Activate the DS peripheral
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_start_reg_t;
+
+/** Type of set_continue register
+ *  DS continue control register
+ */
+typedef union {
+    struct {
+        /** set_continue : WT; bitpos: [0]; default: 0;
+         *  set this bit to continue DS operation.
+         */
+        uint32_t set_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_continue_reg_t;
+
+/** Type of set_finish register
+ *  Ends DS operation
+ */
+typedef union {
+    struct {
+        /** set_finish : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to end DS operation.
+         *  0: Invalid
+         *  1: End DS operation
+         */
+        uint32_t set_finish:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_set_finish_reg_t;
+
+/** Type of query_busy register
+ *  Status of the DS module
+ */
+typedef union {
+    struct {
+        /** query_busy : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the DS module is idle.
+         *  0: The DS module is idle
+         *  1: The DS module is busy
+         */
+        uint32_t query_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ds_query_busy_reg_t;
+
+/** Type of query_key_wrong register
+ *  Checks the reason why \begin{math}DS_KEY\end{math} is not ready
+ */
+typedef union {
+    struct {
+        /** query_key_wrong : RO; bitpos: [3:0]; default: 0;
+         *  Represents the specific problem with HMAC initialization.
+         *  0: HMAC is not called
+         *  1-15: HMAC was activated, but the DS peripheral did not successfully receive the
+         *  \begin{math}DS_KEY\end{math} from the HMAC peripheral. (The biggest value is 15)
+         */
+        uint32_t query_key_wrong:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ds_query_key_wrong_reg_t;
+
+/** Type of query_check register
+ *  Queries DS check result
+ */
+typedef union {
+    struct {
+        /** md_error : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not the MD check passes.
+         *  0: The MD check passes
+         *  1: The MD check fails
+         */
+        uint32_t md_error:1;
+        /** padding_bad : RO; bitpos: [1]; default: 0;
+         *  Represents whether or not the padding check passes.
+         *  0: The padding check passes
+         *  1: The padding check fails
+         */
+        uint32_t padding_bad:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ds_query_check_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of static register
+ *  DS configure key source register
+ */
+typedef union {
+    struct {
+        /** key_source : R/W; bitpos: [0]; default: 0;
+         *  digital signature key source bit.
+         *  1'b0: key is from hmac.
+         *  1'b1: key is from key manager.
+         */
+        uint32_t key_source:1;
+        /** skip_padding_check : R/W; bitpos: [1]; default: 0;
+         *  digital signature padding check bypass bit.
+         *  1'b0: padding check enabled.
+         *  1'b1: padding check skipped.
+         */
+        uint32_t skip_padding_check:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ds_static_reg_t;
+
+/** Type of timeout_limit register
+ *  DS timeout limit configure register
+ */
+typedef union {
+    struct {
+        /** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The timeout limitation for waiting sub-IP.
+         */
+        uint32_t timeout_limit:32;
+    };
+    uint32_t val;
+} ds_timeout_limit_reg_t;
+
+
+/** Group: version control register */
+/** Type of date register
+ *  DS version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539297817;
+         *  ds version information
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} ds_date_reg_t;
+
+
+typedef struct {
+    volatile uint32_t y[128];
+    volatile uint32_t m[128];
+    volatile uint32_t rb[128];
+    volatile uint32_t box[12];
+    volatile uint32_t iv[4];
+    uint32_t reserved_640[112];
+    volatile uint32_t x[128];
+    volatile uint32_t z[128];
+    uint32_t reserved_c00[128];
+    volatile ds_set_start_reg_t set_start;
+    volatile ds_set_continue_reg_t set_continue;
+    volatile ds_set_finish_reg_t set_finish;
+    volatile ds_query_busy_reg_t query_busy;
+    volatile ds_query_key_wrong_reg_t query_key_wrong;
+    volatile ds_query_check_reg_t query_check;
+    volatile ds_static_reg_t static;
+    uint32_t reserved_e1c;
+    volatile ds_date_reg_t date;
+    volatile ds_timeout_limit_reg_t timeout_limit;
+} ds_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ds_dev_t) == 0xe28, "Invalid size of ds_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ecc_mult_reg.h b/components/soc/esp32s31/register/soc/ecc_mult_reg.h
new file mode 100644
index 00000000000..9a54c5b1ed5
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ecc_mult_reg.h
@@ -0,0 +1,224 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  ECC raw interrupt status register
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  ECC masked interrupt status register
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  ECC interrupt enable register
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  ECC interrupt clear register
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  ECC configuration register
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to start calculation of ECC Accelerator. This bit will be
+ *  self-cleared after the calculation is done.
+ *  0: No effect
+ *  1: Start calculation of ECC Accelerator
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Configures whether to reset ECC Accelerator.
+ *  0: No effect
+ *  1: Reset
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
+ *  Configures the key length mode bit of ECC Accelerator.
+ *  0: P-192
+ *  1: P-256
+ *  2: P-384
+ *  3: SM2.
+ */
+#define ECC_MULT_KEY_LENGTH    0x00000003U
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000003U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
+ *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+ *  0: n(order of curve)
+ *  1: p(mod base of curve)
+ */
+#define ECC_MULT_MOD_BASE    (BIT(4))
+#define ECC_MULT_MOD_BASE_M  (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
+#define ECC_MULT_MOD_BASE_V  0x00000001U
+#define ECC_MULT_MOD_BASE_S  4
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
+ *  Configures the work mode of ECC Accelerator.
+ *  0: Point Multi mode
+ *  1: Reserved
+ *  2: Point Verif mode
+ *  3: Point Verif + Multi mode
+ *  4: Jacobian Point Multi mode
+ *  5: Reserved
+ *  6: Jacobian Point Verif mode
+ *  7: Point Verif + Jacobian Point Multi mode
+ *  8: Mod Add mode
+ *  9. Mod Sub mode
+ *  10: Mod Multi mode
+ *  11: Mod Div mode
+ */
+#define ECC_MULT_WORK_MODE    0x0000000FU
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x0000000FU
+#define ECC_MULT_WORK_MODE_S  5
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
+ *  Configures the security mode of ECC Accelerator.
+ *  0: no secure function enabled.
+ *  1: enable constant-time calculation in all point multiplication modes.
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(9))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  9
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
+ *  Represents the verification result of ECC Accelerator, valid only when calculation
+ *  is done.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(29))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  29
+/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Configures whether to force on register clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_CLK_EN    (BIT(30))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  30
+/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
+ *  Configures whether to force on ECC memory clock gate.
+ *  0: No effect
+ *  1: Force on
+ */
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON    (BIT(31))
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M  (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V  0x00000001U
+#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S  31
+
+/** ECC_MULT_FREE_REG register
+ *  ECC free status register
+ */
+#define ECC_MULT_FREE_REG (DR_REG_ECC_MULT_BASE + 0x20)
+/** ECC_MULT_FREE : R/W; bitpos: [0]; default: 1;
+ *  ECC mult free state register
+ *  0: non-free
+ *  1: free
+ */
+#define ECC_MULT_FREE    (BIT(0))
+#define ECC_MULT_FREE_M  (ECC_MULT_FREE_V << ECC_MULT_FREE_S)
+#define ECC_MULT_FREE_V  0x00000001U
+#define ECC_MULT_FREE_S  0
+
+/** ECC_MULT_DATE_REG register
+ *  Version control register
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 38822288;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+/** ECC_MULT_K_MEM register
+ *  The memory that stores k.
+ */
+#define ECC_MULT_K_MEM (DR_REG_ECC_MULT_BASE + 0x100)
+#define ECC_MULT_K_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PX_MEM register
+ *  The memory that stores Px.
+ */
+#define ECC_MULT_PX_MEM (DR_REG_ECC_MULT_BASE + 0x130)
+#define ECC_MULT_PX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_PY_MEM register
+ *  The memory that stores Py.
+ */
+#define ECC_MULT_PY_MEM (DR_REG_ECC_MULT_BASE + 0x160)
+#define ECC_MULT_PY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QX_MEM register
+ *  The memory that stores Qx.
+ */
+#define ECC_MULT_QX_MEM (DR_REG_ECC_MULT_BASE + 0x190)
+#define ECC_MULT_QX_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QY_MEM register
+ *  The memory that stores Qy.
+ */
+#define ECC_MULT_QY_MEM (DR_REG_ECC_MULT_BASE + 0x1c0)
+#define ECC_MULT_QY_MEM_SIZE_BYTES 48
+
+/** ECC_MULT_QZ_MEM register
+ *  The memory that stores Qz.
+ */
+#define ECC_MULT_QZ_MEM (DR_REG_ECC_MULT_BASE + 0x1f0)
+#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ecc_mult_struct.h b/components/soc/esp32s31/register/soc/ecc_mult_struct.h
new file mode 100644
index 00000000000..0eba88be5c8
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ecc_mult_struct.h
@@ -0,0 +1,210 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECC raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECC masked interrupt status register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECC interrupt enable register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECC interrupt clear register
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear the ECC_CALC_DONE_INT interrupt.
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  ECC configuration register
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to start calculation of ECC Accelerator. This bit will be
+         *  self-cleared after the calculation is done.
+         *  0: No effect
+         *  1: Start calculation of ECC Accelerator
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Configures whether to reset ECC Accelerator.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [3:2]; default: 0;
+         *  Configures the key length mode bit of ECC Accelerator.
+         *  0: P-192
+         *  1: P-256
+         *  2: P-384
+         *  3: SM2.
+         */
+        uint32_t key_length:2;
+        /** mod_base : R/W; bitpos: [4]; default: 0;
+         *  Configures the mod base of mod operation, only valid in work_mode 8-11.
+         *  0: n(order of curve)
+         *  1: p(mod base of curve)
+         */
+        uint32_t mod_base:1;
+        /** work_mode : R/W; bitpos: [8:5]; default: 0;
+         *  Configures the work mode of ECC Accelerator.
+         *  0: Point Multi mode
+         *  1: Reserved
+         *  2: Point Verif mode
+         *  3: Point Verif + Multi mode
+         *  4: Jacobian Point Multi mode
+         *  5: Reserved
+         *  6: Jacobian Point Verif mode
+         *  7: Point Verif + Jacobian Point Multi mode
+         *  8: Mod Add mode
+         *  9. Mod Sub mode
+         *  10: Mod Multi mode
+         *  11: Mod Div mode
+         */
+        uint32_t work_mode:4;
+        /** security_mode : R/W; bitpos: [9]; default: 0;
+         *  Configures the security mode of ECC Accelerator.
+         *  0: no secure function enabled.
+         *  1: enable constant-time calculation in all point multiplication modes.
+         */
+        uint32_t security_mode:1;
+        uint32_t reserved_10:19;
+        /** verification_result : RO/SS; bitpos: [29]; default: 0;
+         *  Represents the verification result of ECC Accelerator, valid only when calculation
+         *  is done.
+         */
+        uint32_t verification_result:1;
+        /** clk_en : R/W; bitpos: [30]; default: 0;
+         *  Configures whether to force on register clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t clk_en:1;
+        /** mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
+         *  Configures whether to force on ECC memory clock gate.
+         *  0: No effect
+         *  1: Force on
+         */
+        uint32_t mem_clock_gate_force_on:1;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of free register
+ *  ECC free status register
+ */
+typedef union {
+    struct {
+        /** free : R/W; bitpos: [0]; default: 1;
+         *  ECC mult free state register
+         *  0: non-free
+         *  1: free
+         */
+        uint32_t free:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_free_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38822288;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    volatile ecc_mult_free_reg_t free;
+    uint32_t reserved_024[54];
+    volatile ecc_mult_date_reg_t date;
+    volatile uint32_t k[12];
+    volatile uint32_t px[12];
+    volatile uint32_t py[12];
+    volatile uint32_t qx[12];
+    volatile uint32_t qy[12];
+    volatile uint32_t qz[12];
+} ecc_mult_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x220, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ecdsa_reg.h b/components/soc/esp32s31/register/soc/ecdsa_reg.h
new file mode 100644
index 00000000000..775134760f7
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ecdsa_reg.h
@@ -0,0 +1,539 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECDSA_CONF_REG register
+ *  ECDSA configure register
+ */
+#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
+/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+ *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+ */
+#define ECDSA_WORK_MODE    0x00000003U
+#define ECDSA_WORK_MODE_M  (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
+#define ECDSA_WORK_MODE_V  0x00000003U
+#define ECDSA_WORK_MODE_S  0
+/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
+ *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384 3: SM2.
+ */
+#define ECDSA_ECC_CURVE    0x00000003U
+#define ECDSA_ECC_CURVE_M  (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
+#define ECDSA_ECC_CURVE_V  0x00000003U
+#define ECDSA_ECC_CURVE_S  2
+/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
+ *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+ *  written by software.
+ */
+#define ECDSA_SOFTWARE_SET_K    (BIT(4))
+#define ECDSA_SOFTWARE_SET_K_M  (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
+#define ECDSA_SOFTWARE_SET_K_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_K_S  4
+/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
+ *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+ *  software.
+ */
+#define ECDSA_SOFTWARE_SET_Z    (BIT(5))
+#define ECDSA_SOFTWARE_SET_Z_M  (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
+#define ECDSA_SOFTWARE_SET_Z_V  0x00000001U
+#define ECDSA_SOFTWARE_SET_Z_S  5
+/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
+ *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+ *  deterministic derivation algorithm.
+ */
+#define ECDSA_DETERMINISTIC_K    (BIT(6))
+#define ECDSA_DETERMINISTIC_K_M  (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
+#define ECDSA_DETERMINISTIC_K_V  0x00000001U
+#define ECDSA_DETERMINISTIC_K_S  6
+/** ECDSA_USE_HARDWARE_KEY : R/W; bitpos: [7]; default: 0;
+ *  Configures the ECDSA use software key or hardware key.
+ *  0: Software key.
+ *  1: Hardware key.
+ */
+#define ECDSA_USE_HARDWARE_KEY    (BIT(7))
+#define ECDSA_USE_HARDWARE_KEY_M  (ECDSA_USE_HARDWARE_KEY_V << ECDSA_USE_HARDWARE_KEY_S)
+#define ECDSA_USE_HARDWARE_KEY_V  0x00000001U
+#define ECDSA_USE_HARDWARE_KEY_S  7
+
+/** ECDSA_CLK_REG register
+ *  ECDSA clock gate register
+ */
+#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
+/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to force on register clock gate.
+ */
+#define ECDSA_CLK_GATE_FORCE_ON    (BIT(0))
+#define ECDSA_CLK_GATE_FORCE_ON_M  (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
+#define ECDSA_CLK_GATE_FORCE_ON_V  0x00000001U
+#define ECDSA_CLK_GATE_FORCE_ON_S  0
+
+/** ECDSA_INT_RAW_REG register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
+/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_RAW    (BIT(0))
+#define ECDSA_PREP_DONE_INT_RAW_M  (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
+#define ECDSA_PREP_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_RAW_S  0
+/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_RAW    (BIT(1))
+#define ECDSA_PROC_DONE_INT_RAW_M  (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
+#define ECDSA_PROC_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_RAW_S  1
+/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_RAW    (BIT(2))
+#define ECDSA_POST_DONE_INT_RAW_M  (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
+#define ECDSA_POST_DONE_INT_RAW_V  0x00000001U
+#define ECDSA_POST_DONE_INT_RAW_S  2
+/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_RAW    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_RAW_M  (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
+#define ECDSA_SHA_RELEASE_INT_RAW_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_RAW_S  3
+
+/** ECDSA_INT_ST_REG register
+ *  ECDSA interrupt status register.
+ */
+#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
+/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ST    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ST_M  (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
+#define ECDSA_PREP_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ST_S  0
+/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ST    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ST_M  (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
+#define ECDSA_PROC_DONE_INT_ST_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ST_S  1
+/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ST    (BIT(2))
+#define ECDSA_POST_DONE_INT_ST_M  (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
+#define ECDSA_POST_DONE_INT_ST_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ST_S  2
+/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ST    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ST_M  (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
+#define ECDSA_SHA_RELEASE_INT_ST_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ST_S  3
+
+/** ECDSA_INT_ENA_REG register
+ *  ECDSA interrupt enable register.
+ */
+#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
+/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_ENA    (BIT(0))
+#define ECDSA_PREP_DONE_INT_ENA_M  (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
+#define ECDSA_PREP_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_ENA_S  0
+/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_ENA    (BIT(1))
+#define ECDSA_PROC_DONE_INT_ENA_M  (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
+#define ECDSA_PROC_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_ENA_S  1
+/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_ENA    (BIT(2))
+#define ECDSA_POST_DONE_INT_ENA_M  (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
+#define ECDSA_POST_DONE_INT_ENA_V  0x00000001U
+#define ECDSA_POST_DONE_INT_ENA_S  2
+/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_ENA    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_ENA_M  (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
+#define ECDSA_SHA_RELEASE_INT_ENA_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_ENA_S  3
+
+/** ECDSA_INT_CLR_REG register
+ *  ECDSA interrupt clear register.
+ */
+#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
+/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the ecdsa_prep_done_int interrupt
+ */
+#define ECDSA_PREP_DONE_INT_CLR    (BIT(0))
+#define ECDSA_PREP_DONE_INT_CLR_M  (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
+#define ECDSA_PREP_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PREP_DONE_INT_CLR_S  0
+/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the ecdsa_proc_done_int interrupt
+ */
+#define ECDSA_PROC_DONE_INT_CLR    (BIT(1))
+#define ECDSA_PROC_DONE_INT_CLR_M  (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
+#define ECDSA_PROC_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_PROC_DONE_INT_CLR_S  1
+/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the ecdsa_post_done_int interrupt
+ */
+#define ECDSA_POST_DONE_INT_CLR    (BIT(2))
+#define ECDSA_POST_DONE_INT_CLR_M  (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
+#define ECDSA_POST_DONE_INT_CLR_V  0x00000001U
+#define ECDSA_POST_DONE_INT_CLR_S  2
+/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the ecdsa_sha_release_int interrupt
+ */
+#define ECDSA_SHA_RELEASE_INT_CLR    (BIT(3))
+#define ECDSA_SHA_RELEASE_INT_CLR_M  (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
+#define ECDSA_SHA_RELEASE_INT_CLR_V  0x00000001U
+#define ECDSA_SHA_RELEASE_INT_CLR_S  3
+
+/** ECDSA_START_REG register
+ *  ECDSA start register
+ */
+#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
+/** ECDSA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+ *  after configuration.
+ */
+#define ECDSA_START    (BIT(0))
+#define ECDSA_START_M  (ECDSA_START_V << ECDSA_START_S)
+#define ECDSA_START_V  0x00000001U
+#define ECDSA_START_S  0
+/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_LOAD_DONE    (BIT(1))
+#define ECDSA_LOAD_DONE_M  (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
+#define ECDSA_LOAD_DONE_V  0x00000001U
+#define ECDSA_LOAD_DONE_S  1
+/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
+ *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+ *  self-cleared after configuration.
+ */
+#define ECDSA_GET_DONE    (BIT(2))
+#define ECDSA_GET_DONE_M  (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
+#define ECDSA_GET_DONE_V  0x00000001U
+#define ECDSA_GET_DONE_S  2
+
+/** ECDSA_STATE_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
+/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
+ *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+ *  state.
+ */
+#define ECDSA_BUSY    0x00000003U
+#define ECDSA_BUSY_M  (ECDSA_BUSY_V << ECDSA_BUSY_S)
+#define ECDSA_BUSY_V  0x00000003U
+#define ECDSA_BUSY_S  0
+
+/** ECDSA_RESULT_REG register
+ *  ECDSA result register
+ */
+#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
+/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
+ *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+ *  done.
+ */
+#define ECDSA_OPERATION_RESULT    (BIT(0))
+#define ECDSA_OPERATION_RESULT_M  (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
+#define ECDSA_OPERATION_RESULT_V  0x00000001U
+#define ECDSA_OPERATION_RESULT_S  0
+
+/** ECDSA_TIMEOUT_LIMIT_REG register
+ *  ECDSA timeout limit configure register
+ */
+#define ECDSA_TIMEOUT_LIMIT_REG (DR_REG_ECDSA_BASE + 0x28)
+/** ECDSA_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The timeout limitation for waiting sub-IP.
+ */
+#define ECDSA_TIMEOUT_LIMIT    0xFFFFFFFFU
+#define ECDSA_TIMEOUT_LIMIT_M  (ECDSA_TIMEOUT_LIMIT_V << ECDSA_TIMEOUT_LIMIT_S)
+#define ECDSA_TIMEOUT_LIMIT_V  0xFFFFFFFFU
+#define ECDSA_TIMEOUT_LIMIT_S  0
+
+/** ECDSA_FREE_REG register
+ *  ECDSA free state
+ */
+#define ECDSA_FREE_REG (DR_REG_ECDSA_BASE + 0x2c)
+/** ECDSA_FREE : R/W; bitpos: [0]; default: 1;
+ *  Represents if ECDSA Accelerator is free or not.
+ *  0: non-free
+ *  1: free
+ */
+#define ECDSA_FREE    (BIT(0))
+#define ECDSA_FREE_M  (ECDSA_FREE_V << ECDSA_FREE_S)
+#define ECDSA_FREE_V  0x00000001U
+#define ECDSA_FREE_S  0
+
+/** ECDSA_KEY_0_REG register
+ *  ECDSA key data register 0
+ */
+#define ECDSA_KEY_0_REG (DR_REG_ECDSA_BASE + 0x40)
+/** ECDSA_KEY_0 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_0 that is a part of key material.
+ */
+#define ECDSA_KEY_0    0xFFFFFFFFU
+#define ECDSA_KEY_0_M  (ECDSA_KEY_0_V << ECDSA_KEY_0_S)
+#define ECDSA_KEY_0_V  0xFFFFFFFFU
+#define ECDSA_KEY_0_S  0
+
+/** ECDSA_KEY_1_REG register
+ *  ECDSA key data register 1
+ */
+#define ECDSA_KEY_1_REG (DR_REG_ECDSA_BASE + 0x44)
+/** ECDSA_KEY_1 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_1 that is a part of key material.
+ */
+#define ECDSA_KEY_1    0xFFFFFFFFU
+#define ECDSA_KEY_1_M  (ECDSA_KEY_1_V << ECDSA_KEY_1_S)
+#define ECDSA_KEY_1_V  0xFFFFFFFFU
+#define ECDSA_KEY_1_S  0
+
+/** ECDSA_KEY_2_REG register
+ *  ECDSA key data register 2
+ */
+#define ECDSA_KEY_2_REG (DR_REG_ECDSA_BASE + 0x48)
+/** ECDSA_KEY_2 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_2 that is a part of key material.
+ */
+#define ECDSA_KEY_2    0xFFFFFFFFU
+#define ECDSA_KEY_2_M  (ECDSA_KEY_2_V << ECDSA_KEY_2_S)
+#define ECDSA_KEY_2_V  0xFFFFFFFFU
+#define ECDSA_KEY_2_S  0
+
+/** ECDSA_KEY_3_REG register
+ *  ECDSA key data register 3
+ */
+#define ECDSA_KEY_3_REG (DR_REG_ECDSA_BASE + 0x4c)
+/** ECDSA_KEY_3 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_3 that is a part of key material.
+ */
+#define ECDSA_KEY_3    0xFFFFFFFFU
+#define ECDSA_KEY_3_M  (ECDSA_KEY_3_V << ECDSA_KEY_3_S)
+#define ECDSA_KEY_3_V  0xFFFFFFFFU
+#define ECDSA_KEY_3_S  0
+
+/** ECDSA_KEY_4_REG register
+ *  ECDSA key data register 4
+ */
+#define ECDSA_KEY_4_REG (DR_REG_ECDSA_BASE + 0x50)
+/** ECDSA_KEY_4 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_4 that is a part of key material.
+ */
+#define ECDSA_KEY_4    0xFFFFFFFFU
+#define ECDSA_KEY_4_M  (ECDSA_KEY_4_V << ECDSA_KEY_4_S)
+#define ECDSA_KEY_4_V  0xFFFFFFFFU
+#define ECDSA_KEY_4_S  0
+
+/** ECDSA_KEY_5_REG register
+ *  ECDSA key data register 5
+ */
+#define ECDSA_KEY_5_REG (DR_REG_ECDSA_BASE + 0x54)
+/** ECDSA_KEY_5 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_5 that is a part of key material.
+ */
+#define ECDSA_KEY_5    0xFFFFFFFFU
+#define ECDSA_KEY_5_M  (ECDSA_KEY_5_V << ECDSA_KEY_5_S)
+#define ECDSA_KEY_5_V  0xFFFFFFFFU
+#define ECDSA_KEY_5_S  0
+
+/** ECDSA_KEY_6_REG register
+ *  ECDSA key data register 6
+ */
+#define ECDSA_KEY_6_REG (DR_REG_ECDSA_BASE + 0x58)
+/** ECDSA_KEY_6 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_6 that is a part of key material.
+ */
+#define ECDSA_KEY_6    0xFFFFFFFFU
+#define ECDSA_KEY_6_M  (ECDSA_KEY_6_V << ECDSA_KEY_6_S)
+#define ECDSA_KEY_6_V  0xFFFFFFFFU
+#define ECDSA_KEY_6_S  0
+
+/** ECDSA_KEY_7_REG register
+ *  ECDSA key data register 7
+ */
+#define ECDSA_KEY_7_REG (DR_REG_ECDSA_BASE + 0x5c)
+/** ECDSA_KEY_7 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_7 that is a part of key material.
+ */
+#define ECDSA_KEY_7    0xFFFFFFFFU
+#define ECDSA_KEY_7_M  (ECDSA_KEY_7_V << ECDSA_KEY_7_S)
+#define ECDSA_KEY_7_V  0xFFFFFFFFU
+#define ECDSA_KEY_7_S  0
+
+/** ECDSA_KEY_8_REG register
+ *  ECDSA key data register 8
+ */
+#define ECDSA_KEY_8_REG (DR_REG_ECDSA_BASE + 0x60)
+/** ECDSA_KEY_8 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_8 that is a part of key material.
+ */
+#define ECDSA_KEY_8    0xFFFFFFFFU
+#define ECDSA_KEY_8_M  (ECDSA_KEY_8_V << ECDSA_KEY_8_S)
+#define ECDSA_KEY_8_V  0xFFFFFFFFU
+#define ECDSA_KEY_8_S  0
+
+/** ECDSA_KEY_9_REG register
+ *  ECDSA key data register 9
+ */
+#define ECDSA_KEY_9_REG (DR_REG_ECDSA_BASE + 0x64)
+/** ECDSA_KEY_9 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_9 that is a part of key material.
+ */
+#define ECDSA_KEY_9    0xFFFFFFFFU
+#define ECDSA_KEY_9_M  (ECDSA_KEY_9_V << ECDSA_KEY_9_S)
+#define ECDSA_KEY_9_V  0xFFFFFFFFU
+#define ECDSA_KEY_9_S  0
+
+/** ECDSA_KEY_10_REG register
+ *  ECDSA key data register 10
+ */
+#define ECDSA_KEY_10_REG (DR_REG_ECDSA_BASE + 0x68)
+/** ECDSA_KEY_10 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_10 that is a part of key material.
+ */
+#define ECDSA_KEY_10    0xFFFFFFFFU
+#define ECDSA_KEY_10_M  (ECDSA_KEY_10_V << ECDSA_KEY_10_S)
+#define ECDSA_KEY_10_V  0xFFFFFFFFU
+#define ECDSA_KEY_10_S  0
+
+/** ECDSA_KEY_11_REG register
+ *  ECDSA key data register 11
+ */
+#define ECDSA_KEY_11_REG (DR_REG_ECDSA_BASE + 0x6c)
+/** ECDSA_KEY_11 : R/W; bitpos: [31:0]; default: 0;
+ *  These bits stores key_11 that is a part of key material.
+ */
+#define ECDSA_KEY_11    0xFFFFFFFFU
+#define ECDSA_KEY_11_M  (ECDSA_KEY_11_V << ECDSA_KEY_11_S)
+#define ECDSA_KEY_11_V  0xFFFFFFFFU
+#define ECDSA_KEY_11_S  0
+
+/** ECDSA_DATE_REG register
+ *  Version control register
+ */
+#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
+/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 38830480;
+ *  ECDSA version control register
+ */
+#define ECDSA_DATE    0x0FFFFFFFU
+#define ECDSA_DATE_M  (ECDSA_DATE_V << ECDSA_DATE_S)
+#define ECDSA_DATE_V  0x0FFFFFFFU
+#define ECDSA_DATE_S  0
+
+/** ECDSA_SHA_MODE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
+/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0;
+ *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+ *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
+ *  invalid.
+ */
+#define ECDSA_SHA_MODE    0x0000000FU
+#define ECDSA_SHA_MODE_M  (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
+#define ECDSA_SHA_MODE_V  0x0000000FU
+#define ECDSA_SHA_MODE_S  0
+
+/** ECDSA_SHA_START_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
+/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_START    (BIT(0))
+#define ECDSA_SHA_START_M  (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
+#define ECDSA_SHA_START_V  0x00000001U
+#define ECDSA_SHA_START_S  0
+
+/** ECDSA_SHA_CONTINUE_REG register
+ *  ECDSA control SHA register
+ */
+#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
+/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+ *  bit will be self-cleared after configuration.
+ */
+#define ECDSA_SHA_CONTINUE    (BIT(0))
+#define ECDSA_SHA_CONTINUE_M  (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
+#define ECDSA_SHA_CONTINUE_V  0x00000001U
+#define ECDSA_SHA_CONTINUE_S  0
+
+/** ECDSA_SHA_BUSY_REG register
+ *  ECDSA status register
+ */
+#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
+/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
+ *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+ *  calculation. 0: SHA is idle.
+ */
+#define ECDSA_SHA_BUSY    (BIT(0))
+#define ECDSA_SHA_BUSY_M  (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
+#define ECDSA_SHA_BUSY_V  0x00000001U
+#define ECDSA_SHA_BUSY_S  0
+
+/** ECDSA_MESSAGE_MEM register
+ *  The memory that stores message.
+ */
+#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
+#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
+
+/** ECDSA_R_MEM register
+ *  The memory that stores r.
+ */
+#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
+#define ECDSA_R_MEM_SIZE_BYTES 48
+
+/** ECDSA_S_MEM register
+ *  The memory that stores s.
+ */
+#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
+#define ECDSA_S_MEM_SIZE_BYTES 48
+
+/** ECDSA_Z_MEM register
+ *  The memory that stores software written z.
+ */
+#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
+#define ECDSA_Z_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAX_MEM register
+ *  The memory that stores x coordinates of QA or software written k.
+ */
+#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
+#define ECDSA_QAX_MEM_SIZE_BYTES 48
+
+/** ECDSA_QAY_MEM register
+ *  The memory that stores y coordinates of QA.
+ */
+#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
+#define ECDSA_QAY_MEM_SIZE_BYTES 48
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/ecdsa_struct.h b/components/soc/esp32s31/register/soc/ecdsa_struct.h
new file mode 100644
index 00000000000..deba75ef854
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/ecdsa_struct.h
@@ -0,0 +1,557 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Data Memory */
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  ECDSA configure register
+ */
+typedef union {
+    struct {
+        /** work_mode : R/W; bitpos: [1:0]; default: 0;
+         *  The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
+         *  Generate Mode. 2: Export Public Key Mode. 3: invalid.
+         */
+        uint32_t work_mode:2;
+        /** ecc_curve : R/W; bitpos: [3:2]; default: 0;
+         *  The ecc curve select bit of ECDSA Accelerator.  0: P-192. 1: P-256. 2: P-384 3: SM2.
+         */
+        uint32_t ecc_curve:2;
+        /** software_set_k : R/W; bitpos: [4]; default: 0;
+         *  The source of k select bit. 0: k is automatically generated by hardware. 1: k is
+         *  written by software.
+         */
+        uint32_t software_set_k:1;
+        /** software_set_z : R/W; bitpos: [5]; default: 0;
+         *  The source of z select bit. 0: z is generated from SHA result. 1: z is written by
+         *  software.
+         */
+        uint32_t software_set_z:1;
+        /** deterministic_k : R/W; bitpos: [6]; default: 0;
+         *  The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
+         *  deterministic derivation algorithm.
+         */
+        uint32_t deterministic_k:1;
+        /** use_hardware_key : R/W; bitpos: [7]; default: 0;
+         *  Configures the ECDSA use software key or hardware key.
+         *  0: Software key.
+         *  1: Hardware key.
+         */
+        uint32_t use_hardware_key:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ecdsa_conf_reg_t;
+
+/** Type of start register
+ *  ECDSA start register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
+         *  after configuration.
+         */
+        uint32_t start:1;
+        /** load_done : WT; bitpos: [1]; default: 0;
+         *  Write 1 to input load done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t load_done:1;
+        /** get_done : WT; bitpos: [2]; default: 0;
+         *  Write 1 to input get done signal of ECDSA Accelerator. This bit will be
+         *  self-cleared after configuration.
+         */
+        uint32_t get_done:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} ecdsa_start_reg_t;
+
+/** Type of timeout_limit register
+ *  ECDSA timeout limit configure register
+ */
+typedef union {
+    struct {
+        /** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The timeout limitation for waiting sub-IP.
+         */
+        uint32_t timeout_limit:32;
+    };
+    uint32_t val;
+} ecdsa_timeout_limit_reg_t;
+
+
+/** Group: Clock and reset registers */
+/** Type of clk register
+ *  ECDSA clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_gate_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  ECDSA interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        /** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_raw:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_raw_reg_t;
+
+/** Type of int_st register
+ *  ECDSA interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        /** sha_release_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_st:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_st_reg_t;
+
+/** Type of int_ena register
+ *  ECDSA interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        /** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_ena:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  ECDSA interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the ecdsa_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the ecdsa_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the ecdsa_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        /** sha_release_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the ecdsa_sha_release_int interrupt
+         */
+        uint32_t sha_release_int_clr:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_int_clr_reg_t;
+
+
+/** Group: Status registers */
+/** Type of state register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** busy : RO; bitpos: [1:0]; default: 0;
+         *  The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
+         *  state.
+         */
+        uint32_t busy:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} ecdsa_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of result register
+ *  ECDSA result register
+ */
+typedef union {
+    struct {
+        /** operation_result : RO/SS; bitpos: [0]; default: 0;
+         *  The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
+         *  done.
+         */
+        uint32_t operation_result:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_result_reg_t;
+
+
+/** Group: Status Register */
+/** Type of free register
+ *  ECDSA free state
+ */
+typedef union {
+    struct {
+        /** free : R/W; bitpos: [0]; default: 1;
+         *  Represents if ECDSA Accelerator is free or not.
+         *  0: non-free
+         *  1: free
+         */
+        uint32_t free:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_free_reg_t;
+
+
+/** Group: Key Registers */
+/** Type of key_0 register
+ *  ECDSA key data register 0
+ */
+typedef union {
+    struct {
+        /** key_0 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_0 that is a part of key material.
+         */
+        uint32_t key_0:32;
+    };
+    uint32_t val;
+} ecdsa_key_0_reg_t;
+
+/** Type of key_1 register
+ *  ECDSA key data register 1
+ */
+typedef union {
+    struct {
+        /** key_1 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_1 that is a part of key material.
+         */
+        uint32_t key_1:32;
+    };
+    uint32_t val;
+} ecdsa_key_1_reg_t;
+
+/** Type of key_2 register
+ *  ECDSA key data register 2
+ */
+typedef union {
+    struct {
+        /** key_2 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_2 that is a part of key material.
+         */
+        uint32_t key_2:32;
+    };
+    uint32_t val;
+} ecdsa_key_2_reg_t;
+
+/** Type of key_3 register
+ *  ECDSA key data register 3
+ */
+typedef union {
+    struct {
+        /** key_3 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_3 that is a part of key material.
+         */
+        uint32_t key_3:32;
+    };
+    uint32_t val;
+} ecdsa_key_3_reg_t;
+
+/** Type of key_4 register
+ *  ECDSA key data register 4
+ */
+typedef union {
+    struct {
+        /** key_4 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_4 that is a part of key material.
+         */
+        uint32_t key_4:32;
+    };
+    uint32_t val;
+} ecdsa_key_4_reg_t;
+
+/** Type of key_5 register
+ *  ECDSA key data register 5
+ */
+typedef union {
+    struct {
+        /** key_5 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_5 that is a part of key material.
+         */
+        uint32_t key_5:32;
+    };
+    uint32_t val;
+} ecdsa_key_5_reg_t;
+
+/** Type of key_6 register
+ *  ECDSA key data register 6
+ */
+typedef union {
+    struct {
+        /** key_6 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_6 that is a part of key material.
+         */
+        uint32_t key_6:32;
+    };
+    uint32_t val;
+} ecdsa_key_6_reg_t;
+
+/** Type of key_7 register
+ *  ECDSA key data register 7
+ */
+typedef union {
+    struct {
+        /** key_7 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_7 that is a part of key material.
+         */
+        uint32_t key_7:32;
+    };
+    uint32_t val;
+} ecdsa_key_7_reg_t;
+
+/** Type of key_8 register
+ *  ECDSA key data register 8
+ */
+typedef union {
+    struct {
+        /** key_8 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_8 that is a part of key material.
+         */
+        uint32_t key_8:32;
+    };
+    uint32_t val;
+} ecdsa_key_8_reg_t;
+
+/** Type of key_9 register
+ *  ECDSA key data register 9
+ */
+typedef union {
+    struct {
+        /** key_9 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_9 that is a part of key material.
+         */
+        uint32_t key_9:32;
+    };
+    uint32_t val;
+} ecdsa_key_9_reg_t;
+
+/** Type of key_10 register
+ *  ECDSA key data register 10
+ */
+typedef union {
+    struct {
+        /** key_10 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_10 that is a part of key material.
+         */
+        uint32_t key_10:32;
+    };
+    uint32_t val;
+} ecdsa_key_10_reg_t;
+
+/** Type of key_11 register
+ *  ECDSA key data register 11
+ */
+typedef union {
+    struct {
+        /** key_11 : R/W; bitpos: [31:0]; default: 0;
+         *  These bits stores key_11 that is a part of key material.
+         */
+        uint32_t key_11:32;
+    };
+    uint32_t val;
+} ecdsa_key_11_reg_t;
+
+
+/** Group: SHA register */
+/** Type of sha_mode register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_mode : R/W; bitpos: [3:0]; default: 0;
+         *  The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
+         *  SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
+         *  invalid.
+         */
+        uint32_t sha_mode:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} ecdsa_sha_mode_reg_t;
+
+/** Type of sha_start register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_start_reg_t;
+
+/** Type of sha_continue register
+ *  ECDSA control SHA register
+ */
+typedef union {
+    struct {
+        /** sha_continue : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
+         *  bit will be self-cleared after configuration.
+         */
+        uint32_t sha_continue:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_continue_reg_t;
+
+/** Type of sha_busy register
+ *  ECDSA status register
+ */
+typedef union {
+    struct {
+        /** sha_busy : RO; bitpos: [0]; default: 0;
+         *  The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
+         *  calculation. 0: SHA is idle.
+         */
+        uint32_t sha_busy:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecdsa_sha_busy_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38830480;
+         *  ECDSA version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecdsa_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile ecdsa_conf_reg_t conf;
+    volatile ecdsa_clk_reg_t clk;
+    volatile ecdsa_int_raw_reg_t int_raw;
+    volatile ecdsa_int_st_reg_t int_st;
+    volatile ecdsa_int_ena_reg_t int_ena;
+    volatile ecdsa_int_clr_reg_t int_clr;
+    volatile ecdsa_start_reg_t start;
+    volatile ecdsa_state_reg_t state;
+    volatile ecdsa_result_reg_t result;
+    volatile ecdsa_timeout_limit_reg_t timeout_limit;
+    volatile ecdsa_free_reg_t free;
+    uint32_t reserved_030[4];
+    volatile ecdsa_key_0_reg_t key_0;
+    volatile ecdsa_key_1_reg_t key_1;
+    volatile ecdsa_key_2_reg_t key_2;
+    volatile ecdsa_key_3_reg_t key_3;
+    volatile ecdsa_key_4_reg_t key_4;
+    volatile ecdsa_key_5_reg_t key_5;
+    volatile ecdsa_key_6_reg_t key_6;
+    volatile ecdsa_key_7_reg_t key_7;
+    volatile ecdsa_key_8_reg_t key_8;
+    volatile ecdsa_key_9_reg_t key_9;
+    volatile ecdsa_key_10_reg_t key_10;
+    volatile ecdsa_key_11_reg_t key_11;
+    uint32_t reserved_070[35];
+    volatile ecdsa_date_reg_t date;
+    uint32_t reserved_100[64];
+    volatile ecdsa_sha_mode_reg_t sha_mode;
+    uint32_t reserved_204[3];
+    volatile ecdsa_sha_start_reg_t sha_start;
+    volatile ecdsa_sha_continue_reg_t sha_continue;
+    volatile ecdsa_sha_busy_reg_t sha_busy;
+    uint32_t reserved_21c[25];
+    volatile uint32_t message[16];
+    uint32_t reserved_2c0[72];
+    volatile uint32_t r[12];
+    volatile uint32_t s[12];
+    volatile uint32_t z[12];
+    volatile uint32_t qax[12];
+    volatile uint32_t qay[12];
+} ecdsa_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/efuse_reg.h b/components/soc/esp32s31/register/soc/efuse_reg.h
new file mode 100644
index 00000000000..abefddf6a73
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/efuse_reg.h
@@ -0,0 +1,2800 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Represents pgm_data0
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Represents pgm_data1
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Represents pgm_data2
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Represents pgm_data3
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 3th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Represents pgm_data4
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Represents pgm_data5
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Represents pgm_data6
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Represents pgm_data7
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Represents pgm_check_value0
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 0th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Represents pgm_check_value1
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 1th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Represents pgm_check_value2
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Configures the 2th RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  Represents rd_wr_dis
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  Represents whether programming of individual eFuse memory bit is disabled.  For
+ *  mapping between the bits of this field and the eFuse memory bits, please refer to
+ *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
+ *  1: Disabled
+ *  0: Enabled
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  Represents whether reading of individual eFuse block(block4~block9) is disabled or
+ *  enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [10]; default: 0;
+ *  Represents whether the function of usb switch to jtag is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(10))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  10
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  Represents whether the function that forces chip into download mode is disabled or
+ *  enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0;
+ *  Represents whether SPI0 controller during boot_mode_download is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  Represents whether TWAI function is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+ *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+ *  is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  Represents whether JTAG is disabled in soft way.
+ *  Odd number: disabled
+ *  Even number: enabled
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  Represents whether JTAG is disabled in the hard way(permanently).
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+ *  mode).
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_HUK_GEN_STATE : RO; bitpos: [27:23]; default: 0;
+ *  Represents the control of validation of HUK generate mode. Odd of 1 is invalid,
+ *  even of 1 is valid.
+ */
+#define EFUSE_HUK_GEN_STATE    0x0000001FU
+#define EFUSE_HUK_GEN_STATE_M  (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S)
+#define EFUSE_HUK_GEN_STATE_V  0x0000001FU
+#define EFUSE_HUK_GEN_STATE_S  23
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_KM_RND_SWITCH_CYCLE : RO; bitpos: [0]; default: 0;
+ *  Represents the control of key manager random number switch cycle. 0: control by
+ *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE    (BIT(0))
+#define EFUSE_KM_RND_SWITCH_CYCLE_M  (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_V  0x00000001U
+#define EFUSE_KM_RND_SWITCH_CYCLE_S  0
+/** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [6:2]; default: 0;
+ *  Represents whether the deploy mode of key manager is disable or not.
+ *  1: disabled
+ *  0: enabled.
+ *  bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & rma
+ *  nonce, bit4: psram
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE    0x0000001FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_V  0x0000001FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_S  2
+/** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [11:7]; default: 0;
+ *  Represents whether corresponding key can only be deployed once. 1 is true, 0 is
+ *  false.
+ *  0: ecsda
+ *  1: flash & spi boot srambler
+ *  2: hmac & aes
+ *  3: ds & rma nonce
+ *  4: psram
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE    0x0000001FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_V  0x0000001FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_S  7
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [16:12]; default: 0;
+ *  Represents whether corresponding key must come from key manager. 1 is true, 0 is
+ *  false.
+ *  0: ecsda
+ *  1: flash
+ *  2: reserved
+ *  3: reserved
+ *  4: psram
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY    0x0000001FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_V  0x0000001FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_S  12
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY : RO; bitpos: [17]; default: 0;
+ *  Represents whether to disable software written init key, and force use
+ *  efuse_init_key.
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY    (BIT(17))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S  17
+/** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [18]; default: 0;
+ *  Represents whether to configure flash encryption use xts-128 key. else use xts-256
+ *  key.
+ *  0: 128-bit key
+ *  1: 256-bit key
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256    (BIT(18))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_M  (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_S  18
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [19]; default: 0;
+ *  Represents the threshold level of the RTC watchdog STG0 timeout.
+ *  0: Original threshold configuration value of STG0 *2
+ *  1: Original threshold configuration value of STG0 *4
+ *  2: Original threshold configuration value of STG0 *8
+ *  3: Original threshold configuration value of STG0 *16
+ */
+#define EFUSE_WDT_DELAY_SEL    (BIT(19))
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000001U
+#define EFUSE_WDT_DELAY_SEL_S  19
+/** EFUSE_DIS_SM_CRYPT : RO; bitpos: [20]; default: 0;
+ *  Represents whether to disable all the SM crypto functions, including SM2, SM3.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_SM_CRYPT    (BIT(20))
+#define EFUSE_DIS_SM_CRYPT_M  (EFUSE_DIS_SM_CRYPT_V << EFUSE_DIS_SM_CRYPT_S)
+#define EFUSE_DIS_SM_CRYPT_V  0x00000001U
+#define EFUSE_DIS_SM_CRYPT_S  20
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [23:21]; default: 0;
+ *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.
+ *  Odd number of 1: enabled
+ *  Even number of 1: disabled
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [24]; default: 0;
+ *  Represents whether revoking first secure boot key is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(24))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  24
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [25]; default: 0;
+ *  Represents whether revoking second secure boot key is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(25))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  25
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [26]; default: 0;
+ *  Represents whether revoking third secure boot key is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(26))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  26
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [4:0]; default: 0;
+ *  Represents the purpose of Key0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000001FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_0_S  0
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [9:5]; default: 0;
+ *  Represents the purpose of Key1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000001FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_1_S  5
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [14:10]; default: 0;
+ *  Represents the purpose of Key2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000001FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_2_S  10
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [19:15]; default: 0;
+ *  Represents the purpose of Key3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000001FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_3_S  15
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [24:20]; default: 0;
+ *  Represents the purpose of Key4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000001FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_4_S  20
+/** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [25]; default: 0;
+ *  Represents whether permanently turn on ECC const-time mode.
+ *  1: turn on
+ *  0: turn off
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME    (BIT(25))
+#define EFUSE_ECC_FORCE_CONST_TIME_M  (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_S  25
+/** EFUSE_ECDSA_DISABLE_SOFT_K : RO; bitpos: [26]; default: 0;
+ *  Represents whether permanently turn off ECDSA software set KEY.
+ *  1: turn off
+ *  0: turn on
+ */
+#define EFUSE_ECDSA_DISABLE_SOFT_K    (BIT(26))
+#define EFUSE_ECDSA_DISABLE_SOFT_K_M  (EFUSE_ECDSA_DISABLE_SOFT_K_V << EFUSE_ECDSA_DISABLE_SOFT_K_S)
+#define EFUSE_ECDSA_DISABLE_SOFT_K_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_SOFT_K_S  26
+/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [28:27]; default: 0;
+ *  Represents the spa secure level by configuring the clock random divide mode.
+ */
+#define EFUSE_SEC_DPA_LEVEL    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_M  (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
+#define EFUSE_SEC_DPA_LEVEL_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_S  27
+/** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0;
+ *  Represents whether to enable xts clock anti-dpa attack function.
+ *  0: Disabled.
+ *  1: Enabled
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE    (BIT(29))
+#define EFUSE_XTS_DPA_CLK_ENABLE_M  (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_S  29
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [1:0]; default: 0;
+ *  Represents the control of the xts pseudo-round anti-dpa attack function.
+ *  0: controlled by register.
+ *  1-3: the higher the value is, the more pseudo-rounds are inserted to the xts-aes
+ *  calculation
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_S  0
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [2]; default: 0;
+ *  Represents whether secure boot is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(2))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  2
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [3]; default: 0;
+ *  Represents whether revoking aggressive secure boot is enabled or disabled.
+ *  1: enabled.
+ *  0: disabled
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(3))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  3
+/** EFUSE_FLASH_TYPE : RO; bitpos: [5]; default: 0;
+ *  flash type: 0: nor flash, 1: nand flash
+ */
+#define EFUSE_FLASH_TYPE    (BIT(5))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  5
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [9]; default: 0;
+ *  Set this bit to disable download via USB-OTG.
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE    (BIT(9))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S  9
+/** EFUSE_FLASH_TPUW : RO; bitpos: [15:12]; default: 0;
+ *  Represents the flash waiting time after power-up, in unit of ms. When the value
+ *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+ *  is 2 times the programmed value.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  12
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [16]; default: 0;
+ *  Represents whether Download mode is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(16))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  16
+/** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [17]; default: 0;
+ *  Represents whether direct boot mode is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_DIRECT_BOOT    (BIT(17))
+#define EFUSE_DIS_DIRECT_BOOT_M  (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
+#define EFUSE_DIS_DIRECT_BOOT_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_S  17
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [18]; default: 0;
+ *  Represents whether print from USB-Serial-JTAG is disabled or enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT    (BIT(18))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S  18
+/** EFUSE_LOCK_KM_KEY : RO; bitpos: [19]; default: 0;
+ *  Represetns whether to lock the efuse xts key.
+ *  1. Lock
+ *  0: Unlock
+ */
+#define EFUSE_LOCK_KM_KEY    (BIT(19))
+#define EFUSE_LOCK_KM_KEY_M  (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S)
+#define EFUSE_LOCK_KM_KEY_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_S  19
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [20]; default: 0;
+ *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.
+ *  1: Disable
+ *  0: Enable
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE    (BIT(20))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S  20
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [21]; default: 0;
+ *  Represents whether security download is enabled or disabled.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(21))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  21
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [23:22]; default: 0;
+ *  Represents the type of UART printing.
+ *  00: force enable printing
+ *  01: enable printing when GPIO8 is reset at low level
+ *  10: enable printing when GPIO8 is reset at high level
+ *  11: force disable printing
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  22
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [24]; default: 0;
+ *  Represents whether ROM code is forced to send a resume command during SPI boot.
+ *  1: forced
+ *  0:not forced
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(24))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  24
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_SECURE_VERSION : RO; bitpos: [15:0]; default: 0;
+ *  Represents the version used by ESP-IDF anti-rollback feature.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  0
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [16]; default: 0;
+ *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+ *  enabled.
+ *  1: disabled
+ *  0: enabled
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE    (BIT(16))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S  16
+/** EFUSE_HYS_EN_PAD : RO; bitpos: [17]; default: 0;
+ *  Represents whether the hysteresis function of corresponding PAD is enabled.
+ *  1: enabled
+ *  0:disabled
+ */
+#define EFUSE_HYS_EN_PAD    (BIT(17))
+#define EFUSE_HYS_EN_PAD_M  (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S)
+#define EFUSE_HYS_EN_PAD_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_S  17
+
+/** EFUSE_RD_REPEAT_DATA5_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA5_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_DCDC_VSET_EN : RO; bitpos: [2]; default: 0;
+ *  Select dcdc vset use efuse_dcdc_vset.
+ */
+#define EFUSE_DCDC_VSET_EN    (BIT(2))
+#define EFUSE_DCDC_VSET_EN_M  (EFUSE_DCDC_VSET_EN_V << EFUSE_DCDC_VSET_EN_S)
+#define EFUSE_DCDC_VSET_EN_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_S  2
+/** EFUSE_DIS_WDT : RO; bitpos: [3]; default: 0;
+ *  Set this bit to disable watch dog.
+ */
+#define EFUSE_DIS_WDT    (BIT(3))
+#define EFUSE_DIS_WDT_M  (EFUSE_DIS_WDT_V << EFUSE_DIS_WDT_S)
+#define EFUSE_DIS_WDT_V  0x00000001U
+#define EFUSE_DIS_WDT_S  3
+/** EFUSE_DIS_SWD : RO; bitpos: [4]; default: 0;
+ *  Set this bit to disable super-watchdog.
+ */
+#define EFUSE_DIS_SWD    (BIT(4))
+#define EFUSE_DIS_SWD_M  (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S)
+#define EFUSE_DIS_SWD_V  0x00000001U
+#define EFUSE_DIS_SWD_S  4
+/** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [11]; default: 0;
+ *  Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable
+ */
+#define EFUSE_SECURE_BOOT_SHA384_EN    (BIT(11))
+#define EFUSE_SECURE_BOOT_SHA384_EN_M  (EFUSE_SECURE_BOOT_SHA384_EN_V << EFUSE_SECURE_BOOT_SHA384_EN_S)
+#define EFUSE_SECURE_BOOT_SHA384_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_SHA384_EN_S  11
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION : RO; bitpos: [15:12]; default: 0;
+ *  Represents the anti-rollback secure version of the 2nd stage bootloader used by the
+ *  ROM bootloader.
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION    0x0000000FU
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V  0x0000000FU
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S  12
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [16]; default: 0;
+ *  Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.
+ *  1: Enabled
+ *  0: Disabled
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN    (BIT(16))
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V  0x00000001U
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S  16
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [17]; default: 0;
+ *  Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM
+ *  bootloader.
+ *  1: Enable
+ *  0: Disable
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM    (BIT(17))
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V  0x00000001U
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S  17
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR : RO; bitpos: [29:18]; default: 0;
+ *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+ *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+ *  - this feature is disabled.
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR    0x00000FFFU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V  0x00000FFFU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S  18
+/** EFUSE_RMA_ENA : RO; bitpos: [31:30]; default: 0;
+ *  Represents whether rma function is supported in download mode.
+ *  2'b01/2'b10: enabled
+ *  2'b00/2'b11: disabled
+ */
+#define EFUSE_RMA_ENA    0x00000003U
+#define EFUSE_RMA_ENA_M  (EFUSE_RMA_ENA_V << EFUSE_RMA_ENA_S)
+#define EFUSE_RMA_ENA_V  0x00000003U
+#define EFUSE_RMA_ENA_S  30
+
+/** EFUSE_RD_REPEAT_DATA6_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA6_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_RMA_SESSION_COUNTER : RO; bitpos: [2:0]; default: 0;
+ *  Represents the number of times the RMA session has been entered.
+ */
+#define EFUSE_RMA_SESSION_COUNTER    0x00000007U
+#define EFUSE_RMA_SESSION_COUNTER_M  (EFUSE_RMA_SESSION_COUNTER_V << EFUSE_RMA_SESSION_COUNTER_S)
+#define EFUSE_RMA_SESSION_COUNTER_V  0x00000007U
+#define EFUSE_RMA_SESSION_COUNTER_S  0
+/** EFUSE_RMA_NONCE_ENA : RO; bitpos: [4:3]; default: 0;
+ *  Represents whether random number NONCE is used in RMA and whether the KM module is
+ *  used to generate the NONCE
+ *  . 2'bx0: No NONCE
+ *  2'b1x: Use KM generate NONCE.
+ */
+#define EFUSE_RMA_NONCE_ENA    0x00000003U
+#define EFUSE_RMA_NONCE_ENA_M  (EFUSE_RMA_NONCE_ENA_V << EFUSE_RMA_NONCE_ENA_S)
+#define EFUSE_RMA_NONCE_ENA_V  0x00000003U
+#define EFUSE_RMA_NONCE_ENA_S  3
+/** EFUSE_RMA_CHIP_INFO_SOURCE : RO; bitpos: [5]; default: 0;
+ *  Represents whether HUK_info is selected as the source for calculating CHIP_info in
+ *  RMA.
+ *  1: use HUK_info
+ *  0: use UNIQ_id
+ */
+#define EFUSE_RMA_CHIP_INFO_SOURCE    (BIT(5))
+#define EFUSE_RMA_CHIP_INFO_SOURCE_M  (EFUSE_RMA_CHIP_INFO_SOURCE_V << EFUSE_RMA_CHIP_INFO_SOURCE_S)
+#define EFUSE_RMA_CHIP_INFO_SOURCE_V  0x00000001U
+#define EFUSE_RMA_CHIP_INFO_SOURCE_S  5
+/** EFUSE_RMA_DISABLE_FAST_VEF : RO; bitpos: [6]; default: 0;
+ *  Represents whether disable FAST_VEF in RMA session.
+ *  1: disable
+ *  0: enable
+ */
+#define EFUSE_RMA_DISABLE_FAST_VEF    (BIT(6))
+#define EFUSE_RMA_DISABLE_FAST_VEF_M  (EFUSE_RMA_DISABLE_FAST_VEF_V << EFUSE_RMA_DISABLE_FAST_VEF_S)
+#define EFUSE_RMA_DISABLE_FAST_VEF_V  0x00000001U
+#define EFUSE_RMA_DISABLE_FAST_VEF_S  6
+/** EFUSE_PVT_0_GLITCH_EN : RO; bitpos: [7]; default: 0;
+ *  Represents whether to enable PVT power glitch monitor function.
+ *  1:Enable.
+ *  0:Disable
+ */
+#define EFUSE_PVT_0_GLITCH_EN    (BIT(7))
+#define EFUSE_PVT_0_GLITCH_EN_M  (EFUSE_PVT_0_GLITCH_EN_V << EFUSE_PVT_0_GLITCH_EN_S)
+#define EFUSE_PVT_0_GLITCH_EN_V  0x00000001U
+#define EFUSE_PVT_0_GLITCH_EN_S  7
+/** EFUSE_PVT_0_GLITCH_MODE : RO; bitpos: [9:8]; default: 0;
+ *  Use to configure glitch mode
+ */
+#define EFUSE_PVT_0_GLITCH_MODE    0x00000003U
+#define EFUSE_PVT_0_GLITCH_MODE_M  (EFUSE_PVT_0_GLITCH_MODE_V << EFUSE_PVT_0_GLITCH_MODE_S)
+#define EFUSE_PVT_0_GLITCH_MODE_V  0x00000003U
+#define EFUSE_PVT_0_GLITCH_MODE_S  8
+/** EFUSE_PVT_1_GLITCH_EN : RO; bitpos: [10]; default: 0;
+ *  Represents whether to enable PVT power glitch monitor function.
+ *  1:Enable.
+ *  0:Disable
+ */
+#define EFUSE_PVT_1_GLITCH_EN    (BIT(10))
+#define EFUSE_PVT_1_GLITCH_EN_M  (EFUSE_PVT_1_GLITCH_EN_V << EFUSE_PVT_1_GLITCH_EN_S)
+#define EFUSE_PVT_1_GLITCH_EN_V  0x00000001U
+#define EFUSE_PVT_1_GLITCH_EN_S  10
+/** EFUSE_PVT_1_GLITCH_MODE : RO; bitpos: [12:11]; default: 0;
+ *  Use to configure glitch mode
+ */
+#define EFUSE_PVT_1_GLITCH_MODE    0x00000003U
+#define EFUSE_PVT_1_GLITCH_MODE_M  (EFUSE_PVT_1_GLITCH_MODE_V << EFUSE_PVT_1_GLITCH_MODE_S)
+#define EFUSE_PVT_1_GLITCH_MODE_V  0x00000003U
+#define EFUSE_PVT_1_GLITCH_MODE_S  11
+/** EFUSE_PMU_FLASH_POWER_SEL : RO; bitpos: [13]; default: 0;
+ *  FLASH power select.
+ *  1'b1: use 3.3V
+ *  1'b0: use 1.8V
+ */
+#define EFUSE_PMU_FLASH_POWER_SEL    (BIT(13))
+#define EFUSE_PMU_FLASH_POWER_SEL_M  (EFUSE_PMU_FLASH_POWER_SEL_V << EFUSE_PMU_FLASH_POWER_SEL_S)
+#define EFUSE_PMU_FLASH_POWER_SEL_V  0x00000001U
+#define EFUSE_PMU_FLASH_POWER_SEL_S  13
+/** EFUSE_PMU_FLASH_POWER_SEL_EN : RO; bitpos: [14]; default: 0;
+ *  FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0:
+ *  invalidates EFUSE_PMU_FLASH_POWER_SEL
+ */
+#define EFUSE_PMU_FLASH_POWER_SEL_EN    (BIT(14))
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_M  (EFUSE_PMU_FLASH_POWER_SEL_EN_V << EFUSE_PMU_FLASH_POWER_SEL_EN_S)
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_V  0x00000001U
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_S  14
+/** EFUSE_POWER_GLITCH_EN : RO; bitpos: [18:15]; default: 0;
+ *  set these bit enable power glitch enable
+ */
+#define EFUSE_POWER_GLITCH_EN    0x0000000FU
+#define EFUSE_POWER_GLITCH_EN_M  (EFUSE_POWER_GLITCH_EN_V << EFUSE_POWER_GLITCH_EN_S)
+#define EFUSE_POWER_GLITCH_EN_V  0x0000000FU
+#define EFUSE_POWER_GLITCH_EN_S  15
+/** EFUSE_ENA_XTS_SHADOW : RO; bitpos: [19]; default: 0;
+ *  Represents whether to enable XTS-AES shadow core countermeasure against fault
+ *  injection attacks.
+ *  0: Disabled
+ *  1: Enabled
+ */
+#define EFUSE_ENA_XTS_SHADOW    (BIT(19))
+#define EFUSE_ENA_XTS_SHADOW_M  (EFUSE_ENA_XTS_SHADOW_V << EFUSE_ENA_XTS_SHADOW_S)
+#define EFUSE_ENA_XTS_SHADOW_V  0x00000001U
+#define EFUSE_ENA_XTS_SHADOW_S  19
+/** EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER : RO; bitpos: [20]; default: 0;
+ *  Represents whether to enable ciphertext scrambler for external memory .
+ *  0: Disabled
+ *  1: Enabled
+ */
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER    (BIT(20))
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_M  (EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V << EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S)
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V  0x00000001U
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S  20
+/** EFUSE_RE_ENABLE_JTAG_SOURCE : RO; bitpos: [21]; default: 0;
+ *  Represents which Crypto peripheral is selected for re-enabling JTAG.
+ *  0: RMA
+ *  1: HMAC
+ */
+#define EFUSE_RE_ENABLE_JTAG_SOURCE    (BIT(21))
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_M  (EFUSE_RE_ENABLE_JTAG_SOURCE_V << EFUSE_RE_ENABLE_JTAG_SOURCE_S)
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_V  0x00000001U
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_S  21
+
+/** EFUSE_RD_REPEAT_DATA7_REG register
+ *  Represents rd_repeat_data
+ */
+#define EFUSE_RD_REPEAT_DATA7_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_REPEAT7_RSVD : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_REPEAT7_RSVD    0x0000FFFFU
+#define EFUSE_REPEAT7_RSVD_M  (EFUSE_REPEAT7_RSVD_V << EFUSE_REPEAT7_RSVD_S)
+#define EFUSE_REPEAT7_RSVD_V  0x0000FFFFU
+#define EFUSE_REPEAT7_RSVD_S  0
+
+/** EFUSE_RD_MAC_SYS0_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS0_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents MAC address. Low 32-bit.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SYS1_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS1_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Represents MAC address. High 16-bit.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0;
+ *  Represents the extended bits of MAC address.
+ */
+#define EFUSE_MAC_EXT    0x0000FFFFU
+#define EFUSE_MAC_EXT_M  (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S)
+#define EFUSE_MAC_EXT_V  0x0000FFFFU
+#define EFUSE_MAC_EXT_S  16
+
+/** EFUSE_RD_MAC_SYS3_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
+ *  Represents the first 14-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
+#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_S  18
+
+/** EFUSE_RD_MAC_SYS4_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the second 32-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+/** EFUSE_RD_MAC_SYS5_REG register
+ *  Represents rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the third 32-bit of zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Represents rd_sys_part1_data0
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_0_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Represents rd_sys_part1_data1
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Represents rd_sys_part1_data2
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Represents rd_sys_part1_data3
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Represents rd_sys_part1_data4
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_4_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Represents rd_sys_part1_data5
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_5_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Represents rd_sys_part1_data6
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_6_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Represents rd_sys_part1_data7
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_7_S  0
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Represents rd_usr_data0
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Represents rd_usr_data1
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Represents rd_usr_data2
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Represents rd_usr_data3
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Represents rd_usr_data4
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Represents rd_usr_data5
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Represents rd_usr_data6
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA6    0xFFFFFFFFU
+#define EFUSE_USR_DATA6_M  (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
+#define EFUSE_USR_DATA6_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA6_S  0
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Represents rd_usr_data7
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of block3 (user).
+ */
+#define EFUSE_USR_DATA7    0xFFFFFFFFU
+#define EFUSE_USR_DATA7_M  (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
+#define EFUSE_USR_DATA7_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA7_S  0
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Represents rd_key0_data0
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Represents rd_key0_data1
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Represents rd_key0_data2
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Represents rd_key0_data3
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Represents rd_key0_data4
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Represents rd_key0_data5
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Represents rd_key0_data6
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Represents rd_key0_data7
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Represents rd_key1_data0
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Represents rd_key1_data1
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Represents rd_key1_data2
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Represents rd_key1_data3
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Represents rd_key1_data4
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Represents rd_key1_data5
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Represents rd_key1_data6
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Represents rd_key1_data7
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Represents rd_key2_data0
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Represents rd_key2_data1
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Represents rd_key2_data2
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Represents rd_key2_data3
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Represents rd_key2_data4
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Represents rd_key2_data5
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Represents rd_key2_data6
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Represents rd_key2_data7
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Represents rd_key3_data0
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Represents rd_key3_data1
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Represents rd_key3_data2
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Represents rd_key3_data3
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Represents rd_key3_data4
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Represents rd_key3_data5
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Represents rd_key3_data6
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Represents rd_key3_data7
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Represents rd_key4_data0
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Represents rd_key4_data1
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Represents rd_key4_data2
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Represents rd_key4_data3
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Represents rd_key4_data4
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Represents rd_key4_data5
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Represents rd_key4_data6
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Represents rd_key4_data7
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of key4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the zeroth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the first 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the second 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the third 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the fourth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the fifth 32-bit of second part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Represents rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [0]; default: 0;
+ *  Represents whether enable usb device exchange pins of D+ and D- or not.
+ *  1: enabled
+ *  0: disabled
+ */
+#define EFUSE_USB_DEVICE_EXCHG_PINS    (BIT(0))
+#define EFUSE_USB_DEVICE_EXCHG_PINS_M  (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S)
+#define EFUSE_USB_DEVICE_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_DEVICE_EXCHG_PINS_S  0
+
+/** EFUSE_RD_REPEAT_DATA_ERR0_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  Represents the programming error of EFUSE_RD_DIS
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [10]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_JTAG
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(10))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  10
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+ */
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR    (BIT(13))
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M  (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S)
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V  0x00000001U
+#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_TWAI
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_HUK_GEN_STATE_ERR : RO; bitpos: [27:23]; default: 0;
+ *  Represents the programming error of EFUSE_HUK_GEN_STATE
+ */
+#define EFUSE_HUK_GEN_STATE_ERR    0x0000001FU
+#define EFUSE_HUK_GEN_STATE_ERR_M  (EFUSE_HUK_GEN_STATE_ERR_V << EFUSE_HUK_GEN_STATE_ERR_S)
+#define EFUSE_HUK_GEN_STATE_ERR_V  0x0000001FU
+#define EFUSE_HUK_GEN_STATE_ERR_S  23
+
+/** EFUSE_RD_REPEAT_DATA_ERR1_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_KM_RND_SWITCH_CYCLE_ERR : RO; bitpos: [0]; default: 0;
+ *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+ */
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR    (BIT(0))
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_M  (EFUSE_KM_RND_SWITCH_CYCLE_ERR_V << EFUSE_KM_RND_SWITCH_CYCLE_ERR_S)
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_V  0x00000001U
+#define EFUSE_KM_RND_SWITCH_CYCLE_ERR_S  0
+/** EFUSE_KM_DISABLE_DEPLOY_MODE_ERR : RO; bitpos: [6:2]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+ */
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR    0x0000001FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_M  (EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V << EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S)
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_V  0x0000001FU
+#define EFUSE_KM_DISABLE_DEPLOY_MODE_ERR_S  2
+/** EFUSE_KM_DEPLOY_ONLY_ONCE_ERR : RO; bitpos: [11:7]; default: 0;
+ *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+ */
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR    0x0000001FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_M  (EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V << EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S)
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_V  0x0000001FU
+#define EFUSE_KM_DEPLOY_ONLY_ONCE_ERR_S  7
+/** EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR : RO; bitpos: [16:12]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+ */
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR    0x0000001FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_M  (EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S)
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_V  0x0000001FU
+#define EFUSE_FORCE_USE_KEY_MANAGER_KEY_ERR_S  12
+/** EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR : RO; bitpos: [17]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+ */
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR    (BIT(17))
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_M  (EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V << EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S)
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_V  0x00000001U
+#define EFUSE_FORCE_DISABLE_SW_INIT_KEY_ERR_S  17
+/** EFUSE_KM_XTS_KEY_LENGTH_256_ERR : RO; bitpos: [18]; default: 0;
+ *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+ */
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR    (BIT(18))
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_M  (EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V << EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S)
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_V  0x00000001U
+#define EFUSE_KM_XTS_KEY_LENGTH_256_ERR_S  18
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    (BIT(19))
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000001U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  19
+/** EFUSE_DIS_SM_CRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_SM_CRYPT
+ */
+#define EFUSE_DIS_SM_CRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_SM_CRYPT_ERR_M  (EFUSE_DIS_SM_CRYPT_ERR_V << EFUSE_DIS_SM_CRYPT_ERR_S)
+#define EFUSE_DIS_SM_CRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_SM_CRYPT_ERR_S  20
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [23:21]; default: 0;
+ *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [24]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(24))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  24
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [25]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(25))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  25
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(26))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  26
+
+/** EFUSE_RD_REPEAT_DATA_ERR2_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR2_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [4:0]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000001FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  0
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [9:5]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000001FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  5
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [14:10]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000001FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  10
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [19:15]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000001FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  15
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [24:20]; default: 0;
+ *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000001FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000001FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  20
+/** EFUSE_ECC_FORCE_CONST_TIME_ERR : RO; bitpos: [25]; default: 0;
+ *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+ */
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR    (BIT(25))
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_M  (EFUSE_ECC_FORCE_CONST_TIME_ERR_V << EFUSE_ECC_FORCE_CONST_TIME_ERR_S)
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_V  0x00000001U
+#define EFUSE_ECC_FORCE_CONST_TIME_ERR_S  25
+/** EFUSE_ECDSA_DISABLE_SOFT_K_ERR : RO; bitpos: [26]; default: 0;
+ *  Represents the programming error of EFUSE_ECDSA_DISABLE_SOFT_K
+ */
+#define EFUSE_ECDSA_DISABLE_SOFT_K_ERR    (BIT(26))
+#define EFUSE_ECDSA_DISABLE_SOFT_K_ERR_M  (EFUSE_ECDSA_DISABLE_SOFT_K_ERR_V << EFUSE_ECDSA_DISABLE_SOFT_K_ERR_S)
+#define EFUSE_ECDSA_DISABLE_SOFT_K_ERR_V  0x00000001U
+#define EFUSE_ECDSA_DISABLE_SOFT_K_ERR_S  26
+/** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [28:27]; default: 0;
+ *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+ */
+#define EFUSE_SEC_DPA_LEVEL_ERR    0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_M  (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S)
+#define EFUSE_SEC_DPA_LEVEL_ERR_V  0x00000003U
+#define EFUSE_SEC_DPA_LEVEL_ERR_S  27
+/** EFUSE_XTS_DPA_CLK_ENABLE_ERR : RO; bitpos: [29]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+ */
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR    (BIT(29))
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_M  (EFUSE_XTS_DPA_CLK_ENABLE_ERR_V << EFUSE_XTS_DPA_CLK_ENABLE_ERR_S)
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_V  0x00000001U
+#define EFUSE_XTS_DPA_CLK_ENABLE_ERR_S  29
+
+/** EFUSE_RD_REPEAT_DATA_ERR3_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR : RO; bitpos: [1:0]; default: 0;
+ *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+ */
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR    0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_M  (EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S)
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_V  0x00000003U
+#define EFUSE_XTS_DPA_PSEUDO_LEVEL_ERR_S  0
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [2]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(2))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  2
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [3]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(3))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  3
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [5]; default: 0;
+ *  Represents the programming error of EFUSE_FLASH_TYPE
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(5))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  5
+/** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR : RO; bitpos: [9]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR    (BIT(9))
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_ERR_S  9
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Represents the programming error of EFUSE_FLASH_TPUW
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  12
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [16]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(16))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  16
+/** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [17]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+ */
+#define EFUSE_DIS_DIRECT_BOOT_ERR    (BIT(17))
+#define EFUSE_DIS_DIRECT_BOOT_ERR_M  (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S)
+#define EFUSE_DIS_DIRECT_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_DIRECT_BOOT_ERR_S  17
+/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR : RO; bitpos: [18]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR    (BIT(18))
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR_S  18
+/** EFUSE_LOCK_KM_KEY_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_LOCK_KM_KEY
+ */
+#define EFUSE_LOCK_KM_KEY_ERR    (BIT(19))
+#define EFUSE_LOCK_KM_KEY_ERR_M  (EFUSE_LOCK_KM_KEY_ERR_V << EFUSE_LOCK_KM_KEY_ERR_S)
+#define EFUSE_LOCK_KM_KEY_ERR_V  0x00000001U
+#define EFUSE_LOCK_KM_KEY_ERR_S  19
+/** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+ */
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR    (BIT(20))
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S  20
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [21]; default: 0;
+ *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(21))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  21
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [23:22]; default: 0;
+ *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  22
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [24]; default: 0;
+ *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(24))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  24
+
+/** EFUSE_RD_REPEAT_DATA_ERR4_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [15:0]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_VERSION
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  0
+/** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [16]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+ */
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR    (BIT(16))
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M  (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S)
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S  16
+/** EFUSE_HYS_EN_PAD_ERR : RO; bitpos: [17]; default: 0;
+ *  Represents the programming error of EFUSE_HYS_EN_PAD
+ */
+#define EFUSE_HYS_EN_PAD_ERR    (BIT(17))
+#define EFUSE_HYS_EN_PAD_ERR_M  (EFUSE_HYS_EN_PAD_ERR_V << EFUSE_HYS_EN_PAD_ERR_S)
+#define EFUSE_HYS_EN_PAD_ERR_V  0x00000001U
+#define EFUSE_HYS_EN_PAD_ERR_S  17
+
+/** EFUSE_RD_REPEAT_DATA_ERR5_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR5_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_DCDC_VSET_EN_ERR : RO; bitpos: [2]; default: 0;
+ *  Represents the programming error of EFUSE_DCDC_VSET_EN
+ */
+#define EFUSE_DCDC_VSET_EN_ERR    (BIT(2))
+#define EFUSE_DCDC_VSET_EN_ERR_M  (EFUSE_DCDC_VSET_EN_ERR_V << EFUSE_DCDC_VSET_EN_ERR_S)
+#define EFUSE_DCDC_VSET_EN_ERR_V  0x00000001U
+#define EFUSE_DCDC_VSET_EN_ERR_S  2
+/** EFUSE_DIS_WDT_ERR : RO; bitpos: [3]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_WDT
+ */
+#define EFUSE_DIS_WDT_ERR    (BIT(3))
+#define EFUSE_DIS_WDT_ERR_M  (EFUSE_DIS_WDT_ERR_V << EFUSE_DIS_WDT_ERR_S)
+#define EFUSE_DIS_WDT_ERR_V  0x00000001U
+#define EFUSE_DIS_WDT_ERR_S  3
+/** EFUSE_DIS_SWD_ERR : RO; bitpos: [4]; default: 0;
+ *  Represents the programming error of EFUSE_DIS_SWD
+ */
+#define EFUSE_DIS_SWD_ERR    (BIT(4))
+#define EFUSE_DIS_SWD_ERR_M  (EFUSE_DIS_SWD_ERR_V << EFUSE_DIS_SWD_ERR_S)
+#define EFUSE_DIS_SWD_ERR_V  0x00000001U
+#define EFUSE_DIS_SWD_ERR_S  4
+/** EFUSE_SECURE_BOOT_SHA384_EN_ERR : RO; bitpos: [11]; default: 0;
+ *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
+ */
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR    (BIT(11))
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_M  (EFUSE_SECURE_BOOT_SHA384_EN_ERR_V << EFUSE_SECURE_BOOT_SHA384_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_SHA384_EN_ERR_S  11
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR : RO; bitpos: [15:12]; default: 0;
+ *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR    0x0000000FU
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V  0x0000000FU
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S  12
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [16]; default: 0;
+ *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR    (BIT(16))
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V  0x00000001U
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S  16
+/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [17]; default: 0;
+ *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM
+ */
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR    (BIT(17))
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M  (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S)
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V  0x00000001U
+#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S  17
+/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR : RO; bitpos: [29:18]; default: 0;
+ *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR
+ */
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR    0x00000FFFU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_M  (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S)
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V  0x00000FFFU
+#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S  18
+/** EFUSE_RMA_ENA_ERR : RO; bitpos: [31:30]; default: 0;
+ *  Represents the programming error of EFUSE_RMA_ENA
+ */
+#define EFUSE_RMA_ENA_ERR    0x00000003U
+#define EFUSE_RMA_ENA_ERR_M  (EFUSE_RMA_ENA_ERR_V << EFUSE_RMA_ENA_ERR_S)
+#define EFUSE_RMA_ENA_ERR_V  0x00000003U
+#define EFUSE_RMA_ENA_ERR_S  30
+
+/** EFUSE_RD_REPEAT_DATA_ERR6_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR6_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_RMA_SESSION_COUNTER_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Represents the programming error of EFUSE_RMA_SESSION_COUNTER
+ */
+#define EFUSE_RMA_SESSION_COUNTER_ERR    0x00000007U
+#define EFUSE_RMA_SESSION_COUNTER_ERR_M  (EFUSE_RMA_SESSION_COUNTER_ERR_V << EFUSE_RMA_SESSION_COUNTER_ERR_S)
+#define EFUSE_RMA_SESSION_COUNTER_ERR_V  0x00000007U
+#define EFUSE_RMA_SESSION_COUNTER_ERR_S  0
+/** EFUSE_RMA_NONCE_ENA_ERR : RO; bitpos: [4:3]; default: 0;
+ *  Represents the programming error of EFUSE_RMA_NONCE_ENA
+ */
+#define EFUSE_RMA_NONCE_ENA_ERR    0x00000003U
+#define EFUSE_RMA_NONCE_ENA_ERR_M  (EFUSE_RMA_NONCE_ENA_ERR_V << EFUSE_RMA_NONCE_ENA_ERR_S)
+#define EFUSE_RMA_NONCE_ENA_ERR_V  0x00000003U
+#define EFUSE_RMA_NONCE_ENA_ERR_S  3
+/** EFUSE_RMA_CHIP_INFO_SOURCE_ERR : RO; bitpos: [5]; default: 0;
+ *  Represents the programming error of EFUSE_RMA_CHIP_INFO_SOURCE
+ */
+#define EFUSE_RMA_CHIP_INFO_SOURCE_ERR    (BIT(5))
+#define EFUSE_RMA_CHIP_INFO_SOURCE_ERR_M  (EFUSE_RMA_CHIP_INFO_SOURCE_ERR_V << EFUSE_RMA_CHIP_INFO_SOURCE_ERR_S)
+#define EFUSE_RMA_CHIP_INFO_SOURCE_ERR_V  0x00000001U
+#define EFUSE_RMA_CHIP_INFO_SOURCE_ERR_S  5
+/** EFUSE_RMA_DISABLE_FAST_VEF_ERR : RO; bitpos: [6]; default: 0;
+ *  Represents the programming error of EFUSE_RMA_DISABLE_FAST_VEF
+ */
+#define EFUSE_RMA_DISABLE_FAST_VEF_ERR    (BIT(6))
+#define EFUSE_RMA_DISABLE_FAST_VEF_ERR_M  (EFUSE_RMA_DISABLE_FAST_VEF_ERR_V << EFUSE_RMA_DISABLE_FAST_VEF_ERR_S)
+#define EFUSE_RMA_DISABLE_FAST_VEF_ERR_V  0x00000001U
+#define EFUSE_RMA_DISABLE_FAST_VEF_ERR_S  6
+/** EFUSE_PVT_0_GLITCH_EN_ERR : RO; bitpos: [7]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_0_GLITCH_EN
+ */
+#define EFUSE_PVT_0_GLITCH_EN_ERR    (BIT(7))
+#define EFUSE_PVT_0_GLITCH_EN_ERR_M  (EFUSE_PVT_0_GLITCH_EN_ERR_V << EFUSE_PVT_0_GLITCH_EN_ERR_S)
+#define EFUSE_PVT_0_GLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_PVT_0_GLITCH_EN_ERR_S  7
+/** EFUSE_PVT_0_GLITCH_MODE_ERR : RO; bitpos: [9:8]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_0_GLITCH_MODE
+ */
+#define EFUSE_PVT_0_GLITCH_MODE_ERR    0x00000003U
+#define EFUSE_PVT_0_GLITCH_MODE_ERR_M  (EFUSE_PVT_0_GLITCH_MODE_ERR_V << EFUSE_PVT_0_GLITCH_MODE_ERR_S)
+#define EFUSE_PVT_0_GLITCH_MODE_ERR_V  0x00000003U
+#define EFUSE_PVT_0_GLITCH_MODE_ERR_S  8
+/** EFUSE_PVT_1_GLITCH_EN_ERR : RO; bitpos: [10]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_1_GLITCH_EN
+ */
+#define EFUSE_PVT_1_GLITCH_EN_ERR    (BIT(10))
+#define EFUSE_PVT_1_GLITCH_EN_ERR_M  (EFUSE_PVT_1_GLITCH_EN_ERR_V << EFUSE_PVT_1_GLITCH_EN_ERR_S)
+#define EFUSE_PVT_1_GLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_PVT_1_GLITCH_EN_ERR_S  10
+/** EFUSE_PVT_1_GLITCH_MODE_ERR : RO; bitpos: [12:11]; default: 0;
+ *  Represents the programming error of EFUSE_PVT_1_GLITCH_MODE
+ */
+#define EFUSE_PVT_1_GLITCH_MODE_ERR    0x00000003U
+#define EFUSE_PVT_1_GLITCH_MODE_ERR_M  (EFUSE_PVT_1_GLITCH_MODE_ERR_V << EFUSE_PVT_1_GLITCH_MODE_ERR_S)
+#define EFUSE_PVT_1_GLITCH_MODE_ERR_V  0x00000003U
+#define EFUSE_PVT_1_GLITCH_MODE_ERR_S  11
+/** EFUSE_PMU_FLASH_POWER_SEL_ERR : RO; bitpos: [13]; default: 0;
+ *  Represents the programming error of EFUSE_PMU_FLASH_POWER_SEL
+ */
+#define EFUSE_PMU_FLASH_POWER_SEL_ERR    (BIT(13))
+#define EFUSE_PMU_FLASH_POWER_SEL_ERR_M  (EFUSE_PMU_FLASH_POWER_SEL_ERR_V << EFUSE_PMU_FLASH_POWER_SEL_ERR_S)
+#define EFUSE_PMU_FLASH_POWER_SEL_ERR_V  0x00000001U
+#define EFUSE_PMU_FLASH_POWER_SEL_ERR_S  13
+/** EFUSE_PMU_FLASH_POWER_SEL_EN_ERR : RO; bitpos: [14]; default: 0;
+ *  Represents the programming error of EFUSE_PMU_FLASH_POWER_SEL_EN
+ */
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_ERR    (BIT(14))
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_ERR_M  (EFUSE_PMU_FLASH_POWER_SEL_EN_ERR_V << EFUSE_PMU_FLASH_POWER_SEL_EN_ERR_S)
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_ERR_V  0x00000001U
+#define EFUSE_PMU_FLASH_POWER_SEL_EN_ERR_S  14
+/** EFUSE_POWER_GLITCH_EN_ERR : RO; bitpos: [18:15]; default: 0;
+ *  Represents the programming error of EFUSE_POWER_GLITCH_EN
+ */
+#define EFUSE_POWER_GLITCH_EN_ERR    0x0000000FU
+#define EFUSE_POWER_GLITCH_EN_ERR_M  (EFUSE_POWER_GLITCH_EN_ERR_V << EFUSE_POWER_GLITCH_EN_ERR_S)
+#define EFUSE_POWER_GLITCH_EN_ERR_V  0x0000000FU
+#define EFUSE_POWER_GLITCH_EN_ERR_S  15
+/** EFUSE_ENA_XTS_SHADOW_ERR : RO; bitpos: [19]; default: 0;
+ *  Represents the programming error of EFUSE_ENA_XTS_SHADOW
+ */
+#define EFUSE_ENA_XTS_SHADOW_ERR    (BIT(19))
+#define EFUSE_ENA_XTS_SHADOW_ERR_M  (EFUSE_ENA_XTS_SHADOW_ERR_V << EFUSE_ENA_XTS_SHADOW_ERR_S)
+#define EFUSE_ENA_XTS_SHADOW_ERR_V  0x00000001U
+#define EFUSE_ENA_XTS_SHADOW_ERR_S  19
+/** EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR : RO; bitpos: [20]; default: 0;
+ *  Represents the programming error of EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER
+ */
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR    (BIT(20))
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR_M  (EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR_V << EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR_S)
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR_V  0x00000001U
+#define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_ERR_S  20
+/** EFUSE_RE_ENABLE_JTAG_SOURCE_ERR : RO; bitpos: [21]; default: 0;
+ *  Represents the programming error of EFUSE_RE_ENABLE_JTAG_SOURCE
+ */
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_ERR    (BIT(21))
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_ERR_M  (EFUSE_RE_ENABLE_JTAG_SOURCE_ERR_V << EFUSE_RE_ENABLE_JTAG_SOURCE_ERR_S)
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_ERR_V  0x00000001U
+#define EFUSE_RE_ENABLE_JTAG_SOURCE_ERR_S  21
+
+/** EFUSE_RD_REPEAT_DATA_ERR7_REG register
+ *  Represents rd_repeat_data_err
+ */
+#define EFUSE_RD_REPEAT_DATA_ERR7_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_REPEAT7_RSVD_ERR : RO; bitpos: [15:0]; default: 0;
+ *  Represents the programming error of EFUSE_REPEAT7_RSVD
+ */
+#define EFUSE_REPEAT7_RSVD_ERR    0x0000FFFFU
+#define EFUSE_REPEAT7_RSVD_ERR_M  (EFUSE_REPEAT7_RSVD_ERR_V << EFUSE_REPEAT7_RSVD_ERR_S)
+#define EFUSE_REPEAT7_RSVD_ERR_V  0x0000FFFFU
+#define EFUSE_REPEAT7_RSVD_ERR_S  0
+
+/** EFUSE_RD_RS_DATA_ERR0_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_mac_sys
+ */
+#define EFUSE_RD_MAC_SYS_ERR_NUM    0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_M  (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S)
+#define EFUSE_RD_MAC_SYS_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_MAC_SYS_ERR_NUM_S  0
+/** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_mac_sys is reliable
+ *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
+ */
+#define EFUSE_RD_MAC_SYS_FAIL    (BIT(3))
+#define EFUSE_RD_MAC_SYS_FAIL_M  (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S)
+#define EFUSE_RD_MAC_SYS_FAIL_V  0x00000001U
+#define EFUSE_RD_MAC_SYS_FAIL_S  3
+/** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_sys_part1_data
+ */
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S  4
+/** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_sys_part1_data is reliable
+ *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
+ *  over 6.
+ */
+#define EFUSE_RD_SYS_PART1_DATA_FAIL    (BIT(7))
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_M  (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART1_DATA_FAIL_S  7
+/** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_usr_data
+ */
+#define EFUSE_RD_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_M  (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S)
+#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
+/** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_usr_data is reliable
+ *  1: Means that programming rd_usr_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_M  (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S)
+#define EFUSE_RD_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_USR_DATA_FAIL_S  11
+/** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_key0_data
+ */
+#define EFUSE_RD_KEY0_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_M  (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY0_DATA_ERR_NUM_S  12
+/** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_key0_data is reliable
+ *  1: Means that programming rd_key0_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_KEY0_DATA_FAIL    (BIT(15))
+#define EFUSE_RD_KEY0_DATA_FAIL_M  (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S)
+#define EFUSE_RD_KEY0_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY0_DATA_FAIL_S  15
+/** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_key1_data
+ */
+#define EFUSE_RD_KEY1_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_M  (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY1_DATA_ERR_NUM_S  16
+/** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_key1_data is reliable
+ *  1: Means that programming rd_key1_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_KEY1_DATA_FAIL    (BIT(19))
+#define EFUSE_RD_KEY1_DATA_FAIL_M  (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S)
+#define EFUSE_RD_KEY1_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY1_DATA_FAIL_S  19
+/** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_key2_data
+ */
+#define EFUSE_RD_KEY2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_M  (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY2_DATA_ERR_NUM_S  20
+/** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_key2_data is reliable
+ *  1: Means that programming rd_key2_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_KEY2_DATA_FAIL    (BIT(23))
+#define EFUSE_RD_KEY2_DATA_FAIL_M  (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S)
+#define EFUSE_RD_KEY2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY2_DATA_FAIL_S  23
+/** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_key3_data
+ */
+#define EFUSE_RD_KEY3_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_M  (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY3_DATA_ERR_NUM_S  24
+/** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_key3_data is reliable
+ *  1: Means that programming rd_key3_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_KEY3_DATA_FAIL    (BIT(27))
+#define EFUSE_RD_KEY3_DATA_FAIL_M  (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S)
+#define EFUSE_RD_KEY3_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY3_DATA_FAIL_S  27
+/** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_key4_data
+ */
+#define EFUSE_RD_KEY4_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_M  (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S)
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_KEY4_DATA_ERR_NUM_S  28
+/** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_key4_data is reliable
+ *  1: Means that programming rd_key4_data failed and the number of error bytes is over
+ *  6.
+ */
+#define EFUSE_RD_KEY4_DATA_FAIL    (BIT(31))
+#define EFUSE_RD_KEY4_DATA_FAIL_M  (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S)
+#define EFUSE_RD_KEY4_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_KEY4_DATA_FAIL_S  31
+
+/** EFUSE_RD_RS_DATA_ERR1_REG register
+ *  Represents rd_rs_data_err
+ */
+#define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x18c)
+/** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  Represents the error number of registers.
+ *  The value of this signal means the number of error bytes in rd_sys_part2_data
+ */
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM    0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M  (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S)
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S  0
+/** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [3]; default: 0;
+ *  Represents error status of register.
+ *  0: Means no failure and that the data of rd_sys_part2_data is reliable
+ *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
+ *  over 6.
+ */
+#define EFUSE_RD_SYS_PART2_DATA_FAIL    (BIT(3))
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_M  (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S)
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_V  0x00000001U
+#define EFUSE_RD_SYS_PART2_DATA_FAIL_S  3
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38834580;
+ *  Represents eFuse version. Date:2025-09-19 19:52:16,
+ *  ScriptRev:abfb97fc087287a4eacd02828cb3ca8dd0d0e75f
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to force power down eFuse SRAM.
+ *  1: Force
+ *  0: No effect
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Configures whether to force activate clock signal of eFuse SRAM.
+ *  1: Force activate
+ *  0: No effect
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Configures whether to force power up eFuse SRAM.
+ *  1: Force
+ *  0: No effect
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Configures whether to force enable eFuse register configuration clock signal.
+ *  1: Force
+ *  0: The clock is enabled only during the reading and writing of registers
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuration register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  Configures operation command type.
+ *  0x5A5A: Program operation command
+ *  0x5AA5: Read operation command
+ *  Other values: No effect
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_ECDSA_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_ECDSA_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_CFG_ECDSA_P192_BLK : R/W; bitpos: [3:0]; default: 0;
+ *  Configures which block to use for ECDSA P192 key output.
+ */
+#define EFUSE_CFG_ECDSA_P192_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P192_BLK_M  (EFUSE_CFG_ECDSA_P192_BLK_V << EFUSE_CFG_ECDSA_P192_BLK_S)
+#define EFUSE_CFG_ECDSA_P192_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P192_BLK_S  0
+/** EFUSE_CFG_ECDSA_P256_BLK : R/W; bitpos: [7:4]; default: 0;
+ *  Configures which block to use for ECDSA P256 key output.
+ */
+#define EFUSE_CFG_ECDSA_P256_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P256_BLK_M  (EFUSE_CFG_ECDSA_P256_BLK_V << EFUSE_CFG_ECDSA_P256_BLK_S)
+#define EFUSE_CFG_ECDSA_P256_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P256_BLK_S  4
+/** EFUSE_CFG_ECDSA_P384_L_BLK : R/W; bitpos: [11:8]; default: 0;
+ *  Configures which block to use for ECDSA P384 key low part output.
+ */
+#define EFUSE_CFG_ECDSA_P384_L_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_L_BLK_M  (EFUSE_CFG_ECDSA_P384_L_BLK_V << EFUSE_CFG_ECDSA_P384_L_BLK_S)
+#define EFUSE_CFG_ECDSA_P384_L_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_L_BLK_S  8
+/** EFUSE_CFG_ECDSA_P384_H_BLK : R/W; bitpos: [15:12]; default: 0;
+ *  Configures which block to use for ECDSA P256 key high part output.
+ */
+#define EFUSE_CFG_ECDSA_P384_H_BLK    0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_H_BLK_M  (EFUSE_CFG_ECDSA_P384_H_BLK_V << EFUSE_CFG_ECDSA_P384_H_BLK_S)
+#define EFUSE_CFG_ECDSA_P384_H_BLK_V  0x0000000FU
+#define EFUSE_CFG_ECDSA_P384_H_BLK_S  12
+/** EFUSE_CUR_ECDSA_P192_BLK : RO; bitpos: [19:16]; default: 0;
+ *  Represents which block is used for ECDSA P192 key output.
+ */
+#define EFUSE_CUR_ECDSA_P192_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P192_BLK_M  (EFUSE_CUR_ECDSA_P192_BLK_V << EFUSE_CUR_ECDSA_P192_BLK_S)
+#define EFUSE_CUR_ECDSA_P192_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P192_BLK_S  16
+/** EFUSE_CUR_ECDSA_P256_BLK : RO; bitpos: [23:20]; default: 0;
+ *  Represents which block is used for ECDSA P256 key output.
+ */
+#define EFUSE_CUR_ECDSA_P256_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P256_BLK_M  (EFUSE_CUR_ECDSA_P256_BLK_V << EFUSE_CUR_ECDSA_P256_BLK_S)
+#define EFUSE_CUR_ECDSA_P256_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P256_BLK_S  20
+/** EFUSE_CUR_ECDSA_P384_L_BLK : RO; bitpos: [27:24]; default: 0;
+ *  Represents which block is used for ECDSA P384 key low part output.
+ */
+#define EFUSE_CUR_ECDSA_P384_L_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_L_BLK_M  (EFUSE_CUR_ECDSA_P384_L_BLK_V << EFUSE_CUR_ECDSA_P384_L_BLK_S)
+#define EFUSE_CUR_ECDSA_P384_L_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_L_BLK_S  24
+/** EFUSE_CUR_ECDSA_P384_H_BLK : RO; bitpos: [31:28]; default: 0;
+ *  Represents which block is used for ECDSA P384 key high part output.
+ */
+#define EFUSE_CUR_ECDSA_P384_H_BLK    0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_H_BLK_M  (EFUSE_CUR_ECDSA_P384_H_BLK_V << EFUSE_CUR_ECDSA_P384_H_BLK_S)
+#define EFUSE_CUR_ECDSA_P384_H_BLK_V  0x0000000FU
+#define EFUSE_CUR_ECDSA_P384_H_BLK_S  28
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Represents the state of the eFuse state machine.
+ *  0: Reset state, the initial state after power-up
+ *  1: Idle state
+ *  Other values: Non-idle state
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0;
+ *  Represents the number of block valid bit.
+ */
+#define EFUSE_BLK0_VALID_BIT_CNT    0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_M  (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S)
+#define EFUSE_BLK0_VALID_BIT_CNT_V  0x000003FFU
+#define EFUSE_BLK0_VALID_BIT_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether to send read commands.
+ *  1: Send
+ *  0: No effect
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0;
+ *  Configures whether to send programming commands.
+ *  1: Send
+ *  0: No effect
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  Configures the serial number of the block to be programmed. Value 0-10 corresponds
+ *  to block number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of EFUSE_READ_DONE_INT.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  The raw interrupt status of EFUSE_PGM_DONE_INT.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of EFUSE_READ_DONE_INT.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of EFUSE_PGM_DONE_INT.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable EFUSE_READ_DONE_INT.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable EFUSE_PGM_DONE_INT.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear EFUSE_READ_DONE_INT.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear EFUSE_PGM_DONE_INT.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 24;
+ *  Configures the division factor of the rising clock of the programming voltage
+ *  (ramp-up slew rate be slower than 2.5V/250us, and ramp-up 10mV for one-cycle, so
+ *  reg_dac_clk_div > fclk).
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Configures clock cycles for programming voltage to rise (VDDQ 2.5V, ramp-up 10mV
+ *  for one-cycle). Measurement unit: a clock cycle divided by EFUSE_DAC_CLK_DIV.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Configures whether to reduce the power supply of programming voltage.
+ *  0: Not reduce
+ *  1: Reduce
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the read hold time (>=14ns). Measurement unit: One cycle of the eFuse
+ *  core clock.
+ */
+#define EFUSE_THR_A    0x000000FFU
+#define EFUSE_THR_A_M  (EFUSE_THR_A_V << EFUSE_THR_A_S)
+#define EFUSE_THR_A_V  0x000000FFU
+#define EFUSE_THR_A_S  0
+/** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2;
+ *  Configures the read time (>=52ns). Measurement unit: One cycle of the eFuse core
+ *  clock.
+ */
+#define EFUSE_TRD    0x000000FFU
+#define EFUSE_TRD_M  (EFUSE_TRD_V << EFUSE_TRD_S)
+#define EFUSE_TRD_V  0x000000FFU
+#define EFUSE_TRD_S  8
+/** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1;
+ *  Configures the read setup time (>=14ns). Measurement unit: One cycle of the eFuse
+ *  core clock.
+ */
+#define EFUSE_TSUR_A    0x000000FFU
+#define EFUSE_TSUR_A_M  (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S)
+#define EFUSE_TSUR_A_V  0x000000FFU
+#define EFUSE_TSUR_A_S  16
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 27;
+ *  Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of
+ *  the eFuse core clock.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1;
+ *  Configures the programming setup time (>14ns). Measurement unit: One cycle of the
+ *  eFuse core clock.
+ */
+#define EFUSE_TSUP_A    0x000000FFU
+#define EFUSE_TSUP_A_M  (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S)
+#define EFUSE_TSUP_A_V  0x000000FFU
+#define EFUSE_TSUP_A_S  0
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 14746;
+ *  Configures the power up time for VDDQ (>reg_dac_clk_div*reg_dac_clk_div).
+ *  Measurement unit: One cycle of the eFuse core clock.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+/** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1;
+ *  Configures the programming hold time (>=11ns). Measurement unit: One cycle of the
+ *  eFuse core clock.
+ */
+#define EFUSE_THP_A    0x000000FFU
+#define EFUSE_THP_A_M  (EFUSE_THP_A_V << EFUSE_THP_A_S)
+#define EFUSE_THP_A_V  0x000000FFU
+#define EFUSE_THP_A_S  24
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 480;
+ *  Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse
+ *  core clock.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+/** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 240;
+ *  Configures the active programming time (>10us). Measurement unit: One cycle of the
+ *  eFuse core clock.
+ */
+#define EFUSE_TPGM    0x0000FFFFU
+#define EFUSE_TPGM_M  (EFUSE_TPGM_V << EFUSE_TPGM_S)
+#define EFUSE_TPGM_V  0x0000FFFFU
+#define EFUSE_TPGM_S  16
+
+/** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+#define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0;
+ *  Configures whether to bypass the Reed-Solomon (RS) correction step.
+ *  0: Not bypass
+ *  1: Bypass
+ */
+#define EFUSE_BYPASS_RS_CORRECTION    (BIT(0))
+#define EFUSE_BYPASS_RS_CORRECTION_M  (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S)
+#define EFUSE_BYPASS_RS_CORRECTION_V  0x00000001U
+#define EFUSE_BYPASS_RS_CORRECTION_S  0
+/** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0;
+ *  Configures which block number to bypass the Reed-Solomon (RS) correction step.
+ */
+#define EFUSE_BYPASS_RS_BLK_NUM    0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_M  (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S)
+#define EFUSE_BYPASS_RS_BLK_NUM_V  0x000007FFU
+#define EFUSE_BYPASS_RS_BLK_NUM_S  1
+/** EFUSE_UPDATE : WT; bitpos: [12]; default: 0;
+ *  Configures whether to update multi-bit register signals.
+ *  1: Update
+ *  0: No effect
+ */
+#define EFUSE_UPDATE    (BIT(12))
+#define EFUSE_UPDATE_M  (EFUSE_UPDATE_V << EFUSE_UPDATE_S)
+#define EFUSE_UPDATE_V  0x00000001U
+#define EFUSE_UPDATE_S  12
+/** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1;
+ *  Configures the inactive programming time. Measurement unit: One cycle of the eFuse
+ *  core clock.
+ */
+#define EFUSE_TPGM_INACTIVE    0x000000FFU
+#define EFUSE_TPGM_INACTIVE_M  (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S)
+#define EFUSE_TPGM_INACTIVE_V  0x000000FFU
+#define EFUSE_TPGM_INACTIVE_S  13
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/efuse_struct.h b/components/soc/esp32s31/register/soc/efuse_struct.h
new file mode 100644
index 00000000000..89c3db2d059
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/efuse_struct.h
@@ -0,0 +1,1791 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: program_data registers */
+/** Type of pgm_datan register
+ *  Represents pgm_datan
+ */
+typedef union {
+    struct {
+        /** pgm_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_datan_reg_t;
+
+/** Type of pgm_check_valuen register
+ *  Represents pgm_check_valuen
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_n : R/W; bitpos: [31:0]; default: 0;
+         *  Configures the nth RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_n:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_valuen_reg_t;
+
+
+/** Group: block0 registers */
+/** Type of rd_wr_dis register
+ *  Represents rd_wr_dis
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  Represents whether programming of individual eFuse memory bit is disabled.  For
+         *  mapping between the bits of this field and the eFuse memory bits, please refer to
+         *  Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.
+         *  1: Disabled
+         *  0: Enabled
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  Represents whether reading of individual eFuse block(block4~block9) is disabled or
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t rd_dis:7;
+        uint32_t reserved_7:3;
+        /** dis_usb_jtag : RO; bitpos: [10]; default: 0;
+         *  Represents whether the function of usb switch to jtag is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_usb_jtag:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  Represents whether the function that forces chip into download mode is disabled or
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_force_download:1;
+        /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0;
+         *  Represents whether SPI0 controller during boot_mode_download is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t spi_download_mspi_dis:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  Represents whether TWAI function is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  Represents whether the selection between usb_to_jtag and pad_to_jtag through
+         *  strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
+         *  is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  Represents whether JTAG is disabled in soft way.
+         *  Odd number: disabled
+         *  Even number: enabled
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  Represents whether JTAG is disabled in the hard way(permanently).
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether flash encrypt function is disabled or enabled(except in SPI boot
+         *  mode).
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        uint32_t reserved_21:2;
+        /** huk_gen_state : RO; bitpos: [27:23]; default: 0;
+         *  Represents the control of validation of HUK generate mode. Odd of 1 is invalid,
+         *  even of 1 is valid.
+         */
+        uint32_t huk_gen_state:5;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** km_rnd_switch_cycle : RO; bitpos: [0]; default: 0;
+         *  Represents the control of key manager random number switch cycle. 0: control by
+         *  register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
+         */
+        uint32_t km_rnd_switch_cycle:1;
+        uint32_t reserved_1:1;
+        /** km_disable_deploy_mode : RO; bitpos: [6:2]; default: 0;
+         *  Represents whether the deploy mode of key manager is disable or not.
+         *  1: disabled
+         *  0: enabled.
+         *  bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & rma
+         *  nonce, bit4: psram
+         */
+        uint32_t km_disable_deploy_mode:5;
+        /** km_deploy_only_once : RO; bitpos: [11:7]; default: 0;
+         *  Represents whether corresponding key can only be deployed once. 1 is true, 0 is
+         *  false.
+         *  0: ecsda
+         *  1: flash & spi boot srambler
+         *  2: hmac & aes
+         *  3: ds & rma nonce
+         *  4: psram
+         */
+        uint32_t km_deploy_only_once:5;
+        /** force_use_key_manager_key : RO; bitpos: [16:12]; default: 0;
+         *  Represents whether corresponding key must come from key manager. 1 is true, 0 is
+         *  false.
+         *  0: ecsda
+         *  1: flash
+         *  2: reserved
+         *  3: reserved
+         *  4: psram
+         */
+        uint32_t force_use_key_manager_key:5;
+        /** force_disable_sw_init_key : RO; bitpos: [17]; default: 0;
+         *  Represents whether to disable software written init key, and force use
+         *  efuse_init_key.
+         */
+        uint32_t force_disable_sw_init_key:1;
+        /** km_xts_key_length_256 : RO; bitpos: [18]; default: 0;
+         *  Represents whether to configure flash encryption use xts-128 key. else use xts-256
+         *  key.
+         *  0: 128-bit key
+         *  1: 256-bit key
+         */
+        uint32_t km_xts_key_length_256:1;
+        /** wdt_delay_sel : RO; bitpos: [19]; default: 0;
+         *  Represents the threshold level of the RTC watchdog STG0 timeout.
+         *  0: Original threshold configuration value of STG0 *2
+         *  1: Original threshold configuration value of STG0 *4
+         *  2: Original threshold configuration value of STG0 *8
+         *  3: Original threshold configuration value of STG0 *16
+         */
+        uint32_t wdt_delay_sel:1;
+        /** dis_sm_crypt : RO; bitpos: [20]; default: 0;
+         *  Represents whether to disable all the SM crypto functions, including SM2, SM3.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_sm_crypt:1;
+        /** spi_boot_crypt_cnt : RO; bitpos: [23:21]; default: 0;
+         *  Represents whether SPI boot encrypt/decrypt is disabled or enabled.
+         *  Odd number of 1: enabled
+         *  Even number of 1: disabled
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [24]; default: 0;
+         *  Represents whether revoking first secure boot key is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [25]; default: 0;
+         *  Represents whether revoking second secure boot key is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [26]; default: 0;
+         *  Represents whether revoking third secure boot key is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** key_purpose_0 : RO; bitpos: [4:0]; default: 0;
+         *  Represents the purpose of Key0.
+         */
+        uint32_t key_purpose_0:5;
+        /** key_purpose_1 : RO; bitpos: [9:5]; default: 0;
+         *  Represents the purpose of Key1.
+         */
+        uint32_t key_purpose_1:5;
+        /** key_purpose_2 : RO; bitpos: [14:10]; default: 0;
+         *  Represents the purpose of Key2.
+         */
+        uint32_t key_purpose_2:5;
+        /** key_purpose_3 : RO; bitpos: [19:15]; default: 0;
+         *  Represents the purpose of Key3.
+         */
+        uint32_t key_purpose_3:5;
+        /** key_purpose_4 : RO; bitpos: [24:20]; default: 0;
+         *  Represents the purpose of Key4.
+         */
+        uint32_t key_purpose_4:5;
+        /** ecc_force_const_time : RO; bitpos: [25]; default: 0;
+         *  Represents whether permanently turn on ECC const-time mode.
+         *  1: turn on
+         *  0: turn off
+         */
+        uint32_t ecc_force_const_time:1;
+        /** ecdsa_disable_soft_k : RO; bitpos: [26]; default: 0;
+         *  Represents whether permanently turn off ECDSA software set KEY.
+         *  1: turn off
+         *  0: turn on
+         */
+        uint32_t ecdsa_disable_soft_k:1;
+        /** sec_dpa_level : RO; bitpos: [28:27]; default: 0;
+         *  Represents the spa secure level by configuring the clock random divide mode.
+         */
+        uint32_t sec_dpa_level:2;
+        /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0;
+         *  Represents whether to enable xts clock anti-dpa attack function.
+         *  0: Disabled.
+         *  1: Enabled
+         */
+        uint32_t xts_dpa_clk_enable:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** xts_dpa_pseudo_level : RO; bitpos: [1:0]; default: 0;
+         *  Represents the control of the xts pseudo-round anti-dpa attack function.
+         *  0: controlled by register.
+         *  1-3: the higher the value is, the more pseudo-rounds are inserted to the xts-aes
+         *  calculation
+         */
+        uint32_t xts_dpa_pseudo_level:2;
+        /** secure_boot_en : RO; bitpos: [2]; default: 0;
+         *  Represents whether secure boot is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [3]; default: 0;
+         *  Represents whether revoking aggressive secure boot is enabled or disabled.
+         *  1: enabled.
+         *  0: disabled
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        uint32_t reserved_4:1;
+        /** flash_type : RO; bitpos: [5]; default: 0;
+         *  flash type: 0: nor flash, 1: nand flash
+         */
+        uint32_t flash_type:1;
+        uint32_t reserved_6:3;
+        /** dis_usb_otg_download_mode : RO; bitpos: [9]; default: 0;
+         *  Set this bit to disable download via USB-OTG.
+         */
+        uint32_t dis_usb_otg_download_mode:1;
+        uint32_t reserved_10:2;
+        /** flash_tpuw : RO; bitpos: [15:12]; default: 0;
+         *  Represents the flash waiting time after power-up, in unit of ms. When the value
+         *  less than 15, the waiting time is the programmed value. Otherwise, the waiting time
+         *  is 2 times the programmed value.
+         */
+        uint32_t flash_tpuw:4;
+        /** dis_download_mode : RO; bitpos: [16]; default: 0;
+         *  Represents whether Download mode is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_direct_boot : RO; bitpos: [17]; default: 0;
+         *  Represents whether direct boot mode is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_direct_boot:1;
+        /** dis_usb_serial_jtag_rom_print : RO; bitpos: [18]; default: 0;
+         *  Represents whether print from USB-Serial-JTAG is disabled or enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t dis_usb_serial_jtag_rom_print:1;
+        /** lock_km_key : RO; bitpos: [19]; default: 0;
+         *  Represetns whether to lock the efuse xts key.
+         *  1. Lock
+         *  0: Unlock
+         */
+        uint32_t lock_km_key:1;
+        /** dis_usb_serial_jtag_download_mode : RO; bitpos: [20]; default: 0;
+         *  Represents whether the USB-Serial-JTAG download function is disabled or enabled.
+         *  1: Disable
+         *  0: Enable
+         */
+        uint32_t dis_usb_serial_jtag_download_mode:1;
+        /** enable_security_download : RO; bitpos: [21]; default: 0;
+         *  Represents whether security download is enabled or disabled.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [23:22]; default: 0;
+         *  Represents the type of UART printing.
+         *  00: force enable printing
+         *  01: enable printing when GPIO8 is reset at low level
+         *  10: enable printing when GPIO8 is reset at high level
+         *  11: force disable printing
+         */
+        uint32_t uart_print_control:2;
+        /** force_send_resume : RO; bitpos: [24]; default: 0;
+         *  Represents whether ROM code is forced to send a resume command during SPI boot.
+         *  1: forced
+         *  0:not forced
+         */
+        uint32_t force_send_resume:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** secure_version : RO; bitpos: [15:0]; default: 0;
+         *  Represents the version used by ESP-IDF anti-rollback feature.
+         */
+        uint32_t secure_version:16;
+        /** secure_boot_disable_fast_wake : RO; bitpos: [16]; default: 0;
+         *  Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is
+         *  enabled.
+         *  1: disabled
+         *  0: enabled
+         */
+        uint32_t secure_boot_disable_fast_wake:1;
+        /** hys_en_pad : RO; bitpos: [17]; default: 0;
+         *  Represents whether the hysteresis function of corresponding PAD is enabled.
+         *  1: enabled
+         *  0:disabled
+         */
+        uint32_t hys_en_pad:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_repeat_data5 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** dcdc_vset_en : RO; bitpos: [2]; default: 0;
+         *  Select dcdc vset use efuse_dcdc_vset.
+         */
+        uint32_t dcdc_vset_en:1;
+        /** dis_wdt : RO; bitpos: [3]; default: 0;
+         *  Set this bit to disable watch dog.
+         */
+        uint32_t dis_wdt:1;
+        /** dis_swd : RO; bitpos: [4]; default: 0;
+         *  Set this bit to disable super-watchdog.
+         */
+        uint32_t dis_swd:1;
+        uint32_t reserved_5:6;
+        /** secure_boot_sha384_en : RO; bitpos: [11]; default: 0;
+         *  Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable
+         */
+        uint32_t secure_boot_sha384_en:1;
+        /** bootloader_anti_rollback_secure_version : RO; bitpos: [15:12]; default: 0;
+         *  Represents the anti-rollback secure version of the 2nd stage bootloader used by the
+         *  ROM bootloader.
+         */
+        uint32_t bootloader_anti_rollback_secure_version:4;
+        /** bootloader_anti_rollback_en : RO; bitpos: [16]; default: 0;
+         *  Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.
+         *  1: Enabled
+         *  0: Disabled
+         */
+        uint32_t bootloader_anti_rollback_en:1;
+        /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [17]; default: 0;
+         *  Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM
+         *  bootloader.
+         *  1: Enable
+         *  0: Disable
+         */
+        uint32_t bootloader_anti_rollback_update_in_rom:1;
+        /** recovery_bootloader_flash_sector : RO; bitpos: [29:18]; default: 0;
+         *  Represents the starting flash sector (flash sector size is 0x1000) of the recovery
+         *  bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF
+         *  - this feature is disabled.
+         */
+        uint32_t recovery_bootloader_flash_sector:12;
+        /** rma_ena : RO; bitpos: [31:30]; default: 0;
+         *  Represents whether rma function is supported in download mode.
+         *  2'b01/2'b10: enabled
+         *  2'b00/2'b11: disabled
+         */
+        uint32_t rma_ena:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data5_reg_t;
+
+/** Type of rd_repeat_data6 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** rma_session_counter : RO; bitpos: [2:0]; default: 0;
+         *  Represents the number of times the RMA session has been entered.
+         */
+        uint32_t rma_session_counter:3;
+        /** rma_nonce_ena : RO; bitpos: [4:3]; default: 0;
+         *  Represents whether random number NONCE is used in RMA and whether the KM module is
+         *  used to generate the NONCE
+         *  . 2'bx0: No NONCE
+         *  2'b1x: Use KM generate NONCE.
+         */
+        uint32_t rma_nonce_ena:2;
+        /** rma_chip_info_source : RO; bitpos: [5]; default: 0;
+         *  Represents whether HUK_info is selected as the source for calculating CHIP_info in
+         *  RMA.
+         *  1: use HUK_info
+         *  0: use UNIQ_id
+         */
+        uint32_t rma_chip_info_source:1;
+        /** rma_disable_fast_vef : RO; bitpos: [6]; default: 0;
+         *  Represents whether disable FAST_VEF in RMA session.
+         *  1: disable
+         *  0: enable
+         */
+        uint32_t rma_disable_fast_vef:1;
+        /** pvt_0_glitch_en : RO; bitpos: [7]; default: 0;
+         *  Represents whether to enable PVT power glitch monitor function.
+         *  1:Enable.
+         *  0:Disable
+         */
+        uint32_t pvt_0_glitch_en:1;
+        /** pvt_0_glitch_mode : RO; bitpos: [9:8]; default: 0;
+         *  Use to configure glitch mode
+         */
+        uint32_t pvt_0_glitch_mode:2;
+        /** pvt_1_glitch_en : RO; bitpos: [10]; default: 0;
+         *  Represents whether to enable PVT power glitch monitor function.
+         *  1:Enable.
+         *  0:Disable
+         */
+        uint32_t pvt_1_glitch_en:1;
+        /** pvt_1_glitch_mode : RO; bitpos: [12:11]; default: 0;
+         *  Use to configure glitch mode
+         */
+        uint32_t pvt_1_glitch_mode:2;
+        /** pmu_flash_power_sel : RO; bitpos: [13]; default: 0;
+         *  FLASH power select.
+         *  1'b1: use 3.3V
+         *  1'b0: use 1.8V
+         */
+        uint32_t pmu_flash_power_sel:1;
+        /** pmu_flash_power_sel_en : RO; bitpos: [14]; default: 0;
+         *  FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0:
+         *  invalidates EFUSE_PMU_FLASH_POWER_SEL
+         */
+        uint32_t pmu_flash_power_sel_en:1;
+        /** power_glitch_en : RO; bitpos: [18:15]; default: 0;
+         *  set these bit enable power glitch enable
+         */
+        uint32_t power_glitch_en:4;
+        /** ena_xts_shadow : RO; bitpos: [19]; default: 0;
+         *  Represents whether to enable XTS-AES shadow core countermeasure against fault
+         *  injection attacks.
+         *  0: Disabled
+         *  1: Enabled
+         */
+        uint32_t ena_xts_shadow:1;
+        /** ena_spi_boot_crypt_scrambler : RO; bitpos: [20]; default: 0;
+         *  Represents whether to enable ciphertext scrambler for external memory .
+         *  0: Disabled
+         *  1: Enabled
+         */
+        uint32_t ena_spi_boot_crypt_scrambler:1;
+        /** re_enable_jtag_source : RO; bitpos: [21]; default: 0;
+         *  Represents which Crypto peripheral is selected for re-enabling JTAG.
+         *  0: RMA
+         *  1: HMAC
+         */
+        uint32_t re_enable_jtag_source:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data6_reg_t;
+
+/** Type of rd_repeat_data7 register
+ *  Represents rd_repeat_data
+ */
+typedef union {
+    struct {
+        /** repeat7_rsvd : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t repeat7_rsvd:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data7_reg_t;
+
+
+/** Group: block1 registers */
+/** Type of rd_mac_sys0 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents MAC address. Low 32-bit.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys0_reg_t;
+
+/** Type of rd_mac_sys1 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Represents MAC address. High 16-bit.
+         */
+        uint32_t mac_1:16;
+        /** mac_ext : RO; bitpos: [31:16]; default: 0;
+         *  Represents the extended bits of MAC address.
+         */
+        uint32_t mac_ext:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys1_reg_t;
+
+/** Type of rd_mac_sys3 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Represents the first 14-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys3_reg_t;
+
+/** Type of rd_mac_sys4 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys4_reg_t;
+
+/** Type of rd_mac_sys5 register
+ *  Represents rd_mac_sys
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_sys5_reg_t;
+
+
+/** Group: block2 registers */
+/** Type of rd_sys_part1_datan register
+ *  Represents rd_sys_part1_datan
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of first part of system data.
+         */
+        uint32_t sys_data_part1_n:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_datan_reg_t;
+
+
+/** Group: block3 registers */
+/** Type of rd_usr_datan register
+ *  Represents rd_usr_datan
+ */
+typedef union {
+    struct {
+        /** usr_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of block3 (user).
+         */
+        uint32_t usr_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_datan_reg_t;
+
+
+/** Group: block4 registers */
+/** Type of rd_key0_datan register
+ *  Represents rd_key0_datan
+ */
+typedef union {
+    struct {
+        /** key0_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key0.
+         */
+        uint32_t key0_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_datan_reg_t;
+
+
+/** Group: block5 registers */
+/** Type of rd_key1_datan register
+ *  Represents rd_key1_datan
+ */
+typedef union {
+    struct {
+        /** key1_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key1.
+         */
+        uint32_t key1_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_datan_reg_t;
+
+
+/** Group: block6 registers */
+/** Type of rd_key2_datan register
+ *  Represents rd_key2_datan
+ */
+typedef union {
+    struct {
+        /** key2_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key2.
+         */
+        uint32_t key2_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_datan_reg_t;
+
+
+/** Group: block7 registers */
+/** Type of rd_key3_datan register
+ *  Represents rd_key3_datan
+ */
+typedef union {
+    struct {
+        /** key3_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key3.
+         */
+        uint32_t key3_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_datan_reg_t;
+
+
+/** Group: block8 registers */
+/** Type of rd_key4_datan register
+ *  Represents rd_key4_datan
+ */
+typedef union {
+    struct {
+        /** key4_datan : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of key4.
+         */
+        uint32_t key4_datan:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_datan_reg_t;
+
+
+/** Group: block9 registers */
+/** Type of rd_sys_part2_data0 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the zeroth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the first 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the second 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the third 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fourth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the fifth 32-bit of second part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Represents rd_sys_part2_data
+ */
+typedef union {
+    struct {
+        /** usb_device_exchg_pins : RO; bitpos: [0]; default: 0;
+         *  Represents whether enable usb device exchange pins of D+ and D- or not.
+         *  1: enabled
+         *  0: disabled
+         */
+        uint32_t usb_device_exchg_pins:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+
+/** Group: block0 error report registers */
+/** Type of rd_repeat_data_err0 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  Represents the programming error of EFUSE_RD_DIS
+         */
+        uint32_t rd_dis_err:7;
+        uint32_t reserved_7:3;
+        /** dis_usb_jtag_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_JTAG
+         */
+        uint32_t dis_usb_jtag_err:1;
+        uint32_t reserved_11:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_FORCE_DOWNLOAD
+         */
+        uint32_t dis_force_download_err:1;
+        /** spi_download_mspi_dis_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_DOWNLOAD_MSPI_DIS
+         */
+        uint32_t spi_download_mspi_dis_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_TWAI
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  Represents the programming error of EFUSE_JTAG_SEL_ENABLE
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  Represents the programming error of EFUSE_SOFT_DIS_JTAG
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_PAD_JTAG
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        uint32_t reserved_21:2;
+        /** huk_gen_state_err : RO; bitpos: [27:23]; default: 0;
+         *  Represents the programming error of EFUSE_HUK_GEN_STATE
+         */
+        uint32_t huk_gen_state_err:5;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err0_reg_t;
+
+/** Type of rd_repeat_data_err1 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** km_rnd_switch_cycle_err : RO; bitpos: [0]; default: 0;
+         *  Represents the programming error of EFUSE_KM_RND_SWITCH_CYCLE
+         */
+        uint32_t km_rnd_switch_cycle_err:1;
+        uint32_t reserved_1:1;
+        /** km_disable_deploy_mode_err : RO; bitpos: [6:2]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DISABLE_DEPLOY_MODE
+         */
+        uint32_t km_disable_deploy_mode_err:5;
+        /** km_deploy_only_once_err : RO; bitpos: [11:7]; default: 0;
+         *  Represents the programming error of EFUSE_KM_DEPLOY_ONLY_ONCE
+         */
+        uint32_t km_deploy_only_once_err:5;
+        /** force_use_key_manager_key_err : RO; bitpos: [16:12]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_USE_KEY_MANAGER_KEY
+         */
+        uint32_t force_use_key_manager_key_err:5;
+        /** force_disable_sw_init_key_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_DISABLE_SW_INIT_KEY
+         */
+        uint32_t force_disable_sw_init_key_err:1;
+        /** km_xts_key_length_256_err : RO; bitpos: [18]; default: 0;
+         *  Represents the programming error of EFUSE_KM_XTS_KEY_LENGTH_256
+         */
+        uint32_t km_xts_key_length_256_err:1;
+        /** wdt_delay_sel_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_WDT_DELAY_SEL
+         */
+        uint32_t wdt_delay_sel_err:1;
+        /** dis_sm_crypt_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_SM_CRYPT
+         */
+        uint32_t dis_sm_crypt_err:1;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [23:21]; default: 0;
+         *  Represents the programming error of EFUSE_SPI_BOOT_CRYPT_CNT
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [24]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE0
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE1
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_KEY_REVOKE2
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err1_reg_t;
+
+/** Type of rd_repeat_data_err2 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** key_purpose_0_err : RO; bitpos: [4:0]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_0
+         */
+        uint32_t key_purpose_0_err:5;
+        /** key_purpose_1_err : RO; bitpos: [9:5]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_1
+         */
+        uint32_t key_purpose_1_err:5;
+        /** key_purpose_2_err : RO; bitpos: [14:10]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_2
+         */
+        uint32_t key_purpose_2_err:5;
+        /** key_purpose_3_err : RO; bitpos: [19:15]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_3
+         */
+        uint32_t key_purpose_3_err:5;
+        /** key_purpose_4_err : RO; bitpos: [24:20]; default: 0;
+         *  Represents the programming error of EFUSE_KEY_PURPOSE_4
+         */
+        uint32_t key_purpose_4_err:5;
+        /** ecc_force_const_time_err : RO; bitpos: [25]; default: 0;
+         *  Represents the programming error of EFUSE_ECC_FORCE_CONST_TIME
+         */
+        uint32_t ecc_force_const_time_err:1;
+        /** ecdsa_disable_soft_k_err : RO; bitpos: [26]; default: 0;
+         *  Represents the programming error of EFUSE_ECDSA_DISABLE_SOFT_K
+         */
+        uint32_t ecdsa_disable_soft_k_err:1;
+        /** sec_dpa_level_err : RO; bitpos: [28:27]; default: 0;
+         *  Represents the programming error of EFUSE_SEC_DPA_LEVEL
+         */
+        uint32_t sec_dpa_level_err:2;
+        /** xts_dpa_clk_enable_err : RO; bitpos: [29]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_CLK_ENABLE
+         */
+        uint32_t xts_dpa_clk_enable_err:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err2_reg_t;
+
+/** Type of rd_repeat_data_err3 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** xts_dpa_pseudo_level_err : RO; bitpos: [1:0]; default: 0;
+         *  Represents the programming error of EFUSE_XTS_DPA_PSEUDO_LEVEL
+         */
+        uint32_t xts_dpa_pseudo_level_err:2;
+        /** secure_boot_en_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_EN
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        uint32_t reserved_4:1;
+        /** flash_type_err : RO; bitpos: [5]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TYPE
+         */
+        uint32_t flash_type_err:1;
+        uint32_t reserved_6:3;
+        /** dis_usb_otg_download_mode_err : RO; bitpos: [9]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_OTG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_otg_download_mode_err:1;
+        uint32_t reserved_10:2;
+        /** flash_tpuw_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_FLASH_TPUW
+         */
+        uint32_t flash_tpuw_err:4;
+        /** dis_download_mode_err : RO; bitpos: [16]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DOWNLOAD_MODE
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_direct_boot_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_DIRECT_BOOT
+         */
+        uint32_t dis_direct_boot_err:1;
+        /** dis_usb_serial_jtag_rom_print_err : RO; bitpos: [18]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
+         */
+        uint32_t dis_usb_serial_jtag_rom_print_err:1;
+        /** lock_km_key_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_LOCK_KM_KEY
+         */
+        uint32_t lock_km_key_err:1;
+        /** dis_usb_serial_jtag_download_mode_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+         */
+        uint32_t dis_usb_serial_jtag_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_ENABLE_SECURITY_DOWNLOAD
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [23:22]; default: 0;
+         *  Represents the programming error of EFUSE_UART_PRINT_CONTROL
+         */
+        uint32_t uart_print_control_err:2;
+        /** force_send_resume_err : RO; bitpos: [24]; default: 0;
+         *  Represents the programming error of EFUSE_FORCE_SEND_RESUME
+         */
+        uint32_t force_send_resume_err:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err3_reg_t;
+
+/** Type of rd_repeat_data_err4 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** secure_version_err : RO; bitpos: [15:0]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_VERSION
+         */
+        uint32_t secure_version_err:16;
+        /** secure_boot_disable_fast_wake_err : RO; bitpos: [16]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE
+         */
+        uint32_t secure_boot_disable_fast_wake_err:1;
+        /** hys_en_pad_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_HYS_EN_PAD
+         */
+        uint32_t hys_en_pad_err:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err4_reg_t;
+
+/** Type of rd_repeat_data_err5 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** dcdc_vset_en_err : RO; bitpos: [2]; default: 0;
+         *  Represents the programming error of EFUSE_DCDC_VSET_EN
+         */
+        uint32_t dcdc_vset_en_err:1;
+        /** dis_wdt_err : RO; bitpos: [3]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_WDT
+         */
+        uint32_t dis_wdt_err:1;
+        /** dis_swd_err : RO; bitpos: [4]; default: 0;
+         *  Represents the programming error of EFUSE_DIS_SWD
+         */
+        uint32_t dis_swd_err:1;
+        uint32_t reserved_5:6;
+        /** secure_boot_sha384_en_err : RO; bitpos: [11]; default: 0;
+         *  Represents the programming error of EFUSE_SECURE_BOOT_SHA384_EN
+         */
+        uint32_t secure_boot_sha384_en_err:1;
+        /** bootloader_anti_rollback_secure_version_err : RO; bitpos: [15:12]; default: 0;
+         *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION
+         */
+        uint32_t bootloader_anti_rollback_secure_version_err:4;
+        /** bootloader_anti_rollback_en_err : RO; bitpos: [16]; default: 0;
+         *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN
+         */
+        uint32_t bootloader_anti_rollback_en_err:1;
+        /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [17]; default: 0;
+         *  Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM
+         */
+        uint32_t bootloader_anti_rollback_update_in_rom_err:1;
+        /** recovery_bootloader_flash_sector_err : RO; bitpos: [29:18]; default: 0;
+         *  Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR
+         */
+        uint32_t recovery_bootloader_flash_sector_err:12;
+        /** rma_ena_err : RO; bitpos: [31:30]; default: 0;
+         *  Represents the programming error of EFUSE_RMA_ENA
+         */
+        uint32_t rma_ena_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err5_reg_t;
+
+/** Type of rd_repeat_data_err6 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** rma_session_counter_err : RO; bitpos: [2:0]; default: 0;
+         *  Represents the programming error of EFUSE_RMA_SESSION_COUNTER
+         */
+        uint32_t rma_session_counter_err:3;
+        /** rma_nonce_ena_err : RO; bitpos: [4:3]; default: 0;
+         *  Represents the programming error of EFUSE_RMA_NONCE_ENA
+         */
+        uint32_t rma_nonce_ena_err:2;
+        /** rma_chip_info_source_err : RO; bitpos: [5]; default: 0;
+         *  Represents the programming error of EFUSE_RMA_CHIP_INFO_SOURCE
+         */
+        uint32_t rma_chip_info_source_err:1;
+        /** rma_disable_fast_vef_err : RO; bitpos: [6]; default: 0;
+         *  Represents the programming error of EFUSE_RMA_DISABLE_FAST_VEF
+         */
+        uint32_t rma_disable_fast_vef_err:1;
+        /** pvt_0_glitch_en_err : RO; bitpos: [7]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_0_GLITCH_EN
+         */
+        uint32_t pvt_0_glitch_en_err:1;
+        /** pvt_0_glitch_mode_err : RO; bitpos: [9:8]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_0_GLITCH_MODE
+         */
+        uint32_t pvt_0_glitch_mode_err:2;
+        /** pvt_1_glitch_en_err : RO; bitpos: [10]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_1_GLITCH_EN
+         */
+        uint32_t pvt_1_glitch_en_err:1;
+        /** pvt_1_glitch_mode_err : RO; bitpos: [12:11]; default: 0;
+         *  Represents the programming error of EFUSE_PVT_1_GLITCH_MODE
+         */
+        uint32_t pvt_1_glitch_mode_err:2;
+        /** pmu_flash_power_sel_err : RO; bitpos: [13]; default: 0;
+         *  Represents the programming error of EFUSE_PMU_FLASH_POWER_SEL
+         */
+        uint32_t pmu_flash_power_sel_err:1;
+        /** pmu_flash_power_sel_en_err : RO; bitpos: [14]; default: 0;
+         *  Represents the programming error of EFUSE_PMU_FLASH_POWER_SEL_EN
+         */
+        uint32_t pmu_flash_power_sel_en_err:1;
+        /** power_glitch_en_err : RO; bitpos: [18:15]; default: 0;
+         *  Represents the programming error of EFUSE_POWER_GLITCH_EN
+         */
+        uint32_t power_glitch_en_err:4;
+        /** ena_xts_shadow_err : RO; bitpos: [19]; default: 0;
+         *  Represents the programming error of EFUSE_ENA_XTS_SHADOW
+         */
+        uint32_t ena_xts_shadow_err:1;
+        /** ena_spi_boot_crypt_scrambler_err : RO; bitpos: [20]; default: 0;
+         *  Represents the programming error of EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER
+         */
+        uint32_t ena_spi_boot_crypt_scrambler_err:1;
+        /** re_enable_jtag_source_err : RO; bitpos: [21]; default: 0;
+         *  Represents the programming error of EFUSE_RE_ENABLE_JTAG_SOURCE
+         */
+        uint32_t re_enable_jtag_source_err:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err6_reg_t;
+
+/** Type of rd_repeat_data_err7 register
+ *  Represents rd_repeat_data_err
+ */
+typedef union {
+    struct {
+        /** repeat7_rsvd_err : RO; bitpos: [15:0]; default: 0;
+         *  Represents the programming error of EFUSE_REPEAT7_RSVD
+         */
+        uint32_t repeat7_rsvd_err:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data_err7_reg_t;
+
+
+/** Group: RS block error report registers */
+/** Type of rd_rs_data_err0 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_mac_sys
+         */
+        uint32_t rd_mac_sys_err_num:3;
+        /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_mac_sys is reliable
+         *  1: Means that programming rd_mac_sys failed and the number of error bytes is over 6.
+         */
+        uint32_t rd_mac_sys_fail:1;
+        /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part1_data
+         */
+        uint32_t rd_sys_part1_data_err_num:3;
+        /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part1_data is reliable
+         *  1: Means that programming rd_sys_part1_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part1_data_fail:1;
+        /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_usr_data
+         */
+        uint32_t rd_usr_data_err_num:3;
+        /** rd_usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_usr_data is reliable
+         *  1: Means that programming rd_usr_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_usr_data_fail:1;
+        /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key0_data
+         */
+        uint32_t rd_key0_data_err_num:3;
+        /** rd_key0_data_fail : RO; bitpos: [15]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key0_data is reliable
+         *  1: Means that programming rd_key0_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key0_data_fail:1;
+        /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key1_data
+         */
+        uint32_t rd_key1_data_err_num:3;
+        /** rd_key1_data_fail : RO; bitpos: [19]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key1_data is reliable
+         *  1: Means that programming rd_key1_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key1_data_fail:1;
+        /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key2_data
+         */
+        uint32_t rd_key2_data_err_num:3;
+        /** rd_key2_data_fail : RO; bitpos: [23]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key2_data is reliable
+         *  1: Means that programming rd_key2_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key2_data_fail:1;
+        /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key3_data
+         */
+        uint32_t rd_key3_data_err_num:3;
+        /** rd_key3_data_fail : RO; bitpos: [27]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key3_data is reliable
+         *  1: Means that programming rd_key3_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key3_data_fail:1;
+        /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_key4_data
+         */
+        uint32_t rd_key4_data_err_num:3;
+        /** rd_key4_data_fail : RO; bitpos: [31]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_key4_data is reliable
+         *  1: Means that programming rd_key4_data failed and the number of error bytes is over
+         *  6.
+         */
+        uint32_t rd_key4_data_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err0_reg_t;
+
+/** Type of rd_rs_data_err1 register
+ *  Represents rd_rs_data_err
+ */
+typedef union {
+    struct {
+        /** rd_sys_part2_data_err_num : RO; bitpos: [2:0]; default: 0;
+         *  Represents the error number of registers.
+         *  The value of this signal means the number of error bytes in rd_sys_part2_data
+         */
+        uint32_t rd_sys_part2_data_err_num:3;
+        /** rd_sys_part2_data_fail : RO; bitpos: [3]; default: 0;
+         *  Represents error status of register.
+         *  0: Means no failure and that the data of rd_sys_part2_data is reliable
+         *  1: Means that programming rd_sys_part2_data failed and the number of error bytes is
+         *  over 6.
+         */
+        uint32_t rd_sys_part2_data_fail:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} efuse_rd_rs_data_err1_reg_t;
+
+
+/** Group: EFUSE Version Register */
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38834580;
+         *  Represents eFuse version. Date:2025-09-19 19:52:16,
+         *  ScriptRev:abfb97fc087287a4eacd02828cb3ca8dd0d0e75f
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+/** Group: EFUSE Clock Registers */
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to force power down eFuse SRAM.
+         *  1: Force
+         *  0: No effect
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Configures whether to force activate clock signal of eFuse SRAM.
+         *  1: Force activate
+         *  0: No effect
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Configures whether to force power up eFuse SRAM.
+         *  1: Force
+         *  0: No effect
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether to force enable eFuse register configuration clock signal.
+         *  1: Force
+         *  0: The clock is enabled only during the reading and writing of registers
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+
+/** Group: EFUSE Configure Registers */
+/** Type of conf register
+ *  eFuse operation mode configuration register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  Configures operation command type.
+         *  0x5A5A: Program operation command
+         *  0x5AA5: Read operation command
+         *  Other values: No effect
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 24;
+         *  Configures the division factor of the rising clock of the programming voltage
+         *  (ramp-up slew rate be slower than 2.5V/250us, and ramp-up 10mV for one-cycle, so
+         *  reg_dac_clk_div > fclk).
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Configures clock cycles for programming voltage to rise (VDDQ 2.5V, ramp-up 10mV
+         *  for one-cycle). Measurement unit: a clock cycle divided by EFUSE_DAC_CLK_DIV.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Configures whether to reduce the power supply of programming voltage.
+         *  0: Not reduce
+         *  1: Reduce
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        /** thr_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the read hold time (>=14ns). Measurement unit: One cycle of the eFuse
+         *  core clock.
+         */
+        uint32_t thr_a:8;
+        /** trd : R/W; bitpos: [15:8]; default: 2;
+         *  Configures the read time (>=52ns). Measurement unit: One cycle of the eFuse core
+         *  clock.
+         */
+        uint32_t trd:8;
+        /** tsur_a : R/W; bitpos: [23:16]; default: 1;
+         *  Configures the read setup time (>=14ns). Measurement unit: One cycle of the eFuse
+         *  core clock.
+         */
+        uint32_t tsur_a:8;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 27;
+         *  Configures the waiting time of reading eFuse memory. Measurement unit: One cycle of
+         *  the eFuse core clock.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** tsup_a : R/W; bitpos: [7:0]; default: 1;
+         *  Configures the programming setup time (>14ns). Measurement unit: One cycle of the
+         *  eFuse core clock.
+         */
+        uint32_t tsup_a:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 14746;
+         *  Configures the power up time for VDDQ (>reg_dac_clk_div*reg_dac_clk_div).
+         *  Measurement unit: One cycle of the eFuse core clock.
+         */
+        uint32_t pwr_on_num:16;
+        /** thp_a : R/W; bitpos: [31:24]; default: 1;
+         *  Configures the programming hold time (>=11ns). Measurement unit: One cycle of the
+         *  eFuse core clock.
+         */
+        uint32_t thp_a:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 480;
+         *  Configures the power outage time for VDDQ. Measurement unit: One cycle of the eFuse
+         *  core clock.
+         */
+        uint32_t pwr_off_num:16;
+        /** tpgm : R/W; bitpos: [31:16]; default: 240;
+         *  Configures the active programming time (>10us). Measurement unit: One cycle of the
+         *  eFuse core clock.
+         */
+        uint32_t tpgm:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of wr_tim_conf0_rs_bypass register
+ *  Configurarion register0 of eFuse programming time parameters and rs bypass
+ *  operation.
+ */
+typedef union {
+    struct {
+        /** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
+         *  Configures whether to bypass the Reed-Solomon (RS) correction step.
+         *  0: Not bypass
+         *  1: Bypass
+         */
+        uint32_t bypass_rs_correction:1;
+        /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
+         *  Configures which block number to bypass the Reed-Solomon (RS) correction step.
+         */
+        uint32_t bypass_rs_blk_num:11;
+        /** update : WT; bitpos: [12]; default: 0;
+         *  Configures whether to update multi-bit register signals.
+         *  1: Update
+         *  0: No effect
+         */
+        uint32_t update:1;
+        /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
+         *  Configures the inactive programming time. Measurement unit: One cycle of the eFuse
+         *  core clock.
+         */
+        uint32_t tpgm_inactive:8;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf0_rs_bypass_reg_t;
+
+
+/** Group: EFUSE ECDSA Configure Registers */
+/** Type of ecdsa register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** cfg_ecdsa_p192_blk : R/W; bitpos: [3:0]; default: 0;
+         *  Configures which block to use for ECDSA P192 key output.
+         */
+        uint32_t cfg_ecdsa_p192_blk:4;
+        /** cfg_ecdsa_p256_blk : R/W; bitpos: [7:4]; default: 0;
+         *  Configures which block to use for ECDSA P256 key output.
+         */
+        uint32_t cfg_ecdsa_p256_blk:4;
+        /** cfg_ecdsa_p384_l_blk : R/W; bitpos: [11:8]; default: 0;
+         *  Configures which block to use for ECDSA P384 key low part output.
+         */
+        uint32_t cfg_ecdsa_p384_l_blk:4;
+        /** cfg_ecdsa_p384_h_blk : R/W; bitpos: [15:12]; default: 0;
+         *  Configures which block to use for ECDSA P256 key high part output.
+         */
+        uint32_t cfg_ecdsa_p384_h_blk:4;
+        /** cur_ecdsa_p192_blk : RO; bitpos: [19:16]; default: 0;
+         *  Represents which block is used for ECDSA P192 key output.
+         */
+        uint32_t cur_ecdsa_p192_blk:4;
+        /** cur_ecdsa_p256_blk : RO; bitpos: [23:20]; default: 0;
+         *  Represents which block is used for ECDSA P256 key output.
+         */
+        uint32_t cur_ecdsa_p256_blk:4;
+        /** cur_ecdsa_p384_l_blk : RO; bitpos: [27:24]; default: 0;
+         *  Represents which block is used for ECDSA P384 key low part output.
+         */
+        uint32_t cur_ecdsa_p384_l_blk:4;
+        /** cur_ecdsa_p384_h_blk : RO; bitpos: [31:28]; default: 0;
+         *  Represents which block is used for ECDSA P384 key high part output.
+         */
+        uint32_t cur_ecdsa_p384_h_blk:4;
+    };
+    uint32_t val;
+} efuse_ecdsa_reg_t;
+
+
+/** Group: EFUSE Status Registers */
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Represents the state of the eFuse state machine.
+         *  0: Reset state, the initial state after power-up
+         *  1: Idle state
+         *  Other values: Non-idle state
+         */
+        uint32_t state:4;
+        uint32_t reserved_4:6;
+        /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
+         *  Represents the number of block valid bit.
+         */
+        uint32_t blk0_valid_bit_cnt:10;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+
+/** Group: EFUSE Command Registers */
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether to send read commands.
+         *  1: Send
+         *  0: No effect
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0;
+         *  Configures whether to send programming commands.
+         *  1: Send
+         *  0: No effect
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  Configures the serial number of the block to be programmed. Value 0-10 corresponds
+         *  to block number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of EFUSE_READ_DONE_INT.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  The raw interrupt status of EFUSE_PGM_DONE_INT.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of EFUSE_READ_DONE_INT.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of EFUSE_PGM_DONE_INT.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable EFUSE_READ_DONE_INT.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable EFUSE_PGM_DONE_INT.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear EFUSE_READ_DONE_INT.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear EFUSE_PGM_DONE_INT.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_datan_reg_t pgm_datan[8];
+    volatile efuse_pgm_check_valuen_reg_t pgm_check_valuen[3];
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_repeat_data5_reg_t rd_repeat_data5;
+    volatile efuse_rd_repeat_data6_reg_t rd_repeat_data6;
+    volatile efuse_rd_repeat_data7_reg_t rd_repeat_data7;
+    volatile efuse_rd_mac_sys0_reg_t rd_mac_sys0;
+    volatile efuse_rd_mac_sys1_reg_t rd_mac_sys1;
+    uint32_t reserved_058;
+    volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
+    volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
+    volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
+    volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
+    volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
+    volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
+    volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
+    volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];
+    volatile efuse_rd_key3_datan_reg_t rd_key3_datan[8];
+    volatile efuse_rd_key4_datan_reg_t rd_key4_datan[8];
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    uint32_t reserved_164;
+    volatile efuse_rd_repeat_data_err0_reg_t rd_repeat_data_err0;
+    volatile efuse_rd_repeat_data_err1_reg_t rd_repeat_data_err1;
+    volatile efuse_rd_repeat_data_err2_reg_t rd_repeat_data_err2;
+    volatile efuse_rd_repeat_data_err3_reg_t rd_repeat_data_err3;
+    volatile efuse_rd_repeat_data_err4_reg_t rd_repeat_data_err4;
+    volatile efuse_rd_repeat_data_err5_reg_t rd_repeat_data_err5;
+    volatile efuse_rd_repeat_data_err6_reg_t rd_repeat_data_err6;
+    volatile efuse_rd_repeat_data_err7_reg_t rd_repeat_data_err7;
+    volatile efuse_rd_rs_data_err0_reg_t rd_rs_data_err0;
+    volatile efuse_rd_rs_data_err1_reg_t rd_rs_data_err1;
+    volatile efuse_date_reg_t date;
+    uint32_t reserved_194[13];
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_ecdsa_reg_t ecdsa;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    volatile efuse_wr_tim_conf0_rs_bypass_reg_t wr_tim_conf0_rs_bypass;
+} efuse_dev_t;
+
+extern efuse_dev_t EFUSE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gmac_reg.h b/components/soc/esp32s31/register/soc/gmac_reg.h
new file mode 100644
index 00000000000..cc6e0ad014a
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gmac_reg.h
@@ -0,0 +1,7239 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GMAC_REGISTER0_MACCONFIGURATIONREGISTER_REG register
+ *  This is the operation mode register for the MAC
+ */
+#define GMAC_REGISTER0_MACCONFIGURATIONREGISTER_REG (DR_REG_GMAC_BASE + 0x0)
+/** GMAC_PRELEN : R/W; bitpos: [1:0]; default: 0;
+ *  Preamble Length for Transmit frames These bits control the number of preamble bytes
+ *  that are added to the beginning of every Transmit frame The preamble reduction
+ *  occurs only when the MAC is operating in the fullduplex mode 2'b00: 7 bytes of
+ *  preamble 2'b01: 5 bytes of preamble 2'b10: 3 bytes of preamble 2'b11: Reserved
+ */
+#define GMAC_PRELEN    0x00000003U
+#define GMAC_PRELEN_M  (GMAC_PRELEN_V << GMAC_PRELEN_S)
+#define GMAC_PRELEN_V  0x00000003U
+#define GMAC_PRELEN_S  0
+/** GMAC_RE : R/W; bitpos: [2]; default: 0;
+ *  Receiver Enable When this bit is set, the receiver state machine of the MAC is
+ *  enabled for receiving frames from the GMII or MII When this bit is reset, the MAC
+ *  receive state machine is disabled after the completion of the reception of the
+ *  current frame, and does not receive any further frames from the GMII or MII
+ */
+#define GMAC_RE    (BIT(2))
+#define GMAC_RE_M  (GMAC_RE_V << GMAC_RE_S)
+#define GMAC_RE_V  0x00000001U
+#define GMAC_RE_S  2
+/** GMAC_TE : R/W; bitpos: [3]; default: 0;
+ *  Transmitter Enable When this bit is set, the transmit state machine of the MAC is
+ *  enabled for transmission on the GMII or MII When this bit is reset, the MAC
+ *  transmit state machine is disabled after the completion of the transmission of the
+ *  current frame, and does not transmit any further frames
+ */
+#define GMAC_TE    (BIT(3))
+#define GMAC_TE_M  (GMAC_TE_V << GMAC_TE_S)
+#define GMAC_TE_V  0x00000001U
+#define GMAC_TE_S  3
+/** GMAC_DC : R/W; bitpos: [4]; default: 0;
+ *  Deferral Check When this bit is set, the deferral check function is enabled in the
+ *  MAC The MAC issues a Frame Abort status, along with the excessive deferral error
+ *  bit set in the transmit frame status, when the transmit state machine is deferred
+ *  for more than 24,288 bit times in the 10 or 100 Mbps mode If the MAC is configured
+ *  for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps
+ *  mode, the threshold for deferral is 155,680 bits times Deferral begins when the
+ *  transmitter is ready to transmit, but it is prevented because of an active carrier
+ *  sense signal _CRS_ on GMII or MII The defer time is not cumulative For example, if
+ *  the transmitter defers for 10,000 bit times because the CRS signal is active and
+ *  then the CRS signal becomes inactive, the transmitter transmits and collision
+ *  happens Because of collision, the transmitter needs to back off and then defer
+ *  again after back off completion In such a scenario, the deferral timer is reset to
+ *  0 and it is restarted When this bit is reset, the deferral check function is
+ *  disabled and the MAC defers until the CRS signal goes inactive This bit is
+ *  applicable only in the halfduplex mode and is reserved _RO_ in the fullduplexonly
+ *  configuration
+ */
+#define GMAC_DC    (BIT(4))
+#define GMAC_DC_M  (GMAC_DC_V << GMAC_DC_S)
+#define GMAC_DC_V  0x00000001U
+#define GMAC_DC_S  4
+/** GMAC_BL : R/W; bitpos: [6:5]; default: 0;
+ *  BackOff Limit The BackOff limit determines the random integer number _r_ of slot
+ *  time delays _4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps_ for
+ *  which the MAC waits before rescheduling a transmission attempt during retries after
+ *  a collision This bit is applicable only in the halfduplex mode and is reserved _RO_
+ *  in the fullduplexonly configuration 00: k= min _n, 10_ 01: k = min _n, 8_ 10: k =
+ *  min _n, 4_ 11: k = min _n, 1_ where n = retransmission attempt The random integer r
+ *  takes the value in the range 0 ≤ r < 2k
+ */
+#define GMAC_BL    0x00000003U
+#define GMAC_BL_M  (GMAC_BL_V << GMAC_BL_S)
+#define GMAC_BL_V  0x00000003U
+#define GMAC_BL_S  5
+/** GMAC_ACS : R/W; bitpos: [7]; default: 0;
+ *  Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS
+ *  field on the incoming frames only if the value of the length field is less than
+ *  1,536 bytes All received frames with length field greater than or equal to 1,536
+ *  bytes are passed to the application without stripping the Pad or FCS field When
+ *  this bit is reset, the MAC passes all incoming frames, without modifying them, to
+ *  the Host Note: For information about how the settings of Bit 25 _CST_ and this bit
+ *  impact the frame length, see Table 632
+ */
+#define GMAC_ACS    (BIT(7))
+#define GMAC_ACS_M  (GMAC_ACS_V << GMAC_ACS_S)
+#define GMAC_ACS_V  0x00000001U
+#define GMAC_ACS_S  7
+/** GMAC_LUD : R/W; bitpos: [8]; default: 0;
+ *  Link Up or Down This bit indicates whether the link is up or down during the
+ *  transmission of configuration in the RGMII, SGMII, or SMII interface: 0: Link Down
+ *  1: Link Up This bit is reserved _RO with default value_ and is enabled when the
+ *  RGMII, SGMII, or SMII interface is enabled during core configuration
+ */
+#define GMAC_LUD    (BIT(8))
+#define GMAC_LUD_M  (GMAC_LUD_V << GMAC_LUD_S)
+#define GMAC_LUD_V  0x00000001U
+#define GMAC_LUD_S  8
+/** GMAC_DR : R/W; bitpos: [9]; default: 0;
+ *  Disable Retry When this bit is set, the MAC attempts only one transmission When a
+ *  collision occurs on the GMII or MII interface, the MAC ignores the current frame
+ *  transmission and reports a Frame Abort with excessive collision error in the
+ *  transmit frame status When this bit is reset, the MAC attempts retries based on the
+ *  settings of the BL field _Bits [6:5]_ This bit is applicable only in the halfduplex
+ *  mode and is reserved _RO with default value_ in the fullduplexonly configuration
+ */
+#define GMAC_DR    (BIT(9))
+#define GMAC_DR_M  (GMAC_DR_V << GMAC_DR_S)
+#define GMAC_DR_V  0x00000001U
+#define GMAC_DR_S  9
+/** GMAC_IPC : R/W; bitpos: [10]; default: 0;
+ *  Checksum Offload When this bit is set, the MAC calculates the 16bit one’s
+ *  complement of the one’s complement sum of all received Ethernet frame payloads It
+ *  also checks whether the IPv4 Header checksum _assumed to be bytes 2526 or 2930
+ *  _VLAN tagged_ of the received Ethernet frame_ is correct for the received frame and
+ *  gives the status in the receive status word The MAC also appends the 16bit checksum
+ *  calculated for the IP header datagram payload _bytes after the IPv4 header_ and
+ *  appends it to the Ethernet frame transferred to the application _when Type 2 COE is
+ *  deselected_ When this bit is reset, this function is disabled When Type 2 COE is
+ *  selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or
+ *  IPv6 TCP, UDP, or ICMP payload checksum checking When this bit is reset, the COE
+ *  function in the receiver is disabled and the corresponding PCE and IP HCE status
+ *  bits _see Table 310 on page 138_ are always cleared If the IP Checksum Offload
+ *  feature is not enabled during core configuration, this bit is reserved _RO with
+ *  default value_
+ */
+#define GMAC_IPC    (BIT(10))
+#define GMAC_IPC_M  (GMAC_IPC_V << GMAC_IPC_S)
+#define GMAC_IPC_V  0x00000001U
+#define GMAC_IPC_S  10
+/** GMAC_DM : R/W; bitpos: [11]; default: 0;
+ *  Duplex Mode When this bit is set, the MAC operates in the fullduplex mode where it
+ *  can transmit and receive simultaneously This bit is RO with default value of 1'b1
+ *  in the fullduplexonly configuration
+ */
+#define GMAC_DM    (BIT(11))
+#define GMAC_DM_M  (GMAC_DM_V << GMAC_DM_S)
+#define GMAC_DM_V  0x00000001U
+#define GMAC_DM_S  11
+/** GMAC_LM : R/W; bitpos: [12]; default: 0;
+ *  Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII
+ *  or MII The _G_MII Receive clock input _clk_rx_i_ is required for the loopback to
+ *  work properly, because the Transmit clock is not loopedback internally
+ */
+#define GMAC_LM    (BIT(12))
+#define GMAC_LM_M  (GMAC_LM_V << GMAC_LM_S)
+#define GMAC_LM_V  0x00000001U
+#define GMAC_LM_S  12
+/** GMAC_DO : R/W; bitpos: [13]; default: 0;
+ *  Disable Receive Own When this bit is set, the MAC disables the reception of frames
+ *  when the phy_txen_o is asserted in the halfduplex mode When this bit is reset, the
+ *  MAC receives all packets that are given by the PHY while transmitting This bit is
+ *  not applicable if the MAC is operating in the fullduplex mode This bit is reserved
+ *  _RO with default value_ if the MAC is configured for the fullduplexonly operation
+ */
+#define GMAC_DO    (BIT(13))
+#define GMAC_DO_M  (GMAC_DO_V << GMAC_DO_S)
+#define GMAC_DO_V  0x00000001U
+#define GMAC_DO_S  13
+/** GMAC_FES : R/W; bitpos: [14]; default: 0;
+ *  Speed This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII
+ *  interface: 0: 10 Mbps 1: 100 Mbps This bit is reserved _RO_ by default and is
+ *  enabled only when the parameter SPEED_SELECT = Enabled This bit generates link
+ *  speed encoding when Bit 24 _TC_ is set in the RGMII, SMII, or SGMII mode This bit
+ *  is always enabled for RGMII, SGMII, SMII, or RevMII interface In configurations
+ *  with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output
+ *  signal _mac_speed_o[0]_ to reflect the value of this bit in the mac_speed_o signal
+ *  In configurations with RMII, MII, or GMII interface, you can optionally drive this
+ *  bit as an output signal _mac_speed_o[0]_ to reflect its value in the mac_speed_o
+ *  signal
+ */
+#define GMAC_FES    (BIT(14))
+#define GMAC_FES_M  (GMAC_FES_V << GMAC_FES_S)
+#define GMAC_FES_V  0x00000001U
+#define GMAC_FES_S  14
+/** GMAC_PS : R/W; bitpos: [15]; default: 0;
+ *  Port Select This bit selects the Ethernet line speed 0: For 1000 Mbps operations 1:
+ *  For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with
+ *  FES bit, selects the exact line speed In the 10/100 Mbpsonly _always 1_ or 1000
+ *  Mbpsonly _always 0_ configurations, this bit is readonly with the appropriate value
+ *  In default 10/100/1000 Mbps configuration, this bit is R_W The mac_portselect_o or
+ *  mac_speed_o[1] signal reflects the value of this bit
+ */
+#define GMAC_PS    (BIT(15))
+#define GMAC_PS_M  (GMAC_PS_V << GMAC_PS_S)
+#define GMAC_PS_V  0x00000001U
+#define GMAC_PS_S  15
+/** GMAC_DCRS : R/W; bitpos: [16]; default: 0;
+ *  Disable Carrier Sense During Transmission When set high, this bit makes the MAC
+ *  transmitter ignore the _G_MII CRS signal during frame transmission in the
+ *  halfduplex mode This request results in no errors generated because of Loss of
+ *  Carrier or No Carrier during such transmission When this bit is low, the MAC
+ *  transmitter generates such errors because of Carrier Sense and can even abort the
+ *  transmissions This bit is reserved _and RO_ in the fullduplexonly configurations
+ */
+#define GMAC_DCRS    (BIT(16))
+#define GMAC_DCRS_M  (GMAC_DCRS_V << GMAC_DCRS_S)
+#define GMAC_DCRS_V  0x00000001U
+#define GMAC_DCRS_S  16
+/** GMAC_IFG : R/W; bitpos: [19:17]; default: 0;
+ *  InterFrame Gap These bits control the minimum IFG between frames during
+ *  transmission 000: 96 bit times 001: 88 bit times 010: 80 bit times  111: 40 bit
+ *  times In the halfduplex mode, the minimum IFG can be configured only for 64 bit
+ *  times _IFG = 100_ Lower values are not considered In the 1000Mbps mode, the minimum
+ *  IFG supported is 64 bit times _and above_ in the GMACCORE configuration and 80 bit
+ *  times _and above_ in other configurations When a JAM pattern is being transmitted
+ *  because of backpressure activation, the MAC does not consider the minimum IFG
+ */
+#define GMAC_IFG    0x00000007U
+#define GMAC_IFG_M  (GMAC_IFG_V << GMAC_IFG_S)
+#define GMAC_IFG_V  0x00000007U
+#define GMAC_IFG_S  17
+/** GMAC_JE : R/W; bitpos: [20]; default: 0;
+ *  Jumbo Frame Enable When this bit is set, the MAC allows Jumbo frames of 9,018 bytes
+ *  _9,022 bytes for VLAN tagged frames_ without reporting a giant frame error in the
+ *  receive frame status
+ */
+#define GMAC_JE    (BIT(20))
+#define GMAC_JE_M  (GMAC_JE_V << GMAC_JE_S)
+#define GMAC_JE_V  0x00000001U
+#define GMAC_JE_S  20
+/** GMAC_BE : R/W; bitpos: [21]; default: 0;
+ *  Frame Burst Enable When this bit is set, the MAC allows frame bursting during
+ *  transmission in the GMII halfduplex mode This bit is reserved _and RO_ in the
+ *  10/100 Mbps only or fullduplexonly configurations
+ */
+#define GMAC_BE    (BIT(21))
+#define GMAC_BE_M  (GMAC_BE_V << GMAC_BE_S)
+#define GMAC_BE_V  0x00000001U
+#define GMAC_BE_S  21
+/** GMAC_JD : R/W; bitpos: [22]; default: 0;
+ *  Jabber Disable When this bit is set, the MAC disables the jabber timer on the
+ *  transmitter The MAC can transfer frames of up to 16,383 bytes When this bit is
+ *  reset, the MAC cuts off the transmitter if the application sends out more than
+ *  2,048 bytes of data _10,240 if JE is set high_ during transmission
+ */
+#define GMAC_JD    (BIT(22))
+#define GMAC_JD_M  (GMAC_JD_V << GMAC_JD_S)
+#define GMAC_JD_V  0x00000001U
+#define GMAC_JD_S  22
+/** GMAC_WD : R/W; bitpos: [23]; default: 0;
+ *  Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the
+ *  receiver The MAC can receive frames of up to 16,383 bytes When this bit is reset,
+ *  the MAC does not allow a receive frame which more than 2,048 bytes _10,240 if JE is
+ *  set high_ or the value programmed in Register 55 _Watchdog Timeout Register_ The
+ *  MAC cuts off any bytes received after the watchdog limit number of bytes
+ */
+#define GMAC_WD    (BIT(23))
+#define GMAC_WD_M  (GMAC_WD_V << GMAC_WD_S)
+#define GMAC_WD_V  0x00000001U
+#define GMAC_WD_S  23
+/** GMAC_TC : R/W; bitpos: [24]; default: 0;
+ *  Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the
+ *  transmission of duplex mode, link speed, and link up or down information to the PHY
+ *  in the RGMII, SMII, or SGMII port When this bit is reset, no such information is
+ *  driven to the PHY This bit is reserved _and RO_ if the RGMII, SMII, or SGMII PHY
+ *  port is not selected during core configuration The details of this feature are
+ *  explained in the following sections: “Reduced Gigabit Media Independent Interface”
+ *  on page 249 “Serial Media Independent Interface” on page 245 “Serial Gigabit Media
+ *  Independent Interface” on page 257
+ */
+#define GMAC_TC    (BIT(24))
+#define GMAC_TC_M  (GMAC_TC_V << GMAC_TC_S)
+#define GMAC_TC_V  0x00000001U
+#define GMAC_TC_S  24
+/** GMAC_CST : R/W; bitpos: [25]; default: 0;
+ *  CRC Stripping for Type Frames When this bit is set, the last 4 bytes _FCS_ of all
+ *  frames of Ether type _Length/Type field greater than or equal to 1,536_ are
+ *  stripped and dropped before forwarding the frame to the application This function
+ *  is not valid when the IP Checksum Engine _Type 1_ is enabled in the MAC receiver
+ *  This function is valid when Type 2 Checksum Offload Engine is enabled Note: For
+ *  information about how the settings of Bit 7 _ACS_ and this bit impact the frame
+ *  length, see Table 632
+ */
+#define GMAC_CST    (BIT(25))
+#define GMAC_CST_M  (GMAC_CST_V << GMAC_CST_S)
+#define GMAC_CST_V  0x00000001U
+#define GMAC_CST_S  25
+/** GMAC_SFTERR : R/W; bitpos: [26]; default: 0;
+ *  SMII Force Transmit Error When set, this bit indicates to the PHY to force a
+ *  transmit error in the SMII frame being transmitted This bit is reserved if the SMII
+ *  PHY port is not selected during core configuration
+ */
+#define GMAC_SFTERR    (BIT(26))
+#define GMAC_SFTERR_M  (GMAC_SFTERR_V << GMAC_SFTERR_S)
+#define GMAC_SFTERR_V  0x00000001U
+#define GMAC_SFTERR_S  26
+/** GMAC_TWOKPE : R/W; bitpos: [27]; default: 0;
+ *  IEEE 8023as Support for 2K Packets When set, the MAC considers all frames, with up
+ *  to 2,000 bytes length, as normal packets When Bit 20 _JE_ is not set, the MAC
+ *  considers all received frames of size more than 2K bytes as Giant frames When this
+ *  bit is reset and Bit 20 _JE_ is not set, the MAC considers all received frames of
+ *  size more than 1,518 bytes _1,522 bytes for tagged_ as Giant frames When Bit 20 is
+ *  set, setting this bit has no effect on Giant Frame status For more information
+ *  about how the setting of this bit and Bit 20 impact the Giant frame status, see
+ *  Table 631
+ */
+#define GMAC_TWOKPE    (BIT(27))
+#define GMAC_TWOKPE_M  (GMAC_TWOKPE_V << GMAC_TWOKPE_S)
+#define GMAC_TWOKPE_V  0x00000001U
+#define GMAC_TWOKPE_S  27
+/** GMAC_SARC : R/W; bitpos: [30:28]; default: 0;
+ *  Source Address Insertion or Replacement Control This field controls the source
+ *  address insertion or replacement for all transmitted frames Bit 30 specifies which
+ *  MAC Address register _0 or 1_ is used for source address insertion or replacement
+ *  based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and
+ *  ati_sa_ctrl_i control the SA field generation 2'b10: 	If Bit 30 is set to 0, the
+ *  MAC inserts the content of the MAC Address 0 registers _registers 16 and 17_ in the
+ *  SA field of all transmitted frames 	If Bit 30 is set to 1 and the Enable MAC
+ *  Address Register 1 option is selected during core configuration, the MAC inserts
+ *  the content of the MAC Address 1 registers _registers 18 and 19_ in the SA field of
+ *  all transmitted frames 2'b11: 	If Bit 30 is set to 0, the MAC replaces the content
+ *  of the MAC Address 0 registers _registers 16 and 17_ in the SA field of all
+ *  transmitted frames 	If Bit 30 is set to 1 and the Enable MAC Address Register 1
+ *  option is selected during core configuration, the MAC replaces the content of the
+ *  MAC Address 1 registers _registers 18 and 19_ in the SA field of all transmitted
+ *  frames Note: Changes to this field take effect only on the start of a frame If you
+ *  write this register field when a frame is being transmitted, only the subsequent
+ *  frame can use the updated value, that is, the current frame does not use the
+ *  updated value These bits are reserved and RO when the Enable SA, VLAN, and CRC
+ *  Insertion on TX feature is not selected during core configuration
+ */
+#define GMAC_SARC    0x00000007U
+#define GMAC_SARC_M  (GMAC_SARC_V << GMAC_SARC_S)
+#define GMAC_SARC_V  0x00000007U
+#define GMAC_SARC_S  28
+
+/** GMAC_REGISTER1_MACFRAMEFILTER_REG register
+ *  Contains the frame filtering controls
+ */
+#define GMAC_REGISTER1_MACFRAMEFILTER_REG (DR_REG_GMAC_BASE + 0x4)
+/** GMAC_PROMISCUOUS_MODE : R/W; bitpos: [0]; default: 0;
+ *  Promiscuous Mode When this bit is set, the Address Filter module passes all
+ *  incoming frames irrespective of the destination or source address The SA or DA
+ *  Filter Fails status bits of the Receive Status Word are always cleared when PR is
+ *  set
+ */
+#define GMAC_PROMISCUOUS_MODE    (BIT(0))
+#define GMAC_PROMISCUOUS_MODE_M  (GMAC_PROMISCUOUS_MODE_V << GMAC_PROMISCUOUS_MODE_S)
+#define GMAC_PROMISCUOUS_MODE_V  0x00000001U
+#define GMAC_PROMISCUOUS_MODE_S  0
+/** GMAC_HUC : R/W; bitpos: [1]; default: 0;
+ *  Hash Unicast When set, the MAC performs destination address filtering of unicast
+ *  frames according to the hash table When reset, the MAC performs a perfect
+ *  destination address filtering for unicast frames, that is, it compares the DA field
+ *  with the values programmed in DA registers If Hash Filter is not selected during
+ *  core configuration, this bit is reserved _and RO_
+ */
+#define GMAC_HUC    (BIT(1))
+#define GMAC_HUC_M  (GMAC_HUC_V << GMAC_HUC_S)
+#define GMAC_HUC_V  0x00000001U
+#define GMAC_HUC_S  1
+/** GMAC_HMC : R/W; bitpos: [2]; default: 0;
+ *  Hash Multicast When set, the MAC performs destination address filtering of received
+ *  multicast frames according to the hash table When reset, the MAC performs a perfect
+ *  destination address filtering for multicast frames, that is, it compares the DA
+ *  field with the values programmed in DA registers If Hash Filter is not selected
+ *  during core configuration, this bit is reserved _and RO_
+ */
+#define GMAC_HMC    (BIT(2))
+#define GMAC_HMC_M  (GMAC_HMC_V << GMAC_HMC_S)
+#define GMAC_HMC_V  0x00000001U
+#define GMAC_HMC_S  2
+/** GMAC_DAIF : R/W; bitpos: [3]; default: 0;
+ *  DA Inverse Filtering When this bit is set, the Address Check block operates in
+ *  inverse filtering mode for the DA address comparison for both unicast and multicast
+ *  frames When reset, normal filtering of frames is performed
+ */
+#define GMAC_DAIF    (BIT(3))
+#define GMAC_DAIF_M  (GMAC_DAIF_V << GMAC_DAIF_S)
+#define GMAC_DAIF_V  0x00000001U
+#define GMAC_DAIF_S  3
+/** GMAC_PM : R/W; bitpos: [4]; default: 0;
+ *  Pass All Multicast When set, this bit indicates that all received frames with a
+ *  multicast destination address _first bit in the destination address field is '1'_
+ *  are passed When reset, filtering of multicast frame depends on HMC bit
+ */
+#define GMAC_PM    (BIT(4))
+#define GMAC_PM_M  (GMAC_PM_V << GMAC_PM_S)
+#define GMAC_PM_V  0x00000001U
+#define GMAC_PM_S  4
+/** GMAC_DBF : R/W; bitpos: [5]; default: 0;
+ *  Disable Broadcast Frames When this bit is set, the AFM module blocks all incoming
+ *  broadcast frames In addition, it overrides all other filter settings When this bit
+ *  is reset, the AFM module passes all received broadcast frames
+ */
+#define GMAC_DBF    (BIT(5))
+#define GMAC_DBF_M  (GMAC_DBF_V << GMAC_DBF_S)
+#define GMAC_DBF_V  0x00000001U
+#define GMAC_DBF_S  5
+/** GMAC_PCF : R/W; bitpos: [7:6]; default: 0;
+ *  Pass Control Frames These bits control the forwarding of all control frames
+ *  _including unicast and multicast Pause frames_ 00: MAC filters all control frames
+ *  from reaching the application 01: MAC forwards all control frames except Pause
+ *  frames to application even if they fail the Address filter 10: MAC forwards all
+ *  control frames to application even if they fail the Address Filter 11: MAC forwards
+ *  control frames that pass the Address Filter The following conditions should be true
+ *  for the Pause frames processing: Condition 1 : The MAC is in the fullduplex mode
+ *  and flow control is enabled by setting Bit 2 _RFE_ of Register 6 _Flow Control
+ *  Register_ to 1 Condition 2 : The destination address _DA_ of the received frame
+ *  matches the special multicast address or the MAC Address 0 when Bit 3 _UP_ of the
+ *  Register 6 _Flow Control Register_ is set Condition 3: The Type field of the
+ *  received frame is 0x8808 and the OPCODE field is 0x0001 Note: This field should be
+ *  set to 01 only when the Condition 1 is true, that is, the MAC is programmed to
+ *  operate in the fullduplex mode and the RFE bit is enabled Otherwise, the Pause
+ *  frame filtering may be inconsistent When Condition 1 is false, the Pause frames are
+ *  considered as generic control frames Therefore, to pass all control frames
+ *  _including Pause frames_ when the fullduplex mode and flow control is not enabled,
+ *  you should set the PCF field to 10 or 11 _as required by the application_
+ */
+#define GMAC_PCF    0x00000003U
+#define GMAC_PCF_M  (GMAC_PCF_V << GMAC_PCF_S)
+#define GMAC_PCF_V  0x00000003U
+#define GMAC_PCF_S  6
+/** GMAC_SAIF : R/W; bitpos: [8]; default: 0;
+ *  SA Inverse Filtering When this bit is set, the Address Check block operates in
+ *  inverse filtering mode for the SA address comparison The frames whose SA matches
+ *  the SA registers are marked as failing the SA Address filter When this bit is
+ *  reset, frames whose SA does not match the SA registers are marked as failing the SA
+ *  Address filter
+ */
+#define GMAC_SAIF    (BIT(8))
+#define GMAC_SAIF_M  (GMAC_SAIF_V << GMAC_SAIF_S)
+#define GMAC_SAIF_V  0x00000001U
+#define GMAC_SAIF_S  8
+/** GMAC_SAF : R/W; bitpos: [9]; default: 0;
+ *  Source Address Filter Enable When this bit is set, the MAC compares the SA field of
+ *  the received frames with the values programmed in the enabled SA registers If the
+ *  comparison fails, the MAC drops the frame When this bit is reset, the MAC forwards
+ *  the received frame to the application with updated SAF bit of the Rx Status
+ *  depending on the SA address comparison Note: According to the IEEE specification,
+ *  Bit 47 of the SA is reserved and set to 0 However, in DWC_gmac, the MAC compares
+ *  all 48 bits The software driver should take this into consideration while
+ *  programming the MAC address registers for SA
+ */
+#define GMAC_SAF    (BIT(9))
+#define GMAC_SAF_M  (GMAC_SAF_V << GMAC_SAF_S)
+#define GMAC_SAF_V  0x00000001U
+#define GMAC_SAF_S  9
+/** GMAC_HPF : R/W; bitpos: [10]; default: 0;
+ *  Hash or Perfect Filter When this bit is set, it configures the address filter to
+ *  pass a frame if it matches either the perfect filtering or the hash filtering as
+ *  set by the HMC or HUC bits When this bit is low and the HUC or HMC bit is set, the
+ *  frame is passed only if it matches the Hash filter This bit is reserved _and RO_ if
+ *  the Hash filter is not selected during core configuration
+ */
+#define GMAC_HPF    (BIT(10))
+#define GMAC_HPF_M  (GMAC_HPF_V << GMAC_HPF_S)
+#define GMAC_HPF_V  0x00000001U
+#define GMAC_HPF_S  10
+/** GMAC_VTFE : R/W; bitpos: [16]; default: 0;
+ *  VLAN Tag Filter Enable When set, this bit enables the MAC to drop VLAN tagged
+ *  frames that do not match the VLAN Tag comparison When reset, the MAC forwards all
+ *  frames irrespective of the match status of the VLAN Tag
+ */
+#define GMAC_VTFE    (BIT(16))
+#define GMAC_VTFE_M  (GMAC_VTFE_V << GMAC_VTFE_S)
+#define GMAC_VTFE_V  0x00000001U
+#define GMAC_VTFE_S  16
+/** GMAC_IPFE : R/W; bitpos: [20]; default: 0;
+ *  Layer 3 and Layer 4 Filter Enable When set, this bit enables the MAC to drop frames
+ *  that do not match the enabled Layer 3 and Layer 4 filters If Layer 3 or Layer 4
+ *  filters are not enabled for matching, this bit does not have any effect When reset,
+ *  the MAC forwards all frames irrespective of the match status of the Layer 3 and
+ *  Layer 4 fields If the Layer 3 and Layer 4 Filtering feature is not selected during
+ *  core configuration, this bit is reserved _RO with default value_
+ */
+#define GMAC_IPFE    (BIT(20))
+#define GMAC_IPFE_M  (GMAC_IPFE_V << GMAC_IPFE_S)
+#define GMAC_IPFE_V  0x00000001U
+#define GMAC_IPFE_S  20
+/** GMAC_DNTU : R/W; bitpos: [21]; default: 0;
+ *  Drop nonTCP/UDP over IP Frames When set, this bit enables the MAC to drop the
+ *  nonTCP or UDP over IP frames The MAC forward only those frames that are processed
+ *  by the Layer 4 filter When reset, this bit enables the MAC to forward all nonTCP or
+ *  UDP over IP frames If the Layer 3 and Layer 4 Filtering feature is not selected
+ *  during core configuration, this bit is reserved _RO with default value_
+ */
+#define GMAC_DNTU    (BIT(21))
+#define GMAC_DNTU_M  (GMAC_DNTU_V << GMAC_DNTU_S)
+#define GMAC_DNTU_V  0x00000001U
+#define GMAC_DNTU_S  21
+/** GMAC_RA : R/W; bitpos: [31]; default: 0;
+ *  Receive All When this bit is set, the MAC Receiver module passes all received
+ *  frames, irrespective of whether they pass the address filter or not, to the
+ *  Application The result of the SA or DA filtering is updated _pass or fail_ in the
+ *  corresponding bits in the Receive Status Word When this bit is reset, the Receiver
+ *  module passes only those frames to the Application that pass the SA or DA address
+ *  filter
+ */
+#define GMAC_RA    (BIT(31))
+#define GMAC_RA_M  (GMAC_RA_V << GMAC_RA_S)
+#define GMAC_RA_V  0x00000001U
+#define GMAC_RA_S  31
+
+/** GMAC_REGISTER2_HASHTABLEHIGHREGISTER_REG register
+ *  Contains the higher 32 bits of the Multicast Hash table This register is present
+ *  only when you select the 64bit Hash filter function in coreConsultant _See Table 79_
+ */
+#define GMAC_REGISTER2_HASHTABLEHIGHREGISTER_REG (DR_REG_GMAC_BASE + 0x8)
+/** GMAC_HTH : R/W; bitpos: [31:0]; default: 0;
+ *  Hash Table High This field contains the upper 32 bits of the Hash table
+ */
+#define GMAC_HTH    0xFFFFFFFFU
+#define GMAC_HTH_M  (GMAC_HTH_V << GMAC_HTH_S)
+#define GMAC_HTH_V  0xFFFFFFFFU
+#define GMAC_HTH_S  0
+
+/** GMAC_REGISTER3_HASHTABLELOWREGISTER_REG register
+ *  Contains the lower 32 bits of the Multicast Hash table This register is present
+ *  only when you select the Hash filter function in coreConsultant _See Table 79_
+ */
+#define GMAC_REGISTER3_HASHTABLELOWREGISTER_REG (DR_REG_GMAC_BASE + 0xc)
+/** GMAC_HTL : R/W; bitpos: [31:0]; default: 0;
+ *  Hash Table Low This field contains the lower 32 bits of the Hash table
+ */
+#define GMAC_HTL    0xFFFFFFFFU
+#define GMAC_HTL_M  (GMAC_HTL_V << GMAC_HTL_S)
+#define GMAC_HTL_V  0xFFFFFFFFU
+#define GMAC_HTL_S  0
+
+/** GMAC_REGISTER4_GMIIADDRESSREGISTER_REG register
+ *  Controls the management cycles to an external PHY This register is present only
+ *  when you select the Station Management _MDIO_ feature in coreConsultant _See Table
+ *  726_
+ */
+#define GMAC_REGISTER4_GMIIADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x10)
+/** GMAC_GB : R/W1S; bitpos: [0]; default: 0;
+ *  GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5
+ *  During a PHY or RevMII register access, the software sets this bit to 1’b1 to
+ *  indicate that a Read or Write access is in progress Register 5 is invalid until
+ *  this bit is cleared by the MAC Therefore, Register 5 _GMII Data_ should be kept
+ *  valid until the MAC clears this bit during a PHY Write operation Similarly for a
+ *  read operation, the contents of Register 5 are not valid until this bit is cleared
+ *  The subsequent read or write operation should happen only after the previous
+ *  operation is complete Because there is no acknowledgment from the PHY to MAC after
+ *  a read or write operation is completed, there is no change in the functionality of
+ *  this bit even when the PHY is not present
+ */
+#define GMAC_GB    (BIT(0))
+#define GMAC_GB_M  (GMAC_GB_V << GMAC_GB_S)
+#define GMAC_GB_V  0x00000001U
+#define GMAC_GB_S  0
+/** GMAC_GW : R/W; bitpos: [1]; default: 0;
+ *  GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write
+ *  operation using the GMII Data register If this bit is not set, it indicates that
+ *  this is a Read operation, that is, placing the data in the GMII Data register
+ */
+#define GMAC_GW    (BIT(1))
+#define GMAC_GW_M  (GMAC_GW_V << GMAC_GW_S)
+#define GMAC_GW_V  0x00000001U
+#define GMAC_GW_S  1
+/** GMAC_CR : R/W; bitpos: [5:2]; default: 0;
+ *  CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC
+ *  clock according to the CSR clock frequency used in your design The CSR clock
+ *  corresponding to different GMAC configurations is given in Table 92 on page 564 The
+ *  suggested range of CSR clock frequency applicable for each value _when Bit[5] = 0_
+ *  ensures that the MDC clock is approximately between the frequency range 10 MHz25
+ *  MHz 0000: The CSR clock frequency is 60100 MHz and the MDC clock frequency is CSR
+ *  clock/42 0001: The CSR clock frequency is 100150 MHz and the MDC clock frequency is
+ *  CSR clock/62 0010: The CSR clock frequency is 2035 MHz and the MDC clock frequency
+ *  is CSR clock/16 0011: The CSR clock frequency is 3560 MHz and the MDC clock
+ *  frequency is CSR clock/26 0100: The CSR clock frequency is 150250 MHz and the MDC
+ *  clock frequency is CSR clock/102 0101: The CSR clock frequency is 250300 MHz and
+ *  the MDC clock is CSR clock/124 0110, 0111: Reserved When Bit 5 is set, you can
+ *  achieve higher frequency of the MDC clock than the frequency limit of 25 MHz
+ *  _specified in the IEEE Std 8023_ and program a clock divider of lower value For
+ *  example, when CSR clock is of 100 MHz frequency and you program these bits as 1010,
+ *  then the resultant MDC clock is of 125 MHz which is outside the limit of IEEE 8023
+ *  specified range Program the following values only if the interfacing chips support
+ *  faster MDC clocks 1000: CSR clock/4 1001: CSR clock/6 1010: CSR clock/8 1011: CSR
+ *  clock/10 1100: CSR clock/12 1101: CSR clock/14 1110: CSR clock/16 1111: CSR
+ *  clock/18 These bits are not used for accessing RevMII These bits are readonly if
+ *  the RevMII interface is selected as single PHY interface
+ */
+#define GMAC_CR    0x0000000FU
+#define GMAC_CR_M  (GMAC_CR_V << GMAC_CR_S)
+#define GMAC_CR_V  0x0000000FU
+#define GMAC_CR_S  2
+/** GMAC_GR : R/W; bitpos: [10:6]; default: 0;
+ *  GMII Register These bits select the desired GMII register in the selected PHY
+ *  device For RevMII, these bits select the desired CSR register in the RevMII
+ *  Registers set
+ */
+#define GMAC_GR    0x0000001FU
+#define GMAC_GR_M  (GMAC_GR_V << GMAC_GR_S)
+#define GMAC_GR_V  0x0000001FU
+#define GMAC_GR_S  6
+/** GMAC_PA : R/W; bitpos: [15:11]; default: 0;
+ *  Physical Layer Address This field indicates which of the 32 possible PHY devices
+ *  are being accessed For RevMII, this field gives the PHY Address of the RevMII module
+ */
+#define GMAC_PA    0x0000001FU
+#define GMAC_PA_M  (GMAC_PA_V << GMAC_PA_S)
+#define GMAC_PA_V  0x0000001FU
+#define GMAC_PA_S  11
+
+/** GMAC_REGISTER5_GMIIDATAREGISTER_REG register
+ *  Contains the data to be written to or read from the PHY register This register is
+ *  present only when you select the Station Management _MDIO_ feature in
+ *  coreConsultant _See Table 726_
+ */
+#define GMAC_REGISTER5_GMIIDATAREGISTER_REG (DR_REG_GMAC_BASE + 0x14)
+/** GMAC_GD : R/W; bitpos: [15:0]; default: 0;
+ *  GMII Data This field contains the 16bit data value read from the PHY or RevMII
+ *  after a Management Read operation or the 16bit data value to be written to the PHY
+ *  or RevMII before a Management Write operation
+ */
+#define GMAC_GD    0x0000FFFFU
+#define GMAC_GD_M  (GMAC_GD_V << GMAC_GD_S)
+#define GMAC_GD_V  0x0000FFFFU
+#define GMAC_GD_S  0
+
+/** GMAC_REGISTER6_FLOWCONTROLREGISTER_REG register
+ *  Controls the generation of control frames
+ */
+#define GMAC_REGISTER6_FLOWCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x18)
+/** GMAC_FCB_BPA : R/W1S; bitpos: [0]; default: 0;
+ *  Flow Control Busy or Backpressure Activate This bit initiates a Pause frame in the
+ *  fullduplex mode and activates the backpressure function in the halfduplex mode if
+ *  the TFE bit is set In the fullduplex mode, this bit should be read as 1'b0 before
+ *  writing to the Flow Control register To initiate a Pause frame, the Application
+ *  must set this bit to 1'b1 During a transfer of the Control Frame, this bit
+ *  continues to be set to signify that a frame transmission is in progress After the
+ *  completion of Pause frame transmission, the MAC resets this bit to 1'b0 The Flow
+ *  Control register should not be written to until this bit is cleared In the
+ *  halfduplex mode, when this bit is set _and TFE is set_, then backpressure is
+ *  asserted by the MAC During backpressure, when the MAC receives a new frame, the
+ *  transmitter starts sending a JAM pattern resulting in a collision This control
+ *  register bit is logically ORed with the mti_flowctrl_i input signal for the
+ *  backpressure function When the MAC is configured for the fullduplex mode, the BPA
+ *  is automatically disabled
+ */
+#define GMAC_FCB_BPA    (BIT(0))
+#define GMAC_FCB_BPA_M  (GMAC_FCB_BPA_V << GMAC_FCB_BPA_S)
+#define GMAC_FCB_BPA_V  0x00000001U
+#define GMAC_FCB_BPA_S  0
+/** GMAC_TFE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Flow Control Enable In the fullduplex mode, when this bit is set, the MAC
+ *  enables the flow control operation to transmit Pause frames When this bit is reset,
+ *  the flow control operation in the MAC is disabled, and the MAC does not transmit
+ *  any Pause frames In the halfduplex mode, when this bit is set, the MAC enables the
+ *  backpressure operation When this bit is reset, the backpressure feature is disabled
+ */
+#define GMAC_TFE    (BIT(1))
+#define GMAC_TFE_M  (GMAC_TFE_V << GMAC_TFE_S)
+#define GMAC_TFE_V  0x00000001U
+#define GMAC_TFE_S  1
+/** GMAC_RECEIVE_FLOW_CTRL_E : R/W; bitpos: [2]; default: 0;
+ *  Receive Flow Control Enable When this bit is set, the MAC decodes the received
+ *  Pause frame and disables its transmitter for a specified _Pause_ time When this bit
+ *  is reset, the decode function of the Pause frame is disabled
+ */
+#define GMAC_RECEIVE_FLOW_CTRL_E    (BIT(2))
+#define GMAC_RECEIVE_FLOW_CTRL_E_M  (GMAC_RECEIVE_FLOW_CTRL_E_V << GMAC_RECEIVE_FLOW_CTRL_E_S)
+#define GMAC_RECEIVE_FLOW_CTRL_E_V  0x00000001U
+#define GMAC_RECEIVE_FLOW_CTRL_E_S  2
+/** GMAC_UP : R/W; bitpos: [3]; default: 0;
+ *  Unicast Pause Frame Detect A pause frame is processed when it has the unique
+ *  multicast address specified in the IEEE Std 8023 When this bit is set, the MAC can
+ *  also detect Pause frames with unicast address of the station This unicast address
+ *  should be as specified in the MAC Address0 High Register and MAC Address0 Low
+ *  Register When this bit is reset, the MAC only detects Pause frames with unique
+ *  multicast address Note: The MAC does not process a Pause frame if the multicast
+ *  address of received frame is different from the unique multicast address
+ */
+#define GMAC_UP    (BIT(3))
+#define GMAC_UP_M  (GMAC_UP_V << GMAC_UP_S)
+#define GMAC_UP_V  0x00000001U
+#define GMAC_UP_S  3
+/** GMAC_PLT : R/W; bitpos: [5:4]; default: 0;
+ *  Pause Low Threshold This field configures the threshold of the Pause timer at which
+ *  the input flow control signal mti_flowctrl_i _or sbd_flowctrl_i_ is checked for
+ *  automatic retransmission of the Pause frame The threshold values should be always
+ *  less than the Pause Time configured in Bits[31:16] For example, if PT = 100H _256
+ *  slottimes_, and PLT = 01, then a second Pause frame is automatically transmitted if
+ *  the mti_flowctrl_i signal is asserted at 228 _256  28_ slot times after the first
+ *  Pause frame is transmitted The following list provides the threshold values for
+ *  different values: 00: The threshold is Pause time minus 4 slot times _PT  4 slot
+ *  times_ 01: The threshold is Pause time minus 28 slot times _PT  28 slot times_ 10:
+ *  The threshold is Pause time minus 144 slot times _PT  144 slot times_ 11: The
+ *  threshold is Pause time minus 256 slot times _PT  256 slot times_ The slot time is
+ *  defined as the time taken to transmit 512 bits _64 bytes_ on the GMII or MII
+ *  interface
+ */
+#define GMAC_PLT    0x00000003U
+#define GMAC_PLT_M  (GMAC_PLT_V << GMAC_PLT_S)
+#define GMAC_PLT_V  0x00000003U
+#define GMAC_PLT_S  4
+/** GMAC_DZPQ : R/W; bitpos: [7]; default: 0;
+ *  Disable ZeroQuanta Pause When this bit is set, it disables the automatic generation
+ *  of the ZeroQuanta Pause frames on the deassertion of the flowcontrol signal from
+ *  the FIFO layer _MTL or external sideband flow control signal
+ *  sbd_flowctrl_i/mti_flowctrl_i_ When this bit is reset, normal operation with
+ *  automatic ZeroQuanta Pause frame generation is enabled
+ */
+#define GMAC_DZPQ    (BIT(7))
+#define GMAC_DZPQ_M  (GMAC_DZPQ_V << GMAC_DZPQ_S)
+#define GMAC_DZPQ_V  0x00000001U
+#define GMAC_DZPQ_S  7
+/** GMAC_PT : R/W; bitpos: [31:16]; default: 0;
+ *  Pause Time This field holds the value to be used in the Pause Time field in the
+ *  transmit control frame If the Pause Time bits is configured to be
+ *  doublesynchronized to the _G_MII clock domain, then consecutive writes to this
+ *  register should be performed only after at least four clock cycles in the
+ *  destination clock domain
+ */
+#define GMAC_PT    0x0000FFFFU
+#define GMAC_PT_M  (GMAC_PT_V << GMAC_PT_S)
+#define GMAC_PT_V  0x0000FFFFU
+#define GMAC_PT_S  16
+
+/** GMAC_REGISTER7_VLANTAGREGISTER_REG register
+ *  Identifies IEEE 8021Q VLAN type frames
+ */
+#define GMAC_REGISTER7_VLANTAGREGISTER_REG (DR_REG_GMAC_BASE + 0x1c)
+/** GMAC_VL : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Tag Identifier for Receive Frames This field contains the 8021Q VLAN tag to
+ *  identify the VLAN frames and is compared to the 15th and 16th bytes of the frames
+ *  being received for VLAN frames The following list describes the bits of this field:
+ *  Bits [15:13]: User Priority Bit 12: Canonical Format Indicator _CFI_ or Drop
+ *  Eligible Indicator _DEI_ Bits[11:0]: VLAN tag’s VLAN Identifier _VID_ field When
+ *  the ETV bit is set, only the VID _Bits[11:0]_ is used for comparison If VL
+ *  _VL[11:0] if ETV is set_ is all zeros, the MAC does not check the fifteenth and
+ *  16th bytes for VLAN tag comparison, and declares all frames with a Type field value
+ *  of 0x8100 or 0x88a8 as VLAN frames
+ */
+#define GMAC_VL    0x0000FFFFU
+#define GMAC_VL_M  (GMAC_VL_V << GMAC_VL_S)
+#define GMAC_VL_V  0x0000FFFFU
+#define GMAC_VL_S  0
+/** GMAC_ETV : R/W; bitpos: [16]; default: 0;
+ *  Enable 12-Bit VLAN Tag Comparison
+ */
+#define GMAC_ETV    (BIT(16))
+#define GMAC_ETV_M  (GMAC_ETV_V << GMAC_ETV_S)
+#define GMAC_ETV_V  0x00000001U
+#define GMAC_ETV_S  16
+/** GMAC_VTIM : R/W; bitpos: [17]; default: 0;
+ *  VLAN Tag Inverse Match Enable When set, this bit enables the VLAN Tag inverse
+ *  matching The frames that do not have matching VLAN Tag are marked as matched When
+ *  reset, this bit enables the VLAN Tag perfect matching The frames with matched VLAN
+ *  Tag are marked as matched
+ */
+#define GMAC_VTIM    (BIT(17))
+#define GMAC_VTIM_M  (GMAC_VTIM_V << GMAC_VTIM_S)
+#define GMAC_VTIM_V  0x00000001U
+#define GMAC_VTIM_S  17
+/** GMAC_ESVL : R/W; bitpos: [18]; default: 0;
+ *  Enable SVLAN When this bit is set, the MAC transmitter and receiver also consider
+ *  the SVLAN _Type = 0x88A8_ frames as valid VLAN tagged frames
+ */
+#define GMAC_ESVL    (BIT(18))
+#define GMAC_ESVL_M  (GMAC_ESVL_V << GMAC_ESVL_S)
+#define GMAC_ESVL_V  0x00000001U
+#define GMAC_ESVL_S  18
+/** GMAC_VTHM : R/W; bitpos: [19]; default: 0;
+ *  VLAN Tag Hash Table Match Enable When set, the most significant four bits of the
+ *  VLAN tag’s CRC are used to index the content of Register 354 _VLAN Hash Table
+ *  Register_ A value of 1 in the VLAN Hash Table register, corresponding to the index,
+ *  indicates that the frame matched the VLAN hash table When Bit 16 _ETV_ is set, the
+ *  CRC of the 12bit VLAN Identifier _VID_ is used for comparison whereas when ETV is
+ *  reset, the CRC of the 16bit VLAN tag is used for comparison When reset, the VLAN
+ *  Hash Match operation is not performed If the VLAN Hash feature is not enabled
+ *  during core configuration, this bit is reserved _RO with default value_
+ */
+#define GMAC_VTHM    (BIT(19))
+#define GMAC_VTHM_M  (GMAC_VTHM_V << GMAC_VTHM_S)
+#define GMAC_VTHM_V  0x00000001U
+#define GMAC_VTHM_S  19
+
+/** GMAC_REGISTER8_VERSIONREGISTER_REG register
+ *  Identifies the version of the Core
+ */
+#define GMAC_REGISTER8_VERSIONREGISTER_REG (DR_REG_GMAC_BASE + 0x20)
+/** GMAC_SNPSVER : RO; bitpos: [7:0]; default: 55;
+ *  Synopsysdefined Version _37_
+ */
+#define GMAC_SNPSVER    0x000000FFU
+#define GMAC_SNPSVER_M  (GMAC_SNPSVER_V << GMAC_SNPSVER_S)
+#define GMAC_SNPSVER_V  0x000000FFU
+#define GMAC_SNPSVER_S  0
+/** GMAC_USERVER : RO; bitpos: [15:8]; default: 0;
+ *  Userdefined Version _configured with coreConsultant_
+ */
+#define GMAC_USERVER    0x000000FFU
+#define GMAC_USERVER_M  (GMAC_USERVER_V << GMAC_USERVER_S)
+#define GMAC_USERVER_V  0x000000FFU
+#define GMAC_USERVER_S  8
+
+/** GMAC_REGISTER9_DEBUGREGISTER_REG register
+ *  Gives the status of various internal blocks for debugging
+ */
+#define GMAC_REGISTER9_DEBUGREGISTER_REG (DR_REG_GMAC_BASE + 0x24)
+/** GMAC_RPESTS : RO; bitpos: [0]; default: 0;
+ *  MAC GMII or MII Receive Protocol Engine Status When high, this bit indicates that
+ *  the MAC GMII or MII receive protocol engine is actively receiving data and not in
+ *  IDLE state
+ */
+#define GMAC_RPESTS    (BIT(0))
+#define GMAC_RPESTS_M  (GMAC_RPESTS_V << GMAC_RPESTS_S)
+#define GMAC_RPESTS_V  0x00000001U
+#define GMAC_RPESTS_S  0
+/** GMAC_RFCFCSTS : RO; bitpos: [2:1]; default: 0;
+ *  MAC Receive Frame FIFO Controller Status When high, this field indicates the active
+ *  state of the small FIFO Read and Write controllers of the MAC Receive Frame
+ *  Controller Module RFCFCSTS[1] represents the status of small FIFO Read controller
+ *  RFCFCSTS[0] represents the status of small FIFO Write controller
+ */
+#define GMAC_RFCFCSTS    0x00000003U
+#define GMAC_RFCFCSTS_M  (GMAC_RFCFCSTS_V << GMAC_RFCFCSTS_S)
+#define GMAC_RFCFCSTS_V  0x00000003U
+#define GMAC_RFCFCSTS_S  1
+/** GMAC_RWCSTS : RO; bitpos: [4]; default: 0;
+ *  MTL Rx FIFO Write Controller Active Status When high, this bit indicates that the
+ *  MTL Rx FIFO Write Controller is active and is transferring a received frame to the
+ *  FIFO
+ */
+#define GMAC_RWCSTS    (BIT(4))
+#define GMAC_RWCSTS_M  (GMAC_RWCSTS_V << GMAC_RWCSTS_S)
+#define GMAC_RWCSTS_V  0x00000001U
+#define GMAC_RWCSTS_S  4
+/** GMAC_RRCSTS : RO; bitpos: [6:5]; default: 0;
+ *  MTL RxFIFO Read Controller State This field gives the state of the Rx FIFO read
+ *  Controller: 00: IDLE state 01: Reading frame data 10: Reading frame status _or
+ *  timestamp_ 11: Flushing the frame data and status
+ */
+#define GMAC_RRCSTS    0x00000003U
+#define GMAC_RRCSTS_M  (GMAC_RRCSTS_V << GMAC_RRCSTS_S)
+#define GMAC_RRCSTS_V  0x00000003U
+#define GMAC_RRCSTS_S  5
+/** GMAC_RXFSTS : RO; bitpos: [9:8]; default: 0;
+ *  MTL RxFIFO FillLevel Status This field gives the status of the filllevel of the Rx
+ *  FIFO: 00: Rx FIFO Empty 01: Rx FIFO filllevel below flowcontrol deactivate
+ *  threshold 10: Rx FIFO filllevel above flowcontrol activate threshold 11: Rx FIFO
+ *  Full
+ */
+#define GMAC_RXFSTS    0x00000003U
+#define GMAC_RXFSTS_M  (GMAC_RXFSTS_V << GMAC_RXFSTS_S)
+#define GMAC_RXFSTS_V  0x00000003U
+#define GMAC_RXFSTS_S  8
+/** GMAC_TPESTS : RO; bitpos: [16]; default: 0;
+ *  MAC GMII or MII Transmit Protocol Engine Status When high, this bit indicates that
+ *  the MAC GMII or MII transmit protocol engine is actively transmitting data and is
+ *  not in the IDLE state
+ */
+#define GMAC_TPESTS    (BIT(16))
+#define GMAC_TPESTS_M  (GMAC_TPESTS_V << GMAC_TPESTS_S)
+#define GMAC_TPESTS_V  0x00000001U
+#define GMAC_TPESTS_S  16
+/** GMAC_TFCSTS : RO; bitpos: [18:17]; default: 0;
+ *  MAC Transmit Frame Controller Status This field indicates the state of the MAC
+ *  Transmit Frame Controller module: 00: IDLE state 01: Waiting for status of previous
+ *  frame or IFG or backoff period to be over 10: Generating and transmitting a Pause
+ *  frame _in the fullduplex mode_ 11: Transferring input frame for transmission
+ */
+#define GMAC_TFCSTS    0x00000003U
+#define GMAC_TFCSTS_M  (GMAC_TFCSTS_V << GMAC_TFCSTS_S)
+#define GMAC_TFCSTS_V  0x00000003U
+#define GMAC_TFCSTS_S  17
+/** GMAC_TXPAUSED : RO; bitpos: [19]; default: 0;
+ *  MAC Transmitter in Pause When high, this bit indicates that the MAC transmitter is
+ *  in the Pause condition _in the fullduplexonly mode_ and hence does not schedule any
+ *  frame for transmission
+ */
+#define GMAC_TXPAUSED    (BIT(19))
+#define GMAC_TXPAUSED_M  (GMAC_TXPAUSED_V << GMAC_TXPAUSED_S)
+#define GMAC_TXPAUSED_V  0x00000001U
+#define GMAC_TXPAUSED_S  19
+/** GMAC_TRCSTS : RO; bitpos: [21:20]; default: 0;
+ *  MTL Tx FIFO Read Controller Status This field indicates the state of the Tx FIFO
+ *  Read Controller: 00: IDLE state 01: READ state _transferring data to the MAC
+ *  transmitter_ 10: Waiting for TxStatus from the MAC transmitter 11: Writing the
+ *  received TxStatus or flushing the Tx FIFO
+ */
+#define GMAC_TRCSTS    0x00000003U
+#define GMAC_TRCSTS_M  (GMAC_TRCSTS_V << GMAC_TRCSTS_S)
+#define GMAC_TRCSTS_V  0x00000003U
+#define GMAC_TRCSTS_S  20
+/** GMAC_TWCSTS : RO; bitpos: [22]; default: 0;
+ *  MTL Tx FIFO Write Controller Status When high, this bit indicates that the MTL Tx
+ *  FIFO Write Controller is active and is transferring data to the Tx FIFO
+ */
+#define GMAC_TWCSTS    (BIT(22))
+#define GMAC_TWCSTS_M  (GMAC_TWCSTS_V << GMAC_TWCSTS_S)
+#define GMAC_TWCSTS_V  0x00000001U
+#define GMAC_TWCSTS_S  22
+/** GMAC_TXFSTS : RO; bitpos: [24]; default: 0;
+ *  MTL Tx FIFO Not Empty Status When high, this bit indicates that the MTL Tx FIFO is
+ *  not empty and some data is left for transmission
+ */
+#define GMAC_TXFSTS    (BIT(24))
+#define GMAC_TXFSTS_M  (GMAC_TXFSTS_V << GMAC_TXFSTS_S)
+#define GMAC_TXFSTS_V  0x00000001U
+#define GMAC_TXFSTS_S  24
+/** GMAC_TXSTSFSTS : RO; bitpos: [25]; default: 0;
+ *  MTL TxStatus FIFO Full Status When high, this bit indicates that the MTL TxStatus
+ *  FIFO is full Therefore, the MTL cannot accept any more frames for transmission This
+ *  bit is reserved in the GMACAHB and GMACDMA configurations
+ */
+#define GMAC_TXSTSFSTS    (BIT(25))
+#define GMAC_TXSTSFSTS_M  (GMAC_TXSTSFSTS_V << GMAC_TXSTSFSTS_S)
+#define GMAC_TXSTSFSTS_V  0x00000001U
+#define GMAC_TXSTSFSTS_S  25
+
+/** GMAC_REGISTER10_REMOTEWAKEUPFRAMEFILTERREGISTER_REG register
+ *  Remote Wake-Up Frame Filter Register
+ */
+#define GMAC_REGISTER10_REMOTEWAKEUPFRAMEFILTERREGISTER_REG (DR_REG_GMAC_BASE + 0x28)
+/** GMAC_WKUPFRM_FILTER : R/W; bitpos: [31:0]; default: 0;
+ *  This is the address through which the application writes or reads the remote
+ *  wake-up frame filter registers.The reg_wkupfrm_filter register is a pointer to
+ *  eight reg_wkupfrm_filter registers.The reg_wkupfrm_filter register is loaded by
+ *  sequentially loading the eight register values.Eight sequential writes to this
+ *  address(0x0028)write all reg_wkupfrm_filter registers.Similarly, eight sequential
+ *  reads from this address(0x0028) read all reg_wkupfrm_filter registers.
+ *  This register is present only when you select the PMT module Remote Wake-Up feature
+ *  in coreConsultant.
+ */
+#define GMAC_WKUPFRM_FILTER    0xFFFFFFFFU
+#define GMAC_WKUPFRM_FILTER_M  (GMAC_WKUPFRM_FILTER_V << GMAC_WKUPFRM_FILTER_S)
+#define GMAC_WKUPFRM_FILTER_V  0xFFFFFFFFU
+#define GMAC_WKUPFRM_FILTER_S  0
+
+/** GMAC_REGISTER11_PMTCONTROLANDSTATUSREGISTER_REG register
+ *  PMT Control and Status Register. This register is present only when you select the
+ *  PMT module in coreConsultant.
+ */
+#define GMAC_REGISTER11_PMTCONTROLANDSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x2c)
+/** GMAC_PWRDWN : R/W1S; bitpos: [0]; default: 0;
+ *  Power Down
+ *  When set, the MAC receiver drops all received frames until it receives the expected
+ *  magic packet or remote wake-up frame. This bit is then self-cleared and the
+ *  power-down mode is disabled. The Software can also clear this bit before the
+ *  expected magic packet or remote wake-up frame is received. The frames, received by
+ *  MAC after this bit is cleared, are forwarded to the application. This bit must only
+ *  be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable
+ *  bit is set high.
+ */
+#define GMAC_PWRDWN    (BIT(0))
+#define GMAC_PWRDWN_M  (GMAC_PWRDWN_V << GMAC_PWRDWN_S)
+#define GMAC_PWRDWN_V  0x00000001U
+#define GMAC_PWRDWN_S  0
+/** GMAC_MGKPKTEN : R/W; bitpos: [1]; default: 0;
+ *  Magic Packet Enable
+ *  When set, enables generation of a power management event because of magic packet
+ *  reception.
+ */
+#define GMAC_MGKPKTEN    (BIT(1))
+#define GMAC_MGKPKTEN_M  (GMAC_MGKPKTEN_V << GMAC_MGKPKTEN_S)
+#define GMAC_MGKPKTEN_V  0x00000001U
+#define GMAC_MGKPKTEN_S  1
+/** GMAC_RWKPKTEN : R/W; bitpos: [2]; default: 0;
+ *  Remote Wake-Up Frame Enable
+ *  When set, enables generation of a power management event because of remote wake-up
+ *  frame reception.
+ */
+#define GMAC_RWKPKTEN    (BIT(2))
+#define GMAC_RWKPKTEN_M  (GMAC_RWKPKTEN_V << GMAC_RWKPKTEN_S)
+#define GMAC_RWKPKTEN_V  0x00000001U
+#define GMAC_RWKPKTEN_S  2
+/** GMAC_MGKPRCVD : R/W; bitpos: [5]; default: 0;
+ *  Magic Packet Received
+ *  When set,this bit indicates that the power management event is generated because of
+ *  the reception of a magic packet. This bit is cleared by Read into this register.
+ */
+#define GMAC_MGKPRCVD    (BIT(5))
+#define GMAC_MGKPRCVD_M  (GMAC_MGKPRCVD_V << GMAC_MGKPRCVD_S)
+#define GMAC_MGKPRCVD_V  0x00000001U
+#define GMAC_MGKPRCVD_S  5
+/** GMAC_RWKPRCVD : R/W; bitpos: [6]; default: 0;
+ *  Remote Wake-Up Frame Received
+ *  When set, this bit indicates the power management event is generated because of the
+ *  reception of a remote wake-up frame. This bit is cleared by a Read into this
+ *  register.
+ */
+#define GMAC_RWKPRCVD    (BIT(6))
+#define GMAC_RWKPRCVD_M  (GMAC_RWKPRCVD_V << GMAC_RWKPRCVD_S)
+#define GMAC_RWKPRCVD_V  0x00000001U
+#define GMAC_RWKPRCVD_S  6
+/** GMAC_GLBLUCAST : R/W; bitpos: [9]; default: 0;
+ *  Global Unicast.
+ *  When set, enables any unicast packet filtered by the MAX(DAF) address recognition
+ *  to be a remote wake-up frame.
+ */
+#define GMAC_GLBLUCAST    (BIT(9))
+#define GMAC_GLBLUCAST_M  (GMAC_GLBLUCAST_V << GMAC_GLBLUCAST_S)
+#define GMAC_GLBLUCAST_V  0x00000001U
+#define GMAC_GLBLUCAST_S  9
+/** GMAC_RWKPTR : RO; bitpos: [28:24]; default: 0;
+ *  Remote Wake-up FIFO Pointer.
+ *  This field gives the current value(0 to 31) of the Remote Wake-up Frame filter
+ *  register pointer. When the value of this pointer is erual to 7, 15, 23 or 31, the
+ *  contents of the Remote Wake-up Frame Filter Register are transferred to the
+ *  clk_rx_i domain when a write occurs to that register.
+ *  The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the
+ *  number of Remote Wakeup Filters selected during configuration.
+ */
+#define GMAC_RWKPTR    0x0000001FU
+#define GMAC_RWKPTR_M  (GMAC_RWKPTR_V << GMAC_RWKPTR_S)
+#define GMAC_RWKPTR_V  0x0000001FU
+#define GMAC_RWKPTR_S  24
+/** GMAC_RWKFILTRST : R/W1S; bitpos: [31]; default: 0;
+ *  Remote Wake-Up Frame Filter Register Pointer Reset.
+ *  When this bit is set, it resets the remote wake-up frame filter register pointer to
+ *  3'b000. It is automatically cleared after 1 clock cycle.
+ */
+#define GMAC_RWKFILTRST    (BIT(31))
+#define GMAC_RWKFILTRST_M  (GMAC_RWKFILTRST_V << GMAC_RWKFILTRST_S)
+#define GMAC_RWKFILTRST_V  0x00000001U
+#define GMAC_RWKFILTRST_S  31
+
+/** GMAC_REGISTER12_LPICONTROLANDSTATUSREGISTER_REG register
+ *  Controls the Low Power Idle _LPI_ operations and provides the LPI status of the
+ *  core This register is present only when you select the Energy Efficient Ethernet
+ *  feature in coreConsultant
+ */
+#define GMAC_REGISTER12_LPICONTROLANDSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x30)
+/** GMAC_TLPIEN : R/W; bitpos: [0]; default: 0;
+ *  Transmit LPI Entry When set, this bit indicates that the MAC Transmitter has
+ *  entered the LPI state because of the setting of the LPIEN bit This bit is cleared
+ *  by a read into this register
+ */
+#define GMAC_TLPIEN    (BIT(0))
+#define GMAC_TLPIEN_M  (GMAC_TLPIEN_V << GMAC_TLPIEN_S)
+#define GMAC_TLPIEN_V  0x00000001U
+#define GMAC_TLPIEN_S  0
+/** GMAC_TLPIEX : R/W; bitpos: [1]; default: 0;
+ *  Transmit LPI Exit When set, this bit indicates that the MAC transmitter has exited
+ *  the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has
+ *  expired This bit is cleared by a read into this register
+ */
+#define GMAC_TLPIEX    (BIT(1))
+#define GMAC_TLPIEX_M  (GMAC_TLPIEX_V << GMAC_TLPIEX_S)
+#define GMAC_TLPIEX_V  0x00000001U
+#define GMAC_TLPIEX_S  1
+/** GMAC_RLPIEN : R/W; bitpos: [2]; default: 0;
+ *  Receive LPI Entry When set, this bit indicates that the MAC Receiver has received
+ *  an LPI pattern and entered the LPI state This bit is cleared by a read into this
+ *  register Note: This bit may not get set if the MAC stops receiving the LPI pattern
+ *  for a very short duration, such as, less than 3 clock cycles of CSR clock
+ */
+#define GMAC_RLPIEN    (BIT(2))
+#define GMAC_RLPIEN_M  (GMAC_RLPIEN_V << GMAC_RLPIEN_S)
+#define GMAC_RLPIEN_V  0x00000001U
+#define GMAC_RLPIEN_S  2
+/** GMAC_RLPIEX : R/W; bitpos: [3]; default: 0;
+ *  Receive LPI Exit When set, this bit indicates that the MAC Receiver has stopped
+ *  receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and
+ *  resumed the normal reception This bit is cleared by a read into this register Note:
+ *  This bit may not get set if the MAC stops receiving the LPI pattern for a very
+ *  short duration, such as, less than 3 clock cycles of CSR clock
+ */
+#define GMAC_RLPIEX    (BIT(3))
+#define GMAC_RLPIEX_M  (GMAC_RLPIEX_V << GMAC_RLPIEX_S)
+#define GMAC_RLPIEX_V  0x00000001U
+#define GMAC_RLPIEX_S  3
+/** GMAC_TLPIST : RO; bitpos: [8]; default: 0;
+ *  Transmit LPI State When set, this bit indicates that the MAC is transmitting the
+ *  LPI pattern on the GMII or MII interface
+ */
+#define GMAC_TLPIST    (BIT(8))
+#define GMAC_TLPIST_M  (GMAC_TLPIST_V << GMAC_TLPIST_S)
+#define GMAC_TLPIST_V  0x00000001U
+#define GMAC_TLPIST_S  8
+/** GMAC_RLPIST : RO; bitpos: [9]; default: 0;
+ *  Receive LPI State When set, this bit indicates that the MAC is receiving the LPI
+ *  pattern on the GMII or MII interface
+ */
+#define GMAC_RLPIST    (BIT(9))
+#define GMAC_RLPIST_M  (GMAC_RLPIST_V << GMAC_RLPIST_S)
+#define GMAC_RLPIST_V  0x00000001U
+#define GMAC_RLPIST_S  9
+/** GMAC_LPIEN : R/W; bitpos: [16]; default: 0;
+ *  LPI Enable When set, this bit instructs the MAC Transmitter to enter the LPI state
+ *  When reset, this bit instructs the MAC to exit the LPI state and resume normal
+ *  transmission This bit is cleared when the LPITXA bit is set and the MAC exits the
+ *  LPI state because of the arrival of a new packet for transmission
+ */
+#define GMAC_LPIEN    (BIT(16))
+#define GMAC_LPIEN_M  (GMAC_LPIEN_V << GMAC_LPIEN_S)
+#define GMAC_LPIEN_V  0x00000001U
+#define GMAC_LPIEN_S  16
+/** GMAC_PLS : R/W; bitpos: [17]; default: 0;
+ *  PHY Link Status This bit indicates the link status of the PHY The MAC Transmitter
+ *  asserts the LPI pattern only when the link status is up _okay_ at least for the
+ *  time indicated by the LPI LS TIMER When set, the link is considered to be okay _up_
+ *  and when reset, the link is considered to be down
+ */
+#define GMAC_PLS    (BIT(17))
+#define GMAC_PLS_M  (GMAC_PLS_V << GMAC_PLS_S)
+#define GMAC_PLS_V  0x00000001U
+#define GMAC_PLS_S  17
+/** GMAC_PLSEN : R/W; bitpos: [18]; default: 0;
+ *  PHY Link Status Enable This bit enables the link status received on the RGMII,
+ *  SGMII, or SMII receive paths to be used for activating the LPI LS TIMER When set,
+ *  the MAC uses the linkstatus bits of Register 54 _SGMII/RGMII/SMII Control and
+ *  Status Register_ and Bit 17 _PLS_ for the LPI LS Timer trigger When cleared, the
+ *  MAC ignores the linkstatus bits of Register 54 and takes only the PLS bit This bit
+ *  is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface
+ */
+#define GMAC_PLSEN    (BIT(18))
+#define GMAC_PLSEN_M  (GMAC_PLSEN_V << GMAC_PLSEN_S)
+#define GMAC_PLSEN_V  0x00000001U
+#define GMAC_PLSEN_S  18
+/** GMAC_LPITXA : R/W; bitpos: [19]; default: 0;
+ *  LPI TX Automate This bit controls the behavior of the MAC when it is entering or
+ *  coming out of the LPI mode on the transmit side This bit is not functional in the
+ *  GMAC CORE configuration in which the Tx clock gating is done during the LPI mode If
+ *  the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all
+ *  outstanding frames _in the core_ and pending frames _in the application interface_
+ *  have been transmitted The MAC comes out of the LPI mode when the application sends
+ *  any frame for transmission or the application issues a TX FIFO Flush command In
+ *  addition, the MAC automatically clears the LPIEN bit when it exits the LPI state If
+ *  TX FIFO Flush is set in Bit 20 of Register 6 _Operation Mode Register_, when the
+ *  MAC is in the LPI mode, the MAC exits the LPI mode When this bit is 0, the LPIEN
+ *  bit directly controls behavior of the MAC when it is entering or coming out of the
+ *  LPI mode
+ */
+#define GMAC_LPITXA    (BIT(19))
+#define GMAC_LPITXA_M  (GMAC_LPITXA_V << GMAC_LPITXA_S)
+#define GMAC_LPITXA_V  0x00000001U
+#define GMAC_LPITXA_S  19
+
+/** GMAC_REGISTER13_LPITIMERSCONTROLREGISTER_REG register
+ *  Controls the timeout values in LPI states This register is present only when you
+ *  select the Energy Efficient Ethernet feature in coreConsultant
+ */
+#define GMAC_REGISTER13_LPITIMERSCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x34)
+/** GMAC_TWT : R/W; bitpos: [15:0]; default: 0;
+ *  LPI TW TIMER This field specifies the minimum time _in microseconds_ for which the
+ *  MAC waits after it stops transmitting the LPI pattern to the PHY and before it
+ *  resumes the normal transmission The TLPIEX status bit is set after the expiry of
+ *  this timer
+ */
+#define GMAC_TWT    0x0000FFFFU
+#define GMAC_TWT_M  (GMAC_TWT_V << GMAC_TWT_S)
+#define GMAC_TWT_V  0x0000FFFFU
+#define GMAC_TWT_S  0
+/** GMAC_LST : R/W; bitpos: [25:16]; default: 1000;
+ *  LPI LS TIMER This field specifies the minimum time _in milliseconds_ for which the
+ *  link status from the PHY should be up _OKAY_ before the LPI pattern can be
+ *  transmitted to the PHY The MAC does not transmit the LPI pattern even when the
+ *  LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count The
+ *  default value of the LPI LS Timer is 1000 _1 sec_ as defined in the IEEE standard
+ */
+#define GMAC_LST    0x000003FFU
+#define GMAC_LST_M  (GMAC_LST_V << GMAC_LST_S)
+#define GMAC_LST_V  0x000003FFU
+#define GMAC_LST_S  16
+
+/** GMAC_REGISTER14_INTERRUPTSTATUSREGISTER_REG register
+ *  Contains the interrupt status
+ */
+#define GMAC_REGISTER14_INTERRUPTSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x38)
+/** GMAC_RGSMIIIS : RO; bitpos: [0]; default: 0;
+ *  RGMII or SMII Interrupt Status This bit is set because of any change in value of
+ *  the Link Status of RGMII or SMII interface _Bit 3 in Register 54 _SGMII/RGMII/SMII
+ *  Control and Status Register__ This bit is cleared when you perform a read operation
+ *  on the SGMII/RGMII/SMII Control and Status Register This bit is valid only when you
+ *  select the optional RGMII or SMII PHY interface during core configuration and
+ *  operation
+ */
+#define GMAC_RGSMIIIS    (BIT(0))
+#define GMAC_RGSMIIIS_M  (GMAC_RGSMIIIS_V << GMAC_RGSMIIIS_S)
+#define GMAC_RGSMIIIS_V  0x00000001U
+#define GMAC_RGSMIIIS_S  0
+/** GMAC_PCSLCHGIS : RO; bitpos: [1]; default: 0;
+ *  PCS Link Status Changed This bit is set because of any change in Link Status in the
+ *  TBI, RTBI, or SGMII PHY interface _Bit 2 in Register 49 _AN Status Register__ This
+ *  bit is cleared when you perform a read operation on the AN Status register This bit
+ *  is valid only when you select the optional TBI, RTBI, or SGMII PHY interface during
+ *  core configuration and operation
+ */
+#define GMAC_PCSLCHGIS    (BIT(1))
+#define GMAC_PCSLCHGIS_M  (GMAC_PCSLCHGIS_V << GMAC_PCSLCHGIS_S)
+#define GMAC_PCSLCHGIS_V  0x00000001U
+#define GMAC_PCSLCHGIS_S  1
+/** GMAC_PCSANCIS : RO; bitpos: [2]; default: 0;
+ *  PCS AutoNegotiation Complete This bit is set when the Autonegotiation is completed
+ *  in the TBI, RTBI, or SGMII PHY interface _Bit 5 in Register 49 _AN Status
+ *  Register__ This bit is cleared when you perform a read operation to the AN Status
+ *  register This bit is valid only when you select the optional TBI, RTBI, or SGMII
+ *  PHY interface during core configuration and operation
+ */
+#define GMAC_PCSANCIS    (BIT(2))
+#define GMAC_PCSANCIS_M  (GMAC_PCSANCIS_V << GMAC_PCSANCIS_S)
+#define GMAC_PCSANCIS_V  0x00000001U
+#define GMAC_PCSANCIS_S  2
+/** GMAC_PMTIS : RO; bitpos: [3]; default: 0;
+ *  PMT Interrupt Status This bit is set when a magic packet or remote wakeup frame is
+ *  received in the powerdown mode _see Bits 5 and 6 in the PMT Control and Status
+ *  Register_ This bit is cleared when both Bits[6:5] are cleared because of a read
+ *  operation to the PMT Control and Status register This bit is valid only when you
+ *  select the optional PMT module during core configuration
+ */
+#define GMAC_PMTIS    (BIT(3))
+#define GMAC_PMTIS_M  (GMAC_PMTIS_V << GMAC_PMTIS_S)
+#define GMAC_PMTIS_V  0x00000001U
+#define GMAC_PMTIS_S  3
+/** GMAC_MMCIS : RO; bitpos: [4]; default: 0;
+ *  MMC Interrupt Status This bit is set high when any of the Bits [7:5] is set high
+ *  and cleared only when all of these bits are low This bit is valid only when you
+ *  select the optional MMC module during core configuration
+ */
+#define GMAC_MMCIS    (BIT(4))
+#define GMAC_MMCIS_M  (GMAC_MMCIS_V << GMAC_MMCIS_S)
+#define GMAC_MMCIS_V  0x00000001U
+#define GMAC_MMCIS_S  4
+/** GMAC_MMCRXIS : RO; bitpos: [5]; default: 0;
+ *  MMC Receive Interrupt Status This bit is set high when an interrupt is generated in
+ *  the MMC Receive Interrupt Register This bit is cleared when all the bits in this
+ *  interrupt register are cleared This bit is valid only when you select the optional
+ *  MMC module during core configuration
+ */
+#define GMAC_MMCRXIS    (BIT(5))
+#define GMAC_MMCRXIS_M  (GMAC_MMCRXIS_V << GMAC_MMCRXIS_S)
+#define GMAC_MMCRXIS_V  0x00000001U
+#define GMAC_MMCRXIS_S  5
+/** GMAC_MMCTXIS : RO; bitpos: [6]; default: 0;
+ *  MMC Transmit Interrupt Status This bit is set high when an interrupt is generated
+ *  in the MMC Transmit Interrupt Register This bit is cleared when all the bits in
+ *  this interrupt register are cleared This bit is valid only when you select the
+ *  optional MMC module during core configuration
+ */
+#define GMAC_MMCTXIS    (BIT(6))
+#define GMAC_MMCTXIS_M  (GMAC_MMCTXIS_V << GMAC_MMCTXIS_S)
+#define GMAC_MMCTXIS_V  0x00000001U
+#define GMAC_MMCTXIS_S  6
+/** GMAC_MMCRXIPIS : RO; bitpos: [7]; default: 0;
+ *  MMC Receive Checksum Offload Interrupt Status This bit is set high when an
+ *  interrupt is generated in the MMC Receive Checksum Offload Interrupt Register This
+ *  bit is cleared when all the bits in this interrupt register are cleared This bit is
+ *  valid only when you select the optional MMC module and Checksum Offload Engine
+ *  _Type 2_ during core configuration
+ */
+#define GMAC_MMCRXIPIS    (BIT(7))
+#define GMAC_MMCRXIPIS_M  (GMAC_MMCRXIPIS_V << GMAC_MMCRXIPIS_S)
+#define GMAC_MMCRXIPIS_V  0x00000001U
+#define GMAC_MMCRXIPIS_S  7
+/** GMAC_TSIS : RO; bitpos: [9]; default: 0;
+ *  Timestamp Interrupt Status When the Advanced Timestamp feature is enabled, this bit
+ *  is set when R_SS_RC any of the following conditions is true: The system time value
+ *  equals or exceeds the value specified in the Target Time High and Low registers
+ *  There is an overflow in the seconds register The Auxiliary snapshot trigger is
+ *  asserted This bit is cleared on reading Bit 0 of Register 458 _Timestamp Status
+ *  Register_ If default Timestamping is enabled, when set, this bit indicates that the
+ *  system time value is equal to or exceeds the value specified in the Target Time
+ *  registers In this mode, this bit is cleared after the completion of the read of
+ *  this bit In all other modes, this bit is reserved
+ */
+#define GMAC_TSIS    (BIT(9))
+#define GMAC_TSIS_M  (GMAC_TSIS_V << GMAC_TSIS_S)
+#define GMAC_TSIS_V  0x00000001U
+#define GMAC_TSIS_S  9
+/** GMAC_LPIIS : RO; bitpos: [10]; default: 0;
+ *  LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this
+ *  bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver This
+ *  bit is cleared on reading Bit 0 of Register 12 _LPI Control and Status Register_ In
+ *  all other modes, this bit is reserved
+ */
+#define GMAC_LPIIS    (BIT(10))
+#define GMAC_LPIIS_M  (GMAC_LPIIS_V << GMAC_LPIIS_S)
+#define GMAC_LPIIS_V  0x00000001U
+#define GMAC_LPIIS_S  10
+/** GMAC_GPIIS : RO; bitpos: [11]; default: 0;
+ *  GPI Interrupt Status When the GPIO feature is enabled, this bit is set when any
+ *  active event _LL or LH_ occurs on the GPIS field _Bits [3:0]_ of Register 56
+ *  _General Purpose IO Register_ and the corresponding GPIE bit is enabled This bit is
+ *  cleared on reading lane 0 _GPIS_ of Register 56 _General Purpose IO Register_ When
+ *  the GPIO feature is not enabled, this bit is reserved
+ */
+#define GMAC_GPIIS    (BIT(11))
+#define GMAC_GPIIS_M  (GMAC_GPIIS_V << GMAC_GPIIS_S)
+#define GMAC_GPIIS_V  0x00000001U
+#define GMAC_GPIIS_S  11
+
+/** GMAC_REGISTER15_INTERRUPTMASKREGISTER_REG register
+ *  Contains the masks for generating the interrupts
+ */
+#define GMAC_REGISTER15_INTERRUPTMASKREGISTER_REG (DR_REG_GMAC_BASE + 0x3c)
+/** GMAC_RGSMIIIM : R/W; bitpos: [0]; default: 0;
+ *  RGMII or SMII Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit
+ *  in Register 14 _Interrupt Status Register_
+ */
+#define GMAC_RGSMIIIM    (BIT(0))
+#define GMAC_RGSMIIIM_M  (GMAC_RGSMIIIM_V << GMAC_RGSMIIIM_S)
+#define GMAC_RGSMIIIM_V  0x00000001U
+#define GMAC_RGSMIIIM_S  0
+/** GMAC_PCSLCHGIM : R/W; bitpos: [1]; default: 0;
+ *  PCS Link Status Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of the PCS Linkstatus changed bit in
+ *  Register 14 _Interrupt Status Register_
+ */
+#define GMAC_PCSLCHGIM    (BIT(1))
+#define GMAC_PCSLCHGIM_M  (GMAC_PCSLCHGIM_V << GMAC_PCSLCHGIM_S)
+#define GMAC_PCSLCHGIM_V  0x00000001U
+#define GMAC_PCSLCHGIM_S  1
+/** GMAC_PCSANCIM : R/W; bitpos: [2]; default: 0;
+ *  PCS AN Completion Interrupt Mask When set, this bit disables the assertion of the
+ *  interrupt signal because of the setting of PCS Autonegotiation complete bit in
+ *  Register 14 _Interrupt Status Register_
+ */
+#define GMAC_PCSANCIM    (BIT(2))
+#define GMAC_PCSANCIM_M  (GMAC_PCSANCIM_V << GMAC_PCSANCIM_S)
+#define GMAC_PCSANCIM_V  0x00000001U
+#define GMAC_PCSANCIM_S  2
+/** GMAC_PMTIM : R/W; bitpos: [3]; default: 0;
+ *  PMT Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of PMT Interrupt Status bit in Register 14 _Interrupt
+ *  Status Register_
+ */
+#define GMAC_PMTIM    (BIT(3))
+#define GMAC_PMTIM_M  (GMAC_PMTIM_V << GMAC_PMTIM_S)
+#define GMAC_PMTIM_V  0x00000001U
+#define GMAC_PMTIM_S  3
+/** GMAC_TSIM : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of Timestamp Interrupt Status bit in Register 14
+ *  _Interrupt Status Register_ This bit is valid only when IEEE1588 timestamping is
+ *  enabled In all other modes, this bit is reserved
+ */
+#define GMAC_TSIM    (BIT(9))
+#define GMAC_TSIM_M  (GMAC_TSIM_V << GMAC_TSIM_S)
+#define GMAC_TSIM_V  0x00000001U
+#define GMAC_TSIM_S  9
+/** GMAC_LPIIM : R/W; bitpos: [10]; default: 0;
+ *  LPI Interrupt Mask When set, this bit disables the assertion of the interrupt
+ *  signal because of the setting of the LPI Interrupt Status bit in Register 14
+ *  _Interrupt Status Register_ This bit is valid only when you select the Energy
+ *  Efficient Ethernet feature during core configuration In all other modes, this bit
+ *  is reserved
+ */
+#define GMAC_LPIIM    (BIT(10))
+#define GMAC_LPIIM_M  (GMAC_LPIIM_V << GMAC_LPIIM_S)
+#define GMAC_LPIIM_V  0x00000001U
+#define GMAC_LPIIM_S  10
+
+/** GMAC_REGISTER16_MACADDRESS0HIGHREGISTER_REG register
+ *  Contains the higher 16 bits of the first MAC address
+ */
+#define GMAC_REGISTER16_MACADDRESS0HIGHREGISTER_REG (DR_REG_GMAC_BASE + 0x40)
+/** GMAC_ADDRHI_0 : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address0 [47:32] This field contains the upper 16 bits _47:32_ of the first
+ *  6byte MAC address The MAC uses this field for filtering the received frames and
+ *  inserting the MAC address in the Transmit Flow Control _Pause_ Frames
+ */
+#define GMAC_ADDRHI_0    0x0000FFFFU
+#define GMAC_ADDRHI_0_M  (GMAC_ADDRHI_0_V << GMAC_ADDRHI_0_S)
+#define GMAC_ADDRHI_0_V  0x0000FFFFU
+#define GMAC_ADDRHI_0_S  0
+/** GMAC_AE_0 : RO; bitpos: [31]; default: 1;
+ *  Address Enable This bit is always set to 1
+ */
+#define GMAC_AE_0    (BIT(31))
+#define GMAC_AE_0_M  (GMAC_AE_0_V << GMAC_AE_0_S)
+#define GMAC_AE_0_V  0x00000001U
+#define GMAC_AE_0_S  31
+
+/** GMAC_REGISTER17_MACADDRESS0LOWREGISTER_REG register
+ *  Contains the lower 32 bits of the first MAC address
+ */
+#define GMAC_REGISTER17_MACADDRESS0LOWREGISTER_REG (DR_REG_GMAC_BASE + 0x44)
+/** GMAC_ADDRLO_0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  MAC Address0 [31:0] This field contains the lower 32 bits of the first 6byte MAC
+ *  address This is used by the MAC for filtering the received frames and inserting the
+ *  MAC address in the Transmit Flow Control _Pause_ Frames
+ */
+#define GMAC_ADDRLO_0    0xFFFFFFFFU
+#define GMAC_ADDRLO_0_M  (GMAC_ADDRLO_0_V << GMAC_ADDRLO_0_S)
+#define GMAC_ADDRLO_0_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_0_S  0
+
+/** GMAC_REGISTER18_MACADDRESS1HIGHREGISTER_REG register
+ *  Contains the higher 16 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+#define GMAC_REGISTER18_MACADDRESS1HIGHREGISTER_REG (DR_REG_GMAC_BASE + 0x48)
+/** GMAC_ADDRHI_1 : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address1 [47:32] This field contains the upper 16 bits _47:32_ of the second
+ *  6byte MAC address
+ */
+#define GMAC_ADDRHI_1    0x0000FFFFU
+#define GMAC_ADDRHI_1_M  (GMAC_ADDRHI_1_V << GMAC_ADDRHI_1_S)
+#define GMAC_ADDRHI_1_V  0x0000FFFFU
+#define GMAC_ADDRHI_1_S  0
+/** GMAC_MBC_1 : R/W; bitpos: [29:24]; default: 0;
+ *  Mask Byte Control These bits are mask control bits for comparison of each of the
+ *  MAC Address bytes When set high, the MAC does not compare the corresponding byte of
+ *  received DA or SA with the contents of MAC Address1 registers Each bit controls the
+ *  masking of the bytes as follows: Bit 29: Register 18[15:8] Bit 28: Register 18[7:0]
+ *  Bit 27: Register 19[31:24]  Bit 24: Register 19[7:0] You can filter a group of
+ *  addresses _known as group address filtering_ by masking one or more bytes of the
+ *  address
+ */
+#define GMAC_MBC_1    0x0000003FU
+#define GMAC_MBC_1_M  (GMAC_MBC_1_V << GMAC_MBC_1_S)
+#define GMAC_MBC_1_V  0x0000003FU
+#define GMAC_MBC_1_S  24
+/** GMAC_SA_1 : R/W; bitpos: [30]; default: 0;
+ *  Source Address When this bit is set, the MAC Address1[47:0] is used to compare with
+ *  the SA fields of the received frame When this bit is reset, the MAC Address1[47:0]
+ *  is used to compare with the DA fields of the received frame
+ */
+#define GMAC_SA_1    (BIT(30))
+#define GMAC_SA_1_M  (GMAC_SA_1_V << GMAC_SA_1_S)
+#define GMAC_SA_1_V  0x00000001U
+#define GMAC_SA_1_S  30
+/** GMAC_AE_1 : R/W; bitpos: [31]; default: 0;
+ *  Address Enable
+ */
+#define GMAC_AE_1    (BIT(31))
+#define GMAC_AE_1_M  (GMAC_AE_1_V << GMAC_AE_1_S)
+#define GMAC_AE_1_V  0x00000001U
+#define GMAC_AE_1_S  31
+
+/** GMAC_REGISTER19_MACADDRESS1LOWREGISTER_REG register
+ *  Contains the lower 32 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+#define GMAC_REGISTER19_MACADDRESS1LOWREGISTER_REG (DR_REG_GMAC_BASE + 0x4c)
+/** GMAC_ADDRLO_1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  MAC Address1 [31:0] This field contains the lower 32 bits of the second 6byte MAC
+ *  address The content of this field is undefined until loaded by the Application
+ *  after the initialization process
+ */
+#define GMAC_ADDRLO_1    0xFFFFFFFFU
+#define GMAC_ADDRLO_1_M  (GMAC_ADDRLO_1_V << GMAC_ADDRLO_1_S)
+#define GMAC_ADDRLO_1_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_1_S  0
+
+/** GMAC_MACADDRESS2HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHETHIRDMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS2HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHETHIRDMACADDRESS_REG (DR_REG_GMAC_BASE + 0x50)
+/** GMAC_ADDRHI_2 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_2    0x0000FFFFU
+#define GMAC_ADDRHI_2_M  (GMAC_ADDRHI_2_V << GMAC_ADDRHI_2_S)
+#define GMAC_ADDRHI_2_V  0x0000FFFFU
+#define GMAC_ADDRHI_2_S  0
+/** GMAC_MBC_2 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_2    0x0000003FU
+#define GMAC_MBC_2_M  (GMAC_MBC_2_V << GMAC_MBC_2_S)
+#define GMAC_MBC_2_V  0x0000003FU
+#define GMAC_MBC_2_S  24
+/** GMAC_SA_2 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_2    (BIT(30))
+#define GMAC_SA_2_M  (GMAC_SA_2_V << GMAC_SA_2_S)
+#define GMAC_SA_2_V  0x00000001U
+#define GMAC_SA_2_S  30
+/** GMAC_AE_2 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_2    (BIT(31))
+#define GMAC_AE_2_M  (GMAC_AE_2_V << GMAC_AE_2_S)
+#define GMAC_AE_2_V  0x00000001U
+#define GMAC_AE_2_S  31
+
+/** GMAC_MACADDRESS2LOWREGISTERCONTAINSTHELOWER32BITSOFTHETHIRDMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS2LOWREGISTERCONTAINSTHELOWER32BITSOFTHETHIRDMACADDRESS_REG (DR_REG_GMAC_BASE + 0x54)
+/** GMAC_ADDRLO_2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address2 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_2    0xFFFFFFFFU
+#define GMAC_ADDRLO_2_M  (GMAC_ADDRLO_2_V << GMAC_ADDRLO_2_S)
+#define GMAC_ADDRLO_2_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_2_S  0
+
+/** GMAC_MACADDRESS3HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEFOURTHMACADDRESS_REG
+ *  register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS3HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEFOURTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x58)
+/** GMAC_ADDRHI_3 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_3    0x0000FFFFU
+#define GMAC_ADDRHI_3_M  (GMAC_ADDRHI_3_V << GMAC_ADDRHI_3_S)
+#define GMAC_ADDRHI_3_V  0x0000FFFFU
+#define GMAC_ADDRHI_3_S  0
+/** GMAC_MBC_3 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_3    0x0000003FU
+#define GMAC_MBC_3_M  (GMAC_MBC_3_V << GMAC_MBC_3_S)
+#define GMAC_MBC_3_V  0x0000003FU
+#define GMAC_MBC_3_S  24
+/** GMAC_SA_3 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_3    (BIT(30))
+#define GMAC_SA_3_M  (GMAC_SA_3_V << GMAC_SA_3_S)
+#define GMAC_SA_3_V  0x00000001U
+#define GMAC_SA_3_S  30
+/** GMAC_AE_3 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_3    (BIT(31))
+#define GMAC_AE_3_M  (GMAC_AE_3_V << GMAC_AE_3_S)
+#define GMAC_AE_3_V  0x00000001U
+#define GMAC_AE_3_S  31
+
+/** GMAC_MACADDRESS3LOWREGISTERCONTAINSTHELOWER32BITSOFTHEFOURTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS3LOWREGISTERCONTAINSTHELOWER32BITSOFTHEFOURTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x5c)
+/** GMAC_ADDRLO_3 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address3 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_3    0xFFFFFFFFU
+#define GMAC_ADDRLO_3_M  (GMAC_ADDRLO_3_V << GMAC_ADDRLO_3_S)
+#define GMAC_ADDRLO_3_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_3_S  0
+
+/** GMAC_MACADDRESS4HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEFIFTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS4HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEFIFTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x60)
+/** GMAC_ADDRHI_4 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_4    0x0000FFFFU
+#define GMAC_ADDRHI_4_M  (GMAC_ADDRHI_4_V << GMAC_ADDRHI_4_S)
+#define GMAC_ADDRHI_4_V  0x0000FFFFU
+#define GMAC_ADDRHI_4_S  0
+/** GMAC_MBC_4 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_4    0x0000003FU
+#define GMAC_MBC_4_M  (GMAC_MBC_4_V << GMAC_MBC_4_S)
+#define GMAC_MBC_4_V  0x0000003FU
+#define GMAC_MBC_4_S  24
+/** GMAC_SA_4 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_4    (BIT(30))
+#define GMAC_SA_4_M  (GMAC_SA_4_V << GMAC_SA_4_S)
+#define GMAC_SA_4_V  0x00000001U
+#define GMAC_SA_4_S  30
+/** GMAC_AE_4 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_4    (BIT(31))
+#define GMAC_AE_4_M  (GMAC_AE_4_V << GMAC_AE_4_S)
+#define GMAC_AE_4_V  0x00000001U
+#define GMAC_AE_4_S  31
+
+/** GMAC_MACADDRESS4LOWREGISTERCONTAINSTHELOWER32BITSOFTHEFIFTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS4LOWREGISTERCONTAINSTHELOWER32BITSOFTHEFIFTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x64)
+/** GMAC_ADDRLO_4 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address4 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_4    0xFFFFFFFFU
+#define GMAC_ADDRLO_4_M  (GMAC_ADDRLO_4_V << GMAC_ADDRLO_4_S)
+#define GMAC_ADDRLO_4_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_4_S  0
+
+/** GMAC_MACADDRESS5HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHESIXTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS5HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHESIXTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x68)
+/** GMAC_ADDRHI_5 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_5    0x0000FFFFU
+#define GMAC_ADDRHI_5_M  (GMAC_ADDRHI_5_V << GMAC_ADDRHI_5_S)
+#define GMAC_ADDRHI_5_V  0x0000FFFFU
+#define GMAC_ADDRHI_5_S  0
+/** GMAC_MBC_5 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_5    0x0000003FU
+#define GMAC_MBC_5_M  (GMAC_MBC_5_V << GMAC_MBC_5_S)
+#define GMAC_MBC_5_V  0x0000003FU
+#define GMAC_MBC_5_S  24
+/** GMAC_SA_5 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_5    (BIT(30))
+#define GMAC_SA_5_M  (GMAC_SA_5_V << GMAC_SA_5_S)
+#define GMAC_SA_5_V  0x00000001U
+#define GMAC_SA_5_S  30
+/** GMAC_AE_5 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_5    (BIT(31))
+#define GMAC_AE_5_M  (GMAC_AE_5_V << GMAC_AE_5_S)
+#define GMAC_AE_5_V  0x00000001U
+#define GMAC_AE_5_S  31
+
+/** GMAC_MACADDRESS5LOWREGISTERCONTAINSTHELOWER32BITSOFTHESIXTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS5LOWREGISTERCONTAINSTHELOWER32BITSOFTHESIXTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x6c)
+/** GMAC_ADDRLO_5 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address5 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_5    0xFFFFFFFFU
+#define GMAC_ADDRLO_5_M  (GMAC_ADDRLO_5_V << GMAC_ADDRLO_5_S)
+#define GMAC_ADDRLO_5_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_5_S  0
+
+/** GMAC_MACADDRESS6HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHESEVENTHMACADDRESS_REG
+ *  register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS6HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHESEVENTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x70)
+/** GMAC_ADDRHI_6 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_6    0x0000FFFFU
+#define GMAC_ADDRHI_6_M  (GMAC_ADDRHI_6_V << GMAC_ADDRHI_6_S)
+#define GMAC_ADDRHI_6_V  0x0000FFFFU
+#define GMAC_ADDRHI_6_S  0
+/** GMAC_MBC_6 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_6    0x0000003FU
+#define GMAC_MBC_6_M  (GMAC_MBC_6_V << GMAC_MBC_6_S)
+#define GMAC_MBC_6_V  0x0000003FU
+#define GMAC_MBC_6_S  24
+/** GMAC_SA_6 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_6    (BIT(30))
+#define GMAC_SA_6_M  (GMAC_SA_6_V << GMAC_SA_6_S)
+#define GMAC_SA_6_V  0x00000001U
+#define GMAC_SA_6_S  30
+/** GMAC_AE_6 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_6    (BIT(31))
+#define GMAC_AE_6_M  (GMAC_AE_6_V << GMAC_AE_6_S)
+#define GMAC_AE_6_V  0x00000001U
+#define GMAC_AE_6_S  31
+
+/** GMAC_MACADDRESS6LOWREGISTERCONTAINSTHELOWER32BITSOFTHESEVENTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS6LOWREGISTERCONTAINSTHELOWER32BITSOFTHESEVENTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x74)
+/** GMAC_ADDRLO_6 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address6 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_6    0xFFFFFFFFU
+#define GMAC_ADDRLO_6_M  (GMAC_ADDRLO_6_V << GMAC_ADDRLO_6_S)
+#define GMAC_ADDRLO_6_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_6_S  0
+
+/** GMAC_MACADDRESS7HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEEIGHTHMACADDRESS_REG
+ *  register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS7HIGHREGISTERCONTAINSTHEHIGHER16BITSOFTHEEIGHTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x78)
+/** GMAC_ADDRHI_7 : R/W; bitpos: [15:0]; default: 65535;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRHI_7    0x0000FFFFU
+#define GMAC_ADDRHI_7_M  (GMAC_ADDRHI_7_V << GMAC_ADDRHI_7_S)
+#define GMAC_ADDRHI_7_V  0x0000FFFFU
+#define GMAC_ADDRHI_7_S  0
+/** GMAC_MBC_7 : R/W; bitpos: [29:24]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_MBC_7    0x0000003FU
+#define GMAC_MBC_7_M  (GMAC_MBC_7_V << GMAC_MBC_7_S)
+#define GMAC_MBC_7_V  0x0000003FU
+#define GMAC_MBC_7_S  24
+/** GMAC_SA_7 : R/W; bitpos: [30]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_SA_7    (BIT(30))
+#define GMAC_SA_7_M  (GMAC_SA_7_V << GMAC_SA_7_S)
+#define GMAC_SA_7_V  0x00000001U
+#define GMAC_SA_7_S  30
+/** GMAC_AE_7 : R/W; bitpos: [31]; default: 0;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_AE_7    (BIT(31))
+#define GMAC_AE_7_M  (GMAC_AE_7_V << GMAC_AE_7_S)
+#define GMAC_AE_7_V  0x00000001U
+#define GMAC_AE_7_S  31
+
+/** GMAC_MACADDRESS7LOWREGISTERCONTAINSTHELOWER32BITSOFTHEEIGHTHMACADDRESS_REG register
+ *  Reserved
+ */
+#define GMAC_MACADDRESS7LOWREGISTERCONTAINSTHELOWER32BITSOFTHEEIGHTHMACADDRESS_REG (DR_REG_GMAC_BASE + 0x7c)
+/** GMAC_ADDRLO_7 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This register is present only when Enable MAC Address7 is selected in
+ *  coreConsultant _See Table 78_
+ */
+#define GMAC_ADDRLO_7    0xFFFFFFFFU
+#define GMAC_ADDRLO_7_M  (GMAC_ADDRLO_7_V << GMAC_ADDRLO_7_S)
+#define GMAC_ADDRLO_7_V  0xFFFFFFFFU
+#define GMAC_ADDRLO_7_S  0
+
+/** GMAC_REGISTER48_ANCONTROLREGISTER_REG register
+ *  Enables and/or restarts autonegotiation This register also enables the Physical
+ *  Coding Sublayer _PCS_ loopback This register is present only when you select the
+ *  TBI, RTBI, or SGMII interface in coreConsultant
+ */
+#define GMAC_REGISTER48_ANCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0xc0)
+/** GMAC_RAN : R/W1S; bitpos: [9]; default: 0;
+ *  Restart AutoNegotiation When set, this bit causes autonegotiation to restart if Bit
+ *  12 _ANE_ is set This bit is selfclearing after autonegotiation starts This bit
+ *  should be cleared for normal operation
+ */
+#define GMAC_RAN    (BIT(9))
+#define GMAC_RAN_M  (GMAC_RAN_V << GMAC_RAN_S)
+#define GMAC_RAN_V  0x00000001U
+#define GMAC_RAN_S  9
+/** GMAC_ANE : R/W; bitpos: [12]; default: 0;
+ *  AutoNegotiation Enable When set, this bit enables the MAC to perform
+ *  autonegotiation with the link partner Clearing this bit disables the autonegotiation
+ */
+#define GMAC_ANE    (BIT(12))
+#define GMAC_ANE_M  (GMAC_ANE_V << GMAC_ANE_S)
+#define GMAC_ANE_V  0x00000001U
+#define GMAC_ANE_S  12
+/** GMAC_ELE : R/W; bitpos: [14]; default: 0;
+ *  External Loopback Enable When set, this bit causes the PHY to loopback the transmit
+ *  data into the receive path The pcs_ewrap_o signal is asserted high when this bit is
+ *  set
+ */
+#define GMAC_ELE    (BIT(14))
+#define GMAC_ELE_M  (GMAC_ELE_V << GMAC_ELE_S)
+#define GMAC_ELE_V  0x00000001U
+#define GMAC_ELE_S  14
+/** GMAC_ECD : R/W; bitpos: [16]; default: 0;
+ *  Enable Comma Detect When set, this bit enables the PHY for comma detection and word
+ *  resynchronization This bit controls the pcs_en_cdet_o signal on the TBI, RTBI, or
+ *  SGMII interface
+ */
+#define GMAC_ECD    (BIT(16))
+#define GMAC_ECD_M  (GMAC_ECD_V << GMAC_ECD_S)
+#define GMAC_ECD_V  0x00000001U
+#define GMAC_ECD_S  16
+/** GMAC_LR : R/W; bitpos: [17]; default: 0;
+ *  Lock to Reference When set, this bit enables the PHY to lock its PLL to the 125 MHz
+ *  reference clock This bit controls the pcs_lck_ref_o signal on the TBI, RTBI, or
+ *  SGMII interface
+ */
+#define GMAC_LR    (BIT(17))
+#define GMAC_LR_M  (GMAC_LR_V << GMAC_LR_S)
+#define GMAC_LR_V  0x00000001U
+#define GMAC_LR_S  17
+/** GMAC_SGMRAL : R/W; bitpos: [18]; default: 0;
+ *  SGMII RAL Control When set, this bit forces the SGMII RAL block to operate in the
+ *  speed configured in the Speed and Port Select bits of the MAC Configuration
+ *  register This is useful when the SGMII interface is used in a direct MAC to MAC
+ *  connection _without a PHY_ and any MAC must reconfigure the speed When reset, the
+ *  SGMII RAL block operates according to the link speed status received on SGMII _from
+ *  the PHY_ This bit is reserved _and RO_ if the SGMII PHY interface is not selected
+ *  during core configuration
+ */
+#define GMAC_SGMRAL    (BIT(18))
+#define GMAC_SGMRAL_M  (GMAC_SGMRAL_V << GMAC_SGMRAL_S)
+#define GMAC_SGMRAL_V  0x00000001U
+#define GMAC_SGMRAL_S  18
+
+/** GMAC_REGISTER49_ANSTATUSREGISTER_REG register
+ *  Indicates the link and autonegotiation status This register is present only when
+ *  you select the TBI, RTBI, or SGMII interface in coreConsultant
+ */
+#define GMAC_REGISTER49_ANSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0xc4)
+/** GMAC_LS : RO; bitpos: [2]; default: 0;
+ *  Link Status This bit indicates whether the data channel _link_ is up or down For
+ *  the TBI, RTBI or SGMII interfaces, if ANEG is going on, data cannot be transferred
+ *  across the link and hence the link is given as down
+ */
+#define GMAC_LS    (BIT(2))
+#define GMAC_LS_M  (GMAC_LS_V << GMAC_LS_S)
+#define GMAC_LS_V  0x00000001U
+#define GMAC_LS_S  2
+/** GMAC_ANA : RO; bitpos: [3]; default: 1;
+ *  AutoNegotiation Ability This bit is always high because the MAC supports auto
+ *  negotiation
+ */
+#define GMAC_ANA    (BIT(3))
+#define GMAC_ANA_M  (GMAC_ANA_V << GMAC_ANA_S)
+#define GMAC_ANA_V  0x00000001U
+#define GMAC_ANA_S  3
+/** GMAC_ANC : RO; bitpos: [5]; default: 0;
+ *  AutoNegotiation Complete When set, this bit indicates that the autonegotiation
+ *  process is complete This bit is cleared when autonegotiation is reinitiated
+ */
+#define GMAC_ANC    (BIT(5))
+#define GMAC_ANC_M  (GMAC_ANC_V << GMAC_ANC_S)
+#define GMAC_ANC_V  0x00000001U
+#define GMAC_ANC_S  5
+/** GMAC_ES : RO; bitpos: [8]; default: 1;
+ *  Extended Status This bit is tied to high if the TBI or RTBI interface is selected
+ *  during core configuration indicating that the MAC supports extended status
+ *  information in Register 53 _TBI Extended  Status Register_ This bit is tied to low
+ *  if the SGMII interface is selected and the TBI or RTBI interface is not selected
+ *  during core configuration indicating that Register 53 is not present
+ */
+#define GMAC_ES    (BIT(8))
+#define GMAC_ES_M  (GMAC_ES_V << GMAC_ES_S)
+#define GMAC_ES_V  0x00000001U
+#define GMAC_ES_S  8
+
+/** GMAC_REGISTER50_AUTONEGOTIATIONADVERTISEMENTREGISTER_REG register
+ *  This register is configured before autonegotiation begins It contains the
+ *  advertised ability of the MAC This register is present only when you select the TBI
+ *  or RTBI interface in coreConsultant
+ */
+#define GMAC_REGISTER50_AUTONEGOTIATIONADVERTISEMENTREGISTER_REG (DR_REG_GMAC_BASE + 0xc8)
+/** GMAC_FD : R/W; bitpos: [5]; default: 1;
+ *  FullDuplex When set high, this bit indicates that the MAC supports the fullduplex
+ *  mode
+ */
+#define GMAC_FD    (BIT(5))
+#define GMAC_FD_M  (GMAC_FD_V << GMAC_FD_S)
+#define GMAC_FD_V  0x00000001U
+#define GMAC_FD_S  5
+/** GMAC_HD : R/W; bitpos: [6]; default: 1;
+ *  HalfDuplex When set high, this bit indicates that the MAC supports the halfduplex
+ *  mode This bit is always low _and RO_ when the MAC is configured for the
+ *  fullduplexonly mode
+ */
+#define GMAC_HD    (BIT(6))
+#define GMAC_HD_M  (GMAC_HD_V << GMAC_HD_S)
+#define GMAC_HD_V  0x00000001U
+#define GMAC_HD_S  6
+/** GMAC_PSE : R/W; bitpos: [8:7]; default: 3;
+ *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+ *  the MAC is capable of configuring the Pause function as defined in IEEE 8023x The
+ *  encoding of these bits is defined in IEEE 8023z, Section 37214
+ */
+#define GMAC_PSE    0x00000003U
+#define GMAC_PSE_M  (GMAC_PSE_V << GMAC_PSE_S)
+#define GMAC_PSE_V  0x00000003U
+#define GMAC_PSE_S  7
+/** GMAC_RFE : R/W; bitpos: [13:12]; default: 0;
+ *  Remote Fault Encoding These bits provide a remote fault encoding, indicating to a
+ *  link partner that a fault or error condition has occurred The encoding of these
+ *  bits is defined in IEEE 8023z, Section 37215
+ */
+#define GMAC_RFE    0x00000003U
+#define GMAC_RFE_M  (GMAC_RFE_V << GMAC_RFE_S)
+#define GMAC_RFE_V  0x00000003U
+#define GMAC_RFE_S  12
+/** GMAC_NP : RO; bitpos: [15]; default: 0;
+ *  Next Page Support This bit is always low because the MAC does not support the next
+ *  page
+ */
+#define GMAC_NP    (BIT(15))
+#define GMAC_NP_M  (GMAC_NP_V << GMAC_NP_S)
+#define GMAC_NP_V  0x00000001U
+#define GMAC_NP_S  15
+
+/** GMAC_REGISTER51_AUTONEGOTIATIONLINKPARTNERABILITYREGISTER_REG register
+ *  Contains the advertised ability of the link partner Its value is valid after
+ *  successful completion of autonegotiation or when a new base page has been received
+ *  _indicated in the AutoNegotiation Expansion Register_ This register is present only
+ *  when you select the TBI or RTBI interface in coreConsultant
+ */
+#define GMAC_REGISTER51_AUTONEGOTIATIONLINKPARTNERABILITYREGISTER_REG (DR_REG_GMAC_BASE + 0xcc)
+/** GMAC_FD_ABILITY : RO; bitpos: [5]; default: 0;
+ *  FullDuplex When set, this bit indicates that the link partner has the ability to
+ *  operate in the full duplex mode When cleared, this bit indicates that the link
+ *  partner does not have the ability to operate in the fullduplex mode
+ */
+#define GMAC_FD_ABILITY    (BIT(5))
+#define GMAC_FD_ABILITY_M  (GMAC_FD_ABILITY_V << GMAC_FD_ABILITY_S)
+#define GMAC_FD_ABILITY_V  0x00000001U
+#define GMAC_FD_ABILITY_S  5
+/** GMAC_HD_ABILITY : RO; bitpos: [6]; default: 0;
+ *  HalfDuplex When set, this bit indicates that the link partner has the ability to
+ *  operate in the halfduplex mode When cleared, this bit indicates that the link
+ *  partner does not have the ability to operate in the halfduplex mode
+ */
+#define GMAC_HD_ABILITY    (BIT(6))
+#define GMAC_HD_ABILITY_M  (GMAC_HD_ABILITY_V << GMAC_HD_ABILITY_S)
+#define GMAC_HD_ABILITY_V  0x00000001U
+#define GMAC_HD_ABILITY_S  6
+/** GMAC_PSE_ABILITY : RO; bitpos: [8:7]; default: 0;
+ *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+ *  the link partner's capability of configuring the Pause function as defined in the
+ *  IEEE 8023x specification The encoding of these bits is defined in IEEE 8023z,
+ *  Section 37214
+ */
+#define GMAC_PSE_ABILITY    0x00000003U
+#define GMAC_PSE_ABILITY_M  (GMAC_PSE_ABILITY_V << GMAC_PSE_ABILITY_S)
+#define GMAC_PSE_ABILITY_V  0x00000003U
+#define GMAC_PSE_ABILITY_S  7
+/** GMAC_RFE_ABILITY : RO; bitpos: [13:12]; default: 0;
+ *  Remote Fault Encoding These bits provide a remote fault encoding, indicating a
+ *  fault or error condition of the link partner The encoding of these bits is defined
+ *  in IEEE 8023z, Section 37215
+ */
+#define GMAC_RFE_ABILITY    0x00000003U
+#define GMAC_RFE_ABILITY_M  (GMAC_RFE_ABILITY_V << GMAC_RFE_ABILITY_S)
+#define GMAC_RFE_ABILITY_V  0x00000003U
+#define GMAC_RFE_ABILITY_S  12
+/** GMAC_ACK : RO; bitpos: [14]; default: 0;
+ *  Acknowledge When set, the autonegotiation function uses this bit to indicate that
+ *  the link partner has successfully received the base page of the MAC When cleared,
+ *  it indicates that the link partner did not successfully receive the base page of
+ *  the MAC
+ */
+#define GMAC_ACK    (BIT(14))
+#define GMAC_ACK_M  (GMAC_ACK_V << GMAC_ACK_S)
+#define GMAC_ACK_V  0x00000001U
+#define GMAC_ACK_S  14
+/** GMAC_NO : RO; bitpos: [15]; default: 0;
+ *  Next Page Support When set, this bit indicates that more next page information is
+ *  available When cleared, this bit indicates that next page exchange is not desired
+ */
+#define GMAC_NO    (BIT(15))
+#define GMAC_NO_M  (GMAC_NO_V << GMAC_NO_S)
+#define GMAC_NO_V  0x00000001U
+#define GMAC_NO_S  15
+
+/** GMAC_REGISTER52_AUTONEGOTIATIONEXPANSIONREGISTER_REG register
+ *  Indicates whether a new base page has been received from the link partner This
+ *  register is present only when you select the TBI or RTBI interface in coreConsultant
+ */
+#define GMAC_REGISTER52_AUTONEGOTIATIONEXPANSIONREGISTER_REG (DR_REG_GMAC_BASE + 0xd0)
+/** GMAC_NPR : RO; bitpos: [1]; default: 0;
+ *  New Page Received When set, this bit indicates that the MAC has received a new page
+ *  This bit is cleared when read
+ */
+#define GMAC_NPR    (BIT(1))
+#define GMAC_NPR_M  (GMAC_NPR_V << GMAC_NPR_S)
+#define GMAC_NPR_V  0x00000001U
+#define GMAC_NPR_S  1
+/** GMAC_NPA : RO; bitpos: [2]; default: 0;
+ *  Next Page Ability This bit is always low because the MAC does not support the next
+ *  page function
+ */
+#define GMAC_NPA    (BIT(2))
+#define GMAC_NPA_M  (GMAC_NPA_V << GMAC_NPA_S)
+#define GMAC_NPA_V  0x00000001U
+#define GMAC_NPA_S  2
+
+/** GMAC_REGISTER53_TBIEXTENDEDSTATUSREGISTER_REG register
+ *  Indicates all modes of operation of the MAC This register is present only when you
+ *  select the TBI or RTBI interface in coreConsultant
+ */
+#define GMAC_REGISTER53_TBIEXTENDEDSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0xd4)
+/** GMAC_GHD : RO; bitpos: [14]; default: 1;
+ *  1000BASEX HalfDuplex Capable This bit indicates that the MAC is able to perform the
+ *  halfduplex and 1000BASEX operations This bit is always low when the MAC is
+ *  configured for the fullduplexonly operation during core configuration
+ */
+#define GMAC_GHD    (BIT(14))
+#define GMAC_GHD_M  (GMAC_GHD_V << GMAC_GHD_S)
+#define GMAC_GHD_V  0x00000001U
+#define GMAC_GHD_S  14
+/** GMAC_GFD : RO; bitpos: [15]; default: 1;
+ *  1000BASEX FullDuplex Capable This bit indicates that the MAC is able to perform the
+ *  fullduplex and 1000BASEX operations
+ */
+#define GMAC_GFD    (BIT(15))
+#define GMAC_GFD_M  (GMAC_GFD_V << GMAC_GFD_S)
+#define GMAC_GFD_V  0x00000001U
+#define GMAC_GFD_S  15
+
+/** GMAC_REGISTER54_SGMII_RGMII_SMIICONTROLANDSTATUSREGISTER_REG register
+ *  Indicates the status signals received from the PHY through the SGMII, RGMII, or
+ *  SMII interface This register is present only when you select the SGMII, RGMII, or
+ *  SMII interface in coreConsultant
+ */
+#define GMAC_REGISTER54_SGMII_RGMII_SMIICONTROLANDSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0xd8)
+/** GMAC_LNKMOD : RO; bitpos: [0]; default: 0;
+ *  Link Mode This bit indicates the current mode of operation of the link: 1’b0:
+ *  Halfduplex mode 1’b1: Fullduplex mode
+ */
+#define GMAC_LNKMOD    (BIT(0))
+#define GMAC_LNKMOD_M  (GMAC_LNKMOD_V << GMAC_LNKMOD_S)
+#define GMAC_LNKMOD_V  0x00000001U
+#define GMAC_LNKMOD_S  0
+/** GMAC_LNKSPEED : RO; bitpos: [2:1]; default: 2;
+ *  Link Speed
+ */
+#define GMAC_LNKSPEED    0x00000003U
+#define GMAC_LNKSPEED_M  (GMAC_LNKSPEED_V << GMAC_LNKSPEED_S)
+#define GMAC_LNKSPEED_V  0x00000003U
+#define GMAC_LNKSPEED_S  1
+/** GMAC_LNKSTS : RO; bitpos: [3]; default: 0;
+ *  Link Status This bit indicates whether the link between the local PHY and the
+ *  remote PHY is up or down It gives the status of the link between the SGMII of MAC
+ *  and the SGMII of the local PHY The status bits are received from the local PHY
+ *  during ANEG between he MAC and PHY on the SGMII link
+ */
+#define GMAC_LNKSTS    (BIT(3))
+#define GMAC_LNKSTS_M  (GMAC_LNKSTS_V << GMAC_LNKSTS_S)
+#define GMAC_LNKSTS_V  0x00000001U
+#define GMAC_LNKSTS_S  3
+/** GMAC_JABTO : RO; bitpos: [4]; default: 0;
+ *  Jabber Timeout This bit indicates whether there is jabber timeout error _1'b1_ in
+ *  the received frame This bit is reserved when the MAC is configured for the SGMII or
+ *  RGMII PHY interface
+ */
+#define GMAC_JABTO    (BIT(4))
+#define GMAC_JABTO_M  (GMAC_JABTO_V << GMAC_JABTO_S)
+#define GMAC_JABTO_V  0x00000001U
+#define GMAC_JABTO_S  4
+/** GMAC_FALSCARDET : RO; bitpos: [5]; default: 0;
+ *  False Carrier Detected This bit indicates whether the SMII PHY detected false
+ *  carrier _1'b1_ This bit is reserved when the MAC is configured for the SGMII or
+ *  RGMII PHY interface
+ */
+#define GMAC_FALSCARDET    (BIT(5))
+#define GMAC_FALSCARDET_M  (GMAC_FALSCARDET_V << GMAC_FALSCARDET_S)
+#define GMAC_FALSCARDET_V  0x00000001U
+#define GMAC_FALSCARDET_S  5
+/** GMAC_SMIDRXS : R/W; bitpos: [16]; default: 0;
+ *  Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the
+ *  first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal When
+ *  reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal
+ *  If the SMII PHY Interface with source synchronous mode is selected during core
+ *  configuration, this bit is reserved _RO with default value_
+ */
+#define GMAC_SMIDRXS    (BIT(16))
+#define GMAC_SMIDRXS_M  (GMAC_SMIDRXS_V << GMAC_SMIDRXS_S)
+#define GMAC_SMIDRXS_V  0x00000001U
+#define GMAC_SMIDRXS_S  16
+
+/** GMAC_REGISTER55_WATCHDOGTIMEOUTREGISTER_REG register
+ *  Controls the watchdog timeout for received frames
+ */
+#define GMAC_REGISTER55_WATCHDOGTIMEOUTREGISTER_REG (DR_REG_GMAC_BASE + 0xdc)
+/** GMAC_WTO : R/W; bitpos: [13:0]; default: 0;
+ *  Watchdog Timeout When Bit 16 _PWE_ is set and Bit 23 _WD_ of Register 0 _MAC
+ *  Configuration Register_ is reset, this field is used as watchdog timeout for a
+ *  received frame If the length of a received frame exceeds the value of this field,
+ *  such frame is terminated and declared as an error frame Note: When Bit 16 _PWE_ is
+ *  set, the value in this field should be more than 1,522 _0x05F2_ Otherwise, the IEEE
+ *  Std 8023specified valid tagged frames are declared as error frames and are dropped
+ */
+#define GMAC_WTO    0x00003FFFU
+#define GMAC_WTO_M  (GMAC_WTO_V << GMAC_WTO_S)
+#define GMAC_WTO_V  0x00003FFFU
+#define GMAC_WTO_S  0
+/** GMAC_PWE : R/W; bitpos: [16]; default: 0;
+ *  Programmable Watchdog Enable When this bit is set and Bit 23 _WD_ of Register 0
+ *  _MAC Configuration Register_ is reset, the WTO field _Bits[13:0]_ is used as
+ *  watchdog timeout for a received frame When this bit is cleared, the watchdog
+ *  timeout for a received frame is controlled by the setting of Bit 23 _WD_ and Bit 20
+ *  _JE_ in Register 0 _MAC Configuration Register_
+ */
+#define GMAC_PWE    (BIT(16))
+#define GMAC_PWE_M  (GMAC_PWE_V << GMAC_PWE_S)
+#define GMAC_PWE_V  0x00000001U
+#define GMAC_PWE_S  16
+
+/** GMAC_REGISTER56_GENERALPURPOSEIOREGISTER_REG register
+ *  Provides the control to drive up to 4 bits of output ports _GPO_ and also provides
+ *  the status of up to 4 input ports _GPIS_
+ */
+#define GMAC_REGISTER56_GENERALPURPOSEIOREGISTER_REG (DR_REG_GMAC_BASE + 0xe0)
+/** GMAC_GPIS : R/W; bitpos: [3:0]; default: 0;
+ *  General Purpose Input Status This field gives the status of the signals connected
+ *  to the gpi_i input ports This field is of the following types based on the setting
+ *  of the corresponding GPIT field of this register: Latchedlow _LL_: This field is
+ *  cleared when the corresponding gpi_i input becomes low This field remains low until
+ *  the host reads this field After this, this field reflects the current value of the
+ *  gpi_i input Latchedhigh _LH_: This field is set when the corresponding gpi_i input
+ *  becomes high This field remains high until the host reads this field After this,
+ *  this field reflects the current value of the gpi_i input The number of bits
+ *  available in this field depend on the GP Input Signal Width option Other bits are
+ *  not used _reserved and always reset_
+ */
+#define GMAC_GPIS    0x0000000FU
+#define GMAC_GPIS_M  (GMAC_GPIS_V << GMAC_GPIS_S)
+#define GMAC_GPIS_V  0x0000000FU
+#define GMAC_GPIS_S  0
+/** GMAC_GPO : R/W; bitpos: [11:8]; default: 0;
+ *  General Purpose Output When this bit is set, it directly drives the gpo_o output
+ *  ports When this bit is reset, it does not directly drive the gpo_o output ports The
+ *  number of bits available in this field depend on the GP Output Signal Width option
+ *  Other bits are not used _reserved and always reset_
+ */
+#define GMAC_GPO    0x0000000FU
+#define GMAC_GPO_M  (GMAC_GPO_V << GMAC_GPO_S)
+#define GMAC_GPO_V  0x0000000FU
+#define GMAC_GPO_S  8
+/** GMAC_GPIE : R/W; bitpos: [19:16]; default: 0;
+ *  GPI Interrupt Enable When this bit is set and the programmed event _LL or LH_
+ *  occurs on the corresponding GPIS bit, Bit 11 _GPIIS_ of Register 14 _Interrupt
+ *  Status Register_ is set Accordingly, the interrupt is generated on the mci_intr_o
+ *  or sbd_intr_o The GPIIS bit is cleared when the host reads the Bits[7:0] of this
+ *  register When reset, Bit 11 _GPIIS_ of Register 14 _Interrupt Status Register_ is
+ *  not set when any event occurs on the corresponding GPIS bits The number of bits
+ *  available in this field depend on the GP Input Signal Width option Other bits are
+ *  not used _reserved and always reset_
+ */
+#define GMAC_GPIE    0x0000000FU
+#define GMAC_GPIE_M  (GMAC_GPIE_V << GMAC_GPIE_S)
+#define GMAC_GPIE_V  0x0000000FU
+#define GMAC_GPIE_S  16
+/** GMAC_GPIT : R/W; bitpos: [27:24]; default: 0;
+ *  GPI Type When set, this bit indicates that the corresponding GPIS is of latchedlow
+ *  _LL_ type When reset, this bit indicates that the corresponding GPIS is of
+ *  latchedhigh _LH_ type The number of bits available in this field depend on the GP
+ *  Input Signal Width option Other bits are not used _reserved and always reset_
+ */
+#define GMAC_GPIT    0x0000000FU
+#define GMAC_GPIT_M  (GMAC_GPIT_V << GMAC_GPIT_S)
+#define GMAC_GPIT_V  0x0000000FU
+#define GMAC_GPIT_S  24
+
+/** GMAC_REGISTER256_LAYER3ANDLAYER4CONTROLREGISTER0_REG register
+ *  Controls the operations of the Layer 3 and Layer 4 frame filtering
+ */
+#define GMAC_REGISTER256_LAYER3ANDLAYER4CONTROLREGISTER0_REG (DR_REG_GMAC_BASE + 0x400)
+/** GMAC_L3PEN0 : R/W; bitpos: [0]; default: 0;
+ *  Layer 3 Protocol Enable When set, this bit indicates that the Layer 3 IP Source or
+ *  Destination Address matching is enabled for the IPv6 frames When reset, this bit
+ *  indicates that the Layer 3 IP Source or Destination Address matching is enabled for
+ *  the IPv4 frames The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit
+ *  is set high
+ */
+#define GMAC_L3PEN0    (BIT(0))
+#define GMAC_L3PEN0_M  (GMAC_L3PEN0_V << GMAC_L3PEN0_S)
+#define GMAC_L3PEN0_V  0x00000001U
+#define GMAC_L3PEN0_S  0
+/** GMAC_L3SAM0 : R/W; bitpos: [2]; default: 0;
+ *  Layer 3 IP SA Match Enable When set, this bit indicates that the Layer 3 IP Source
+ *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+ *  Source Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should set
+ *  either this bit or Bit 4 _L3DAM0_ because either IPv6 SA or DA can be checked for
+ *  filtering
+ */
+#define GMAC_L3SAM0    (BIT(2))
+#define GMAC_L3SAM0_M  (GMAC_L3SAM0_V << GMAC_L3SAM0_S)
+#define GMAC_L3SAM0_V  0x00000001U
+#define GMAC_L3SAM0_S  2
+/** GMAC_L3SAIM0 : R/W; bitpos: [3]; default: 0;
+ *  Layer 3 IP SA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+ *  Source Address field is enabled for inverse matching When reset, this bit indicates
+ *  that the Layer 3 IP Source Address field is enabled for perfect matching This bit
+ *  is valid and applicable only when Bit 2 _L3SAM0_ is set high
+ */
+#define GMAC_L3SAIM0    (BIT(3))
+#define GMAC_L3SAIM0_M  (GMAC_L3SAIM0_V << GMAC_L3SAIM0_S)
+#define GMAC_L3SAIM0_V  0x00000001U
+#define GMAC_L3SAIM0_S  3
+/** GMAC_L3DAM0 : R/W; bitpos: [4]; default: 0;
+ *  Layer 3 IP DA Match Enable When set, this bit indicates that Layer 3 IP Destination
+ *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+ *  Destination Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should
+ *  set either this bit or Bit 2 _L3SAM0_ because either IPv6 DA or SA can be checked
+ *  for filtering
+ */
+#define GMAC_L3DAM0    (BIT(4))
+#define GMAC_L3DAM0_M  (GMAC_L3DAM0_V << GMAC_L3DAM0_S)
+#define GMAC_L3DAM0_V  0x00000001U
+#define GMAC_L3DAM0_S  4
+/** GMAC_L3DAIM0 : R/W; bitpos: [5]; default: 0;
+ *  Layer 3 IP DA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+ *  Destination Address field is enabled for inverse matching When reset, this bit
+ *  indicates that the Layer 3 IP Destination Address field is enabled for perfect
+ *  matching This bit is valid and applicable only when Bit 4 _L3DAM0_ is set high
+ */
+#define GMAC_L3DAIM0    (BIT(5))
+#define GMAC_L3DAIM0_M  (GMAC_L3DAIM0_V << GMAC_L3DAIM0_S)
+#define GMAC_L3DAIM0_V  0x00000001U
+#define GMAC_L3DAIM0_S  5
+/** GMAC_L3HSBM0 : R/W; bitpos: [10:6]; default: 0;
+ *  Layer 3 IP SA Higher Bits Match IPv4 Frames: This field contains the number of
+ *  lower bits of IP Source Address that are masked for matching in the IPv4 frames The
+ *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+ *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+ *  Frames: This field contains Bits [4:0] of the field that indicates the number of
+ *  higher bits of IP Source or Destination Address matched in the IPv6 frames This
+ *  field is valid and applicable only if L3DAM0 or L3SAM0 is set high
+ */
+#define GMAC_L3HSBM0    0x0000001FU
+#define GMAC_L3HSBM0_M  (GMAC_L3HSBM0_V << GMAC_L3HSBM0_S)
+#define GMAC_L3HSBM0_V  0x0000001FU
+#define GMAC_L3HSBM0_S  6
+/** GMAC_L3HDBM0 : R/W; bitpos: [15:11]; default: 0;
+ *  Layer 3 IP DA Higher Bits Match IPv4 Frames: This field contains the number of
+ *  higher bits of IP Destination Address that are matched in the IPv4 frames The
+ *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+ *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+ *  Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which
+ *  indicate the number of lower bits of IP Source or Destination Address that are
+ *  masked in the IPv6 frames The following list describes the concatenated values of
+ *  the L3HDBM0[1:0] and L3HSBM0 bits: 0: No bits are masked 1: LSb[0] is masked 2: Two
+ *  LSbs [1:0] are masked … 127: All bits except MSb are masked This field is valid and
+ *  applicable only if L3DAM0 or L3SAM0 is set high
+ */
+#define GMAC_L3HDBM0    0x0000001FU
+#define GMAC_L3HDBM0_M  (GMAC_L3HDBM0_V << GMAC_L3HDBM0_S)
+#define GMAC_L3HDBM0_V  0x0000001FU
+#define GMAC_L3HDBM0_S  11
+/** GMAC_L4PEN0 : R/W; bitpos: [16]; default: 0;
+ *  Layer 4 Protocol Enable When set, this bit indicates that the Source and
+ *  Destination Port number fields for UDP frames are used for matching When reset,
+ *  this bit indicates that the Source and Destination Port number fields for TCP
+ *  frames are used for matching The Layer 4 matching is done only when either L4SPM0
+ *  or L4DPM0 bit is set high
+ */
+#define GMAC_L4PEN0    (BIT(16))
+#define GMAC_L4PEN0_M  (GMAC_L4PEN0_V << GMAC_L4PEN0_S)
+#define GMAC_L4PEN0_V  0x00000001U
+#define GMAC_L4PEN0_S  16
+/** GMAC_L4SPM0 : R/W; bitpos: [18]; default: 0;
+ *  Layer 4 Source Port Match Enable When set, this bit indicates that the Layer 4
+ *  Source Port number field is enabled for matching When reset, the MAC ignores the
+ *  Layer 4 Source Port number field for matching
+ */
+#define GMAC_L4SPM0    (BIT(18))
+#define GMAC_L4SPM0_M  (GMAC_L4SPM0_V << GMAC_L4SPM0_S)
+#define GMAC_L4SPM0_V  0x00000001U
+#define GMAC_L4SPM0_S  18
+/** GMAC_L4SPIM0 : R/W; bitpos: [19]; default: 0;
+ *  Layer 4 Source Port Inverse Match Enable When set, this bit indicates that the
+ *  Layer 4 Source Port number field is enabled for inverse matching When reset, this
+ *  bit indicates that the Layer 4 Source Port number field is enabled for perfect
+ *  matching This bit is valid and applicable only when Bit 18 _L4SPM0_ is set high
+ */
+#define GMAC_L4SPIM0    (BIT(19))
+#define GMAC_L4SPIM0_M  (GMAC_L4SPIM0_V << GMAC_L4SPIM0_S)
+#define GMAC_L4SPIM0_V  0x00000001U
+#define GMAC_L4SPIM0_S  19
+/** GMAC_L4DPM0 : R/W; bitpos: [20]; default: 0;
+ *  Layer 4 Destination Port Match Enable When set, this bit indicates that the Layer 4
+ *  Destination Port number field is enabled for matching When reset, the MAC ignores
+ *  the Layer 4 Destination Port number field for matching
+ */
+#define GMAC_L4DPM0    (BIT(20))
+#define GMAC_L4DPM0_M  (GMAC_L4DPM0_V << GMAC_L4DPM0_S)
+#define GMAC_L4DPM0_V  0x00000001U
+#define GMAC_L4DPM0_S  20
+/** GMAC_L4DPIM0 : R/W; bitpos: [21]; default: 0;
+ *  Layer 4 Destination Port Inverse Match Enable When set, this bit indicates that the
+ *  Layer 4 Destination Port number field is enabled for inverse matching When reset,
+ *  this bit indicates that the Layer 4 Destination Port number field is enabled for
+ *  perfect matching This bit is valid and applicable only when Bit 20 _L4DPM0_ is set
+ *  high
+ */
+#define GMAC_L4DPIM0    (BIT(21))
+#define GMAC_L4DPIM0_M  (GMAC_L4DPIM0_V << GMAC_L4DPIM0_S)
+#define GMAC_L4DPIM0_V  0x00000001U
+#define GMAC_L4DPIM0_S  21
+
+/** GMAC_REGISTER257_LAYER4ADDRESSREGISTER0_REG register
+ *  Layer 4 Port number field It contains the 16bit Source and Destination Port numbers
+ *  of the TCP or UDP frame
+ */
+#define GMAC_REGISTER257_LAYER4ADDRESSREGISTER0_REG (DR_REG_GMAC_BASE + 0x404)
+/** GMAC_L4SP0 : R/W; bitpos: [15:0]; default: 0;
+ *  Layer 4 Source Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20 _L4DPM0_
+ *  is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this field
+ *  contains the value to be matched with the TCP Source Port Number field in the IPv4
+ *  or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in Register 256
+ *  _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with the UDP Source Port Number field in the IPv4 or IPv6 frames
+ */
+#define GMAC_L4SP0    0x0000FFFFU
+#define GMAC_L4SP0_M  (GMAC_L4SP0_V << GMAC_L4SP0_S)
+#define GMAC_L4SP0_V  0x0000FFFFU
+#define GMAC_L4SP0_S  0
+/** GMAC_L4DP0 : R/W; bitpos: [31:16]; default: 0;
+ *  Layer 4 Destination Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20
+ *  _L4DPM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+ *  field contains the value to be matched with the TCP Destination Port Number field
+ *  in the IPv4 or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in
+ *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this field contains the
+ *  value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6
+ *  frames
+ */
+#define GMAC_L4DP0    0x0000FFFFU
+#define GMAC_L4DP0_M  (GMAC_L4DP0_V << GMAC_L4DP0_S)
+#define GMAC_L4DP0_V  0x0000FFFFU
+#define GMAC_L4DP0_S  16
+
+/** GMAC_REGISTER260_LAYER3ADDRESS0REGISTER0_REG register
+ *  Layer 3 Address field For IPv4 frames, it contains the 32bit IP Source Address
+ *  field For IPv6 frames, it contains Bits [31:0] of the 128bit IP Source Address or
+ *  Destination Address field
+ */
+#define GMAC_REGISTER260_LAYER3ADDRESS0REGISTER0_REG (DR_REG_GMAC_BASE + 0x410)
+/** GMAC_L3A00 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 0 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [31:0] of the IP Source Address field in the IPv6 frames When Bit
+ *  0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4 Control
+ *  Register 0_, this field contains the value to be matched with Bits [31:0] of the IP
+ *  Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset and Bit 2
+ *  _L3SAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+ *  field contains the value to be matched with the IP Source Address field in the IPv4
+ *  frames
+ */
+#define GMAC_L3A00    0xFFFFFFFFU
+#define GMAC_L3A00_M  (GMAC_L3A00_V << GMAC_L3A00_S)
+#define GMAC_L3A00_V  0xFFFFFFFFU
+#define GMAC_L3A00_S  0
+
+/** GMAC_REGISTER261_LAYER3ADDRESS1REGISTER0_REG register
+ *  Layer 3 Address 1 field For IPv4 frames, it contains the 32bit IP Destination
+ *  Address field For IPv6 frames, it contains Bits [63:32] of the 128bit IP Source
+ *  Address or Destination Address field
+ */
+#define GMAC_REGISTER261_LAYER3ADDRESS1REGISTER0_REG (DR_REG_GMAC_BASE + 0x414)
+/** GMAC_L3A10 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 1 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [63:32] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains the value to be matched with Bits [63:32]
+ *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+ *  and Bit 4 _L3DAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_,
+ *  this field contains the value to be matched with the IP Destination Address field
+ *  in the IPv4 frames
+ */
+#define GMAC_L3A10    0xFFFFFFFFU
+#define GMAC_L3A10_M  (GMAC_L3A10_V << GMAC_L3A10_S)
+#define GMAC_L3A10_V  0xFFFFFFFFU
+#define GMAC_L3A10_S  0
+
+/** GMAC_REGISTER262_LAYER3ADDRESS2REGISTER0_REG register
+ *  Layer 3 Address 2 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [95:64] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+#define GMAC_REGISTER262_LAYER3ADDRESS2REGISTER0_REG (DR_REG_GMAC_BASE + 0x418)
+/** GMAC_L3A20 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 2 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [95:64] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains value to be matched with Bits [95:64] of
+ *  the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset in
+ *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+ */
+#define GMAC_L3A20    0xFFFFFFFFU
+#define GMAC_L3A20_M  (GMAC_L3A20_V << GMAC_L3A20_S)
+#define GMAC_L3A20_V  0xFFFFFFFFU
+#define GMAC_L3A20_S  0
+
+/** GMAC_REGISTER263_LAYER3ADDRESS3REGISTER0_REG register
+ *  Layer 3 Address 3 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [127:96] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+#define GMAC_REGISTER263_LAYER3ADDRESS3REGISTER0_REG (DR_REG_GMAC_BASE + 0x41c)
+/** GMAC_L3A30 : R/W; bitpos: [31:0]; default: 0;
+ *  Layer 3 Address 3 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+ *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+ *  matched with Bits [127:96] of the IP Source Address field in the IPv6 frames When
+ *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+ *  Control Register 0_, this field contains the value to be matched with Bits [127:96]
+ *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+ *  in Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+ */
+#define GMAC_L3A30    0xFFFFFFFFU
+#define GMAC_L3A30_M  (GMAC_L3A30_V << GMAC_L3A30_S)
+#define GMAC_L3A30_V  0xFFFFFFFFU
+#define GMAC_L3A30_S  0
+
+/** GMAC_REGISTER320_HASHTABLEREGISTER0_REG register
+ *  This register contains the first 32 bits of the hash table when the width of the
+ *  Hash table is 128 bits or 256 bits
+ */
+#define GMAC_REGISTER320_HASHTABLEREGISTER0_REG (DR_REG_GMAC_BASE + 0x500)
+/** GMAC_HT31T0 : R/W; bitpos: [31:0]; default: 0;
+ *  First 32 bits of Hash Table This field contains the first 32 Bits _31:0_ of the
+ *  Hash table Note Registers 321 through 327 are similar to Register 320 _Hash Table
+ *  Register 0_ Registers 324 through 327 are present only when you select the 256bit
+ *  Hash table during core configuration
+ */
+#define GMAC_HT31T0    0xFFFFFFFFU
+#define GMAC_HT31T0_M  (GMAC_HT31T0_V << GMAC_HT31T0_S)
+#define GMAC_HT31T0_V  0xFFFFFFFFU
+#define GMAC_HT31T0_S  0
+
+/** GMAC_REGISTER353_VLANTAGINCLUSIONORREPLACEMENTREGISTER_REG register
+ *  This register contains the VLAN tag for insertion into or replacement in the
+ *  transmit frames
+ */
+#define GMAC_REGISTER353_VLANTAGINCLUSIONORREPLACEMENTREGISTER_REG (DR_REG_GMAC_BASE + 0x584)
+/** GMAC_VLT : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Tag for Transmit Frames This field contains the value of the VLAN tag to be
+ *  inserted or replaced The value must only be changed when the transmit lines are
+ *  inactive or during the initialization phase Bits[15:13] are the User Priority, Bit
+ *  12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field
+ */
+#define GMAC_VLT    0x0000FFFFU
+#define GMAC_VLT_M  (GMAC_VLT_V << GMAC_VLT_S)
+#define GMAC_VLT_V  0x0000FFFFU
+#define GMAC_VLT_S  0
+/** GMAC_VLC : R/W; bitpos: [17:16]; default: 0;
+ *  VLAN Tag Control in Transmit Frames 2’b00: No VLAN tag deletion, insertion, or
+ *  replacement 2’b01: VLAN tag deletion The MAC removes the VLAN type _bytes 13 and
+ *  14_ and VLAN tag _bytes 15 and 16_ of all transmitted frames with VLAN tags 2’b10:
+ *  VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after
+ *  inserting the Type value _0x8100/0x88a8_ in bytes 13 and 14 This operation is
+ *  performed on all transmitted frames, irrespective of whether they already have a
+ *  VLAN tag 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all
+ *  VLANtype transmitted frames _Bytes 13 and 14 are 0x8100/0x88a8_ Note: Changes to
+ *  this field take effect only on the start of a frame If you write this register
+ *  field when a frame is being transmitted, only the subsequent frame can use the
+ *  updated value, that is, the current frame does not use the updated value
+ */
+#define GMAC_VLC    0x00000003U
+#define GMAC_VLC_M  (GMAC_VLC_V << GMAC_VLC_S)
+#define GMAC_VLC_V  0x00000003U
+#define GMAC_VLC_S  16
+/** GMAC_VLP : R/W; bitpos: [18]; default: 0;
+ *  VLAN Priority Control When this bit is set, the control Bits [17:16] are used for
+ *  VLAN deletion, insertion, or replacement When this bit is reset, the
+ *  mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored
+ */
+#define GMAC_VLP    (BIT(18))
+#define GMAC_VLP_M  (GMAC_VLP_V << GMAC_VLP_S)
+#define GMAC_VLP_V  0x00000001U
+#define GMAC_VLP_S  18
+/** GMAC_CSVL : R/W; bitpos: [19]; default: 0;
+ *  CVLAN or SVLAN When this bit is set, SVLAN type _0x88A8_ is inserted or replaced in
+ *  the 13th and 14th bytes of transmitted frames When this bit is reset, CVLAN type
+ *  _0x8100_ is inserted or replaced in the transmitted frames
+ */
+#define GMAC_CSVL    (BIT(19))
+#define GMAC_CSVL_M  (GMAC_CSVL_V << GMAC_CSVL_S)
+#define GMAC_CSVL_V  0x00000001U
+#define GMAC_CSVL_S  19
+
+/** GMAC_REGISTER354_VLANHASHTABLEREGISTER_REG register
+ *  This register contains the VLAN hash table
+ */
+#define GMAC_REGISTER354_VLANHASHTABLEREGISTER_REG (DR_REG_GMAC_BASE + 0x588)
+/** GMAC_VLHT : R/W; bitpos: [15:0]; default: 0;
+ *  VLAN Hash Table This field contains the 16bit VLAN Hash Table
+ */
+#define GMAC_VLHT    0x0000FFFFU
+#define GMAC_VLHT_M  (GMAC_VLHT_V << GMAC_VLHT_S)
+#define GMAC_VLHT_V  0x0000FFFFU
+#define GMAC_VLHT_S  0
+
+/** GMAC_REGISTER448_TIMESTAMPCONTROLREGISTER_REG register
+ *  Controls the timestamp generation and update logic This register is present only
+ *  when IEEE1588 timestamping is enabled during coreConsultant configuration
+ */
+#define GMAC_REGISTER448_TIMESTAMPCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x700)
+/** GMAC_TSENA : R/W; bitpos: [0]; default: 0;
+ *  Timestamp Enable When set, the timestamp is added for the transmit and receive
+ *  frames When disabled, timestamp is not added for the transmit and receive frames
+ *  and the Timestamp Generator is also suspended You need to initialize the Timestamp
+ *  _system time_ after enabling this mode On the receive side, the MAC processes the
+ *  1588 frames only if this bit is set
+ */
+#define GMAC_TSENA    (BIT(0))
+#define GMAC_TSENA_M  (GMAC_TSENA_V << GMAC_TSENA_S)
+#define GMAC_TSENA_V  0x00000001U
+#define GMAC_TSENA_S  0
+/** GMAC_TSCFUPDT : R/W; bitpos: [1]; default: 0;
+ *  Timestamp Fine or Coarse Update When set, this bit indicates that the system times
+ *  update should be done using the fine update method When reset, it indicates the
+ *  system timestamp update should be done using the Coarse method
+ */
+#define GMAC_TSCFUPDT    (BIT(1))
+#define GMAC_TSCFUPDT_M  (GMAC_TSCFUPDT_V << GMAC_TSCFUPDT_S)
+#define GMAC_TSCFUPDT_V  0x00000001U
+#define GMAC_TSCFUPDT_S  1
+/** GMAC_TSINIT : R/W1S; bitpos: [2]; default: 0;
+ *  Timestamp Initialize When set, the system time is initialized _overwritten_ with
+ *  the value specified in the Register 452 _System Time  Seconds Update Register_ and
+ *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+ *  zero before updating it This bit is reset when the initialization is complete The
+ *  “Timestamp Higher Word” register _if enabled during core configuration_ can only be
+ *  initialized
+ */
+#define GMAC_TSINIT    (BIT(2))
+#define GMAC_TSINIT_M  (GMAC_TSINIT_V << GMAC_TSINIT_S)
+#define GMAC_TSINIT_V  0x00000001U
+#define GMAC_TSINIT_S  2
+/** GMAC_TSUPDT : R/W1S; bitpos: [3]; default: 0;
+ *  Timestamp Update When set, the system time is updated _added or subtracted_ with
+ *  the value specified in Register 452 _System Time  Seconds Update Register_ and
+ *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+ *  zero before updating it This bit is reset when the update is completed in hardware
+ *  The “Timestamp Higher Word” register _if enabled during core configuration_ is not
+ *  updated
+ */
+#define GMAC_TSUPDT    (BIT(3))
+#define GMAC_TSUPDT_M  (GMAC_TSUPDT_V << GMAC_TSUPDT_S)
+#define GMAC_TSUPDT_V  0x00000001U
+#define GMAC_TSUPDT_S  3
+/** GMAC_TSTRIG : R/W1S; bitpos: [4]; default: 0;
+ *  Timestamp Interrupt Trigger Enable When set, the timestamp interrupt is generated
+ *  when the System Time becomes greater than the value written in the Target Time
+ *  register This bit is reset after the generation of the Timestamp Trigger Interrupt
+ */
+#define GMAC_TSTRIG    (BIT(4))
+#define GMAC_TSTRIG_M  (GMAC_TSTRIG_V << GMAC_TSTRIG_S)
+#define GMAC_TSTRIG_V  0x00000001U
+#define GMAC_TSTRIG_S  4
+/** GMAC_TSADDREG : R/W1S; bitpos: [5]; default: 0;
+ *  Addend Reg Update When set, the content of the Timestamp Addend register is updated
+ *  in the PTP block for fine correction This is cleared when the update is completed
+ *  This register bit should be zero before setting it
+ */
+#define GMAC_TSADDREG    (BIT(5))
+#define GMAC_TSADDREG_M  (GMAC_TSADDREG_V << GMAC_TSADDREG_S)
+#define GMAC_TSADDREG_V  0x00000001U
+#define GMAC_TSADDREG_S  5
+/** GMAC_TSENALL : R/W; bitpos: [8]; default: 0;
+ *  Enable Timestamp for All Frames When set, the timestamp snapshot is enabled for all
+ *  frames received by the MAC
+ */
+#define GMAC_TSENALL    (BIT(8))
+#define GMAC_TSENALL_M  (GMAC_TSENALL_V << GMAC_TSENALL_S)
+#define GMAC_TSENALL_V  0x00000001U
+#define GMAC_TSENALL_S  8
+/** GMAC_TSCTRLSSR : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Digital or Binary Rollover Control When set, the Timestamp Low register
+ *  rolls over after 0x3B9A_C9FF value _that is, 1 nanosecond accuracy_ and increments
+ *  the timestamp _High_ seconds When reset, the rollover value of subsecond register
+ *  is 0x7FFF_FFFF The subsecond increment has to be programmed correctly depending on
+ *  the PTP reference clock frequency and the value of this bit
+ */
+#define GMAC_TSCTRLSSR    (BIT(9))
+#define GMAC_TSCTRLSSR_M  (GMAC_TSCTRLSSR_V << GMAC_TSCTRLSSR_S)
+#define GMAC_TSCTRLSSR_V  0x00000001U
+#define GMAC_TSCTRLSSR_S  9
+/** GMAC_TSVER2ENA : R/W; bitpos: [10]; default: 0;
+ *  Enable PTP packet Processing for Version 2 Format When set, the PTP packets are
+ *  processed using the 1588 version 2 format Otherwise, the PTP packets are processed
+ *  using the version 1 format The IEEE 1588 Version 1 and Version 2 format are
+ *  described in “PTP Processing and Control” on page 155
+ */
+#define GMAC_TSVER2ENA    (BIT(10))
+#define GMAC_TSVER2ENA_M  (GMAC_TSVER2ENA_V << GMAC_TSVER2ENA_S)
+#define GMAC_TSVER2ENA_V  0x00000001U
+#define GMAC_TSVER2ENA_S  10
+/** GMAC_TSIPENA : R/W; bitpos: [11]; default: 0;
+ *  Enable Processing of PTP over Ethernet Frames When set, the MAC receiver processes
+ *  the PTP packets encapsulated directly in the Ethernet frames When this bit is
+ *  clear, the MAC ignores the PTP over Ethernet packets
+ */
+#define GMAC_TSIPENA    (BIT(11))
+#define GMAC_TSIPENA_M  (GMAC_TSIPENA_V << GMAC_TSIPENA_S)
+#define GMAC_TSIPENA_V  0x00000001U
+#define GMAC_TSIPENA_S  11
+/** GMAC_TSIPV6ENA : R/W; bitpos: [12]; default: 0;
+ *  Enable Processing of PTP Frames Sent over IPv6UDP When set, the MAC receiver
+ *  processes PTP packets encapsulated in UDP over IPv6 packets When this bit is clear,
+ *  the MAC ignores the PTP transported over UDPIPv6 packets
+ */
+#define GMAC_TSIPV6ENA    (BIT(12))
+#define GMAC_TSIPV6ENA_M  (GMAC_TSIPV6ENA_V << GMAC_TSIPV6ENA_S)
+#define GMAC_TSIPV6ENA_V  0x00000001U
+#define GMAC_TSIPV6ENA_S  12
+/** GMAC_TSIPV4ENA : R/W; bitpos: [13]; default: 1;
+ *  Enable Processing of PTP Frames Sent over IPv4UDP When set, the MAC receiver
+ *  processes the PTP packets encapsulated in UDP over IPv4 packets When this bit is
+ *  clear, the MAC ignores the PTP transported over UDPIPv4 packets This bit is set by
+ *  default
+ */
+#define GMAC_TSIPV4ENA    (BIT(13))
+#define GMAC_TSIPV4ENA_M  (GMAC_TSIPV4ENA_V << GMAC_TSIPV4ENA_S)
+#define GMAC_TSIPV4ENA_V  0x00000001U
+#define GMAC_TSIPV4ENA_S  13
+/** GMAC_TSEVNTENA : R/W; bitpos: [14]; default: 0;
+ *  Enable Timestamp Snapshot for Event Messages When set, the timestamp snapshot is
+ *  taken only for event messages _SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp_ When
+ *  reset, the snapshot is taken for all messages except Announce, Management, and
+ *  Signaling For more information about the timestamp snapshots, see Table 670 on page
+ *  462
+ */
+#define GMAC_TSEVNTENA    (BIT(14))
+#define GMAC_TSEVNTENA_M  (GMAC_TSEVNTENA_V << GMAC_TSEVNTENA_S)
+#define GMAC_TSEVNTENA_V  0x00000001U
+#define GMAC_TSEVNTENA_S  14
+/** GMAC_TSMSTRENA : R/W; bitpos: [15]; default: 0;
+ *  Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken
+ *  only for the messages relevant to the master node Otherwise, the snapshot is taken
+ *  for the messages relevant to the slave node
+ */
+#define GMAC_TSMSTRENA    (BIT(15))
+#define GMAC_TSMSTRENA_M  (GMAC_TSMSTRENA_V << GMAC_TSMSTRENA_S)
+#define GMAC_TSMSTRENA_V  0x00000001U
+#define GMAC_TSMSTRENA_S  15
+/** GMAC_SNAPTYPSEL : R/W; bitpos: [17:16]; default: 0;
+ *  Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide
+ *  the set of PTP packet types for which snapshot needs to be taken The encoding is
+ *  given in Table 670 on page 462
+ */
+#define GMAC_SNAPTYPSEL    0x00000003U
+#define GMAC_SNAPTYPSEL_M  (GMAC_SNAPTYPSEL_V << GMAC_SNAPTYPSEL_S)
+#define GMAC_SNAPTYPSEL_V  0x00000003U
+#define GMAC_SNAPTYPSEL_S  16
+/** GMAC_TSENMACADDR : R/W; bitpos: [18]; default: 0;
+ *  Enable MAC address for PTP Frame Filtering When set, the DA MAC address _that
+ *  matches any MAC Address register_ is used to filter the PTP frames when PTP is
+ *  directly sent over Ethernet
+ */
+#define GMAC_TSENMACADDR    (BIT(18))
+#define GMAC_TSENMACADDR_M  (GMAC_TSENMACADDR_V << GMAC_TSENMACADDR_S)
+#define GMAC_TSENMACADDR_V  0x00000001U
+#define GMAC_TSENMACADDR_S  18
+/** GMAC_ATSFC : R/W1S; bitpos: [24]; default: 0;
+ *  Auxiliary Snapshot FIFO Clear When set, it resets the pointers of the Auxiliary
+ *  Snapshot FIFO This bit is cleared when the pointers are reset and the FIFO is empty
+ *  When this bit is high, auxiliary snapshots get stored in the FIFO This bit is
+ *  reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during
+ *  core configuration
+ */
+#define GMAC_ATSFC    (BIT(24))
+#define GMAC_ATSFC_M  (GMAC_ATSFC_V << GMAC_ATSFC_S)
+#define GMAC_ATSFC_V  0x00000001U
+#define GMAC_ATSFC_S  24
+/** GMAC_ATSEN0 : R/W; bitpos: [25]; default: 0;
+ *  Auxiliary Snapshot 0 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 0 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[0] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration
+ */
+#define GMAC_ATSEN0    (BIT(25))
+#define GMAC_ATSEN0_M  (GMAC_ATSEN0_V << GMAC_ATSEN0_S)
+#define GMAC_ATSEN0_V  0x00000001U
+#define GMAC_ATSEN0_S  25
+/** GMAC_ATSEN1 : R/W; bitpos: [26]; default: 0;
+ *  Auxiliary Snapshot 1 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 1 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[1] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than two
+ */
+#define GMAC_ATSEN1    (BIT(26))
+#define GMAC_ATSEN1_M  (GMAC_ATSEN1_V << GMAC_ATSEN1_S)
+#define GMAC_ATSEN1_V  0x00000001U
+#define GMAC_ATSEN1_S  26
+/** GMAC_ATSEN2 : R/W; bitpos: [27]; default: 0;
+ *  Auxiliary Snapshot 2 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 2 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[2] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than three
+ */
+#define GMAC_ATSEN2    (BIT(27))
+#define GMAC_ATSEN2_M  (GMAC_ATSEN2_V << GMAC_ATSEN2_S)
+#define GMAC_ATSEN2_V  0x00000001U
+#define GMAC_ATSEN2_S  27
+/** GMAC_ATSEN3 : R/W; bitpos: [28]; default: 0;
+ *  Auxiliary Snapshot 3 Enable This field controls capturing the Auxiliary Snapshot
+ *  Trigger 3 When this bit is set, the Auxiliary snapshot of event on
+ *  ptp_aux_trig_i[3] input is enabled When this bit is reset, the events on this input
+ *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+ *  is not selected during core configuration or the selected number in the Number of
+ *  IEEE 1588 Auxiliary Snapshot Inputs option is less than four
+ */
+#define GMAC_ATSEN3    (BIT(28))
+#define GMAC_ATSEN3_M  (GMAC_ATSEN3_V << GMAC_ATSEN3_S)
+#define GMAC_ATSEN3_V  0x00000001U
+#define GMAC_ATSEN3_S  28
+
+/** GMAC_REGISTER449_SUBSECONDINCREMENTREGISTER_REG register
+ *  Contains the 8bit value by which the SubSecond register is incremented This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define GMAC_REGISTER449_SUBSECONDINCREMENTREGISTER_REG (DR_REG_GMAC_BASE + 0x704)
+/** GMAC_SSINC : R/W; bitpos: [7:0]; default: 0;
+ *  Subsecond Increment Value The value programmed in this field is accumulated every
+ *  clock cycle _of clk_ptp_i_ with the contents of the subsecond register For example,
+ *  when PTP clock is 50 MHz _period is 20 ns_, you should program 20 _0x14_ when the
+ *  System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 _TSCTRLSSR_ is set
+ *  in Register 448 _Timestamp Control Register_] When TSCTRLSSR is clear, the
+ *  Nanoseconds register has a resolution of ~0465ns In this case, you should program a
+ *  value of 43 _0x2B_ that is derived by 20ns/0465
+ */
+#define GMAC_SSINC    0x000000FFU
+#define GMAC_SSINC_M  (GMAC_SSINC_V << GMAC_SSINC_S)
+#define GMAC_SSINC_V  0x000000FFU
+#define GMAC_SSINC_S  0
+
+/** GMAC_REGISTER450_SYSTEMTIMESECONDSREGISTER_REG register
+ *  Contains the lower 32 bits of the seconds field of the system time This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input
+ */
+#define GMAC_REGISTER450_SYSTEMTIMESECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x708)
+/** GMAC_TSS_RO : RO; bitpos: [31:0]; default: 0;
+ *  Timestamp Second The value in this field indicates the current value in seconds of
+ *  the System Time maintained by the MAC
+ */
+#define GMAC_TSS_RO    0xFFFFFFFFU
+#define GMAC_TSS_RO_M  (GMAC_TSS_RO_V << GMAC_TSS_RO_S)
+#define GMAC_TSS_RO_V  0xFFFFFFFFU
+#define GMAC_TSS_RO_S  0
+
+/** GMAC_REGISTER451_SYSTEMTIMENANOSECONDSREGISTER_REG register
+ *  Contains 32 bits of the nanoseconds field of the system time This register is only
+ *  present when IEEE1588 timestamping is enabled without an external timestamp input
+ */
+#define GMAC_REGISTER451_SYSTEMTIMENANOSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x70c)
+/** GMAC_TSSS_RO : RO; bitpos: [30:0]; default: 0;
+ *  Timestamp Sub Seconds The value in this field has the sub second representation of
+ *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+ *  _Timestamp Control Register_, each bit represents 1 ns and the maximum value is
+ *  0x3B9A_C9FF, after which it rollsover to zero
+ */
+#define GMAC_TSSS_RO    0x7FFFFFFFU
+#define GMAC_TSSS_RO_M  (GMAC_TSSS_RO_V << GMAC_TSSS_RO_S)
+#define GMAC_TSSS_RO_V  0x7FFFFFFFU
+#define GMAC_TSSS_RO_S  0
+
+/** GMAC_REGISTER452_SYSTEMTIMESECONDSUPDATEREGISTER_REG register
+ *  Contains the lower 32 bits of the seconds field to be written to, added to, or
+ *  subtracted from the System Time value This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+#define GMAC_REGISTER452_SYSTEMTIMESECONDSUPDATEREGISTER_REG (DR_REG_GMAC_BASE + 0x710)
+/** GMAC_TSS : R/W; bitpos: [31:0]; default: 0;
+ *  TIMESTAMP SECOND THE VALUE IN THIS FIELD INDICATES THE TIME IN SECONDS TO BE
+ *  INITIALIZED OR ADDED TO THE SYSTEM TIME
+ */
+#define GMAC_TSS    0xFFFFFFFFU
+#define GMAC_TSS_M  (GMAC_TSS_V << GMAC_TSS_S)
+#define GMAC_TSS_V  0xFFFFFFFFU
+#define GMAC_TSS_S  0
+
+/** GMAC_REGISTER453_SYSTEMTIMENANOSECONDSUPDATEREGISTER_REG register
+ *  Contains 32 bits of the nanoseconds field to be written to, added to, or subtracted
+ *  from the System Time value This register is only present when IEEE1588 timestamping
+ *  is enabled without an external timestamp input
+ */
+#define GMAC_REGISTER453_SYSTEMTIMENANOSECONDSUPDATEREGISTER_REG (DR_REG_GMAC_BASE + 0x714)
+/** GMAC_TSSS : R/W; bitpos: [30:0]; default: 0;
+ *  Timestamp Sub Seconds The value in this field has the sub second representation of
+ *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+ *  _Timestamp Control Register_, each bit represents 1 ns and the programmed value
+ *  should not exceed 0x3B9A_C9FF
+ */
+#define GMAC_TSSS    0x7FFFFFFFU
+#define GMAC_TSSS_M  (GMAC_TSSS_V << GMAC_TSSS_S)
+#define GMAC_TSSS_V  0x7FFFFFFFU
+#define GMAC_TSSS_S  0
+/** GMAC_ADDSUB : R/W; bitpos: [31]; default: 0;
+ *  Add or Subtract Time When this bit is set, the time value is subtracted with the
+ *  contents of the update register When this bit is reset, the time value is added
+ *  with the contents of the update register
+ */
+#define GMAC_ADDSUB    (BIT(31))
+#define GMAC_ADDSUB_M  (GMAC_ADDSUB_V << GMAC_ADDSUB_S)
+#define GMAC_ADDSUB_V  0x00000001U
+#define GMAC_ADDSUB_S  31
+
+/** GMAC_REGISTER454_TIMESTAMPADDENDREGISTER_REG register
+ *  This register is used by the software to readjust the clock frequency linearly to
+ *  match the master clock frequency This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+#define GMAC_REGISTER454_TIMESTAMPADDENDREGISTER_REG (DR_REG_GMAC_BASE + 0x718)
+/** GMAC_TSAR : R/W; bitpos: [31:0]; default: 0;
+ *  Timestamp Addend Register This field indicates the 32bit time value to be added to
+ *  the Accumulator register to achieve time synchronization
+ */
+#define GMAC_TSAR    0xFFFFFFFFU
+#define GMAC_TSAR_M  (GMAC_TSAR_V << GMAC_TSAR_S)
+#define GMAC_TSAR_V  0xFFFFFFFFU
+#define GMAC_TSAR_S  0
+
+/** GMAC_REGISTER455_TARGETTIMESECONDSREGISTER_REG register
+ *  Contains the higher 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define GMAC_REGISTER455_TARGETTIMESECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x71c)
+/** GMAC_TSTR : R/W; bitpos: [31:0]; default: 0;
+ *  Target Time Seconds Register This register stores the time in seconds When the
+ *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+ *  Bits [6:5] of Register 459 _PPS Control Register_, the MAC starts or stops the PPS
+ *  signal output and generates an interrupt _if enabled_
+ */
+#define GMAC_TSTR    0xFFFFFFFFU
+#define GMAC_TSTR_M  (GMAC_TSTR_V << GMAC_TSTR_S)
+#define GMAC_TSTR_V  0xFFFFFFFFU
+#define GMAC_TSTR_S  0
+
+/** GMAC_REGISTER456_TARGETTIMENANOSECONDSREGISTER_REG register
+ *  Contains the lower 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+#define GMAC_REGISTER456_TARGETTIMENANOSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x720)
+/** GMAC_TTSLO : R/W; bitpos: [30:0]; default: 0;
+ *  Target Timestamp Low Register This register stores the time in _signed_ nanoseconds
+ *  When the value of the timestamp matches the both Target Timestamp registers, then
+ *  based on the TRGTMODSEL0 field _Bits [6:5]_ in Register 459 _PPS Control Register_,
+ *  the MAC starts or stops the PPS signal output and generates an interrupt _if
+ *  enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9 _TSCTRLSSR_ is set in
+ *  Register 448 _Timestamp Control Register_ The actual start or stop time of the PPS
+ *  signal output may have an error margin up to one unit of subsecond increment value
+ */
+#define GMAC_TTSLO    0x7FFFFFFFU
+#define GMAC_TTSLO_M  (GMAC_TTSLO_V << GMAC_TTSLO_S)
+#define GMAC_TTSLO_V  0x7FFFFFFFU
+#define GMAC_TTSLO_S  0
+/** GMAC_TRGTBUSY : R/W1S; bitpos: [31]; default: 0;
+ *  Target Time Register Busy The MAC sets this bit when the PPSCMD field _Bit [3:0]_
+ *  in Register 459 _PPS Control Register_ is programmed to 010 or 011 Programming the
+ *  PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time
+ *  Registers to the PTP clock domain The MAC clears this bit after synchronizing the
+ *  Target Time Registers to the PTP clock domain The application must not update the
+ *  Target Time Registers when this bit is read as 1 Otherwise, the synchronization of
+ *  the previous programmed time gets corrupted This bit is reserved when the Enable
+ *  Flexible PulsePerSecond Output feature is not selected
+ */
+#define GMAC_TRGTBUSY    (BIT(31))
+#define GMAC_TRGTBUSY_M  (GMAC_TRGTBUSY_V << GMAC_TRGTBUSY_S)
+#define GMAC_TRGTBUSY_V  0x00000001U
+#define GMAC_TRGTBUSY_S  31
+
+/** GMAC_REGISTER457_SYSTEMTIMEHIGHERWORDSECONDSREGISTER_REG register
+ *  Contains the most significant 16bits of the timestamp seconds value This register
+ *  is optional and can be selected using the parameter mentioned in “IEEE 1588
+ *  Timestamp Block” on page 492
+ */
+#define GMAC_REGISTER457_SYSTEMTIMEHIGHERWORDSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x724)
+/** GMAC_TSHWR : R/W; bitpos: [15:0]; default: 0;
+ *  Timestamp Higher Word Register This field contains the most significant 16bits of
+ *  the timestamp seconds value This register is optional and can be selected using the
+ *  Enable IEEE 1588 Higher Word Register option during core configuration The register
+ *  is directly written to initialize the value This register is incremented when there
+ *  is an overflow from the 32bits of the System Time  Seconds register
+ */
+#define GMAC_TSHWR    0x0000FFFFU
+#define GMAC_TSHWR_M  (GMAC_TSHWR_V << GMAC_TSHWR_S)
+#define GMAC_TSHWR_V  0x0000FFFFU
+#define GMAC_TSHWR_S  0
+
+/** GMAC_REGISTER458_TIMESTAMPSTATUSREGISTER_REG register
+ *  Contains the PTP status This register is available only when the advanced IEEE 1588
+ *  timestamp feature is selected
+ */
+#define GMAC_REGISTER458_TIMESTAMPSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x728)
+/** GMAC_TSSOVF : R/W; bitpos: [0]; default: 0;
+ *  Timestamp Seconds Overflow When set, this bit indicates that the seconds value of
+ *  the timestamp _when supporting version 2 format_ has overflowed beyond 32’hFFFF_FFFF
+ */
+#define GMAC_TSSOVF    (BIT(0))
+#define GMAC_TSSOVF_M  (GMAC_TSSOVF_V << GMAC_TSSOVF_S)
+#define GMAC_TSSOVF_V  0x00000001U
+#define GMAC_TSSOVF_S  0
+/** GMAC_TSTARGT : R/W; bitpos: [1]; default: 0;
+ *  Timestamp Target Time Reached When set, this bit indicates that the value of system
+ *  time is greater than or equal to the value specified in the Register 455 _Target
+ *  Time Seconds Register_ and Register 456 _Target Time Nanoseconds Register_
+ */
+#define GMAC_TSTARGT    (BIT(1))
+#define GMAC_TSTARGT_M  (GMAC_TSTARGT_V << GMAC_TSTARGT_S)
+#define GMAC_TSTARGT_V  0x00000001U
+#define GMAC_TSTARGT_S  1
+/** GMAC_AUXTSTRIG : R/W; bitpos: [2]; default: 0;
+ *  Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary
+ *  snapshot is written to the FIFO This bit is valid only if the Enable IEEE 1588
+ *  Auxiliary Snapshot feature is selected
+ */
+#define GMAC_AUXTSTRIG    (BIT(2))
+#define GMAC_AUXTSTRIG_M  (GMAC_AUXTSTRIG_V << GMAC_AUXTSTRIG_S)
+#define GMAC_AUXTSTRIG_V  0x00000001U
+#define GMAC_AUXTSTRIG_S  2
+/** GMAC_TSTRGTERR : R/W; bitpos: [3]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 455 and Register 456, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define GMAC_TSTRGTERR    (BIT(3))
+#define GMAC_TSTRGTERR_M  (GMAC_TSTRGTERR_V << GMAC_TSTRGTERR_S)
+#define GMAC_TSTRGTERR_V  0x00000001U
+#define GMAC_TSTRGTERR_S  3
+/** GMAC_TSTARGT1 : R/W; bitpos: [4]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 480 _PPS1 Target Time High Register_ and Register 481 _PPS1 Target Time
+ *  Low Register_
+ */
+#define GMAC_TSTARGT1    (BIT(4))
+#define GMAC_TSTARGT1_M  (GMAC_TSTARGT1_V << GMAC_TSTARGT1_S)
+#define GMAC_TSTARGT1_V  0x00000001U
+#define GMAC_TSTARGT1_S  4
+/** GMAC_TSTRGTERR1 : R/W; bitpos: [5]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 480 and Register 481, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define GMAC_TSTRGTERR1    (BIT(5))
+#define GMAC_TSTRGTERR1_M  (GMAC_TSTRGTERR1_V << GMAC_TSTRGTERR1_S)
+#define GMAC_TSTRGTERR1_V  0x00000001U
+#define GMAC_TSTRGTERR1_S  5
+/** GMAC_TSTARGT2 : R/W; bitpos: [6]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 488 _PPS2 Target Time High Register_ and Register 489 _PPS2 Target Time
+ *  Low Register_
+ */
+#define GMAC_TSTARGT2    (BIT(6))
+#define GMAC_TSTARGT2_M  (GMAC_TSTARGT2_V << GMAC_TSTARGT2_S)
+#define GMAC_TSTARGT2_V  0x00000001U
+#define GMAC_TSTARGT2_S  6
+/** GMAC_TSTRGTERR2 : R/W; bitpos: [7]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 488 and Register 489, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define GMAC_TSTRGTERR2    (BIT(7))
+#define GMAC_TSTRGTERR2_M  (GMAC_TSTRGTERR2_V << GMAC_TSTRGTERR2_S)
+#define GMAC_TSTRGTERR2_V  0x00000001U
+#define GMAC_TSTRGTERR2_S  7
+/** GMAC_TSTARGT3 : R/W; bitpos: [8]; default: 0;
+ *  Timestamp Target Time Reached for Target Time PPS3 When set, this bit indicates
+ *  that the value of system time is greater than or equal to the value specified in
+ *  Register 496 _PPS3 Target Time High Register_ and Register 497 _PPS3 Target Time
+ *  Low Register_
+ */
+#define GMAC_TSTARGT3    (BIT(8))
+#define GMAC_TSTARGT3_M  (GMAC_TSTARGT3_V << GMAC_TSTARGT3_S)
+#define GMAC_TSTARGT3_V  0x00000001U
+#define GMAC_TSTARGT3_S  8
+/** GMAC_TSTRGTERR3 : R/W; bitpos: [9]; default: 0;
+ *  Timestamp Target Time Error This bit is set when the target time, being programmed
+ *  in Register 496 and Register 497, is already elapsed This bit is cleared when read
+ *  by the application
+ */
+#define GMAC_TSTRGTERR3    (BIT(9))
+#define GMAC_TSTRGTERR3_M  (GMAC_TSTRGTERR3_V << GMAC_TSTRGTERR3_S)
+#define GMAC_TSTRGTERR3_V  0x00000001U
+#define GMAC_TSTRGTERR3_S  9
+/** GMAC_ATSSTN : R/W; bitpos: [19:16]; default: 0;
+ *  Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
+ *  trigger inputs for which the timestamp available in the Auxiliary Snapshot Register
+ *  is applicable When more than one bit is set at the same time, it means that
+ *  corresponding auxiliary triggers were sampled at the same clock These bits are
+ *  applicable only if the number of Auxiliary snapshots is more than one One bit is
+ *  assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger
+ *  0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger
+ *  3 The software can read this register to find the triggers that are set when the
+ *  timestamp is taken
+ */
+#define GMAC_ATSSTN    0x0000000FU
+#define GMAC_ATSSTN_M  (GMAC_ATSSTN_V << GMAC_ATSSTN_S)
+#define GMAC_ATSSTN_V  0x0000000FU
+#define GMAC_ATSSTN_S  16
+/** GMAC_ATSSTM : RO; bitpos: [24]; default: 0;
+ *  Auxiliary Timestamp Snapshot Trigger Missed
+ */
+#define GMAC_ATSSTM    (BIT(24))
+#define GMAC_ATSSTM_M  (GMAC_ATSSTM_V << GMAC_ATSSTM_S)
+#define GMAC_ATSSTM_V  0x00000001U
+#define GMAC_ATSSTM_S  24
+/** GMAC_ATSNS : RO; bitpos: [29:25]; default: 0;
+ *  Number of Auxiliary Timestamp Snapshots This field indicates the number of
+ *  Snapshots available in the FIFO A value equal to the selected depth of FIFO _4, 8,
+ *  or 16_ indicates that the Auxiliary Snapshot FIFO is full These bits are cleared
+ *  _to 00000_ when the Auxiliary snapshot FIFO clear bit is set This bit is valid only
+ *  if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration
+ */
+#define GMAC_ATSNS    0x0000001FU
+#define GMAC_ATSNS_M  (GMAC_ATSNS_V << GMAC_ATSNS_S)
+#define GMAC_ATSNS_V  0x0000001FU
+#define GMAC_ATSNS_S  25
+
+/** GMAC_REGISTER459_PPSCONTROLREGISTER_REG register
+ *  This register is used to control the interval of the PPS signal output This
+ *  register is available only when the advanced IEEE 1588 timestamp feature is selected
+ */
+#define GMAC_REGISTER459_PPSCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x72c)
+/** GMAC_PPSCTRL0 : R/W1S; bitpos: [3:0]; default: 0;
+ *  PPSCTRL0: PPS0 Output Frequency Control This field controls the frequency of the
+ *  PPS0 output _ptp_pps_o[0]_ signal The default value of PPSCTRL is 0000, and the PPS
+ *  output is 1 pulse _of width clk_ptp_i_ every second For other values of PPSCTRL,
+ *  the PPS output becomes a generated clock of following frequencies: 0001: The binary
+ *  rollover is 2 Hz, and the digital rollover is 1 Hz 0010: The binary rollover is 4
+ *  Hz, and the digital rollover is 2 Hz 0011: The binary rollover is 8 Hz, and the
+ *  digital rollover is 4 Hz 0100: The binary rollover is 16 Hz, and the digital
+ *  rollover is 8 Hz  1111: The binary rollover is 32768 KHz, and the digital rollover
+ *  is 16384 KHz Note: In the binary rollover mode, the PPS output _ptp_pps_o_ has a
+ *  duty cycle of 50 percent with these frequencies In the digital rollover mode, the
+ *  PPS output frequency is an average number The actual clock is of different
+ *  frequency that gets synchronized every second For example: When PPSCTRL = 0001, the
+ *  PPS _1 Hz_ has a low period of 537 ms and a high period of 463 ms When PPSCTRL =
+ *  0010, the PPS _2 Hz_ is a sequence of: 	One clock of 50 percent duty cycle and 537
+ *  ms period 	Second clock of 463 ms period _268 ms low and 195 ms high_ When PPSCTRL
+ *  = 0011, the PPS _4 Hz_ is a sequence of: 	Three clocks of 50 percent duty cycle and
+ *  268 ms period 	Fourth clock of 195 ms period _134 ms low and 61 ms high_ This
+ *  behavior is because of the nonlinear toggling of bits in the digital rollover mode
+ *  in Register 451 _System Time  Nanoseconds Register_ / PPSCMD0: Flexible PPS0 Output
+ *  _ptp_pps_o[0]_ Control Programming these bits with a nonzero value instructs the
+ *  MAC to initiate an event When the command is transferred or synchronized to the PTP
+ *  clock domain, these bits get cleared automatically The Software should ensure that
+ *  these bits are programmed only when they are “allzero” The following list describes
+ *  the values of PPSCMD0: 0000: No Command 0001: START Single Pulse This command
+ *  generates single pulse rising at the start point defined in Target Time Registers
+ *  _register 455 and 456_ and of a duration defined in the PPS0 Width Register 0010:
+ *  START Pulse Train This command generates the train of pulses rising at the start
+ *  point defined in the Target Time Registers and of a duration defined in the PPS0
+ *  Width Register and repeated at interval defined in the PPS Interval Register By
+ *  default, the PPS pulse train is freerunning unless stopped by 'STOP Pulse train at
+ *  time' or 'STOP Pulse Train immediately' commands 0011: Cancel START This command
+ *  cancels the START Single Pulse and START Pulse Train commands if the system time
+ *  has not crossed the programmed start time 0100: STOP Pulse train at time This
+ *  command stops the train of pulses initiated by the START Pulse Train command
+ *  _PPSCMD = 0010_ after the time programmed in the Target Time registers elapses
+ *  0101: STOP Pulse Train immediately This command immediately stops the train of
+ *  pulses initiated by the START Pulse Train command _PPSCMD = 0010_ 0110: Cancel STOP
+ *  Pulse train This command cancels the STOP pulse train at time command if the
+ *  programmed stop time has not elapsed The PPS pulse train becomes freerunning on the
+ *  successful execution of this command 01111111: Reserved
+ */
+#define GMAC_PPSCTRL0    0x0000000FU
+#define GMAC_PPSCTRL0_M  (GMAC_PPSCTRL0_V << GMAC_PPSCTRL0_S)
+#define GMAC_PPSCTRL0_V  0x0000000FU
+#define GMAC_PPSCTRL0_S  0
+/** GMAC_PPSEN0 : R/W; bitpos: [4]; default: 0;
+ *  Flexible PPS Output Mode Enable When set low, Bits [3:0] function as PPSCTRL
+ *  _backward compatible_ When set high, Bits[3:0] function as PPSCMD
+ */
+#define GMAC_PPSEN0    (BIT(4))
+#define GMAC_PPSEN0_M  (GMAC_PPSEN0_V << GMAC_PPSEN0_S)
+#define GMAC_PPSEN0_V  0x00000001U
+#define GMAC_PPSEN0_S  4
+/** GMAC_TRGTMODSEL0 : R/W; bitpos: [6:5]; default: 0;
+ *  Target Time Register Mode for PPS0 Output This field indicates the Target Time
+ *  registers _register 455 and 456_ mode for PPS0 output signal: 00: Indicates that
+ *  the Target Time registers are programmed only for generating the interrupt event
+ *  01: Reserved 10: Indicates that the Target Time registers are programmed for
+ *  generating the interrupt event and starting or stopping the generation of the PPS0
+ *  output signal 11: Indicates that the Target Time registers are programmed only for
+ *  starting or stopping the generation of the PPS0 output signal No interrupt is
+ *  asserted
+ */
+#define GMAC_TRGTMODSEL0    0x00000003U
+#define GMAC_TRGTMODSEL0_M  (GMAC_TRGTMODSEL0_V << GMAC_TRGTMODSEL0_S)
+#define GMAC_TRGTMODSEL0_V  0x00000003U
+#define GMAC_TRGTMODSEL0_S  5
+/** GMAC_PPSCMD1 : R/W1S; bitpos: [10:8]; default: 0;
+ *  Flexible PPS1 Output Control This field controls the flexible PPS1 output
+ *  _ptp_pps_o[1]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define GMAC_PPSCMD1    0x00000007U
+#define GMAC_PPSCMD1_M  (GMAC_PPSCMD1_V << GMAC_PPSCMD1_S)
+#define GMAC_PPSCMD1_V  0x00000007U
+#define GMAC_PPSCMD1_S  8
+/** GMAC_TRGTMODSEL1 : R/W; bitpos: [14:13]; default: 0;
+ *  Target Time Register Mode for PPS1 Output This field indicates the Target Time
+ *  registers _register 480 and 481_ mode for PPS1 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define GMAC_TRGTMODSEL1    0x00000003U
+#define GMAC_TRGTMODSEL1_M  (GMAC_TRGTMODSEL1_V << GMAC_TRGTMODSEL1_S)
+#define GMAC_TRGTMODSEL1_V  0x00000003U
+#define GMAC_TRGTMODSEL1_S  13
+/** GMAC_PPSCMD2 : R/W1S; bitpos: [18:16]; default: 0;
+ *  Flexible PPS2 Output Control This field controls the flexible PPS2 output
+ *  _ptp_pps_o[2]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define GMAC_PPSCMD2    0x00000007U
+#define GMAC_PPSCMD2_M  (GMAC_PPSCMD2_V << GMAC_PPSCMD2_S)
+#define GMAC_PPSCMD2_V  0x00000007U
+#define GMAC_PPSCMD2_S  16
+/** GMAC_TRGTMODSEL2 : R/W; bitpos: [22:21]; default: 0;
+ *  Target Time Register Mode for PPS2 Output This field indicates the Target Time
+ *  registers _register 488 and 489_ mode for PPS2 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define GMAC_TRGTMODSEL2    0x00000003U
+#define GMAC_TRGTMODSEL2_M  (GMAC_TRGTMODSEL2_V << GMAC_TRGTMODSEL2_S)
+#define GMAC_TRGTMODSEL2_V  0x00000003U
+#define GMAC_TRGTMODSEL2_S  21
+/** GMAC_PPSCMD3 : R/W1S; bitpos: [26:24]; default: 0;
+ *  Flexible PPS3 Output Control This field controls the flexible PPS3 output
+ *  _ptp_pps_o[3]_ signal This field is similar to PPSCMD0[2:0] in functionality
+ */
+#define GMAC_PPSCMD3    0x00000007U
+#define GMAC_PPSCMD3_M  (GMAC_PPSCMD3_V << GMAC_PPSCMD3_S)
+#define GMAC_PPSCMD3_V  0x00000007U
+#define GMAC_PPSCMD3_S  24
+/** GMAC_TRGTMODSEL3 : R/W; bitpos: [30:29]; default: 0;
+ *  Target Time Register Mode for PPS3 Output This field indicates the Target Time
+ *  registers _register 496 and 497_ mode for PPS3 output signal This field is similar
+ *  to the TRGTMODSEL0 field
+ */
+#define GMAC_TRGTMODSEL3    0x00000003U
+#define GMAC_TRGTMODSEL3_M  (GMAC_TRGTMODSEL3_V << GMAC_TRGTMODSEL3_S)
+#define GMAC_TRGTMODSEL3_V  0x00000003U
+#define GMAC_TRGTMODSEL3_S  29
+
+/** GMAC_REGISTER460_AUXILIARYTIMESTAMPNANOSECONDSREGISTER_REG register
+ *  Contains the lower 32 bits _nanoseconds field_ of the auxiliary timestamp register
+ */
+#define GMAC_REGISTER460_AUXILIARYTIMESTAMPNANOSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x730)
+/** GMAC_AUXTSLO : RO; bitpos: [30:0]; default: 0;
+ *  Contains the lower 31 bits _nanoseconds field_ of the auxiliary timestamp
+ */
+#define GMAC_AUXTSLO    0x7FFFFFFFU
+#define GMAC_AUXTSLO_M  (GMAC_AUXTSLO_V << GMAC_AUXTSLO_S)
+#define GMAC_AUXTSLO_V  0x7FFFFFFFU
+#define GMAC_AUXTSLO_S  0
+
+/** GMAC_REGISTER461_AUXILIARYTIMESTAMPSECONDSREGISTER_REG register
+ *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp register
+ */
+#define GMAC_REGISTER461_AUXILIARYTIMESTAMPSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x734)
+/** GMAC_AUXTSHI : RO; bitpos: [31:0]; default: 0;
+ *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp
+ */
+#define GMAC_AUXTSHI    0xFFFFFFFFU
+#define GMAC_AUXTSHI_M  (GMAC_AUXTSHI_V << GMAC_AUXTSHI_S)
+#define GMAC_AUXTSHI_V  0xFFFFFFFFU
+#define GMAC_AUXTSHI_S  0
+
+/** GMAC_REGISTER462_AVMACCONTROLREGISTER_REG register
+ *  Controls the AV traffic and queue management in the MAC Receiver This register is
+ *  present only when you select the AV feature in coreConsultant
+ */
+#define GMAC_REGISTER462_AVMACCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x738)
+/** GMAC_AVT : R/W; bitpos: [15:0]; default: 0;
+ *  AV EtherType Value This field contains the value that is compared with the
+ *  EtherType field of the incoming _tagged or untagged_ Ethernet frame to detect an AV
+ *  packet
+ */
+#define GMAC_AVT    0x0000FFFFU
+#define GMAC_AVT_M  (GMAC_AVT_V << GMAC_AVT_S)
+#define GMAC_AVT_V  0x0000FFFFU
+#define GMAC_AVT_S  0
+/** GMAC_AVP : R/W; bitpos: [18:16]; default: 0;
+ *  AV Priority for Queuing The value programmed in these bits control the receive
+ *  channel _0, 1, or 2_ to which an AV packet with a given priority must be queued If
+ *  only Channel 1 receive path is enabled, the AV packets with priority value greater
+ *  than or equal to the programmed value are queued on Channel 1 and all other packets
+ *  are queued on Channel 0 If Channel 2 receive path is also enabled, the AV packets
+ *  with priority value greater than or equal to the programmed value are queued on
+ *  Channel 2 The AV packets with value less than the programmed value on Channel 1 and
+ *  all other packets are queued on Channel 0 These bits are applicable only if at
+ *  least one additional receive channel is selected in the AV mode
+ */
+#define GMAC_AVP    0x00000007U
+#define GMAC_AVP_M  (GMAC_AVP_V << GMAC_AVP_S)
+#define GMAC_AVP_V  0x00000007U
+#define GMAC_AVP_S  16
+/** GMAC_VQE : R/W; bitpos: [19]; default: 0;
+ *  VLAN Tagged NonAV Packets Queueing Enable When this bit is set, the MAC also queues
+ *  nonAV VLAN tagged packets into the available channels according to the value of the
+ *  AVP bits This bit is reserved and readonly if Channel 1 and Channel 2 Receive paths
+ *  are not selected during core configuration
+ */
+#define GMAC_VQE    (BIT(19))
+#define GMAC_VQE_M  (GMAC_VQE_V << GMAC_VQE_S)
+#define GMAC_VQE_V  0x00000001U
+#define GMAC_VQE_S  19
+/** GMAC_AVCD : R/W; bitpos: [20]; default: 0;
+ *  AV Channel Disable When this bit is set, the MAC forwards all packets to the
+ *  default Channel 0 and the values programmed in the AVP, AVCH, and PTPCH fields are
+ *  ignored This bit is reserved and readonly if Channel 1 or Channel 2 receive paths
+ *  are not selected during core configuration
+ */
+#define GMAC_AVCD    (BIT(20))
+#define GMAC_AVCD_M  (GMAC_AVCD_V << GMAC_AVCD_S)
+#define GMAC_AVCD_V  0x00000001U
+#define GMAC_AVCD_S  20
+/** GMAC_AVCH : R/W; bitpos: [22:21]; default: 0;
+ *  Channel for Queuing the AV Control Packets This field specifies the channel on
+ *  which the received untagged AV control packets are queued 00: Channel 0 01: Channel
+ *  1 10: Channel 2 11: Reserved These bits are reserved if the receive paths of
+ *  Channel 1 or Channel 2 are not enabled
+ */
+#define GMAC_AVCH    0x00000003U
+#define GMAC_AVCH_M  (GMAC_AVCH_V << GMAC_AVCH_S)
+#define GMAC_AVCH_V  0x00000003U
+#define GMAC_AVCH_S  21
+/** GMAC_PTPCH : R/W; bitpos: [25:24]; default: 0;
+ *  Channel for Queuing the PTP Packets This field specifies the channel on which the
+ *  untagged PTP packets, sent over the Ethernet payload and not over IPv4 or IPv6, are
+ *  queued 00: Channel 0 01: Channel 1 10: Channel 2 11: Reserved These bits are
+ *  reserved if the receive paths of Channel 1 or Channel 2 are not enabled
+ */
+#define GMAC_PTPCH    0x00000003U
+#define GMAC_PTPCH_M  (GMAC_PTPCH_V << GMAC_PTPCH_S)
+#define GMAC_PTPCH_V  0x00000003U
+#define GMAC_PTPCH_S  24
+
+/** GMAC_REGISTER472_PPS0INTERVALREGISTER_REG register
+ *  Contains the number of units of subsecond increment value between the rising edges
+ *  of PPS0 signal output This register is available only when the flexible PPS feature
+ *  is selected
+ */
+#define GMAC_REGISTER472_PPS0INTERVALREGISTER_REG (DR_REG_GMAC_BASE + 0x760)
+/** GMAC_PPSINT : R/W; bitpos: [31:0]; default: 0;
+ *  PPS0 Output Signal Interval These bits store the interval between the rising edges
+ *  of PPS0 signal output in terms of units of subsecond increment value You need to
+ *  program one value less than the required interval For example, if the PTP reference
+ *  clock is 50 MHz _period of 20ns_, and desired interval between rising edges of PPS0
+ *  signal output is 100ns _that is, five units of subsecond increment value_, then you
+ *  should program value 4 _5  1_ in this register
+ */
+#define GMAC_PPSINT    0xFFFFFFFFU
+#define GMAC_PPSINT_M  (GMAC_PPSINT_V << GMAC_PPSINT_S)
+#define GMAC_PPSINT_V  0xFFFFFFFFU
+#define GMAC_PPSINT_S  0
+
+/** GMAC_REGISTER473_PPS0WIDTHREGISTER_REG register
+ *  Contains the number of units of subsecond increment value between the rising and
+ *  corresponding falling edges of PPS0 signal output This register is available only
+ *  when the flexible PPS feature is selected
+ */
+#define GMAC_REGISTER473_PPS0WIDTHREGISTER_REG (DR_REG_GMAC_BASE + 0x764)
+/** GMAC_PPSWIDTH : R/W; bitpos: [31:0]; default: 0;
+ *  PPS0 Output Signal Width These bits store the width between the rising edge and
+ *  corresponding falling edge of the PPS0 signal output in terms of units of subsecond
+ *  increment value You need to program one value less than the required interval For
+ *  example, if PTP reference clock is 50 MHz _period of 20ns_, and desired width
+ *  between the rising and corresponding falling edges of PPS0 signal output is 80ns
+ *  _that is, four units of subsecond increment value_, then you should program value 3
+ *  _4  1_ in this register Note: The value programmed in this register must be lesser
+ *  than the value programmed in Register 472 _PPS0 Interval Register_
+ */
+#define GMAC_PPSWIDTH    0xFFFFFFFFU
+#define GMAC_PPSWIDTH_M  (GMAC_PPSWIDTH_V << GMAC_PPSWIDTH_S)
+#define GMAC_PPSWIDTH_V  0xFFFFFFFFU
+#define GMAC_PPSWIDTH_S  0
+
+/** GMAC_REGISTER480_PPS1TARGETTIMESECONDSREGISTER_REG register
+ *  Contains the higher 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+#define GMAC_REGISTER480_PPS1TARGETTIMESECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x780)
+/** GMAC_TSTRH1 : R/W; bitpos: [31:0]; default: 0;
+ *  PPS1 Target Time Seconds Register This register stores the time in seconds When the
+ *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+ *  Bits [14:13], TRGTMODSEL1, of Register 459 _PPS Control Register_, the MAC starts
+ *  or stops the PPS signal output and generates an interrupt _if enabled_
+ */
+#define GMAC_TSTRH1    0xFFFFFFFFU
+#define GMAC_TSTRH1_M  (GMAC_TSTRH1_V << GMAC_TSTRH1_S)
+#define GMAC_TSTRH1_V  0xFFFFFFFFU
+#define GMAC_TSTRH1_S  0
+
+/** GMAC_REGISTER481_PPS1TARGETTIMENANOSECONDSREGISTER_REG register
+ *  Contains the lower 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+#define GMAC_REGISTER481_PPS1TARGETTIMENANOSECONDSREGISTER_REG (DR_REG_GMAC_BASE + 0x784)
+/** GMAC_TTSL1 : R/W; bitpos: [30:0]; default: 0;
+ *  Target Time Low for PPS1 Register This register stores the time in _signed_
+ *  nanoseconds When the value of the timestamp matches the both Target Timestamp
+ *  registers, then based on the TRGTMODSEL1 field _Bits [14:13]_ in Register 459 _PPS
+ *  Control Register_, the MAC starts or stops the PPS signal output and generates an
+ *  interrupt _if enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9
+ *  _TSCTRLSSR_ is set in Register 448 _Timestamp Control Register_ The actual start or
+ *  stop time of the PPS signal output may have an error margin up to one unit of
+ *  subsecond increment value
+ */
+#define GMAC_TTSL1    0x7FFFFFFFU
+#define GMAC_TTSL1_M  (GMAC_TTSL1_V << GMAC_TTSL1_S)
+#define GMAC_TTSL1_V  0x7FFFFFFFU
+#define GMAC_TTSL1_S  0
+/** GMAC_TRGTBUSY1 : R/W1S; bitpos: [31]; default: 0;
+ *  PPS1 Target Time Register Busy The MAC sets this bit when the PPSCMD1 field _Bits
+ *  [10:8]_ in Register 459 _PPS Control Register_ is programmed to 010 or 011
+ *  Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the
+ *  Target Time Registers to the PTP clock domain The MAC clears this bit after
+ *  synchronizing the Target Time Registers to the PTP clock domain The application
+ *  must not update the Target Time Registers when this bit is read as 1 Otherwise, the
+ *  synchronization of the previous programmed time gets corrupted
+ */
+#define GMAC_TRGTBUSY1    (BIT(31))
+#define GMAC_TRGTBUSY1_M  (GMAC_TRGTBUSY1_V << GMAC_TRGTBUSY1_S)
+#define GMAC_TRGTBUSY1_V  0x00000001U
+#define GMAC_TRGTBUSY1_S  31
+
+/** GMAC_REGISTER544_MACADDRESS32HIGHREGISTER_REG register
+ *  Contains the higher 16 bits of the 33rd MAC address This register is present only
+ *  when Enable Additional 32 MAC Address Registers is selected in coreConsultant _See
+ *  Table 78_
+ */
+#define GMAC_REGISTER544_MACADDRESS32HIGHREGISTER_REG (DR_REG_GMAC_BASE + 0x880)
+/** GMAC_ADDRHI : R/W; bitpos: [15:0]; default: 65535;
+ *  MAC Address32 [47:32] This field contains the upper 16 bits _47:32_ of the 33rd
+ *  6byte MAC address
+ */
+#define GMAC_ADDRHI    0x0000FFFFU
+#define GMAC_ADDRHI_M  (GMAC_ADDRHI_V << GMAC_ADDRHI_S)
+#define GMAC_ADDRHI_V  0x0000FFFFU
+#define GMAC_ADDRHI_S  0
+/** GMAC_AE : R/W; bitpos: [31]; default: 0;
+ *  Address Enable When this bit is set, the Address filter module uses the 33rd MAC
+ *  address for perfect filtering When reset, the address filter module ignores the
+ *  address for filtering
+ */
+#define GMAC_AE    (BIT(31))
+#define GMAC_AE_M  (GMAC_AE_V << GMAC_AE_S)
+#define GMAC_AE_V  0x00000001U
+#define GMAC_AE_S  31
+
+/** GMAC_REGISTER0_BUSMODEREGISTER_REG register
+ *  Controls the Host Interface Mode
+ */
+#define GMAC_REGISTER0_BUSMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1000)
+/** GMAC_SWR : R/W1S_SC; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+ *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define GMAC_SWR    (BIT(0))
+#define GMAC_SWR_M  (GMAC_SWR_V << GMAC_SWR_S)
+#define GMAC_SWR_V  0x00000001U
+#define GMAC_SWR_S  0
+/** GMAC_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 0 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the GMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define GMAC_DA    (BIT(1))
+#define GMAC_DA_M  (GMAC_DA_V << GMAC_DA_S)
+#define GMAC_DA_V  0x00000001U
+#define GMAC_DA_S  1
+/** GMAC_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define GMAC_DSL    0x0000001FU
+#define GMAC_DSL_M  (GMAC_DSL_V << GMAC_DSL_S)
+#define GMAC_DSL_V  0x0000001FU
+#define GMAC_DSL_S  2
+/** GMAC_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define GMAC_ATDS    (BIT(7))
+#define GMAC_ATDS_M  (GMAC_ATDS_V << GMAC_ATDS_S)
+#define GMAC_ATDS_V  0x00000001U
+#define GMAC_ATDS_S  7
+/** GMAC_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define GMAC_PBL    0x0000003FU
+#define GMAC_PBL_M  (GMAC_PBL_V << GMAC_PBL_S)
+#define GMAC_PBL_V  0x0000003FU
+#define GMAC_PBL_S  8
+/** GMAC_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define GMAC_PR    0x00000003U
+#define GMAC_PR_M  (GMAC_PR_V << GMAC_PR_S)
+#define GMAC_PR_V  0x00000003U
+#define GMAC_PR_S  14
+/** GMAC_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+ */
+#define GMAC_FB    (BIT(16))
+#define GMAC_FB_M  (GMAC_FB_V << GMAC_FB_S)
+#define GMAC_FB_V  0x00000001U
+#define GMAC_FB_S  16
+/** GMAC_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define GMAC_RPBL    0x0000003FU
+#define GMAC_RPBL_M  (GMAC_RPBL_V << GMAC_RPBL_S)
+#define GMAC_RPBL_V  0x0000003FU
+#define GMAC_RPBL_S  17
+/** GMAC_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define GMAC_USP    (BIT(23))
+#define GMAC_USP_M  (GMAC_USP_V << GMAC_USP_S)
+#define GMAC_USP_V  0x00000001U
+#define GMAC_USP_S  23
+/** GMAC_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define GMAC_PBLX8    (BIT(24))
+#define GMAC_PBLX8_M  (GMAC_PBLX8_V << GMAC_PBLX8_S)
+#define GMAC_PBLX8_V  0x00000001U
+#define GMAC_PBLX8_S  24
+/** GMAC_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define GMAC_AAL    (BIT(25))
+#define GMAC_AAL_M  (GMAC_AAL_V << GMAC_AAL_S)
+#define GMAC_AAL_V  0x00000001U
+#define GMAC_AAL_S  25
+/** GMAC_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define GMAC_MB    (BIT(26))
+#define GMAC_MB_M  (GMAC_MB_V << GMAC_MB_S)
+#define GMAC_MB_V  0x00000001U
+#define GMAC_MB_S  26
+/** GMAC_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_TXPR    (BIT(27))
+#define GMAC_TXPR_M  (GMAC_TXPR_V << GMAC_TXPR_S)
+#define GMAC_TXPR_V  0x00000001U
+#define GMAC_TXPR_S  27
+/** GMAC_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 0 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_gmac configurations
+ *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_PRWG    0x00000003U
+#define GMAC_PRWG_M  (GMAC_PRWG_V << GMAC_PRWG_S)
+#define GMAC_PRWG_V  0x00000003U
+#define GMAC_PRWG_S  28
+/** GMAC_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define GMAC_RIB    (BIT(31))
+#define GMAC_RIB_M  (GMAC_RIB_V << GMAC_RIB_S)
+#define GMAC_RIB_V  0x00000001U
+#define GMAC_RIB_S  31
+
+/** GMAC_REGISTER1_TRANSMITPOLLDEMANDREGISTER_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define GMAC_REGISTER1_TRANSMITPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1004)
+/** GMAC_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define GMAC_TPD    0xFFFFFFFFU
+#define GMAC_TPD_M  (GMAC_TPD_V << GMAC_TPD_S)
+#define GMAC_TPD_V  0xFFFFFFFFU
+#define GMAC_TPD_S  0
+
+/** GMAC_REGISTER2_RECEIVEPOLLDEMANDREGISTER_REG register
+ *  Used by the host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define GMAC_REGISTER2_RECEIVEPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1008)
+/** GMAC_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define GMAC_RPD    0xFFFFFFFFU
+#define GMAC_RPD_M  (GMAC_RPD_V << GMAC_RPD_S)
+#define GMAC_RPD_V  0xFFFFFFFFU
+#define GMAC_RPD_S  0
+
+/** GMAC_REGISTER3_RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define GMAC_REGISTER3_RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x100c)
+/** GMAC_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define GMAC_RDESLA    0xFFFFFFFFU
+#define GMAC_RDESLA_M  (GMAC_RDESLA_V << GMAC_RDESLA_S)
+#define GMAC_RDESLA_V  0xFFFFFFFFU
+#define GMAC_RDESLA_S  0
+
+/** GMAC_REGISTER4_TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+#define GMAC_REGISTER4_TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1010)
+/** GMAC_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define GMAC_TDESLA    0xFFFFFFFFU
+#define GMAC_TDESLA_M  (GMAC_TDESLA_V << GMAC_TDESLA_S)
+#define GMAC_TDESLA_V  0xFFFFFFFFU
+#define GMAC_TDESLA_S  0
+
+/** GMAC_REGISTER5_STATUSREGISTER_REG register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA
+ */
+#define GMAC_REGISTER5_STATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1014)
+/** GMAC_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define GMAC_TI    (BIT(0))
+#define GMAC_TI_M  (GMAC_TI_V << GMAC_TI_S)
+#define GMAC_TI_V  0x00000001U
+#define GMAC_TI_S  0
+/** GMAC_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define GMAC_TPS    (BIT(1))
+#define GMAC_TPS_M  (GMAC_TPS_V << GMAC_TPS_S)
+#define GMAC_TPS_V  0x00000001U
+#define GMAC_TPS_S  1
+/** GMAC_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define GMAC_TU    (BIT(2))
+#define GMAC_TU_M  (GMAC_TU_V << GMAC_TU_S)
+#define GMAC_TU_V  0x00000001U
+#define GMAC_TU_S  2
+/** GMAC_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define GMAC_TJT    (BIT(3))
+#define GMAC_TJT_M  (GMAC_TJT_V << GMAC_TJT_S)
+#define GMAC_TJT_V  0x00000001U
+#define GMAC_TJT_S  3
+/** GMAC_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define GMAC_OVF    (BIT(4))
+#define GMAC_OVF_M  (GMAC_OVF_V << GMAC_OVF_S)
+#define GMAC_OVF_V  0x00000001U
+#define GMAC_OVF_S  4
+/** GMAC_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define GMAC_UNF    (BIT(5))
+#define GMAC_UNF_M  (GMAC_UNF_V << GMAC_UNF_S)
+#define GMAC_UNF_V  0x00000001U
+#define GMAC_UNF_S  5
+/** GMAC_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define GMAC_RI    (BIT(6))
+#define GMAC_RI_M  (GMAC_RI_V << GMAC_RI_S)
+#define GMAC_RI_V  0x00000001U
+#define GMAC_RI_S  6
+/** GMAC_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define GMAC_RU    (BIT(7))
+#define GMAC_RU_M  (GMAC_RU_V << GMAC_RU_S)
+#define GMAC_RU_V  0x00000001U
+#define GMAC_RU_S  7
+/** GMAC_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define GMAC_RPS    (BIT(8))
+#define GMAC_RPS_M  (GMAC_RPS_V << GMAC_RPS_S)
+#define GMAC_RPS_V  0x00000001U
+#define GMAC_RPS_S  8
+/** GMAC_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define GMAC_RWT    (BIT(9))
+#define GMAC_RWT_M  (GMAC_RWT_V << GMAC_RWT_S)
+#define GMAC_RWT_V  0x00000001U
+#define GMAC_RWT_S  9
+/** GMAC_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define GMAC_ETI    (BIT(10))
+#define GMAC_ETI_M  (GMAC_ETI_V << GMAC_ETI_S)
+#define GMAC_ETI_V  0x00000001U
+#define GMAC_ETI_S  10
+/** GMAC_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define GMAC_FBI    (BIT(13))
+#define GMAC_FBI_M  (GMAC_FBI_V << GMAC_FBI_S)
+#define GMAC_FBI_V  0x00000001U
+#define GMAC_FBI_S  13
+/** GMAC_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define GMAC_ERI    (BIT(14))
+#define GMAC_ERI_M  (GMAC_ERI_V << GMAC_ERI_S)
+#define GMAC_ERI_V  0x00000001U
+#define GMAC_ERI_S  14
+/** GMAC_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define GMAC_AIS    (BIT(15))
+#define GMAC_AIS_M  (GMAC_AIS_V << GMAC_AIS_S)
+#define GMAC_AIS_V  0x00000001U
+#define GMAC_AIS_S  15
+/** GMAC_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define GMAC_NIS    (BIT(16))
+#define GMAC_NIS_M  (GMAC_NIS_V << GMAC_NIS_S)
+#define GMAC_NIS_V  0x00000001U
+#define GMAC_NIS_S  16
+/** GMAC_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define GMAC_RS    0x00000007U
+#define GMAC_RS_M  (GMAC_RS_V << GMAC_RS_S)
+#define GMAC_RS_V  0x00000007U
+#define GMAC_RS_S  17
+/** GMAC_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define GMAC_TS    0x00000007U
+#define GMAC_TS_M  (GMAC_TS_V << GMAC_TS_S)
+#define GMAC_TS_V  0x00000007U
+#define GMAC_TS_S  20
+/** GMAC_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define GMAC_EB    0x00000007U
+#define GMAC_EB_M  (GMAC_EB_V << GMAC_EB_S)
+#define GMAC_EB_V  0x00000007U
+#define GMAC_EB_S  23
+/** GMAC_GLI : RO; bitpos: [26]; default: 0;
+ *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define GMAC_GLI    (BIT(26))
+#define GMAC_GLI_M  (GMAC_GLI_V << GMAC_GLI_S)
+#define GMAC_GLI_V  0x00000001U
+#define GMAC_GLI_S  26
+/** GMAC_GMI : RO; bitpos: [27]; default: 0;
+ *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define GMAC_GMI    (BIT(27))
+#define GMAC_GMI_M  (GMAC_GMI_V << GMAC_GMI_S)
+#define GMAC_GMI_V  0x00000001U
+#define GMAC_GMI_S  27
+/** GMAC_GPI : RO; bitpos: [28]; default: 0;
+ *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define GMAC_GPI    (BIT(28))
+#define GMAC_GPI_M  (GMAC_GPI_V << GMAC_GPI_S)
+#define GMAC_GPI_V  0x00000001U
+#define GMAC_GPI_S  28
+/** GMAC_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_gmac The software must read the corresponding registers
+ *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define GMAC_TTI    (BIT(29))
+#define GMAC_TTI_M  (GMAC_TTI_V << GMAC_TTI_S)
+#define GMAC_TTI_V  0x00000001U
+#define GMAC_TTI_S  29
+/** GMAC_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GLPII: GMAC LPI Interrupt This bit indicates an interrupt event in the LPI logic of
+ *  the MAC To reset this bit to 1'b0, the software must read the corresponding
+ *  registers in the DWC_gmac to get the exact cause of the interrupt and clear its
+ *  source Note: GLPII status is given only in Channel 0 DMA register and is applicable
+ *  only when the Energy Efficient Ethernet feature is enabled Otherwise, this bit is
+ *  reserved When this bit is high, the interrupt signal from the MAC _sbd_intr_o_ is
+ *  high
+ */
+#define GMAC_GLPII_GTMSI    (BIT(30))
+#define GMAC_GLPII_GTMSI_M  (GMAC_GLPII_GTMSI_V << GMAC_GLPII_GTMSI_S)
+#define GMAC_GLPII_GTMSI_V  0x00000001U
+#define GMAC_GLPII_GTMSI_S  30
+
+/** GMAC_REGISTER6_OPERATIONMODEREGISTER_REG register
+ *  Establishes the Receive and Transmit operating modes and command Note: This
+ *  register is valid and present in the GMACMTL configuration
+ */
+#define GMAC_REGISTER6_OPERATIONMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1018)
+/** GMAC_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define GMAC_SR    (BIT(1))
+#define GMAC_SR_M  (GMAC_SR_V << GMAC_SR_S)
+#define GMAC_SR_V  0x00000001U
+#define GMAC_SR_S  1
+/** GMAC_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define GMAC_OSF    (BIT(2))
+#define GMAC_OSF_M  (GMAC_OSF_V << GMAC_OSF_S)
+#define GMAC_OSF_V  0x00000001U
+#define GMAC_OSF_S  2
+/** GMAC_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define GMAC_RTC    0x00000003U
+#define GMAC_RTC_M  (GMAC_RTC_V << GMAC_RTC_S)
+#define GMAC_RTC_V  0x00000003U
+#define GMAC_RTC_S  3
+/** GMAC_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define GMAC_DGF    (BIT(5))
+#define GMAC_DGF_M  (GMAC_DGF_V << GMAC_DGF_S)
+#define GMAC_DGF_V  0x00000001U
+#define GMAC_DGF_S  5
+/** GMAC_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define GMAC_FUF    (BIT(6))
+#define GMAC_FUF_M  (GMAC_FUF_V << GMAC_FUF_S)
+#define GMAC_FUF_V  0x00000001U
+#define GMAC_FUF_S  6
+/** GMAC_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+ *  configurations
+ */
+#define GMAC_FEF    (BIT(7))
+#define GMAC_FEF_M  (GMAC_FEF_V << GMAC_FEF_S)
+#define GMAC_FEF_V  0x00000001U
+#define GMAC_FEF_S  7
+/** GMAC_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define GMAC_EFC    (BIT(8))
+#define GMAC_EFC_M  (GMAC_EFC_V << GMAC_EFC_S)
+#define GMAC_EFC_V  0x00000001U
+#define GMAC_EFC_S  8
+/** GMAC_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define GMAC_RFA    0x00000003U
+#define GMAC_RFA_M  (GMAC_RFA_V << GMAC_RFA_S)
+#define GMAC_RFA_V  0x00000003U
+#define GMAC_RFA_S  9
+/** GMAC_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define GMAC_RFD    0x00000003U
+#define GMAC_RFD_M  (GMAC_RFD_V << GMAC_RFD_S)
+#define GMAC_RFD_V  0x00000003U
+#define GMAC_RFD_S  11
+/** GMAC_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define GMAC_ST    (BIT(13))
+#define GMAC_ST_M  (GMAC_ST_V << GMAC_ST_S)
+#define GMAC_ST_V  0x00000001U
+#define GMAC_ST_S  13
+/** GMAC_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define GMAC_TTC    0x00000007U
+#define GMAC_TTC_M  (GMAC_TTC_V << GMAC_TTC_S)
+#define GMAC_TTC_V  0x00000007U
+#define GMAC_TTC_S  14
+/** GMAC_FTF : R/W1S; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define GMAC_FTF    (BIT(20))
+#define GMAC_FTF_M  (GMAC_FTF_V << GMAC_FTF_S)
+#define GMAC_FTF_V  0x00000001U
+#define GMAC_FTF_S  20
+/** GMAC_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define GMAC_TSF    (BIT(21))
+#define GMAC_TSF_M  (GMAC_TSF_V << GMAC_TSF_S)
+#define GMAC_TSF_V  0x00000001U
+#define GMAC_TSF_S  21
+/** GMAC_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define GMAC_RFD_2    (BIT(22))
+#define GMAC_RFD_2_M  (GMAC_RFD_2_V << GMAC_RFD_2_S)
+#define GMAC_RFD_2_V  0x00000001U
+#define GMAC_RFD_2_S  22
+/** GMAC_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define GMAC_RFA_2    (BIT(23))
+#define GMAC_RFA_2_M  (GMAC_RFA_2_V << GMAC_RFA_2_S)
+#define GMAC_RFA_2_V  0x00000001U
+#define GMAC_RFA_2_S  23
+/** GMAC_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the GMACMTL configuration
+ */
+#define GMAC_DFF    (BIT(24))
+#define GMAC_DFF_M  (GMAC_DFF_V << GMAC_DFF_S)
+#define GMAC_DFF_V  0x00000001U
+#define GMAC_DFF_S  24
+/** GMAC_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define GMAC_RSF    (BIT(25))
+#define GMAC_RSF_M  (GMAC_RSF_V << GMAC_RSF_S)
+#define GMAC_RSF_V  0x00000001U
+#define GMAC_RSF_S  25
+/** GMAC_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define GMAC_DT    (BIT(26))
+#define GMAC_DT_M  (GMAC_DT_V << GMAC_DT_S)
+#define GMAC_DT_V  0x00000001U
+#define GMAC_DT_S  26
+
+/** GMAC_REGISTER7_INTERRUPTENABLEREGISTER_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define GMAC_REGISTER7_INTERRUPTENABLEREGISTER_REG (DR_REG_GMAC_BASE + 0x101c)
+/** GMAC_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define GMAC_TIE    (BIT(0))
+#define GMAC_TIE_M  (GMAC_TIE_V << GMAC_TIE_S)
+#define GMAC_TIE_V  0x00000001U
+#define GMAC_TIE_S  0
+/** GMAC_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define GMAC_TSE    (BIT(1))
+#define GMAC_TSE_M  (GMAC_TSE_V << GMAC_TSE_S)
+#define GMAC_TSE_V  0x00000001U
+#define GMAC_TSE_S  1
+/** GMAC_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_TUE    (BIT(2))
+#define GMAC_TUE_M  (GMAC_TUE_V << GMAC_TUE_S)
+#define GMAC_TUE_V  0x00000001U
+#define GMAC_TUE_S  2
+/** GMAC_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define GMAC_TJE    (BIT(3))
+#define GMAC_TJE_M  (GMAC_TJE_V << GMAC_TJE_S)
+#define GMAC_TJE_V  0x00000001U
+#define GMAC_TJE_S  3
+/** GMAC_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define GMAC_OVE    (BIT(4))
+#define GMAC_OVE_M  (GMAC_OVE_V << GMAC_OVE_S)
+#define GMAC_OVE_V  0x00000001U
+#define GMAC_OVE_S  4
+/** GMAC_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define GMAC_UNE    (BIT(5))
+#define GMAC_UNE_M  (GMAC_UNE_V << GMAC_UNE_S)
+#define GMAC_UNE_V  0x00000001U
+#define GMAC_UNE_S  5
+/** GMAC_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define GMAC_RIE    (BIT(6))
+#define GMAC_RIE_M  (GMAC_RIE_V << GMAC_RIE_S)
+#define GMAC_RIE_V  0x00000001U
+#define GMAC_RIE_S  6
+/** GMAC_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_RUE    (BIT(7))
+#define GMAC_RUE_M  (GMAC_RUE_V << GMAC_RUE_S)
+#define GMAC_RUE_V  0x00000001U
+#define GMAC_RUE_S  7
+/** GMAC_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define GMAC_RSE    (BIT(8))
+#define GMAC_RSE_M  (GMAC_RSE_V << GMAC_RSE_S)
+#define GMAC_RSE_V  0x00000001U
+#define GMAC_RSE_S  8
+/** GMAC_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define GMAC_RWE    (BIT(9))
+#define GMAC_RWE_M  (GMAC_RWE_V << GMAC_RWE_S)
+#define GMAC_RWE_V  0x00000001U
+#define GMAC_RWE_S  9
+/** GMAC_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define GMAC_ETE    (BIT(10))
+#define GMAC_ETE_M  (GMAC_ETE_V << GMAC_ETE_S)
+#define GMAC_ETE_V  0x00000001U
+#define GMAC_ETE_S  10
+/** GMAC_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define GMAC_FBE    (BIT(13))
+#define GMAC_FBE_M  (GMAC_FBE_V << GMAC_FBE_S)
+#define GMAC_FBE_V  0x00000001U
+#define GMAC_FBE_S  13
+/** GMAC_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define GMAC_ERE    (BIT(14))
+#define GMAC_ERE_M  (GMAC_ERE_V << GMAC_ERE_S)
+#define GMAC_ERE_V  0x00000001U
+#define GMAC_ERE_S  14
+/** GMAC_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define GMAC_AIE    (BIT(15))
+#define GMAC_AIE_M  (GMAC_AIE_V << GMAC_AIE_S)
+#define GMAC_AIE_V  0x00000001U
+#define GMAC_AIE_S  15
+/** GMAC_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define GMAC_NIE    (BIT(16))
+#define GMAC_NIE_M  (GMAC_NIE_V << GMAC_NIE_S)
+#define GMAC_NIE_V  0x00000001U
+#define GMAC_NIE_S  16
+
+/** GMAC_REGISTER8_MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+#define GMAC_REGISTER8_MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG (DR_REG_GMAC_BASE + 0x1020)
+/** GMAC_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define GMAC_MISFRMCNT    0x0000FFFFU
+#define GMAC_MISFRMCNT_M  (GMAC_MISFRMCNT_V << GMAC_MISFRMCNT_S)
+#define GMAC_MISFRMCNT_V  0x0000FFFFU
+#define GMAC_MISFRMCNT_S  0
+/** GMAC_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define GMAC_MISCNTOVF    (BIT(16))
+#define GMAC_MISCNTOVF_M  (GMAC_MISCNTOVF_V << GMAC_MISCNTOVF_S)
+#define GMAC_MISCNTOVF_V  0x00000001U
+#define GMAC_MISCNTOVF_S  16
+/** GMAC_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define GMAC_OVFFRMCNT    0x000007FFU
+#define GMAC_OVFFRMCNT_M  (GMAC_OVFFRMCNT_V << GMAC_OVFFRMCNT_S)
+#define GMAC_OVFFRMCNT_V  0x000007FFU
+#define GMAC_OVFFRMCNT_S  17
+/** GMAC_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define GMAC_OVFCNTOVF    (BIT(28))
+#define GMAC_OVFCNTOVF_M  (GMAC_OVFCNTOVF_V << GMAC_OVFCNTOVF_S)
+#define GMAC_OVFCNTOVF_V  0x00000001U
+#define GMAC_OVFCNTOVF_S  28
+
+/** GMAC_REGISTER9_RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define GMAC_REGISTER9_RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG (DR_REG_GMAC_BASE + 0x1024)
+/** GMAC_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define GMAC_RIWT    0x000000FFU
+#define GMAC_RIWT_M  (GMAC_RIWT_V << GMAC_RIWT_S)
+#define GMAC_RIWT_V  0x000000FFU
+#define GMAC_RIWT_S  0
+
+/** GMAC_REGISTER10_AXIBUSMODEREGISTER_REG register
+ *  Controls AXI master behavior _mainly controls burst splitting and number of
+ *  outstanding requests_
+ */
+#define GMAC_REGISTER10_AXIBUSMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1028)
+/** GMAC_UNDEF : RO; bitpos: [0]; default: 1;
+ *  AXI Undefined Burst Length This bit is readonly bit and indicates the complement
+ *  _invert_ value of Bit 16 _FB_ in Register 0 _Bus Mode Register_ When this bit is
+ *  set to 1, the GMACAXI is allowed to perform any burst length equal to or below the
+ *  maximum allowed burst length programmed in Bits[7:3] When this bit is set to 0, the
+ *  GMACAXI is allowed to perform only fixed burst lengths as indicated by BLEN256,
+ *  BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1 If UNDEF
+ *  is set and none of the BLEN bits is set, then GMACAXI is allowed to perform a burst
+ *  length of 16
+ */
+#define GMAC_UNDEF    (BIT(0))
+#define GMAC_UNDEF_M  (GMAC_UNDEF_V << GMAC_UNDEF_S)
+#define GMAC_UNDEF_V  0x00000001U
+#define GMAC_UNDEF_S  0
+/** GMAC_BLEN4 : R/W; bitpos: [1]; default: 0;
+ *  AXI Burst Length 4 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 4 on the AXI master interface Setting this bit has no effect when
+ *  UNDEF is set to 1
+ */
+#define GMAC_BLEN4    (BIT(1))
+#define GMAC_BLEN4_M  (GMAC_BLEN4_V << GMAC_BLEN4_S)
+#define GMAC_BLEN4_V  0x00000001U
+#define GMAC_BLEN4_S  1
+/** GMAC_BLEN8 : R/W; bitpos: [2]; default: 0;
+ *  AXI Burst Length 8 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 8 on the AXI master interface Setting this bit has no effect when
+ *  UNDEF is set to 1
+ */
+#define GMAC_BLEN8    (BIT(2))
+#define GMAC_BLEN8_M  (GMAC_BLEN8_V << GMAC_BLEN8_S)
+#define GMAC_BLEN8_V  0x00000001U
+#define GMAC_BLEN8_S  2
+/** GMAC_BLEN16 : R/W; bitpos: [3]; default: 0;
+ *  AXI Burst Length 16 When this bit is set to 1 or UNDEF is set to 1, the GMACAXI is
+ *  allowed to select a burst length of 16 on the AXI master interface
+ */
+#define GMAC_BLEN16    (BIT(3))
+#define GMAC_BLEN16_M  (GMAC_BLEN16_V << GMAC_BLEN16_S)
+#define GMAC_BLEN16_V  0x00000001U
+#define GMAC_BLEN16_S  3
+/** GMAC_BLEN32 : R/W; bitpos: [4]; default: 0;
+ *  AXI Burst Length 32 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 32 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 32 or more Otherwise, this bit is reserved
+ *  and is readonly _RO_
+ */
+#define GMAC_BLEN32    (BIT(4))
+#define GMAC_BLEN32_M  (GMAC_BLEN32_V << GMAC_BLEN32_S)
+#define GMAC_BLEN32_V  0x00000001U
+#define GMAC_BLEN32_S  4
+/** GMAC_BLEN64 : R/W; bitpos: [5]; default: 0;
+ *  AXI Burst Length 64 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 64 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 64 or more Otherwise, this bit is reserved
+ *  and is readonly _RO_
+ */
+#define GMAC_BLEN64    (BIT(5))
+#define GMAC_BLEN64_M  (GMAC_BLEN64_V << GMAC_BLEN64_S)
+#define GMAC_BLEN64_V  0x00000001U
+#define GMAC_BLEN64_S  5
+/** GMAC_BLEN128 : R/W; bitpos: [6]; default: 0;
+ *  AXI Burst Length 128 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 128 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 128 or more Otherwise, this bit is
+ *  reserved and is readonly _RO_
+ */
+#define GMAC_BLEN128    (BIT(6))
+#define GMAC_BLEN128_M  (GMAC_BLEN128_V << GMAC_BLEN128_S)
+#define GMAC_BLEN128_V  0x00000001U
+#define GMAC_BLEN128_S  6
+/** GMAC_BLEN256 : R/W; bitpos: [7]; default: 0;
+ *  AXI Burst Length 256 When this bit is set to 1, the GMACAXI is allowed to select a
+ *  burst length of 256 on the AXI master interface This bit is present only when the
+ *  configuration parameter AXI_BL is set to 256 Otherwise, this bit is reserved and is
+ *  readonly _RO_
+ */
+#define GMAC_BLEN256    (BIT(7))
+#define GMAC_BLEN256_M  (GMAC_BLEN256_V << GMAC_BLEN256_S)
+#define GMAC_BLEN256_V  0x00000001U
+#define GMAC_BLEN256_S  7
+/** GMAC_AXI_AAL : RO; bitpos: [12]; default: 0;
+ *  AddressAligned Beats This bit is readonly bit and reflects the Bit 25 _AAL_ of
+ *  Register 0 _Bus Mode Register_ When this bit is set to 1, the GMACAXI performs
+ *  addressaligned burst transfers on both read and write channels 11:8		Reserved	0H	RO
+ */
+#define GMAC_AXI_AAL    (BIT(12))
+#define GMAC_AXI_AAL_M  (GMAC_AXI_AAL_V << GMAC_AXI_AAL_S)
+#define GMAC_AXI_AAL_V  0x00000001U
+#define GMAC_AXI_AAL_S  12
+/** GMAC_ONEKBBE : R/W; bitpos: [13]; default: 0;
+ *  1 KB Boundary Crossing Enable for the GMACAXI Master When set, the GMACAXI master
+ *  performs burst transfers that do not cross 1 KB boundary When reset, the GMACAXI
+ *  master performs burst transfers that do not cross 4 KB boundary
+ */
+#define GMAC_ONEKBBE    (BIT(13))
+#define GMAC_ONEKBBE_M  (GMAC_ONEKBBE_V << GMAC_ONEKBBE_S)
+#define GMAC_ONEKBBE_V  0x00000001U
+#define GMAC_ONEKBBE_S  13
+/** GMAC_RD_OSR_LMT : R/W; bitpos: [19:16]; default: 1;
+ *  AXI Maximum Read Outstanding Request Limit This value limits the maximum
+ *  outstanding request on the AXI read interface Maximum outstanding requests =
+ *  RD_OSR_LMT+1 Note: Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4 Bit 19 is
+ *  reserved if AXI_GM_MAX_RD_REQUESTS != 16 15:14		Reserved	00	RO
+ */
+#define GMAC_RD_OSR_LMT    0x0000000FU
+#define GMAC_RD_OSR_LMT_M  (GMAC_RD_OSR_LMT_V << GMAC_RD_OSR_LMT_S)
+#define GMAC_RD_OSR_LMT_V  0x0000000FU
+#define GMAC_RD_OSR_LMT_S  16
+/** GMAC_WR_OSR_LMT : R/W; bitpos: [23:20]; default: 1;
+ *  AXI Maximum Write Outstanding Request Limit This value limits the maximum
+ *  outstanding request on the AXI write interface Maximum outstanding requests =
+ *  WR_OSR_LMT+1 Note: Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4 Bit 23 bit is
+ *  reserved if AXI_GM_MAX_WR_REQUESTS != 16
+ */
+#define GMAC_WR_OSR_LMT    0x0000000FU
+#define GMAC_WR_OSR_LMT_M  (GMAC_WR_OSR_LMT_V << GMAC_WR_OSR_LMT_S)
+#define GMAC_WR_OSR_LMT_V  0x0000000FU
+#define GMAC_WR_OSR_LMT_S  20
+/** GMAC_LPI_XIT_FRM : R/W; bitpos: [30]; default: 0;
+ *  Unlock on Magic Packet or Remote WakeUp Frame When set to 1, this bit enables the
+ *  GMACAXI to come out of the LPI mode only when the magic packet or remote wakeup
+ *  frame is received When set to 0, this bit enables the GMACAXI to come out of LPI
+ *  mode when any frame is received 29:24		Reserved	00H	RO
+ */
+#define GMAC_LPI_XIT_FRM    (BIT(30))
+#define GMAC_LPI_XIT_FRM_M  (GMAC_LPI_XIT_FRM_V << GMAC_LPI_XIT_FRM_S)
+#define GMAC_LPI_XIT_FRM_V  0x00000001U
+#define GMAC_LPI_XIT_FRM_S  30
+/** GMAC_EN_LPI : R/W; bitpos: [31]; default: 0;
+ *  Enable Low Power Interface _LPI_ When set to 1, this bit enables the LPI mode
+ *  supported by the GMACAXI configuration and accepts the LPI request from the AXI
+ *  System Clock controller When set to 0, this bit disables the LPI mode and always
+ *  denies the LPI request from the AXI System Clock controller
+ */
+#define GMAC_EN_LPI    (BIT(31))
+#define GMAC_EN_LPI_M  (GMAC_EN_LPI_V << GMAC_EN_LPI_S)
+#define GMAC_EN_LPI_V  0x00000001U
+#define GMAC_EN_LPI_S  31
+
+/** GMAC_REGISTER11_AHBORAXISTATUSREGISTER_REG register
+ *  Gives the idle status of the AHB master interface in the GMACAHB configuration
+ *  Gives the idle status of the AXI master's read or write channel in the GMACAXI
+ *  configuration
+ */
+#define GMAC_REGISTER11_AHBORAXISTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x102c)
+/** GMAC_AXWHSTS : RO; bitpos: [0]; default: 0;
+ *  AXI Master Write Channel or AHB Master Status When high, it indicates that AXI
+ *  master's write channel is active and transferring data in the GMACAXI configuration
+ *  In the GMACAHB configuration, it indicates that the AHB master interface FSMs are
+ *  in the nonidle state
+ */
+#define GMAC_AXWHSTS    (BIT(0))
+#define GMAC_AXWHSTS_M  (GMAC_AXWHSTS_V << GMAC_AXWHSTS_S)
+#define GMAC_AXWHSTS_V  0x00000001U
+#define GMAC_AXWHSTS_S  0
+/** GMAC_AXIRDSTS : RO; bitpos: [1]; default: 0;
+ *  AXI Master Read Channel Status When high, it indicates that AXI master's read
+ *  channel is active and transferring data
+ */
+#define GMAC_AXIRDSTS    (BIT(1))
+#define GMAC_AXIRDSTS_M  (GMAC_AXIRDSTS_V << GMAC_AXIRDSTS_S)
+#define GMAC_AXIRDSTS_V  0x00000001U
+#define GMAC_AXIRDSTS_S  1
+
+/** GMAC_REGISTER18_CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define GMAC_REGISTER18_CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x1048)
+/** GMAC_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define GMAC_CURTDESAPTR    0xFFFFFFFFU
+#define GMAC_CURTDESAPTR_M  (GMAC_CURTDESAPTR_V << GMAC_CURTDESAPTR_S)
+#define GMAC_CURTDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CURTDESAPTR_S  0
+
+/** GMAC_REGISTER19_CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define GMAC_REGISTER19_CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x104c)
+/** GMAC_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define GMAC_CURRDESAPTR    0xFFFFFFFFU
+#define GMAC_CURRDESAPTR_M  (GMAC_CURRDESAPTR_V << GMAC_CURRDESAPTR_S)
+#define GMAC_CURRDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CURRDESAPTR_S  0
+
+/** GMAC_REGISTER20_CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define GMAC_REGISTER20_CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1050)
+/** GMAC_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define GMAC_CURTBUFAPTR    0xFFFFFFFFU
+#define GMAC_CURTBUFAPTR_M  (GMAC_CURTBUFAPTR_V << GMAC_CURTBUFAPTR_S)
+#define GMAC_CURTBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CURTBUFAPTR_S  0
+
+/** GMAC_REGISTER21_CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define GMAC_REGISTER21_CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1054)
+/** GMAC_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define GMAC_CURRBUFAPTR    0xFFFFFFFFU
+#define GMAC_CURRBUFAPTR_M  (GMAC_CURRBUFAPTR_V << GMAC_CURRBUFAPTR_S)
+#define GMAC_CURRBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CURRBUFAPTR_S  0
+
+/** GMAC_REGISTER22_HWFEATUREREGISTER_REG register
+ *  Indicates the presence of the optional features of the core
+ */
+#define GMAC_REGISTER22_HWFEATUREREGISTER_REG (DR_REG_GMAC_BASE + 0x1058)
+/** GMAC_MIISEL : RO; bitpos: [0]; default: 0;
+ *  10 or 100 Mbps support
+ */
+#define GMAC_MIISEL    (BIT(0))
+#define GMAC_MIISEL_M  (GMAC_MIISEL_V << GMAC_MIISEL_S)
+#define GMAC_MIISEL_V  0x00000001U
+#define GMAC_MIISEL_S  0
+/** GMAC_GMIISEL : RO; bitpos: [1]; default: 0;
+ *  1000 Mbps support
+ */
+#define GMAC_GMIISEL    (BIT(1))
+#define GMAC_GMIISEL_M  (GMAC_GMIISEL_V << GMAC_GMIISEL_S)
+#define GMAC_GMIISEL_V  0x00000001U
+#define GMAC_GMIISEL_S  1
+/** GMAC_HDSEL : RO; bitpos: [2]; default: 0;
+ *  Halfduplex support
+ */
+#define GMAC_HDSEL    (BIT(2))
+#define GMAC_HDSEL_M  (GMAC_HDSEL_V << GMAC_HDSEL_S)
+#define GMAC_HDSEL_V  0x00000001U
+#define GMAC_HDSEL_S  2
+/** GMAC_EXTHASHEN : RO; bitpos: [3]; default: 0;
+ *  Expanded DA Hash filter
+ */
+#define GMAC_EXTHASHEN    (BIT(3))
+#define GMAC_EXTHASHEN_M  (GMAC_EXTHASHEN_V << GMAC_EXTHASHEN_S)
+#define GMAC_EXTHASHEN_V  0x00000001U
+#define GMAC_EXTHASHEN_S  3
+/** GMAC_HASHSEL : RO; bitpos: [4]; default: 0;
+ *  HASH filter
+ */
+#define GMAC_HASHSEL    (BIT(4))
+#define GMAC_HASHSEL_M  (GMAC_HASHSEL_V << GMAC_HASHSEL_S)
+#define GMAC_HASHSEL_V  0x00000001U
+#define GMAC_HASHSEL_S  4
+/** GMAC_ADDMACADRSEL : RO; bitpos: [5]; default: 0;
+ *  Multiple MAC Address registers
+ */
+#define GMAC_ADDMACADRSEL    (BIT(5))
+#define GMAC_ADDMACADRSEL_M  (GMAC_ADDMACADRSEL_V << GMAC_ADDMACADRSEL_S)
+#define GMAC_ADDMACADRSEL_V  0x00000001U
+#define GMAC_ADDMACADRSEL_S  5
+/** GMAC_PCSSEL : RO; bitpos: [6]; default: 0;
+ *  PCS registers _TBI, SGMII, or RTBI PHY interface_
+ */
+#define GMAC_PCSSEL    (BIT(6))
+#define GMAC_PCSSEL_M  (GMAC_PCSSEL_V << GMAC_PCSSEL_S)
+#define GMAC_PCSSEL_V  0x00000001U
+#define GMAC_PCSSEL_S  6
+/** GMAC_L3L4FLTREN : RO; bitpos: [7]; default: 0;
+ *  Layer 3 and Layer 4 feature
+ */
+#define GMAC_L3L4FLTREN    (BIT(7))
+#define GMAC_L3L4FLTREN_M  (GMAC_L3L4FLTREN_V << GMAC_L3L4FLTREN_S)
+#define GMAC_L3L4FLTREN_V  0x00000001U
+#define GMAC_L3L4FLTREN_S  7
+/** GMAC_SMASEL : RO; bitpos: [8]; default: 0;
+ *  SMA _MDIO_ Interface
+ */
+#define GMAC_SMASEL    (BIT(8))
+#define GMAC_SMASEL_M  (GMAC_SMASEL_V << GMAC_SMASEL_S)
+#define GMAC_SMASEL_V  0x00000001U
+#define GMAC_SMASEL_S  8
+/** GMAC_RWKSEL : RO; bitpos: [9]; default: 0;
+ *  PMT remote wakeup frame
+ */
+#define GMAC_RWKSEL    (BIT(9))
+#define GMAC_RWKSEL_M  (GMAC_RWKSEL_V << GMAC_RWKSEL_S)
+#define GMAC_RWKSEL_V  0x00000001U
+#define GMAC_RWKSEL_S  9
+/** GMAC_MGKSEL : RO; bitpos: [10]; default: 0;
+ *  PMT magic packet
+ */
+#define GMAC_MGKSEL    (BIT(10))
+#define GMAC_MGKSEL_M  (GMAC_MGKSEL_V << GMAC_MGKSEL_S)
+#define GMAC_MGKSEL_V  0x00000001U
+#define GMAC_MGKSEL_S  10
+/** GMAC_MMCSEL : RO; bitpos: [11]; default: 0;
+ *  RMON module
+ */
+#define GMAC_MMCSEL    (BIT(11))
+#define GMAC_MMCSEL_M  (GMAC_MMCSEL_V << GMAC_MMCSEL_S)
+#define GMAC_MMCSEL_V  0x00000001U
+#define GMAC_MMCSEL_S  11
+/** GMAC_TSVER1SEL : RO; bitpos: [12]; default: 0;
+ *  Only IEEE 15882002 timestamp
+ */
+#define GMAC_TSVER1SEL    (BIT(12))
+#define GMAC_TSVER1SEL_M  (GMAC_TSVER1SEL_V << GMAC_TSVER1SEL_S)
+#define GMAC_TSVER1SEL_V  0x00000001U
+#define GMAC_TSVER1SEL_S  12
+/** GMAC_TSVER2SEL : RO; bitpos: [13]; default: 0;
+ *  IEEE 15882008 Advanced timestamp
+ */
+#define GMAC_TSVER2SEL    (BIT(13))
+#define GMAC_TSVER2SEL_M  (GMAC_TSVER2SEL_V << GMAC_TSVER2SEL_S)
+#define GMAC_TSVER2SEL_V  0x00000001U
+#define GMAC_TSVER2SEL_S  13
+/** GMAC_EEESEL : RO; bitpos: [14]; default: 0;
+ *  Energy Efficient Ethernet
+ */
+#define GMAC_EEESEL    (BIT(14))
+#define GMAC_EEESEL_M  (GMAC_EEESEL_V << GMAC_EEESEL_S)
+#define GMAC_EEESEL_V  0x00000001U
+#define GMAC_EEESEL_S  14
+/** GMAC_AVSEL : RO; bitpos: [15]; default: 0;
+ *  AV feature
+ */
+#define GMAC_AVSEL    (BIT(15))
+#define GMAC_AVSEL_M  (GMAC_AVSEL_V << GMAC_AVSEL_S)
+#define GMAC_AVSEL_V  0x00000001U
+#define GMAC_AVSEL_S  15
+/** GMAC_TXCOESEL : RO; bitpos: [16]; default: 0;
+ *  Checksum Offload in Tx
+ */
+#define GMAC_TXCOESEL    (BIT(16))
+#define GMAC_TXCOESEL_M  (GMAC_TXCOESEL_V << GMAC_TXCOESEL_S)
+#define GMAC_TXCOESEL_V  0x00000001U
+#define GMAC_TXCOESEL_S  16
+/** GMAC_RXTYP1COE : RO; bitpos: [17]; default: 0;
+ *  IP Checksum Offload _Type 1_ in Rx Note: If IPCHKSUM_EN = Enabled and
+ *  IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1
+ */
+#define GMAC_RXTYP1COE    (BIT(17))
+#define GMAC_RXTYP1COE_M  (GMAC_RXTYP1COE_V << GMAC_RXTYP1COE_S)
+#define GMAC_RXTYP1COE_V  0x00000001U
+#define GMAC_RXTYP1COE_S  17
+/** GMAC_RXTYP2COE : RO; bitpos: [18]; default: 0;
+ *  IP Checksum Offload _Type 2_ in Rx
+ */
+#define GMAC_RXTYP2COE    (BIT(18))
+#define GMAC_RXTYP2COE_M  (GMAC_RXTYP2COE_V << GMAC_RXTYP2COE_S)
+#define GMAC_RXTYP2COE_V  0x00000001U
+#define GMAC_RXTYP2COE_S  18
+/** GMAC_RXFIFOSIZE : RO; bitpos: [19]; default: 0;
+ *  Rx FIFO > 2,048 Bytes
+ */
+#define GMAC_RXFIFOSIZE    (BIT(19))
+#define GMAC_RXFIFOSIZE_M  (GMAC_RXFIFOSIZE_V << GMAC_RXFIFOSIZE_S)
+#define GMAC_RXFIFOSIZE_V  0x00000001U
+#define GMAC_RXFIFOSIZE_S  19
+/** GMAC_RXCHCNT : RO; bitpos: [21:20]; default: 0;
+ *  Number of additional Rx Channels
+ */
+#define GMAC_RXCHCNT    0x00000003U
+#define GMAC_RXCHCNT_M  (GMAC_RXCHCNT_V << GMAC_RXCHCNT_S)
+#define GMAC_RXCHCNT_V  0x00000003U
+#define GMAC_RXCHCNT_S  20
+/** GMAC_TXCHCNT : RO; bitpos: [23:22]; default: 0;
+ *  Number of additional Tx Channels
+ */
+#define GMAC_TXCHCNT    0x00000003U
+#define GMAC_TXCHCNT_M  (GMAC_TXCHCNT_V << GMAC_TXCHCNT_S)
+#define GMAC_TXCHCNT_V  0x00000003U
+#define GMAC_TXCHCNT_S  22
+/** GMAC_ENHDESSEL : RO; bitpos: [24]; default: 0;
+ *  Alternate _Enhanced Descriptor_
+ */
+#define GMAC_ENHDESSEL    (BIT(24))
+#define GMAC_ENHDESSEL_M  (GMAC_ENHDESSEL_V << GMAC_ENHDESSEL_S)
+#define GMAC_ENHDESSEL_V  0x00000001U
+#define GMAC_ENHDESSEL_S  24
+/** GMAC_INTTSEN : RO; bitpos: [25]; default: 0;
+ *  Timestamping with Internal System Time
+ */
+#define GMAC_INTTSEN    (BIT(25))
+#define GMAC_INTTSEN_M  (GMAC_INTTSEN_V << GMAC_INTTSEN_S)
+#define GMAC_INTTSEN_V  0x00000001U
+#define GMAC_INTTSEN_S  25
+/** GMAC_FLEXIPPSEN : RO; bitpos: [26]; default: 0;
+ *  Flexible PulsePerSecond Output
+ */
+#define GMAC_FLEXIPPSEN    (BIT(26))
+#define GMAC_FLEXIPPSEN_M  (GMAC_FLEXIPPSEN_V << GMAC_FLEXIPPSEN_S)
+#define GMAC_FLEXIPPSEN_V  0x00000001U
+#define GMAC_FLEXIPPSEN_S  26
+/** GMAC_SAVLANINS : RO; bitpos: [27]; default: 0;
+ *  Source Address or VLAN Insertion
+ */
+#define GMAC_SAVLANINS    (BIT(27))
+#define GMAC_SAVLANINS_M  (GMAC_SAVLANINS_V << GMAC_SAVLANINS_S)
+#define GMAC_SAVLANINS_V  0x00000001U
+#define GMAC_SAVLANINS_S  27
+/** GMAC_ACTPHYIF : RO; bitpos: [30:28]; default: 0;
+ *  Active or selected PHY interface When you have multiple PHY interfaces in your
+ *  configuration, this field indicates the sampled value of phy_intf_sel_i during
+ *  reset deassertion 000: GMII or MII 001: RGMII 010: SGMII 011: TBI 100: RMII 101:
+ *  RTBI 110: SMII 111: RevMII All Others: Reserved
+ */
+#define GMAC_ACTPHYIF    0x00000007U
+#define GMAC_ACTPHYIF_M  (GMAC_ACTPHYIF_V << GMAC_ACTPHYIF_S)
+#define GMAC_ACTPHYIF_V  0x00000007U
+#define GMAC_ACTPHYIF_S  28
+
+/** GMAC_REGISTER64_CHANNEL1BUSMODEREGISTER_REG register
+ *  Controls the Host Interface mode for Channel 1
+ */
+#define GMAC_REGISTER64_CHANNEL1BUSMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1100)
+/** GMAC_CH1_SWR : R/W1S; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+ *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define GMAC_CH1_SWR    (BIT(0))
+#define GMAC_CH1_SWR_M  (GMAC_CH1_SWR_V << GMAC_CH1_SWR_S)
+#define GMAC_CH1_SWR_V  0x00000001U
+#define GMAC_CH1_SWR_S  0
+/** GMAC_CH1_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 1 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the GMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define GMAC_CH1_DA    (BIT(1))
+#define GMAC_CH1_DA_M  (GMAC_CH1_DA_V << GMAC_CH1_DA_S)
+#define GMAC_CH1_DA_V  0x00000001U
+#define GMAC_CH1_DA_S  1
+/** GMAC_CH1_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define GMAC_CH1_DSL    0x0000001FU
+#define GMAC_CH1_DSL_M  (GMAC_CH1_DSL_V << GMAC_CH1_DSL_S)
+#define GMAC_CH1_DSL_V  0x0000001FU
+#define GMAC_CH1_DSL_S  2
+/** GMAC_CH1_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define GMAC_CH1_ATDS    (BIT(7))
+#define GMAC_CH1_ATDS_M  (GMAC_CH1_ATDS_V << GMAC_CH1_ATDS_S)
+#define GMAC_CH1_ATDS_V  0x00000001U
+#define GMAC_CH1_ATDS_S  7
+/** GMAC_CH1_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define GMAC_CH1_PBL    0x0000003FU
+#define GMAC_CH1_PBL_M  (GMAC_CH1_PBL_V << GMAC_CH1_PBL_S)
+#define GMAC_CH1_PBL_V  0x0000003FU
+#define GMAC_CH1_PBL_S  8
+/** GMAC_CH1_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define GMAC_CH1_PR    0x00000003U
+#define GMAC_CH1_PR_M  (GMAC_CH1_PR_V << GMAC_CH1_PR_S)
+#define GMAC_CH1_PR_V  0x00000003U
+#define GMAC_CH1_PR_S  14
+/** GMAC_CH1_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+ */
+#define GMAC_CH1_FB    (BIT(16))
+#define GMAC_CH1_FB_M  (GMAC_CH1_FB_V << GMAC_CH1_FB_S)
+#define GMAC_CH1_FB_V  0x00000001U
+#define GMAC_CH1_FB_S  16
+/** GMAC_CH1_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define GMAC_CH1_RPBL    0x0000003FU
+#define GMAC_CH1_RPBL_M  (GMAC_CH1_RPBL_V << GMAC_CH1_RPBL_S)
+#define GMAC_CH1_RPBL_V  0x0000003FU
+#define GMAC_CH1_RPBL_S  17
+/** GMAC_CH1_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define GMAC_CH1_USP    (BIT(23))
+#define GMAC_CH1_USP_M  (GMAC_CH1_USP_V << GMAC_CH1_USP_S)
+#define GMAC_CH1_USP_V  0x00000001U
+#define GMAC_CH1_USP_S  23
+/** GMAC_CH1_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define GMAC_CH1_PBLX8    (BIT(24))
+#define GMAC_CH1_PBLX8_M  (GMAC_CH1_PBLX8_V << GMAC_CH1_PBLX8_S)
+#define GMAC_CH1_PBLX8_V  0x00000001U
+#define GMAC_CH1_PBLX8_S  24
+/** GMAC_CH1_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define GMAC_CH1_AAL    (BIT(25))
+#define GMAC_CH1_AAL_M  (GMAC_CH1_AAL_V << GMAC_CH1_AAL_S)
+#define GMAC_CH1_AAL_V  0x00000001U
+#define GMAC_CH1_AAL_S  25
+/** GMAC_CH1_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define GMAC_CH1_MB    (BIT(26))
+#define GMAC_CH1_MB_M  (GMAC_CH1_MB_V << GMAC_CH1_MB_S)
+#define GMAC_CH1_MB_V  0x00000001U
+#define GMAC_CH1_MB_S  26
+/** GMAC_CH1_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_CH1_TXPR    (BIT(27))
+#define GMAC_CH1_TXPR_M  (GMAC_CH1_TXPR_V << GMAC_CH1_TXPR_S)
+#define GMAC_CH1_TXPR_V  0x00000001U
+#define GMAC_CH1_TXPR_S  27
+/** GMAC_CH1_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 1 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_gmac configurations
+ *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_CH1_PRWG    0x00000003U
+#define GMAC_CH1_PRWG_M  (GMAC_CH1_PRWG_V << GMAC_CH1_PRWG_S)
+#define GMAC_CH1_PRWG_V  0x00000003U
+#define GMAC_CH1_PRWG_S  28
+/** GMAC_CH1_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define GMAC_CH1_RIB    (BIT(31))
+#define GMAC_CH1_RIB_M  (GMAC_CH1_RIB_V << GMAC_CH1_RIB_S)
+#define GMAC_CH1_RIB_V  0x00000001U
+#define GMAC_CH1_RIB_S  31
+
+/** GMAC_REGISTER65_CHANNEL1TRANSMITPOLLDEMANDREGISTER_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define GMAC_REGISTER65_CHANNEL1TRANSMITPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1104)
+/** GMAC_CH1_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define GMAC_CH1_TPD    0xFFFFFFFFU
+#define GMAC_CH1_TPD_M  (GMAC_CH1_TPD_V << GMAC_CH1_TPD_S)
+#define GMAC_CH1_TPD_V  0xFFFFFFFFU
+#define GMAC_CH1_TPD_S  0
+
+/** GMAC_REGISTER66_CHANNEL1RECEIVEPOLLDEMANDREGISTER_REG register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define GMAC_REGISTER66_CHANNEL1RECEIVEPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1108)
+/** GMAC_CH1_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define GMAC_CH1_RPD    0xFFFFFFFFU
+#define GMAC_CH1_RPD_M  (GMAC_CH1_RPD_V << GMAC_CH1_RPD_S)
+#define GMAC_CH1_RPD_V  0xFFFFFFFFU
+#define GMAC_CH1_RPD_S  0
+
+/** GMAC_REGISTER67_CHANNEL1RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define GMAC_REGISTER67_CHANNEL1RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x110c)
+/** GMAC_CH1_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define GMAC_CH1_RDESLA    0xFFFFFFFFU
+#define GMAC_CH1_RDESLA_M  (GMAC_CH1_RDESLA_V << GMAC_CH1_RDESLA_S)
+#define GMAC_CH1_RDESLA_V  0xFFFFFFFFU
+#define GMAC_CH1_RDESLA_S  0
+
+/** GMAC_REGISTER68_CHANNEL1TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+#define GMAC_REGISTER68_CHANNEL1TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1110)
+/** GMAC_CH1_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define GMAC_CH1_TDESLA    0xFFFFFFFFU
+#define GMAC_CH1_TDESLA_M  (GMAC_CH1_TDESLA_V << GMAC_CH1_TDESLA_S)
+#define GMAC_CH1_TDESLA_V  0xFFFFFFFFU
+#define GMAC_CH1_TDESLA_S  0
+
+/** GMAC_REGISTER69_CHANNEL1STATUSREGISTER_REG register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits 29:26 are reserved for
+ *  the Channel 1 Status Register
+ */
+#define GMAC_REGISTER69_CHANNEL1STATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1114)
+/** GMAC_CH1_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define GMAC_CH1_TI    (BIT(0))
+#define GMAC_CH1_TI_M  (GMAC_CH1_TI_V << GMAC_CH1_TI_S)
+#define GMAC_CH1_TI_V  0x00000001U
+#define GMAC_CH1_TI_S  0
+/** GMAC_CH1_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define GMAC_CH1_TPS    (BIT(1))
+#define GMAC_CH1_TPS_M  (GMAC_CH1_TPS_V << GMAC_CH1_TPS_S)
+#define GMAC_CH1_TPS_V  0x00000001U
+#define GMAC_CH1_TPS_S  1
+/** GMAC_CH1_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define GMAC_CH1_TU    (BIT(2))
+#define GMAC_CH1_TU_M  (GMAC_CH1_TU_V << GMAC_CH1_TU_S)
+#define GMAC_CH1_TU_V  0x00000001U
+#define GMAC_CH1_TU_S  2
+/** GMAC_CH1_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define GMAC_CH1_TJT    (BIT(3))
+#define GMAC_CH1_TJT_M  (GMAC_CH1_TJT_V << GMAC_CH1_TJT_S)
+#define GMAC_CH1_TJT_V  0x00000001U
+#define GMAC_CH1_TJT_S  3
+/** GMAC_CH1_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define GMAC_CH1_OVF    (BIT(4))
+#define GMAC_CH1_OVF_M  (GMAC_CH1_OVF_V << GMAC_CH1_OVF_S)
+#define GMAC_CH1_OVF_V  0x00000001U
+#define GMAC_CH1_OVF_S  4
+/** GMAC_CH1_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define GMAC_CH1_UNF    (BIT(5))
+#define GMAC_CH1_UNF_M  (GMAC_CH1_UNF_V << GMAC_CH1_UNF_S)
+#define GMAC_CH1_UNF_V  0x00000001U
+#define GMAC_CH1_UNF_S  5
+/** GMAC_CH1_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define GMAC_CH1_RI    (BIT(6))
+#define GMAC_CH1_RI_M  (GMAC_CH1_RI_V << GMAC_CH1_RI_S)
+#define GMAC_CH1_RI_V  0x00000001U
+#define GMAC_CH1_RI_S  6
+/** GMAC_CH1_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define GMAC_CH1_RU    (BIT(7))
+#define GMAC_CH1_RU_M  (GMAC_CH1_RU_V << GMAC_CH1_RU_S)
+#define GMAC_CH1_RU_V  0x00000001U
+#define GMAC_CH1_RU_S  7
+/** GMAC_CH1_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define GMAC_CH1_RPS    (BIT(8))
+#define GMAC_CH1_RPS_M  (GMAC_CH1_RPS_V << GMAC_CH1_RPS_S)
+#define GMAC_CH1_RPS_V  0x00000001U
+#define GMAC_CH1_RPS_S  8
+/** GMAC_CH1_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define GMAC_CH1_RWT    (BIT(9))
+#define GMAC_CH1_RWT_M  (GMAC_CH1_RWT_V << GMAC_CH1_RWT_S)
+#define GMAC_CH1_RWT_V  0x00000001U
+#define GMAC_CH1_RWT_S  9
+/** GMAC_CH1_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define GMAC_CH1_ETI    (BIT(10))
+#define GMAC_CH1_ETI_M  (GMAC_CH1_ETI_V << GMAC_CH1_ETI_S)
+#define GMAC_CH1_ETI_V  0x00000001U
+#define GMAC_CH1_ETI_S  10
+/** GMAC_CH1_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define GMAC_CH1_FBI    (BIT(13))
+#define GMAC_CH1_FBI_M  (GMAC_CH1_FBI_V << GMAC_CH1_FBI_S)
+#define GMAC_CH1_FBI_V  0x00000001U
+#define GMAC_CH1_FBI_S  13
+/** GMAC_CH1_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define GMAC_CH1_ERI    (BIT(14))
+#define GMAC_CH1_ERI_M  (GMAC_CH1_ERI_V << GMAC_CH1_ERI_S)
+#define GMAC_CH1_ERI_V  0x00000001U
+#define GMAC_CH1_ERI_S  14
+/** GMAC_CH1_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define GMAC_CH1_AIS    (BIT(15))
+#define GMAC_CH1_AIS_M  (GMAC_CH1_AIS_V << GMAC_CH1_AIS_S)
+#define GMAC_CH1_AIS_V  0x00000001U
+#define GMAC_CH1_AIS_S  15
+/** GMAC_CH1_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define GMAC_CH1_NIS    (BIT(16))
+#define GMAC_CH1_NIS_M  (GMAC_CH1_NIS_V << GMAC_CH1_NIS_S)
+#define GMAC_CH1_NIS_V  0x00000001U
+#define GMAC_CH1_NIS_S  16
+/** GMAC_CH1_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define GMAC_CH1_RS    0x00000007U
+#define GMAC_CH1_RS_M  (GMAC_CH1_RS_V << GMAC_CH1_RS_S)
+#define GMAC_CH1_RS_V  0x00000007U
+#define GMAC_CH1_RS_S  17
+/** GMAC_CH1_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define GMAC_CH1_TS    0x00000007U
+#define GMAC_CH1_TS_M  (GMAC_CH1_TS_V << GMAC_CH1_TS_S)
+#define GMAC_CH1_TS_V  0x00000007U
+#define GMAC_CH1_TS_S  20
+/** GMAC_CH1_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define GMAC_CH1_EB    0x00000007U
+#define GMAC_CH1_EB_M  (GMAC_CH1_EB_V << GMAC_CH1_EB_S)
+#define GMAC_CH1_EB_V  0x00000007U
+#define GMAC_CH1_EB_S  23
+/** GMAC_CH1_GLI : RO; bitpos: [26]; default: 0;
+ *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define GMAC_CH1_GLI    (BIT(26))
+#define GMAC_CH1_GLI_M  (GMAC_CH1_GLI_V << GMAC_CH1_GLI_S)
+#define GMAC_CH1_GLI_V  0x00000001U
+#define GMAC_CH1_GLI_S  26
+/** GMAC_CH1_GMI : RO; bitpos: [27]; default: 0;
+ *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define GMAC_CH1_GMI    (BIT(27))
+#define GMAC_CH1_GMI_M  (GMAC_CH1_GMI_V << GMAC_CH1_GMI_S)
+#define GMAC_CH1_GMI_V  0x00000001U
+#define GMAC_CH1_GMI_S  27
+/** GMAC_CH1_GPI : RO; bitpos: [28]; default: 0;
+ *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define GMAC_CH1_GPI    (BIT(28))
+#define GMAC_CH1_GPI_M  (GMAC_CH1_GPI_V << GMAC_CH1_GPI_S)
+#define GMAC_CH1_GPI_V  0x00000001U
+#define GMAC_CH1_GPI_S  28
+/** GMAC_CH1_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_gmac The software must read the corresponding registers
+ *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define GMAC_CH1_TTI    (BIT(29))
+#define GMAC_CH1_TTI_M  (GMAC_CH1_TTI_V << GMAC_CH1_TTI_S)
+#define GMAC_CH1_TTI_V  0x00000001U
+#define GMAC_CH1_TTI_S  29
+/** GMAC_CH1_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GTMSI: GMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+ *  interrupt event in the traffic manager and scheduler logic of DWC_gmac To reset
+ *  this bit, the software must read the corresponding registers _Channel Status
+ *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+ *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+ *  enabled and corresponding additional transmit channels are present Otherwise, this
+ *  bit is reserved When this bit is high, the interrupt signal from the MAC
+ *  _sbd_intr_o_ is high
+ */
+#define GMAC_CH1_GLPII_GTMSI    (BIT(30))
+#define GMAC_CH1_GLPII_GTMSI_M  (GMAC_CH1_GLPII_GTMSI_V << GMAC_CH1_GLPII_GTMSI_S)
+#define GMAC_CH1_GLPII_GTMSI_V  0x00000001U
+#define GMAC_CH1_GLPII_GTMSI_S  30
+
+/** GMAC_REGISTER70_CHANNEL1OPERATIONMODEREGISTER_REG register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+#define GMAC_REGISTER70_CHANNEL1OPERATIONMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1118)
+/** GMAC_CH1_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define GMAC_CH1_SR    (BIT(1))
+#define GMAC_CH1_SR_M  (GMAC_CH1_SR_V << GMAC_CH1_SR_S)
+#define GMAC_CH1_SR_V  0x00000001U
+#define GMAC_CH1_SR_S  1
+/** GMAC_CH1_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define GMAC_CH1_OSF    (BIT(2))
+#define GMAC_CH1_OSF_M  (GMAC_CH1_OSF_V << GMAC_CH1_OSF_S)
+#define GMAC_CH1_OSF_V  0x00000001U
+#define GMAC_CH1_OSF_S  2
+/** GMAC_CH1_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define GMAC_CH1_RTC    0x00000003U
+#define GMAC_CH1_RTC_M  (GMAC_CH1_RTC_V << GMAC_CH1_RTC_S)
+#define GMAC_CH1_RTC_V  0x00000003U
+#define GMAC_CH1_RTC_S  3
+/** GMAC_CH1_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define GMAC_CH1_DGF    (BIT(5))
+#define GMAC_CH1_DGF_M  (GMAC_CH1_DGF_V << GMAC_CH1_DGF_S)
+#define GMAC_CH1_DGF_V  0x00000001U
+#define GMAC_CH1_DGF_S  5
+/** GMAC_CH1_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define GMAC_CH1_FUF    (BIT(6))
+#define GMAC_CH1_FUF_M  (GMAC_CH1_FUF_V << GMAC_CH1_FUF_S)
+#define GMAC_CH1_FUF_V  0x00000001U
+#define GMAC_CH1_FUF_S  6
+/** GMAC_CH1_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+ *  configurations
+ */
+#define GMAC_CH1_FEF    (BIT(7))
+#define GMAC_CH1_FEF_M  (GMAC_CH1_FEF_V << GMAC_CH1_FEF_S)
+#define GMAC_CH1_FEF_V  0x00000001U
+#define GMAC_CH1_FEF_S  7
+/** GMAC_CH1_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define GMAC_CH1_EFC    (BIT(8))
+#define GMAC_CH1_EFC_M  (GMAC_CH1_EFC_V << GMAC_CH1_EFC_S)
+#define GMAC_CH1_EFC_V  0x00000001U
+#define GMAC_CH1_EFC_S  8
+/** GMAC_CH1_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define GMAC_CH1_RFA    0x00000003U
+#define GMAC_CH1_RFA_M  (GMAC_CH1_RFA_V << GMAC_CH1_RFA_S)
+#define GMAC_CH1_RFA_V  0x00000003U
+#define GMAC_CH1_RFA_S  9
+/** GMAC_CH1_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define GMAC_CH1_RFD    0x00000003U
+#define GMAC_CH1_RFD_M  (GMAC_CH1_RFD_V << GMAC_CH1_RFD_S)
+#define GMAC_CH1_RFD_V  0x00000003U
+#define GMAC_CH1_RFD_S  11
+/** GMAC_CH1_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define GMAC_CH1_ST    (BIT(13))
+#define GMAC_CH1_ST_M  (GMAC_CH1_ST_V << GMAC_CH1_ST_S)
+#define GMAC_CH1_ST_V  0x00000001U
+#define GMAC_CH1_ST_S  13
+/** GMAC_CH1_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define GMAC_CH1_TTC    0x00000007U
+#define GMAC_CH1_TTC_M  (GMAC_CH1_TTC_V << GMAC_CH1_TTC_S)
+#define GMAC_CH1_TTC_V  0x00000007U
+#define GMAC_CH1_TTC_S  14
+/** GMAC_CH1_FTF : R/W1S; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define GMAC_CH1_FTF    (BIT(20))
+#define GMAC_CH1_FTF_M  (GMAC_CH1_FTF_V << GMAC_CH1_FTF_S)
+#define GMAC_CH1_FTF_V  0x00000001U
+#define GMAC_CH1_FTF_S  20
+/** GMAC_CH1_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define GMAC_CH1_TSF    (BIT(21))
+#define GMAC_CH1_TSF_M  (GMAC_CH1_TSF_V << GMAC_CH1_TSF_S)
+#define GMAC_CH1_TSF_V  0x00000001U
+#define GMAC_CH1_TSF_S  21
+/** GMAC_CH1_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define GMAC_CH1_RFD_2    (BIT(22))
+#define GMAC_CH1_RFD_2_M  (GMAC_CH1_RFD_2_V << GMAC_CH1_RFD_2_S)
+#define GMAC_CH1_RFD_2_V  0x00000001U
+#define GMAC_CH1_RFD_2_S  22
+/** GMAC_CH1_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define GMAC_CH1_RFA_2    (BIT(23))
+#define GMAC_CH1_RFA_2_M  (GMAC_CH1_RFA_2_V << GMAC_CH1_RFA_2_S)
+#define GMAC_CH1_RFA_2_V  0x00000001U
+#define GMAC_CH1_RFA_2_S  23
+/** GMAC_CH1_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the GMACMTL configuration
+ */
+#define GMAC_CH1_DFF    (BIT(24))
+#define GMAC_CH1_DFF_M  (GMAC_CH1_DFF_V << GMAC_CH1_DFF_S)
+#define GMAC_CH1_DFF_V  0x00000001U
+#define GMAC_CH1_DFF_S  24
+/** GMAC_CH1_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define GMAC_CH1_RSF    (BIT(25))
+#define GMAC_CH1_RSF_M  (GMAC_CH1_RSF_V << GMAC_CH1_RSF_S)
+#define GMAC_CH1_RSF_V  0x00000001U
+#define GMAC_CH1_RSF_S  25
+/** GMAC_CH1_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define GMAC_CH1_DT    (BIT(26))
+#define GMAC_CH1_DT_M  (GMAC_CH1_DT_V << GMAC_CH1_DT_S)
+#define GMAC_CH1_DT_V  0x00000001U
+#define GMAC_CH1_DT_S  26
+
+/** GMAC_REGISTER71_CHANNEL1INTERRUPTENABLEREGISTER_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define GMAC_REGISTER71_CHANNEL1INTERRUPTENABLEREGISTER_REG (DR_REG_GMAC_BASE + 0x111c)
+/** GMAC_CH1_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define GMAC_CH1_TIE    (BIT(0))
+#define GMAC_CH1_TIE_M  (GMAC_CH1_TIE_V << GMAC_CH1_TIE_S)
+#define GMAC_CH1_TIE_V  0x00000001U
+#define GMAC_CH1_TIE_S  0
+/** GMAC_CH1_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define GMAC_CH1_TSE    (BIT(1))
+#define GMAC_CH1_TSE_M  (GMAC_CH1_TSE_V << GMAC_CH1_TSE_S)
+#define GMAC_CH1_TSE_V  0x00000001U
+#define GMAC_CH1_TSE_S  1
+/** GMAC_CH1_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_CH1_TUE    (BIT(2))
+#define GMAC_CH1_TUE_M  (GMAC_CH1_TUE_V << GMAC_CH1_TUE_S)
+#define GMAC_CH1_TUE_V  0x00000001U
+#define GMAC_CH1_TUE_S  2
+/** GMAC_CH1_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define GMAC_CH1_TJE    (BIT(3))
+#define GMAC_CH1_TJE_M  (GMAC_CH1_TJE_V << GMAC_CH1_TJE_S)
+#define GMAC_CH1_TJE_V  0x00000001U
+#define GMAC_CH1_TJE_S  3
+/** GMAC_CH1_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define GMAC_CH1_OVE    (BIT(4))
+#define GMAC_CH1_OVE_M  (GMAC_CH1_OVE_V << GMAC_CH1_OVE_S)
+#define GMAC_CH1_OVE_V  0x00000001U
+#define GMAC_CH1_OVE_S  4
+/** GMAC_CH1_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define GMAC_CH1_UNE    (BIT(5))
+#define GMAC_CH1_UNE_M  (GMAC_CH1_UNE_V << GMAC_CH1_UNE_S)
+#define GMAC_CH1_UNE_V  0x00000001U
+#define GMAC_CH1_UNE_S  5
+/** GMAC_CH1_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define GMAC_CH1_RIE    (BIT(6))
+#define GMAC_CH1_RIE_M  (GMAC_CH1_RIE_V << GMAC_CH1_RIE_S)
+#define GMAC_CH1_RIE_V  0x00000001U
+#define GMAC_CH1_RIE_S  6
+/** GMAC_CH1_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_CH1_RUE    (BIT(7))
+#define GMAC_CH1_RUE_M  (GMAC_CH1_RUE_V << GMAC_CH1_RUE_S)
+#define GMAC_CH1_RUE_V  0x00000001U
+#define GMAC_CH1_RUE_S  7
+/** GMAC_CH1_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define GMAC_CH1_RSE    (BIT(8))
+#define GMAC_CH1_RSE_M  (GMAC_CH1_RSE_V << GMAC_CH1_RSE_S)
+#define GMAC_CH1_RSE_V  0x00000001U
+#define GMAC_CH1_RSE_S  8
+/** GMAC_CH1_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define GMAC_CH1_RWE    (BIT(9))
+#define GMAC_CH1_RWE_M  (GMAC_CH1_RWE_V << GMAC_CH1_RWE_S)
+#define GMAC_CH1_RWE_V  0x00000001U
+#define GMAC_CH1_RWE_S  9
+/** GMAC_CH1_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define GMAC_CH1_ETE    (BIT(10))
+#define GMAC_CH1_ETE_M  (GMAC_CH1_ETE_V << GMAC_CH1_ETE_S)
+#define GMAC_CH1_ETE_V  0x00000001U
+#define GMAC_CH1_ETE_S  10
+/** GMAC_CH1_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define GMAC_CH1_FBE    (BIT(13))
+#define GMAC_CH1_FBE_M  (GMAC_CH1_FBE_V << GMAC_CH1_FBE_S)
+#define GMAC_CH1_FBE_V  0x00000001U
+#define GMAC_CH1_FBE_S  13
+/** GMAC_CH1_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define GMAC_CH1_ERE    (BIT(14))
+#define GMAC_CH1_ERE_M  (GMAC_CH1_ERE_V << GMAC_CH1_ERE_S)
+#define GMAC_CH1_ERE_V  0x00000001U
+#define GMAC_CH1_ERE_S  14
+/** GMAC_CH1_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define GMAC_CH1_AIE    (BIT(15))
+#define GMAC_CH1_AIE_M  (GMAC_CH1_AIE_V << GMAC_CH1_AIE_S)
+#define GMAC_CH1_AIE_V  0x00000001U
+#define GMAC_CH1_AIE_S  15
+/** GMAC_CH1_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define GMAC_CH1_NIE    (BIT(16))
+#define GMAC_CH1_NIE_M  (GMAC_CH1_NIE_V << GMAC_CH1_NIE_S)
+#define GMAC_CH1_NIE_V  0x00000001U
+#define GMAC_CH1_NIE_S  16
+
+/** GMAC_REGISTER72_CHANNEL1MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available, and discarded frames because of Receive FIFO Overflow
+ */
+#define GMAC_REGISTER72_CHANNEL1MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG (DR_REG_GMAC_BASE + 0x1120)
+/** GMAC_CH1_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define GMAC_CH1_MISFRMCNT    0x0000FFFFU
+#define GMAC_CH1_MISFRMCNT_M  (GMAC_CH1_MISFRMCNT_V << GMAC_CH1_MISFRMCNT_S)
+#define GMAC_CH1_MISFRMCNT_V  0x0000FFFFU
+#define GMAC_CH1_MISFRMCNT_S  0
+/** GMAC_CH1_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define GMAC_CH1_MISCNTOVF    (BIT(16))
+#define GMAC_CH1_MISCNTOVF_M  (GMAC_CH1_MISCNTOVF_V << GMAC_CH1_MISCNTOVF_S)
+#define GMAC_CH1_MISCNTOVF_V  0x00000001U
+#define GMAC_CH1_MISCNTOVF_S  16
+/** GMAC_CH1_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define GMAC_CH1_OVFFRMCNT    0x000007FFU
+#define GMAC_CH1_OVFFRMCNT_M  (GMAC_CH1_OVFFRMCNT_V << GMAC_CH1_OVFFRMCNT_S)
+#define GMAC_CH1_OVFFRMCNT_V  0x000007FFU
+#define GMAC_CH1_OVFFRMCNT_S  17
+/** GMAC_CH1_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define GMAC_CH1_OVFCNTOVF    (BIT(28))
+#define GMAC_CH1_OVFCNTOVF_M  (GMAC_CH1_OVFCNTOVF_V << GMAC_CH1_OVFCNTOVF_S)
+#define GMAC_CH1_OVFCNTOVF_V  0x00000001U
+#define GMAC_CH1_OVFCNTOVF_S  28
+
+/** GMAC_REGISTER73_CHANNEL1RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define GMAC_REGISTER73_CHANNEL1RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG (DR_REG_GMAC_BASE + 0x1124)
+/** GMAC_CH1_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define GMAC_CH1_RIWT    0x000000FFU
+#define GMAC_CH1_RIWT_M  (GMAC_CH1_RIWT_V << GMAC_CH1_RIWT_S)
+#define GMAC_CH1_RIWT_V  0x000000FFU
+#define GMAC_CH1_RIWT_S  0
+
+/** GMAC_REGISTER76_CHANNEL1SLOTFUNCTIONCONTROLANDSTATUSREGISTER_REG register
+ *  Contains the control bits for slot function and its status for Channel 1 transmit
+ *  path
+ */
+#define GMAC_REGISTER76_CHANNEL1SLOTFUNCTIONCONTROLANDSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1130)
+/** GMAC_ESC : R/W; bitpos: [0]; default: 0;
+ *  Enable Slot Comparison When set, this bit enables the checking of the slot numbers,
+ *  programmed in the transmit descriptor, with the current reference given in Bits
+ *  [19:16] The DMA fetches the data from the corresponding buffer only when the slot
+ *  number is equal to the reference slot number or is ahead of the reference slot
+ *  number by one slot When reset, this bit disables the checking of the slot numbers
+ *  The DMA fetches the data immediately after the descriptor is processed
+ */
+#define GMAC_ESC    (BIT(0))
+#define GMAC_ESC_M  (GMAC_ESC_V << GMAC_ESC_S)
+#define GMAC_ESC_V  0x00000001U
+#define GMAC_ESC_S  0
+/** GMAC_ASC : R/W; bitpos: [1]; default: 0;
+ *  Advance Slot Check When set, this bit enables the DMA to fetch the data from the
+ *  buffer when the slot number _SLOTNUM_ programmed in the transmit descriptor is:
+ *  equal to the reference slot number given in Bits [19:16] or ahead of the reference
+ *  slot number by up to two slots This bit is applicable only when Bit 0 _ESC_ is set
+ */
+#define GMAC_ASC    (BIT(1))
+#define GMAC_ASC_M  (GMAC_ASC_V << GMAC_ASC_S)
+#define GMAC_ASC_V  0x00000001U
+#define GMAC_ASC_S  1
+/** GMAC_RSN : RO; bitpos: [19:16]; default: 0;
+ *  Reference Slot Number This field gives the current value of the reference slot
+ *  number in DMA used for comparison checking
+ */
+#define GMAC_RSN    0x0000000FU
+#define GMAC_RSN_M  (GMAC_RSN_V << GMAC_RSN_S)
+#define GMAC_RSN_V  0x0000000FU
+#define GMAC_RSN_S  16
+
+/** GMAC_REGISTER82_CHANNEL1CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define GMAC_REGISTER82_CHANNEL1CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x1148)
+/** GMAC_CH1_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define GMAC_CH1_CURTDESAPTR    0xFFFFFFFFU
+#define GMAC_CH1_CURTDESAPTR_M  (GMAC_CH1_CURTDESAPTR_V << GMAC_CH1_CURTDESAPTR_S)
+#define GMAC_CH1_CURTDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CH1_CURTDESAPTR_S  0
+
+/** GMAC_REGISTER83_CHANNEL1CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define GMAC_REGISTER83_CHANNEL1CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x114c)
+/** GMAC_CH1_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define GMAC_CH1_CURRDESAPTR    0xFFFFFFFFU
+#define GMAC_CH1_CURRDESAPTR_M  (GMAC_CH1_CURRDESAPTR_V << GMAC_CH1_CURRDESAPTR_S)
+#define GMAC_CH1_CURRDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CH1_CURRDESAPTR_S  0
+
+/** GMAC_REGISTER84_CHANNEL1CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define GMAC_REGISTER84_CHANNEL1CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1150)
+/** GMAC_CH1_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define GMAC_CH1_CURTBUFAPTR    0xFFFFFFFFU
+#define GMAC_CH1_CURTBUFAPTR_M  (GMAC_CH1_CURTBUFAPTR_V << GMAC_CH1_CURTBUFAPTR_S)
+#define GMAC_CH1_CURTBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CH1_CURTBUFAPTR_S  0
+
+/** GMAC_REGISTER85_CHANNEL1CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define GMAC_REGISTER85_CHANNEL1CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1154)
+/** GMAC_CH1_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define GMAC_CH1_CURRBUFAPTR    0xFFFFFFFFU
+#define GMAC_CH1_CURRBUFAPTR_M  (GMAC_CH1_CURRBUFAPTR_V << GMAC_CH1_CURRBUFAPTR_S)
+#define GMAC_CH1_CURRBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CH1_CURRBUFAPTR_S  0
+
+/** GMAC_REGISTER88_CHANNEL1CBSCONTROLREGISTER_REG register
+ *  Controls the Channel 1 credit shaping operation on the transmit path
+ */
+#define GMAC_REGISTER88_CHANNEL1CBSCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x1160)
+/** GMAC_CH1_CBSD : R/W; bitpos: [0]; default: 0;
+ *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+ *  algorithm for Channel 1 traffic and makes the traffic management algorithm to
+ *  strict priority for Channel 1 over Channel 0 When reset, the creditbased shaper
+ *  algorithm schedules the traffic in Channel 1 for transmission
+ */
+#define GMAC_CH1_CBSD    (BIT(0))
+#define GMAC_CH1_CBSD_M  (GMAC_CH1_CBSD_V << GMAC_CH1_CBSD_S)
+#define GMAC_CH1_CBSD_V  0x00000001U
+#define GMAC_CH1_CBSD_S  0
+/** GMAC_CH1_CC : R/W; bitpos: [1]; default: 0;
+ *  Credit Control When reset, the accumulated credit parameter in the creditbased
+ *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+ *  transmit in Channel 1 When there is no frame waiting in Channel 1 and other channel
+ *  is transmitting, no credit is accumulated When set, the accumulated credit
+ *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+ *  is positive credit and no frame to transmit in Channel 1 The credit accumulates
+ *  even when there is no frame waiting in Channel 1 and another channel is transmitting
+ */
+#define GMAC_CH1_CC    (BIT(1))
+#define GMAC_CH1_CC_M  (GMAC_CH1_CC_V << GMAC_CH1_CC_S)
+#define GMAC_CH1_CC_V  0x00000001U
+#define GMAC_CH1_CC_S  1
+/** GMAC_CH1_SLC : R/W; bitpos: [6:4]; default: 0;
+ *  Slot Count The software can program the number of slots _of duration 125 microsec_
+ *  over which the average transmitted bits per slot _provided in the CBS Status
+ *  register_ need to be computed for Channel 1 when the creditbased shaper algorithm
+ *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+ *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+ */
+#define GMAC_CH1_SLC    0x00000007U
+#define GMAC_CH1_SLC_M  (GMAC_CH1_SLC_V << GMAC_CH1_SLC_S)
+#define GMAC_CH1_SLC_V  0x00000007U
+#define GMAC_CH1_SLC_S  4
+/** GMAC_CH1_ABPSSIE : R/W; bitpos: [17]; default: 0;
+ *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+ *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+ *  updated _Bit 17 _ABSU_ in Register 89_ for Channel 1 When this bit is cleared,
+ *  interrupt is not asserted for such an event
+ */
+#define GMAC_CH1_ABPSSIE    (BIT(17))
+#define GMAC_CH1_ABPSSIE_M  (GMAC_CH1_ABPSSIE_V << GMAC_CH1_ABPSSIE_S)
+#define GMAC_CH1_ABPSSIE_V  0x00000001U
+#define GMAC_CH1_ABPSSIE_S  17
+
+/** GMAC_REGISTER89_CHANNEL1CBSSTATUSREGISTER_REG register
+ *  Provides the average traffic transmitted in Channel 1
+ */
+#define GMAC_REGISTER89_CHANNEL1CBSSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1164)
+/** GMAC_CH1_ABS : RO; bitpos: [16:0]; default: 0;
+ *  Average Bits per Slot This field contains the average transmitted bits per slot
+ *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+ *  Register_ for Channel 1 traffic The maximum value is 0x30D4 for 100 Mbps and
+ *  0x1E848 for 1000 Mbps
+ */
+#define GMAC_CH1_ABS    0x0001FFFFU
+#define GMAC_CH1_ABS_M  (GMAC_CH1_ABS_V << GMAC_CH1_ABS_S)
+#define GMAC_CH1_ABS_V  0x0001FFFFU
+#define GMAC_CH1_ABS_S  0
+/** GMAC_CH1_ABSU : RO; bitpos: [17]; default: 0;
+ *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+ *  This bit is cleared when the application reads the ABS value
+ */
+#define GMAC_CH1_ABSU    (BIT(17))
+#define GMAC_CH1_ABSU_M  (GMAC_CH1_ABSU_V << GMAC_CH1_ABSU_S)
+#define GMAC_CH1_ABSU_V  0x00000001U
+#define GMAC_CH1_ABSU_S  17
+
+/** GMAC_REGISTER90_CHANNEL1IDLESLOPECREDITREGISTER_REG register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+#define GMAC_REGISTER90_CHANNEL1IDLESLOPECREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1168)
+/** GMAC_CH1_ISC : R/W; bitpos: [13:0]; default: 0;
+ *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+ *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is increasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+ */
+#define GMAC_CH1_ISC    0x00003FFFU
+#define GMAC_CH1_ISC_M  (GMAC_CH1_ISC_V << GMAC_CH1_ISC_S)
+#define GMAC_CH1_ISC_V  0x00003FFFU
+#define GMAC_CH1_ISC_S  0
+
+/** GMAC_REGISTER91_CHANNEL1SENDSLOPECREDITREGISTER_REG register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+#define GMAC_REGISTER91_CHANNEL1SENDSLOPECREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x116c)
+/** GMAC_CH1_SSC : R/W; bitpos: [13:0]; default: 0;
+ *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+ *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is decreasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+ *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+ *  subtracts it from the accumulated credit when Channel 1 is selected for transmission
+ */
+#define GMAC_CH1_SSC    0x00003FFFU
+#define GMAC_CH1_SSC_M  (GMAC_CH1_SSC_V << GMAC_CH1_SSC_S)
+#define GMAC_CH1_SSC_V  0x00003FFFU
+#define GMAC_CH1_SSC_S  0
+
+/** GMAC_REGISTER92_CHANNEL1HICREDITREGISTER_REG register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+#define GMAC_REGISTER92_CHANNEL1HICREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1170)
+/** GMAC_CH1_HC : R/W; bitpos: [28:0]; default: 0;
+ *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+ *  algorithm for Channel 1 This is the maximum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000
+ */
+#define GMAC_CH1_HC    0x1FFFFFFFU
+#define GMAC_CH1_HC_M  (GMAC_CH1_HC_V << GMAC_CH1_HC_S)
+#define GMAC_CH1_HC_V  0x1FFFFFFFU
+#define GMAC_CH1_HC_S  0
+
+/** GMAC_REGISTER93_CHANNEL1LOCREDITREGISTER_REG register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+#define GMAC_REGISTER93_CHANNEL1LOCREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1174)
+/** GMAC_CH1_LC : R/W; bitpos: [28:0]; default: 536870911;
+ *  loCredit This field contains the loCredit value required for the creditbased shaper
+ *  algorithm for Channel 1 This is the minimum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+ *  0xF800_0000
+ */
+#define GMAC_CH1_LC    0x1FFFFFFFU
+#define GMAC_CH1_LC_M  (GMAC_CH1_LC_V << GMAC_CH1_LC_S)
+#define GMAC_CH1_LC_V  0x1FFFFFFFU
+#define GMAC_CH1_LC_S  0
+
+/** GMAC_REGISTER128_CHANNEL2BUSMODEREGISTER_REG register
+ *  Controls the Host Interface mode for Channel 2
+ */
+#define GMAC_REGISTER128_CHANNEL2BUSMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1200)
+/** GMAC_CH2_SWR : R/W; bitpos: [0]; default: 1;
+ *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+ *  all internal registers of the MAC It is cleared automatically after the reset
+ *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+ *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+ *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+ *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+ *  the Software reset function The reset operation is completed only when all resets
+ *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+ *  inputs clocks _applicable for the selected PHY interface_ are present for the
+ *  software reset completion The time to complete the software reset operation depends
+ *  on the frequency of the slowest active clock
+ */
+#define GMAC_CH2_SWR    (BIT(0))
+#define GMAC_CH2_SWR_M  (GMAC_CH2_SWR_V << GMAC_CH2_SWR_S)
+#define GMAC_CH2_SWR_V  0x00000001U
+#define GMAC_CH2_SWR_S  0
+/** GMAC_CH2_DA : R/W; bitpos: [1]; default: 0;
+ *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+ *  transmit and receive paths of Channel 2 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+ *  The priority between the paths is according to the priority specified in Bits
+ *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+ *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+ *  receive path has priority over the transmit path In the GMACAXI configuration,
+ *  these bits are reserved and are readonly _RO_ For more information about the
+ *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+ *  Arbiter Functions” on page 167
+ */
+#define GMAC_CH2_DA    (BIT(1))
+#define GMAC_CH2_DA_M  (GMAC_CH2_DA_V << GMAC_CH2_DA_S)
+#define GMAC_CH2_DA_V  0x00000001U
+#define GMAC_CH2_DA_S  1
+/** GMAC_CH2_DSL : R/W; bitpos: [6:2]; default: 0;
+ *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+ *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+ *  descriptors The address skipping starts from the end of current descriptor to the
+ *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+ *  is taken as contiguous by the DMA in Ring mode
+ */
+#define GMAC_CH2_DSL    0x0000001FU
+#define GMAC_CH2_DSL_M  (GMAC_CH2_DSL_V << GMAC_CH2_DSL_S)
+#define GMAC_CH2_DSL_V  0x0000001FU
+#define GMAC_CH2_DSL_S  2
+/** GMAC_CH2_ATDS : R/W; bitpos: [7]; default: 0;
+ *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+ *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+ *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+ *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+ *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+ *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+ *  to save 4 bytes of memory This bit is present only when you select the Alternate
+ *  Descriptor feature and any one of the following features during core configuration:
+ *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+ *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+ *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+ *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+ *  for both normal and enhanced descriptors In version 350a, descriptor size is
+ *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+ *  Offload Engine _Type 2_ features
+ */
+#define GMAC_CH2_ATDS    (BIT(7))
+#define GMAC_CH2_ATDS_M  (GMAC_CH2_ATDS_V << GMAC_CH2_ATDS_S)
+#define GMAC_CH2_ATDS_V  0x00000001U
+#define GMAC_CH2_ATDS_S  7
+/** GMAC_CH2_PBL : R/W; bitpos: [13:8]; default: 1;
+ *  Programmable Burst Length These bits indicate the maximum number of beats to be
+ *  transferred in one DMA transaction This is the maximum value that is used in a
+ *  single block Read or Write The DMA always attempts to burst as specified in PBL
+ *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+ *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+ *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+ *  transactions If the number of beats to be transferred is more than 32, then perform
+ *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+ *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+ *  to 8 The PBL values have the following limitation: The maximum number of possible
+ *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+ *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+ *  supported is half the depth of the FIFO, except when specified For different data
+ *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+ *  Table 66 on page 382
+ */
+#define GMAC_CH2_PBL    0x0000003FU
+#define GMAC_CH2_PBL_M  (GMAC_CH2_PBL_V << GMAC_CH2_PBL_S)
+#define GMAC_CH2_PBL_V  0x0000003FU
+#define GMAC_CH2_PBL_S  8
+/** GMAC_CH2_PR : R/W; bitpos: [15:14]; default: 0;
+ *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+ *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+ *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+ *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+ *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+ *  these bits are reserved and readonly _RO_ For more information about the priority
+ *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+ *  Functions” on page 167
+ */
+#define GMAC_CH2_PR    0x00000003U
+#define GMAC_CH2_PR_M  (GMAC_CH2_PR_V << GMAC_CH2_PR_S)
+#define GMAC_CH2_PR_V  0x00000003U
+#define GMAC_CH2_PR_S  14
+/** GMAC_CH2_FB : R/W; bitpos: [16]; default: 0;
+ *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+ *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+ *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+ *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+ *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+ */
+#define GMAC_CH2_FB    (BIT(16))
+#define GMAC_CH2_FB_M  (GMAC_CH2_FB_V << GMAC_CH2_FB_S)
+#define GMAC_CH2_FB_V  0x00000001U
+#define GMAC_CH2_FB_S  16
+/** GMAC_CH2_RPBL : R/W; bitpos: [22:17]; default: 1;
+ *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+ *  one Rx DMA transaction This is the maximum value that is used in a single block
+ *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+ *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+ *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+ *  valid and applicable only when USP is set high
+ */
+#define GMAC_CH2_RPBL    0x0000003FU
+#define GMAC_CH2_RPBL_M  (GMAC_CH2_RPBL_V << GMAC_CH2_RPBL_S)
+#define GMAC_CH2_RPBL_V  0x0000003FU
+#define GMAC_CH2_RPBL_S  17
+/** GMAC_CH2_USP : R/W; bitpos: [23]; default: 0;
+ *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+ *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+ *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+ *  applicable for both DMA engines
+ */
+#define GMAC_CH2_USP    (BIT(23))
+#define GMAC_CH2_USP_M  (GMAC_CH2_USP_V << GMAC_CH2_USP_S)
+#define GMAC_CH2_USP_V  0x00000001U
+#define GMAC_CH2_USP_S  23
+/** GMAC_CH2_PBLX8 : R/W; bitpos: [24]; default: 0;
+ *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+ *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+ *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+ *  not backward compatible Before release 350a, this bit was 4xPBL
+ */
+#define GMAC_CH2_PBLX8    (BIT(24))
+#define GMAC_CH2_PBLX8_M  (GMAC_CH2_PBLX8_V << GMAC_CH2_PBLX8_S)
+#define GMAC_CH2_PBLX8_V  0x00000001U
+#define GMAC_CH2_PBLX8_S  24
+/** GMAC_CH2_AAL : R/W; bitpos: [25]; default: 0;
+ *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+ *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+ *  the FB bit is equal to 0, the first burst _accessing the start address of data
+ *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+ *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+ *  default value 0_ in all other configurations
+ */
+#define GMAC_CH2_AAL    (BIT(25))
+#define GMAC_CH2_AAL_M  (GMAC_CH2_AAL_V << GMAC_CH2_AAL_S)
+#define GMAC_CH2_AAL_V  0x00000001U
+#define GMAC_CH2_AAL_S  25
+/** GMAC_CH2_MB : R/W; bitpos: [26]; default: 0;
+ *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+ *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+ *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+ *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+ *  other configuration
+ */
+#define GMAC_CH2_MB    (BIT(26))
+#define GMAC_CH2_MB_M  (GMAC_CH2_MB_V << GMAC_CH2_MB_S)
+#define GMAC_CH2_MB_V  0x00000001U
+#define GMAC_CH2_MB_S  26
+/** GMAC_CH2_TXPR : R/W; bitpos: [27]; default: 0;
+ *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+ *  priority than the receive DMA during arbitration for the systemside bus In the
+ *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+ *  about the priority scheme between the transmit and receive paths, see Table 412 in
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_CH2_TXPR    (BIT(27))
+#define GMAC_CH2_TXPR_M  (GMAC_CH2_TXPR_V << GMAC_CH2_TXPR_S)
+#define GMAC_CH2_TXPR_V  0x00000001U
+#define GMAC_CH2_TXPR_S  27
+/** GMAC_CH2_PRWG : R/W; bitpos: [29:28]; default: 0;
+ *  Channel Priority Weights This field sets the priority weights for Channel 2 during
+ *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+ *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+ *  The priority weight is 4 This field is present in all DWC_gmac configurations
+ *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+ *  readonly _RO_ For more information about the priority weights of DMA channels, see
+ *  “DMA Arbiter Functions” on page 167
+ */
+#define GMAC_CH2_PRWG    0x00000003U
+#define GMAC_CH2_PRWG_M  (GMAC_CH2_PRWG_V << GMAC_CH2_PRWG_S)
+#define GMAC_CH2_PRWG_V  0x00000003U
+#define GMAC_CH2_PRWG_S  28
+/** GMAC_CH2_RIB : R/W; bitpos: [31]; default: 0;
+ *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+ *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+ *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+ *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+ *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+ *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+ *  all other configuration
+ */
+#define GMAC_CH2_RIB    (BIT(31))
+#define GMAC_CH2_RIB_M  (GMAC_CH2_RIB_V << GMAC_CH2_RIB_S)
+#define GMAC_CH2_RIB_V  0x00000001U
+#define GMAC_CH2_RIB_S  31
+
+/** GMAC_REGISTER129_CHANNEL2TRANSMITPOLLDEMANDREGISTER_REG register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+#define GMAC_REGISTER129_CHANNEL2TRANSMITPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1204)
+/** GMAC_CH2_TPD : RO; bitpos: [31:0]; default: 0;
+ *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the transmission resumes
+ */
+#define GMAC_CH2_TPD    0xFFFFFFFFU
+#define GMAC_CH2_TPD_M  (GMAC_CH2_TPD_V << GMAC_CH2_TPD_S)
+#define GMAC_CH2_TPD_V  0xFFFFFFFFU
+#define GMAC_CH2_TPD_S  0
+
+/** GMAC_REGISTER130_CHANNEL2RECEIVEPOLLDEMANDREGISTER_REG register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+#define GMAC_REGISTER130_CHANNEL2RECEIVEPOLLDEMANDREGISTER_REG (DR_REG_GMAC_BASE + 0x1208)
+/** GMAC_CH2_RPD : RO; bitpos: [31:0]; default: 0;
+ *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+ *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+ *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+ *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+ *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+ *  active state
+ */
+#define GMAC_CH2_RPD    0xFFFFFFFFU
+#define GMAC_CH2_RPD_M  (GMAC_CH2_RPD_V << GMAC_CH2_RPD_S)
+#define GMAC_CH2_RPD_V  0xFFFFFFFFU
+#define GMAC_CH2_RPD_S  0
+
+/** GMAC_REGISTER131_CHANNEL2RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+#define GMAC_REGISTER131_CHANNEL2RECEIVEDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x120c)
+/** GMAC_CH2_RDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Receive List This field contains the base address of the first descriptor
+ *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+ *  these LSB bits are readonly _RO_
+ */
+#define GMAC_CH2_RDESLA    0xFFFFFFFFU
+#define GMAC_CH2_RDESLA_M  (GMAC_CH2_RDESLA_V << GMAC_CH2_RDESLA_S)
+#define GMAC_CH2_RDESLA_V  0xFFFFFFFFU
+#define GMAC_CH2_RDESLA_S  0
+
+/** GMAC_REGISTER132_CHANNEL2TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG register
+ *  Points the DMA to the start of the Transmit Descriptor List
+ */
+#define GMAC_REGISTER132_CHANNEL2TRANSMITDESCRIPTORLISTADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1210)
+/** GMAC_CH2_TDESLA : R/W; bitpos: [31:0]; default: 0;
+ *  Start of Transmit List This field contains the base address of the first descriptor
+ *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+ *  128bit bus width are ignored and are internally taken as allzero by the DMA
+ *  Therefore, these LSB bits are readonly _RO_
+ */
+#define GMAC_CH2_TDESLA    0xFFFFFFFFU
+#define GMAC_CH2_TDESLA_M  (GMAC_CH2_TDESLA_V << GMAC_CH2_TDESLA_S)
+#define GMAC_CH2_TDESLA_V  0xFFFFFFFFU
+#define GMAC_CH2_TDESLA_S  0
+
+/** GMAC_REGISTER133_CHANNEL2STATUSREGISTER_REG register
+ *  The software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits [29:26] are reserved for
+ *  the Channel 2 Status Register
+ */
+#define GMAC_REGISTER133_CHANNEL2STATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1214)
+/** GMAC_CH2_TI : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+ *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+ *  status information is updated in the descriptor
+ */
+#define GMAC_CH2_TI    (BIT(0))
+#define GMAC_CH2_TI_M  (GMAC_CH2_TI_V << GMAC_CH2_TI_S)
+#define GMAC_CH2_TI_V  0x00000001U
+#define GMAC_CH2_TI_S  0
+/** GMAC_CH2_TPS : R/W; bitpos: [1]; default: 0;
+ *  Transmit Process Stopped This bit is set when the transmission is stopped
+ */
+#define GMAC_CH2_TPS    (BIT(1))
+#define GMAC_CH2_TPS_M  (GMAC_CH2_TPS_V << GMAC_CH2_TPS_S)
+#define GMAC_CH2_TPS_V  0x00000001U
+#define GMAC_CH2_TPS_S  1
+/** GMAC_CH2_TU : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+ *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+ *  processing Transmit descriptors, the host should change the ownership of the
+ *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+ */
+#define GMAC_CH2_TU    (BIT(2))
+#define GMAC_CH2_TU_M  (GMAC_CH2_TU_V << GMAC_CH2_TU_S)
+#define GMAC_CH2_TU_V  0x00000001U
+#define GMAC_CH2_TU_S  2
+/** GMAC_CH2_TJT : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+ *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+ *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+ *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+ *  to assert
+ */
+#define GMAC_CH2_TJT    (BIT(3))
+#define GMAC_CH2_TJT_M  (GMAC_CH2_TJT_V << GMAC_CH2_TJT_S)
+#define GMAC_CH2_TJT_V  0x00000001U
+#define GMAC_CH2_TJT_S  3
+/** GMAC_CH2_OVF : R/W; bitpos: [4]; default: 0;
+ *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+ *  frame reception If the partial frame is transferred to the application, the
+ *  overflow status is set in RDES0[11]
+ */
+#define GMAC_CH2_OVF    (BIT(4))
+#define GMAC_CH2_OVF_M  (GMAC_CH2_OVF_V << GMAC_CH2_OVF_S)
+#define GMAC_CH2_OVF_V  0x00000001U
+#define GMAC_CH2_OVF_S  4
+/** GMAC_CH2_UNF : R/W; bitpos: [5]; default: 0;
+ *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+ *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+ *  is set
+ */
+#define GMAC_CH2_UNF    (BIT(5))
+#define GMAC_CH2_UNF_M  (GMAC_CH2_UNF_V << GMAC_CH2_UNF_S)
+#define GMAC_CH2_UNF_V  0x00000001U
+#define GMAC_CH2_UNF_S  5
+/** GMAC_CH2_RI : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt This bit indicates that the frame reception is complete When
+ *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+ *  reset in the last Descriptor, and the specific frame status information is updated
+ *  in the descriptor The reception remains in the Running state
+ */
+#define GMAC_CH2_RI    (BIT(6))
+#define GMAC_CH2_RI_M  (GMAC_CH2_RI_V << GMAC_CH2_RI_S)
+#define GMAC_CH2_RI_V  0x00000001U
+#define GMAC_CH2_RI_S  6
+/** GMAC_CH2_RU : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+ *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+ *  suspended To resume processing Receive descriptors, the host should change the
+ *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+ *  Poll Demand is issued, the Receive Process resumes when the next recognized
+ *  incoming frame is received This bit is set only when the previous Receive
+ *  Descriptor is owned by the DMA
+ */
+#define GMAC_CH2_RU    (BIT(7))
+#define GMAC_CH2_RU_M  (GMAC_CH2_RU_V << GMAC_CH2_RU_S)
+#define GMAC_CH2_RU_V  0x00000001U
+#define GMAC_CH2_RU_S  7
+/** GMAC_CH2_RPS : R/W; bitpos: [8]; default: 0;
+ *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+ *  Stopped state
+ */
+#define GMAC_CH2_RPS    (BIT(8))
+#define GMAC_CH2_RPS_M  (GMAC_CH2_RPS_V << GMAC_CH2_RPS_S)
+#define GMAC_CH2_RPS_V  0x00000001U
+#define GMAC_CH2_RPS_S  8
+/** GMAC_CH2_RWT : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+ *  Timer expired while receiving the current frame and the current frame is truncated
+ *  after the watchdog timeout
+ */
+#define GMAC_CH2_RWT    (BIT(9))
+#define GMAC_CH2_RWT_M  (GMAC_CH2_RWT_V << GMAC_CH2_RWT_S)
+#define GMAC_CH2_RWT_V  0x00000001U
+#define GMAC_CH2_RWT_S  9
+/** GMAC_CH2_ETI : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+ *  fully transferred to the MTL Transmit FIFO
+ */
+#define GMAC_CH2_ETI    (BIT(10))
+#define GMAC_CH2_ETI_M  (GMAC_CH2_ETI_V << GMAC_CH2_ETI_S)
+#define GMAC_CH2_ETI_V  0x00000001U
+#define GMAC_CH2_ETI_S  10
+/** GMAC_CH2_FBI : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+ *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+ *  disables all of its bus accesses 12:11		Reserved	00	RO
+ */
+#define GMAC_CH2_FBI    (BIT(13))
+#define GMAC_CH2_FBI_M  (GMAC_CH2_FBI_V << GMAC_CH2_FBI_S)
+#define GMAC_CH2_FBI_V  0x00000001U
+#define GMAC_CH2_FBI_S  13
+/** GMAC_CH2_ERI : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+ *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+ *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+ */
+#define GMAC_CH2_ERI    (BIT(14))
+#define GMAC_CH2_ERI_M  (GMAC_CH2_ERI_V << GMAC_CH2_ERI_S)
+#define GMAC_CH2_ERI_V  0x00000001U
+#define GMAC_CH2_ERI_S  14
+/** GMAC_CH2_AIS : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+ *  of the following when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+ *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+ *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+ *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+ *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+ *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+ *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+ */
+#define GMAC_CH2_AIS    (BIT(15))
+#define GMAC_CH2_AIS_M  (GMAC_CH2_AIS_V << GMAC_CH2_AIS_S)
+#define GMAC_CH2_AIS_V  0x00000001U
+#define GMAC_CH2_AIS_S  15
+/** GMAC_CH2_NIS : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+ *  the following bits when the corresponding interrupt bits are enabled in Register 7
+ *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+ *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+ *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+ *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+ *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+ *  causes NIS to be set, is cleared
+ */
+#define GMAC_CH2_NIS    (BIT(16))
+#define GMAC_CH2_NIS_M  (GMAC_CH2_NIS_V << GMAC_CH2_NIS_S)
+#define GMAC_CH2_NIS_V  0x00000001U
+#define GMAC_CH2_NIS_S  16
+/** GMAC_CH2_RS : RO; bitpos: [19:17]; default: 0;
+ *  Receive Process State This field indicates the Receive DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+ *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+ *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+ *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+ *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+ *  receive buffer to host memory
+ */
+#define GMAC_CH2_RS    0x00000007U
+#define GMAC_CH2_RS_M  (GMAC_CH2_RS_V << GMAC_CH2_RS_S)
+#define GMAC_CH2_RS_V  0x00000007U
+#define GMAC_CH2_RS_S  17
+/** GMAC_CH2_TS : RO; bitpos: [22:20]; default: 0;
+ *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+ *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+ *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+ *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+ *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+ *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+ *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+ */
+#define GMAC_CH2_TS    0x00000007U
+#define GMAC_CH2_TS_M  (GMAC_CH2_TS_V << GMAC_CH2_TS_S)
+#define GMAC_CH2_TS_V  0x00000007U
+#define GMAC_CH2_TS_S  20
+/** GMAC_CH2_EB : RO; bitpos: [25:23]; default: 0;
+ *  Error Bits This field indicates the type of error that caused a Bus Error, for
+ *  example, error response on the AHB or AXI interface This field is valid only when
+ *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+ *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+ *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+ *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+ *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+ */
+#define GMAC_CH2_EB    0x00000007U
+#define GMAC_CH2_EB_M  (GMAC_CH2_EB_V << GMAC_CH2_EB_S)
+#define GMAC_CH2_EB_V  0x00000007U
+#define GMAC_CH2_EB_S  23
+/** GMAC_CH2_GLI : RO; bitpos: [26]; default: 0;
+ *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+ *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+ *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+ *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+ *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+ *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+ *  Register_ and then to clear the source of interrupt _which also clears the GLI
+ *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+ *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+ *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+ *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+ *  subsystem _sbd_intr_o_ is high when this bit is high
+ */
+#define GMAC_CH2_GLI    (BIT(26))
+#define GMAC_CH2_GLI_M  (GMAC_CH2_GLI_V << GMAC_CH2_GLI_S)
+#define GMAC_CH2_GLI_V  0x00000001U
+#define GMAC_CH2_GLI_S  26
+/** GMAC_CH2_GMI : RO; bitpos: [27]; default: 0;
+ *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+ *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+ *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+ *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+ *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+ *  are enabled Otherwise, this bit is reserved
+ */
+#define GMAC_CH2_GMI    (BIT(27))
+#define GMAC_CH2_GMI_M  (GMAC_CH2_GMI_V << GMAC_CH2_GMI_S)
+#define GMAC_CH2_GMI_V  0x00000001U
+#define GMAC_CH2_GMI_S  27
+/** GMAC_CH2_GPI : RO; bitpos: [28]; default: 0;
+ *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+ *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+ *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+ *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+ *  high This bit is applicable only when the Power Management feature is enabled
+ *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+ *  generated in different clock domains
+ */
+#define GMAC_CH2_GPI    (BIT(28))
+#define GMAC_CH2_GPI_M  (GMAC_CH2_GPI_V << GMAC_CH2_GPI_S)
+#define GMAC_CH2_GPI_V  0x00000001U
+#define GMAC_CH2_GPI_S  28
+/** GMAC_CH2_TTI : RO; bitpos: [29]; default: 0;
+ *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+ *  Generator block of the DWC_gmac The software must read the corresponding registers
+ *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+ *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+ *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+ *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+ */
+#define GMAC_CH2_TTI    (BIT(29))
+#define GMAC_CH2_TTI_M  (GMAC_CH2_TTI_V << GMAC_CH2_TTI_S)
+#define GMAC_CH2_TTI_V  0x00000001U
+#define GMAC_CH2_TTI_S  29
+/** GMAC_CH2_GLPII_GTMSI : RO; bitpos: [30]; default: 0;
+ *  GTMSI: GMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+ *  interrupt event in the traffic manager and scheduler logic of DWC_gmac To reset
+ *  this bit, the software must read the corresponding registers _Channel Status
+ *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+ *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+ *  enabled and corresponding additional transmit channels are present Otherwise, this
+ *  bit is reserved When this bit is high, the interrupt signal from the MAC
+ *  _sbd_intr_o_ is high
+ */
+#define GMAC_CH2_GLPII_GTMSI    (BIT(30))
+#define GMAC_CH2_GLPII_GTMSI_M  (GMAC_CH2_GLPII_GTMSI_V << GMAC_CH2_GLPII_GTMSI_S)
+#define GMAC_CH2_GLPII_GTMSI_V  0x00000001U
+#define GMAC_CH2_GLPII_GTMSI_S  30
+
+/** GMAC_REGISTER134_CHANNEL2OPERATIONMODEREGISTER_REG register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+#define GMAC_REGISTER134_CHANNEL2OPERATIONMODEREGISTER_REG (DR_REG_GMAC_BASE + 0x1218)
+/** GMAC_CH2_SR : R/W; bitpos: [1]; default: 0;
+ *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+ *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+ *  processes the incoming frames The descriptor acquisition is attempted from the
+ *  current position in the list, which is the address set by the Register 3 _Receive
+ *  Descriptor List Address Register_ or the position retained when the Receive process
+ *  was previously stopped If the DMA does not own the descriptor, reception is
+ *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+ *  set The Start Receive command is effective only when the reception has stopped If
+ *  the command is issued before setting Register 3 _Receive Descriptor List Address
+ *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+ *  operation is stopped after the transfer of the current frame The next descriptor
+ *  position in the Receive list is saved and becomes the current position after the
+ *  Receive process is restarted The Stop Receive command is effective only when the
+ *  Receive process is in either the Running _waiting for receive packet_ or in the
+ *  Suspended state Note: For information about how to pause the transmission, see
+ *  “Stopping and Starting Transmission” on page 715
+ */
+#define GMAC_CH2_SR    (BIT(1))
+#define GMAC_CH2_SR_M  (GMAC_CH2_SR_V << GMAC_CH2_SR_S)
+#define GMAC_CH2_SR_V  0x00000001U
+#define GMAC_CH2_SR_S  1
+/** GMAC_CH2_OSF : R/W; bitpos: [2]; default: 0;
+ *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+ *  second frame of the Transmit data even before the status for the first frame is
+ *  obtained
+ */
+#define GMAC_CH2_OSF    (BIT(2))
+#define GMAC_CH2_OSF_M  (GMAC_CH2_OSF_V << GMAC_CH2_OSF_S)
+#define GMAC_CH2_OSF_V  0x00000001U
+#define GMAC_CH2_OSF_S  2
+/** GMAC_CH2_RTC : R/W; bitpos: [4:3]; default: 0;
+ *  Receive Threshold Control These two bits control the threshold level of the MTL
+ *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+ *  Receive FIFO is larger than the threshold In addition, full frames with length less
+ *  than the threshold are automatically transferred The value of 11 is not applicable
+ *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+ *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+ *  11: 128
+ */
+#define GMAC_CH2_RTC    0x00000003U
+#define GMAC_CH2_RTC_M  (GMAC_CH2_RTC_V << GMAC_CH2_RTC_S)
+#define GMAC_CH2_RTC_V  0x00000003U
+#define GMAC_CH2_RTC_S  3
+/** GMAC_CH2_DGF : R/W; bitpos: [5]; default: 0;
+ *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+ *  that is, frames that are larger than the computed giant frame limit When reset, the
+ *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+ *  the following configurations in which the giant frame status is not provided in Rx
+ *  status and giant frames are not dropped by default: Configurations in which IP
+ *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+ *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+ *  Configurations in which the Advanced Timestamp feature is selected In all other
+ *  configurations, this bit is not used _reserved and always reset_
+ */
+#define GMAC_CH2_DGF    (BIT(5))
+#define GMAC_CH2_DGF_M  (GMAC_CH2_DGF_V << GMAC_CH2_DGF_S)
+#define GMAC_CH2_DGF_V  0x00000001U
+#define GMAC_CH2_DGF_S  5
+/** GMAC_CH2_FUF : R/W; bitpos: [6]; default: 0;
+ *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+ *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+ *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+ *  frame is already transferred because of the lower value of Receive Threshold, for
+ *  example, RTC = 01
+ */
+#define GMAC_CH2_FUF    (BIT(6))
+#define GMAC_CH2_FUF_M  (GMAC_CH2_FUF_V << GMAC_CH2_FUF_S)
+#define GMAC_CH2_FUF_V  0x00000001U
+#define GMAC_CH2_FUF_S  6
+/** GMAC_CH2_FEF : R/W; bitpos: [7]; default: 0;
+ *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+ *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+ *  overflow_ However, if the start byte _write_ pointer of a frame is already
+ *  transferred to the read controller side _in Threshold mode_, then the frame is not
+ *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+ *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+ *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+ *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+ *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+ *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+ *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+ *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+ *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+ *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+ *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+ *  the extended status is selected The extended status is available with the following
+ *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+ *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+ *  configurations
+ */
+#define GMAC_CH2_FEF    (BIT(7))
+#define GMAC_CH2_FEF_M  (GMAC_CH2_FEF_V << GMAC_CH2_FEF_S)
+#define GMAC_CH2_FEF_V  0x00000001U
+#define GMAC_CH2_FEF_S  7
+/** GMAC_CH2_EFC : R/W; bitpos: [8]; default: 0;
+ *  Enable HW Flow Control When this bit is set, the flow control signal operation
+ *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+ *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+ *  less than 4 KB
+ */
+#define GMAC_CH2_EFC    (BIT(8))
+#define GMAC_CH2_EFC_M  (GMAC_CH2_EFC_V << GMAC_CH2_EFC_S)
+#define GMAC_CH2_EFC_V  0x00000001U
+#define GMAC_CH2_EFC_S  8
+/** GMAC_CH2_RFA : R/W; bitpos: [10:9]; default: 0;
+ *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+ *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+ *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+ *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+ *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+ *  used for more threshold levels as described in Bit 23 These bits are reserved and
+ *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+ *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+ *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+ *  flow control on FIFO empty condition
+ */
+#define GMAC_CH2_RFA    0x00000003U
+#define GMAC_CH2_RFA_M  (GMAC_CH2_RFA_V << GMAC_CH2_RFA_S)
+#define GMAC_CH2_RFA_V  0x00000003U
+#define GMAC_CH2_RFA_S  9
+/** GMAC_CH2_RFD : R/W; bitpos: [12:11]; default: 0;
+ *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+ *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+ *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+ *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+ *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+ *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+ *  used for more threshold levels as described in Bit 22 These bits are reserved and
+ *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+ *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+ *  value programmed in the “RFA_2, RFA” fields
+ */
+#define GMAC_CH2_RFD    0x00000003U
+#define GMAC_CH2_RFD_M  (GMAC_CH2_RFD_V << GMAC_CH2_RFD_S)
+#define GMAC_CH2_RFD_V  0x00000003U
+#define GMAC_CH2_RFD_S  11
+/** GMAC_CH2_ST : R/W; bitpos: [13]; default: 0;
+ *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+ *  the Running state, and the DMA checks the Transmit List at the current position for
+ *  a frame to be transmitted Descriptor acquisition is attempted either from the
+ *  current position in the list, which is the Transmit List Base Address set by
+ *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+ *  retained when transmission was stopped previously If the DMA does not own the
+ *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+ *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+ *  command is effective only when transmission is stopped If the command is issued
+ *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+ *  behavior is unpredictable When this bit is reset, the transmission process is
+ *  placed in the Stopped state after completing the transmission of the current frame
+ *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+ *  current position when transmission is restarted To change the list address, you
+ *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+ *  value when this bit is reset The new value is considered when this bit is set again
+ *  The stop transmission command is effective only when the transmission of the
+ *  current frame is complete or the transmission is in the Suspended state Note: For
+ *  information about how to pause the transmission, see “Stopping and Starting
+ *  Transmission” on page 715
+ */
+#define GMAC_CH2_ST    (BIT(13))
+#define GMAC_CH2_ST_M  (GMAC_CH2_ST_V << GMAC_CH2_ST_S)
+#define GMAC_CH2_ST_V  0x00000001U
+#define GMAC_CH2_ST_S  13
+/** GMAC_CH2_TTC : R/W; bitpos: [16:14]; default: 0;
+ *  Transmit Threshold Control These bits control the threshold level of the MTL
+ *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+ *  is larger than the threshold In addition, full frames with a length less than the
+ *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+ *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+ */
+#define GMAC_CH2_TTC    0x00000007U
+#define GMAC_CH2_TTC_M  (GMAC_CH2_TTC_V << GMAC_CH2_TTC_S)
+#define GMAC_CH2_TTC_V  0x00000007U
+#define GMAC_CH2_TTC_S  14
+/** GMAC_CH2_FTF : R/W; bitpos: [20]; default: 0;
+ *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+ *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+ *  This bit is cleared internally when the flushing operation is complete The
+ *  Operation Mode register should not be written to until this bit is cleared The data
+ *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+ *  transmission and results in underflow and runt frame transmission Note: The flush
+ *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+ *  pending Transmit Status of the transmitted frames are accepted by the host In order
+ *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+ *  be active 19:17		Reserved 	000	RO
+ */
+#define GMAC_CH2_FTF    (BIT(20))
+#define GMAC_CH2_FTF_M  (GMAC_CH2_FTF_V << GMAC_CH2_FTF_S)
+#define GMAC_CH2_FTF_V  0x00000001U
+#define GMAC_CH2_FTF_S  20
+/** GMAC_CH2_TSF : R/W; bitpos: [21]; default: 0;
+ *  Transmit Store and Forward When this bit is set, transmission starts when a full
+ *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+ *  specified in Bits [16:14] are ignored This bit should be changed only when the
+ *  transmission is stopped
+ */
+#define GMAC_CH2_TSF    (BIT(21))
+#define GMAC_CH2_TSF_M  (GMAC_CH2_TSF_V << GMAC_CH2_TSF_S)
+#define GMAC_CH2_TSF_V  0x00000001U
+#define GMAC_CH2_TSF_S  21
+/** GMAC_CH2_RFD_2 : R/W; bitpos: [22]; default: 0;
+ *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+ *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+ *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+ *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+ *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+ *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+ *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+ */
+#define GMAC_CH2_RFD_2    (BIT(22))
+#define GMAC_CH2_RFD_2_M  (GMAC_CH2_RFD_2_V << GMAC_CH2_RFD_2_S)
+#define GMAC_CH2_RFD_2_V  0x00000001U
+#define GMAC_CH2_RFD_2_S  22
+/** GMAC_CH2_RFA_2 : R/W; bitpos: [23]; default: 0;
+ *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+ *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+ *  levels for activating the flow control in both half duplex and fullduplex modes
+ *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+ *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+ *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+ *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+ *  or less deep
+ */
+#define GMAC_CH2_RFA_2    (BIT(23))
+#define GMAC_CH2_RFA_2_M  (GMAC_CH2_RFA_2_V << GMAC_CH2_RFA_2_S)
+#define GMAC_CH2_RFA_2_V  0x00000001U
+#define GMAC_CH2_RFA_2_S  23
+/** GMAC_CH2_DFF : R/W; bitpos: [24]; default: 0;
+ *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+ *  any frames because of the unavailability of receive descriptors or buffers as it
+ *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+ *  This bit is reserved _and RO_ in the GMACMTL configuration
+ */
+#define GMAC_CH2_DFF    (BIT(24))
+#define GMAC_CH2_DFF_M  (GMAC_CH2_DFF_V << GMAC_CH2_DFF_S)
+#define GMAC_CH2_DFF_V  0x00000001U
+#define GMAC_CH2_DFF_S  24
+/** GMAC_CH2_RSF : R/W; bitpos: [25]; default: 0;
+ *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+ *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+ *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+ *  threshold specified by the RTC bits
+ */
+#define GMAC_CH2_RSF    (BIT(25))
+#define GMAC_CH2_RSF_M  (GMAC_CH2_RSF_V << GMAC_CH2_RSF_S)
+#define GMAC_CH2_RSF_V  0x00000001U
+#define GMAC_CH2_RSF_S  25
+/** GMAC_CH2_DT : R/W; bitpos: [26]; default: 0;
+ *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+ *  not drop the frames which only have errors detected by the Receive Checksum Offload
+ *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+ *  frame received by the MAC but have errors only in the encapsulated payload When
+ *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+ *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+ *  value 1'b0_
+ */
+#define GMAC_CH2_DT    (BIT(26))
+#define GMAC_CH2_DT_M  (GMAC_CH2_DT_V << GMAC_CH2_DT_S)
+#define GMAC_CH2_DT_V  0x00000001U
+#define GMAC_CH2_DT_S  26
+
+/** GMAC_REGISTER135_CHANNEL2INTERRUPTENABLEREGISTER_REG register
+ *  Enables the interrupts reported by the Status Register
+ */
+#define GMAC_REGISTER135_CHANNEL2INTERRUPTENABLEREGISTER_REG (DR_REG_GMAC_BASE + 0x121c)
+/** GMAC_CH2_TIE : R/W; bitpos: [0]; default: 0;
+ *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+ *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+ *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+ *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+ *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+ */
+#define GMAC_CH2_TIE    (BIT(0))
+#define GMAC_CH2_TIE_M  (GMAC_CH2_TIE_V << GMAC_CH2_TIE_S)
+#define GMAC_CH2_TIE_V  0x00000001U
+#define GMAC_CH2_TIE_S  0
+/** GMAC_CH2_TSE : R/W; bitpos: [1]; default: 0;
+ *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+ *  Transmission Stopped Interrupt is disabled
+ */
+#define GMAC_CH2_TSE    (BIT(1))
+#define GMAC_CH2_TSE_M  (GMAC_CH2_TSE_V << GMAC_CH2_TSE_S)
+#define GMAC_CH2_TSE_V  0x00000001U
+#define GMAC_CH2_TSE_S  1
+/** GMAC_CH2_TUE : R/W; bitpos: [2]; default: 0;
+ *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+ *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_CH2_TUE    (BIT(2))
+#define GMAC_CH2_TUE_M  (GMAC_CH2_TUE_V << GMAC_CH2_TUE_S)
+#define GMAC_CH2_TUE_V  0x00000001U
+#define GMAC_CH2_TUE_S  2
+/** GMAC_CH2_TJE : R/W; bitpos: [3]; default: 0;
+ *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+ *  reset, the Transmit Jabber Timeout Interrupt is disabled
+ */
+#define GMAC_CH2_TJE    (BIT(3))
+#define GMAC_CH2_TJE_M  (GMAC_CH2_TJE_V << GMAC_CH2_TJE_S)
+#define GMAC_CH2_TJE_V  0x00000001U
+#define GMAC_CH2_TJE_S  3
+/** GMAC_CH2_OVE : R/W; bitpos: [4]; default: 0;
+ *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+ *  the Overflow Interrupt is disabled
+ */
+#define GMAC_CH2_OVE    (BIT(4))
+#define GMAC_CH2_OVE_M  (GMAC_CH2_OVE_V << GMAC_CH2_OVE_S)
+#define GMAC_CH2_OVE_V  0x00000001U
+#define GMAC_CH2_OVE_S  4
+/** GMAC_CH2_UNE : R/W; bitpos: [5]; default: 0;
+ *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+ *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+ *  reset, the Underflow Interrupt is disabled
+ */
+#define GMAC_CH2_UNE    (BIT(5))
+#define GMAC_CH2_UNE_M  (GMAC_CH2_UNE_V << GMAC_CH2_UNE_S)
+#define GMAC_CH2_UNE_V  0x00000001U
+#define GMAC_CH2_UNE_S  5
+/** GMAC_CH2_RIE : R/W; bitpos: [6]; default: 0;
+ *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+ *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+ *  Interrupt is disabled
+ */
+#define GMAC_CH2_RIE    (BIT(6))
+#define GMAC_CH2_RIE_M  (GMAC_CH2_RIE_V << GMAC_CH2_RIE_S)
+#define GMAC_CH2_RIE_V  0x00000001U
+#define GMAC_CH2_RIE_S  6
+/** GMAC_CH2_RUE : R/W; bitpos: [7]; default: 0;
+ *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+ *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+ */
+#define GMAC_CH2_RUE    (BIT(7))
+#define GMAC_CH2_RUE_M  (GMAC_CH2_RUE_V << GMAC_CH2_RUE_S)
+#define GMAC_CH2_RUE_V  0x00000001U
+#define GMAC_CH2_RUE_S  7
+/** GMAC_CH2_RSE : R/W; bitpos: [8]; default: 0;
+ *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+ *  Receive Stopped Interrupt is disabled
+ */
+#define GMAC_CH2_RSE    (BIT(8))
+#define GMAC_CH2_RSE_M  (GMAC_CH2_RSE_V << GMAC_CH2_RSE_S)
+#define GMAC_CH2_RSE_V  0x00000001U
+#define GMAC_CH2_RSE_S  8
+/** GMAC_CH2_RWE : R/W; bitpos: [9]; default: 0;
+ *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+ *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+ */
+#define GMAC_CH2_RWE    (BIT(9))
+#define GMAC_CH2_RWE_M  (GMAC_CH2_RWE_V << GMAC_CH2_RWE_S)
+#define GMAC_CH2_RWE_V  0x00000001U
+#define GMAC_CH2_RWE_S  9
+/** GMAC_CH2_ETE : R/W; bitpos: [10]; default: 0;
+ *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+ *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+ *  reset, the Early Transmit Interrupt is disabled
+ */
+#define GMAC_CH2_ETE    (BIT(10))
+#define GMAC_CH2_ETE_M  (GMAC_CH2_ETE_V << GMAC_CH2_ETE_S)
+#define GMAC_CH2_ETE_V  0x00000001U
+#define GMAC_CH2_ETE_S  10
+/** GMAC_CH2_FBE : R/W; bitpos: [13]; default: 0;
+ *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+ *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+ *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+ */
+#define GMAC_CH2_FBE    (BIT(13))
+#define GMAC_CH2_FBE_M  (GMAC_CH2_FBE_V << GMAC_CH2_FBE_S)
+#define GMAC_CH2_FBE_V  0x00000001U
+#define GMAC_CH2_FBE_S  13
+/** GMAC_CH2_ERE : R/W; bitpos: [14]; default: 0;
+ *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+ *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+ *  Early Receive Interrupt is disabled
+ */
+#define GMAC_CH2_ERE    (BIT(14))
+#define GMAC_CH2_ERE_M  (GMAC_CH2_ERE_V << GMAC_CH2_ERE_S)
+#define GMAC_CH2_ERE_V  0x00000001U
+#define GMAC_CH2_ERE_S  14
+/** GMAC_CH2_AIE : R/W; bitpos: [15]; default: 0;
+ *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+ *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+ *  bit enables the following interrupts in Register 5 _Status Register_: Register
+ *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+ *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+ *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+ *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+ *  Error
+ */
+#define GMAC_CH2_AIE    (BIT(15))
+#define GMAC_CH2_AIE_M  (GMAC_CH2_AIE_V << GMAC_CH2_AIE_S)
+#define GMAC_CH2_AIE_V  0x00000001U
+#define GMAC_CH2_AIE_S  15
+/** GMAC_CH2_NIE : R/W; bitpos: [16]; default: 0;
+ *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+ *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+ *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+ *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+ *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+ */
+#define GMAC_CH2_NIE    (BIT(16))
+#define GMAC_CH2_NIE_M  (GMAC_CH2_NIE_V << GMAC_CH2_NIE_S)
+#define GMAC_CH2_NIE_V  0x00000001U
+#define GMAC_CH2_NIE_S  16
+
+/** GMAC_REGISTER136_CHANNEL2MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+#define GMAC_REGISTER136_CHANNEL2MISSEDFRAMEANDBUFFEROVERFLOWCOUNTERREGISTER_REG (DR_REG_GMAC_BASE + 0x1220)
+/** GMAC_CH2_MISFRMCNT : R/W; bitpos: [15:0]; default: 0;
+ *  Missed Frame Counter This field indicates the number of frames missed by the
+ *  controller because of the Host Receive Buffer being unavailable This counter is
+ *  incremented each time the DMA discards an incoming frame The counter is cleared
+ *  when this register is read with mci_be_i[0] at 1’b1
+ */
+#define GMAC_CH2_MISFRMCNT    0x0000FFFFU
+#define GMAC_CH2_MISFRMCNT_M  (GMAC_CH2_MISFRMCNT_V << GMAC_CH2_MISFRMCNT_S)
+#define GMAC_CH2_MISFRMCNT_V  0x0000FFFFU
+#define GMAC_CH2_MISFRMCNT_S  0
+/** GMAC_CH2_MISCNTOVF : R/W; bitpos: [16]; default: 0;
+ *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+ *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+ *  of the Host Receive Buffer being unavailable with the missed frame counter at
+ *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+ *  this bit indicates that the rollover happened
+ */
+#define GMAC_CH2_MISCNTOVF    (BIT(16))
+#define GMAC_CH2_MISCNTOVF_M  (GMAC_CH2_MISCNTOVF_V << GMAC_CH2_MISCNTOVF_S)
+#define GMAC_CH2_MISCNTOVF_V  0x00000001U
+#define GMAC_CH2_MISCNTOVF_S  16
+/** GMAC_CH2_OVFFRMCNT : R/W; bitpos: [27:17]; default: 0;
+ *  Overflow Frame Counter This field indicates the number of frames missed by the
+ *  application This counter is incremented each time the MTL FIFO overflows The
+ *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+ */
+#define GMAC_CH2_OVFFRMCNT    0x000007FFU
+#define GMAC_CH2_OVFFRMCNT_M  (GMAC_CH2_OVFFRMCNT_V << GMAC_CH2_OVFFRMCNT_S)
+#define GMAC_CH2_OVFFRMCNT_V  0x000007FFU
+#define GMAC_CH2_OVFFRMCNT_S  17
+/** GMAC_CH2_OVFCNTOVF : R/W; bitpos: [28]; default: 0;
+ *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+ *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+ *  overflow frame counter at maximum value In such a scenario, the overflow frame
+ *  counter is reset to allzeros and this bit indicates that the rollover happened
+ */
+#define GMAC_CH2_OVFCNTOVF    (BIT(28))
+#define GMAC_CH2_OVFCNTOVF_M  (GMAC_CH2_OVFCNTOVF_V << GMAC_CH2_OVFCNTOVF_S)
+#define GMAC_CH2_OVFCNTOVF_V  0x00000001U
+#define GMAC_CH2_OVFCNTOVF_S  28
+
+/** GMAC_REGISTER137_CHANNEL2RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+#define GMAC_REGISTER137_CHANNEL2RECEIVEINTERRUPTWATCHDOGTIMERREGISTER_REG (DR_REG_GMAC_BASE + 0x1224)
+/** GMAC_CH2_RIWT : R/W; bitpos: [7:0]; default: 0;
+ *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+ *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+ *  triggered with the programmed value after the Rx DMA completes the transfer of a
+ *  frame for which the RI status bit is not set because of the setting in the
+ *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+ *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+ *  high because of automatic setting of RI as per RDES1[31] of any received frame
+ */
+#define GMAC_CH2_RIWT    0x000000FFU
+#define GMAC_CH2_RIWT_M  (GMAC_CH2_RIWT_V << GMAC_CH2_RIWT_S)
+#define GMAC_CH2_RIWT_V  0x000000FFU
+#define GMAC_CH2_RIWT_S  0
+
+/** GMAC_REGISTER146_CHANNEL2CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+#define GMAC_REGISTER146_CHANNEL2CURRENTHOSTTRANSMITDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x1248)
+/** GMAC_CH2_CURTDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Descriptor Address Pointer
+ */
+#define GMAC_CH2_CURTDESAPTR    0xFFFFFFFFU
+#define GMAC_CH2_CURTDESAPTR_M  (GMAC_CH2_CURTDESAPTR_V << GMAC_CH2_CURTDESAPTR_S)
+#define GMAC_CH2_CURTDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CH2_CURTDESAPTR_S  0
+
+/** GMAC_REGISTER147_CHANNEL2CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+#define GMAC_REGISTER147_CHANNEL2CURRENTHOSTRECEIVEDESCRIPTORREGISTER_REG (DR_REG_GMAC_BASE + 0x124c)
+/** GMAC_CH2_CURRDESAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Descriptor Address Pointer
+ */
+#define GMAC_CH2_CURRDESAPTR    0xFFFFFFFFU
+#define GMAC_CH2_CURRDESAPTR_M  (GMAC_CH2_CURRDESAPTR_V << GMAC_CH2_CURRDESAPTR_S)
+#define GMAC_CH2_CURRDESAPTR_V  0xFFFFFFFFU
+#define GMAC_CH2_CURRDESAPTR_S  0
+
+/** GMAC_REGISTER148_CHANNEL2CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+#define GMAC_REGISTER148_CHANNEL2CURRENTHOSTTRANSMITBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1250)
+/** GMAC_CH2_CURTBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Transmit Buffer Address Pointer
+ */
+#define GMAC_CH2_CURTBUFAPTR    0xFFFFFFFFU
+#define GMAC_CH2_CURTBUFAPTR_M  (GMAC_CH2_CURTBUFAPTR_V << GMAC_CH2_CURTBUFAPTR_S)
+#define GMAC_CH2_CURTBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CH2_CURTBUFAPTR_S  0
+
+/** GMAC_REGISTER149_CHANNEL2CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+#define GMAC_REGISTER149_CHANNEL2CURRENTHOSTRECEIVEBUFFERADDRESSREGISTER_REG (DR_REG_GMAC_BASE + 0x1254)
+/** GMAC_CH2_CURRBUFAPTR : RO; bitpos: [31:0]; default: 0;
+ *  Host Receive Buffer Address Pointer
+ */
+#define GMAC_CH2_CURRBUFAPTR    0xFFFFFFFFU
+#define GMAC_CH2_CURRBUFAPTR_M  (GMAC_CH2_CURRBUFAPTR_V << GMAC_CH2_CURRBUFAPTR_S)
+#define GMAC_CH2_CURRBUFAPTR_V  0xFFFFFFFFU
+#define GMAC_CH2_CURRBUFAPTR_S  0
+
+/** GMAC_REGISTER152_CHANNEL2CBSCONTROLREGISTER_REG register
+ *  Controls the Channel 2 credit shaping operation on the transmit path
+ */
+#define GMAC_REGISTER152_CHANNEL2CBSCONTROLREGISTER_REG (DR_REG_GMAC_BASE + 0x1260)
+/** GMAC_CH2_CBSD : R/W; bitpos: [0]; default: 0;
+ *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+ *  algorithm for Channel 2 traffic and makes the traffic management algorithm to
+ *  strict priority for Channel 2 over Channel 0 When reset, the creditbased shaper
+ *  algorithm schedules the traffic in Channel 2 for transmission
+ */
+#define GMAC_CH2_CBSD    (BIT(0))
+#define GMAC_CH2_CBSD_M  (GMAC_CH2_CBSD_V << GMAC_CH2_CBSD_S)
+#define GMAC_CH2_CBSD_V  0x00000001U
+#define GMAC_CH2_CBSD_S  0
+/** GMAC_CH2_CC : R/W; bitpos: [1]; default: 0;
+ *  Credit Control When reset, the accumulated credit parameter in the creditbased
+ *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+ *  transmit in Channel 2 When there is no frame waiting in Channel 2 and other channel
+ *  is transmitting, no credit is accumulated When set, the accumulated credit
+ *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+ *  is positive credit and no frame to transmit in Channel 2 The credit accumulates
+ *  even when there is no frame waiting in Channel 2 and another channel is transmitting
+ */
+#define GMAC_CH2_CC    (BIT(1))
+#define GMAC_CH2_CC_M  (GMAC_CH2_CC_V << GMAC_CH2_CC_S)
+#define GMAC_CH2_CC_V  0x00000001U
+#define GMAC_CH2_CC_S  1
+/** GMAC_CH2_SLC : R/W; bitpos: [6:4]; default: 0;
+ *  Slot Count The software can program the number of slots _of duration 125 microsec_
+ *  over which the average transmitted bits per slot _provided in the CBS Status
+ *  register_ need to be computed for Channel 2 when the creditbased shaper algorithm
+ *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+ *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+ */
+#define GMAC_CH2_SLC    0x00000007U
+#define GMAC_CH2_SLC_M  (GMAC_CH2_SLC_V << GMAC_CH2_SLC_S)
+#define GMAC_CH2_SLC_V  0x00000007U
+#define GMAC_CH2_SLC_S  4
+/** GMAC_CH2_ABPSSIE : R/W; bitpos: [17]; default: 0;
+ *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+ *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+ *  updated _Bit 17 _ABSU_ in Register 153_ for Channel 2 When this bit is cleared,
+ *  interrupt is not asserted for such an event
+ */
+#define GMAC_CH2_ABPSSIE    (BIT(17))
+#define GMAC_CH2_ABPSSIE_M  (GMAC_CH2_ABPSSIE_V << GMAC_CH2_ABPSSIE_S)
+#define GMAC_CH2_ABPSSIE_V  0x00000001U
+#define GMAC_CH2_ABPSSIE_S  17
+
+/** GMAC_REGISTER153_CHANNEL2CBSSTATUSREGISTER_REG register
+ *  Provides the average traffic transmitted in Channel 2
+ */
+#define GMAC_REGISTER153_CHANNEL2CBSSTATUSREGISTER_REG (DR_REG_GMAC_BASE + 0x1264)
+/** GMAC_CH2_ABS : RO; bitpos: [16:0]; default: 0;
+ *  Average Bits per Slot This field contains the average transmitted bits per slot
+ *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+ *  Register_ for Channel 2 traffic The maximum value is 0x30D4 for 100 Mbps and
+ *  0x1E848 for 1000 Mbps
+ */
+#define GMAC_CH2_ABS    0x0001FFFFU
+#define GMAC_CH2_ABS_M  (GMAC_CH2_ABS_V << GMAC_CH2_ABS_S)
+#define GMAC_CH2_ABS_V  0x0001FFFFU
+#define GMAC_CH2_ABS_S  0
+/** GMAC_CH2_ABSU : RO; bitpos: [17]; default: 0;
+ *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+ *  This bit is cleared when the application reads the ABS value
+ */
+#define GMAC_CH2_ABSU    (BIT(17))
+#define GMAC_CH2_ABSU_M  (GMAC_CH2_ABSU_V << GMAC_CH2_ABSU_S)
+#define GMAC_CH2_ABSU_V  0x00000001U
+#define GMAC_CH2_ABSU_S  17
+
+/** GMAC_REGISTER154_CHANNEL2IDLESLOPECREDITREGISTER_REG register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+#define GMAC_REGISTER154_CHANNEL2IDLESLOPECREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1268)
+/** GMAC_CH2_ISC : R/W; bitpos: [13:0]; default: 0;
+ *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+ *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is increasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+ */
+#define GMAC_CH2_ISC    0x00003FFFU
+#define GMAC_CH2_ISC_M  (GMAC_CH2_ISC_V << GMAC_CH2_ISC_S)
+#define GMAC_CH2_ISC_V  0x00003FFFU
+#define GMAC_CH2_ISC_S  0
+
+/** GMAC_REGISTER155_CHANNEL2SENDSLOPECREDITREGISTER_REG register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+#define GMAC_REGISTER155_CHANNEL2SENDSLOPECREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x126c)
+/** GMAC_CH2_SSC : R/W; bitpos: [13:0]; default: 0;
+ *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+ *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+ *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+ *  credit is decreasing The software should program this field with computed credit in
+ *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+ *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+ *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+ *  subtracts it from the accumulated credit when Channel 2 is selected for transmission
+ */
+#define GMAC_CH2_SSC    0x00003FFFU
+#define GMAC_CH2_SSC_M  (GMAC_CH2_SSC_V << GMAC_CH2_SSC_S)
+#define GMAC_CH2_SSC_V  0x00003FFFU
+#define GMAC_CH2_SSC_S  0
+
+/** GMAC_REGISTER156_CHANNEL2HICREDITREGISTER_REG register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+#define GMAC_REGISTER156_CHANNEL2HICREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1270)
+/** GMAC_CH2_HC : R/W; bitpos: [28:0]; default: 0;
+ *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+ *  algorithm for Channel 2 This is the maximum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000
+ */
+#define GMAC_CH2_HC    0x1FFFFFFFU
+#define GMAC_CH2_HC_M  (GMAC_CH2_HC_V << GMAC_CH2_HC_S)
+#define GMAC_CH2_HC_V  0x1FFFFFFFU
+#define GMAC_CH2_HC_S  0
+
+/** GMAC_REGISTER157_CHANNEL2LOCREDITREGISTER_REG register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+#define GMAC_REGISTER157_CHANNEL2LOCREDITREGISTER_REG (DR_REG_GMAC_BASE + 0x1274)
+/** GMAC_CH2_LC : R/W; bitpos: [28:0]; default: 536870911;
+ *  loCredit This field contains the loCredit value required for the creditbased shaper
+ *  algorithm for Channel 2 This is the minimum value that can be accumulated in the
+ *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+ *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+ *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+ *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+ *  0xF800_0000
+ */
+#define GMAC_CH2_LC    0x1FFFFFFFU
+#define GMAC_CH2_LC_M  (GMAC_CH2_LC_V << GMAC_CH2_LC_S)
+#define GMAC_CH2_LC_V  0x1FFFFFFFU
+#define GMAC_CH2_LC_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gmac_struct.h b/components/soc/esp32s31/register/soc/gmac_struct.h
new file mode 100644
index 00000000000..d3678132e10
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gmac_struct.h
@@ -0,0 +1,6258 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: gmac register */
+/** Type of register0_macconfigurationregister register
+ *  This is the operation mode register for the MAC
+ */
+typedef union {
+    struct {
+        /** prelen : R/W; bitpos: [1:0]; default: 0;
+         *  Preamble Length for Transmit frames These bits control the number of preamble bytes
+         *  that are added to the beginning of every Transmit frame The preamble reduction
+         *  occurs only when the MAC is operating in the fullduplex mode 2'b00: 7 bytes of
+         *  preamble 2'b01: 5 bytes of preamble 2'b10: 3 bytes of preamble 2'b11: Reserved
+         */
+        uint32_t prelen:2;
+        /** re : R/W; bitpos: [2]; default: 0;
+         *  Receiver Enable When this bit is set, the receiver state machine of the MAC is
+         *  enabled for receiving frames from the GMII or MII When this bit is reset, the MAC
+         *  receive state machine is disabled after the completion of the reception of the
+         *  current frame, and does not receive any further frames from the GMII or MII
+         */
+        uint32_t re:1;
+        /** ten : R/W; bitpos: [3]; default: 0;
+         *  Transmitter Enable When this bit is set, the transmit state machine of the MAC is
+         *  enabled for transmission on the GMII or MII When this bit is reset, the MAC
+         *  transmit state machine is disabled after the completion of the transmission of the
+         *  current frame, and does not transmit any further frames
+         */
+        uint32_t ten:1;
+        /** dc : R/W; bitpos: [4]; default: 0;
+         *  Deferral Check When this bit is set, the deferral check function is enabled in the
+         *  MAC The MAC issues a Frame Abort status, along with the excessive deferral error
+         *  bit set in the transmit frame status, when the transmit state machine is deferred
+         *  for more than 24,288 bit times in the 10 or 100 Mbps mode If the MAC is configured
+         *  for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps
+         *  mode, the threshold for deferral is 155,680 bits times Deferral begins when the
+         *  transmitter is ready to transmit, but it is prevented because of an active carrier
+         *  sense signal _CRS_ on GMII or MII The defer time is not cumulative For example, if
+         *  the transmitter defers for 10,000 bit times because the CRS signal is active and
+         *  then the CRS signal becomes inactive, the transmitter transmits and collision
+         *  happens Because of collision, the transmitter needs to back off and then defer
+         *  again after back off completion In such a scenario, the deferral timer is reset to
+         *  0 and it is restarted When this bit is reset, the deferral check function is
+         *  disabled and the MAC defers until the CRS signal goes inactive This bit is
+         *  applicable only in the halfduplex mode and is reserved _RO_ in the fullduplexonly
+         *  configuration
+         */
+        uint32_t dc:1;
+        /** bl : R/W; bitpos: [6:5]; default: 0;
+         *  BackOff Limit The BackOff limit determines the random integer number _r_ of slot
+         *  time delays _4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps_ for
+         *  which the MAC waits before rescheduling a transmission attempt during retries after
+         *  a collision This bit is applicable only in the halfduplex mode and is reserved _RO_
+         *  in the fullduplexonly configuration 00: k= min _n, 10_ 01: k = min _n, 8_ 10: k =
+         *  min _n, 4_ 11: k = min _n, 1_ where n = retransmission attempt The random integer r
+         *  takes the value in the range 0 ≤ r < 2k
+         */
+        uint32_t bl:2;
+        /** acs : R/W; bitpos: [7]; default: 0;
+         *  Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS
+         *  field on the incoming frames only if the value of the length field is less than
+         *  1,536 bytes All received frames with length field greater than or equal to 1,536
+         *  bytes are passed to the application without stripping the Pad or FCS field When
+         *  this bit is reset, the MAC passes all incoming frames, without modifying them, to
+         *  the Host Note: For information about how the settings of Bit 25 _CST_ and this bit
+         *  impact the frame length, see Table 632
+         */
+        uint32_t acs:1;
+        /** lud : R/W; bitpos: [8]; default: 0;
+         *  Link Up or Down This bit indicates whether the link is up or down during the
+         *  transmission of configuration in the RGMII, SGMII, or SMII interface: 0: Link Down
+         *  1: Link Up This bit is reserved _RO with default value_ and is enabled when the
+         *  RGMII, SGMII, or SMII interface is enabled during core configuration
+         */
+        uint32_t lud:1;
+        /** dr : R/W; bitpos: [9]; default: 0;
+         *  Disable Retry When this bit is set, the MAC attempts only one transmission When a
+         *  collision occurs on the GMII or MII interface, the MAC ignores the current frame
+         *  transmission and reports a Frame Abort with excessive collision error in the
+         *  transmit frame status When this bit is reset, the MAC attempts retries based on the
+         *  settings of the BL field _Bits [6:5]_ This bit is applicable only in the halfduplex
+         *  mode and is reserved _RO with default value_ in the fullduplexonly configuration
+         */
+        uint32_t dr:1;
+        /** ipc : R/W; bitpos: [10]; default: 0;
+         *  Checksum Offload When this bit is set, the MAC calculates the 16bit one’s
+         *  complement of the one’s complement sum of all received Ethernet frame payloads It
+         *  also checks whether the IPv4 Header checksum _assumed to be bytes 2526 or 2930
+         *  _VLAN tagged_ of the received Ethernet frame_ is correct for the received frame and
+         *  gives the status in the receive status word The MAC also appends the 16bit checksum
+         *  calculated for the IP header datagram payload _bytes after the IPv4 header_ and
+         *  appends it to the Ethernet frame transferred to the application _when Type 2 COE is
+         *  deselected_ When this bit is reset, this function is disabled When Type 2 COE is
+         *  selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or
+         *  IPv6 TCP, UDP, or ICMP payload checksum checking When this bit is reset, the COE
+         *  function in the receiver is disabled and the corresponding PCE and IP HCE status
+         *  bits _see Table 310 on page 138_ are always cleared If the IP Checksum Offload
+         *  feature is not enabled during core configuration, this bit is reserved _RO with
+         *  default value_
+         */
+        uint32_t ipc:1;
+        /** dm : R/W; bitpos: [11]; default: 0;
+         *  Duplex Mode When this bit is set, the MAC operates in the fullduplex mode where it
+         *  can transmit and receive simultaneously This bit is RO with default value of 1'b1
+         *  in the fullduplexonly configuration
+         */
+        uint32_t dm:1;
+        /** lm : R/W; bitpos: [12]; default: 0;
+         *  Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII
+         *  or MII The _G_MII Receive clock input _clk_rx_i_ is required for the loopback to
+         *  work properly, because the Transmit clock is not loopedback internally
+         */
+        uint32_t lm:1;
+        /** do : R/W; bitpos: [13]; default: 0;
+         *  Disable Receive Own When this bit is set, the MAC disables the reception of frames
+         *  when the phy_txen_o is asserted in the halfduplex mode When this bit is reset, the
+         *  MAC receives all packets that are given by the PHY while transmitting This bit is
+         *  not applicable if the MAC is operating in the fullduplex mode This bit is reserved
+         *  _RO with default value_ if the MAC is configured for the fullduplexonly operation
+         */
+        uint32_t do:1;
+        /** fes : R/W; bitpos: [14]; default: 0;
+         *  Speed This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII
+         *  interface: 0: 10 Mbps 1: 100 Mbps This bit is reserved _RO_ by default and is
+         *  enabled only when the parameter SPEED_SELECT = Enabled This bit generates link
+         *  speed encoding when Bit 24 _TC_ is set in the RGMII, SMII, or SGMII mode This bit
+         *  is always enabled for RGMII, SGMII, SMII, or RevMII interface In configurations
+         *  with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output
+         *  signal _mac_speed_o[0]_ to reflect the value of this bit in the mac_speed_o signal
+         *  In configurations with RMII, MII, or GMII interface, you can optionally drive this
+         *  bit as an output signal _mac_speed_o[0]_ to reflect its value in the mac_speed_o
+         *  signal
+         */
+        uint32_t fes:1;
+        /** ps : R/W; bitpos: [15]; default: 0;
+         *  Port Select This bit selects the Ethernet line speed 0: For 1000 Mbps operations 1:
+         *  For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with
+         *  FES bit, selects the exact line speed In the 10/100 Mbpsonly _always 1_ or 1000
+         *  Mbpsonly _always 0_ configurations, this bit is readonly with the appropriate value
+         *  In default 10/100/1000 Mbps configuration, this bit is R_W The mac_portselect_o or
+         *  mac_speed_o[1] signal reflects the value of this bit
+         */
+        uint32_t ps:1;
+        /** dcrs : R/W; bitpos: [16]; default: 0;
+         *  Disable Carrier Sense During Transmission When set high, this bit makes the MAC
+         *  transmitter ignore the _G_MII CRS signal during frame transmission in the
+         *  halfduplex mode This request results in no errors generated because of Loss of
+         *  Carrier or No Carrier during such transmission When this bit is low, the MAC
+         *  transmitter generates such errors because of Carrier Sense and can even abort the
+         *  transmissions This bit is reserved _and RO_ in the fullduplexonly configurations
+         */
+        uint32_t dcrs:1;
+        /** ifg : R/W; bitpos: [19:17]; default: 0;
+         *  InterFrame Gap These bits control the minimum IFG between frames during
+         *  transmission 000: 96 bit times 001: 88 bit times 010: 80 bit times  111: 40 bit
+         *  times In the halfduplex mode, the minimum IFG can be configured only for 64 bit
+         *  times _IFG = 100_ Lower values are not considered In the 1000Mbps mode, the minimum
+         *  IFG supported is 64 bit times _and above_ in the GMACCORE configuration and 80 bit
+         *  times _and above_ in other configurations When a JAM pattern is being transmitted
+         *  because of backpressure activation, the MAC does not consider the minimum IFG
+         */
+        uint32_t ifg:3;
+        /** je : R/W; bitpos: [20]; default: 0;
+         *  Jumbo Frame Enable When this bit is set, the MAC allows Jumbo frames of 9,018 bytes
+         *  _9,022 bytes for VLAN tagged frames_ without reporting a giant frame error in the
+         *  receive frame status
+         */
+        uint32_t je:1;
+        /** be : R/W; bitpos: [21]; default: 0;
+         *  Frame Burst Enable When this bit is set, the MAC allows frame bursting during
+         *  transmission in the GMII halfduplex mode This bit is reserved _and RO_ in the
+         *  10/100 Mbps only or fullduplexonly configurations
+         */
+        uint32_t be:1;
+        /** jd : R/W; bitpos: [22]; default: 0;
+         *  Jabber Disable When this bit is set, the MAC disables the jabber timer on the
+         *  transmitter The MAC can transfer frames of up to 16,383 bytes When this bit is
+         *  reset, the MAC cuts off the transmitter if the application sends out more than
+         *  2,048 bytes of data _10,240 if JE is set high_ during transmission
+         */
+        uint32_t jd:1;
+        /** wd : R/W; bitpos: [23]; default: 0;
+         *  Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the
+         *  receiver The MAC can receive frames of up to 16,383 bytes When this bit is reset,
+         *  the MAC does not allow a receive frame which more than 2,048 bytes _10,240 if JE is
+         *  set high_ or the value programmed in Register 55 _Watchdog Timeout Register_ The
+         *  MAC cuts off any bytes received after the watchdog limit number of bytes
+         */
+        uint32_t wd:1;
+        /** tc : R/W; bitpos: [24]; default: 0;
+         *  Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the
+         *  transmission of duplex mode, link speed, and link up or down information to the PHY
+         *  in the RGMII, SMII, or SGMII port When this bit is reset, no such information is
+         *  driven to the PHY This bit is reserved _and RO_ if the RGMII, SMII, or SGMII PHY
+         *  port is not selected during core configuration The details of this feature are
+         *  explained in the following sections: “Reduced Gigabit Media Independent Interface”
+         *  on page 249 “Serial Media Independent Interface” on page 245 “Serial Gigabit Media
+         *  Independent Interface” on page 257
+         */
+        uint32_t tc:1;
+        /** cst : R/W; bitpos: [25]; default: 0;
+         *  CRC Stripping for Type Frames When this bit is set, the last 4 bytes _FCS_ of all
+         *  frames of Ether type _Length/Type field greater than or equal to 1,536_ are
+         *  stripped and dropped before forwarding the frame to the application This function
+         *  is not valid when the IP Checksum Engine _Type 1_ is enabled in the MAC receiver
+         *  This function is valid when Type 2 Checksum Offload Engine is enabled Note: For
+         *  information about how the settings of Bit 7 _ACS_ and this bit impact the frame
+         *  length, see Table 632
+         */
+        uint32_t cst:1;
+        /** sfterr : R/W; bitpos: [26]; default: 0;
+         *  SMII Force Transmit Error When set, this bit indicates to the PHY to force a
+         *  transmit error in the SMII frame being transmitted This bit is reserved if the SMII
+         *  PHY port is not selected during core configuration
+         */
+        uint32_t sfterr:1;
+        /** twokpe : R/W; bitpos: [27]; default: 0;
+         *  IEEE 8023as Support for 2K Packets When set, the MAC considers all frames, with up
+         *  to 2,000 bytes length, as normal packets When Bit 20 _JE_ is not set, the MAC
+         *  considers all received frames of size more than 2K bytes as Giant frames When this
+         *  bit is reset and Bit 20 _JE_ is not set, the MAC considers all received frames of
+         *  size more than 1,518 bytes _1,522 bytes for tagged_ as Giant frames When Bit 20 is
+         *  set, setting this bit has no effect on Giant Frame status For more information
+         *  about how the setting of this bit and Bit 20 impact the Giant frame status, see
+         *  Table 631
+         */
+        uint32_t twokpe:1;
+        /** sarc : R/W; bitpos: [30:28]; default: 0;
+         *  Source Address Insertion or Replacement Control This field controls the source
+         *  address insertion or replacement for all transmitted frames Bit 30 specifies which
+         *  MAC Address register _0 or 1_ is used for source address insertion or replacement
+         *  based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and
+         *  ati_sa_ctrl_i control the SA field generation 2'b10: 	If Bit 30 is set to 0, the
+         *  MAC inserts the content of the MAC Address 0 registers _registers 16 and 17_ in the
+         *  SA field of all transmitted frames 	If Bit 30 is set to 1 and the Enable MAC
+         *  Address Register 1 option is selected during core configuration, the MAC inserts
+         *  the content of the MAC Address 1 registers _registers 18 and 19_ in the SA field of
+         *  all transmitted frames 2'b11: 	If Bit 30 is set to 0, the MAC replaces the content
+         *  of the MAC Address 0 registers _registers 16 and 17_ in the SA field of all
+         *  transmitted frames 	If Bit 30 is set to 1 and the Enable MAC Address Register 1
+         *  option is selected during core configuration, the MAC replaces the content of the
+         *  MAC Address 1 registers _registers 18 and 19_ in the SA field of all transmitted
+         *  frames Note: Changes to this field take effect only on the start of a frame If you
+         *  write this register field when a frame is being transmitted, only the subsequent
+         *  frame can use the updated value, that is, the current frame does not use the
+         *  updated value These bits are reserved and RO when the Enable SA, VLAN, and CRC
+         *  Insertion on TX feature is not selected during core configuration
+         */
+        uint32_t sarc:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register0_macconfigurationregister_reg_t;
+
+/** Type of register1_macframefilter register
+ *  Contains the frame filtering controls
+ */
+typedef union {
+    struct {
+        /** promiscuous_mode : R/W; bitpos: [0]; default: 0;
+         *  Promiscuous Mode When this bit is set, the Address Filter module passes all
+         *  incoming frames irrespective of the destination or source address The SA or DA
+         *  Filter Fails status bits of the Receive Status Word are always cleared when PR is
+         *  set
+         */
+        uint32_t promiscuous_mode:1;
+        /** huc : R/W; bitpos: [1]; default: 0;
+         *  Hash Unicast When set, the MAC performs destination address filtering of unicast
+         *  frames according to the hash table When reset, the MAC performs a perfect
+         *  destination address filtering for unicast frames, that is, it compares the DA field
+         *  with the values programmed in DA registers If Hash Filter is not selected during
+         *  core configuration, this bit is reserved _and RO_
+         */
+        uint32_t huc:1;
+        /** hmc : R/W; bitpos: [2]; default: 0;
+         *  Hash Multicast When set, the MAC performs destination address filtering of received
+         *  multicast frames according to the hash table When reset, the MAC performs a perfect
+         *  destination address filtering for multicast frames, that is, it compares the DA
+         *  field with the values programmed in DA registers If Hash Filter is not selected
+         *  during core configuration, this bit is reserved _and RO_
+         */
+        uint32_t hmc:1;
+        /** daif : R/W; bitpos: [3]; default: 0;
+         *  DA Inverse Filtering When this bit is set, the Address Check block operates in
+         *  inverse filtering mode for the DA address comparison for both unicast and multicast
+         *  frames When reset, normal filtering of frames is performed
+         */
+        uint32_t daif:1;
+        /** pm : R/W; bitpos: [4]; default: 0;
+         *  Pass All Multicast When set, this bit indicates that all received frames with a
+         *  multicast destination address _first bit in the destination address field is '1'_
+         *  are passed When reset, filtering of multicast frame depends on HMC bit
+         */
+        uint32_t pm:1;
+        /** dbf : R/W; bitpos: [5]; default: 0;
+         *  Disable Broadcast Frames When this bit is set, the AFM module blocks all incoming
+         *  broadcast frames In addition, it overrides all other filter settings When this bit
+         *  is reset, the AFM module passes all received broadcast frames
+         */
+        uint32_t dbf:1;
+        /** pcf : R/W; bitpos: [7:6]; default: 0;
+         *  Pass Control Frames These bits control the forwarding of all control frames
+         *  _including unicast and multicast Pause frames_ 00: MAC filters all control frames
+         *  from reaching the application 01: MAC forwards all control frames except Pause
+         *  frames to application even if they fail the Address filter 10: MAC forwards all
+         *  control frames to application even if they fail the Address Filter 11: MAC forwards
+         *  control frames that pass the Address Filter The following conditions should be true
+         *  for the Pause frames processing: Condition 1 : The MAC is in the fullduplex mode
+         *  and flow control is enabled by setting Bit 2 _RFE_ of Register 6 _Flow Control
+         *  Register_ to 1 Condition 2 : The destination address _DA_ of the received frame
+         *  matches the special multicast address or the MAC Address 0 when Bit 3 _UP_ of the
+         *  Register 6 _Flow Control Register_ is set Condition 3: The Type field of the
+         *  received frame is 0x8808 and the OPCODE field is 0x0001 Note: This field should be
+         *  set to 01 only when the Condition 1 is true, that is, the MAC is programmed to
+         *  operate in the fullduplex mode and the RFE bit is enabled Otherwise, the Pause
+         *  frame filtering may be inconsistent When Condition 1 is false, the Pause frames are
+         *  considered as generic control frames Therefore, to pass all control frames
+         *  _including Pause frames_ when the fullduplex mode and flow control is not enabled,
+         *  you should set the PCF field to 10 or 11 _as required by the application_
+         */
+        uint32_t pcf:2;
+        /** saif : R/W; bitpos: [8]; default: 0;
+         *  SA Inverse Filtering When this bit is set, the Address Check block operates in
+         *  inverse filtering mode for the SA address comparison The frames whose SA matches
+         *  the SA registers are marked as failing the SA Address filter When this bit is
+         *  reset, frames whose SA does not match the SA registers are marked as failing the SA
+         *  Address filter
+         */
+        uint32_t saif:1;
+        /** saf : R/W; bitpos: [9]; default: 0;
+         *  Source Address Filter Enable When this bit is set, the MAC compares the SA field of
+         *  the received frames with the values programmed in the enabled SA registers If the
+         *  comparison fails, the MAC drops the frame When this bit is reset, the MAC forwards
+         *  the received frame to the application with updated SAF bit of the Rx Status
+         *  depending on the SA address comparison Note: According to the IEEE specification,
+         *  Bit 47 of the SA is reserved and set to 0 However, in DWC_gmac, the MAC compares
+         *  all 48 bits The software driver should take this into consideration while
+         *  programming the MAC address registers for SA
+         */
+        uint32_t saf:1;
+        /** hpf : R/W; bitpos: [10]; default: 0;
+         *  Hash or Perfect Filter When this bit is set, it configures the address filter to
+         *  pass a frame if it matches either the perfect filtering or the hash filtering as
+         *  set by the HMC or HUC bits When this bit is low and the HUC or HMC bit is set, the
+         *  frame is passed only if it matches the Hash filter This bit is reserved _and RO_ if
+         *  the Hash filter is not selected during core configuration
+         */
+        uint32_t hpf:1;
+        uint32_t reserved_11:5;
+        /** vtfe : R/W; bitpos: [16]; default: 0;
+         *  VLAN Tag Filter Enable When set, this bit enables the MAC to drop VLAN tagged
+         *  frames that do not match the VLAN Tag comparison When reset, the MAC forwards all
+         *  frames irrespective of the match status of the VLAN Tag
+         */
+        uint32_t vtfe:1;
+        uint32_t reserved_17:3;
+        /** ipfe : R/W; bitpos: [20]; default: 0;
+         *  Layer 3 and Layer 4 Filter Enable When set, this bit enables the MAC to drop frames
+         *  that do not match the enabled Layer 3 and Layer 4 filters If Layer 3 or Layer 4
+         *  filters are not enabled for matching, this bit does not have any effect When reset,
+         *  the MAC forwards all frames irrespective of the match status of the Layer 3 and
+         *  Layer 4 fields If the Layer 3 and Layer 4 Filtering feature is not selected during
+         *  core configuration, this bit is reserved _RO with default value_
+         */
+        uint32_t ipfe:1;
+        /** dntu : R/W; bitpos: [21]; default: 0;
+         *  Drop nonTCP/UDP over IP Frames When set, this bit enables the MAC to drop the
+         *  nonTCP or UDP over IP frames The MAC forward only those frames that are processed
+         *  by the Layer 4 filter When reset, this bit enables the MAC to forward all nonTCP or
+         *  UDP over IP frames If the Layer 3 and Layer 4 Filtering feature is not selected
+         *  during core configuration, this bit is reserved _RO with default value_
+         */
+        uint32_t dntu:1;
+        uint32_t reserved_22:9;
+        /** ra : R/W; bitpos: [31]; default: 0;
+         *  Receive All When this bit is set, the MAC Receiver module passes all received
+         *  frames, irrespective of whether they pass the address filter or not, to the
+         *  Application The result of the SA or DA filtering is updated _pass or fail_ in the
+         *  corresponding bits in the Receive Status Word When this bit is reset, the Receiver
+         *  module passes only those frames to the Application that pass the SA or DA address
+         *  filter
+         */
+        uint32_t ra:1;
+    };
+    uint32_t val;
+} gmac_register1_macframefilter_reg_t;
+
+/** Type of register2_hashtablehighregister register
+ *  Contains the higher 32 bits of the Multicast Hash table This register is present
+ *  only when you select the 64bit Hash filter function in coreConsultant _See Table 79_
+ */
+typedef union {
+    struct {
+        /** hth : R/W; bitpos: [31:0]; default: 0;
+         *  Hash Table High This field contains the upper 32 bits of the Hash table
+         */
+        uint32_t hth:32;
+    };
+    uint32_t val;
+} gmac_register2_hashtablehighregister_reg_t;
+
+/** Type of register3_hashtablelowregister register
+ *  Contains the lower 32 bits of the Multicast Hash table This register is present
+ *  only when you select the Hash filter function in coreConsultant _See Table 79_
+ */
+typedef union {
+    struct {
+        /** htl : R/W; bitpos: [31:0]; default: 0;
+         *  Hash Table Low This field contains the lower 32 bits of the Hash table
+         */
+        uint32_t htl:32;
+    };
+    uint32_t val;
+} gmac_register3_hashtablelowregister_reg_t;
+
+/** Type of register4_gmiiaddressregister register
+ *  Controls the management cycles to an external PHY This register is present only
+ *  when you select the Station Management _MDIO_ feature in coreConsultant _See Table
+ *  726_
+ */
+typedef union {
+    struct {
+        /** gb : R/W1S; bitpos: [0]; default: 0;
+         *  GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5
+         *  During a PHY or RevMII register access, the software sets this bit to 1’b1 to
+         *  indicate that a Read or Write access is in progress Register 5 is invalid until
+         *  this bit is cleared by the MAC Therefore, Register 5 _GMII Data_ should be kept
+         *  valid until the MAC clears this bit during a PHY Write operation Similarly for a
+         *  read operation, the contents of Register 5 are not valid until this bit is cleared
+         *  The subsequent read or write operation should happen only after the previous
+         *  operation is complete Because there is no acknowledgment from the PHY to MAC after
+         *  a read or write operation is completed, there is no change in the functionality of
+         *  this bit even when the PHY is not present
+         */
+        uint32_t gb:1;
+        /** gw : R/W; bitpos: [1]; default: 0;
+         *  GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write
+         *  operation using the GMII Data register If this bit is not set, it indicates that
+         *  this is a Read operation, that is, placing the data in the GMII Data register
+         */
+        uint32_t gw:1;
+        /** cr : R/W; bitpos: [5:2]; default: 0;
+         *  CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC
+         *  clock according to the CSR clock frequency used in your design The CSR clock
+         *  corresponding to different GMAC configurations is given in Table 92 on page 564 The
+         *  suggested range of CSR clock frequency applicable for each value _when Bit[5] = 0_
+         *  ensures that the MDC clock is approximately between the frequency range 10 MHz25
+         *  MHz 0000: The CSR clock frequency is 60100 MHz and the MDC clock frequency is CSR
+         *  clock/42 0001: The CSR clock frequency is 100150 MHz and the MDC clock frequency is
+         *  CSR clock/62 0010: The CSR clock frequency is 2035 MHz and the MDC clock frequency
+         *  is CSR clock/16 0011: The CSR clock frequency is 3560 MHz and the MDC clock
+         *  frequency is CSR clock/26 0100: The CSR clock frequency is 150250 MHz and the MDC
+         *  clock frequency is CSR clock/102 0101: The CSR clock frequency is 250300 MHz and
+         *  the MDC clock is CSR clock/124 0110, 0111: Reserved When Bit 5 is set, you can
+         *  achieve higher frequency of the MDC clock than the frequency limit of 25 MHz
+         *  _specified in the IEEE Std 8023_ and program a clock divider of lower value For
+         *  example, when CSR clock is of 100 MHz frequency and you program these bits as 1010,
+         *  then the resultant MDC clock is of 125 MHz which is outside the limit of IEEE 8023
+         *  specified range Program the following values only if the interfacing chips support
+         *  faster MDC clocks 1000: CSR clock/4 1001: CSR clock/6 1010: CSR clock/8 1011: CSR
+         *  clock/10 1100: CSR clock/12 1101: CSR clock/14 1110: CSR clock/16 1111: CSR
+         *  clock/18 These bits are not used for accessing RevMII These bits are readonly if
+         *  the RevMII interface is selected as single PHY interface
+         */
+        uint32_t cr:4;
+        /** gr : R/W; bitpos: [10:6]; default: 0;
+         *  GMII Register These bits select the desired GMII register in the selected PHY
+         *  device For RevMII, these bits select the desired CSR register in the RevMII
+         *  Registers set
+         */
+        uint32_t gr:5;
+        /** pa : R/W; bitpos: [15:11]; default: 0;
+         *  Physical Layer Address This field indicates which of the 32 possible PHY devices
+         *  are being accessed For RevMII, this field gives the PHY Address of the RevMII module
+         */
+        uint32_t pa:5;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register4_gmiiaddressregister_reg_t;
+
+/** Type of register5_gmiidataregister register
+ *  Contains the data to be written to or read from the PHY register This register is
+ *  present only when you select the Station Management _MDIO_ feature in
+ *  coreConsultant _See Table 726_
+ */
+typedef union {
+    struct {
+        /** gd : R/W; bitpos: [15:0]; default: 0;
+         *  GMII Data This field contains the 16bit data value read from the PHY or RevMII
+         *  after a Management Read operation or the 16bit data value to be written to the PHY
+         *  or RevMII before a Management Write operation
+         */
+        uint32_t gd:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register5_gmiidataregister_reg_t;
+
+/** Type of register6_flowcontrolregister register
+ *  Controls the generation of control frames
+ */
+typedef union {
+    struct {
+        /** fcb_bpa : R/W1S; bitpos: [0]; default: 0;
+         *  Flow Control Busy or Backpressure Activate This bit initiates a Pause frame in the
+         *  fullduplex mode and activates the backpressure function in the halfduplex mode if
+         *  the TFE bit is set In the fullduplex mode, this bit should be read as 1'b0 before
+         *  writing to the Flow Control register To initiate a Pause frame, the Application
+         *  must set this bit to 1'b1 During a transfer of the Control Frame, this bit
+         *  continues to be set to signify that a frame transmission is in progress After the
+         *  completion of Pause frame transmission, the MAC resets this bit to 1'b0 The Flow
+         *  Control register should not be written to until this bit is cleared In the
+         *  halfduplex mode, when this bit is set _and TFE is set_, then backpressure is
+         *  asserted by the MAC During backpressure, when the MAC receives a new frame, the
+         *  transmitter starts sending a JAM pattern resulting in a collision This control
+         *  register bit is logically ORed with the mti_flowctrl_i input signal for the
+         *  backpressure function When the MAC is configured for the fullduplex mode, the BPA
+         *  is automatically disabled
+         */
+        uint32_t fcb_bpa:1;
+        /** tfe : R/W; bitpos: [1]; default: 0;
+         *  Transmit Flow Control Enable In the fullduplex mode, when this bit is set, the MAC
+         *  enables the flow control operation to transmit Pause frames When this bit is reset,
+         *  the flow control operation in the MAC is disabled, and the MAC does not transmit
+         *  any Pause frames In the halfduplex mode, when this bit is set, the MAC enables the
+         *  backpressure operation When this bit is reset, the backpressure feature is disabled
+         */
+        uint32_t tfe:1;
+        /** receive_flow_ctrl_e : R/W; bitpos: [2]; default: 0;
+         *  Receive Flow Control Enable When this bit is set, the MAC decodes the received
+         *  Pause frame and disables its transmitter for a specified _Pause_ time When this bit
+         *  is reset, the decode function of the Pause frame is disabled
+         */
+        uint32_t receive_flow_ctrl_e:1;
+        /** up : R/W; bitpos: [3]; default: 0;
+         *  Unicast Pause Frame Detect A pause frame is processed when it has the unique
+         *  multicast address specified in the IEEE Std 8023 When this bit is set, the MAC can
+         *  also detect Pause frames with unicast address of the station This unicast address
+         *  should be as specified in the MAC Address0 High Register and MAC Address0 Low
+         *  Register When this bit is reset, the MAC only detects Pause frames with unique
+         *  multicast address Note: The MAC does not process a Pause frame if the multicast
+         *  address of received frame is different from the unique multicast address
+         */
+        uint32_t up:1;
+        /** plt : R/W; bitpos: [5:4]; default: 0;
+         *  Pause Low Threshold This field configures the threshold of the Pause timer at which
+         *  the input flow control signal mti_flowctrl_i _or sbd_flowctrl_i_ is checked for
+         *  automatic retransmission of the Pause frame The threshold values should be always
+         *  less than the Pause Time configured in Bits[31:16] For example, if PT = 100H _256
+         *  slottimes_, and PLT = 01, then a second Pause frame is automatically transmitted if
+         *  the mti_flowctrl_i signal is asserted at 228 _256  28_ slot times after the first
+         *  Pause frame is transmitted The following list provides the threshold values for
+         *  different values: 00: The threshold is Pause time minus 4 slot times _PT  4 slot
+         *  times_ 01: The threshold is Pause time minus 28 slot times _PT  28 slot times_ 10:
+         *  The threshold is Pause time minus 144 slot times _PT  144 slot times_ 11: The
+         *  threshold is Pause time minus 256 slot times _PT  256 slot times_ The slot time is
+         *  defined as the time taken to transmit 512 bits _64 bytes_ on the GMII or MII
+         *  interface
+         */
+        uint32_t plt:2;
+        uint32_t reserved_6:1;
+        /** dzpq : R/W; bitpos: [7]; default: 0;
+         *  Disable ZeroQuanta Pause When this bit is set, it disables the automatic generation
+         *  of the ZeroQuanta Pause frames on the deassertion of the flowcontrol signal from
+         *  the FIFO layer _MTL or external sideband flow control signal
+         *  sbd_flowctrl_i/mti_flowctrl_i_ When this bit is reset, normal operation with
+         *  automatic ZeroQuanta Pause frame generation is enabled
+         */
+        uint32_t dzpq:1;
+        uint32_t reserved_8:8;
+        /** pt : R/W; bitpos: [31:16]; default: 0;
+         *  Pause Time This field holds the value to be used in the Pause Time field in the
+         *  transmit control frame If the Pause Time bits is configured to be
+         *  doublesynchronized to the _G_MII clock domain, then consecutive writes to this
+         *  register should be performed only after at least four clock cycles in the
+         *  destination clock domain
+         */
+        uint32_t pt:16;
+    };
+    uint32_t val;
+} gmac_register6_flowcontrolregister_reg_t;
+
+/** Type of register7_vlantagregister register
+ *  Identifies IEEE 8021Q VLAN type frames
+ */
+typedef union {
+    struct {
+        /** vl : R/W; bitpos: [15:0]; default: 0;
+         *  VLAN Tag Identifier for Receive Frames This field contains the 8021Q VLAN tag to
+         *  identify the VLAN frames and is compared to the 15th and 16th bytes of the frames
+         *  being received for VLAN frames The following list describes the bits of this field:
+         *  Bits [15:13]: User Priority Bit 12: Canonical Format Indicator _CFI_ or Drop
+         *  Eligible Indicator _DEI_ Bits[11:0]: VLAN tag’s VLAN Identifier _VID_ field When
+         *  the ETV bit is set, only the VID _Bits[11:0]_ is used for comparison If VL
+         *  _VL[11:0] if ETV is set_ is all zeros, the MAC does not check the fifteenth and
+         *  16th bytes for VLAN tag comparison, and declares all frames with a Type field value
+         *  of 0x8100 or 0x88a8 as VLAN frames
+         */
+        uint32_t vl:16;
+        /** etv : R/W; bitpos: [16]; default: 0;
+         *  Enable 12-Bit VLAN Tag Comparison
+         */
+        uint32_t etv:1;
+        /** vtim : R/W; bitpos: [17]; default: 0;
+         *  VLAN Tag Inverse Match Enable When set, this bit enables the VLAN Tag inverse
+         *  matching The frames that do not have matching VLAN Tag are marked as matched When
+         *  reset, this bit enables the VLAN Tag perfect matching The frames with matched VLAN
+         *  Tag are marked as matched
+         */
+        uint32_t vtim:1;
+        /** esvl : R/W; bitpos: [18]; default: 0;
+         *  Enable SVLAN When this bit is set, the MAC transmitter and receiver also consider
+         *  the SVLAN _Type = 0x88A8_ frames as valid VLAN tagged frames
+         */
+        uint32_t esvl:1;
+        /** vthm : R/W; bitpos: [19]; default: 0;
+         *  VLAN Tag Hash Table Match Enable When set, the most significant four bits of the
+         *  VLAN tag’s CRC are used to index the content of Register 354 _VLAN Hash Table
+         *  Register_ A value of 1 in the VLAN Hash Table register, corresponding to the index,
+         *  indicates that the frame matched the VLAN hash table When Bit 16 _ETV_ is set, the
+         *  CRC of the 12bit VLAN Identifier _VID_ is used for comparison whereas when ETV is
+         *  reset, the CRC of the 16bit VLAN tag is used for comparison When reset, the VLAN
+         *  Hash Match operation is not performed If the VLAN Hash feature is not enabled
+         *  during core configuration, this bit is reserved _RO with default value_
+         */
+        uint32_t vthm:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gmac_register7_vlantagregister_reg_t;
+
+/** Type of register8_versionregister register
+ *  Identifies the version of the Core
+ */
+typedef union {
+    struct {
+        /** snpsver : RO; bitpos: [7:0]; default: 55;
+         *  Synopsysdefined Version _37_
+         */
+        uint32_t snpsver:8;
+        /** userver : RO; bitpos: [15:8]; default: 0;
+         *  Userdefined Version _configured with coreConsultant_
+         */
+        uint32_t userver:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register8_versionregister_reg_t;
+
+/** Type of register9_debugregister register
+ *  Gives the status of various internal blocks for debugging
+ */
+typedef union {
+    struct {
+        /** rpests : RO; bitpos: [0]; default: 0;
+         *  MAC GMII or MII Receive Protocol Engine Status When high, this bit indicates that
+         *  the MAC GMII or MII receive protocol engine is actively receiving data and not in
+         *  IDLE state
+         */
+        uint32_t rpests:1;
+        /** rfcfcsts : RO; bitpos: [2:1]; default: 0;
+         *  MAC Receive Frame FIFO Controller Status When high, this field indicates the active
+         *  state of the small FIFO Read and Write controllers of the MAC Receive Frame
+         *  Controller Module RFCFCSTS[1] represents the status of small FIFO Read controller
+         *  RFCFCSTS[0] represents the status of small FIFO Write controller
+         */
+        uint32_t rfcfcsts:2;
+        uint32_t reserved_3:1;
+        /** rwcsts : RO; bitpos: [4]; default: 0;
+         *  MTL Rx FIFO Write Controller Active Status When high, this bit indicates that the
+         *  MTL Rx FIFO Write Controller is active and is transferring a received frame to the
+         *  FIFO
+         */
+        uint32_t rwcsts:1;
+        /** rrcsts : RO; bitpos: [6:5]; default: 0;
+         *  MTL RxFIFO Read Controller State This field gives the state of the Rx FIFO read
+         *  Controller: 00: IDLE state 01: Reading frame data 10: Reading frame status _or
+         *  timestamp_ 11: Flushing the frame data and status
+         */
+        uint32_t rrcsts:2;
+        uint32_t reserved_7:1;
+        /** rxfsts : RO; bitpos: [9:8]; default: 0;
+         *  MTL RxFIFO FillLevel Status This field gives the status of the filllevel of the Rx
+         *  FIFO: 00: Rx FIFO Empty 01: Rx FIFO filllevel below flowcontrol deactivate
+         *  threshold 10: Rx FIFO filllevel above flowcontrol activate threshold 11: Rx FIFO
+         *  Full
+         */
+        uint32_t rxfsts:2;
+        uint32_t reserved_10:6;
+        /** tpests : RO; bitpos: [16]; default: 0;
+         *  MAC GMII or MII Transmit Protocol Engine Status When high, this bit indicates that
+         *  the MAC GMII or MII transmit protocol engine is actively transmitting data and is
+         *  not in the IDLE state
+         */
+        uint32_t tpests:1;
+        /** tfcsts : RO; bitpos: [18:17]; default: 0;
+         *  MAC Transmit Frame Controller Status This field indicates the state of the MAC
+         *  Transmit Frame Controller module: 00: IDLE state 01: Waiting for status of previous
+         *  frame or IFG or backoff period to be over 10: Generating and transmitting a Pause
+         *  frame _in the fullduplex mode_ 11: Transferring input frame for transmission
+         */
+        uint32_t tfcsts:2;
+        /** txpaused : RO; bitpos: [19]; default: 0;
+         *  MAC Transmitter in Pause When high, this bit indicates that the MAC transmitter is
+         *  in the Pause condition _in the fullduplexonly mode_ and hence does not schedule any
+         *  frame for transmission
+         */
+        uint32_t txpaused:1;
+        /** trcsts : RO; bitpos: [21:20]; default: 0;
+         *  MTL Tx FIFO Read Controller Status This field indicates the state of the Tx FIFO
+         *  Read Controller: 00: IDLE state 01: READ state _transferring data to the MAC
+         *  transmitter_ 10: Waiting for TxStatus from the MAC transmitter 11: Writing the
+         *  received TxStatus or flushing the Tx FIFO
+         */
+        uint32_t trcsts:2;
+        /** twcsts : RO; bitpos: [22]; default: 0;
+         *  MTL Tx FIFO Write Controller Status When high, this bit indicates that the MTL Tx
+         *  FIFO Write Controller is active and is transferring data to the Tx FIFO
+         */
+        uint32_t twcsts:1;
+        uint32_t reserved_23:1;
+        /** txfsts : RO; bitpos: [24]; default: 0;
+         *  MTL Tx FIFO Not Empty Status When high, this bit indicates that the MTL Tx FIFO is
+         *  not empty and some data is left for transmission
+         */
+        uint32_t txfsts:1;
+        /** txstsfsts : RO; bitpos: [25]; default: 0;
+         *  MTL TxStatus FIFO Full Status When high, this bit indicates that the MTL TxStatus
+         *  FIFO is full Therefore, the MTL cannot accept any more frames for transmission This
+         *  bit is reserved in the GMACAHB and GMACDMA configurations
+         */
+        uint32_t txstsfsts:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} gmac_register9_debugregister_reg_t;
+
+/** Type of register10_remotewakeupframefilterregister register
+ *  Remote Wake-Up Frame Filter Register
+ */
+typedef union {
+    struct {
+        /** wkupfrm_filter : R/W; bitpos: [31:0]; default: 0;
+         *  This is the address through which the application writes or reads the remote
+         *  wake-up frame filter registers.The reg_wkupfrm_filter register is a pointer to
+         *  eight reg_wkupfrm_filter registers.The reg_wkupfrm_filter register is loaded by
+         *  sequentially loading the eight register values.Eight sequential writes to this
+         *  address(0x0028)write all reg_wkupfrm_filter registers.Similarly, eight sequential
+         *  reads from this address(0x0028) read all reg_wkupfrm_filter registers.
+         *  This register is present only when you select the PMT module Remote Wake-Up feature
+         *  in coreConsultant.
+         */
+        uint32_t wkupfrm_filter:32;
+    };
+    uint32_t val;
+} gmac_register10_remotewakeupframefilterregister_reg_t;
+
+/** Type of register11_pmtcontrolandstatusregister register
+ *  PMT Control and Status Register. This register is present only when you select the
+ *  PMT module in coreConsultant.
+ */
+typedef union {
+    struct {
+        /** pwrdwn : R/W1S; bitpos: [0]; default: 0;
+         *  Power Down
+         *  When set, the MAC receiver drops all received frames until it receives the expected
+         *  magic packet or remote wake-up frame. This bit is then self-cleared and the
+         *  power-down mode is disabled. The Software can also clear this bit before the
+         *  expected magic packet or remote wake-up frame is received. The frames, received by
+         *  MAC after this bit is cleared, are forwarded to the application. This bit must only
+         *  be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Up Frame Enable
+         *  bit is set high.
+         */
+        uint32_t pwrdwn:1;
+        /** mgkpkten : R/W; bitpos: [1]; default: 0;
+         *  Magic Packet Enable
+         *  When set, enables generation of a power management event because of magic packet
+         *  reception.
+         */
+        uint32_t mgkpkten:1;
+        /** rwkpkten : R/W; bitpos: [2]; default: 0;
+         *  Remote Wake-Up Frame Enable
+         *  When set, enables generation of a power management event because of remote wake-up
+         *  frame reception.
+         */
+        uint32_t rwkpkten:1;
+        uint32_t reserved_3:2;
+        /** mgkprcvd : R/W; bitpos: [5]; default: 0;
+         *  Magic Packet Received
+         *  When set,this bit indicates that the power management event is generated because of
+         *  the reception of a magic packet. This bit is cleared by Read into this register.
+         */
+        uint32_t mgkprcvd:1;
+        /** rwkprcvd : R/W; bitpos: [6]; default: 0;
+         *  Remote Wake-Up Frame Received
+         *  When set, this bit indicates the power management event is generated because of the
+         *  reception of a remote wake-up frame. This bit is cleared by a Read into this
+         *  register.
+         */
+        uint32_t rwkprcvd:1;
+        uint32_t reserved_7:2;
+        /** glblucast : R/W; bitpos: [9]; default: 0;
+         *  Global Unicast.
+         *  When set, enables any unicast packet filtered by the MAX(DAF) address recognition
+         *  to be a remote wake-up frame.
+         */
+        uint32_t glblucast:1;
+        uint32_t reserved_10:14;
+        /** rwkptr : RO; bitpos: [28:24]; default: 0;
+         *  Remote Wake-up FIFO Pointer.
+         *  This field gives the current value(0 to 31) of the Remote Wake-up Frame filter
+         *  register pointer. When the value of this pointer is erual to 7, 15, 23 or 31, the
+         *  contents of the Remote Wake-up Frame Filter Register are transferred to the
+         *  clk_rx_i domain when a write occurs to that register.
+         *  The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the
+         *  number of Remote Wakeup Filters selected during configuration.
+         */
+        uint32_t rwkptr:5;
+        uint32_t reserved_29:2;
+        /** rwkfiltrst : R/W1S; bitpos: [31]; default: 0;
+         *  Remote Wake-Up Frame Filter Register Pointer Reset.
+         *  When this bit is set, it resets the remote wake-up frame filter register pointer to
+         *  3'b000. It is automatically cleared after 1 clock cycle.
+         */
+        uint32_t rwkfiltrst:1;
+    };
+    uint32_t val;
+} gmac_register11_pmtcontrolandstatusregister_reg_t;
+
+/** Type of register12_lpicontrolandstatusregister register
+ *  Controls the Low Power Idle _LPI_ operations and provides the LPI status of the
+ *  core This register is present only when you select the Energy Efficient Ethernet
+ *  feature in coreConsultant
+ */
+typedef union {
+    struct {
+        /** tlpien : R/W; bitpos: [0]; default: 0;
+         *  Transmit LPI Entry When set, this bit indicates that the MAC Transmitter has
+         *  entered the LPI state because of the setting of the LPIEN bit This bit is cleared
+         *  by a read into this register
+         */
+        uint32_t tlpien:1;
+        /** tlpiex : R/W; bitpos: [1]; default: 0;
+         *  Transmit LPI Exit When set, this bit indicates that the MAC transmitter has exited
+         *  the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has
+         *  expired This bit is cleared by a read into this register
+         */
+        uint32_t tlpiex:1;
+        /** rlpien : R/W; bitpos: [2]; default: 0;
+         *  Receive LPI Entry When set, this bit indicates that the MAC Receiver has received
+         *  an LPI pattern and entered the LPI state This bit is cleared by a read into this
+         *  register Note: This bit may not get set if the MAC stops receiving the LPI pattern
+         *  for a very short duration, such as, less than 3 clock cycles of CSR clock
+         */
+        uint32_t rlpien:1;
+        /** rlpiex : R/W; bitpos: [3]; default: 0;
+         *  Receive LPI Exit When set, this bit indicates that the MAC Receiver has stopped
+         *  receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and
+         *  resumed the normal reception This bit is cleared by a read into this register Note:
+         *  This bit may not get set if the MAC stops receiving the LPI pattern for a very
+         *  short duration, such as, less than 3 clock cycles of CSR clock
+         */
+        uint32_t rlpiex:1;
+        uint32_t reserved_4:4;
+        /** tlpist : RO; bitpos: [8]; default: 0;
+         *  Transmit LPI State When set, this bit indicates that the MAC is transmitting the
+         *  LPI pattern on the GMII or MII interface
+         */
+        uint32_t tlpist:1;
+        /** rlpist : RO; bitpos: [9]; default: 0;
+         *  Receive LPI State When set, this bit indicates that the MAC is receiving the LPI
+         *  pattern on the GMII or MII interface
+         */
+        uint32_t rlpist:1;
+        uint32_t reserved_10:6;
+        /** lpien : R/W; bitpos: [16]; default: 0;
+         *  LPI Enable When set, this bit instructs the MAC Transmitter to enter the LPI state
+         *  When reset, this bit instructs the MAC to exit the LPI state and resume normal
+         *  transmission This bit is cleared when the LPITXA bit is set and the MAC exits the
+         *  LPI state because of the arrival of a new packet for transmission
+         */
+        uint32_t lpien:1;
+        /** pls : R/W; bitpos: [17]; default: 0;
+         *  PHY Link Status This bit indicates the link status of the PHY The MAC Transmitter
+         *  asserts the LPI pattern only when the link status is up _okay_ at least for the
+         *  time indicated by the LPI LS TIMER When set, the link is considered to be okay _up_
+         *  and when reset, the link is considered to be down
+         */
+        uint32_t pls:1;
+        /** plsen : R/W; bitpos: [18]; default: 0;
+         *  PHY Link Status Enable This bit enables the link status received on the RGMII,
+         *  SGMII, or SMII receive paths to be used for activating the LPI LS TIMER When set,
+         *  the MAC uses the linkstatus bits of Register 54 _SGMII/RGMII/SMII Control and
+         *  Status Register_ and Bit 17 _PLS_ for the LPI LS Timer trigger When cleared, the
+         *  MAC ignores the linkstatus bits of Register 54 and takes only the PLS bit This bit
+         *  is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface
+         */
+        uint32_t plsen:1;
+        /** lpitxa : R/W; bitpos: [19]; default: 0;
+         *  LPI TX Automate This bit controls the behavior of the MAC when it is entering or
+         *  coming out of the LPI mode on the transmit side This bit is not functional in the
+         *  GMAC CORE configuration in which the Tx clock gating is done during the LPI mode If
+         *  the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all
+         *  outstanding frames _in the core_ and pending frames _in the application interface_
+         *  have been transmitted The MAC comes out of the LPI mode when the application sends
+         *  any frame for transmission or the application issues a TX FIFO Flush command In
+         *  addition, the MAC automatically clears the LPIEN bit when it exits the LPI state If
+         *  TX FIFO Flush is set in Bit 20 of Register 6 _Operation Mode Register_, when the
+         *  MAC is in the LPI mode, the MAC exits the LPI mode When this bit is 0, the LPIEN
+         *  bit directly controls behavior of the MAC when it is entering or coming out of the
+         *  LPI mode
+         */
+        uint32_t lpitxa:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gmac_register12_lpicontrolandstatusregister_reg_t;
+
+/** Type of register13_lpitimerscontrolregister register
+ *  Controls the timeout values in LPI states This register is present only when you
+ *  select the Energy Efficient Ethernet feature in coreConsultant
+ */
+typedef union {
+    struct {
+        /** twt : R/W; bitpos: [15:0]; default: 0;
+         *  LPI TW TIMER This field specifies the minimum time _in microseconds_ for which the
+         *  MAC waits after it stops transmitting the LPI pattern to the PHY and before it
+         *  resumes the normal transmission The TLPIEX status bit is set after the expiry of
+         *  this timer
+         */
+        uint32_t twt:16;
+        /** lst : R/W; bitpos: [25:16]; default: 1000;
+         *  LPI LS TIMER This field specifies the minimum time _in milliseconds_ for which the
+         *  link status from the PHY should be up _OKAY_ before the LPI pattern can be
+         *  transmitted to the PHY The MAC does not transmit the LPI pattern even when the
+         *  LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count The
+         *  default value of the LPI LS Timer is 1000 _1 sec_ as defined in the IEEE standard
+         */
+        uint32_t lst:10;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} gmac_register13_lpitimerscontrolregister_reg_t;
+
+/** Type of register14_interruptstatusregister register
+ *  Contains the interrupt status
+ */
+typedef union {
+    struct {
+        /** rgsmiiis : RO; bitpos: [0]; default: 0;
+         *  RGMII or SMII Interrupt Status This bit is set because of any change in value of
+         *  the Link Status of RGMII or SMII interface _Bit 3 in Register 54 _SGMII/RGMII/SMII
+         *  Control and Status Register__ This bit is cleared when you perform a read operation
+         *  on the SGMII/RGMII/SMII Control and Status Register This bit is valid only when you
+         *  select the optional RGMII or SMII PHY interface during core configuration and
+         *  operation
+         */
+        uint32_t rgsmiiis:1;
+        /** pcslchgis : RO; bitpos: [1]; default: 0;
+         *  PCS Link Status Changed This bit is set because of any change in Link Status in the
+         *  TBI, RTBI, or SGMII PHY interface _Bit 2 in Register 49 _AN Status Register__ This
+         *  bit is cleared when you perform a read operation on the AN Status register This bit
+         *  is valid only when you select the optional TBI, RTBI, or SGMII PHY interface during
+         *  core configuration and operation
+         */
+        uint32_t pcslchgis:1;
+        /** pcsancis : RO; bitpos: [2]; default: 0;
+         *  PCS AutoNegotiation Complete This bit is set when the Autonegotiation is completed
+         *  in the TBI, RTBI, or SGMII PHY interface _Bit 5 in Register 49 _AN Status
+         *  Register__ This bit is cleared when you perform a read operation to the AN Status
+         *  register This bit is valid only when you select the optional TBI, RTBI, or SGMII
+         *  PHY interface during core configuration and operation
+         */
+        uint32_t pcsancis:1;
+        /** pmtis : RO; bitpos: [3]; default: 0;
+         *  PMT Interrupt Status This bit is set when a magic packet or remote wakeup frame is
+         *  received in the powerdown mode _see Bits 5 and 6 in the PMT Control and Status
+         *  Register_ This bit is cleared when both Bits[6:5] are cleared because of a read
+         *  operation to the PMT Control and Status register This bit is valid only when you
+         *  select the optional PMT module during core configuration
+         */
+        uint32_t pmtis:1;
+        /** mmcis : RO; bitpos: [4]; default: 0;
+         *  MMC Interrupt Status This bit is set high when any of the Bits [7:5] is set high
+         *  and cleared only when all of these bits are low This bit is valid only when you
+         *  select the optional MMC module during core configuration
+         */
+        uint32_t mmcis:1;
+        /** mmcrxis : RO; bitpos: [5]; default: 0;
+         *  MMC Receive Interrupt Status This bit is set high when an interrupt is generated in
+         *  the MMC Receive Interrupt Register This bit is cleared when all the bits in this
+         *  interrupt register are cleared This bit is valid only when you select the optional
+         *  MMC module during core configuration
+         */
+        uint32_t mmcrxis:1;
+        /** mmctxis : RO; bitpos: [6]; default: 0;
+         *  MMC Transmit Interrupt Status This bit is set high when an interrupt is generated
+         *  in the MMC Transmit Interrupt Register This bit is cleared when all the bits in
+         *  this interrupt register are cleared This bit is valid only when you select the
+         *  optional MMC module during core configuration
+         */
+        uint32_t mmctxis:1;
+        /** mmcrxipis : RO; bitpos: [7]; default: 0;
+         *  MMC Receive Checksum Offload Interrupt Status This bit is set high when an
+         *  interrupt is generated in the MMC Receive Checksum Offload Interrupt Register This
+         *  bit is cleared when all the bits in this interrupt register are cleared This bit is
+         *  valid only when you select the optional MMC module and Checksum Offload Engine
+         *  _Type 2_ during core configuration
+         */
+        uint32_t mmcrxipis:1;
+        uint32_t reserved_8:1;
+        /** tsis : RO; bitpos: [9]; default: 0;
+         *  Timestamp Interrupt Status When the Advanced Timestamp feature is enabled, this bit
+         *  is set when R_SS_RC any of the following conditions is true: The system time value
+         *  equals or exceeds the value specified in the Target Time High and Low registers
+         *  There is an overflow in the seconds register The Auxiliary snapshot trigger is
+         *  asserted This bit is cleared on reading Bit 0 of Register 458 _Timestamp Status
+         *  Register_ If default Timestamping is enabled, when set, this bit indicates that the
+         *  system time value is equal to or exceeds the value specified in the Target Time
+         *  registers In this mode, this bit is cleared after the completion of the read of
+         *  this bit In all other modes, this bit is reserved
+         */
+        uint32_t tsis:1;
+        /** lpiis : RO; bitpos: [10]; default: 0;
+         *  LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this
+         *  bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver This
+         *  bit is cleared on reading Bit 0 of Register 12 _LPI Control and Status Register_ In
+         *  all other modes, this bit is reserved
+         */
+        uint32_t lpiis:1;
+        /** gpiis : RO; bitpos: [11]; default: 0;
+         *  GPI Interrupt Status When the GPIO feature is enabled, this bit is set when any
+         *  active event _LL or LH_ occurs on the GPIS field _Bits [3:0]_ of Register 56
+         *  _General Purpose IO Register_ and the corresponding GPIE bit is enabled This bit is
+         *  cleared on reading lane 0 _GPIS_ of Register 56 _General Purpose IO Register_ When
+         *  the GPIO feature is not enabled, this bit is reserved
+         */
+        uint32_t gpiis:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gmac_register14_interruptstatusregister_reg_t;
+
+/** Type of register15_interruptmaskregister register
+ *  Contains the masks for generating the interrupts
+ */
+typedef union {
+    struct {
+        /** rgsmiiim : R/W; bitpos: [0]; default: 0;
+         *  RGMII or SMII Interrupt Mask When set, this bit disables the assertion of the
+         *  interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit
+         *  in Register 14 _Interrupt Status Register_
+         */
+        uint32_t rgsmiiim:1;
+        /** pcslchgim : R/W; bitpos: [1]; default: 0;
+         *  PCS Link Status Interrupt Mask When set, this bit disables the assertion of the
+         *  interrupt signal because of the setting of the PCS Linkstatus changed bit in
+         *  Register 14 _Interrupt Status Register_
+         */
+        uint32_t pcslchgim:1;
+        /** pcsancim : R/W; bitpos: [2]; default: 0;
+         *  PCS AN Completion Interrupt Mask When set, this bit disables the assertion of the
+         *  interrupt signal because of the setting of PCS Autonegotiation complete bit in
+         *  Register 14 _Interrupt Status Register_
+         */
+        uint32_t pcsancim:1;
+        /** pmtim : R/W; bitpos: [3]; default: 0;
+         *  PMT Interrupt Mask When set, this bit disables the assertion of the interrupt
+         *  signal because of the setting of PMT Interrupt Status bit in Register 14 _Interrupt
+         *  Status Register_
+         */
+        uint32_t pmtim:1;
+        uint32_t reserved_4:5;
+        /** tsim : R/W; bitpos: [9]; default: 0;
+         *  Timestamp Interrupt Mask When set, this bit disables the assertion of the interrupt
+         *  signal because of the setting of Timestamp Interrupt Status bit in Register 14
+         *  _Interrupt Status Register_ This bit is valid only when IEEE1588 timestamping is
+         *  enabled In all other modes, this bit is reserved
+         */
+        uint32_t tsim:1;
+        /** lpiim : R/W; bitpos: [10]; default: 0;
+         *  LPI Interrupt Mask When set, this bit disables the assertion of the interrupt
+         *  signal because of the setting of the LPI Interrupt Status bit in Register 14
+         *  _Interrupt Status Register_ This bit is valid only when you select the Energy
+         *  Efficient Ethernet feature during core configuration In all other modes, this bit
+         *  is reserved
+         */
+        uint32_t lpiim:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} gmac_register15_interruptmaskregister_reg_t;
+
+/** Type of register16_macaddress0highregister register
+ *  Contains the higher 16 bits of the first MAC address
+ */
+typedef union {
+    struct {
+        /** addrhi_0 : R/W; bitpos: [15:0]; default: 65535;
+         *  MAC Address0 [47:32] This field contains the upper 16 bits _47:32_ of the first
+         *  6byte MAC address The MAC uses this field for filtering the received frames and
+         *  inserting the MAC address in the Transmit Flow Control _Pause_ Frames
+         */
+        uint32_t addrhi_0:16;
+        uint32_t reserved_16:15;
+        /** ae_0 : RO; bitpos: [31]; default: 1;
+         *  Address Enable This bit is always set to 1
+         */
+        uint32_t ae_0:1;
+    };
+    uint32_t val;
+} gmac_register16_macaddress0highregister_reg_t;
+
+/** Type of register17_macaddress0lowregister register
+ *  Contains the lower 32 bits of the first MAC address
+ */
+typedef union {
+    struct {
+        /** addrlo_0 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  MAC Address0 [31:0] This field contains the lower 32 bits of the first 6byte MAC
+         *  address This is used by the MAC for filtering the received frames and inserting the
+         *  MAC address in the Transmit Flow Control _Pause_ Frames
+         */
+        uint32_t addrlo_0:32;
+    };
+    uint32_t val;
+} gmac_register17_macaddress0lowregister_reg_t;
+
+/** Type of register18_macaddress1highregister register
+ *  Contains the higher 16 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+typedef union {
+    struct {
+        /** addrhi_1 : R/W; bitpos: [15:0]; default: 65535;
+         *  MAC Address1 [47:32] This field contains the upper 16 bits _47:32_ of the second
+         *  6byte MAC address
+         */
+        uint32_t addrhi_1:16;
+        uint32_t reserved_16:8;
+        /** mbc_1 : R/W; bitpos: [29:24]; default: 0;
+         *  Mask Byte Control These bits are mask control bits for comparison of each of the
+         *  MAC Address bytes When set high, the MAC does not compare the corresponding byte of
+         *  received DA or SA with the contents of MAC Address1 registers Each bit controls the
+         *  masking of the bytes as follows: Bit 29: Register 18[15:8] Bit 28: Register 18[7:0]
+         *  Bit 27: Register 19[31:24]  Bit 24: Register 19[7:0] You can filter a group of
+         *  addresses _known as group address filtering_ by masking one or more bytes of the
+         *  address
+         */
+        uint32_t mbc_1:6;
+        /** sa_1 : R/W; bitpos: [30]; default: 0;
+         *  Source Address When this bit is set, the MAC Address1[47:0] is used to compare with
+         *  the SA fields of the received frame When this bit is reset, the MAC Address1[47:0]
+         *  is used to compare with the DA fields of the received frame
+         */
+        uint32_t sa_1:1;
+        /** ae_1 : R/W; bitpos: [31]; default: 0;
+         *  Address Enable
+         */
+        uint32_t ae_1:1;
+    };
+    uint32_t val;
+} gmac_register18_macaddress1highregister_reg_t;
+
+/** Type of register19_macaddress1lowregister register
+ *  Contains the lower 32 bits of the second MAC address This register is present only
+ *  when Enable MAC Address1 is selected in coreConsultant _See Table 78_
+ */
+typedef union {
+    struct {
+        /** addrlo_1 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  MAC Address1 [31:0] This field contains the lower 32 bits of the second 6byte MAC
+         *  address The content of this field is undefined until loaded by the Application
+         *  after the initialization process
+         */
+        uint32_t addrlo_1:32;
+    };
+    uint32_t val;
+} gmac_register19_macaddress1lowregister_reg_t;
+
+/** Type of macaddress2highregistercontainsthehigher16bitsofthethirdmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_2 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address2 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_2:16;
+        uint32_t reserved_16:8;
+        /** mbc_2 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address2 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_2:6;
+        /** sa_2 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address2 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_2:1;
+        /** ae_2 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address2 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_2:1;
+    };
+    uint32_t val;
+} gmac_macaddress2highregistercontainsthehigher16bitsofthethirdmacaddress_reg_t;
+
+/** Type of macaddress2lowregistercontainsthelower32bitsofthethirdmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_2 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address2 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_2:32;
+    };
+    uint32_t val;
+} gmac_macaddress2lowregistercontainsthelower32bitsofthethirdmacaddress_reg_t;
+
+/** Type of macaddress3highregistercontainsthehigher16bitsofthefourthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_3 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address3 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_3:16;
+        uint32_t reserved_16:8;
+        /** mbc_3 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address3 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_3:6;
+        /** sa_3 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address3 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_3:1;
+        /** ae_3 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address3 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_3:1;
+    };
+    uint32_t val;
+} gmac_macaddress3highregistercontainsthehigher16bitsofthefourthmacaddress_reg_t;
+
+/** Type of macaddress3lowregistercontainsthelower32bitsofthefourthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_3 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address3 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_3:32;
+    };
+    uint32_t val;
+} gmac_macaddress3lowregistercontainsthelower32bitsofthefourthmacaddress_reg_t;
+
+/** Type of macaddress4highregistercontainsthehigher16bitsofthefifthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_4 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address4 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_4:16;
+        uint32_t reserved_16:8;
+        /** mbc_4 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address4 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_4:6;
+        /** sa_4 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address4 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_4:1;
+        /** ae_4 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address4 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_4:1;
+    };
+    uint32_t val;
+} gmac_macaddress4highregistercontainsthehigher16bitsofthefifthmacaddress_reg_t;
+
+/** Type of macaddress4lowregistercontainsthelower32bitsofthefifthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_4 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address4 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_4:32;
+    };
+    uint32_t val;
+} gmac_macaddress4lowregistercontainsthelower32bitsofthefifthmacaddress_reg_t;
+
+/** Type of macaddress5highregistercontainsthehigher16bitsofthesixthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_5 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address5 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_5:16;
+        uint32_t reserved_16:8;
+        /** mbc_5 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address5 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_5:6;
+        /** sa_5 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address5 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_5:1;
+        /** ae_5 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address5 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_5:1;
+    };
+    uint32_t val;
+} gmac_macaddress5highregistercontainsthehigher16bitsofthesixthmacaddress_reg_t;
+
+/** Type of macaddress5lowregistercontainsthelower32bitsofthesixthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_5 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address5 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_5:32;
+    };
+    uint32_t val;
+} gmac_macaddress5lowregistercontainsthelower32bitsofthesixthmacaddress_reg_t;
+
+/** Type of macaddress6highregistercontainsthehigher16bitsoftheseventhmacaddress
+ *  register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_6 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address6 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_6:16;
+        uint32_t reserved_16:8;
+        /** mbc_6 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address6 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_6:6;
+        /** sa_6 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address6 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_6:1;
+        /** ae_6 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address6 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_6:1;
+    };
+    uint32_t val;
+} gmac_macaddress6highregistercontainsthehigher16bitsoftheseventhmacaddress_reg_t;
+
+/** Type of macaddress6lowregistercontainsthelower32bitsoftheseventhmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_6 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address6 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_6:32;
+    };
+    uint32_t val;
+} gmac_macaddress6lowregistercontainsthelower32bitsoftheseventhmacaddress_reg_t;
+
+/** Type of macaddress7highregistercontainsthehigher16bitsoftheeighthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrhi_7 : R/W; bitpos: [15:0]; default: 65535;
+         *  This register is present only when Enable MAC Address7 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrhi_7:16;
+        uint32_t reserved_16:8;
+        /** mbc_7 : R/W; bitpos: [29:24]; default: 0;
+         *  This register is present only when Enable MAC Address7 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t mbc_7:6;
+        /** sa_7 : R/W; bitpos: [30]; default: 0;
+         *  This register is present only when Enable MAC Address7 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t sa_7:1;
+        /** ae_7 : R/W; bitpos: [31]; default: 0;
+         *  This register is present only when Enable MAC Address7 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t ae_7:1;
+    };
+    uint32_t val;
+} gmac_macaddress7highregistercontainsthehigher16bitsoftheeighthmacaddress_reg_t;
+
+/** Type of macaddress7lowregistercontainsthelower32bitsoftheeighthmacaddress register
+ *  Reserved
+ */
+typedef union {
+    struct {
+        /** addrlo_7 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This register is present only when Enable MAC Address7 is selected in
+         *  coreConsultant _See Table 78_
+         */
+        uint32_t addrlo_7:32;
+    };
+    uint32_t val;
+} gmac_macaddress7lowregistercontainsthelower32bitsoftheeighthmacaddress_reg_t;
+
+/** Type of register48_ancontrolregister register
+ *  Enables and/or restarts autonegotiation This register also enables the Physical
+ *  Coding Sublayer _PCS_ loopback This register is present only when you select the
+ *  TBI, RTBI, or SGMII interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:9;
+        /** ran : R/W1S; bitpos: [9]; default: 0;
+         *  Restart AutoNegotiation When set, this bit causes autonegotiation to restart if Bit
+         *  12 _ANE_ is set This bit is selfclearing after autonegotiation starts This bit
+         *  should be cleared for normal operation
+         */
+        uint32_t ran:1;
+        uint32_t reserved_10:2;
+        /** and : R/W; bitpos: [12]; default: 0;
+         *  AutoNegotiation Enable When set, this bit enables the MAC to perform
+         *  autonegotiation with the link partner Clearing this bit disables the autonegotiation
+         */
+        uint32_t and:1;
+        uint32_t reserved_13:1;
+        /** ele : R/W; bitpos: [14]; default: 0;
+         *  External Loopback Enable When set, this bit causes the PHY to loopback the transmit
+         *  data into the receive path The pcs_ewrap_o signal is asserted high when this bit is
+         *  set
+         */
+        uint32_t ele:1;
+        uint32_t reserved_15:1;
+        /** ecd : R/W; bitpos: [16]; default: 0;
+         *  Enable Comma Detect When set, this bit enables the PHY for comma detection and word
+         *  resynchronization This bit controls the pcs_en_cdet_o signal on the TBI, RTBI, or
+         *  SGMII interface
+         */
+        uint32_t ecd:1;
+        /** lr : R/W; bitpos: [17]; default: 0;
+         *  Lock to Reference When set, this bit enables the PHY to lock its PLL to the 125 MHz
+         *  reference clock This bit controls the pcs_lck_ref_o signal on the TBI, RTBI, or
+         *  SGMII interface
+         */
+        uint32_t lr:1;
+        /** sgmral : R/W; bitpos: [18]; default: 0;
+         *  SGMII RAL Control When set, this bit forces the SGMII RAL block to operate in the
+         *  speed configured in the Speed and Port Select bits of the MAC Configuration
+         *  register This is useful when the SGMII interface is used in a direct MAC to MAC
+         *  connection _without a PHY_ and any MAC must reconfigure the speed When reset, the
+         *  SGMII RAL block operates according to the link speed status received on SGMII _from
+         *  the PHY_ This bit is reserved _and RO_ if the SGMII PHY interface is not selected
+         *  during core configuration
+         */
+        uint32_t sgmral:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} gmac_register48_ancontrolregister_reg_t;
+
+/** Type of register49_anstatusregister register
+ *  Indicates the link and autonegotiation status This register is present only when
+ *  you select the TBI, RTBI, or SGMII interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** ls : RO; bitpos: [2]; default: 0;
+         *  Link Status This bit indicates whether the data channel _link_ is up or down For
+         *  the TBI, RTBI or SGMII interfaces, if ANEG is going on, data cannot be transferred
+         *  across the link and hence the link is given as down
+         */
+        uint32_t ls:1;
+        /** ana : RO; bitpos: [3]; default: 1;
+         *  AutoNegotiation Ability This bit is always high because the MAC supports auto
+         *  negotiation
+         */
+        uint32_t ana:1;
+        uint32_t reserved_4:1;
+        /** anc : RO; bitpos: [5]; default: 0;
+         *  AutoNegotiation Complete When set, this bit indicates that the autonegotiation
+         *  process is complete This bit is cleared when autonegotiation is reinitiated
+         */
+        uint32_t anc:1;
+        uint32_t reserved_6:2;
+        /** es : RO; bitpos: [8]; default: 1;
+         *  Extended Status This bit is tied to high if the TBI or RTBI interface is selected
+         *  during core configuration indicating that the MAC supports extended status
+         *  information in Register 53 _TBI Extended  Status Register_ This bit is tied to low
+         *  if the SGMII interface is selected and the TBI or RTBI interface is not selected
+         *  during core configuration indicating that Register 53 is not present
+         */
+        uint32_t es:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} gmac_register49_anstatusregister_reg_t;
+
+/** Type of register50_autonegotiationadvertisementregister register
+ *  This register is configured before autonegotiation begins It contains the
+ *  advertised ability of the MAC This register is present only when you select the TBI
+ *  or RTBI interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** fd : R/W; bitpos: [5]; default: 1;
+         *  FullDuplex When set high, this bit indicates that the MAC supports the fullduplex
+         *  mode
+         */
+        uint32_t fd:1;
+        /** hd : R/W; bitpos: [6]; default: 1;
+         *  HalfDuplex When set high, this bit indicates that the MAC supports the halfduplex
+         *  mode This bit is always low _and RO_ when the MAC is configured for the
+         *  fullduplexonly mode
+         */
+        uint32_t hd:1;
+        /** pse : R/W; bitpos: [8:7]; default: 3;
+         *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+         *  the MAC is capable of configuring the Pause function as defined in IEEE 8023x The
+         *  encoding of these bits is defined in IEEE 8023z, Section 37214
+         */
+        uint32_t pse:2;
+        uint32_t reserved_9:3;
+        /** rfe : R/W; bitpos: [13:12]; default: 0;
+         *  Remote Fault Encoding These bits provide a remote fault encoding, indicating to a
+         *  link partner that a fault or error condition has occurred The encoding of these
+         *  bits is defined in IEEE 8023z, Section 37215
+         */
+        uint32_t rfe:2;
+        uint32_t reserved_14:1;
+        /** np : RO; bitpos: [15]; default: 0;
+         *  Next Page Support This bit is always low because the MAC does not support the next
+         *  page
+         */
+        uint32_t np:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register50_autonegotiationadvertisementregister_reg_t;
+
+/** Type of register51_autonegotiationlinkpartnerabilityregister register
+ *  Contains the advertised ability of the link partner Its value is valid after
+ *  successful completion of autonegotiation or when a new base page has been received
+ *  _indicated in the AutoNegotiation Expansion Register_ This register is present only
+ *  when you select the TBI or RTBI interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** fd_ability : RO; bitpos: [5]; default: 0;
+         *  FullDuplex When set, this bit indicates that the link partner has the ability to
+         *  operate in the full duplex mode When cleared, this bit indicates that the link
+         *  partner does not have the ability to operate in the fullduplex mode
+         */
+        uint32_t fd_ability:1;
+        /** hd_ability : RO; bitpos: [6]; default: 0;
+         *  HalfDuplex When set, this bit indicates that the link partner has the ability to
+         *  operate in the halfduplex mode When cleared, this bit indicates that the link
+         *  partner does not have the ability to operate in the halfduplex mode
+         */
+        uint32_t hd_ability:1;
+        /** pse_ability : RO; bitpos: [8:7]; default: 0;
+         *  Pause Encoding These bits provide an encoding for the Pause bits, indicating that
+         *  the link partner's capability of configuring the Pause function as defined in the
+         *  IEEE 8023x specification The encoding of these bits is defined in IEEE 8023z,
+         *  Section 37214
+         */
+        uint32_t pse_ability:2;
+        uint32_t reserved_9:3;
+        /** rfe_ability : RO; bitpos: [13:12]; default: 0;
+         *  Remote Fault Encoding These bits provide a remote fault encoding, indicating a
+         *  fault or error condition of the link partner The encoding of these bits is defined
+         *  in IEEE 8023z, Section 37215
+         */
+        uint32_t rfe_ability:2;
+        /** ack : RO; bitpos: [14]; default: 0;
+         *  Acknowledge When set, the autonegotiation function uses this bit to indicate that
+         *  the link partner has successfully received the base page of the MAC When cleared,
+         *  it indicates that the link partner did not successfully receive the base page of
+         *  the MAC
+         */
+        uint32_t ack:1;
+        /** no : RO; bitpos: [15]; default: 0;
+         *  Next Page Support When set, this bit indicates that more next page information is
+         *  available When cleared, this bit indicates that next page exchange is not desired
+         */
+        uint32_t no:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register51_autonegotiationlinkpartnerabilityregister_reg_t;
+
+/** Type of register52_autonegotiationexpansionregister register
+ *  Indicates whether a new base page has been received from the link partner This
+ *  register is present only when you select the TBI or RTBI interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** npr : RO; bitpos: [1]; default: 0;
+         *  New Page Received When set, this bit indicates that the MAC has received a new page
+         *  This bit is cleared when read
+         */
+        uint32_t npr:1;
+        /** npa : RO; bitpos: [2]; default: 0;
+         *  Next Page Ability This bit is always low because the MAC does not support the next
+         *  page function
+         */
+        uint32_t npa:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gmac_register52_autonegotiationexpansionregister_reg_t;
+
+/** Type of register53_tbiextendedstatusregister register
+ *  Indicates all modes of operation of the MAC This register is present only when you
+ *  select the TBI or RTBI interface in coreConsultant
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:14;
+        /** ghd : RO; bitpos: [14]; default: 1;
+         *  1000BASEX HalfDuplex Capable This bit indicates that the MAC is able to perform the
+         *  halfduplex and 1000BASEX operations This bit is always low when the MAC is
+         *  configured for the fullduplexonly operation during core configuration
+         */
+        uint32_t ghd:1;
+        /** gfd : RO; bitpos: [15]; default: 1;
+         *  1000BASEX FullDuplex Capable This bit indicates that the MAC is able to perform the
+         *  fullduplex and 1000BASEX operations
+         */
+        uint32_t gfd:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register53_tbiextendedstatusregister_reg_t;
+
+/** Type of register54_sgmii_rgmii_smiicontrolandstatusregister register
+ *  Indicates the status signals received from the PHY through the SGMII, RGMII, or
+ *  SMII interface This register is present only when you select the SGMII, RGMII, or
+ *  SMII interface in coreConsultant
+ */
+typedef union {
+    struct {
+        /** lnkmod : RO; bitpos: [0]; default: 0;
+         *  Link Mode This bit indicates the current mode of operation of the link: 1’b0:
+         *  Halfduplex mode 1’b1: Fullduplex mode
+         */
+        uint32_t lnkmod:1;
+        /** lnkspeed : RO; bitpos: [2:1]; default: 2;
+         *  Link Speed
+         */
+        uint32_t lnkspeed:2;
+        /** lnksts : RO; bitpos: [3]; default: 0;
+         *  Link Status This bit indicates whether the link between the local PHY and the
+         *  remote PHY is up or down It gives the status of the link between the SGMII of MAC
+         *  and the SGMII of the local PHY The status bits are received from the local PHY
+         *  during ANEG between he MAC and PHY on the SGMII link
+         */
+        uint32_t lnksts:1;
+        /** jabto : RO; bitpos: [4]; default: 0;
+         *  Jabber Timeout This bit indicates whether there is jabber timeout error _1'b1_ in
+         *  the received frame This bit is reserved when the MAC is configured for the SGMII or
+         *  RGMII PHY interface
+         */
+        uint32_t jabto:1;
+        /** falscardet : RO; bitpos: [5]; default: 0;
+         *  False Carrier Detected This bit indicates whether the SMII PHY detected false
+         *  carrier _1'b1_ This bit is reserved when the MAC is configured for the SGMII or
+         *  RGMII PHY interface
+         */
+        uint32_t falscardet:1;
+        uint32_t reserved_6:10;
+        /** smidrxs : R/W; bitpos: [16]; default: 0;
+         *  Delay SMII RX Data Sampling with respect to the SMII SYNC Signal When set, the
+         *  first bit of the SMII RX data is sampled one cycle after the SMII SYNC signal When
+         *  reset, the first bit of the SMII RX data is sampled along with the SMII SYNC signal
+         *  If the SMII PHY Interface with source synchronous mode is selected during core
+         *  configuration, this bit is reserved _RO with default value_
+         */
+        uint32_t smidrxs:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} gmac_register54_sgmii_rgmii_smiicontrolandstatusregister_reg_t;
+
+/** Type of register55_watchdogtimeoutregister register
+ *  Controls the watchdog timeout for received frames
+ */
+typedef union {
+    struct {
+        /** wto : R/W; bitpos: [13:0]; default: 0;
+         *  Watchdog Timeout When Bit 16 _PWE_ is set and Bit 23 _WD_ of Register 0 _MAC
+         *  Configuration Register_ is reset, this field is used as watchdog timeout for a
+         *  received frame If the length of a received frame exceeds the value of this field,
+         *  such frame is terminated and declared as an error frame Note: When Bit 16 _PWE_ is
+         *  set, the value in this field should be more than 1,522 _0x05F2_ Otherwise, the IEEE
+         *  Std 8023specified valid tagged frames are declared as error frames and are dropped
+         */
+        uint32_t wto:14;
+        uint32_t reserved_14:2;
+        /** pwe : R/W; bitpos: [16]; default: 0;
+         *  Programmable Watchdog Enable When this bit is set and Bit 23 _WD_ of Register 0
+         *  _MAC Configuration Register_ is reset, the WTO field _Bits[13:0]_ is used as
+         *  watchdog timeout for a received frame When this bit is cleared, the watchdog
+         *  timeout for a received frame is controlled by the setting of Bit 23 _WD_ and Bit 20
+         *  _JE_ in Register 0 _MAC Configuration Register_
+         */
+        uint32_t pwe:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} gmac_register55_watchdogtimeoutregister_reg_t;
+
+/** Type of register56_generalpurposeioregister register
+ *  Provides the control to drive up to 4 bits of output ports _GPO_ and also provides
+ *  the status of up to 4 input ports _GPIS_
+ */
+typedef union {
+    struct {
+        /** gpis : R/W; bitpos: [3:0]; default: 0;
+         *  General Purpose Input Status This field gives the status of the signals connected
+         *  to the gpi_i input ports This field is of the following types based on the setting
+         *  of the corresponding GPIT field of this register: Latchedlow _LL_: This field is
+         *  cleared when the corresponding gpi_i input becomes low This field remains low until
+         *  the host reads this field After this, this field reflects the current value of the
+         *  gpi_i input Latchedhigh _LH_: This field is set when the corresponding gpi_i input
+         *  becomes high This field remains high until the host reads this field After this,
+         *  this field reflects the current value of the gpi_i input The number of bits
+         *  available in this field depend on the GP Input Signal Width option Other bits are
+         *  not used _reserved and always reset_
+         */
+        uint32_t gpis:4;
+        uint32_t reserved_4:4;
+        /** gpo : R/W; bitpos: [11:8]; default: 0;
+         *  General Purpose Output When this bit is set, it directly drives the gpo_o output
+         *  ports When this bit is reset, it does not directly drive the gpo_o output ports The
+         *  number of bits available in this field depend on the GP Output Signal Width option
+         *  Other bits are not used _reserved and always reset_
+         */
+        uint32_t gpo:4;
+        uint32_t reserved_12:4;
+        /** gpie : R/W; bitpos: [19:16]; default: 0;
+         *  GPI Interrupt Enable When this bit is set and the programmed event _LL or LH_
+         *  occurs on the corresponding GPIS bit, Bit 11 _GPIIS_ of Register 14 _Interrupt
+         *  Status Register_ is set Accordingly, the interrupt is generated on the mci_intr_o
+         *  or sbd_intr_o The GPIIS bit is cleared when the host reads the Bits[7:0] of this
+         *  register When reset, Bit 11 _GPIIS_ of Register 14 _Interrupt Status Register_ is
+         *  not set when any event occurs on the corresponding GPIS bits The number of bits
+         *  available in this field depend on the GP Input Signal Width option Other bits are
+         *  not used _reserved and always reset_
+         */
+        uint32_t gpie:4;
+        uint32_t reserved_20:4;
+        /** gpit : R/W; bitpos: [27:24]; default: 0;
+         *  GPI Type When set, this bit indicates that the corresponding GPIS is of latchedlow
+         *  _LL_ type When reset, this bit indicates that the corresponding GPIS is of
+         *  latchedhigh _LH_ type The number of bits available in this field depend on the GP
+         *  Input Signal Width option Other bits are not used _reserved and always reset_
+         */
+        uint32_t gpit:4;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gmac_register56_generalpurposeioregister_reg_t;
+
+/** Type of register256_layer3andlayer4controlregister0 register
+ *  Controls the operations of the Layer 3 and Layer 4 frame filtering
+ */
+typedef union {
+    struct {
+        /** l3pen0 : R/W; bitpos: [0]; default: 0;
+         *  Layer 3 Protocol Enable When set, this bit indicates that the Layer 3 IP Source or
+         *  Destination Address matching is enabled for the IPv6 frames When reset, this bit
+         *  indicates that the Layer 3 IP Source or Destination Address matching is enabled for
+         *  the IPv4 frames The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit
+         *  is set high
+         */
+        uint32_t l3pen0:1;
+        uint32_t reserved_1:1;
+        /** l3sam0 : R/W; bitpos: [2]; default: 0;
+         *  Layer 3 IP SA Match Enable When set, this bit indicates that the Layer 3 IP Source
+         *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+         *  Source Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should set
+         *  either this bit or Bit 4 _L3DAM0_ because either IPv6 SA or DA can be checked for
+         *  filtering
+         */
+        uint32_t l3sam0:1;
+        /** l3saim0 : R/W; bitpos: [3]; default: 0;
+         *  Layer 3 IP SA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+         *  Source Address field is enabled for inverse matching When reset, this bit indicates
+         *  that the Layer 3 IP Source Address field is enabled for perfect matching This bit
+         *  is valid and applicable only when Bit 2 _L3SAM0_ is set high
+         */
+        uint32_t l3saim0:1;
+        /** l3dam0 : R/W; bitpos: [4]; default: 0;
+         *  Layer 3 IP DA Match Enable When set, this bit indicates that Layer 3 IP Destination
+         *  Address field is enabled for matching When reset, the MAC ignores the Layer 3 IP
+         *  Destination Address field for matching Note: When Bit 0 _L3PEN0_ is set, you should
+         *  set either this bit or Bit 2 _L3SAM0_ because either IPv6 DA or SA can be checked
+         *  for filtering
+         */
+        uint32_t l3dam0:1;
+        /** l3daim0 : R/W; bitpos: [5]; default: 0;
+         *  Layer 3 IP DA Inverse Match Enable When set, this bit indicates that the Layer 3 IP
+         *  Destination Address field is enabled for inverse matching When reset, this bit
+         *  indicates that the Layer 3 IP Destination Address field is enabled for perfect
+         *  matching This bit is valid and applicable only when Bit 4 _L3DAM0_ is set high
+         */
+        uint32_t l3daim0:1;
+        /** l3hsbm0 : R/W; bitpos: [10:6]; default: 0;
+         *  Layer 3 IP SA Higher Bits Match IPv4 Frames: This field contains the number of
+         *  lower bits of IP Source Address that are masked for matching in the IPv4 frames The
+         *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+         *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+         *  Frames: This field contains Bits [4:0] of the field that indicates the number of
+         *  higher bits of IP Source or Destination Address matched in the IPv6 frames This
+         *  field is valid and applicable only if L3DAM0 or L3SAM0 is set high
+         */
+        uint32_t l3hsbm0:5;
+        /** l3hdbm0 : R/W; bitpos: [15:11]; default: 0;
+         *  Layer 3 IP DA Higher Bits Match IPv4 Frames: This field contains the number of
+         *  higher bits of IP Destination Address that are matched in the IPv4 frames The
+         *  following list describes the values of this field: 0: No bits are masked 1: LSb[0]
+         *  is masked 2: Two LSbs [1:0] are masked  31: All bits except MSb are masked IPv6
+         *  Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which
+         *  indicate the number of lower bits of IP Source or Destination Address that are
+         *  masked in the IPv6 frames The following list describes the concatenated values of
+         *  the L3HDBM0[1:0] and L3HSBM0 bits: 0: No bits are masked 1: LSb[0] is masked 2: Two
+         *  LSbs [1:0] are masked … 127: All bits except MSb are masked This field is valid and
+         *  applicable only if L3DAM0 or L3SAM0 is set high
+         */
+        uint32_t l3hdbm0:5;
+        /** l4pen0 : R/W; bitpos: [16]; default: 0;
+         *  Layer 4 Protocol Enable When set, this bit indicates that the Source and
+         *  Destination Port number fields for UDP frames are used for matching When reset,
+         *  this bit indicates that the Source and Destination Port number fields for TCP
+         *  frames are used for matching The Layer 4 matching is done only when either L4SPM0
+         *  or L4DPM0 bit is set high
+         */
+        uint32_t l4pen0:1;
+        uint32_t reserved_17:1;
+        /** l4spm0 : R/W; bitpos: [18]; default: 0;
+         *  Layer 4 Source Port Match Enable When set, this bit indicates that the Layer 4
+         *  Source Port number field is enabled for matching When reset, the MAC ignores the
+         *  Layer 4 Source Port number field for matching
+         */
+        uint32_t l4spm0:1;
+        /** l4spim0 : R/W; bitpos: [19]; default: 0;
+         *  Layer 4 Source Port Inverse Match Enable When set, this bit indicates that the
+         *  Layer 4 Source Port number field is enabled for inverse matching When reset, this
+         *  bit indicates that the Layer 4 Source Port number field is enabled for perfect
+         *  matching This bit is valid and applicable only when Bit 18 _L4SPM0_ is set high
+         */
+        uint32_t l4spim0:1;
+        /** l4dpm0 : R/W; bitpos: [20]; default: 0;
+         *  Layer 4 Destination Port Match Enable When set, this bit indicates that the Layer 4
+         *  Destination Port number field is enabled for matching When reset, the MAC ignores
+         *  the Layer 4 Destination Port number field for matching
+         */
+        uint32_t l4dpm0:1;
+        /** l4dpim0 : R/W; bitpos: [21]; default: 0;
+         *  Layer 4 Destination Port Inverse Match Enable When set, this bit indicates that the
+         *  Layer 4 Destination Port number field is enabled for inverse matching When reset,
+         *  this bit indicates that the Layer 4 Destination Port number field is enabled for
+         *  perfect matching This bit is valid and applicable only when Bit 20 _L4DPM0_ is set
+         *  high
+         */
+        uint32_t l4dpim0:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} gmac_register256_layer3andlayer4controlregister0_reg_t;
+
+/** Type of register257_layer4addressregister0 register
+ *  Layer 4 Port number field It contains the 16bit Source and Destination Port numbers
+ *  of the TCP or UDP frame
+ */
+typedef union {
+    struct {
+        /** l4sp0 : R/W; bitpos: [15:0]; default: 0;
+         *  Layer 4 Source Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20 _L4DPM0_
+         *  is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this field
+         *  contains the value to be matched with the TCP Source Port Number field in the IPv4
+         *  or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in Register 256
+         *  _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+         *  matched with the UDP Source Port Number field in the IPv4 or IPv6 frames
+         */
+        uint32_t l4sp0:16;
+        /** l4dp0 : R/W; bitpos: [31:16]; default: 0;
+         *  Layer 4 Destination Port Number Field When Bit 16 _L4PEN0_ is reset and Bit 20
+         *  _L4DPM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+         *  field contains the value to be matched with the TCP Destination Port Number field
+         *  in the IPv4 or IPv6 frames When Bit 16 _L4PEN0_ and Bit 20 _L4DPM0_ are set in
+         *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this field contains the
+         *  value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6
+         *  frames
+         */
+        uint32_t l4dp0:16;
+    };
+    uint32_t val;
+} gmac_register257_layer4addressregister0_reg_t;
+
+/** Type of register260_layer3address0register0 register
+ *  Layer 3 Address field For IPv4 frames, it contains the 32bit IP Source Address
+ *  field For IPv6 frames, it contains Bits [31:0] of the 128bit IP Source Address or
+ *  Destination Address field
+ */
+typedef union {
+    struct {
+        /** l3a00 : R/W; bitpos: [31:0]; default: 0;
+         *  Layer 3 Address 0 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+         *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+         *  matched with Bits [31:0] of the IP Source Address field in the IPv6 frames When Bit
+         *  0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4 Control
+         *  Register 0_, this field contains the value to be matched with Bits [31:0] of the IP
+         *  Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset and Bit 2
+         *  _L3SAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_, this
+         *  field contains the value to be matched with the IP Source Address field in the IPv4
+         *  frames
+         */
+        uint32_t l3a00:32;
+    };
+    uint32_t val;
+} gmac_register260_layer3address0register0_reg_t;
+
+/** Type of register261_layer3address1register0 register
+ *  Layer 3 Address 1 field For IPv4 frames, it contains the 32bit IP Destination
+ *  Address field For IPv6 frames, it contains Bits [63:32] of the 128bit IP Source
+ *  Address or Destination Address field
+ */
+typedef union {
+    struct {
+        /** l3a10 : R/W; bitpos: [31:0]; default: 0;
+         *  Layer 3 Address 1 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+         *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+         *  matched with Bits [63:32] of the IP Source Address field in the IPv6 frames When
+         *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+         *  Control Register 0_, this field contains the value to be matched with Bits [63:32]
+         *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+         *  and Bit 4 _L3DAM0_ is set in Register 256 _Layer 3 and Layer 4 Control Register 0_,
+         *  this field contains the value to be matched with the IP Destination Address field
+         *  in the IPv4 frames
+         */
+        uint32_t l3a10:32;
+    };
+    uint32_t val;
+} gmac_register261_layer3address1register0_reg_t;
+
+/** Type of register262_layer3address2register0 register
+ *  Layer 3 Address 2 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [95:64] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+typedef union {
+    struct {
+        /** l3a20 : R/W; bitpos: [31:0]; default: 0;
+         *  Layer 3 Address 2 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+         *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+         *  matched with Bits [95:64] of the IP Source Address field in the IPv6 frames When
+         *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+         *  Control Register 0_, this field contains value to be matched with Bits [95:64] of
+         *  the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset in
+         *  Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+         */
+        uint32_t l3a20:32;
+    };
+    uint32_t val;
+} gmac_register262_layer3address2register0_reg_t;
+
+/** Type of register263_layer3address3register0 register
+ *  Layer 3 Address 3 field This register is reserved for IPv4 frames For IPv6 frames,
+ *  it contains Bits [127:96] of the 128bit IP Source Address or Destination Address
+ *  field
+ */
+typedef union {
+    struct {
+        /** l3a30 : R/W; bitpos: [31:0]; default: 0;
+         *  Layer 3 Address 3 Field When Bit 0 _L3PEN0_ and Bit 2 _L3SAM0_ are set in Register
+         *  256 _Layer 3 and Layer 4 Control Register 0_, this field contains the value to be
+         *  matched with Bits [127:96] of the IP Source Address field in the IPv6 frames When
+         *  Bit 0 _L3PEN0_ and Bit 4 _L3DAM0_ are set in Register 256 _Layer 3 and Layer 4
+         *  Control Register 0_, this field contains the value to be matched with Bits [127:96]
+         *  of the IP Destination Address field in the IPv6 frames When Bit 0 _L3PEN0_ is reset
+         *  in Register 256 _Layer 3 and Layer 4 Control Register 0_, this register is not used
+         */
+        uint32_t l3a30:32;
+    };
+    uint32_t val;
+} gmac_register263_layer3address3register0_reg_t;
+
+/** Type of register320_hashtableregister0 register
+ *  This register contains the first 32 bits of the hash table when the width of the
+ *  Hash table is 128 bits or 256 bits
+ */
+typedef union {
+    struct {
+        /** ht31t0 : R/W; bitpos: [31:0]; default: 0;
+         *  First 32 bits of Hash Table This field contains the first 32 Bits _31:0_ of the
+         *  Hash table Note Registers 321 through 327 are similar to Register 320 _Hash Table
+         *  Register 0_ Registers 324 through 327 are present only when you select the 256bit
+         *  Hash table during core configuration
+         */
+        uint32_t ht31t0:32;
+    };
+    uint32_t val;
+} gmac_register320_hashtableregister0_reg_t;
+
+/** Type of register353_vlantaginclusionorreplacementregister register
+ *  This register contains the VLAN tag for insertion into or replacement in the
+ *  transmit frames
+ */
+typedef union {
+    struct {
+        /** vlt : R/W; bitpos: [15:0]; default: 0;
+         *  VLAN Tag for Transmit Frames This field contains the value of the VLAN tag to be
+         *  inserted or replaced The value must only be changed when the transmit lines are
+         *  inactive or during the initialization phase Bits[15:13] are the User Priority, Bit
+         *  12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field
+         */
+        uint32_t vlt:16;
+        /** vlc : R/W; bitpos: [17:16]; default: 0;
+         *  VLAN Tag Control in Transmit Frames 2’b00: No VLAN tag deletion, insertion, or
+         *  replacement 2’b01: VLAN tag deletion The MAC removes the VLAN type _bytes 13 and
+         *  14_ and VLAN tag _bytes 15 and 16_ of all transmitted frames with VLAN tags 2’b10:
+         *  VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after
+         *  inserting the Type value _0x8100/0x88a8_ in bytes 13 and 14 This operation is
+         *  performed on all transmitted frames, irrespective of whether they already have a
+         *  VLAN tag 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all
+         *  VLANtype transmitted frames _Bytes 13 and 14 are 0x8100/0x88a8_ Note: Changes to
+         *  this field take effect only on the start of a frame If you write this register
+         *  field when a frame is being transmitted, only the subsequent frame can use the
+         *  updated value, that is, the current frame does not use the updated value
+         */
+        uint32_t vlc:2;
+        /** vlp : R/W; bitpos: [18]; default: 0;
+         *  VLAN Priority Control When this bit is set, the control Bits [17:16] are used for
+         *  VLAN deletion, insertion, or replacement When this bit is reset, the
+         *  mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored
+         */
+        uint32_t vlp:1;
+        /** csvl : R/W; bitpos: [19]; default: 0;
+         *  CVLAN or SVLAN When this bit is set, SVLAN type _0x88A8_ is inserted or replaced in
+         *  the 13th and 14th bytes of transmitted frames When this bit is reset, CVLAN type
+         *  _0x8100_ is inserted or replaced in the transmitted frames
+         */
+        uint32_t csvl:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gmac_register353_vlantaginclusionorreplacementregister_reg_t;
+
+/** Type of register354_vlanhashtableregister register
+ *  This register contains the VLAN hash table
+ */
+typedef union {
+    struct {
+        /** vlht : R/W; bitpos: [15:0]; default: 0;
+         *  VLAN Hash Table This field contains the 16bit VLAN Hash Table
+         */
+        uint32_t vlht:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register354_vlanhashtableregister_reg_t;
+
+/** Type of register544_macaddress32highregister register
+ *  Contains the higher 16 bits of the 33rd MAC address This register is present only
+ *  when Enable Additional 32 MAC Address Registers is selected in coreConsultant _See
+ *  Table 78_
+ */
+typedef union {
+    struct {
+        /** addrhi : R/W; bitpos: [15:0]; default: 65535;
+         *  MAC Address32 [47:32] This field contains the upper 16 bits _47:32_ of the 33rd
+         *  6byte MAC address
+         */
+        uint32_t addrhi:16;
+        uint32_t reserved_16:15;
+        /** ae : R/W; bitpos: [31]; default: 0;
+         *  Address Enable When this bit is set, the Address filter module uses the 33rd MAC
+         *  address for perfect filtering When reset, the address filter module ignores the
+         *  address for filtering
+         */
+        uint32_t ae:1;
+    };
+    uint32_t val;
+} gmac_register544_macaddress32highregister_reg_t;
+
+
+/** Group: IEEE 1588 Timestamp register */
+/** Type of register448_timestampcontrolregister register
+ *  Controls the timestamp generation and update logic This register is present only
+ *  when IEEE1588 timestamping is enabled during coreConsultant configuration
+ */
+typedef union {
+    struct {
+        /** tsena : R/W; bitpos: [0]; default: 0;
+         *  Timestamp Enable When set, the timestamp is added for the transmit and receive
+         *  frames When disabled, timestamp is not added for the transmit and receive frames
+         *  and the Timestamp Generator is also suspended You need to initialize the Timestamp
+         *  _system time_ after enabling this mode On the receive side, the MAC processes the
+         *  1588 frames only if this bit is set
+         */
+        uint32_t tsena:1;
+        /** tscfupdt : R/W; bitpos: [1]; default: 0;
+         *  Timestamp Fine or Coarse Update When set, this bit indicates that the system times
+         *  update should be done using the fine update method When reset, it indicates the
+         *  system timestamp update should be done using the Coarse method
+         */
+        uint32_t tscfupdt:1;
+        /** tsinit : R/W1S; bitpos: [2]; default: 0;
+         *  Timestamp Initialize When set, the system time is initialized _overwritten_ with
+         *  the value specified in the Register 452 _System Time  Seconds Update Register_ and
+         *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+         *  zero before updating it This bit is reset when the initialization is complete The
+         *  “Timestamp Higher Word” register _if enabled during core configuration_ can only be
+         *  initialized
+         */
+        uint32_t tsinit:1;
+        /** tsupdt : R/W1S; bitpos: [3]; default: 0;
+         *  Timestamp Update When set, the system time is updated _added or subtracted_ with
+         *  the value specified in Register 452 _System Time  Seconds Update Register_ and
+         *  Register 453 _System Time  Nanoseconds Update Register_ This bit should be read
+         *  zero before updating it This bit is reset when the update is completed in hardware
+         *  The “Timestamp Higher Word” register _if enabled during core configuration_ is not
+         *  updated
+         */
+        uint32_t tsupdt:1;
+        /** tstrig : R/W1S; bitpos: [4]; default: 0;
+         *  Timestamp Interrupt Trigger Enable When set, the timestamp interrupt is generated
+         *  when the System Time becomes greater than the value written in the Target Time
+         *  register This bit is reset after the generation of the Timestamp Trigger Interrupt
+         */
+        uint32_t tstrig:1;
+        /** tsaddreg : R/W1S; bitpos: [5]; default: 0;
+         *  Addend Reg Update When set, the content of the Timestamp Addend register is updated
+         *  in the PTP block for fine correction This is cleared when the update is completed
+         *  This register bit should be zero before setting it
+         */
+        uint32_t tsaddreg:1;
+        uint32_t reserved_6:2;
+        /** tsenall : R/W; bitpos: [8]; default: 0;
+         *  Enable Timestamp for All Frames When set, the timestamp snapshot is enabled for all
+         *  frames received by the MAC
+         */
+        uint32_t tsenall:1;
+        /** tsctrlssr : R/W; bitpos: [9]; default: 0;
+         *  Timestamp Digital or Binary Rollover Control When set, the Timestamp Low register
+         *  rolls over after 0x3B9A_C9FF value _that is, 1 nanosecond accuracy_ and increments
+         *  the timestamp _High_ seconds When reset, the rollover value of subsecond register
+         *  is 0x7FFF_FFFF The subsecond increment has to be programmed correctly depending on
+         *  the PTP reference clock frequency and the value of this bit
+         */
+        uint32_t tsctrlssr:1;
+        /** tsver2ena : R/W; bitpos: [10]; default: 0;
+         *  Enable PTP packet Processing for Version 2 Format When set, the PTP packets are
+         *  processed using the 1588 version 2 format Otherwise, the PTP packets are processed
+         *  using the version 1 format The IEEE 1588 Version 1 and Version 2 format are
+         *  described in “PTP Processing and Control” on page 155
+         */
+        uint32_t tsver2ena:1;
+        /** tsipena : R/W; bitpos: [11]; default: 0;
+         *  Enable Processing of PTP over Ethernet Frames When set, the MAC receiver processes
+         *  the PTP packets encapsulated directly in the Ethernet frames When this bit is
+         *  clear, the MAC ignores the PTP over Ethernet packets
+         */
+        uint32_t tsipena:1;
+        /** tsipv6ena : R/W; bitpos: [12]; default: 0;
+         *  Enable Processing of PTP Frames Sent over IPv6UDP When set, the MAC receiver
+         *  processes PTP packets encapsulated in UDP over IPv6 packets When this bit is clear,
+         *  the MAC ignores the PTP transported over UDPIPv6 packets
+         */
+        uint32_t tsipv6ena:1;
+        /** tsipv4ena : R/W; bitpos: [13]; default: 1;
+         *  Enable Processing of PTP Frames Sent over IPv4UDP When set, the MAC receiver
+         *  processes the PTP packets encapsulated in UDP over IPv4 packets When this bit is
+         *  clear, the MAC ignores the PTP transported over UDPIPv4 packets This bit is set by
+         *  default
+         */
+        uint32_t tsipv4ena:1;
+        /** tsevntena : R/W; bitpos: [14]; default: 0;
+         *  Enable Timestamp Snapshot for Event Messages When set, the timestamp snapshot is
+         *  taken only for event messages _SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp_ When
+         *  reset, the snapshot is taken for all messages except Announce, Management, and
+         *  Signaling For more information about the timestamp snapshots, see Table 670 on page
+         *  462
+         */
+        uint32_t tsevntena:1;
+        /** tsmstrena : R/W; bitpos: [15]; default: 0;
+         *  Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken
+         *  only for the messages relevant to the master node Otherwise, the snapshot is taken
+         *  for the messages relevant to the slave node
+         */
+        uint32_t tsmstrena:1;
+        /** snaptypsel : R/W; bitpos: [17:16]; default: 0;
+         *  Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide
+         *  the set of PTP packet types for which snapshot needs to be taken The encoding is
+         *  given in Table 670 on page 462
+         */
+        uint32_t snaptypsel:2;
+        /** tsenmacaddr : R/W; bitpos: [18]; default: 0;
+         *  Enable MAC address for PTP Frame Filtering When set, the DA MAC address _that
+         *  matches any MAC Address register_ is used to filter the PTP frames when PTP is
+         *  directly sent over Ethernet
+         */
+        uint32_t tsenmacaddr:1;
+        uint32_t reserved_19:5;
+        /** atsfc : R/W1S; bitpos: [24]; default: 0;
+         *  Auxiliary Snapshot FIFO Clear When set, it resets the pointers of the Auxiliary
+         *  Snapshot FIFO This bit is cleared when the pointers are reset and the FIFO is empty
+         *  When this bit is high, auxiliary snapshots get stored in the FIFO This bit is
+         *  reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during
+         *  core configuration
+         */
+        uint32_t atsfc:1;
+        /** atsen0 : R/W; bitpos: [25]; default: 0;
+         *  Auxiliary Snapshot 0 Enable This field controls capturing the Auxiliary Snapshot
+         *  Trigger 0 When this bit is set, the Auxiliary snapshot of event on
+         *  ptp_aux_trig_i[0] input is enabled When this bit is reset, the events on this input
+         *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+         *  is not selected during core configuration
+         */
+        uint32_t atsen0:1;
+        /** atsen1 : R/W; bitpos: [26]; default: 0;
+         *  Auxiliary Snapshot 1 Enable This field controls capturing the Auxiliary Snapshot
+         *  Trigger 1 When this bit is set, the Auxiliary snapshot of event on
+         *  ptp_aux_trig_i[1] input is enabled When this bit is reset, the events on this input
+         *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+         *  is not selected during core configuration or the selected number in the Number of
+         *  IEEE 1588 Auxiliary Snapshot Inputs option is less than two
+         */
+        uint32_t atsen1:1;
+        /** atsen2 : R/W; bitpos: [27]; default: 0;
+         *  Auxiliary Snapshot 2 Enable This field controls capturing the Auxiliary Snapshot
+         *  Trigger 2 When this bit is set, the Auxiliary snapshot of event on
+         *  ptp_aux_trig_i[2] input is enabled When this bit is reset, the events on this input
+         *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+         *  is not selected during core configuration or the selected number in the Number of
+         *  IEEE 1588 Auxiliary Snapshot Inputs option is less than three
+         */
+        uint32_t atsen2:1;
+        /** atsen3 : R/W; bitpos: [28]; default: 0;
+         *  Auxiliary Snapshot 3 Enable This field controls capturing the Auxiliary Snapshot
+         *  Trigger 3 When this bit is set, the Auxiliary snapshot of event on
+         *  ptp_aux_trig_i[3] input is enabled When this bit is reset, the events on this input
+         *  are ignored This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option
+         *  is not selected during core configuration or the selected number in the Number of
+         *  IEEE 1588 Auxiliary Snapshot Inputs option is less than four
+         */
+        uint32_t atsen3:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register448_timestampcontrolregister_reg_t;
+
+/** Type of register449_subsecondincrementregister register
+ *  Contains the 8bit value by which the SubSecond register is incremented This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+typedef union {
+    struct {
+        /** ssinc : R/W; bitpos: [7:0]; default: 0;
+         *  Subsecond Increment Value The value programmed in this field is accumulated every
+         *  clock cycle _of clk_ptp_i_ with the contents of the subsecond register For example,
+         *  when PTP clock is 50 MHz _period is 20 ns_, you should program 20 _0x14_ when the
+         *  System Time Nanoseconds register has an accuracy of 1 ns [Bit 9 _TSCTRLSSR_ is set
+         *  in Register 448 _Timestamp Control Register_] When TSCTRLSSR is clear, the
+         *  Nanoseconds register has a resolution of ~0465ns In this case, you should program a
+         *  value of 43 _0x2B_ that is derived by 20ns/0465
+         */
+        uint32_t ssinc:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gmac_register449_subsecondincrementregister_reg_t;
+
+/** Type of register450_systemtimesecondsregister register
+ *  Contains the lower 32 bits of the seconds field of the system time This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input
+ */
+typedef union {
+    struct {
+        /** tss_ro : RO; bitpos: [31:0]; default: 0;
+         *  Timestamp Second The value in this field indicates the current value in seconds of
+         *  the System Time maintained by the MAC
+         */
+        uint32_t tss_ro:32;
+    };
+    uint32_t val;
+} gmac_register450_systemtimesecondsregister_reg_t;
+
+/** Type of register451_systemtimenanosecondsregister register
+ *  Contains 32 bits of the nanoseconds field of the system time This register is only
+ *  present when IEEE1588 timestamping is enabled without an external timestamp input
+ */
+typedef union {
+    struct {
+        /** tsss_ro : RO; bitpos: [30:0]; default: 0;
+         *  Timestamp Sub Seconds The value in this field has the sub second representation of
+         *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+         *  _Timestamp Control Register_, each bit represents 1 ns and the maximum value is
+         *  0x3B9A_C9FF, after which it rollsover to zero
+         */
+        uint32_t tsss_ro:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register451_systemtimenanosecondsregister_reg_t;
+
+/** Type of register452_systemtimesecondsupdateregister register
+ *  Contains the lower 32 bits of the seconds field to be written to, added to, or
+ *  subtracted from the System Time value This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+typedef union {
+    struct {
+        /** tss : R/W; bitpos: [31:0]; default: 0;
+         *  TIMESTAMP SECOND THE VALUE IN THIS FIELD INDICATES THE TIME IN SECONDS TO BE
+         *  INITIALIZED OR ADDED TO THE SYSTEM TIME
+         */
+        uint32_t tss:32;
+    };
+    uint32_t val;
+} gmac_register452_systemtimesecondsupdateregister_reg_t;
+
+/** Type of register453_systemtimenanosecondsupdateregister register
+ *  Contains 32 bits of the nanoseconds field to be written to, added to, or subtracted
+ *  from the System Time value This register is only present when IEEE1588 timestamping
+ *  is enabled without an external timestamp input
+ */
+typedef union {
+    struct {
+        /** tsss : R/W; bitpos: [30:0]; default: 0;
+         *  Timestamp Sub Seconds The value in this field has the sub second representation of
+         *  time, with an accuracy of 046 ns When Bit 9 _TSCTRLSSR_ is set in Register 448
+         *  _Timestamp Control Register_, each bit represents 1 ns and the programmed value
+         *  should not exceed 0x3B9A_C9FF
+         */
+        uint32_t tsss:31;
+        /** addsub : R/W; bitpos: [31]; default: 0;
+         *  Add or Subtract Time When this bit is set, the time value is subtracted with the
+         *  contents of the update register When this bit is reset, the time value is added
+         *  with the contents of the update register
+         */
+        uint32_t addsub:1;
+    };
+    uint32_t val;
+} gmac_register453_systemtimenanosecondsupdateregister_reg_t;
+
+/** Type of register454_timestampaddendregister register
+ *  This register is used by the software to readjust the clock frequency linearly to
+ *  match the master clock frequency This register is only present when IEEE1588
+ *  timestamping is enabled without an external timestamp input
+ */
+typedef union {
+    struct {
+        /** tsar : R/W; bitpos: [31:0]; default: 0;
+         *  Timestamp Addend Register This field indicates the 32bit time value to be added to
+         *  the Accumulator register to achieve time synchronization
+         */
+        uint32_t tsar:32;
+    };
+    uint32_t val;
+} gmac_register454_timestampaddendregister_reg_t;
+
+/** Type of register455_targettimesecondsregister register
+ *  Contains the higher 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+typedef union {
+    struct {
+        /** tstr : R/W; bitpos: [31:0]; default: 0;
+         *  Target Time Seconds Register This register stores the time in seconds When the
+         *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+         *  Bits [6:5] of Register 459 _PPS Control Register_, the MAC starts or stops the PPS
+         *  signal output and generates an interrupt _if enabled_
+         */
+        uint32_t tstr:32;
+    };
+    uint32_t val;
+} gmac_register455_targettimesecondsregister_reg_t;
+
+/** Type of register456_targettimenanosecondsregister register
+ *  Contains the lower 32 bits of time to be compared with the system time for
+ *  interrupt event generation or to start the PPS signal output generation This
+ *  register is present only when IEEE1588 timestamping is enabled without an external
+ *  timestamp input
+ */
+typedef union {
+    struct {
+        /** ttslo : R/W; bitpos: [30:0]; default: 0;
+         *  Target Timestamp Low Register This register stores the time in _signed_ nanoseconds
+         *  When the value of the timestamp matches the both Target Timestamp registers, then
+         *  based on the TRGTMODSEL0 field _Bits [6:5]_ in Register 459 _PPS Control Register_,
+         *  the MAC starts or stops the PPS signal output and generates an interrupt _if
+         *  enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9 _TSCTRLSSR_ is set in
+         *  Register 448 _Timestamp Control Register_ The actual start or stop time of the PPS
+         *  signal output may have an error margin up to one unit of subsecond increment value
+         */
+        uint32_t ttslo:31;
+        /** trgtbusy : R/W1S; bitpos: [31]; default: 0;
+         *  Target Time Register Busy The MAC sets this bit when the PPSCMD field _Bit [3:0]_
+         *  in Register 459 _PPS Control Register_ is programmed to 010 or 011 Programming the
+         *  PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time
+         *  Registers to the PTP clock domain The MAC clears this bit after synchronizing the
+         *  Target Time Registers to the PTP clock domain The application must not update the
+         *  Target Time Registers when this bit is read as 1 Otherwise, the synchronization of
+         *  the previous programmed time gets corrupted This bit is reserved when the Enable
+         *  Flexible PulsePerSecond Output feature is not selected
+         */
+        uint32_t trgtbusy:1;
+    };
+    uint32_t val;
+} gmac_register456_targettimenanosecondsregister_reg_t;
+
+/** Type of register457_systemtimehigherwordsecondsregister register
+ *  Contains the most significant 16bits of the timestamp seconds value This register
+ *  is optional and can be selected using the parameter mentioned in “IEEE 1588
+ *  Timestamp Block” on page 492
+ */
+typedef union {
+    struct {
+        /** tshwr : R/W; bitpos: [15:0]; default: 0;
+         *  Timestamp Higher Word Register This field contains the most significant 16bits of
+         *  the timestamp seconds value This register is optional and can be selected using the
+         *  Enable IEEE 1588 Higher Word Register option during core configuration The register
+         *  is directly written to initialize the value This register is incremented when there
+         *  is an overflow from the 32bits of the System Time  Seconds register
+         */
+        uint32_t tshwr:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gmac_register457_systemtimehigherwordsecondsregister_reg_t;
+
+/** Type of register458_timestampstatusregister register
+ *  Contains the PTP status This register is available only when the advanced IEEE 1588
+ *  timestamp feature is selected
+ */
+typedef union {
+    struct {
+        /** tssovf : R/W; bitpos: [0]; default: 0;
+         *  Timestamp Seconds Overflow When set, this bit indicates that the seconds value of
+         *  the timestamp _when supporting version 2 format_ has overflowed beyond 32’hFFFF_FFFF
+         */
+        uint32_t tssovf:1;
+        /** tstargt : R/W; bitpos: [1]; default: 0;
+         *  Timestamp Target Time Reached When set, this bit indicates that the value of system
+         *  time is greater than or equal to the value specified in the Register 455 _Target
+         *  Time Seconds Register_ and Register 456 _Target Time Nanoseconds Register_
+         */
+        uint32_t tstargt:1;
+        /** auxtstrig : R/W; bitpos: [2]; default: 0;
+         *  Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary
+         *  snapshot is written to the FIFO This bit is valid only if the Enable IEEE 1588
+         *  Auxiliary Snapshot feature is selected
+         */
+        uint32_t auxtstrig:1;
+        /** tstrgterr : R/W; bitpos: [3]; default: 0;
+         *  Timestamp Target Time Error This bit is set when the target time, being programmed
+         *  in Register 455 and Register 456, is already elapsed This bit is cleared when read
+         *  by the application
+         */
+        uint32_t tstrgterr:1;
+        /** tstargt1 : R/W; bitpos: [4]; default: 0;
+         *  Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates
+         *  that the value of system time is greater than or equal to the value specified in
+         *  Register 480 _PPS1 Target Time High Register_ and Register 481 _PPS1 Target Time
+         *  Low Register_
+         */
+        uint32_t tstargt1:1;
+        /** tstrgterr1 : R/W; bitpos: [5]; default: 0;
+         *  Timestamp Target Time Error This bit is set when the target time, being programmed
+         *  in Register 480 and Register 481, is already elapsed This bit is cleared when read
+         *  by the application
+         */
+        uint32_t tstrgterr1:1;
+        /** tstargt2 : R/W; bitpos: [6]; default: 0;
+         *  Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates
+         *  that the value of system time is greater than or equal to the value specified in
+         *  Register 488 _PPS2 Target Time High Register_ and Register 489 _PPS2 Target Time
+         *  Low Register_
+         */
+        uint32_t tstargt2:1;
+        /** tstrgterr2 : R/W; bitpos: [7]; default: 0;
+         *  Timestamp Target Time Error This bit is set when the target time, being programmed
+         *  in Register 488 and Register 489, is already elapsed This bit is cleared when read
+         *  by the application
+         */
+        uint32_t tstrgterr2:1;
+        /** tstargt3 : R/W; bitpos: [8]; default: 0;
+         *  Timestamp Target Time Reached for Target Time PPS3 When set, this bit indicates
+         *  that the value of system time is greater than or equal to the value specified in
+         *  Register 496 _PPS3 Target Time High Register_ and Register 497 _PPS3 Target Time
+         *  Low Register_
+         */
+        uint32_t tstargt3:1;
+        /** tstrgterr3 : R/W; bitpos: [9]; default: 0;
+         *  Timestamp Target Time Error This bit is set when the target time, being programmed
+         *  in Register 496 and Register 497, is already elapsed This bit is cleared when read
+         *  by the application
+         */
+        uint32_t tstrgterr3:1;
+        uint32_t reserved_10:6;
+        /** atsstn : R/W; bitpos: [19:16]; default: 0;
+         *  Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
+         *  trigger inputs for which the timestamp available in the Auxiliary Snapshot Register
+         *  is applicable When more than one bit is set at the same time, it means that
+         *  corresponding auxiliary triggers were sampled at the same clock These bits are
+         *  applicable only if the number of Auxiliary snapshots is more than one One bit is
+         *  assigned for each trigger as shown in the following list: Bit 16: Auxiliary trigger
+         *  0 Bit 17: Auxiliary trigger 1 Bit 18: Auxiliary trigger 2 Bit 19: Auxiliary trigger
+         *  3 The software can read this register to find the triggers that are set when the
+         *  timestamp is taken
+         */
+        uint32_t atsstn:4;
+        uint32_t reserved_20:4;
+        /** atsstm : RO; bitpos: [24]; default: 0;
+         *  Auxiliary Timestamp Snapshot Trigger Missed
+         */
+        uint32_t atsstm:1;
+        /** atsns : RO; bitpos: [29:25]; default: 0;
+         *  Number of Auxiliary Timestamp Snapshots This field indicates the number of
+         *  Snapshots available in the FIFO A value equal to the selected depth of FIFO _4, 8,
+         *  or 16_ indicates that the Auxiliary Snapshot FIFO is full These bits are cleared
+         *  _to 00000_ when the Auxiliary snapshot FIFO clear bit is set This bit is valid only
+         *  if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration
+         */
+        uint32_t atsns:5;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gmac_register458_timestampstatusregister_reg_t;
+
+/** Type of register459_ppscontrolregister register
+ *  This register is used to control the interval of the PPS signal output This
+ *  register is available only when the advanced IEEE 1588 timestamp feature is selected
+ */
+typedef union {
+    struct {
+        /** ppsctrl0 : R/W1S; bitpos: [3:0]; default: 0;
+         *  PPSCTRL0: PPS0 Output Frequency Control This field controls the frequency of the
+         *  PPS0 output _ptp_pps_o[0]_ signal The default value of PPSCTRL is 0000, and the PPS
+         *  output is 1 pulse _of width clk_ptp_i_ every second For other values of PPSCTRL,
+         *  the PPS output becomes a generated clock of following frequencies: 0001: The binary
+         *  rollover is 2 Hz, and the digital rollover is 1 Hz 0010: The binary rollover is 4
+         *  Hz, and the digital rollover is 2 Hz 0011: The binary rollover is 8 Hz, and the
+         *  digital rollover is 4 Hz 0100: The binary rollover is 16 Hz, and the digital
+         *  rollover is 8 Hz  1111: The binary rollover is 32768 KHz, and the digital rollover
+         *  is 16384 KHz Note: In the binary rollover mode, the PPS output _ptp_pps_o_ has a
+         *  duty cycle of 50 percent with these frequencies In the digital rollover mode, the
+         *  PPS output frequency is an average number The actual clock is of different
+         *  frequency that gets synchronized every second For example: When PPSCTRL = 0001, the
+         *  PPS _1 Hz_ has a low period of 537 ms and a high period of 463 ms When PPSCTRL =
+         *  0010, the PPS _2 Hz_ is a sequence of: 	One clock of 50 percent duty cycle and 537
+         *  ms period 	Second clock of 463 ms period _268 ms low and 195 ms high_ When PPSCTRL
+         *  = 0011, the PPS _4 Hz_ is a sequence of: 	Three clocks of 50 percent duty cycle and
+         *  268 ms period 	Fourth clock of 195 ms period _134 ms low and 61 ms high_ This
+         *  behavior is because of the nonlinear toggling of bits in the digital rollover mode
+         *  in Register 451 _System Time  Nanoseconds Register_ / PPSCMD0: Flexible PPS0 Output
+         *  _ptp_pps_o[0]_ Control Programming these bits with a nonzero value instructs the
+         *  MAC to initiate an event When the command is transferred or synchronized to the PTP
+         *  clock domain, these bits get cleared automatically The Software should ensure that
+         *  these bits are programmed only when they are “allzero” The following list describes
+         *  the values of PPSCMD0: 0000: No Command 0001: START Single Pulse This command
+         *  generates single pulse rising at the start point defined in Target Time Registers
+         *  _register 455 and 456_ and of a duration defined in the PPS0 Width Register 0010:
+         *  START Pulse Train This command generates the train of pulses rising at the start
+         *  point defined in the Target Time Registers and of a duration defined in the PPS0
+         *  Width Register and repeated at interval defined in the PPS Interval Register By
+         *  default, the PPS pulse train is freerunning unless stopped by 'STOP Pulse train at
+         *  time' or 'STOP Pulse Train immediately' commands 0011: Cancel START This command
+         *  cancels the START Single Pulse and START Pulse Train commands if the system time
+         *  has not crossed the programmed start time 0100: STOP Pulse train at time This
+         *  command stops the train of pulses initiated by the START Pulse Train command
+         *  _PPSCMD = 0010_ after the time programmed in the Target Time registers elapses
+         *  0101: STOP Pulse Train immediately This command immediately stops the train of
+         *  pulses initiated by the START Pulse Train command _PPSCMD = 0010_ 0110: Cancel STOP
+         *  Pulse train This command cancels the STOP pulse train at time command if the
+         *  programmed stop time has not elapsed The PPS pulse train becomes freerunning on the
+         *  successful execution of this command 01111111: Reserved
+         */
+        uint32_t ppsctrl0:4;
+        /** ppsen0 : R/W; bitpos: [4]; default: 0;
+         *  Flexible PPS Output Mode Enable When set low, Bits [3:0] function as PPSCTRL
+         *  _backward compatible_ When set high, Bits[3:0] function as PPSCMD
+         */
+        uint32_t ppsen0:1;
+        /** trgtmodsel0 : R/W; bitpos: [6:5]; default: 0;
+         *  Target Time Register Mode for PPS0 Output This field indicates the Target Time
+         *  registers _register 455 and 456_ mode for PPS0 output signal: 00: Indicates that
+         *  the Target Time registers are programmed only for generating the interrupt event
+         *  01: Reserved 10: Indicates that the Target Time registers are programmed for
+         *  generating the interrupt event and starting or stopping the generation of the PPS0
+         *  output signal 11: Indicates that the Target Time registers are programmed only for
+         *  starting or stopping the generation of the PPS0 output signal No interrupt is
+         *  asserted
+         */
+        uint32_t trgtmodsel0:2;
+        uint32_t reserved_7:1;
+        /** ppscmd1 : R/W1S; bitpos: [10:8]; default: 0;
+         *  Flexible PPS1 Output Control This field controls the flexible PPS1 output
+         *  _ptp_pps_o[1]_ signal This field is similar to PPSCMD0[2:0] in functionality
+         */
+        uint32_t ppscmd1:3;
+        uint32_t reserved_11:2;
+        /** trgtmodsel1 : R/W; bitpos: [14:13]; default: 0;
+         *  Target Time Register Mode for PPS1 Output This field indicates the Target Time
+         *  registers _register 480 and 481_ mode for PPS1 output signal This field is similar
+         *  to the TRGTMODSEL0 field
+         */
+        uint32_t trgtmodsel1:2;
+        uint32_t reserved_15:1;
+        /** ppscmd2 : R/W1S; bitpos: [18:16]; default: 0;
+         *  Flexible PPS2 Output Control This field controls the flexible PPS2 output
+         *  _ptp_pps_o[2]_ signal This field is similar to PPSCMD0[2:0] in functionality
+         */
+        uint32_t ppscmd2:3;
+        uint32_t reserved_19:2;
+        /** trgtmodsel2 : R/W; bitpos: [22:21]; default: 0;
+         *  Target Time Register Mode for PPS2 Output This field indicates the Target Time
+         *  registers _register 488 and 489_ mode for PPS2 output signal This field is similar
+         *  to the TRGTMODSEL0 field
+         */
+        uint32_t trgtmodsel2:2;
+        uint32_t reserved_23:1;
+        /** ppscmd3 : R/W1S; bitpos: [26:24]; default: 0;
+         *  Flexible PPS3 Output Control This field controls the flexible PPS3 output
+         *  _ptp_pps_o[3]_ signal This field is similar to PPSCMD0[2:0] in functionality
+         */
+        uint32_t ppscmd3:3;
+        uint32_t reserved_27:2;
+        /** trgtmodsel3 : R/W; bitpos: [30:29]; default: 0;
+         *  Target Time Register Mode for PPS3 Output This field indicates the Target Time
+         *  registers _register 496 and 497_ mode for PPS3 output signal This field is similar
+         *  to the TRGTMODSEL0 field
+         */
+        uint32_t trgtmodsel3:2;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register459_ppscontrolregister_reg_t;
+
+/** Type of register460_auxiliarytimestampnanosecondsregister register
+ *  Contains the lower 32 bits _nanoseconds field_ of the auxiliary timestamp register
+ */
+typedef union {
+    struct {
+        /** auxtslo : RO; bitpos: [30:0]; default: 0;
+         *  Contains the lower 31 bits _nanoseconds field_ of the auxiliary timestamp
+         */
+        uint32_t auxtslo:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register460_auxiliarytimestampnanosecondsregister_reg_t;
+
+/** Type of register461_auxiliarytimestampsecondsregister register
+ *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp register
+ */
+typedef union {
+    struct {
+        /** auxtshi : RO; bitpos: [31:0]; default: 0;
+         *  Contains the lower 32 bits of the Seconds field of the auxiliary timestamp
+         */
+        uint32_t auxtshi:32;
+    };
+    uint32_t val;
+} gmac_register461_auxiliarytimestampsecondsregister_reg_t;
+
+/** Type of register462_avmaccontrolregister register
+ *  Controls the AV traffic and queue management in the MAC Receiver This register is
+ *  present only when you select the AV feature in coreConsultant
+ */
+typedef union {
+    struct {
+        /** avt : R/W; bitpos: [15:0]; default: 0;
+         *  AV EtherType Value This field contains the value that is compared with the
+         *  EtherType field of the incoming _tagged or untagged_ Ethernet frame to detect an AV
+         *  packet
+         */
+        uint32_t avt:16;
+        /** avp : R/W; bitpos: [18:16]; default: 0;
+         *  AV Priority for Queuing The value programmed in these bits control the receive
+         *  channel _0, 1, or 2_ to which an AV packet with a given priority must be queued If
+         *  only Channel 1 receive path is enabled, the AV packets with priority value greater
+         *  than or equal to the programmed value are queued on Channel 1 and all other packets
+         *  are queued on Channel 0 If Channel 2 receive path is also enabled, the AV packets
+         *  with priority value greater than or equal to the programmed value are queued on
+         *  Channel 2 The AV packets with value less than the programmed value on Channel 1 and
+         *  all other packets are queued on Channel 0 These bits are applicable only if at
+         *  least one additional receive channel is selected in the AV mode
+         */
+        uint32_t avp:3;
+        /** vqe : R/W; bitpos: [19]; default: 0;
+         *  VLAN Tagged NonAV Packets Queueing Enable When this bit is set, the MAC also queues
+         *  nonAV VLAN tagged packets into the available channels according to the value of the
+         *  AVP bits This bit is reserved and readonly if Channel 1 and Channel 2 Receive paths
+         *  are not selected during core configuration
+         */
+        uint32_t vqe:1;
+        /** avcd : R/W; bitpos: [20]; default: 0;
+         *  AV Channel Disable When this bit is set, the MAC forwards all packets to the
+         *  default Channel 0 and the values programmed in the AVP, AVCH, and PTPCH fields are
+         *  ignored This bit is reserved and readonly if Channel 1 or Channel 2 receive paths
+         *  are not selected during core configuration
+         */
+        uint32_t avcd:1;
+        /** avch : R/W; bitpos: [22:21]; default: 0;
+         *  Channel for Queuing the AV Control Packets This field specifies the channel on
+         *  which the received untagged AV control packets are queued 00: Channel 0 01: Channel
+         *  1 10: Channel 2 11: Reserved These bits are reserved if the receive paths of
+         *  Channel 1 or Channel 2 are not enabled
+         */
+        uint32_t avch:2;
+        uint32_t reserved_23:1;
+        /** ptpch : R/W; bitpos: [25:24]; default: 0;
+         *  Channel for Queuing the PTP Packets This field specifies the channel on which the
+         *  untagged PTP packets, sent over the Ethernet payload and not over IPv4 or IPv6, are
+         *  queued 00: Channel 0 01: Channel 1 10: Channel 2 11: Reserved These bits are
+         *  reserved if the receive paths of Channel 1 or Channel 2 are not enabled
+         */
+        uint32_t ptpch:2;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} gmac_register462_avmaccontrolregister_reg_t;
+
+/** Type of register472_pps0intervalregister register
+ *  Contains the number of units of subsecond increment value between the rising edges
+ *  of PPS0 signal output This register is available only when the flexible PPS feature
+ *  is selected
+ */
+typedef union {
+    struct {
+        /** ppsint : R/W; bitpos: [31:0]; default: 0;
+         *  PPS0 Output Signal Interval These bits store the interval between the rising edges
+         *  of PPS0 signal output in terms of units of subsecond increment value You need to
+         *  program one value less than the required interval For example, if the PTP reference
+         *  clock is 50 MHz _period of 20ns_, and desired interval between rising edges of PPS0
+         *  signal output is 100ns _that is, five units of subsecond increment value_, then you
+         *  should program value 4 _5  1_ in this register
+         */
+        uint32_t ppsint:32;
+    };
+    uint32_t val;
+} gmac_register472_pps0intervalregister_reg_t;
+
+/** Type of register473_pps0widthregister register
+ *  Contains the number of units of subsecond increment value between the rising and
+ *  corresponding falling edges of PPS0 signal output This register is available only
+ *  when the flexible PPS feature is selected
+ */
+typedef union {
+    struct {
+        /** ppswidth : R/W; bitpos: [31:0]; default: 0;
+         *  PPS0 Output Signal Width These bits store the width between the rising edge and
+         *  corresponding falling edge of the PPS0 signal output in terms of units of subsecond
+         *  increment value You need to program one value less than the required interval For
+         *  example, if PTP reference clock is 50 MHz _period of 20ns_, and desired width
+         *  between the rising and corresponding falling edges of PPS0 signal output is 80ns
+         *  _that is, four units of subsecond increment value_, then you should program value 3
+         *  _4  1_ in this register Note: The value programmed in this register must be lesser
+         *  than the value programmed in Register 472 _PPS0 Interval Register_
+         */
+        uint32_t ppswidth:32;
+    };
+    uint32_t val;
+} gmac_register473_pps0widthregister_reg_t;
+
+/** Type of register480_pps1targettimesecondsregister register
+ *  Contains the higher 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+typedef union {
+    struct {
+        /** tstrh1 : R/W; bitpos: [31:0]; default: 0;
+         *  PPS1 Target Time Seconds Register This register stores the time in seconds When the
+         *  timestamp value matches or exceeds both Target Timestamp registers, then based on
+         *  Bits [14:13], TRGTMODSEL1, of Register 459 _PPS Control Register_, the MAC starts
+         *  or stops the PPS signal output and generates an interrupt _if enabled_
+         */
+        uint32_t tstrh1:32;
+    };
+    uint32_t val;
+} gmac_register480_pps1targettimesecondsregister_reg_t;
+
+/** Type of register481_pps1targettimenanosecondsregister register
+ *  Contains the lower 32 bits of time to be compared with the system time to generate
+ *  the interrupt event or to start generating the PPS1 output signal This register is
+ *  present only when IEEE1588 timestamping is enabled without an external timestamp
+ *  input and at least one additional PPS output is selected
+ */
+typedef union {
+    struct {
+        /** ttsl1 : R/W; bitpos: [30:0]; default: 0;
+         *  Target Time Low for PPS1 Register This register stores the time in _signed_
+         *  nanoseconds When the value of the timestamp matches the both Target Timestamp
+         *  registers, then based on the TRGTMODSEL1 field _Bits [14:13]_ in Register 459 _PPS
+         *  Control Register_, the MAC starts or stops the PPS signal output and generates an
+         *  interrupt _if enabled_ This value should not exceed 0x3B9A_C9FF when Bit 9
+         *  _TSCTRLSSR_ is set in Register 448 _Timestamp Control Register_ The actual start or
+         *  stop time of the PPS signal output may have an error margin up to one unit of
+         *  subsecond increment value
+         */
+        uint32_t ttsl1:31;
+        /** trgtbusy1 : R/W1S; bitpos: [31]; default: 0;
+         *  PPS1 Target Time Register Busy The MAC sets this bit when the PPSCMD1 field _Bits
+         *  [10:8]_ in Register 459 _PPS Control Register_ is programmed to 010 or 011
+         *  Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the
+         *  Target Time Registers to the PTP clock domain The MAC clears this bit after
+         *  synchronizing the Target Time Registers to the PTP clock domain The application
+         *  must not update the Target Time Registers when this bit is read as 1 Otherwise, the
+         *  synchronization of the previous programmed time gets corrupted
+         */
+        uint32_t trgtbusy1:1;
+    };
+    uint32_t val;
+} gmac_register481_pps1targettimenanosecondsregister_reg_t;
+
+
+/** Group: dma register */
+/** Type of register0_busmoderegister register
+ *  Controls the Host Interface Mode
+ */
+typedef union {
+    struct {
+        /** swr : R/W1S_SC; bitpos: [0]; default: 1;
+         *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+         *  all internal registers of the MAC It is cleared automatically after the reset
+         *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+         *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+         *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+         *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+         *  the Software reset function The reset operation is completed only when all resets
+         *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+         *  inputs clocks _applicable for the selected PHY interface_ are present for the
+         *  software reset completion The time to complete the software reset operation depends
+         *  on the frequency of the slowest active clock
+         */
+        uint32_t swr:1;
+        /** da : R/W; bitpos: [1]; default: 0;
+         *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+         *  transmit and receive paths of Channel 0 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+         *  The priority between the paths is according to the priority specified in Bits
+         *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+         *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+         *  receive path has priority over the transmit path In the GMACAXI configuration,
+         *  these bits are reserved and are readonly _RO_ For more information about the
+         *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+         *  Arbiter Functions” on page 167
+         */
+        uint32_t da:1;
+        /** dsl : R/W; bitpos: [6:2]; default: 0;
+         *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+         *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+         *  descriptors The address skipping starts from the end of current descriptor to the
+         *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+         *  is taken as contiguous by the DMA in Ring mode
+         */
+        uint32_t dsl:5;
+        /** atds : R/W; bitpos: [7]; default: 0;
+         *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+         *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+         *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+         *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+         *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+         *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+         *  to save 4 bytes of memory This bit is present only when you select the Alternate
+         *  Descriptor feature and any one of the following features during core configuration:
+         *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+         *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+         *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+         *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+         *  for both normal and enhanced descriptors In version 350a, descriptor size is
+         *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+         *  Offload Engine _Type 2_ features
+         */
+        uint32_t atds:1;
+        /** pbl : R/W; bitpos: [13:8]; default: 1;
+         *  Programmable Burst Length These bits indicate the maximum number of beats to be
+         *  transferred in one DMA transaction This is the maximum value that is used in a
+         *  single block Read or Write The DMA always attempts to burst as specified in PBL
+         *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+         *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+         *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+         *  transactions If the number of beats to be transferred is more than 32, then perform
+         *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+         *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+         *  to 8 The PBL values have the following limitation: The maximum number of possible
+         *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+         *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+         *  supported is half the depth of the FIFO, except when specified For different data
+         *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+         *  Table 66 on page 382
+         */
+        uint32_t pbl:6;
+        /** pr : R/W; bitpos: [15:14]; default: 0;
+         *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+         *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+         *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+         *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+         *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+         *  these bits are reserved and readonly _RO_ For more information about the priority
+         *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+         *  Functions” on page 167
+         */
+        uint32_t pr:2;
+        /** fb : R/W; bitpos: [16]; default: 0;
+         *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+         *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+         *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+         *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+         *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+         */
+        uint32_t fb:1;
+        /** rpbl : R/W; bitpos: [22:17]; default: 1;
+         *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+         *  one Rx DMA transaction This is the maximum value that is used in a single block
+         *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+         *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+         *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+         *  valid and applicable only when USP is set high
+         */
+        uint32_t rpbl:6;
+        /** usp : R/W; bitpos: [23]; default: 0;
+         *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+         *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+         *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+         *  applicable for both DMA engines
+         */
+        uint32_t usp:1;
+        /** pblx8 : R/W; bitpos: [24]; default: 0;
+         *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+         *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+         *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+         *  not backward compatible Before release 350a, this bit was 4xPBL
+         */
+        uint32_t pblx8:1;
+        /** aal : R/W; bitpos: [25]; default: 0;
+         *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+         *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+         *  the FB bit is equal to 0, the first burst _accessing the start address of data
+         *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+         *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+         *  default value 0_ in all other configurations
+         */
+        uint32_t aal:1;
+        /** mb : R/W; bitpos: [26]; default: 0;
+         *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+         *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+         *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+         *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+         *  other configuration
+         */
+        uint32_t mb:1;
+        /** txpr : R/W; bitpos: [27]; default: 0;
+         *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+         *  priority than the receive DMA during arbitration for the systemside bus In the
+         *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+         *  about the priority scheme between the transmit and receive paths, see Table 412 in
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t txpr:1;
+        /** prwg : R/W; bitpos: [29:28]; default: 0;
+         *  Channel Priority Weights This field sets the priority weights for Channel 0 during
+         *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+         *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+         *  The priority weight is 4 This field is present in all DWC_gmac configurations
+         *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+         *  readonly _RO_ For more information about the priority weights of DMA channels, see
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t prwg:2;
+        uint32_t reserved_30:1;
+        /** rib : R/W; bitpos: [31]; default: 0;
+         *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+         *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+         *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+         *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+         *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+         *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+         *  all other configuration
+         */
+        uint32_t rib:1;
+    };
+    uint32_t val;
+} gmac_register0_busmoderegister_reg_t;
+
+/** Type of register1_transmitpolldemandregister register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+typedef union {
+    struct {
+        /** tpd : RO; bitpos: [31:0]; default: 0;
+         *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the transmission resumes
+         */
+        uint32_t tpd:32;
+    };
+    uint32_t val;
+} gmac_register1_transmitpolldemandregister_reg_t;
+
+/** Type of register2_receivepolldemandregister register
+ *  Used by the host to instruct the DMA to poll the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** rpd : RO; bitpos: [31:0]; default: 0;
+         *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+         *  active state
+         */
+        uint32_t rpd:32;
+    };
+    uint32_t val;
+} gmac_register2_receivepolldemandregister_reg_t;
+
+/** Type of register3_receivedescriptorlistaddressregister register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** rdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Receive List This field contains the base address of the first descriptor
+         *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+         *  these LSB bits are readonly _RO_
+         */
+        uint32_t rdesla:32;
+    };
+    uint32_t val;
+} gmac_register3_receivedescriptorlistaddressregister_reg_t;
+
+/** Type of register4_transmitdescriptorlistaddressregister register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+typedef union {
+    struct {
+        /** tdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Transmit List This field contains the base address of the first descriptor
+         *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and are internally taken as allzero by the DMA
+         *  Therefore, these LSB bits are readonly _RO_
+         */
+        uint32_t tdesla:32;
+    };
+    uint32_t val;
+} gmac_register4_transmitdescriptorlistaddressregister_reg_t;
+
+/** Type of register5_statusregister register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA
+ */
+typedef union {
+    struct {
+        /** ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+         *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+         *  status information is updated in the descriptor
+         */
+        uint32_t ti:1;
+        /** tps : R/W; bitpos: [1]; default: 0;
+         *  Transmit Process Stopped This bit is set when the transmission is stopped
+         */
+        uint32_t tps:1;
+        /** tu : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+         *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+         *  processing Transmit descriptors, the host should change the ownership of the
+         *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+         */
+        uint32_t tu:1;
+        /** tjt : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+         *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+         *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+         *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+         *  to assert
+         */
+        uint32_t tjt:1;
+        /** ovf : R/W; bitpos: [4]; default: 0;
+         *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+         *  frame reception If the partial frame is transferred to the application, the
+         *  overflow status is set in RDES0[11]
+         */
+        uint32_t ovf:1;
+        /** unf : R/W; bitpos: [5]; default: 0;
+         *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+         *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+         *  is set
+         */
+        uint32_t unf:1;
+        /** ri : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt This bit indicates that the frame reception is complete When
+         *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+         *  reset in the last Descriptor, and the specific frame status information is updated
+         *  in the descriptor The reception remains in the Running state
+         */
+        uint32_t ri:1;
+        /** ru : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+         *  suspended To resume processing Receive descriptors, the host should change the
+         *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+         *  Poll Demand is issued, the Receive Process resumes when the next recognized
+         *  incoming frame is received This bit is set only when the previous Receive
+         *  Descriptor is owned by the DMA
+         */
+        uint32_t ru:1;
+        /** rps : R/W; bitpos: [8]; default: 0;
+         *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+         *  Stopped state
+         */
+        uint32_t rps:1;
+        /** rwt : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+         *  Timer expired while receiving the current frame and the current frame is truncated
+         *  after the watchdog timeout
+         */
+        uint32_t rwt:1;
+        /** eti : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+         *  fully transferred to the MTL Transmit FIFO
+         */
+        uint32_t eti:1;
+        uint32_t reserved_11:2;
+        /** fbi : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+         *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+         *  disables all of its bus accesses 12:11		Reserved	00	RO
+         */
+        uint32_t fbi:1;
+        /** eri : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+         *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+         *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+         */
+        uint32_t eri:1;
+        /** ais : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+         *  of the following when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+         *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+         *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+         *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+         *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+         *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+         *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+         */
+        uint32_t ais:1;
+        /** nis : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+         *  the following bits when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+         *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+         *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+         *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+         *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+         *  causes NIS to be set, is cleared
+         */
+        uint32_t nis:1;
+        /** rs : RO; bitpos: [19:17]; default: 0;
+         *  Receive Process State This field indicates the Receive DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+         *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+         *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+         *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+         *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+         *  receive buffer to host memory
+         */
+        uint32_t rs:3;
+        /** ts : RO; bitpos: [22:20]; default: 0;
+         *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+         *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+         *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+         *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+         *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+         *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+         */
+        uint32_t ts:3;
+        /** eb : RO; bitpos: [25:23]; default: 0;
+         *  Error Bits This field indicates the type of error that caused a Bus Error, for
+         *  example, error response on the AHB or AXI interface This field is valid only when
+         *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+         *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+         *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+         *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+         *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+         */
+        uint32_t eb:3;
+        /** gli : RO; bitpos: [26]; default: 0;
+         *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+         *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+         *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+         *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+         *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+         *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+         *  Register_ and then to clear the source of interrupt _which also clears the GLI
+         *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+         *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+         *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+         *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+         *  subsystem _sbd_intr_o_ is high when this bit is high
+         */
+        uint32_t gli:1;
+        /** gmi : RO; bitpos: [27]; default: 0;
+         *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+         *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+         *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+         *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+         *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+         *  are enabled Otherwise, this bit is reserved
+         */
+        uint32_t gmi:1;
+        /** gpi : RO; bitpos: [28]; default: 0;
+         *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+         *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+         *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+         *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+         *  high This bit is applicable only when the Power Management feature is enabled
+         *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+         *  generated in different clock domains
+         */
+        uint32_t gpi:1;
+        /** tti : RO; bitpos: [29]; default: 0;
+         *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+         *  Generator block of the DWC_gmac The software must read the corresponding registers
+         *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+         *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+         *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+         *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+         */
+        uint32_t tti:1;
+        /** glpii_gtmsi : RO; bitpos: [30]; default: 0;
+         *  GLPII: GMAC LPI Interrupt This bit indicates an interrupt event in the LPI logic of
+         *  the MAC To reset this bit to 1'b0, the software must read the corresponding
+         *  registers in the DWC_gmac to get the exact cause of the interrupt and clear its
+         *  source Note: GLPII status is given only in Channel 0 DMA register and is applicable
+         *  only when the Energy Efficient Ethernet feature is enabled Otherwise, this bit is
+         *  reserved When this bit is high, the interrupt signal from the MAC _sbd_intr_o_ is
+         *  high
+         */
+        uint32_t glpii_gtmsi:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register5_statusregister_reg_t;
+
+/** Type of register6_operationmoderegister register
+ *  Establishes the Receive and Transmit operating modes and command Note: This
+ *  register is valid and present in the GMACMTL configuration
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** sr : R/W; bitpos: [1]; default: 0;
+         *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+         *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+         *  processes the incoming frames The descriptor acquisition is attempted from the
+         *  current position in the list, which is the address set by the Register 3 _Receive
+         *  Descriptor List Address Register_ or the position retained when the Receive process
+         *  was previously stopped If the DMA does not own the descriptor, reception is
+         *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+         *  set The Start Receive command is effective only when the reception has stopped If
+         *  the command is issued before setting Register 3 _Receive Descriptor List Address
+         *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+         *  operation is stopped after the transfer of the current frame The next descriptor
+         *  position in the Receive list is saved and becomes the current position after the
+         *  Receive process is restarted The Stop Receive command is effective only when the
+         *  Receive process is in either the Running _waiting for receive packet_ or in the
+         *  Suspended state Note: For information about how to pause the transmission, see
+         *  “Stopping and Starting Transmission” on page 715
+         */
+        uint32_t sr:1;
+        /** osf : R/W; bitpos: [2]; default: 0;
+         *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+         *  second frame of the Transmit data even before the status for the first frame is
+         *  obtained
+         */
+        uint32_t osf:1;
+        /** rtc : R/W; bitpos: [4:3]; default: 0;
+         *  Receive Threshold Control These two bits control the threshold level of the MTL
+         *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+         *  Receive FIFO is larger than the threshold In addition, full frames with length less
+         *  than the threshold are automatically transferred The value of 11 is not applicable
+         *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+         *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+         *  11: 128
+         */
+        uint32_t rtc:2;
+        /** dgf : R/W; bitpos: [5]; default: 0;
+         *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+         *  that is, frames that are larger than the computed giant frame limit When reset, the
+         *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+         *  the following configurations in which the giant frame status is not provided in Rx
+         *  status and giant frames are not dropped by default: Configurations in which IP
+         *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+         *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+         *  Configurations in which the Advanced Timestamp feature is selected In all other
+         *  configurations, this bit is not used _reserved and always reset_
+         */
+        uint32_t dgf:1;
+        /** fuf : R/W; bitpos: [6]; default: 0;
+         *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+         *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+         *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+         *  frame is already transferred because of the lower value of Receive Threshold, for
+         *  example, RTC = 01
+         */
+        uint32_t fuf:1;
+        /** fef : R/W; bitpos: [7]; default: 0;
+         *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+         *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+         *  overflow_ However, if the start byte _write_ pointer of a frame is already
+         *  transferred to the read controller side _in Threshold mode_, then the frame is not
+         *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+         *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+         *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+         *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+         *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+         *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+         *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+         *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+         *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+         *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+         *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+         *  the extended status is selected The extended status is available with the following
+         *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+         *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+         *  configurations
+         */
+        uint32_t fef:1;
+        /** efc : R/W; bitpos: [8]; default: 0;
+         *  Enable HW Flow Control When this bit is set, the flow control signal operation
+         *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+         *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+         *  less than 4 KB
+         */
+        uint32_t efc:1;
+        /** rfa : R/W; bitpos: [10:9]; default: 0;
+         *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+         *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+         *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+         *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+         *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+         *  used for more threshold levels as described in Bit 23 These bits are reserved and
+         *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+         *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+         *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+         *  flow control on FIFO empty condition
+         */
+        uint32_t rfa:2;
+        /** rfd : R/W; bitpos: [12:11]; default: 0;
+         *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+         *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+         *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+         *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+         *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+         *  used for more threshold levels as described in Bit 22 These bits are reserved and
+         *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+         *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+         *  value programmed in the “RFA_2, RFA” fields
+         */
+        uint32_t rfd:2;
+        /** st : R/W; bitpos: [13]; default: 0;
+         *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+         *  the Running state, and the DMA checks the Transmit List at the current position for
+         *  a frame to be transmitted Descriptor acquisition is attempted either from the
+         *  current position in the list, which is the Transmit List Base Address set by
+         *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+         *  retained when transmission was stopped previously If the DMA does not own the
+         *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+         *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+         *  command is effective only when transmission is stopped If the command is issued
+         *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+         *  behavior is unpredictable When this bit is reset, the transmission process is
+         *  placed in the Stopped state after completing the transmission of the current frame
+         *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+         *  current position when transmission is restarted To change the list address, you
+         *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+         *  value when this bit is reset The new value is considered when this bit is set again
+         *  The stop transmission command is effective only when the transmission of the
+         *  current frame is complete or the transmission is in the Suspended state Note: For
+         *  information about how to pause the transmission, see “Stopping and Starting
+         *  Transmission” on page 715
+         */
+        uint32_t st:1;
+        /** ttc : R/W; bitpos: [16:14]; default: 0;
+         *  Transmit Threshold Control These bits control the threshold level of the MTL
+         *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+         *  is larger than the threshold In addition, full frames with a length less than the
+         *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+         *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+         */
+        uint32_t ttc:3;
+        uint32_t reserved_17:3;
+        /** ftf : R/W1S; bitpos: [20]; default: 0;
+         *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+         *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+         *  This bit is cleared internally when the flushing operation is complete The
+         *  Operation Mode register should not be written to until this bit is cleared The data
+         *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+         *  transmission and results in underflow and runt frame transmission Note: The flush
+         *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+         *  pending Transmit Status of the transmitted frames are accepted by the host In order
+         *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+         *  be active 19:17		Reserved 	000	RO
+         */
+        uint32_t ftf:1;
+        /** tsf : R/W; bitpos: [21]; default: 0;
+         *  Transmit Store and Forward When this bit is set, transmission starts when a full
+         *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+         *  specified in Bits [16:14] are ignored This bit should be changed only when the
+         *  transmission is stopped
+         */
+        uint32_t tsf:1;
+        /** rfd_2 : R/W; bitpos: [22]; default: 0;
+         *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+         *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+         *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+         *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+         *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+         *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+         *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+         */
+        uint32_t rfd_2:1;
+        /** rfa_2 : R/W; bitpos: [23]; default: 0;
+         *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+         *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+         *  levels for activating the flow control in both half duplex and fullduplex modes
+         *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+         *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+         *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+         *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+         *  or less deep
+         */
+        uint32_t rfa_2:1;
+        /** dff : R/W; bitpos: [24]; default: 0;
+         *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+         *  any frames because of the unavailability of receive descriptors or buffers as it
+         *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+         *  This bit is reserved _and RO_ in the GMACMTL configuration
+         */
+        uint32_t dff:1;
+        /** rsf : R/W; bitpos: [25]; default: 0;
+         *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+         *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+         *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+         *  threshold specified by the RTC bits
+         */
+        uint32_t rsf:1;
+        /** dt : R/W; bitpos: [26]; default: 0;
+         *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+         *  not drop the frames which only have errors detected by the Receive Checksum Offload
+         *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+         *  frame received by the MAC but have errors only in the encapsulated payload When
+         *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+         *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+         *  value 1'b0_
+         */
+        uint32_t dt:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} gmac_register6_operationmoderegister_reg_t;
+
+/** Type of register7_interruptenableregister register
+ *  Enables the interrupts reported by the Status Register
+ */
+typedef union {
+    struct {
+        /** tie : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+         *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+         *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+         *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+         *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+         */
+        uint32_t tie:1;
+        /** tse : R/W; bitpos: [1]; default: 0;
+         *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+         *  Transmission Stopped Interrupt is disabled
+         */
+        uint32_t tse:1;
+        /** tue : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+         *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t tue:1;
+        /** the : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+         *  reset, the Transmit Jabber Timeout Interrupt is disabled
+         */
+        uint32_t the:1;
+        /** ove : R/W; bitpos: [4]; default: 0;
+         *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+         *  the Overflow Interrupt is disabled
+         */
+        uint32_t ove:1;
+        /** une : R/W; bitpos: [5]; default: 0;
+         *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+         *  reset, the Underflow Interrupt is disabled
+         */
+        uint32_t une:1;
+        /** rie : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+         *  Interrupt is disabled
+         */
+        uint32_t rie:1;
+        /** rue : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t rue:1;
+        /** rse : R/W; bitpos: [8]; default: 0;
+         *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+         *  Receive Stopped Interrupt is disabled
+         */
+        uint32_t rse:1;
+        /** rwe : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+         *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+         */
+        uint32_t rwe:1;
+        /** ete : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+         *  reset, the Early Transmit Interrupt is disabled
+         */
+        uint32_t ete:1;
+        uint32_t reserved_11:2;
+        /** fbe : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+         *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+         */
+        uint32_t fbe:1;
+        /** ere : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+         *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+         *  Early Receive Interrupt is disabled
+         */
+        uint32_t ere:1;
+        /** aie : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+         *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+         *  bit enables the following interrupts in Register 5 _Status Register_: Register
+         *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+         *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+         *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+         *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+         *  Error
+         */
+        uint32_t aie:1;
+        /** nie : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+         *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+         *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+         *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+         *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+         */
+        uint32_t nie:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} gmac_register7_interruptenableregister_reg_t;
+
+/** Type of register8_missedframeandbufferoverflowcounterregister register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+typedef union {
+    struct {
+        /** misfrmcnt : R/W; bitpos: [15:0]; default: 0;
+         *  Missed Frame Counter This field indicates the number of frames missed by the
+         *  controller because of the Host Receive Buffer being unavailable This counter is
+         *  incremented each time the DMA discards an incoming frame The counter is cleared
+         *  when this register is read with mci_be_i[0] at 1’b1
+         */
+        uint32_t misfrmcnt:16;
+        /** miscntovf : R/W; bitpos: [16]; default: 0;
+         *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+         *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+         *  of the Host Receive Buffer being unavailable with the missed frame counter at
+         *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+         *  this bit indicates that the rollover happened
+         */
+        uint32_t miscntovf:1;
+        /** ovffrmcnt : R/W; bitpos: [27:17]; default: 0;
+         *  Overflow Frame Counter This field indicates the number of frames missed by the
+         *  application This counter is incremented each time the MTL FIFO overflows The
+         *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+         */
+        uint32_t ovffrmcnt:11;
+        /** ovfcntovf : R/W; bitpos: [28]; default: 0;
+         *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+         *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+         *  overflow frame counter at maximum value In such a scenario, the overflow frame
+         *  counter is reset to allzeros and this bit indicates that the rollover happened
+         */
+        uint32_t ovfcntovf:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register8_missedframeandbufferoverflowcounterregister_reg_t;
+
+/** Type of register9_receiveinterruptwatchdogtimerregister register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+typedef union {
+    struct {
+        /** riwt : R/W; bitpos: [7:0]; default: 0;
+         *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+         *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+         *  triggered with the programmed value after the Rx DMA completes the transfer of a
+         *  frame for which the RI status bit is not set because of the setting in the
+         *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+         *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+         *  high because of automatic setting of RI as per RDES1[31] of any received frame
+         */
+        uint32_t riwt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gmac_register9_receiveinterruptwatchdogtimerregister_reg_t;
+
+/** Type of register10_axibusmoderegister register
+ *  Controls AXI master behavior _mainly controls burst splitting and number of
+ *  outstanding requests_
+ */
+typedef union {
+    struct {
+        /** undef : RO; bitpos: [0]; default: 1;
+         *  AXI Undefined Burst Length This bit is readonly bit and indicates the complement
+         *  _invert_ value of Bit 16 _FB_ in Register 0 _Bus Mode Register_ When this bit is
+         *  set to 1, the GMACAXI is allowed to perform any burst length equal to or below the
+         *  maximum allowed burst length programmed in Bits[7:3] When this bit is set to 0, the
+         *  GMACAXI is allowed to perform only fixed burst lengths as indicated by BLEN256,
+         *  BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1 If UNDEF
+         *  is set and none of the BLEN bits is set, then GMACAXI is allowed to perform a burst
+         *  length of 16
+         */
+        uint32_t undef:1;
+        /** blen4 : R/W; bitpos: [1]; default: 0;
+         *  AXI Burst Length 4 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 4 on the AXI master interface Setting this bit has no effect when
+         *  UNDEF is set to 1
+         */
+        uint32_t blen4:1;
+        /** blen8 : R/W; bitpos: [2]; default: 0;
+         *  AXI Burst Length 8 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 8 on the AXI master interface Setting this bit has no effect when
+         *  UNDEF is set to 1
+         */
+        uint32_t blen8:1;
+        /** blen16 : R/W; bitpos: [3]; default: 0;
+         *  AXI Burst Length 16 When this bit is set to 1 or UNDEF is set to 1, the GMACAXI is
+         *  allowed to select a burst length of 16 on the AXI master interface
+         */
+        uint32_t blen16:1;
+        /** blen32 : R/W; bitpos: [4]; default: 0;
+         *  AXI Burst Length 32 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 32 on the AXI master interface This bit is present only when the
+         *  configuration parameter AXI_BL is set to 32 or more Otherwise, this bit is reserved
+         *  and is readonly _RO_
+         */
+        uint32_t blen32:1;
+        /** blen64 : R/W; bitpos: [5]; default: 0;
+         *  AXI Burst Length 64 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 64 on the AXI master interface This bit is present only when the
+         *  configuration parameter AXI_BL is set to 64 or more Otherwise, this bit is reserved
+         *  and is readonly _RO_
+         */
+        uint32_t blen64:1;
+        /** blen128 : R/W; bitpos: [6]; default: 0;
+         *  AXI Burst Length 128 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 128 on the AXI master interface This bit is present only when the
+         *  configuration parameter AXI_BL is set to 128 or more Otherwise, this bit is
+         *  reserved and is readonly _RO_
+         */
+        uint32_t blen128:1;
+        /** blen256 : R/W; bitpos: [7]; default: 0;
+         *  AXI Burst Length 256 When this bit is set to 1, the GMACAXI is allowed to select a
+         *  burst length of 256 on the AXI master interface This bit is present only when the
+         *  configuration parameter AXI_BL is set to 256 Otherwise, this bit is reserved and is
+         *  readonly _RO_
+         */
+        uint32_t blen256:1;
+        uint32_t reserved_8:4;
+        /** axi_aal : RO; bitpos: [12]; default: 0;
+         *  AddressAligned Beats This bit is readonly bit and reflects the Bit 25 _AAL_ of
+         *  Register 0 _Bus Mode Register_ When this bit is set to 1, the GMACAXI performs
+         *  addressaligned burst transfers on both read and write channels 11:8		Reserved	0H	RO
+         */
+        uint32_t axi_aal:1;
+        /** onekbbe : R/W; bitpos: [13]; default: 0;
+         *  1 KB Boundary Crossing Enable for the GMACAXI Master When set, the GMACAXI master
+         *  performs burst transfers that do not cross 1 KB boundary When reset, the GMACAXI
+         *  master performs burst transfers that do not cross 4 KB boundary
+         */
+        uint32_t onekbbe:1;
+        uint32_t reserved_14:2;
+        /** rd_osr_lmt : R/W; bitpos: [19:16]; default: 1;
+         *  AXI Maximum Read Outstanding Request Limit This value limits the maximum
+         *  outstanding request on the AXI read interface Maximum outstanding requests =
+         *  RD_OSR_LMT+1 Note: Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4 Bit 19 is
+         *  reserved if AXI_GM_MAX_RD_REQUESTS != 16 15:14		Reserved	00	RO
+         */
+        uint32_t rd_osr_lmt:4;
+        /** wr_osr_lmt : R/W; bitpos: [23:20]; default: 1;
+         *  AXI Maximum Write Outstanding Request Limit This value limits the maximum
+         *  outstanding request on the AXI write interface Maximum outstanding requests =
+         *  WR_OSR_LMT+1 Note: Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4 Bit 23 bit is
+         *  reserved if AXI_GM_MAX_WR_REQUESTS != 16
+         */
+        uint32_t wr_osr_lmt:4;
+        uint32_t reserved_24:6;
+        /** lpi_xit_frm : R/W; bitpos: [30]; default: 0;
+         *  Unlock on Magic Packet or Remote WakeUp Frame When set to 1, this bit enables the
+         *  GMACAXI to come out of the LPI mode only when the magic packet or remote wakeup
+         *  frame is received When set to 0, this bit enables the GMACAXI to come out of LPI
+         *  mode when any frame is received 29:24		Reserved	00H	RO
+         */
+        uint32_t lpi_xit_frm:1;
+        /** en_lpi : R/W; bitpos: [31]; default: 0;
+         *  Enable Low Power Interface _LPI_ When set to 1, this bit enables the LPI mode
+         *  supported by the GMACAXI configuration and accepts the LPI request from the AXI
+         *  System Clock controller When set to 0, this bit disables the LPI mode and always
+         *  denies the LPI request from the AXI System Clock controller
+         */
+        uint32_t en_lpi:1;
+    };
+    uint32_t val;
+} gmac_register10_axibusmoderegister_reg_t;
+
+/** Type of register11_ahboraxistatusregister register
+ *  Gives the idle status of the AHB master interface in the GMACAHB configuration
+ *  Gives the idle status of the AXI master's read or write channel in the GMACAXI
+ *  configuration
+ */
+typedef union {
+    struct {
+        /** axwhsts : RO; bitpos: [0]; default: 0;
+         *  AXI Master Write Channel or AHB Master Status When high, it indicates that AXI
+         *  master's write channel is active and transferring data in the GMACAXI configuration
+         *  In the GMACAHB configuration, it indicates that the AHB master interface FSMs are
+         *  in the nonidle state
+         */
+        uint32_t axwhsts:1;
+        /** axirdsts : RO; bitpos: [1]; default: 0;
+         *  AXI Master Read Channel Status When high, it indicates that AXI master's read
+         *  channel is active and transferring data
+         */
+        uint32_t axirdsts:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} gmac_register11_ahboraxistatusregister_reg_t;
+
+/** Type of register18_currenthosttransmitdescriptorregister register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** curtdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Descriptor Address Pointer
+         */
+        uint32_t curtdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register18_currenthosttransmitdescriptorregister_reg_t;
+
+/** Type of register19_currenthostreceivedescriptorregister register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** currdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Descriptor Address Pointer
+         */
+        uint32_t currdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register19_currenthostreceivedescriptorregister_reg_t;
+
+/** Type of register20_currenthosttransmitbufferaddressregister register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** curtbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Buffer Address Pointer
+         */
+        uint32_t curtbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register20_currenthosttransmitbufferaddressregister_reg_t;
+
+/** Type of register21_currenthostreceivebufferaddressregister register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** currbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Buffer Address Pointer
+         */
+        uint32_t currbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register21_currenthostreceivebufferaddressregister_reg_t;
+
+/** Type of register22_hwfeatureregister register
+ *  Indicates the presence of the optional features of the core
+ */
+typedef union {
+    struct {
+        /** miisel : RO; bitpos: [0]; default: 0;
+         *  10 or 100 Mbps support
+         */
+        uint32_t miisel:1;
+        /** gmiisel : RO; bitpos: [1]; default: 0;
+         *  1000 Mbps support
+         */
+        uint32_t gmiisel:1;
+        /** hdsel : RO; bitpos: [2]; default: 0;
+         *  Halfduplex support
+         */
+        uint32_t hdsel:1;
+        /** exthashen : RO; bitpos: [3]; default: 0;
+         *  Expanded DA Hash filter
+         */
+        uint32_t exthashen:1;
+        /** hashsel : RO; bitpos: [4]; default: 0;
+         *  HASH filter
+         */
+        uint32_t hashsel:1;
+        /** addmacadrsel : RO; bitpos: [5]; default: 0;
+         *  Multiple MAC Address registers
+         */
+        uint32_t addmacadrsel:1;
+        /** pcssel : RO; bitpos: [6]; default: 0;
+         *  PCS registers _TBI, SGMII, or RTBI PHY interface_
+         */
+        uint32_t pcssel:1;
+        /** l3l4fltren : RO; bitpos: [7]; default: 0;
+         *  Layer 3 and Layer 4 feature
+         */
+        uint32_t l3l4fltren:1;
+        /** smasel : RO; bitpos: [8]; default: 0;
+         *  SMA _MDIO_ Interface
+         */
+        uint32_t smasel:1;
+        /** rwksel : RO; bitpos: [9]; default: 0;
+         *  PMT remote wakeup frame
+         */
+        uint32_t rwksel:1;
+        /** mgksel : RO; bitpos: [10]; default: 0;
+         *  PMT magic packet
+         */
+        uint32_t mgksel:1;
+        /** mmcsel : RO; bitpos: [11]; default: 0;
+         *  RMON module
+         */
+        uint32_t mmcsel:1;
+        /** tsver1sel : RO; bitpos: [12]; default: 0;
+         *  Only IEEE 15882002 timestamp
+         */
+        uint32_t tsver1sel:1;
+        /** tsver2sel : RO; bitpos: [13]; default: 0;
+         *  IEEE 15882008 Advanced timestamp
+         */
+        uint32_t tsver2sel:1;
+        /** eeesel : RO; bitpos: [14]; default: 0;
+         *  Energy Efficient Ethernet
+         */
+        uint32_t eeesel:1;
+        /** avsel : RO; bitpos: [15]; default: 0;
+         *  AV feature
+         */
+        uint32_t avsel:1;
+        /** txcoesel : RO; bitpos: [16]; default: 0;
+         *  Checksum Offload in Tx
+         */
+        uint32_t txcoesel:1;
+        /** rxtyp1coe : RO; bitpos: [17]; default: 0;
+         *  IP Checksum Offload _Type 1_ in Rx Note: If IPCHKSUM_EN = Enabled and
+         *  IPC_FULL_OFFLOAD = Enabled, then RXTYP1COE = 0 and RXTYP2COE = 1
+         */
+        uint32_t rxtyp1coe:1;
+        /** rxtyp2coe : RO; bitpos: [18]; default: 0;
+         *  IP Checksum Offload _Type 2_ in Rx
+         */
+        uint32_t rxtyp2coe:1;
+        /** rxfifosize : RO; bitpos: [19]; default: 0;
+         *  Rx FIFO > 2,048 Bytes
+         */
+        uint32_t rxfifosize:1;
+        /** rxchcnt : RO; bitpos: [21:20]; default: 0;
+         *  Number of additional Rx Channels
+         */
+        uint32_t rxchcnt:2;
+        /** txchcnt : RO; bitpos: [23:22]; default: 0;
+         *  Number of additional Tx Channels
+         */
+        uint32_t txchcnt:2;
+        /** enhdessel : RO; bitpos: [24]; default: 0;
+         *  Alternate _Enhanced Descriptor_
+         */
+        uint32_t enhdessel:1;
+        /** inttsen : RO; bitpos: [25]; default: 0;
+         *  Timestamping with Internal System Time
+         */
+        uint32_t inttsen:1;
+        /** flexippsen : RO; bitpos: [26]; default: 0;
+         *  Flexible PulsePerSecond Output
+         */
+        uint32_t flexippsen:1;
+        /** savlanins : RO; bitpos: [27]; default: 0;
+         *  Source Address or VLAN Insertion
+         */
+        uint32_t savlanins:1;
+        /** actphyif : RO; bitpos: [30:28]; default: 0;
+         *  Active or selected PHY interface When you have multiple PHY interfaces in your
+         *  configuration, this field indicates the sampled value of phy_intf_sel_i during
+         *  reset deassertion 000: GMII or MII 001: RGMII 010: SGMII 011: TBI 100: RMII 101:
+         *  RTBI 110: SMII 111: RevMII All Others: Reserved
+         */
+        uint32_t actphyif:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register22_hwfeatureregister_reg_t;
+
+/** Type of register64_channel1busmoderegister register
+ *  Controls the Host Interface mode for Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_swr : R/W1S; bitpos: [0]; default: 1;
+         *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+         *  all internal registers of the MAC It is cleared automatically after the reset
+         *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+         *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+         *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+         *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+         *  the Software reset function The reset operation is completed only when all resets
+         *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+         *  inputs clocks _applicable for the selected PHY interface_ are present for the
+         *  software reset completion The time to complete the software reset operation depends
+         *  on the frequency of the slowest active clock
+         */
+        uint32_t ch1_swr:1;
+        /** ch1_da : R/W; bitpos: [1]; default: 0;
+         *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+         *  transmit and receive paths of Channel 1 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+         *  The priority between the paths is according to the priority specified in Bits
+         *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+         *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+         *  receive path has priority over the transmit path In the GMACAXI configuration,
+         *  these bits are reserved and are readonly _RO_ For more information about the
+         *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+         *  Arbiter Functions” on page 167
+         */
+        uint32_t ch1_da:1;
+        /** ch1_dsl : R/W; bitpos: [6:2]; default: 0;
+         *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+         *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+         *  descriptors The address skipping starts from the end of current descriptor to the
+         *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+         *  is taken as contiguous by the DMA in Ring mode
+         */
+        uint32_t ch1_dsl:5;
+        /** ch1_atds : R/W; bitpos: [7]; default: 0;
+         *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+         *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+         *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+         *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+         *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+         *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+         *  to save 4 bytes of memory This bit is present only when you select the Alternate
+         *  Descriptor feature and any one of the following features during core configuration:
+         *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+         *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+         *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+         *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+         *  for both normal and enhanced descriptors In version 350a, descriptor size is
+         *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+         *  Offload Engine _Type 2_ features
+         */
+        uint32_t ch1_atds:1;
+        /** ch1_pbl : R/W; bitpos: [13:8]; default: 1;
+         *  Programmable Burst Length These bits indicate the maximum number of beats to be
+         *  transferred in one DMA transaction This is the maximum value that is used in a
+         *  single block Read or Write The DMA always attempts to burst as specified in PBL
+         *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+         *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+         *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+         *  transactions If the number of beats to be transferred is more than 32, then perform
+         *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+         *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+         *  to 8 The PBL values have the following limitation: The maximum number of possible
+         *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+         *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+         *  supported is half the depth of the FIFO, except when specified For different data
+         *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+         *  Table 66 on page 382
+         */
+        uint32_t ch1_pbl:6;
+        /** ch1_pr : R/W; bitpos: [15:14]; default: 0;
+         *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+         *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+         *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+         *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+         *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+         *  these bits are reserved and readonly _RO_ For more information about the priority
+         *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+         *  Functions” on page 167
+         */
+        uint32_t ch1_pr:2;
+        /** ch1_fb : R/W; bitpos: [16]; default: 0;
+         *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+         *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+         *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+         *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+         *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+         */
+        uint32_t ch1_fb:1;
+        /** ch1_rpbl : R/W; bitpos: [22:17]; default: 1;
+         *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+         *  one Rx DMA transaction This is the maximum value that is used in a single block
+         *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+         *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+         *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+         *  valid and applicable only when USP is set high
+         */
+        uint32_t ch1_rpbl:6;
+        /** ch1_usp : R/W; bitpos: [23]; default: 0;
+         *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+         *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+         *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+         *  applicable for both DMA engines
+         */
+        uint32_t ch1_usp:1;
+        /** ch1_pblx8 : R/W; bitpos: [24]; default: 0;
+         *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+         *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+         *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+         *  not backward compatible Before release 350a, this bit was 4xPBL
+         */
+        uint32_t ch1_pblx8:1;
+        /** ch1_aal : R/W; bitpos: [25]; default: 0;
+         *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+         *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+         *  the FB bit is equal to 0, the first burst _accessing the start address of data
+         *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+         *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+         *  default value 0_ in all other configurations
+         */
+        uint32_t ch1_aal:1;
+        /** ch1_mb : R/W; bitpos: [26]; default: 0;
+         *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+         *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+         *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+         *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+         *  other configuration
+         */
+        uint32_t ch1_mb:1;
+        /** ch1_txpr : R/W; bitpos: [27]; default: 0;
+         *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+         *  priority than the receive DMA during arbitration for the systemside bus In the
+         *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+         *  about the priority scheme between the transmit and receive paths, see Table 412 in
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t ch1_txpr:1;
+        /** ch1_prwg : R/W; bitpos: [29:28]; default: 0;
+         *  Channel Priority Weights This field sets the priority weights for Channel 1 during
+         *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+         *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+         *  The priority weight is 4 This field is present in all DWC_gmac configurations
+         *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+         *  readonly _RO_ For more information about the priority weights of DMA channels, see
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t ch1_prwg:2;
+        uint32_t reserved_30:1;
+        /** ch1_rib : R/W; bitpos: [31]; default: 0;
+         *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+         *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+         *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+         *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+         *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+         *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+         *  all other configuration
+         */
+        uint32_t ch1_rib:1;
+    };
+    uint32_t val;
+} gmac_register64_channel1busmoderegister_reg_t;
+
+/** Type of register65_channel1transmitpolldemandregister register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch1_tpd : RO; bitpos: [31:0]; default: 0;
+         *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the transmission resumes
+         */
+        uint32_t ch1_tpd:32;
+    };
+    uint32_t val;
+} gmac_register65_channel1transmitpolldemandregister_reg_t;
+
+/** Type of register66_channel1receivepolldemandregister register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch1_rpd : RO; bitpos: [31:0]; default: 0;
+         *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+         *  active state
+         */
+        uint32_t ch1_rpd:32;
+    };
+    uint32_t val;
+} gmac_register66_channel1receivepolldemandregister_reg_t;
+
+/** Type of register67_channel1receivedescriptorlistaddressregister register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch1_rdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Receive List This field contains the base address of the first descriptor
+         *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+         *  these LSB bits are readonly _RO_
+         */
+        uint32_t ch1_rdesla:32;
+    };
+    uint32_t val;
+} gmac_register67_channel1receivedescriptorlistaddressregister_reg_t;
+
+/** Type of register68_channel1transmitdescriptorlistaddressregister register
+ *  Points the DMA to the start of the Transmit Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch1_tdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Transmit List This field contains the base address of the first descriptor
+         *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and are internally taken as allzero by the DMA
+         *  Therefore, these LSB bits are readonly _RO_
+         */
+        uint32_t ch1_tdesla:32;
+    };
+    uint32_t val;
+} gmac_register68_channel1transmitdescriptorlistaddressregister_reg_t;
+
+/** Type of register69_channel1statusregister register
+ *  The Software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits 29:26 are reserved for
+ *  the Channel 1 Status Register
+ */
+typedef union {
+    struct {
+        /** ch1_ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+         *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+         *  status information is updated in the descriptor
+         */
+        uint32_t ch1_ti:1;
+        /** ch1_tps : R/W; bitpos: [1]; default: 0;
+         *  Transmit Process Stopped This bit is set when the transmission is stopped
+         */
+        uint32_t ch1_tps:1;
+        /** ch1_tu : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+         *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+         *  processing Transmit descriptors, the host should change the ownership of the
+         *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+         */
+        uint32_t ch1_tu:1;
+        /** ch1_tjt : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+         *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+         *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+         *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+         *  to assert
+         */
+        uint32_t ch1_tjt:1;
+        /** ch1_ovf : R/W; bitpos: [4]; default: 0;
+         *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+         *  frame reception If the partial frame is transferred to the application, the
+         *  overflow status is set in RDES0[11]
+         */
+        uint32_t ch1_ovf:1;
+        /** ch1_unf : R/W; bitpos: [5]; default: 0;
+         *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+         *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+         *  is set
+         */
+        uint32_t ch1_unf:1;
+        /** ch1_ri : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt This bit indicates that the frame reception is complete When
+         *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+         *  reset in the last Descriptor, and the specific frame status information is updated
+         *  in the descriptor The reception remains in the Running state
+         */
+        uint32_t ch1_ri:1;
+        /** ch1_ru : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+         *  suspended To resume processing Receive descriptors, the host should change the
+         *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+         *  Poll Demand is issued, the Receive Process resumes when the next recognized
+         *  incoming frame is received This bit is set only when the previous Receive
+         *  Descriptor is owned by the DMA
+         */
+        uint32_t ch1_ru:1;
+        /** ch1_rps : R/W; bitpos: [8]; default: 0;
+         *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+         *  Stopped state
+         */
+        uint32_t ch1_rps:1;
+        /** ch1_rwt : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+         *  Timer expired while receiving the current frame and the current frame is truncated
+         *  after the watchdog timeout
+         */
+        uint32_t ch1_rwt:1;
+        /** ch1_eti : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+         *  fully transferred to the MTL Transmit FIFO
+         */
+        uint32_t ch1_eti:1;
+        uint32_t reserved_11:2;
+        /** ch1_fbi : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+         *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+         *  disables all of its bus accesses 12:11		Reserved	00	RO
+         */
+        uint32_t ch1_fbi:1;
+        /** ch1_eri : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+         *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+         *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+         */
+        uint32_t ch1_eri:1;
+        /** ch1_ais : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+         *  of the following when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+         *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+         *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+         *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+         *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+         *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+         *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+         */
+        uint32_t ch1_ais:1;
+        /** ch1_nis : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+         *  the following bits when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+         *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+         *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+         *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+         *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+         *  causes NIS to be set, is cleared
+         */
+        uint32_t ch1_nis:1;
+        /** ch1_rs : RO; bitpos: [19:17]; default: 0;
+         *  Receive Process State This field indicates the Receive DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+         *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+         *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+         *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+         *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+         *  receive buffer to host memory
+         */
+        uint32_t ch1_rs:3;
+        /** ch1_ts : RO; bitpos: [22:20]; default: 0;
+         *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+         *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+         *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+         *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+         *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+         *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+         */
+        uint32_t ch1_ts:3;
+        /** ch1_eb : RO; bitpos: [25:23]; default: 0;
+         *  Error Bits This field indicates the type of error that caused a Bus Error, for
+         *  example, error response on the AHB or AXI interface This field is valid only when
+         *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+         *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+         *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+         *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+         *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+         */
+        uint32_t ch1_eb:3;
+        /** ch1_gli : RO; bitpos: [26]; default: 0;
+         *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+         *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+         *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+         *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+         *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+         *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+         *  Register_ and then to clear the source of interrupt _which also clears the GLI
+         *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+         *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+         *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+         *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+         *  subsystem _sbd_intr_o_ is high when this bit is high
+         */
+        uint32_t ch1_gli:1;
+        /** ch1_gmi : RO; bitpos: [27]; default: 0;
+         *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+         *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+         *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+         *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+         *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+         *  are enabled Otherwise, this bit is reserved
+         */
+        uint32_t ch1_gmi:1;
+        /** ch1_gpi : RO; bitpos: [28]; default: 0;
+         *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+         *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+         *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+         *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+         *  high This bit is applicable only when the Power Management feature is enabled
+         *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+         *  generated in different clock domains
+         */
+        uint32_t ch1_gpi:1;
+        /** ch1_tti : RO; bitpos: [29]; default: 0;
+         *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+         *  Generator block of the DWC_gmac The software must read the corresponding registers
+         *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+         *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+         *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+         *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+         */
+        uint32_t ch1_tti:1;
+        /** ch1_glpii_gtmsi : RO; bitpos: [30]; default: 0;
+         *  GTMSI: GMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+         *  interrupt event in the traffic manager and scheduler logic of DWC_gmac To reset
+         *  this bit, the software must read the corresponding registers _Channel Status
+         *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+         *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+         *  enabled and corresponding additional transmit channels are present Otherwise, this
+         *  bit is reserved When this bit is high, the interrupt signal from the MAC
+         *  _sbd_intr_o_ is high
+         */
+        uint32_t ch1_glpii_gtmsi:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register69_channel1statusregister_reg_t;
+
+/** Type of register70_channel1operationmoderegister register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** ch1_sr : R/W; bitpos: [1]; default: 0;
+         *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+         *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+         *  processes the incoming frames The descriptor acquisition is attempted from the
+         *  current position in the list, which is the address set by the Register 3 _Receive
+         *  Descriptor List Address Register_ or the position retained when the Receive process
+         *  was previously stopped If the DMA does not own the descriptor, reception is
+         *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+         *  set The Start Receive command is effective only when the reception has stopped If
+         *  the command is issued before setting Register 3 _Receive Descriptor List Address
+         *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+         *  operation is stopped after the transfer of the current frame The next descriptor
+         *  position in the Receive list is saved and becomes the current position after the
+         *  Receive process is restarted The Stop Receive command is effective only when the
+         *  Receive process is in either the Running _waiting for receive packet_ or in the
+         *  Suspended state Note: For information about how to pause the transmission, see
+         *  “Stopping and Starting Transmission” on page 715
+         */
+        uint32_t ch1_sr:1;
+        /** ch1_osf : R/W; bitpos: [2]; default: 0;
+         *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+         *  second frame of the Transmit data even before the status for the first frame is
+         *  obtained
+         */
+        uint32_t ch1_osf:1;
+        /** ch1_rtc : R/W; bitpos: [4:3]; default: 0;
+         *  Receive Threshold Control These two bits control the threshold level of the MTL
+         *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+         *  Receive FIFO is larger than the threshold In addition, full frames with length less
+         *  than the threshold are automatically transferred The value of 11 is not applicable
+         *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+         *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+         *  11: 128
+         */
+        uint32_t ch1_rtc:2;
+        /** ch1_dgf : R/W; bitpos: [5]; default: 0;
+         *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+         *  that is, frames that are larger than the computed giant frame limit When reset, the
+         *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+         *  the following configurations in which the giant frame status is not provided in Rx
+         *  status and giant frames are not dropped by default: Configurations in which IP
+         *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+         *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+         *  Configurations in which the Advanced Timestamp feature is selected In all other
+         *  configurations, this bit is not used _reserved and always reset_
+         */
+        uint32_t ch1_dgf:1;
+        /** ch1_fuf : R/W; bitpos: [6]; default: 0;
+         *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+         *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+         *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+         *  frame is already transferred because of the lower value of Receive Threshold, for
+         *  example, RTC = 01
+         */
+        uint32_t ch1_fuf:1;
+        /** ch1_fef : R/W; bitpos: [7]; default: 0;
+         *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+         *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+         *  overflow_ However, if the start byte _write_ pointer of a frame is already
+         *  transferred to the read controller side _in Threshold mode_, then the frame is not
+         *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+         *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+         *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+         *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+         *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+         *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+         *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+         *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+         *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+         *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+         *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+         *  the extended status is selected The extended status is available with the following
+         *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+         *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+         *  configurations
+         */
+        uint32_t ch1_fef:1;
+        /** ch1_efc : R/W; bitpos: [8]; default: 0;
+         *  Enable HW Flow Control When this bit is set, the flow control signal operation
+         *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+         *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+         *  less than 4 KB
+         */
+        uint32_t ch1_efc:1;
+        /** ch1_rfa : R/W; bitpos: [10:9]; default: 0;
+         *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+         *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+         *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+         *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+         *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+         *  used for more threshold levels as described in Bit 23 These bits are reserved and
+         *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+         *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+         *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+         *  flow control on FIFO empty condition
+         */
+        uint32_t ch1_rfa:2;
+        /** ch1_rfd : R/W; bitpos: [12:11]; default: 0;
+         *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+         *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+         *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+         *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+         *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+         *  used for more threshold levels as described in Bit 22 These bits are reserved and
+         *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+         *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+         *  value programmed in the “RFA_2, RFA” fields
+         */
+        uint32_t ch1_rfd:2;
+        /** ch1_st : R/W; bitpos: [13]; default: 0;
+         *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+         *  the Running state, and the DMA checks the Transmit List at the current position for
+         *  a frame to be transmitted Descriptor acquisition is attempted either from the
+         *  current position in the list, which is the Transmit List Base Address set by
+         *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+         *  retained when transmission was stopped previously If the DMA does not own the
+         *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+         *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+         *  command is effective only when transmission is stopped If the command is issued
+         *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+         *  behavior is unpredictable When this bit is reset, the transmission process is
+         *  placed in the Stopped state after completing the transmission of the current frame
+         *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+         *  current position when transmission is restarted To change the list address, you
+         *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+         *  value when this bit is reset The new value is considered when this bit is set again
+         *  The stop transmission command is effective only when the transmission of the
+         *  current frame is complete or the transmission is in the Suspended state Note: For
+         *  information about how to pause the transmission, see “Stopping and Starting
+         *  Transmission” on page 715
+         */
+        uint32_t ch1_st:1;
+        /** ch1_ttc : R/W; bitpos: [16:14]; default: 0;
+         *  Transmit Threshold Control These bits control the threshold level of the MTL
+         *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+         *  is larger than the threshold In addition, full frames with a length less than the
+         *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+         *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+         */
+        uint32_t ch1_ttc:3;
+        uint32_t reserved_17:3;
+        /** ch1_ftf : R/W1S; bitpos: [20]; default: 0;
+         *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+         *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+         *  This bit is cleared internally when the flushing operation is complete The
+         *  Operation Mode register should not be written to until this bit is cleared The data
+         *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+         *  transmission and results in underflow and runt frame transmission Note: The flush
+         *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+         *  pending Transmit Status of the transmitted frames are accepted by the host In order
+         *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+         *  be active 19:17		Reserved 	000	RO
+         */
+        uint32_t ch1_ftf:1;
+        /** ch1_tsf : R/W; bitpos: [21]; default: 0;
+         *  Transmit Store and Forward When this bit is set, transmission starts when a full
+         *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+         *  specified in Bits [16:14] are ignored This bit should be changed only when the
+         *  transmission is stopped
+         */
+        uint32_t ch1_tsf:1;
+        /** ch1_rfd_2 : R/W; bitpos: [22]; default: 0;
+         *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+         *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+         *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+         *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+         *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+         *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+         *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+         */
+        uint32_t ch1_rfd_2:1;
+        /** ch1_rfa_2 : R/W; bitpos: [23]; default: 0;
+         *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+         *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+         *  levels for activating the flow control in both half duplex and fullduplex modes
+         *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+         *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+         *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+         *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+         *  or less deep
+         */
+        uint32_t ch1_rfa_2:1;
+        /** ch1_dff : R/W; bitpos: [24]; default: 0;
+         *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+         *  any frames because of the unavailability of receive descriptors or buffers as it
+         *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+         *  This bit is reserved _and RO_ in the GMACMTL configuration
+         */
+        uint32_t ch1_dff:1;
+        /** ch1_rsf : R/W; bitpos: [25]; default: 0;
+         *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+         *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+         *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+         *  threshold specified by the RTC bits
+         */
+        uint32_t ch1_rsf:1;
+        /** ch1_dt : R/W; bitpos: [26]; default: 0;
+         *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+         *  not drop the frames which only have errors detected by the Receive Checksum Offload
+         *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+         *  frame received by the MAC but have errors only in the encapsulated payload When
+         *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+         *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+         *  value 1'b0_
+         */
+        uint32_t ch1_dt:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} gmac_register70_channel1operationmoderegister_reg_t;
+
+/** Type of register71_channel1interruptenableregister register
+ *  Enables the interrupts reported by the Status Register
+ */
+typedef union {
+    struct {
+        /** ch1_tie : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+         *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+         *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+         *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+         *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+         */
+        uint32_t ch1_tie:1;
+        /** ch1_tse : R/W; bitpos: [1]; default: 0;
+         *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+         *  Transmission Stopped Interrupt is disabled
+         */
+        uint32_t ch1_tse:1;
+        /** ch1_tue : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+         *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t ch1_tue:1;
+        /** ch1_tje : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+         *  reset, the Transmit Jabber Timeout Interrupt is disabled
+         */
+        uint32_t ch1_tje:1;
+        /** ch1_ove : R/W; bitpos: [4]; default: 0;
+         *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+         *  the Overflow Interrupt is disabled
+         */
+        uint32_t ch1_ove:1;
+        /** ch1_une : R/W; bitpos: [5]; default: 0;
+         *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+         *  reset, the Underflow Interrupt is disabled
+         */
+        uint32_t ch1_une:1;
+        /** ch1_rie : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+         *  Interrupt is disabled
+         */
+        uint32_t ch1_rie:1;
+        /** ch1_rue : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t ch1_rue:1;
+        /** ch1_rse : R/W; bitpos: [8]; default: 0;
+         *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+         *  Receive Stopped Interrupt is disabled
+         */
+        uint32_t ch1_rse:1;
+        /** ch1_rwe : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+         *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+         */
+        uint32_t ch1_rwe:1;
+        /** ch1_ete : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+         *  reset, the Early Transmit Interrupt is disabled
+         */
+        uint32_t ch1_ete:1;
+        uint32_t reserved_11:2;
+        /** ch1_fbe : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+         *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+         */
+        uint32_t ch1_fbe:1;
+        /** ch1_ere : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+         *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+         *  Early Receive Interrupt is disabled
+         */
+        uint32_t ch1_ere:1;
+        /** ch1_aie : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+         *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+         *  bit enables the following interrupts in Register 5 _Status Register_: Register
+         *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+         *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+         *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+         *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+         *  Error
+         */
+        uint32_t ch1_aie:1;
+        /** ch1_nie : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+         *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+         *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+         *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+         *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+         */
+        uint32_t ch1_nie:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} gmac_register71_channel1interruptenableregister_reg_t;
+
+/** Type of register72_channel1missedframeandbufferoverflowcounterregister register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available, and discarded frames because of Receive FIFO Overflow
+ */
+typedef union {
+    struct {
+        /** ch1_misfrmcnt : R/W; bitpos: [15:0]; default: 0;
+         *  Missed Frame Counter This field indicates the number of frames missed by the
+         *  controller because of the Host Receive Buffer being unavailable This counter is
+         *  incremented each time the DMA discards an incoming frame The counter is cleared
+         *  when this register is read with mci_be_i[0] at 1’b1
+         */
+        uint32_t ch1_misfrmcnt:16;
+        /** ch1_miscntovf : R/W; bitpos: [16]; default: 0;
+         *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+         *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+         *  of the Host Receive Buffer being unavailable with the missed frame counter at
+         *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+         *  this bit indicates that the rollover happened
+         */
+        uint32_t ch1_miscntovf:1;
+        /** ch1_ovffrmcnt : R/W; bitpos: [27:17]; default: 0;
+         *  Overflow Frame Counter This field indicates the number of frames missed by the
+         *  application This counter is incremented each time the MTL FIFO overflows The
+         *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+         */
+        uint32_t ch1_ovffrmcnt:11;
+        /** ch1_ovfcntovf : R/W; bitpos: [28]; default: 0;
+         *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+         *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+         *  overflow frame counter at maximum value In such a scenario, the overflow frame
+         *  counter is reset to allzeros and this bit indicates that the rollover happened
+         */
+        uint32_t ch1_ovfcntovf:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register72_channel1missedframeandbufferoverflowcounterregister_reg_t;
+
+/** Type of register73_channel1receiveinterruptwatchdogtimerregister register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+typedef union {
+    struct {
+        /** ch1_riwt : R/W; bitpos: [7:0]; default: 0;
+         *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+         *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+         *  triggered with the programmed value after the Rx DMA completes the transfer of a
+         *  frame for which the RI status bit is not set because of the setting in the
+         *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+         *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+         *  high because of automatic setting of RI as per RDES1[31] of any received frame
+         */
+        uint32_t ch1_riwt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gmac_register73_channel1receiveinterruptwatchdogtimerregister_reg_t;
+
+/** Type of register76_channel1slotfunctioncontrolandstatusregister register
+ *  Contains the control bits for slot function and its status for Channel 1 transmit
+ *  path
+ */
+typedef union {
+    struct {
+        /** esc : R/W; bitpos: [0]; default: 0;
+         *  Enable Slot Comparison When set, this bit enables the checking of the slot numbers,
+         *  programmed in the transmit descriptor, with the current reference given in Bits
+         *  [19:16] The DMA fetches the data from the corresponding buffer only when the slot
+         *  number is equal to the reference slot number or is ahead of the reference slot
+         *  number by one slot When reset, this bit disables the checking of the slot numbers
+         *  The DMA fetches the data immediately after the descriptor is processed
+         */
+        uint32_t esc:1;
+        /** asc : R/W; bitpos: [1]; default: 0;
+         *  Advance Slot Check When set, this bit enables the DMA to fetch the data from the
+         *  buffer when the slot number _SLOTNUM_ programmed in the transmit descriptor is:
+         *  equal to the reference slot number given in Bits [19:16] or ahead of the reference
+         *  slot number by up to two slots This bit is applicable only when Bit 0 _ESC_ is set
+         */
+        uint32_t asc:1;
+        uint32_t reserved_2:14;
+        /** rsn : RO; bitpos: [19:16]; default: 0;
+         *  Reference Slot Number This field gives the current value of the reference slot
+         *  number in DMA used for comparison checking
+         */
+        uint32_t rsn:4;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gmac_register76_channel1slotfunctioncontrolandstatusregister_reg_t;
+
+/** Type of register82_channel1currenthosttransmitdescriptorregister register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch1_curtdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Descriptor Address Pointer
+         */
+        uint32_t ch1_curtdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register82_channel1currenthosttransmitdescriptorregister_reg_t;
+
+/** Type of register83_channel1currenthostreceivedescriptorregister register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch1_currdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Descriptor Address Pointer
+         */
+        uint32_t ch1_currdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register83_channel1currenthostreceivedescriptorregister_reg_t;
+
+/** Type of register84_channel1currenthosttransmitbufferaddressregister register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch1_curtbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Buffer Address Pointer
+         */
+        uint32_t ch1_curtbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register84_channel1currenthosttransmitbufferaddressregister_reg_t;
+
+/** Type of register85_channel1currenthostreceivebufferaddressregister register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch1_currbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Buffer Address Pointer
+         */
+        uint32_t ch1_currbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register85_channel1currenthostreceivebufferaddressregister_reg_t;
+
+/** Type of register88_channel1cbscontrolregister register
+ *  Controls the Channel 1 credit shaping operation on the transmit path
+ */
+typedef union {
+    struct {
+        /** ch1_cbsd : R/W; bitpos: [0]; default: 0;
+         *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+         *  algorithm for Channel 1 traffic and makes the traffic management algorithm to
+         *  strict priority for Channel 1 over Channel 0 When reset, the creditbased shaper
+         *  algorithm schedules the traffic in Channel 1 for transmission
+         */
+        uint32_t ch1_cbsd:1;
+        /** ch1_cc : R/W; bitpos: [1]; default: 0;
+         *  Credit Control When reset, the accumulated credit parameter in the creditbased
+         *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+         *  transmit in Channel 1 When there is no frame waiting in Channel 1 and other channel
+         *  is transmitting, no credit is accumulated When set, the accumulated credit
+         *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+         *  is positive credit and no frame to transmit in Channel 1 The credit accumulates
+         *  even when there is no frame waiting in Channel 1 and another channel is transmitting
+         */
+        uint32_t ch1_cc:1;
+        uint32_t reserved_2:2;
+        /** ch1_slc : R/W; bitpos: [6:4]; default: 0;
+         *  Slot Count The software can program the number of slots _of duration 125 microsec_
+         *  over which the average transmitted bits per slot _provided in the CBS Status
+         *  register_ need to be computed for Channel 1 when the creditbased shaper algorithm
+         *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+         *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+         */
+        uint32_t ch1_slc:3;
+        uint32_t reserved_7:10;
+        /** ch1_abpssie : R/W; bitpos: [17]; default: 0;
+         *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+         *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+         *  updated _Bit 17 _ABSU_ in Register 89_ for Channel 1 When this bit is cleared,
+         *  interrupt is not asserted for such an event
+         */
+        uint32_t ch1_abpssie:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gmac_register88_channel1cbscontrolregister_reg_t;
+
+/** Type of register89_channel1cbsstatusregister register
+ *  Provides the average traffic transmitted in Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_abs : RO; bitpos: [16:0]; default: 0;
+         *  Average Bits per Slot This field contains the average transmitted bits per slot
+         *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+         *  Register_ for Channel 1 traffic The maximum value is 0x30D4 for 100 Mbps and
+         *  0x1E848 for 1000 Mbps
+         */
+        uint32_t ch1_abs:17;
+        /** ch1_absu : RO; bitpos: [17]; default: 0;
+         *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+         *  This bit is cleared when the application reads the ABS value
+         */
+        uint32_t ch1_absu:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gmac_register89_channel1cbsstatusregister_reg_t;
+
+/** Type of register90_channel1idleslopecreditregister register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_isc : R/W; bitpos: [13:0]; default: 0;
+         *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+         *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+         *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+         *  credit is increasing The software should program this field with computed credit in
+         *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+         *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+         */
+        uint32_t ch1_isc:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} gmac_register90_channel1idleslopecreditregister_reg_t;
+
+/** Type of register91_channel1sendslopecreditregister register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_ssc : R/W; bitpos: [13:0]; default: 0;
+         *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+         *  creditbased shaper algorithm for Channel 1 This is the rate of change of credit in
+         *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+         *  credit is decreasing The software should program this field with computed credit in
+         *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+         *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+         *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+         *  subtracts it from the accumulated credit when Channel 1 is selected for transmission
+         */
+        uint32_t ch1_ssc:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} gmac_register91_channel1sendslopecreditregister_reg_t;
+
+/** Type of register92_channel1hicreditregister register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_hc : R/W; bitpos: [28:0]; default: 0;
+         *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+         *  algorithm for Channel 1 This is the maximum value that can be accumulated in the
+         *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+         *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+         *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+         *  0x0800_0000
+         */
+        uint32_t ch1_hc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register92_channel1hicreditregister_reg_t;
+
+/** Type of register93_channel1locreditregister register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 1
+ */
+typedef union {
+    struct {
+        /** ch1_lc : R/W; bitpos: [28:0]; default: 536870911;
+         *  loCredit This field contains the loCredit value required for the creditbased shaper
+         *  algorithm for Channel 1 This is the minimum value that can be accumulated in the
+         *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+         *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+         *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+         *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+         *  0xF800_0000
+         */
+        uint32_t ch1_lc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register93_channel1locreditregister_reg_t;
+
+/** Type of register128_channel2busmoderegister register
+ *  Controls the Host Interface mode for Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_swr : R/W; bitpos: [0]; default: 1;
+         *  Software Reset When this bit is set, the MAC DMA Controller resets the logic and
+         *  all internal registers of the MAC It is cleared automatically after the reset
+         *  operation is complete in all of the DWC_gmac clock domains Before reprogramming any
+         *  register of the DWC_gmac, you should read a zero _0_ value in this bit Note: The
+         *  Software reset function is driven only by this bit Bit 0 of Register 64 _Channel 1
+         *  Bus Mode Register_ or Register 128 _Channel 2 Bus Mode Register_ has no impact on
+         *  the Software reset function The reset operation is completed only when all resets
+         *  in all active clock domains are deasserted Therefore, it is essential that all PHY
+         *  inputs clocks _applicable for the selected PHY interface_ are present for the
+         *  software reset completion The time to complete the software reset operation depends
+         *  on the frequency of the slowest active clock
+         */
+        uint32_t ch2_swr:1;
+        /** ch2_da : R/W; bitpos: [1]; default: 0;
+         *  DMA Arbitration Scheme This bit specifies the arbitration scheme between the
+         *  transmit and receive paths of Channel 2 0: Weighted roundrobin with Rx:Tx or Tx:Rx
+         *  The priority between the paths is according to the priority specified in Bits
+         *  [15:14] _PR_ and priority weights specified in Bit 27 _TXPR_ 1: Fixed priority The
+         *  transmit path has priority over receive path when Bit 27 _TXPR_ is set Otherwise,
+         *  receive path has priority over the transmit path In the GMACAXI configuration,
+         *  these bits are reserved and are readonly _RO_ For more information about the
+         *  priority scheme between the transmit and receive paths, see Table 412 in “DMA
+         *  Arbiter Functions” on page 167
+         */
+        uint32_t ch2_da:1;
+        /** ch2_dsl : R/W; bitpos: [6:2]; default: 0;
+         *  Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword
+         *  _depending on the 32bit, 64bit, or 128bit bus_ to skip between two unchained
+         *  descriptors The address skipping starts from the end of current descriptor to the
+         *  start of next descriptor When the DSL value is equal to zero, the descriptor table
+         *  is taken as contiguous by the DMA in Ring mode
+         */
+        uint32_t ch2_dsl:5;
+        /** ch2_atds : R/W; bitpos: [7]; default: 0;
+         *  Alternate Descriptor Size When set, the size of the alternate descriptor _described
+         *  in “Alternate or Enhanced Descriptors” on page 545_ increases to 32 bytes _8
+         *  DWORDS_ This is required when the Advanced Timestamp feature or the IPC Full
+         *  Checksum Offload Engine _Type 2_ is enabled in the receiver The enhanced descriptor
+         *  is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine
+         *  _Type 2_ features are not enabled In such case, you can use the 16 bytes descriptor
+         *  to save 4 bytes of memory This bit is present only when you select the Alternate
+         *  Descriptor feature and any one of the following features during core configuration:
+         *  Advanced Timestamp feature IPC Full Checksum Offload Engine _Type 2_ feature
+         *  Otherwise, this bit is reserved and is readonly When reset, the descriptor size
+         *  reverts back to 4 DWORDs _16 bytes_ This bit preserves the backward compatibility
+         *  for the descriptor size In versions prior to 350a, the descriptor size is 16 bytes
+         *  for both normal and enhanced descriptors In version 350a, descriptor size is
+         *  increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum
+         *  Offload Engine _Type 2_ features
+         */
+        uint32_t ch2_atds:1;
+        /** ch2_pbl : R/W; bitpos: [13:8]; default: 1;
+         *  Programmable Burst Length These bits indicate the maximum number of beats to be
+         *  transferred in one DMA transaction This is the maximum value that is used in a
+         *  single block Read or Write The DMA always attempts to burst as specified in PBL
+         *  each time it starts a Burst transfer on the host bus PBL can be programmed with
+         *  permissible values of 1, 2, 4, 8, 16, and 32 Any other value results in undefined
+         *  behavior When USP is set high, this PBL value is applicable only for Tx DMA
+         *  transactions If the number of beats to be transferred is more than 32, then perform
+         *  the following steps: 1 Set the PBLx8 mode 2 Set the PBL For example, if the maximum
+         *  number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL
+         *  to 8 The PBL values have the following limitation: The maximum number of possible
+         *  beats _PBL_ is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and
+         *  the data bus width on the DMA The FIFO has a constraint that the maximum beat
+         *  supported is half the depth of the FIFO, except when specified For different data
+         *  bus widths and FIFO sizes, the valid PBL range _including x8 mode_ is provided in
+         *  Table 66 on page 382
+         */
+        uint32_t ch2_pbl:6;
+        /** ch2_pr : R/W; bitpos: [15:14]; default: 0;
+         *  Priority Ratio These bits control the priority ratio in the weighted roundrobin
+         *  arbitration between the Rx DMA and Tx DMA These bits are valid only when Bit 1 _DA_
+         *  is reset The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 _TXPR_ is
+         *  reset or set 00: The Priority Ratio is 1:1 01: The Priority Ratio is 2:1 10: The
+         *  Priority Ratio is 3:1 11: The Priority Ratio is 4:1 In the GMACAXI configuration,
+         *  these bits are reserved and readonly _RO_ For more information about the priority
+         *  scheme between the transmit and receive paths, see Table 412 in “DMA Arbiter
+         *  Functions” on page 167
+         */
+        uint32_t ch2_pr:2;
+        /** ch2_fb : R/W; bitpos: [16]; default: 0;
+         *  Fixed Burst This bit controls whether the AHB or AXI master interface performs
+         *  fixed burst transfers or not When set, the AHB interface uses only SINGLE, INCR4,
+         *  INCR8, or INCR16 during start of the normal burst transfers When reset, the AHB or
+         *  AXI interface uses SINGLE and INCR burst transfer operations For more information,
+         *  see Bit 0 _UNDEF_ of the AXI Bus Mode register in the GMACAXI configuration
+         */
+        uint32_t ch2_fb:1;
+        /** ch2_rpbl : R/W; bitpos: [22:17]; default: 1;
+         *  Rx DMA PBL This field indicates the maximum number of beats to be transferred in
+         *  one Rx DMA transaction This is the maximum value that is used in a single block
+         *  Read or Write The Rx DMA always attempts to burst as specified in the RPBL bit each
+         *  time it starts a Burst transfer on the host bus You can program RPBL with values of
+         *  1, 2, 4, 8, 16, and 32 Any other value results in undefined behavior This field is
+         *  valid and applicable only when USP is set high
+         */
+        uint32_t ch2_rpbl:6;
+        /** ch2_usp : R/W; bitpos: [23]; default: 0;
+         *  Use Separate PBL When set high, this bit configures the Rx DMA to use the value
+         *  configured in Bits [22:17] as PBL The PBL value in Bits [13:8] is applicable only
+         *  to the Tx DMA operations When reset to low, the PBL value in Bits [13:8] is
+         *  applicable for both DMA engines
+         */
+        uint32_t ch2_usp:1;
+        /** ch2_pblx8 : R/W; bitpos: [24]; default: 0;
+         *  PBLx8 Mode When set high, this bit multiplies the programmed PBL value _Bits
+         *  [22:17] and Bits[13:8]_ eight times Therefore, the DMA transfers the data in 8, 16,
+         *  32, 64, 128, and 256 beats depending on the PBL value Note: This bit function is
+         *  not backward compatible Before release 350a, this bit was 4xPBL
+         */
+        uint32_t ch2_pblx8:1;
+        /** ch2_aal : R/W; bitpos: [25]; default: 0;
+         *  AddressAligned Beats When this bit is set high and the FB bit is equal to 1, the
+         *  AHB or AXI interface generates all bursts aligned to the start address LS bits If
+         *  the FB bit is equal to 0, the first burst _accessing the start address of data
+         *  buffer_ is not aligned, but subsequent bursts are aligned to the address This bit
+         *  is valid only in the GMACAHB and GMACAXI configurations and is reserved _RO with
+         *  default value 0_ in all other configurations
+         */
+        uint32_t ch2_aal:1;
+        /** ch2_mb : R/W; bitpos: [26]; default: 0;
+         *  Mixed Burst When this bit is set high and the FB bit is low, the AHB master
+         *  interface starts all bursts of length more than 16 with INCR _undefined burst_,
+         *  whereas it reverts to fixed burst transfers _INCRx and SINGLE_ for burst length of
+         *  16 and less This bit is valid only in the GMACAHB configuration and reserved in all
+         *  other configuration
+         */
+        uint32_t ch2_mb:1;
+        /** ch2_txpr : R/W; bitpos: [27]; default: 0;
+         *  Transmit Priority When set, this bit indicates that the transmit DMA has higher
+         *  priority than the receive DMA during arbitration for the systemside bus In the
+         *  GMACAXI configuration, this bit is reserved and readonly _RO_ For more information
+         *  about the priority scheme between the transmit and receive paths, see Table 412 in
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t ch2_txpr:1;
+        /** ch2_prwg : R/W; bitpos: [29:28]; default: 0;
+         *  Channel Priority Weights This field sets the priority weights for Channel 2 during
+         *  the roundrobin arbitration between the DMA channels for the system bus 00: The
+         *  priority weight is 1 01: The priority weight is 2 10: The priority weight is 3 11:
+         *  The priority weight is 4 This field is present in all DWC_gmac configurations
+         *  except GMACAXI when you select the AV feature Otherwise, this field is reserved and
+         *  readonly _RO_ For more information about the priority weights of DMA channels, see
+         *  “DMA Arbiter Functions” on page 167
+         */
+        uint32_t ch2_prwg:2;
+        uint32_t reserved_30:1;
+        /** ch2_rib : R/W; bitpos: [31]; default: 0;
+         *  Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT
+         *  _Retry, Split, or Losing bus grant_, the AHB master interface rebuilds the pending
+         *  beats of any burst transfer initiated with INCRx The AHB master interface rebuilds
+         *  the beats with a combination of specified bursts with INCRx and SINGLE By default,
+         *  the AHB master interface rebuilds pending beats of an EBT with an unspecified
+         *  _INCR_ burst This bit is valid only in the GMACAHB configuration It is reserved in
+         *  all other configuration
+         */
+        uint32_t ch2_rib:1;
+    };
+    uint32_t val;
+} gmac_register128_channel2busmoderegister_reg_t;
+
+/** Type of register129_channel2transmitpolldemandregister register
+ *  Used by the host to instruct the DMA to poll the Transmit Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch2_tpd : RO; bitpos: [31:0]; default: 0;
+         *  Transmit Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 18 _Current Host Transmit Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  transmission returns to the Suspend state and Bit 2 _TU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the transmission resumes
+         */
+        uint32_t ch2_tpd:32;
+    };
+    uint32_t val;
+} gmac_register129_channel2transmitpolldemandregister_reg_t;
+
+/** Type of register130_channel2receivepolldemandregister register
+ *  Used by the Host to instruct the DMA to poll the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch2_rpd : RO; bitpos: [31:0]; default: 0;
+         *  Receive Poll Demand When these bits are written with any value, the DMA reads the
+         *  current descriptor to which the Register 19 _Current Host Receive Descriptor
+         *  Register_ is pointing If that descriptor is not available _owned by the Host_, the
+         *  reception returns to the Suspended state and Bit 7 _RU_ of Register 5 _Status
+         *  Register_ is asserted If the descriptor is available, the Rx DMA returns to the
+         *  active state
+         */
+        uint32_t ch2_rpd:32;
+    };
+    uint32_t val;
+} gmac_register130_channel2receivepolldemandregister_reg_t;
+
+/** Type of register131_channel2receivedescriptorlistaddressregister register
+ *  Points the DMA to the start of the Receive Descriptor list
+ */
+typedef union {
+    struct {
+        /** ch2_rdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Receive List This field contains the base address of the first descriptor
+         *  in the Receive Descriptor list The LSB bits _1:0, 2:0, or 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and internally taken as allzero by the DMA Therefore,
+         *  these LSB bits are readonly _RO_
+         */
+        uint32_t ch2_rdesla:32;
+    };
+    uint32_t val;
+} gmac_register131_channel2receivedescriptorlistaddressregister_reg_t;
+
+/** Type of register132_channel2transmitdescriptorlistaddressregister register
+ *  Points the DMA to the start of the Transmit Descriptor List
+ */
+typedef union {
+    struct {
+        /** ch2_tdesla : R/W; bitpos: [31:0]; default: 0;
+         *  Start of Transmit List This field contains the base address of the first descriptor
+         *  in the Transmit Descriptor list The LSB bits _1:0, 2:0, 3:0_ for 32bit, 64bit, or
+         *  128bit bus width are ignored and are internally taken as allzero by the DMA
+         *  Therefore, these LSB bits are readonly _RO_
+         */
+        uint32_t ch2_tdesla:32;
+    };
+    uint32_t val;
+} gmac_register132_channel2transmitdescriptorlistaddressregister_reg_t;
+
+/** Type of register133_channel2statusregister register
+ *  The software driver _application_ reads this register during interrupt service
+ *  routine or polling to determine the status of the DMA Bits [29:26] are reserved for
+ *  the Channel 2 Status Register
+ */
+typedef union {
+    struct {
+        /** ch2_ti : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt This bit indicates that the frame transmission is complete When
+         *  transmission is complete, Bit 31 _OWN_ of TDES0 is reset, and the specific frame
+         *  status information is updated in the descriptor
+         */
+        uint32_t ch2_ti:1;
+        /** ch2_tps : R/W; bitpos: [1]; default: 0;
+         *  Transmit Process Stopped This bit is set when the transmission is stopped
+         */
+        uint32_t ch2_tps:1;
+        /** ch2_tu : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Transmit List and the DMA cannot acquire it Transmission is
+         *  suspended Bits[22:20] explain the Transmit Process state transitions To resume
+         *  processing Transmit descriptors, the host should change the ownership of the
+         *  descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command
+         */
+        uint32_t ch2_tu:1;
+        /** ch2_tjt : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired,
+         *  which happens when the frame size exceeds 2,048 _10,240 bytes when the Jumbo frame
+         *  is enabled_ When the Jabber Timeout occurs, the transmission process is aborted and
+         *  placed in the Stopped state This causes the Transmit Jabber Timeout TDES0[14] flag
+         *  to assert
+         */
+        uint32_t ch2_tjt:1;
+        /** ch2_ovf : R/W; bitpos: [4]; default: 0;
+         *  Receive Overflow This bit indicates that the Receive Buffer had an Overflow during
+         *  frame reception If the partial frame is transferred to the application, the
+         *  overflow status is set in RDES0[11]
+         */
+        uint32_t ch2_ovf:1;
+        /** ch2_unf : R/W; bitpos: [5]; default: 0;
+         *  Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow
+         *  during frame transmission Transmission is suspended and an Underflow Error TDES0[1]
+         *  is set
+         */
+        uint32_t ch2_unf:1;
+        /** ch2_ri : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt This bit indicates that the frame reception is complete When
+         *  reception is complete, the Bit 31 of RDES1 _Disable Interrupt on Completion_ is
+         *  reset in the last Descriptor, and the specific frame status information is updated
+         *  in the descriptor The reception remains in the Running state
+         */
+        uint32_t ch2_ri:1;
+        /** ch2_ru : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable This bit indicates that the host owns the Next
+         *  Descriptor in the Receive List and the DMA cannot acquire it The Receive Process is
+         *  suspended To resume processing Receive descriptors, the host should change the
+         *  ownership of the descriptor and issue a Receive Poll Demand command If no Receive
+         *  Poll Demand is issued, the Receive Process resumes when the next recognized
+         *  incoming frame is received This bit is set only when the previous Receive
+         *  Descriptor is owned by the DMA
+         */
+        uint32_t ch2_ru:1;
+        /** ch2_rps : R/W; bitpos: [8]; default: 0;
+         *  Receive Process Stopped This bit is asserted when the Receive Process enters the
+         *  Stopped state
+         */
+        uint32_t ch2_rps:1;
+        /** ch2_rwt : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog
+         *  Timer expired while receiving the current frame and the current frame is truncated
+         *  after the watchdog timeout
+         */
+        uint32_t ch2_rwt:1;
+        /** ch2_eti : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt This bit indicates that the frame to be transmitted is
+         *  fully transferred to the MTL Transmit FIFO
+         */
+        uint32_t ch2_eti:1;
+        uint32_t reserved_11:2;
+        /** ch2_fbi : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as
+         *  described in Bits [25:23] When this bit is set, the corresponding DMA engine
+         *  disables all of its bus accesses 12:11		Reserved	00	RO
+         */
+        uint32_t ch2_fbi:1;
+        /** ch2_eri : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt This bit indicates that the DMA filled the first data
+         *  buffer of the packet This bit is cleared when the software writes 1 to this bit or
+         *  Bit 6 _RI_ of this register is set _whichever occurs earlier_
+         */
+        uint32_t ch2_eri:1;
+        /** ch2_ais : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR
+         *  of the following when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[1]: Transmit Process Stopped Register 5[3]:
+         *  Transmit Jabber Timeout Register 5[4]: Receive FIFO Overflow Register 5[5]:
+         *  Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive
+         *  Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early
+         *  Transmit Interrupt Register 5[13]: Fatal Bus Error Only unmasked bits affect the
+         *  Abnormal Interrupt Summary bit This is a sticky bit and must be cleared _by writing
+         *  1 to this bit_ each time a corresponding bit, which causes AIS to be set, is cleared
+         */
+        uint32_t ch2_ais:1;
+        /** ch2_nis : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of
+         *  the following bits when the corresponding interrupt bits are enabled in Register 7
+         *  _Interrupt Enable Register_: Register 5[0]: Transmit Interrupt Register 5[2]:
+         *  Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early
+         *  Receive Interrupt Only unmasked bits _interrupts for which interrupt enable is set
+         *  in Register 7_ affect the Normal Interrupt Summary bit This is a sticky bit and
+         *  must be cleared _by writing 1 to this bit_ each time a corresponding bit, which
+         *  causes NIS to be set, is cleared
+         */
+        uint32_t ch2_nis:1;
+        /** ch2_rs : RO; bitpos: [19:17]; default: 0;
+         *  Receive Process State This field indicates the Receive DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Receive Command
+         *  issued 3’b001: Running: Fetching Receive Transfer Descriptor 3’b010: Reserved for
+         *  future use 3’b011: Running: Waiting for receive packet 3’b100: Suspended: Receive
+         *  Descriptor Unavailable 3’b101: Running: Closing Receive Descriptor 3’b110:
+         *  TIME_STAMP write state 3’b111: Running: Transferring the receive packet data from
+         *  receive buffer to host memory
+         */
+        uint32_t ch2_rs:3;
+        /** ch2_ts : RO; bitpos: [22:20]; default: 0;
+         *  Transmit Process State This field indicates the Transmit DMA FSM state This field
+         *  does not generate an interrupt 3’b000: Stopped: Reset or Stop Transmit Command
+         *  issued 3’b001: Running: Fetching Transmit Transfer Descriptor 3’b010: Running:
+         *  Waiting for status 3’b011: Running: Reading Data from host memory buffer and
+         *  queuing it to transmit buffer _Tx FIFO_ 3’b100: TIME_STAMP write state 3’b101:
+         *  Reserved for future use 3’b110: Suspended: Transmit Descriptor Unavailable or
+         *  Transmit Buffer Underflow 3’b111: Running: Closing Transmit Descriptor
+         */
+        uint32_t ch2_ts:3;
+        /** ch2_eb : RO; bitpos: [25:23]; default: 0;
+         *  Error Bits This field indicates the type of error that caused a Bus Error, for
+         *  example, error response on the AHB or AXI interface This field is valid only when
+         *  Bit 13 _FBI_ is set This field does not generate an interrupt 0 0 0: Error during
+         *  Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0:
+         *  Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor
+         *  Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during
+         *  Tx DMA Descriptor Read Access Note: 001 and 010 are reserved
+         */
+        uint32_t ch2_eb:3;
+        /** ch2_gli : RO; bitpos: [26]; default: 0;
+         *  GMAC Line Interface Interrupt When set, this bit reflects any of the following
+         *  interrupt events in the DWC_gmac interfaces _if present and enabled in your
+         *  configuration_: PCS _TBI, RTBI, or SGMII_: Link change or autonegotiation complete
+         *  event SMII or RGMII: Link change event General Purpose Input Status _GPIS_: Any LL
+         *  or LH event on the gpi_i input ports To identify the exact cause of the interrupt,
+         *  the software must first read Bit 11 and Bits[2:0] of Register 14 _Interrupt Status
+         *  Register_ and then to clear the source of interrupt _which also clears the GLI
+         *  interrupt_, read any of the following corresponding registers: PCS _TBI, RTBI, or
+         *  SGMII_: Register 49 _AN Status Register_ SMII or RGMII: Register 54
+         *  _SGMII/RGMII/SMII Control and Status Register_ General Purpose Input _GPI_:
+         *  Register 56 _General Purpose IO Register_ The interrupt signal from the DWC_gmac
+         *  subsystem _sbd_intr_o_ is high when this bit is high
+         */
+        uint32_t ch2_gli:1;
+        /** ch2_gmi : RO; bitpos: [27]; default: 0;
+         *  GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the
+         *  DWC_gmac The software must read the corresponding registers in the DWC_gmac to get
+         *  the exact cause of the interrupt and clear the source of interrupt to make this bit
+         *  as 1’b0 The interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when
+         *  this bit is high This bit is applicable only when the MAC Management Counters _MMC_
+         *  are enabled Otherwise, this bit is reserved
+         */
+        uint32_t ch2_gmi:1;
+        /** ch2_gpi : RO; bitpos: [28]; default: 0;
+         *  GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the
+         *  DWC_gmac The software must read the PMT Control and Status Register in the MAC to
+         *  get the exact cause of interrupt and clear its source to reset this bit to 1’b0 The
+         *  interrupt signal from the DWC_gmac subsystem _sbd_intr_o_ is high when this bit is
+         *  high This bit is applicable only when the Power Management feature is enabled
+         *  Otherwise, this bit is reserved Note: The GPI and pmt_intr_o interrupts are
+         *  generated in different clock domains
+         */
+        uint32_t ch2_gpi:1;
+        /** ch2_tti : RO; bitpos: [29]; default: 0;
+         *  Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp
+         *  Generator block of the DWC_gmac The software must read the corresponding registers
+         *  in the DWC_gmac to get the exact cause of the interrupt and clear its source to
+         *  reset this bit to 1'b0 When this bit is high, the interrupt signal from the
+         *  DWC_gmac subsystem _sbd_intr_o_ is high This bit is applicable only when the IEEE
+         *  1588 Timestamp feature is enabled Otherwise, this bit is reserved
+         */
+        uint32_t ch2_tti:1;
+        /** ch2_glpii_gtmsi : RO; bitpos: [30]; default: 0;
+         *  GTMSI: GMAC TMS Interrupt _for Channel 1 and Channel 2_ This bit indicates an
+         *  interrupt event in the traffic manager and scheduler logic of DWC_gmac To reset
+         *  this bit, the software must read the corresponding registers _Channel Status
+         *  Register_ to get the exact cause of the interrupt and clear its source Note: GTMSI
+         *  status is given only in Channel 1 and Channel 2 DMA register when the AV feature is
+         *  enabled and corresponding additional transmit channels are present Otherwise, this
+         *  bit is reserved When this bit is high, the interrupt signal from the MAC
+         *  _sbd_intr_o_ is high
+         */
+        uint32_t ch2_glpii_gtmsi:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} gmac_register133_channel2statusregister_reg_t;
+
+/** Type of register134_channel2operationmoderegister register
+ *  Establishes the Receive and Transmit operating modes and command
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** ch2_sr : R/W; bitpos: [1]; default: 0;
+         *  Start or Stop Receive When this bit is set, the Receive process is placed in the
+         *  Running state The DMA attempts to acquire the descriptor from the Receive list and
+         *  processes the incoming frames The descriptor acquisition is attempted from the
+         *  current position in the list, which is the address set by the Register 3 _Receive
+         *  Descriptor List Address Register_ or the position retained when the Receive process
+         *  was previously stopped If the DMA does not own the descriptor, reception is
+         *  suspended and Bit 7 _Receive Buffer Unavailable_ of Register 5 _Status Register_ is
+         *  set The Start Receive command is effective only when the reception has stopped If
+         *  the command is issued before setting Register 3 _Receive Descriptor List Address
+         *  Register_, the DMA behavior is unpredictable When this bit is cleared, the Rx DMA
+         *  operation is stopped after the transfer of the current frame The next descriptor
+         *  position in the Receive list is saved and becomes the current position after the
+         *  Receive process is restarted The Stop Receive command is effective only when the
+         *  Receive process is in either the Running _waiting for receive packet_ or in the
+         *  Suspended state Note: For information about how to pause the transmission, see
+         *  “Stopping and Starting Transmission” on page 715
+         */
+        uint32_t ch2_sr:1;
+        /** ch2_osf : R/W; bitpos: [2]; default: 0;
+         *  Operate on Second Frame When this bit is set, it instructs the DMA to process the
+         *  second frame of the Transmit data even before the status for the first frame is
+         *  obtained
+         */
+        uint32_t ch2_osf:1;
+        /** ch2_rtc : R/W; bitpos: [4:3]; default: 0;
+         *  Receive Threshold Control These two bits control the threshold level of the MTL
+         *  Receive FIFO Transfer _request_ to DMA starts when the frame size within the MTL
+         *  Receive FIFO is larger than the threshold In addition, full frames with length less
+         *  than the threshold are automatically transferred The value of 11 is not applicable
+         *  if the configured Receive FIFO size is 128 bytes These bits are valid only when the
+         *  RSF bit is zero, and are ignored when the RSF bit is set to 1 00: 64 01: 32 10: 96
+         *  11: 128
+         */
+        uint32_t ch2_rtc:2;
+        /** ch2_dgf : R/W; bitpos: [5]; default: 0;
+         *  Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO,
+         *  that is, frames that are larger than the computed giant frame limit When reset, the
+         *  MAC does not drop the giant frames in the Rx FIFO Note: This bit is available in
+         *  the following configurations in which the giant frame status is not provided in Rx
+         *  status and giant frames are not dropped by default: Configurations in which IP
+         *  Checksum Offload _Type 1_ is selected in Rx Configurations in which the IPC Full
+         *  Checksum Offload Engine _Type 2_ is selected in Rx with normal descriptor format
+         *  Configurations in which the Advanced Timestamp feature is selected In all other
+         *  configurations, this bit is not used _reserved and always reset_
+         */
+        uint32_t ch2_dgf:1;
+        /** ch2_fuf : R/W; bitpos: [6]; default: 0;
+         *  Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames
+         *  _that is, frames with no Error and length less than 64 bytes_ including padbytes
+         *  and CRC When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a
+         *  frame is already transferred because of the lower value of Receive Threshold, for
+         *  example, RTC = 01
+         */
+        uint32_t ch2_fuf:1;
+        /** ch2_fef : R/W; bitpos: [7]; default: 0;
+         *  Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error
+         *  status _CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or
+         *  overflow_ However, if the start byte _write_ pointer of a frame is already
+         *  transferred to the read controller side _in Threshold mode_, then the frame is not
+         *  dropped In the GMACMTL configuration in which the Frame Length FIFO is also enabled
+         *  during core configuration, the Rx FIFO drops the error frames if that frame's start
+         *  byte is not transferred _output_ on the ARI bus When the FEF bit is set, all frames
+         *  except runt error frames are forwarded to the DMA If the Bit 25 _RSF_ is set and
+         *  the Rx FIFO overflows when a partial frame is written, then the frame is dropped
+         *  irrespective of the FEF bit setting However, if the Bit 25 _RSF_ is reset and the
+         *  Rx FIFO overflows when a partial frame is written, then a partial frame may be
+         *  forwarded to the DMA Note: When FEF bit is reset, the giant frames are dropped if
+         *  the giant frame status is given in Rx Status _in Table 86 or Table 823_ in the
+         *  following configurations: The IP checksum engine _Type 1_ and full checksum offload
+         *  engine _Type 2_ are not selected The advanced timestamp feature is not selected but
+         *  the extended status is selected The extended status is available with the following
+         *  features: 	L3L4 filter in GMACCORE or GMACMTL configurations 	Full checksum offload
+         *  engine _Type 2_ with enhanced descriptor format in the GMACDMA, GMACAHB, or GMACAXI
+         *  configurations
+         */
+        uint32_t ch2_fef:1;
+        /** ch2_efc : R/W; bitpos: [8]; default: 0;
+         *  Enable HW Flow Control When this bit is set, the flow control signal operation
+         *  based on the filllevel of Rx FIFO is enabled When reset, the flow control operation
+         *  is disabled This bit is not used _reserved and always reset_ when the Rx FIFO is
+         *  less than 4 KB
+         */
+        uint32_t ch2_efc:1;
+        /** ch2_rfa : R/W; bitpos: [10:9]; default: 0;
+         *  Threshold for Activating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Fill level of Rx FIFO_ at which the flow control is
+         *  activated 00: Full minus 1 KB, that is, FULL—1KB 01: Full minus 2 KB, that is,
+         *  FULL—2KB 10: Full minus 3 KB, that is, FULL—3KB 11: Full minus 4 KB, that is,
+         *  FULL—4KB These values are applicable only to Rx FIFOs of 4 KB or more and when Bit
+         *  8 _EFC_ is set high If the Rx FIFO is 8 KB or more, an additional Bit _RFA_2_ is
+         *  used for more threshold levels as described in Bit 23 These bits are reserved and
+         *  readonly when the depth of Rx FIFO is less than 4 KB Note: When FIFO size is
+         *  exactly 4 KB, although the DWC_gmac allows you to program the value of these bits
+         *  to 11, the software should not program these bits to 2'b11 The value 2'b11 means
+         *  flow control on FIFO empty condition
+         */
+        uint32_t ch2_rfa:2;
+        /** ch2_rfd : R/W; bitpos: [12:11]; default: 0;
+         *  Threshold for Deactivating Flow Control _in halfduplex and fullduplex modes_ These
+         *  bits control the threshold _Filllevel of Rx FIFO_ at which the flow control is
+         *  deasserted after activation 00: Full minus 1 KB, that is, FULL — 1 KB 01: Full
+         *  minus 2 KB, that is, FULL — 2 KB 10: Full minus 3 KB, that is, FULL — 3 KB 11: Full
+         *  minus 4 KB, that is, FULL — 4 KB The deassertion is effective only after flow
+         *  control is asserted If the Rx FIFO is 8 KB or more, an additional Bit _RFD_2_ is
+         *  used for more threshold levels as described in Bit 22 These bits are reserved and
+         *  readonly when the Rx FIFO depth is less than 4 KB Note: For proper flow control,
+         *  the value programmed in the “RFD_2, RFD” fields should be equal to or more than the
+         *  value programmed in the “RFA_2, RFA” fields
+         */
+        uint32_t ch2_rfd:2;
+        /** ch2_st : R/W; bitpos: [13]; default: 0;
+         *  Start or Stop Transmission Command When this bit is set, transmission is placed in
+         *  the Running state, and the DMA checks the Transmit List at the current position for
+         *  a frame to be transmitted Descriptor acquisition is attempted either from the
+         *  current position in the list, which is the Transmit List Base Address set by
+         *  Register 4 _Transmit Descriptor List Address Register_, or from the position
+         *  retained when transmission was stopped previously If the DMA does not own the
+         *  current descriptor, transmission enters the Suspended state and Bit 2 _Transmit
+         *  Buffer Unavailable_ of Register 5 _Status Register_ is set The Start Transmission
+         *  command is effective only when transmission is stopped If the command is issued
+         *  before setting Register 4 _Transmit Descriptor List Address Register_, then the DMA
+         *  behavior is unpredictable When this bit is reset, the transmission process is
+         *  placed in the Stopped state after completing the transmission of the current frame
+         *  The Next Descriptor position in the Transmit List is saved, and it becomes the
+         *  current position when transmission is restarted To change the list address, you
+         *  need to program Register 4 _Transmit Descriptor List Address Register_ with a new
+         *  value when this bit is reset The new value is considered when this bit is set again
+         *  The stop transmission command is effective only when the transmission of the
+         *  current frame is complete or the transmission is in the Suspended state Note: For
+         *  information about how to pause the transmission, see “Stopping and Starting
+         *  Transmission” on page 715
+         */
+        uint32_t ch2_st:1;
+        /** ch2_ttc : R/W; bitpos: [16:14]; default: 0;
+         *  Transmit Threshold Control These bits control the threshold level of the MTL
+         *  Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO
+         *  is larger than the threshold In addition, full frames with a length less than the
+         *  threshold are also transmitted These bits are used only when Bit 21 _TSF_ is reset
+         *  000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16
+         */
+        uint32_t ch2_ttc:3;
+        uint32_t reserved_17:3;
+        /** ch2_ftf : R/W; bitpos: [20]; default: 0;
+         *  Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is
+         *  reset to its default values and thus all data in the Tx FIFO is lost or flushed
+         *  This bit is cleared internally when the flushing operation is complete The
+         *  Operation Mode register should not be written to until this bit is cleared The data
+         *  which is already accepted by the MAC transmitter is not flushed It is scheduled for
+         *  transmission and results in underflow and runt frame transmission Note: The flush
+         *  operation is complete only when the Tx FIFO is emptied of its contents and all the
+         *  pending Transmit Status of the transmitted frames are accepted by the host In order
+         *  to complete this flush operation, the PHY transmit clock _clk_tx_i_ is required to
+         *  be active 19:17		Reserved 	000	RO
+         */
+        uint32_t ch2_ftf:1;
+        /** ch2_tsf : R/W; bitpos: [21]; default: 0;
+         *  Transmit Store and Forward When this bit is set, transmission starts when a full
+         *  frame resides in the MTL Transmit FIFO When this bit is set, the TTC values
+         *  specified in Bits [16:14] are ignored This bit should be changed only when the
+         *  transmission is stopped
+         */
+        uint32_t ch2_tsf:1;
+        /** ch2_rfd_2 : R/W; bitpos: [22]; default: 0;
+         *  MSB of Threshold for Deactivating Flow Control If the DWC_gmac is configured for Rx
+         *  FIFO size of 8 KB or more, this bit _when set_ provides additional threshold levels
+         *  for deactivating the flow control in both halfduplex and fullduplex modes This bit
+         *  _as Most Significant Bit_ along with the RFD _Bits [12:11]_ gives the following
+         *  thresholds for deactivating flow control: 100: Full minus 5 KB, that is, FULL — 5
+         *  KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that is, FULL —
+         *  7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB or less deep
+         */
+        uint32_t ch2_rfd_2:1;
+        /** ch2_rfa_2 : R/W; bitpos: [23]; default: 0;
+         *  MSB of Threshold for Activating Flow Control If the DWC_gmac is configured for an
+         *  Rx FIFO size of 8 KB or more, this bit _when set_ provides additional threshold
+         *  levels for activating the flow control in both half duplex and fullduplex modes
+         *  This bit _as Most Significant Bit_, along with the RFA _Bits [10:9]_, gives the
+         *  following thresholds for activating flow control: 100: Full minus 5 KB, that is,
+         *  FULL — 5 KB 101: Full minus 6 KB, that is, FULL — 6 KB 110: Full minus 7 KB, that
+         *  is, FULL — 7 KB 111: Reserved This bit is reserved _and RO_ if the Rx FIFO is 4 KB
+         *  or less deep
+         */
+        uint32_t ch2_rfa_2:1;
+        /** ch2_dff : R/W; bitpos: [24]; default: 0;
+         *  Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush
+         *  any frames because of the unavailability of receive descriptors or buffers as it
+         *  does normally when this bit is reset _See “Receive Process Suspended” on page 83_
+         *  This bit is reserved _and RO_ in the GMACMTL configuration
+         */
+        uint32_t ch2_dff:1;
+        /** ch2_rsf : R/W; bitpos: [25]; default: 0;
+         *  Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx
+         *  FIFO only after the complete frame has been written to it, ignoring the RTC bits
+         *  When this bit is reset, the Rx FIFO operates in the cutthrough mode, subject to the
+         *  threshold specified by the RTC bits
+         */
+        uint32_t ch2_rsf:1;
+        /** ch2_dt : R/W; bitpos: [26]; default: 0;
+         *  Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does
+         *  not drop the frames which only have errors detected by the Receive Checksum Offload
+         *  engine Such frames do not have any errors _including FCS error_ in the Ethernet
+         *  frame received by the MAC but have errors only in the encapsulated payload When
+         *  this bit is reset, all error frames are dropped if the FEF bit is reset If the IPC
+         *  Full Checksum Offload Engine _Type 2_ is disabled, this bit is reserved _RO with
+         *  value 1'b0_
+         */
+        uint32_t ch2_dt:1;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} gmac_register134_channel2operationmoderegister_reg_t;
+
+/** Type of register135_channel2interruptenableregister register
+ *  Enables the interrupts reported by the Status Register
+ */
+typedef union {
+    struct {
+        /** ch2_tie : R/W; bitpos: [0]; default: 0;
+         *  Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Transmit Interrupt is enabled When this bit is reset, the Transmit
+         *  Interrupt is disabled The sbd_intr_o interrupt is generated as shown in Figure 61
+         *  It is asserted only when the TTI, GPI, GMI, GLI, or GLPII bit of the DMA Status
+         *  register is asserted, or when the NIS or AIS Status bit is asserted and the
+         *  corresponding Interrupt Enable bits _NIE or AIE_ are enabled
+         */
+        uint32_t ch2_tie:1;
+        /** ch2_tse : R/W; bitpos: [1]; default: 0;
+         *  Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Transmission Stopped Interrupt is enabled When this bit is reset, the
+         *  Transmission Stopped Interrupt is disabled
+         */
+        uint32_t ch2_tse:1;
+        /** ch2_tue : R/W; bitpos: [2]; default: 0;
+         *  Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt
+         *  Summary Enable _Bit 16_, the Transmit Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t ch2_tue:1;
+        /** ch2_tje : R/W; bitpos: [3]; default: 0;
+         *  Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Jabber Timeout Interrupt is enabled When this bit is
+         *  reset, the Transmit Jabber Timeout Interrupt is disabled
+         */
+        uint32_t ch2_tje:1;
+        /** ch2_ove : R/W; bitpos: [4]; default: 0;
+         *  Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Receive Overflow Interrupt is enabled When this bit is reset,
+         *  the Overflow Interrupt is disabled
+         */
+        uint32_t ch2_ove:1;
+        /** ch2_une : R/W; bitpos: [5]; default: 0;
+         *  Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary
+         *  Enable _Bit 15_, the Transmit Underflow Interrupt is enabled When this bit is
+         *  reset, the Underflow Interrupt is disabled
+         */
+        uint32_t ch2_une:1;
+        /** ch2_rie : R/W; bitpos: [6]; default: 0;
+         *  Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable
+         *  _Bit 16_, the Receive Interrupt is enabled When this bit is reset, the Receive
+         *  Interrupt is disabled
+         */
+        uint32_t ch2_rie:1;
+        /** ch2_rue : R/W; bitpos: [7]; default: 0;
+         *  Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Buffer Unavailable Interrupt is enabled When
+         *  this bit is reset, the Receive Buffer Unavailable Interrupt is disabled
+         */
+        uint32_t ch2_rue:1;
+        /** ch2_rse : R/W; bitpos: [8]; default: 0;
+         *  Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Receive Stopped Interrupt is enabled When this bit is reset, the
+         *  Receive Stopped Interrupt is disabled
+         */
+        uint32_t ch2_rse:1;
+        /** ch2_rwe : R/W; bitpos: [9]; default: 0;
+         *  Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Receive Watchdog Timeout Interrupt is enabled When
+         *  this bit is reset, the Receive Watchdog Timeout Interrupt is disabled
+         */
+        uint32_t ch2_rwe:1;
+        /** ch2_ete : R/W; bitpos: [10]; default: 0;
+         *  Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt
+         *  Summary Enable _Bit 15_, the Early Transmit Interrupt is enabled When this bit is
+         *  reset, the Early Transmit Interrupt is disabled
+         */
+        uint32_t ch2_ete:1;
+        uint32_t reserved_11:2;
+        /** ch2_fbe : R/W; bitpos: [13]; default: 0;
+         *  Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable
+         *  _Bit 15_, the Fatal Bus Error Interrupt is enabled When this bit is reset, the
+         *  Fatal Bus Error Enable Interrupt is disabled 12:11		Reserved	00	RO
+         */
+        uint32_t ch2_fbe:1;
+        /** ch2_ere : R/W; bitpos: [14]; default: 0;
+         *  Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary
+         *  Enable _Bit 16_, the Early Receive Interrupt is enabled When this bit is reset, the
+         *  Early Receive Interrupt is disabled
+         */
+        uint32_t ch2_ere:1;
+        /** ch2_aie : R/W; bitpos: [15]; default: 0;
+         *  Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary
+         *  is enabled When this bit is reset, the abnormal interrupt summary is disabled This
+         *  bit enables the following interrupts in Register 5 _Status Register_: Register
+         *  5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register
+         *  5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive
+         *  Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive
+         *  Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus
+         *  Error
+         */
+        uint32_t ch2_aie:1;
+        /** ch2_nie : R/W; bitpos: [16]; default: 0;
+         *  Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is
+         *  enabled When this bit is reset, normal interrupt summary is disabled This bit
+         *  enables the following interrupts in Register 5 _Status Register_: Register 5[0]:
+         *  Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]:
+         *  Receive Interrupt Register 5[14]: Early Receive Interrupt
+         */
+        uint32_t ch2_nie:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} gmac_register135_channel2interruptenableregister_reg_t;
+
+/** Type of register136_channel2missedframeandbufferoverflowcounterregister register
+ *  Contains the counters for discarded frames because no host Receive Descriptor was
+ *  available or because of Receive FIFO Overflow
+ */
+typedef union {
+    struct {
+        /** ch2_misfrmcnt : R/W; bitpos: [15:0]; default: 0;
+         *  Missed Frame Counter This field indicates the number of frames missed by the
+         *  controller because of the Host Receive Buffer being unavailable This counter is
+         *  incremented each time the DMA discards an incoming frame The counter is cleared
+         *  when this register is read with mci_be_i[0] at 1’b1
+         */
+        uint32_t ch2_misfrmcnt:16;
+        /** ch2_miscntovf : R/W; bitpos: [16]; default: 0;
+         *  Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame
+         *  Counter _Bits[15:0]_ overflows, that is, the DMA discards an incoming frame because
+         *  of the Host Receive Buffer being unavailable with the missed frame counter at
+         *  maximum value In such a scenario, the Missed frame counter is reset to allzeros and
+         *  this bit indicates that the rollover happened
+         */
+        uint32_t ch2_miscntovf:1;
+        /** ch2_ovffrmcnt : R/W; bitpos: [27:17]; default: 0;
+         *  Overflow Frame Counter This field indicates the number of frames missed by the
+         *  application This counter is incremented each time the MTL FIFO overflows The
+         *  counter is cleared when this register is read with mci_be_i[2] at 1’b1
+         */
+        uint32_t ch2_ovffrmcnt:11;
+        /** ch2_ovfcntovf : R/W; bitpos: [28]; default: 0;
+         *  Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow
+         *  Frame Counter _Bits[27:17]_ overflows, that is, the Rx FIFO overflows with the
+         *  overflow frame counter at maximum value In such a scenario, the overflow frame
+         *  counter is reset to allzeros and this bit indicates that the rollover happened
+         */
+        uint32_t ch2_ovfcntovf:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register136_channel2missedframeandbufferoverflowcounterregister_reg_t;
+
+/** Type of register137_channel2receiveinterruptwatchdogtimerregister register
+ *  Watchdog timeout for Receive Interrupt _RI_ from DMA
+ */
+typedef union {
+    struct {
+        /** ch2_riwt : R/W; bitpos: [7:0]; default: 0;
+         *  RI Watchdog Timer Count This bit indicates the number of system clock cycles
+         *  multiplied by 256 for which the watchdog timer is set The watchdog timer gets
+         *  triggered with the programmed value after the Rx DMA completes the transfer of a
+         *  frame for which the RI status bit is not set because of the setting in the
+         *  corresponding descriptor RDES1[31] When the watchdog timer runs out, the RI bit is
+         *  set and the timer is stopped The watchdog timer is reset when the RI bit is set
+         *  high because of automatic setting of RI as per RDES1[31] of any received frame
+         */
+        uint32_t ch2_riwt:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gmac_register137_channel2receiveinterruptwatchdogtimerregister_reg_t;
+
+/** Type of register146_channel2currenthosttransmitdescriptorregister register
+ *  Points to the start of current Transmit Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch2_curtdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Descriptor Address Pointer
+         */
+        uint32_t ch2_curtdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register146_channel2currenthosttransmitdescriptorregister_reg_t;
+
+/** Type of register147_channel2currenthostreceivedescriptorregister register
+ *  Points to the start of current Receive Descriptor read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch2_currdesaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Descriptor Address Pointer
+         */
+        uint32_t ch2_currdesaptr:32;
+    };
+    uint32_t val;
+} gmac_register147_channel2currenthostreceivedescriptorregister_reg_t;
+
+/** Type of register148_channel2currenthosttransmitbufferaddressregister register
+ *  Points to the current Transmit Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch2_curtbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Transmit Buffer Address Pointer
+         */
+        uint32_t ch2_curtbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register148_channel2currenthosttransmitbufferaddressregister_reg_t;
+
+/** Type of register149_channel2currenthostreceivebufferaddressregister register
+ *  Points to the current Receive Buffer address read by the DMA
+ */
+typedef union {
+    struct {
+        /** ch2_currbufaptr : RO; bitpos: [31:0]; default: 0;
+         *  Host Receive Buffer Address Pointer
+         */
+        uint32_t ch2_currbufaptr:32;
+    };
+    uint32_t val;
+} gmac_register149_channel2currenthostreceivebufferaddressregister_reg_t;
+
+/** Type of register152_channel2cbscontrolregister register
+ *  Controls the Channel 2 credit shaping operation on the transmit path
+ */
+typedef union {
+    struct {
+        /** ch2_cbsd : R/W; bitpos: [0]; default: 0;
+         *  CreditBased Shaper Disable When set, the MAC disables the creditbased shaper
+         *  algorithm for Channel 2 traffic and makes the traffic management algorithm to
+         *  strict priority for Channel 2 over Channel 0 When reset, the creditbased shaper
+         *  algorithm schedules the traffic in Channel 2 for transmission
+         */
+        uint32_t ch2_cbsd:1;
+        /** ch2_cc : R/W; bitpos: [1]; default: 0;
+         *  Credit Control When reset, the accumulated credit parameter in the creditbased
+         *  shaper algorithm logic is set to zero when there is positive credit and no frame to
+         *  transmit in Channel 2 When there is no frame waiting in Channel 2 and other channel
+         *  is transmitting, no credit is accumulated When set, the accumulated credit
+         *  parameter in the creditbased shaper algorithm logic is not reset to zero when there
+         *  is positive credit and no frame to transmit in Channel 2 The credit accumulates
+         *  even when there is no frame waiting in Channel 2 and another channel is transmitting
+         */
+        uint32_t ch2_cc:1;
+        uint32_t reserved_2:2;
+        /** ch2_slc : R/W; bitpos: [6:4]; default: 0;
+         *  Slot Count The software can program the number of slots _of duration 125 microsec_
+         *  over which the average transmitted bits per slot _provided in the CBS Status
+         *  register_ need to be computed for Channel 2 when the creditbased shaper algorithm
+         *  is enabled The encoding is as follows: 3'b000: 1 Slot 3'b001: 2 Slots 3'b010: 4
+         *  Slots 3'b011: 8 Slots 3'b100: 16 Slots 3'b1013'b111: Reserved
+         */
+        uint32_t ch2_slc:3;
+        uint32_t reserved_7:10;
+        /** ch2_abpssie : R/W; bitpos: [17]; default: 0;
+         *  Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts an
+         *  interrupt _sbd_intr_o or mci_intr_o_ when the average bits per slot status is
+         *  updated _Bit 17 _ABSU_ in Register 153_ for Channel 2 When this bit is cleared,
+         *  interrupt is not asserted for such an event
+         */
+        uint32_t ch2_abpssie:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gmac_register152_channel2cbscontrolregister_reg_t;
+
+/** Type of register153_channel2cbsstatusregister register
+ *  Provides the average traffic transmitted in Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_abs : RO; bitpos: [16:0]; default: 0;
+         *  Average Bits per Slot This field contains the average transmitted bits per slot
+         *  This field is computed over programmed number of slots _SLC bits in the CBS Control
+         *  Register_ for Channel 2 traffic The maximum value is 0x30D4 for 100 Mbps and
+         *  0x1E848 for 1000 Mbps
+         */
+        uint32_t ch2_abs:17;
+        /** ch2_absu : RO; bitpos: [17]; default: 0;
+         *  ABS Updated When set, this bit indicates that the MAC has updated the ABS value
+         *  This bit is cleared when the application reads the ABS value
+         */
+        uint32_t ch2_absu:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gmac_register153_channel2cbsstatusregister_reg_t;
+
+/** Type of register154_channel2idleslopecreditregister register
+ *  Contains the idleSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_isc : R/W; bitpos: [13:0]; default: 0;
+         *  idleSlopeCredit This field contains the idleSlopeCredit value required for the
+         *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+         *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+         *  credit is increasing The software should program this field with computed credit in
+         *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+         *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode
+         */
+        uint32_t ch2_isc:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} gmac_register154_channel2idleslopecreditregister_reg_t;
+
+/** Type of register155_channel2sendslopecreditregister register
+ *  Contains the sendSlope credit value required for the creditbased shaper algorithm
+ *  for Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_ssc : R/W; bitpos: [13:0]; default: 0;
+         *  sendSlopeCredit This field contains the sendSlopeCredit value required for
+         *  creditbased shaper algorithm for Channel 2 This is the rate of change of credit in
+         *  bits per cycle _40ns and 8ns for 100 Mbps and 1000 Mbps respectively_ when the
+         *  credit is decreasing The software should program this field with computed credit in
+         *  bits per cycle scaled by 1024 The maximum value is portTransmitRate, that is,
+         *  0x2000 in 1000 Mbps mode and 0x1000 in 100 Mbps mode This field should be
+         *  programmed with absolute sendSlopeCredit value The creditbased shaper logic
+         *  subtracts it from the accumulated credit when Channel 2 is selected for transmission
+         */
+        uint32_t ch2_ssc:14;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} gmac_register155_channel2sendslopecreditregister_reg_t;
+
+/** Type of register156_channel2hicreditregister register
+ *  Contains the hiCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_hc : R/W; bitpos: [28:0]; default: 0;
+         *  hiCredit This field contains the hiCredit value required for the creditbased shaper
+         *  algorithm for Channel 2 This is the maximum value that can be accumulated in the
+         *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+         *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+         *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+         *  0x0800_0000
+         */
+        uint32_t ch2_hc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register156_channel2hicreditregister_reg_t;
+
+/** Type of register157_channel2locreditregister register
+ *  Contains the loCredit value required for the creditbased shaper algorithm for
+ *  Channel 2
+ */
+typedef union {
+    struct {
+        /** ch2_lc : R/W; bitpos: [28:0]; default: 536870911;
+         *  loCredit This field contains the loCredit value required for the creditbased shaper
+         *  algorithm for Channel 2 This is the minimum value that can be accumulated in the
+         *  credit parameter This is specified in bits scaled by 1,024 The maximum value is
+         *  maxInterferenceSize, that is, besteffort maximum frame size which is 16,384 bytes
+         *  or 131,072 bits The value to be specified is 131,072 * 1,024 = 134,217,728 or
+         *  0x0800_0000 The programmed value is 2's complement _negative number_, that is,
+         *  0xF800_0000
+         */
+        uint32_t ch2_lc:29;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} gmac_register157_channel2locreditregister_reg_t;
+
+
+typedef struct {
+    volatile gmac_register0_macconfigurationregister_reg_t register0_macconfigurationregister;
+    volatile gmac_register1_macframefilter_reg_t register1_macframefilter;
+    volatile gmac_register2_hashtablehighregister_reg_t register2_hashtablehighregister;
+    volatile gmac_register3_hashtablelowregister_reg_t register3_hashtablelowregister;
+    volatile gmac_register4_gmiiaddressregister_reg_t register4_gmiiaddressregister;
+    volatile gmac_register5_gmiidataregister_reg_t register5_gmiidataregister;
+    volatile gmac_register6_flowcontrolregister_reg_t register6_flowcontrolregister;
+    volatile gmac_register7_vlantagregister_reg_t register7_vlantagregister;
+    volatile gmac_register8_versionregister_reg_t register8_versionregister;
+    volatile gmac_register9_debugregister_reg_t register9_debugregister;
+    volatile gmac_register10_remotewakeupframefilterregister_reg_t register10_remotewakeupframefilterregister;
+    volatile gmac_register11_pmtcontrolandstatusregister_reg_t register11_pmtcontrolandstatusregister;
+    volatile gmac_register12_lpicontrolandstatusregister_reg_t register12_lpicontrolandstatusregister;
+    volatile gmac_register13_lpitimerscontrolregister_reg_t register13_lpitimerscontrolregister;
+    volatile gmac_register14_interruptstatusregister_reg_t register14_interruptstatusregister;
+    volatile gmac_register15_interruptmaskregister_reg_t register15_interruptmaskregister;
+    volatile gmac_register16_macaddress0highregister_reg_t register16_macaddress0highregister;
+    volatile gmac_register17_macaddress0lowregister_reg_t register17_macaddress0lowregister;
+    volatile gmac_register18_macaddress1highregister_reg_t register18_macaddress1highregister;
+    volatile gmac_register19_macaddress1lowregister_reg_t register19_macaddress1lowregister;
+    volatile gmac_macaddress2highregistercontainsthehigher16bitsofthethirdmacaddress_reg_t macaddress2highregistercontainsthehigher16bitsofthethirdmacaddress;
+    volatile gmac_macaddress2lowregistercontainsthelower32bitsofthethirdmacaddress_reg_t macaddress2lowregistercontainsthelower32bitsofthethirdmacaddress;
+    volatile gmac_macaddress3highregistercontainsthehigher16bitsofthefourthmacaddress_reg_t macaddress3highregistercontainsthehigher16bitsofthefourthmacaddress;
+    volatile gmac_macaddress3lowregistercontainsthelower32bitsofthefourthmacaddress_reg_t macaddress3lowregistercontainsthelower32bitsofthefourthmacaddress;
+    volatile gmac_macaddress4highregistercontainsthehigher16bitsofthefifthmacaddress_reg_t macaddress4highregistercontainsthehigher16bitsofthefifthmacaddress;
+    volatile gmac_macaddress4lowregistercontainsthelower32bitsofthefifthmacaddress_reg_t macaddress4lowregistercontainsthelower32bitsofthefifthmacaddress;
+    volatile gmac_macaddress5highregistercontainsthehigher16bitsofthesixthmacaddress_reg_t macaddress5highregistercontainsthehigher16bitsofthesixthmacaddress;
+    volatile gmac_macaddress5lowregistercontainsthelower32bitsofthesixthmacaddress_reg_t macaddress5lowregistercontainsthelower32bitsofthesixthmacaddress;
+    volatile gmac_macaddress6highregistercontainsthehigher16bitsoftheseventhmacaddress_reg_t macaddress6highregistercontainsthehigher16bitsoftheseventhmacaddress;
+    volatile gmac_macaddress6lowregistercontainsthelower32bitsoftheseventhmacaddress_reg_t macaddress6lowregistercontainsthelower32bitsoftheseventhmacaddress;
+    volatile gmac_macaddress7highregistercontainsthehigher16bitsoftheeighthmacaddress_reg_t macaddress7highregistercontainsthehigher16bitsoftheeighthmacaddress;
+    volatile gmac_macaddress7lowregistercontainsthelower32bitsoftheeighthmacaddress_reg_t macaddress7lowregistercontainsthelower32bitsoftheeighthmacaddress;
+    uint32_t reserved_080[16];
+    volatile gmac_register48_ancontrolregister_reg_t register48_ancontrolregister;
+    volatile gmac_register49_anstatusregister_reg_t register49_anstatusregister;
+    volatile gmac_register50_autonegotiationadvertisementregister_reg_t register50_autonegotiationadvertisementregister;
+    volatile gmac_register51_autonegotiationlinkpartnerabilityregister_reg_t register51_autonegotiationlinkpartnerabilityregister;
+    volatile gmac_register52_autonegotiationexpansionregister_reg_t register52_autonegotiationexpansionregister;
+    volatile gmac_register53_tbiextendedstatusregister_reg_t register53_tbiextendedstatusregister;
+    volatile gmac_register54_sgmii_rgmii_smiicontrolandstatusregister_reg_t register54_sgmii_rgmii_smiicontrolandstatusregister;
+    volatile gmac_register55_watchdogtimeoutregister_reg_t register55_watchdogtimeoutregister;
+    volatile gmac_register56_generalpurposeioregister_reg_t register56_generalpurposeioregister;
+    uint32_t reserved_0e4[199];
+    volatile gmac_register256_layer3andlayer4controlregister0_reg_t register256_layer3andlayer4controlregister0;
+    volatile gmac_register257_layer4addressregister0_reg_t register257_layer4addressregister0;
+    uint32_t reserved_408[2];
+    volatile gmac_register260_layer3address0register0_reg_t register260_layer3address0register0;
+    volatile gmac_register261_layer3address1register0_reg_t register261_layer3address1register0;
+    volatile gmac_register262_layer3address2register0_reg_t register262_layer3address2register0;
+    volatile gmac_register263_layer3address3register0_reg_t register263_layer3address3register0;
+    uint32_t reserved_420[56];
+    volatile gmac_register320_hashtableregister0_reg_t register320_hashtableregister0;
+    uint32_t reserved_504[32];
+    volatile gmac_register353_vlantaginclusionorreplacementregister_reg_t register353_vlantaginclusionorreplacementregister;
+    volatile gmac_register354_vlanhashtableregister_reg_t register354_vlanhashtableregister;
+    uint32_t reserved_58c[93];
+    volatile gmac_register448_timestampcontrolregister_reg_t register448_timestampcontrolregister;
+    volatile gmac_register449_subsecondincrementregister_reg_t register449_subsecondincrementregister;
+    volatile gmac_register450_systemtimesecondsregister_reg_t register450_systemtimesecondsregister;
+    volatile gmac_register451_systemtimenanosecondsregister_reg_t register451_systemtimenanosecondsregister;
+    volatile gmac_register452_systemtimesecondsupdateregister_reg_t register452_systemtimesecondsupdateregister;
+    volatile gmac_register453_systemtimenanosecondsupdateregister_reg_t register453_systemtimenanosecondsupdateregister;
+    volatile gmac_register454_timestampaddendregister_reg_t register454_timestampaddendregister;
+    volatile gmac_register455_targettimesecondsregister_reg_t register455_targettimesecondsregister;
+    volatile gmac_register456_targettimenanosecondsregister_reg_t register456_targettimenanosecondsregister;
+    volatile gmac_register457_systemtimehigherwordsecondsregister_reg_t register457_systemtimehigherwordsecondsregister;
+    volatile gmac_register458_timestampstatusregister_reg_t register458_timestampstatusregister;
+    volatile gmac_register459_ppscontrolregister_reg_t register459_ppscontrolregister;
+    volatile gmac_register460_auxiliarytimestampnanosecondsregister_reg_t register460_auxiliarytimestampnanosecondsregister;
+    volatile gmac_register461_auxiliarytimestampsecondsregister_reg_t register461_auxiliarytimestampsecondsregister;
+    volatile gmac_register462_avmaccontrolregister_reg_t register462_avmaccontrolregister;
+    uint32_t reserved_73c[9];
+    volatile gmac_register472_pps0intervalregister_reg_t register472_pps0intervalregister;
+    volatile gmac_register473_pps0widthregister_reg_t register473_pps0widthregister;
+    uint32_t reserved_768[6];
+    volatile gmac_register480_pps1targettimesecondsregister_reg_t register480_pps1targettimesecondsregister;
+    volatile gmac_register481_pps1targettimenanosecondsregister_reg_t register481_pps1targettimenanosecondsregister;
+    uint32_t reserved_788[62];
+    volatile gmac_register544_macaddress32highregister_reg_t register544_macaddress32highregister;
+    uint32_t reserved_884[479];
+    volatile gmac_register0_busmoderegister_reg_t register0_busmoderegister;
+    volatile gmac_register1_transmitpolldemandregister_reg_t register1_transmitpolldemandregister;
+    volatile gmac_register2_receivepolldemandregister_reg_t register2_receivepolldemandregister;
+    volatile gmac_register3_receivedescriptorlistaddressregister_reg_t register3_receivedescriptorlistaddressregister;
+    volatile gmac_register4_transmitdescriptorlistaddressregister_reg_t register4_transmitdescriptorlistaddressregister;
+    volatile gmac_register5_statusregister_reg_t register5_statusregister;
+    volatile gmac_register6_operationmoderegister_reg_t register6_operationmoderegister;
+    volatile gmac_register7_interruptenableregister_reg_t register7_interruptenableregister;
+    volatile gmac_register8_missedframeandbufferoverflowcounterregister_reg_t register8_missedframeandbufferoverflowcounterregister;
+    volatile gmac_register9_receiveinterruptwatchdogtimerregister_reg_t register9_receiveinterruptwatchdogtimerregister;
+    volatile gmac_register10_axibusmoderegister_reg_t register10_axibusmoderegister;
+    volatile gmac_register11_ahboraxistatusregister_reg_t register11_ahboraxistatusregister;
+    uint32_t reserved_1030[6];
+    volatile gmac_register18_currenthosttransmitdescriptorregister_reg_t register18_currenthosttransmitdescriptorregister;
+    volatile gmac_register19_currenthostreceivedescriptorregister_reg_t register19_currenthostreceivedescriptorregister;
+    volatile gmac_register20_currenthosttransmitbufferaddressregister_reg_t register20_currenthosttransmitbufferaddressregister;
+    volatile gmac_register21_currenthostreceivebufferaddressregister_reg_t register21_currenthostreceivebufferaddressregister;
+    volatile gmac_register22_hwfeatureregister_reg_t register22_hwfeatureregister;
+    uint32_t reserved_105c[41];
+    volatile gmac_register64_channel1busmoderegister_reg_t register64_channel1busmoderegister;
+    volatile gmac_register65_channel1transmitpolldemandregister_reg_t register65_channel1transmitpolldemandregister;
+    volatile gmac_register66_channel1receivepolldemandregister_reg_t register66_channel1receivepolldemandregister;
+    volatile gmac_register67_channel1receivedescriptorlistaddressregister_reg_t register67_channel1receivedescriptorlistaddressregister;
+    volatile gmac_register68_channel1transmitdescriptorlistaddressregister_reg_t register68_channel1transmitdescriptorlistaddressregister;
+    volatile gmac_register69_channel1statusregister_reg_t register69_channel1statusregister;
+    volatile gmac_register70_channel1operationmoderegister_reg_t register70_channel1operationmoderegister;
+    volatile gmac_register71_channel1interruptenableregister_reg_t register71_channel1interruptenableregister;
+    volatile gmac_register72_channel1missedframeandbufferoverflowcounterregister_reg_t register72_channel1missedframeandbufferoverflowcounterregister;
+    volatile gmac_register73_channel1receiveinterruptwatchdogtimerregister_reg_t register73_channel1receiveinterruptwatchdogtimerregister;
+    uint32_t reserved_1128[2];
+    volatile gmac_register76_channel1slotfunctioncontrolandstatusregister_reg_t register76_channel1slotfunctioncontrolandstatusregister;
+    uint32_t reserved_1134[5];
+    volatile gmac_register82_channel1currenthosttransmitdescriptorregister_reg_t register82_channel1currenthosttransmitdescriptorregister;
+    volatile gmac_register83_channel1currenthostreceivedescriptorregister_reg_t register83_channel1currenthostreceivedescriptorregister;
+    volatile gmac_register84_channel1currenthosttransmitbufferaddressregister_reg_t register84_channel1currenthosttransmitbufferaddressregister;
+    volatile gmac_register85_channel1currenthostreceivebufferaddressregister_reg_t register85_channel1currenthostreceivebufferaddressregister;
+    uint32_t reserved_1158[2];
+    volatile gmac_register88_channel1cbscontrolregister_reg_t register88_channel1cbscontrolregister;
+    volatile gmac_register89_channel1cbsstatusregister_reg_t register89_channel1cbsstatusregister;
+    volatile gmac_register90_channel1idleslopecreditregister_reg_t register90_channel1idleslopecreditregister;
+    volatile gmac_register91_channel1sendslopecreditregister_reg_t register91_channel1sendslopecreditregister;
+    volatile gmac_register92_channel1hicreditregister_reg_t register92_channel1hicreditregister;
+    volatile gmac_register93_channel1locreditregister_reg_t register93_channel1locreditregister;
+    uint32_t reserved_1178[34];
+    volatile gmac_register128_channel2busmoderegister_reg_t register128_channel2busmoderegister;
+    volatile gmac_register129_channel2transmitpolldemandregister_reg_t register129_channel2transmitpolldemandregister;
+    volatile gmac_register130_channel2receivepolldemandregister_reg_t register130_channel2receivepolldemandregister;
+    volatile gmac_register131_channel2receivedescriptorlistaddressregister_reg_t register131_channel2receivedescriptorlistaddressregister;
+    volatile gmac_register132_channel2transmitdescriptorlistaddressregister_reg_t register132_channel2transmitdescriptorlistaddressregister;
+    volatile gmac_register133_channel2statusregister_reg_t register133_channel2statusregister;
+    volatile gmac_register134_channel2operationmoderegister_reg_t register134_channel2operationmoderegister;
+    volatile gmac_register135_channel2interruptenableregister_reg_t register135_channel2interruptenableregister;
+    volatile gmac_register136_channel2missedframeandbufferoverflowcounterregister_reg_t register136_channel2missedframeandbufferoverflowcounterregister;
+    volatile gmac_register137_channel2receiveinterruptwatchdogtimerregister_reg_t register137_channel2receiveinterruptwatchdogtimerregister;
+    uint32_t reserved_1228[8];
+    volatile gmac_register146_channel2currenthosttransmitdescriptorregister_reg_t register146_channel2currenthosttransmitdescriptorregister;
+    volatile gmac_register147_channel2currenthostreceivedescriptorregister_reg_t register147_channel2currenthostreceivedescriptorregister;
+    volatile gmac_register148_channel2currenthosttransmitbufferaddressregister_reg_t register148_channel2currenthosttransmitbufferaddressregister;
+    volatile gmac_register149_channel2currenthostreceivebufferaddressregister_reg_t register149_channel2currenthostreceivebufferaddressregister;
+    uint32_t reserved_1258[2];
+    volatile gmac_register152_channel2cbscontrolregister_reg_t register152_channel2cbscontrolregister;
+    volatile gmac_register153_channel2cbsstatusregister_reg_t register153_channel2cbsstatusregister;
+    volatile gmac_register154_channel2idleslopecreditregister_reg_t register154_channel2idleslopecreditregister;
+    volatile gmac_register155_channel2sendslopecreditregister_reg_t register155_channel2sendslopecreditregister;
+    volatile gmac_register156_channel2hicreditregister_reg_t register156_channel2hicreditregister;
+    volatile gmac_register157_channel2locreditregister_reg_t register157_channel2locreditregister;
+} gmac_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gmac_dev_t) == 0x1278, "Invalid size of gmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gpio_ext_reg.h b/components/soc/esp32s31/register/soc/gpio_ext_reg.h
new file mode 100644
index 00000000000..3d9a658a2ec
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gpio_ext_reg.h
@@ -0,0 +1,2104 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_EXT_SIGMADELTA_MISC_REG register
+ *  MISC Register
+ */
+#define GPIO_EXT_SIGMADELTA_MISC_REG (DR_REG_GPIO_EXT_BASE + 0x4)
+/** GPIO_EXT_SIGMADELTA_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable the clock for sigma delta modulation.
+ *  0: Not enable
+ *  1: Enable
+ *  %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
+ */
+#define GPIO_EXT_SIGMADELTA_CLK_EN    (BIT(0))
+#define GPIO_EXT_SIGMADELTA_CLK_EN_M  (GPIO_EXT_SIGMADELTA_CLK_EN_V << GPIO_EXT_SIGMADELTA_CLK_EN_S)
+#define GPIO_EXT_SIGMADELTA_CLK_EN_V  0x00000001U
+#define GPIO_EXT_SIGMADELTA_CLK_EN_S  0
+
+/** GPIO_EXT_SIGMADELTA0_REG register
+ *  Duty cycle configuration register for SDM channel 0
+ */
+#define GPIO_EXT_SIGMADELTA0_REG (DR_REG_GPIO_EXT_BASE + 0x8)
+/** GPIO_EXT_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD0_IN    0x000000FFU
+#define GPIO_EXT_SD0_IN_M  (GPIO_EXT_SD0_IN_V << GPIO_EXT_SD0_IN_S)
+#define GPIO_EXT_SD0_IN_V  0x000000FFU
+#define GPIO_EXT_SD0_IN_S  0
+/** GPIO_EXT_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD0_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_M  (GPIO_EXT_SD0_PRESCALE_V << GPIO_EXT_SD0_PRESCALE_S)
+#define GPIO_EXT_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD0_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA1_REG register
+ *  Duty cycle configuration register for SDM channel 1
+ */
+#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0xc)
+/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD1_IN    0x000000FFU
+#define GPIO_EXT_SD1_IN_M  (GPIO_EXT_SD1_IN_V << GPIO_EXT_SD1_IN_S)
+#define GPIO_EXT_SD1_IN_V  0x000000FFU
+#define GPIO_EXT_SD1_IN_S  0
+/** GPIO_EXT_SD1_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD1_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_M  (GPIO_EXT_SD1_PRESCALE_V << GPIO_EXT_SD1_PRESCALE_S)
+#define GPIO_EXT_SD1_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD1_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA2_REG register
+ *  Duty cycle configuration register for SDM channel 2
+ */
+#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x10)
+/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD2_IN    0x000000FFU
+#define GPIO_EXT_SD2_IN_M  (GPIO_EXT_SD2_IN_V << GPIO_EXT_SD2_IN_S)
+#define GPIO_EXT_SD2_IN_V  0x000000FFU
+#define GPIO_EXT_SD2_IN_S  0
+/** GPIO_EXT_SD2_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD2_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_M  (GPIO_EXT_SD2_PRESCALE_V << GPIO_EXT_SD2_PRESCALE_S)
+#define GPIO_EXT_SD2_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD2_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA3_REG register
+ *  Duty cycle configuration register for SDM channel 3
+ */
+#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0x14)
+/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD3_IN    0x000000FFU
+#define GPIO_EXT_SD3_IN_M  (GPIO_EXT_SD3_IN_V << GPIO_EXT_SD3_IN_S)
+#define GPIO_EXT_SD3_IN_V  0x000000FFU
+#define GPIO_EXT_SD3_IN_S  0
+/** GPIO_EXT_SD3_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD3_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_M  (GPIO_EXT_SD3_PRESCALE_V << GPIO_EXT_SD3_PRESCALE_S)
+#define GPIO_EXT_SD3_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD3_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA4_REG register
+ *  Duty cycle configuration register for SDM channel 4
+ */
+#define GPIO_EXT_SIGMADELTA4_REG (DR_REG_GPIO_EXT_BASE + 0x18)
+/** GPIO_EXT_SD4_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD4_IN    0x000000FFU
+#define GPIO_EXT_SD4_IN_M  (GPIO_EXT_SD4_IN_V << GPIO_EXT_SD4_IN_S)
+#define GPIO_EXT_SD4_IN_V  0x000000FFU
+#define GPIO_EXT_SD4_IN_S  0
+/** GPIO_EXT_SD4_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD4_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_M  (GPIO_EXT_SD4_PRESCALE_V << GPIO_EXT_SD4_PRESCALE_S)
+#define GPIO_EXT_SD4_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD4_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA5_REG register
+ *  Duty cycle configuration register for SDM channel 5
+ */
+#define GPIO_EXT_SIGMADELTA5_REG (DR_REG_GPIO_EXT_BASE + 0x1c)
+/** GPIO_EXT_SD5_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD5_IN    0x000000FFU
+#define GPIO_EXT_SD5_IN_M  (GPIO_EXT_SD5_IN_V << GPIO_EXT_SD5_IN_S)
+#define GPIO_EXT_SD5_IN_V  0x000000FFU
+#define GPIO_EXT_SD5_IN_S  0
+/** GPIO_EXT_SD5_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD5_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_M  (GPIO_EXT_SD5_PRESCALE_V << GPIO_EXT_SD5_PRESCALE_S)
+#define GPIO_EXT_SD5_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD5_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA6_REG register
+ *  Duty cycle configuration register for SDM channel 6
+ */
+#define GPIO_EXT_SIGMADELTA6_REG (DR_REG_GPIO_EXT_BASE + 0x20)
+/** GPIO_EXT_SD6_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD6_IN    0x000000FFU
+#define GPIO_EXT_SD6_IN_M  (GPIO_EXT_SD6_IN_V << GPIO_EXT_SD6_IN_S)
+#define GPIO_EXT_SD6_IN_V  0x000000FFU
+#define GPIO_EXT_SD6_IN_S  0
+/** GPIO_EXT_SD6_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD6_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_M  (GPIO_EXT_SD6_PRESCALE_V << GPIO_EXT_SD6_PRESCALE_S)
+#define GPIO_EXT_SD6_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD6_PRESCALE_S  8
+
+/** GPIO_EXT_SIGMADELTA7_REG register
+ *  Duty cycle configuration register for SDM channel 7
+ */
+#define GPIO_EXT_SIGMADELTA7_REG (DR_REG_GPIO_EXT_BASE + 0x24)
+/** GPIO_EXT_SD7_IN : R/W; bitpos: [7:0]; default: 0;
+ *  Configures the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_EXT_SD7_IN    0x000000FFU
+#define GPIO_EXT_SD7_IN_M  (GPIO_EXT_SD7_IN_V << GPIO_EXT_SD7_IN_S)
+#define GPIO_EXT_SD7_IN_V  0x000000FFU
+#define GPIO_EXT_SD7_IN_S  0
+/** GPIO_EXT_SD7_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  Configures the divider value to divide IO MUX operating clock.
+ */
+#define GPIO_EXT_SD7_PRESCALE    0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_M  (GPIO_EXT_SD7_PRESCALE_V << GPIO_EXT_SD7_PRESCALE_S)
+#define GPIO_EXT_SD7_PRESCALE_V  0x000000FFU
+#define GPIO_EXT_SD7_PRESCALE_S  8
+
+/** GPIO_EXT_GLITCH_FILTER_CH0_REG register
+ *  Glitch Filter Configure Register of Channel0
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH0_REG (DR_REG_GPIO_EXT_BASE + 0xd8)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 0 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH0_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH1_REG register
+ *  Glitch Filter Configure Register of Channel1
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH1_REG (DR_REG_GPIO_EXT_BASE + 0xdc)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 1 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH1_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH2_REG register
+ *  Glitch Filter Configure Register of Channel2
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH2_REG (DR_REG_GPIO_EXT_BASE + 0xe0)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 2 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH2_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH3_REG register
+ *  Glitch Filter Configure Register of Channel3
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH3_REG (DR_REG_GPIO_EXT_BASE + 0xe4)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 3 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH3_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH4_REG register
+ *  Glitch Filter Configure Register of Channel4
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH4_REG (DR_REG_GPIO_EXT_BASE + 0xe8)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 4 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH4_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH5_REG register
+ *  Glitch Filter Configure Register of Channel5
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH5_REG (DR_REG_GPIO_EXT_BASE + 0xec)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 5 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH5_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH6_REG register
+ *  Glitch Filter Configure Register of Channel6
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH6_REG (DR_REG_GPIO_EXT_BASE + 0xf0)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 6 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH6_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_GLITCH_FILTER_CH7_REG register
+ *  Glitch Filter Configure Register of Channel7
+ */
+#define GPIO_EXT_GLITCH_FILTER_CH7_REG (DR_REG_GPIO_EXT_BASE + 0xf4)
+/** GPIO_EXT_FILTER_CH0_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable channel 7 of Glitch Filter.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_FILTER_CH0_EN    (BIT(0))
+#define GPIO_EXT_FILTER_CH0_EN_M  (GPIO_EXT_FILTER_CH0_EN_V << GPIO_EXT_FILTER_CH0_EN_S)
+#define GPIO_EXT_FILTER_CH0_EN_V  0x00000001U
+#define GPIO_EXT_FILTER_CH0_EN_S  0
+/** GPIO_EXT_FILTER_CH0_INPUT_IO_NUM : R/W; bitpos: [7:1]; default: 0;
+ *  Configures to select the input GPIO for Glitch Filter.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM    0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_M  (GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V << GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S)
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_V  0x0000007FU
+#define GPIO_EXT_FILTER_CH0_INPUT_IO_NUM_S  1
+/** GPIO_EXT_FILTER_CH0_WINDOW_THRES : R/W; bitpos: [13:8]; default: 0;
+ *  Configures the window threshold for Glitch Filter. The window threshold should be
+ *  less than or equal to GPIOSD_FILTER_CH7_WINDOW_WIDTH.
+ *  %see DOC-4768
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_M  (GPIO_EXT_FILTER_CH0_WINDOW_THRES_V << GPIO_EXT_FILTER_CH0_WINDOW_THRES_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_THRES_S  8
+/** GPIO_EXT_FILTER_CH0_WINDOW_WIDTH : R/W; bitpos: [19:14]; default: 0;
+ *  Configures the window width for Glitch Filter. The effective value of window width
+ *  is 0 ~ 63.
+ *  Measurement unit: IO MUX operating clock cycle
+ */
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH    0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_M  (GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V << GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S)
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_V  0x0000003FU
+#define GPIO_EXT_FILTER_CH0_WINDOW_WIDTH_S  14
+
+/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
+ *  ETM configuration register for channel 0
+ */
+#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118)
+/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_M  (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH0_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH0_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH0_EVENT_EN_M  (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH0_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH0_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
+ *  ETM configuration register for channel 1
+ */
+#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c)
+/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH1_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH1_EVENT_SEL_M  (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH1_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH1_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH1_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH1_EVENT_EN_M  (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH1_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH1_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
+ *  ETM configuration register for channel 2
+ */
+#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120)
+/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH2_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH2_EVENT_SEL_M  (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH2_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH2_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH2_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH2_EVENT_EN_M  (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH2_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH2_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
+ *  ETM configuration register for channel 3
+ */
+#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124)
+/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH3_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH3_EVENT_SEL_M  (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH3_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH3_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH3_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH3_EVENT_EN_M  (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH3_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH3_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
+ *  ETM configuration register for channel 4
+ */
+#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128)
+/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH4_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH4_EVENT_SEL_M  (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH4_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH4_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH4_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH4_EVENT_EN_M  (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH4_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH4_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
+ *  ETM configuration register for channel 5
+ */
+#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c)
+/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH5_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH5_EVENT_SEL_M  (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH5_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH5_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH5_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH5_EVENT_EN_M  (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH5_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH5_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
+ *  ETM configuration register for channel 6
+ */
+#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130)
+/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH6_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH6_EVENT_SEL_M  (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH6_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH6_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH6_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH6_EVENT_EN_M  (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH6_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH6_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
+ *  ETM configuration register for channel 7
+ */
+#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134)
+/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [6:0]; default: 0;
+ *  Configures to select GPIO for ETM event channel.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  63 ~ 127: Reserved
+ */
+#define GPIO_EXT_ETM_CH7_EVENT_SEL    0x0000007FU
+#define GPIO_EXT_ETM_CH7_EVENT_SEL_M  (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S)
+#define GPIO_EXT_ETM_CH7_EVENT_SEL_V  0x0000007FU
+#define GPIO_EXT_ETM_CH7_EVENT_SEL_S  0
+/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to enable ETM event send.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_CH7_EVENT_EN    (BIT(7))
+#define GPIO_EXT_ETM_CH7_EVENT_EN_M  (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S)
+#define GPIO_EXT_ETM_CH7_EVENT_EN_V  0x00000001U
+#define GPIO_EXT_ETM_CH7_EVENT_EN_S  7
+
+/** GPIO_EXT_ETM_TASK_P0_CFG_REG register
+ *  GPIO selection register 0 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158)
+/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO0.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M  (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO0 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO0_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_M  (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO0_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO1.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M  (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO1 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO1_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_M  (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO1_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO2.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M  (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO2 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO2_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_M  (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO2_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO3.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M  (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO3 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO3_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_M  (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO3_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO4.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M  (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO4 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO4_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_M  (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO4_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P1_CFG_REG register
+ *  GPIO selection register 1 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c)
+/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO5.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M  (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO5 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO5_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_M  (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO5_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO6.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M  (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO6 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO6_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_M  (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO6_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO7.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M  (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO7 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO7_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_M  (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO7_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO8.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M  (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO8 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO8_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_M  (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO8_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO9.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M  (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO9 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO9_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_M  (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO9_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P2_CFG_REG register
+ *  GPIO selection register 2 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160)
+/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO10.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M  (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO10 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO10_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_M  (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO10_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO11.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M  (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO11 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO11_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_M  (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO11_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO12.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M  (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO12 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO12_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_M  (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO12_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO13.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M  (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO13 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO13_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_M  (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO13_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO14.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M  (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO14 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO14_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_M  (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO14_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P3_CFG_REG register
+ *  GPIO selection register 3 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164)
+/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO15.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M  (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO15 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO15_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_M  (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO15_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO16.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M  (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO16 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO16_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_M  (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO16_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO17.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M  (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO17 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO17_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_M  (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO17_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO18.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M  (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO18 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO18_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_M  (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO18_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO19.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M  (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO19 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO19_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_M  (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO19_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P4_CFG_REG register
+ *  GPIO selection register 4 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168)
+/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO20.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M  (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO20 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO20_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_M  (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO20_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO21.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M  (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO21 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO21_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_M  (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO21_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO22.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M  (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO22 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO22_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_M  (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO22_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO23.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M  (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO23 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO23_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_M  (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO23_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO24.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M  (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO24 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO24_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_M  (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO24_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P5_CFG_REG register
+ *  GPIO selection register 5 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x16c)
+/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO25.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M  (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO25 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO25_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_M  (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO25_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO26.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M  (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO26 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO26_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_M  (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO26_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO27_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO27.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M  (GPIO_EXT_ETM_TASK_GPIO27_SEL_V << GPIO_EXT_ETM_TASK_GPIO27_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO27_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO27 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO27_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_M  (GPIO_EXT_ETM_TASK_GPIO27_EN_V << GPIO_EXT_ETM_TASK_GPIO27_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO27_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO28_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO28.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M  (GPIO_EXT_ETM_TASK_GPIO28_SEL_V << GPIO_EXT_ETM_TASK_GPIO28_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO28_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO28 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO28_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_M  (GPIO_EXT_ETM_TASK_GPIO28_EN_V << GPIO_EXT_ETM_TASK_GPIO28_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO28_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO29_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO29.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M  (GPIO_EXT_ETM_TASK_GPIO29_SEL_V << GPIO_EXT_ETM_TASK_GPIO29_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO29_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO29 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO29_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_M  (GPIO_EXT_ETM_TASK_GPIO29_EN_V << GPIO_EXT_ETM_TASK_GPIO29_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO29_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P6_CFG_REG register
+ *  GPIO selection register 6 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x170)
+/** GPIO_EXT_ETM_TASK_GPIO30_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO30.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_M  (GPIO_EXT_ETM_TASK_GPIO30_SEL_V << GPIO_EXT_ETM_TASK_GPIO30_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO30_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO30_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO30 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO30_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_M  (GPIO_EXT_ETM_TASK_GPIO30_EN_V << GPIO_EXT_ETM_TASK_GPIO30_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO30_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO31_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO31.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_M  (GPIO_EXT_ETM_TASK_GPIO31_SEL_V << GPIO_EXT_ETM_TASK_GPIO31_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO31_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO31_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO31 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO31_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_M  (GPIO_EXT_ETM_TASK_GPIO31_EN_V << GPIO_EXT_ETM_TASK_GPIO31_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO31_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO32_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO32.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_M  (GPIO_EXT_ETM_TASK_GPIO32_SEL_V << GPIO_EXT_ETM_TASK_GPIO32_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO32_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO32_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO32 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO32_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_M  (GPIO_EXT_ETM_TASK_GPIO32_EN_V << GPIO_EXT_ETM_TASK_GPIO32_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO32_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO33_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO33.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_M  (GPIO_EXT_ETM_TASK_GPIO33_SEL_V << GPIO_EXT_ETM_TASK_GPIO33_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO33_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO33_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO33 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO33_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_M  (GPIO_EXT_ETM_TASK_GPIO33_EN_V << GPIO_EXT_ETM_TASK_GPIO33_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO33_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO34_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO34.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_M  (GPIO_EXT_ETM_TASK_GPIO34_SEL_V << GPIO_EXT_ETM_TASK_GPIO34_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO34_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO34_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO34 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO34_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_M  (GPIO_EXT_ETM_TASK_GPIO34_EN_V << GPIO_EXT_ETM_TASK_GPIO34_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO34_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P7_CFG_REG register
+ *  GPIO selection register 7 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x174)
+/** GPIO_EXT_ETM_TASK_GPIO35_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO35.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_M  (GPIO_EXT_ETM_TASK_GPIO35_SEL_V << GPIO_EXT_ETM_TASK_GPIO35_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO35_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO35_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO35 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO35_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_M  (GPIO_EXT_ETM_TASK_GPIO35_EN_V << GPIO_EXT_ETM_TASK_GPIO35_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO35_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO36_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO36.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_M  (GPIO_EXT_ETM_TASK_GPIO36_SEL_V << GPIO_EXT_ETM_TASK_GPIO36_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO36_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO36_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO36 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO36_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_M  (GPIO_EXT_ETM_TASK_GPIO36_EN_V << GPIO_EXT_ETM_TASK_GPIO36_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO36_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO37_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO37.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_M  (GPIO_EXT_ETM_TASK_GPIO37_SEL_V << GPIO_EXT_ETM_TASK_GPIO37_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO37_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO37_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO37 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO37_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_M  (GPIO_EXT_ETM_TASK_GPIO37_EN_V << GPIO_EXT_ETM_TASK_GPIO37_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO37_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO38_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO38.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_M  (GPIO_EXT_ETM_TASK_GPIO38_SEL_V << GPIO_EXT_ETM_TASK_GPIO38_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO38_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO38_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO38 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO38_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_M  (GPIO_EXT_ETM_TASK_GPIO38_EN_V << GPIO_EXT_ETM_TASK_GPIO38_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO38_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO39_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO39.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_M  (GPIO_EXT_ETM_TASK_GPIO39_SEL_V << GPIO_EXT_ETM_TASK_GPIO39_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO39_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO39_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO39 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO39_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_M  (GPIO_EXT_ETM_TASK_GPIO39_EN_V << GPIO_EXT_ETM_TASK_GPIO39_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO39_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P8_CFG_REG register
+ *  GPIO selection register 8 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P8_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x178)
+/** GPIO_EXT_ETM_TASK_GPIO40_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO40.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_M  (GPIO_EXT_ETM_TASK_GPIO40_SEL_V << GPIO_EXT_ETM_TASK_GPIO40_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO40_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO40_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO40 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO40_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_M  (GPIO_EXT_ETM_TASK_GPIO40_EN_V << GPIO_EXT_ETM_TASK_GPIO40_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO40_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO41_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO41.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_M  (GPIO_EXT_ETM_TASK_GPIO41_SEL_V << GPIO_EXT_ETM_TASK_GPIO41_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO41_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO41_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO41 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO41_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_M  (GPIO_EXT_ETM_TASK_GPIO41_EN_V << GPIO_EXT_ETM_TASK_GPIO41_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO41_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO42_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO42.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_M  (GPIO_EXT_ETM_TASK_GPIO42_SEL_V << GPIO_EXT_ETM_TASK_GPIO42_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO42_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO42_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO42 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO42_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_M  (GPIO_EXT_ETM_TASK_GPIO42_EN_V << GPIO_EXT_ETM_TASK_GPIO42_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO42_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO43_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO43.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_M  (GPIO_EXT_ETM_TASK_GPIO43_SEL_V << GPIO_EXT_ETM_TASK_GPIO43_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO43_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO43_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO43 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO43_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_M  (GPIO_EXT_ETM_TASK_GPIO43_EN_V << GPIO_EXT_ETM_TASK_GPIO43_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO43_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO44_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO44.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_M  (GPIO_EXT_ETM_TASK_GPIO44_SEL_V << GPIO_EXT_ETM_TASK_GPIO44_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO44_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO44_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO44 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO44_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_M  (GPIO_EXT_ETM_TASK_GPIO44_EN_V << GPIO_EXT_ETM_TASK_GPIO44_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO44_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P9_CFG_REG register
+ *  GPIO selection register 9 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P9_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x17c)
+/** GPIO_EXT_ETM_TASK_GPIO45_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO45.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_M  (GPIO_EXT_ETM_TASK_GPIO45_SEL_V << GPIO_EXT_ETM_TASK_GPIO45_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO45_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO45_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO45 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO45_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_M  (GPIO_EXT_ETM_TASK_GPIO45_EN_V << GPIO_EXT_ETM_TASK_GPIO45_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO45_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO46_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO46.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_M  (GPIO_EXT_ETM_TASK_GPIO46_SEL_V << GPIO_EXT_ETM_TASK_GPIO46_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO46_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO46_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO46 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO46_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_M  (GPIO_EXT_ETM_TASK_GPIO46_EN_V << GPIO_EXT_ETM_TASK_GPIO46_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO46_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO47_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO47.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_M  (GPIO_EXT_ETM_TASK_GPIO47_SEL_V << GPIO_EXT_ETM_TASK_GPIO47_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO47_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO47_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO47 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO47_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_M  (GPIO_EXT_ETM_TASK_GPIO47_EN_V << GPIO_EXT_ETM_TASK_GPIO47_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO47_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO48_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO48.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_M  (GPIO_EXT_ETM_TASK_GPIO48_SEL_V << GPIO_EXT_ETM_TASK_GPIO48_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO48_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO48_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO48 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO48_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_M  (GPIO_EXT_ETM_TASK_GPIO48_EN_V << GPIO_EXT_ETM_TASK_GPIO48_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO48_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO49_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO49.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_M  (GPIO_EXT_ETM_TASK_GPIO49_SEL_V << GPIO_EXT_ETM_TASK_GPIO49_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO49_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO49_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO49 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO49_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_M  (GPIO_EXT_ETM_TASK_GPIO49_EN_V << GPIO_EXT_ETM_TASK_GPIO49_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO49_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P10_CFG_REG register
+ *  GPIO selection register 10 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P10_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x180)
+/** GPIO_EXT_ETM_TASK_GPIO50_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO50.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_M  (GPIO_EXT_ETM_TASK_GPIO50_SEL_V << GPIO_EXT_ETM_TASK_GPIO50_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO50_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO50_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO50 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO50_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_M  (GPIO_EXT_ETM_TASK_GPIO50_EN_V << GPIO_EXT_ETM_TASK_GPIO50_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO50_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO51_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO51.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_M  (GPIO_EXT_ETM_TASK_GPIO51_SEL_V << GPIO_EXT_ETM_TASK_GPIO51_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO51_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO51_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO51 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO51_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_M  (GPIO_EXT_ETM_TASK_GPIO51_EN_V << GPIO_EXT_ETM_TASK_GPIO51_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO51_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO52_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO52.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_M  (GPIO_EXT_ETM_TASK_GPIO52_SEL_V << GPIO_EXT_ETM_TASK_GPIO52_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO52_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO52_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO52 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO52_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_M  (GPIO_EXT_ETM_TASK_GPIO52_EN_V << GPIO_EXT_ETM_TASK_GPIO52_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO52_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO53_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO53.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_M  (GPIO_EXT_ETM_TASK_GPIO53_SEL_V << GPIO_EXT_ETM_TASK_GPIO53_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO53_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO53_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO53 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO53_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_M  (GPIO_EXT_ETM_TASK_GPIO53_EN_V << GPIO_EXT_ETM_TASK_GPIO53_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO53_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO54_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO54.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_M  (GPIO_EXT_ETM_TASK_GPIO54_SEL_V << GPIO_EXT_ETM_TASK_GPIO54_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO54_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO54_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO54 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO54_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_M  (GPIO_EXT_ETM_TASK_GPIO54_EN_V << GPIO_EXT_ETM_TASK_GPIO54_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO54_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P11_CFG_REG register
+ *  GPIO selection register 11 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P11_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x184)
+/** GPIO_EXT_ETM_TASK_GPIO55_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO55.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO55_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO55_SEL_M  (GPIO_EXT_ETM_TASK_GPIO55_SEL_V << GPIO_EXT_ETM_TASK_GPIO55_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO55_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO55_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO55_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO55 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO55_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO55_EN_M  (GPIO_EXT_ETM_TASK_GPIO55_EN_V << GPIO_EXT_ETM_TASK_GPIO55_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO55_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO55_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO56_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO56.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO56_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO56_SEL_M  (GPIO_EXT_ETM_TASK_GPIO56_SEL_V << GPIO_EXT_ETM_TASK_GPIO56_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO56_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO56_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO56_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO56 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO56_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO56_EN_M  (GPIO_EXT_ETM_TASK_GPIO56_EN_V << GPIO_EXT_ETM_TASK_GPIO56_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO56_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO56_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO57_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO57.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO57_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO57_SEL_M  (GPIO_EXT_ETM_TASK_GPIO57_SEL_V << GPIO_EXT_ETM_TASK_GPIO57_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO57_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO57_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO57_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO57 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO57_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO57_EN_M  (GPIO_EXT_ETM_TASK_GPIO57_EN_V << GPIO_EXT_ETM_TASK_GPIO57_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO57_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO57_EN_S  17
+/** GPIO_EXT_ETM_TASK_GPIO58_SEL : R/W; bitpos: [20:18]; default: 0;
+ *  Configures to select an ETM task channel for GPIO58.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO58_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO58_SEL_M  (GPIO_EXT_ETM_TASK_GPIO58_SEL_V << GPIO_EXT_ETM_TASK_GPIO58_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO58_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO58_SEL_S  18
+/** GPIO_EXT_ETM_TASK_GPIO58_EN : R/W; bitpos: [23]; default: 0;
+ *  Configures whether or not to enable GPIO58 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO58_EN    (BIT(23))
+#define GPIO_EXT_ETM_TASK_GPIO58_EN_M  (GPIO_EXT_ETM_TASK_GPIO58_EN_V << GPIO_EXT_ETM_TASK_GPIO58_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO58_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO58_EN_S  23
+/** GPIO_EXT_ETM_TASK_GPIO59_SEL : R/W; bitpos: [26:24]; default: 0;
+ *  Configures to select an ETM task channel for GPIO59.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO59_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO59_SEL_M  (GPIO_EXT_ETM_TASK_GPIO59_SEL_V << GPIO_EXT_ETM_TASK_GPIO59_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO59_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO59_SEL_S  24
+/** GPIO_EXT_ETM_TASK_GPIO59_EN : R/W; bitpos: [29]; default: 0;
+ *  Configures whether or not to enable GPIO59 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO59_EN    (BIT(29))
+#define GPIO_EXT_ETM_TASK_GPIO59_EN_M  (GPIO_EXT_ETM_TASK_GPIO59_EN_V << GPIO_EXT_ETM_TASK_GPIO59_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO59_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO59_EN_S  29
+
+/** GPIO_EXT_ETM_TASK_P12_CFG_REG register
+ *  GPIO selection register 12 for ETM
+ */
+#define GPIO_EXT_ETM_TASK_P12_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x188)
+/** GPIO_EXT_ETM_TASK_GPIO60_SEL : R/W; bitpos: [2:0]; default: 0;
+ *  Configures to select an ETM task channel for GPIO60.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO60_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO60_SEL_M  (GPIO_EXT_ETM_TASK_GPIO60_SEL_V << GPIO_EXT_ETM_TASK_GPIO60_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO60_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO60_SEL_S  0
+/** GPIO_EXT_ETM_TASK_GPIO60_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether or not to enable GPIO60 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO60_EN    (BIT(5))
+#define GPIO_EXT_ETM_TASK_GPIO60_EN_M  (GPIO_EXT_ETM_TASK_GPIO60_EN_V << GPIO_EXT_ETM_TASK_GPIO60_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO60_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO60_EN_S  5
+/** GPIO_EXT_ETM_TASK_GPIO61_SEL : R/W; bitpos: [8:6]; default: 0;
+ *  Configures to select an ETM task channel for GPIO61.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO61_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO61_SEL_M  (GPIO_EXT_ETM_TASK_GPIO61_SEL_V << GPIO_EXT_ETM_TASK_GPIO61_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO61_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO61_SEL_S  6
+/** GPIO_EXT_ETM_TASK_GPIO61_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to enable GPIO61 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO61_EN    (BIT(11))
+#define GPIO_EXT_ETM_TASK_GPIO61_EN_M  (GPIO_EXT_ETM_TASK_GPIO61_EN_V << GPIO_EXT_ETM_TASK_GPIO61_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO61_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO61_EN_S  11
+/** GPIO_EXT_ETM_TASK_GPIO62_SEL : R/W; bitpos: [14:12]; default: 0;
+ *  Configures to select an ETM task channel for GPIO62.
+ *  0: Select channel 0
+ *  1: Select channel 1
+ *  ......
+ *  7: Select channel 7
+ */
+#define GPIO_EXT_ETM_TASK_GPIO62_SEL    0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO62_SEL_M  (GPIO_EXT_ETM_TASK_GPIO62_SEL_V << GPIO_EXT_ETM_TASK_GPIO62_SEL_S)
+#define GPIO_EXT_ETM_TASK_GPIO62_SEL_V  0x00000007U
+#define GPIO_EXT_ETM_TASK_GPIO62_SEL_S  12
+/** GPIO_EXT_ETM_TASK_GPIO62_EN : R/W; bitpos: [17]; default: 0;
+ *  Configures whether or not to enable GPIO62 to response ETM task.
+ *  0: Not enable
+ *  1: Enable
+ */
+#define GPIO_EXT_ETM_TASK_GPIO62_EN    (BIT(17))
+#define GPIO_EXT_ETM_TASK_GPIO62_EN_M  (GPIO_EXT_ETM_TASK_GPIO62_EN_V << GPIO_EXT_ETM_TASK_GPIO62_EN_S)
+#define GPIO_EXT_ETM_TASK_GPIO62_EN_V  0x00000001U
+#define GPIO_EXT_ETM_TASK_GPIO62_EN_S  17
+
+/** GPIO_EXT_VERSION_REG register
+ *  Version control register
+ */
+#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc)
+/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 38830416;
+ *  Version control register.
+ */
+#define GPIO_EXT_DATE    0x0FFFFFFFU
+#define GPIO_EXT_DATE_M  (GPIO_EXT_DATE_V << GPIO_EXT_DATE_S)
+#define GPIO_EXT_DATE_V  0x0FFFFFFFU
+#define GPIO_EXT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gpio_ext_struct.h b/components/soc/esp32s31/register/soc/gpio_ext_struct.h
new file mode 100644
index 00000000000..e4525c5b7dd
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gpio_ext_struct.h
@@ -0,0 +1,1243 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: SDM Configure Registers */
+/** Type of sigmadelta_misc register
+ *  MISC Register
+ */
+typedef union {
+    struct {
+        /** sigmadelta_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable the clock for sigma delta modulation.
+         *  0: Not enable
+         *  1: Enable
+         *  %\label{fielddesc:GPIOSDSPISWAP}- [GPIOSD_SPI_SWAP] Reserved.
+         */
+        uint32_t sigmadelta_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_ext_sigmadelta_misc_reg_t;
+
+/** Type of sigmadeltan register
+ *  Duty cycle configuration register for SDM channel n
+ */
+typedef union {
+    struct {
+        /** sdn_in : R/W; bitpos: [7:0]; default: 0;
+         *  Configures the duty cycle of sigma delta modulation output.
+         */
+        uint32_t sdn_in:8;
+        /** sdn_prescale : R/W; bitpos: [15:8]; default: 255;
+         *  Configures the divider value to divide IO MUX operating clock.
+         */
+        uint32_t sdn_prescale:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_ext_sigmadeltan_reg_t;
+
+
+/** Group: Glitch filter Configure Registers */
+/** Type of glitch_filter_chn register
+ *  Glitch Filter Configure Register of Channeln
+ */
+typedef union {
+    struct {
+        /** filter_ch0_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable channel n of Glitch Filter.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t filter_ch0_en:1;
+        /** filter_ch0_input_io_num : R/W; bitpos: [7:1]; default: 0;
+         *  Configures to select the input GPIO for Glitch Filter.
+         *  0: Select GPIO0
+         *  1: Select GPIO1
+         *  ......
+         *  61: Select GPIO61
+         *  62: Select GPIO62
+         *  63 ~ 127: Reserved
+         */
+        uint32_t filter_ch0_input_io_num:7;
+        /** filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
+         *  Configures the window threshold for Glitch Filter. The window threshold should be
+         *  less than or equal to GPIOSD_FILTER_CHn_WINDOW_WIDTH.
+         *  %see DOC-4768
+         *  Measurement unit: IO MUX operating clock cycle
+         */
+        uint32_t filter_ch0_window_thres:6;
+        /** filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
+         *  Configures the window width for Glitch Filter. The effective value of window width
+         *  is 0 ~ 63.
+         *  Measurement unit: IO MUX operating clock cycle
+         */
+        uint32_t filter_ch0_window_width:6;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} gpio_ext_glitch_filter_chn_reg_t;
+
+
+/** Group: ETM Configuration Registers */
+/** Type of etm_event_chn_cfg register
+ *  ETM configuration register for channel n
+ */
+typedef union {
+    struct {
+        /** etm_chn_event_sel : R/W; bitpos: [6:0]; default: 0;
+         *  Configures to select GPIO for ETM event channel.
+         *  0: Select GPIO0
+         *  1: Select GPIO1
+         *  ......
+         *  61: Select GPIO61
+         *  62: Select GPIO62
+         *  63 ~ 127: Reserved
+         */
+        uint32_t etm_chn_event_sel:7;
+        /** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable ETM event send.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_chn_event_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} gpio_ext_etm_event_chn_cfg_reg_t;
+
+/** Type of etm_task_p0_cfg register
+ *  GPIO selection register 0 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO0.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio0_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO0 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio0_en:1;
+        /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO1.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio1_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO1 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio1_en:1;
+        /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO2.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio2_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO2 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio2_en:1;
+        /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO3.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio3_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO3 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio3_en:1;
+        /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO4.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio4_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO4 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio4_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p0_cfg_reg_t;
+
+/** Type of etm_task_p1_cfg register
+ *  GPIO selection register 1 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO5.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio5_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO5 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio5_en:1;
+        /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO6.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio6_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO6 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio6_en:1;
+        /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO7.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio7_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO7 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio7_en:1;
+        /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO8.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio8_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO8 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio8_en:1;
+        /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO9.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio9_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO9 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio9_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p1_cfg_reg_t;
+
+/** Type of etm_task_p2_cfg register
+ *  GPIO selection register 2 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO10.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio10_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO10 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio10_en:1;
+        /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO11.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio11_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO11 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio11_en:1;
+        /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO12.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio12_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO12 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio12_en:1;
+        /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO13.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio13_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO13 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio13_en:1;
+        /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO14.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio14_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO14 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio14_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p2_cfg_reg_t;
+
+/** Type of etm_task_p3_cfg register
+ *  GPIO selection register 3 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO15.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio15_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO15 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio15_en:1;
+        /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO16.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio16_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO16 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio16_en:1;
+        /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO17.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio17_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO17 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio17_en:1;
+        /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO18.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio18_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO18 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio18_en:1;
+        /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO19.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio19_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO19 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio19_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p3_cfg_reg_t;
+
+/** Type of etm_task_p4_cfg register
+ *  GPIO selection register 4 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO20.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio20_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO20 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio20_en:1;
+        /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO21.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio21_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO21 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio21_en:1;
+        /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO22.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio22_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO22 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio22_en:1;
+        /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO23.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio23_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO23 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio23_en:1;
+        /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO24.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio24_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO24 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio24_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p4_cfg_reg_t;
+
+/** Type of etm_task_p5_cfg register
+ *  GPIO selection register 5 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO25.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio25_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO25 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio25_en:1;
+        /** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO26.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio26_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO26 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio26_en:1;
+        /** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO27.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio27_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO27 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio27_en:1;
+        /** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO28.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio28_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO28 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio28_en:1;
+        /** etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO29.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio29_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio29_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO29 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio29_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p5_cfg_reg_t;
+
+/** Type of etm_task_p6_cfg register
+ *  GPIO selection register 6 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio30_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO30.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio30_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio30_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO30 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio30_en:1;
+        /** etm_task_gpio31_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO31.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio31_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio31_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO31 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio31_en:1;
+        /** etm_task_gpio32_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO32.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio32_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio32_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO32 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio32_en:1;
+        /** etm_task_gpio33_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO33.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio33_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio33_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO33 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio33_en:1;
+        /** etm_task_gpio34_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO34.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio34_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio34_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO34 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio34_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p6_cfg_reg_t;
+
+/** Type of etm_task_p7_cfg register
+ *  GPIO selection register 7 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio35_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO35.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio35_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio35_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO35 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio35_en:1;
+        /** etm_task_gpio36_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO36.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio36_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio36_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO36 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio36_en:1;
+        /** etm_task_gpio37_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO37.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio37_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio37_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO37 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio37_en:1;
+        /** etm_task_gpio38_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO38.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio38_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio38_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO38 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio38_en:1;
+        /** etm_task_gpio39_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO39.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio39_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio39_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO39 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio39_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p7_cfg_reg_t;
+
+/** Type of etm_task_p8_cfg register
+ *  GPIO selection register 8 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio40_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO40.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio40_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio40_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO40 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio40_en:1;
+        /** etm_task_gpio41_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO41.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio41_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio41_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO41 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio41_en:1;
+        /** etm_task_gpio42_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO42.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio42_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio42_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO42 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio42_en:1;
+        /** etm_task_gpio43_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO43.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio43_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio43_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO43 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio43_en:1;
+        /** etm_task_gpio44_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO44.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio44_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio44_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO44 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio44_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p8_cfg_reg_t;
+
+/** Type of etm_task_p9_cfg register
+ *  GPIO selection register 9 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio45_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO45.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio45_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio45_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO45 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio45_en:1;
+        /** etm_task_gpio46_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO46.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio46_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio46_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO46 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio46_en:1;
+        /** etm_task_gpio47_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO47.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio47_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio47_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO47 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio47_en:1;
+        /** etm_task_gpio48_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO48.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio48_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio48_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO48 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio48_en:1;
+        /** etm_task_gpio49_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO49.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio49_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio49_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO49 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio49_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p9_cfg_reg_t;
+
+/** Type of etm_task_p10_cfg register
+ *  GPIO selection register 10 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio50_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO50.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio50_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio50_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO50 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio50_en:1;
+        /** etm_task_gpio51_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO51.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio51_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio51_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO51 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio51_en:1;
+        /** etm_task_gpio52_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO52.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio52_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio52_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO52 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio52_en:1;
+        /** etm_task_gpio53_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO53.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio53_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio53_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO53 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio53_en:1;
+        /** etm_task_gpio54_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO54.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio54_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio54_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO54 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio54_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p10_cfg_reg_t;
+
+/** Type of etm_task_p11_cfg register
+ *  GPIO selection register 11 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio55_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO55.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio55_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio55_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO55 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio55_en:1;
+        /** etm_task_gpio56_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO56.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio56_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio56_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO56 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio56_en:1;
+        /** etm_task_gpio57_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO57.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio57_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio57_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO57 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio57_en:1;
+        /** etm_task_gpio58_sel : R/W; bitpos: [20:18]; default: 0;
+         *  Configures to select an ETM task channel for GPIO58.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio58_sel:3;
+        uint32_t reserved_21:2;
+        /** etm_task_gpio58_en : R/W; bitpos: [23]; default: 0;
+         *  Configures whether or not to enable GPIO58 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio58_en:1;
+        /** etm_task_gpio59_sel : R/W; bitpos: [26:24]; default: 0;
+         *  Configures to select an ETM task channel for GPIO59.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio59_sel:3;
+        uint32_t reserved_27:2;
+        /** etm_task_gpio59_en : R/W; bitpos: [29]; default: 0;
+         *  Configures whether or not to enable GPIO59 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio59_en:1;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p11_cfg_reg_t;
+
+/** Type of etm_task_p12_cfg register
+ *  GPIO selection register 12 for ETM
+ */
+typedef union {
+    struct {
+        /** etm_task_gpio60_sel : R/W; bitpos: [2:0]; default: 0;
+         *  Configures to select an ETM task channel for GPIO60.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio60_sel:3;
+        uint32_t reserved_3:2;
+        /** etm_task_gpio60_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether or not to enable GPIO60 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio60_en:1;
+        /** etm_task_gpio61_sel : R/W; bitpos: [8:6]; default: 0;
+         *  Configures to select an ETM task channel for GPIO61.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio61_sel:3;
+        uint32_t reserved_9:2;
+        /** etm_task_gpio61_en : R/W; bitpos: [11]; default: 0;
+         *  Configures whether or not to enable GPIO61 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio61_en:1;
+        /** etm_task_gpio62_sel : R/W; bitpos: [14:12]; default: 0;
+         *  Configures to select an ETM task channel for GPIO62.
+         *  0: Select channel 0
+         *  1: Select channel 1
+         *  ......
+         *  7: Select channel 7
+         */
+        uint32_t etm_task_gpio62_sel:3;
+        uint32_t reserved_15:2;
+        /** etm_task_gpio62_en : R/W; bitpos: [17]; default: 0;
+         *  Configures whether or not to enable GPIO62 to response ETM task.
+         *  0: Not enable
+         *  1: Enable
+         */
+        uint32_t etm_task_gpio62_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_ext_etm_task_p12_cfg_reg_t;
+
+
+/** Group: Version Register */
+/** Type of version register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38830416;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_ext_version_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile gpio_ext_sigmadelta_misc_reg_t sigmadelta_misc;
+    volatile gpio_ext_sigmadeltan_reg_t sigmadeltan[8];
+    uint32_t reserved_028[44];
+    volatile gpio_ext_glitch_filter_chn_reg_t glitch_filter_chn[8];
+    uint32_t reserved_0f8[8];
+    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_138[8];
+    volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
+    volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
+    volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
+    volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
+    volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpio_ext_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
+    volatile gpio_ext_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
+    volatile gpio_ext_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
+    volatile gpio_ext_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
+    volatile gpio_ext_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
+    volatile gpio_ext_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
+    volatile gpio_ext_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
+    volatile gpio_ext_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
+    uint32_t reserved_18c[28];
+    volatile gpio_ext_version_reg_t version;
+} gpio_ext_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gpio_reg.h b/components/soc/esp32s31/register/soc/gpio_reg.h
new file mode 100644
index 00000000000..4248e40498c
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gpio_reg.h
@@ -0,0 +1,19042 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** GPIO_STRAP_REG register
+ *  Strapping pin register
+ */
+#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0)
+/** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0;
+ *  Represents the values of GPIO strapping pins. (need update the description, for
+ *  example)
+ *
+ *  - bit0: invalid
+ *  - bit1: MTMS
+ *  - bit2: MTDI
+ *  - bit3: GPIO27
+ *  - bit4: GPIO28
+ *  - bit5: GPIO7
+ *  - bit6 ~ bit15: invalid
+ */
+#define GPIO_STRAPPING    0x0000FFFFU
+#define GPIO_STRAPPING_M  (GPIO_STRAPPING_V << GPIO_STRAPPING_S)
+#define GPIO_STRAPPING_V  0x0000FFFFU
+#define GPIO_STRAPPING_S  0
+
+/** GPIO_OUT_REG register
+ *  GPIO output register
+ */
+#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4)
+/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+ *  Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode.
+ *  0: Low level
+ *  1: High level
+ *  The value of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31
+ *  respectively. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_OUT_DATA_ORIG    0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_M  (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S)
+#define GPIO_OUT_DATA_ORIG_V  0xFFFFFFFFU
+#define GPIO_OUT_DATA_ORIG_S  0
+
+/** GPIO_OUT_W1TS_REG register
+ *  GPIO output set register
+ */
+#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8)
+/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ GPIO31.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_OUT_REG will be set to 1
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_OUT_REG.
+ */
+#define GPIO_OUT_W1TS    0xFFFFFFFFU
+#define GPIO_OUT_W1TS_M  (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S)
+#define GPIO_OUT_W1TS_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TS_S  0
+
+/** GPIO_OUT_W1TC_REG register
+ *  GPIO output clear register
+ */
+#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc)
+/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
+ *  GPIO31 output.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_OUT_REG will be cleared.
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_OUT_REG.
+ */
+#define GPIO_OUT_W1TC    0xFFFFFFFFU
+#define GPIO_OUT_W1TC_M  (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S)
+#define GPIO_OUT_W1TC_V  0xFFFFFFFFU
+#define GPIO_OUT_W1TC_S  0
+
+/** GPIO_OUT1_REG register
+ *  GPIO output register
+ */
+#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10)
+/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+ *  Configures the output value of GPIO32 ~ 63 output in simple GPIO output mode.
+ *  0: Low level
+ *  1: High level
+ *  The value of bit32 ~ bit63 correspond to the output value of GPIO32 ~ GPIO63
+ *  respectively. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_OUT1_DATA_ORIG    0xFFFFFFFFU
+#define GPIO_OUT1_DATA_ORIG_M  (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S)
+#define GPIO_OUT1_DATA_ORIG_V  0xFFFFFFFFU
+#define GPIO_OUT1_DATA_ORIG_S  0
+
+/** GPIO_OUT1_W1TS_REG register
+ *  GPIO output set register
+ */
+#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14)
+/** GPIO_OUT1_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the output register GPIO_OUT1_REG of GPIO32 ~
+ *  GPIO63.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_OUT1_REG will be set to 1
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_OUT1_REG.
+ */
+#define GPIO_OUT1_W1TS    0xFFFFFFFFU
+#define GPIO_OUT1_W1TS_M  (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S)
+#define GPIO_OUT1_W1TS_V  0xFFFFFFFFU
+#define GPIO_OUT1_W1TS_S  0
+
+/** GPIO_OUT1_W1TC_REG register
+ *  GPIO output clear register
+ */
+#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18)
+/** GPIO_OUT1_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the output register GPIO_OUT1_REG of GPIO32 ~
+ *  GPIO63 output.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_OUT1_REG will be cleared.
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_OUT1_REG.
+ */
+#define GPIO_OUT1_W1TC    0xFFFFFFFFU
+#define GPIO_OUT1_W1TC_M  (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S)
+#define GPIO_OUT1_W1TC_V  0xFFFFFFFFU
+#define GPIO_OUT1_W1TC_S  0
+
+/** GPIO_OUT2_REG register
+ *  GPIO output register
+ */
+#define GPIO_OUT2_REG (DR_REG_GPIO_BASE + 0x1c)
+/** GPIO_OUT2_DATA_ORIG : R/W/SC/WTC; bitpos: [2:0]; default: 0;
+ *  Configures the output value of GPIO64 ~ 66 output in simple GPIO output mode.
+ *  0: Low level
+ *  1: High level
+ *  The value of bit64 ~ bit66 correspond to the output value of GPIO64 ~ GPIO66
+ *  respectively. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_OUT2_DATA_ORIG    0x00000007U
+#define GPIO_OUT2_DATA_ORIG_M  (GPIO_OUT2_DATA_ORIG_V << GPIO_OUT2_DATA_ORIG_S)
+#define GPIO_OUT2_DATA_ORIG_V  0x00000007U
+#define GPIO_OUT2_DATA_ORIG_S  0
+
+/** GPIO_OUT2_W1TS_REG register
+ *  GPIO output set register
+ */
+#define GPIO_OUT2_W1TS_REG (DR_REG_GPIO_BASE + 0x20)
+/** GPIO_OUT2_W1TS : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to set the output register GPIO_OUT2_REG of GPIO64 ~
+ *  GPIO66.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_OUT2_REG will be set to 1
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_OUT2_REG.
+ */
+#define GPIO_OUT2_W1TS    0x00000007U
+#define GPIO_OUT2_W1TS_M  (GPIO_OUT2_W1TS_V << GPIO_OUT2_W1TS_S)
+#define GPIO_OUT2_W1TS_V  0x00000007U
+#define GPIO_OUT2_W1TS_S  0
+
+/** GPIO_OUT2_W1TC_REG register
+ *  GPIO output clear register
+ */
+#define GPIO_OUT2_W1TC_REG (DR_REG_GPIO_BASE + 0x24)
+/** GPIO_OUT2_W1TC : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to clear the output register GPIO_OUT2_REG of GPIO64 ~
+ *  GPIO66 output.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_OUT2_REG will be cleared.
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_OUT2_REG.
+ */
+#define GPIO_OUT2_W1TC    0x00000007U
+#define GPIO_OUT2_W1TC_M  (GPIO_OUT2_W1TC_V << GPIO_OUT2_W1TC_S)
+#define GPIO_OUT2_W1TC_V  0x00000007U
+#define GPIO_OUT2_W1TC_S  0
+
+/** GPIO_ENABLE_REG register
+ *  GPIO output enable register
+ */
+#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34)
+/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to enable the output of GPIO0 ~ GPIO31.
+ *  0: Not enable
+ *  1: Enable
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_ENABLE_DATA    0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_M  (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S)
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFFU
+#define GPIO_ENABLE_DATA_S  0
+
+/** GPIO_ENABLE_W1TS_REG register
+ *  GPIO output enable set register
+ */
+#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38)
+/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
+ *  GPIO0 ~ GPIO31.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_ENABLE_REG.
+ */
+#define GPIO_ENABLE_W1TS    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_M  (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S)
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TS_S  0
+
+/** GPIO_ENABLE_W1TC_REG register
+ *  GPIO output enable clear register
+ */
+#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c)
+/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
+ *  GPIO0 ~ GPIO31.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_ENABLE_REG.
+ */
+#define GPIO_ENABLE_W1TC    0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_M  (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S)
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFFU
+#define GPIO_ENABLE_W1TC_S  0
+
+/** GPIO_ENABLE1_REG register
+ *  GPIO output enable register
+ */
+#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x40)
+/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to enable the output of GPIO32 ~ GPIO63.
+ *  0: Not enable
+ *  1: Enable
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_ENABLE1_DATA    0xFFFFFFFFU
+#define GPIO_ENABLE1_DATA_M  (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S)
+#define GPIO_ENABLE1_DATA_V  0xFFFFFFFFU
+#define GPIO_ENABLE1_DATA_S  0
+
+/** GPIO_ENABLE1_W1TS_REG register
+ *  GPIO output enable set register
+ */
+#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x44)
+/** GPIO_ENABLE1_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the output enable register GPIO_ENABLE1_REG of
+ *  GPIO32 ~ GPIO63.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_ENABLE1_REG will be set to 1
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_ENABLE1_REG.
+ */
+#define GPIO_ENABLE1_W1TS    0xFFFFFFFFU
+#define GPIO_ENABLE1_W1TS_M  (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S)
+#define GPIO_ENABLE1_W1TS_V  0xFFFFFFFFU
+#define GPIO_ENABLE1_W1TS_S  0
+
+/** GPIO_ENABLE1_W1TC_REG register
+ *  GPIO output enable clear register
+ */
+#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x48)
+/** GPIO_ENABLE1_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the output enable register GPIO_ENABLE1_REG of
+ *  GPIO32 ~ GPIO63.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_ENABLE1_REG will be cleared
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_ENABLE1_REG.
+ */
+#define GPIO_ENABLE1_W1TC    0xFFFFFFFFU
+#define GPIO_ENABLE1_W1TC_M  (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S)
+#define GPIO_ENABLE1_W1TC_V  0xFFFFFFFFU
+#define GPIO_ENABLE1_W1TC_S  0
+
+/** GPIO_ENABLE2_REG register
+ *  GPIO output enable register
+ */
+#define GPIO_ENABLE2_REG (DR_REG_GPIO_BASE + 0x4c)
+/** GPIO_ENABLE2_DATA : R/W/WTC; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to enable the output of GPIO64 ~ GPIO66.
+ *  0: Not enable
+ *  1: Enable
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_ENABLE2_DATA    0x00000007U
+#define GPIO_ENABLE2_DATA_M  (GPIO_ENABLE2_DATA_V << GPIO_ENABLE2_DATA_S)
+#define GPIO_ENABLE2_DATA_V  0x00000007U
+#define GPIO_ENABLE2_DATA_S  0
+
+/** GPIO_ENABLE2_W1TS_REG register
+ *  GPIO output enable set register
+ */
+#define GPIO_ENABLE2_W1TS_REG (DR_REG_GPIO_BASE + 0x50)
+/** GPIO_ENABLE2_W1TS : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to set the output enable register GPIO_ENABLE2_REG of
+ *  GPIO64 ~ GPIO66.
+ *  0: Not set
+ *  1: The corresponding bit in GPIO_ENABLE2_REG will be set to 1
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to set GPIO_ENABLE2_REG.
+ */
+#define GPIO_ENABLE2_W1TS    0x00000007U
+#define GPIO_ENABLE2_W1TS_M  (GPIO_ENABLE2_W1TS_V << GPIO_ENABLE2_W1TS_S)
+#define GPIO_ENABLE2_W1TS_V  0x00000007U
+#define GPIO_ENABLE2_W1TS_S  0
+
+/** GPIO_ENABLE2_W1TC_REG register
+ *  GPIO output enable clear register
+ */
+#define GPIO_ENABLE2_W1TC_REG (DR_REG_GPIO_BASE + 0x54)
+/** GPIO_ENABLE2_W1TC : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to clear the output enable register GPIO_ENABLE2_REG of
+ *  GPIO64 ~ GPIO66.
+ *  0: Not clear
+ *  1: The corresponding bit in GPIO_ENABLE2_REG will be cleared
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  Recommended operation: use this register to clear GPIO_ENABLE2_REG.
+ */
+#define GPIO_ENABLE2_W1TC    0x00000007U
+#define GPIO_ENABLE2_W1TC_M  (GPIO_ENABLE2_W1TC_V << GPIO_ENABLE2_W1TC_S)
+#define GPIO_ENABLE2_W1TC_V  0x00000007U
+#define GPIO_ENABLE2_W1TC_S  0
+
+/** GPIO_IN_REG register
+ *  GPIO input register
+ */
+#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64)
+/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input value:
+ *  0: Low level
+ *  1: High level
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_IN_DATA_NEXT    0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_M  (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S)
+#define GPIO_IN_DATA_NEXT_V  0xFFFFFFFFU
+#define GPIO_IN_DATA_NEXT_S  0
+
+/** GPIO_IN1_REG register
+ *  GPIO input register
+ */
+#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x68)
+/** GPIO_IN1_DATA_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  Represents the input value of GPIO32 ~ GPIO63. Each bit represents a pin input
+ *  value:
+ *  0: Low level
+ *  1: High level
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_IN1_DATA_NEXT    0xFFFFFFFFU
+#define GPIO_IN1_DATA_NEXT_M  (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S)
+#define GPIO_IN1_DATA_NEXT_V  0xFFFFFFFFU
+#define GPIO_IN1_DATA_NEXT_S  0
+
+/** GPIO_IN2_REG register
+ *  GPIO input register
+ */
+#define GPIO_IN2_REG (DR_REG_GPIO_BASE + 0x6c)
+/** GPIO_IN2_DATA_NEXT : RO; bitpos: [2:0]; default: 0;
+ *  Represents the input value of GPIO64 ~ GPIO66. Each bit represents a pin input
+ *  value:
+ *  0: Low level
+ *  1: High level
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ */
+#define GPIO_IN2_DATA_NEXT    0x00000007U
+#define GPIO_IN2_DATA_NEXT_M  (GPIO_IN2_DATA_NEXT_V << GPIO_IN2_DATA_NEXT_S)
+#define GPIO_IN2_DATA_NEXT_V  0x00000007U
+#define GPIO_IN2_DATA_NEXT_S  0
+
+/** GPIO_STATUS_REG register
+ *  GPIO interrupt status register
+ */
+#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74)
+/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  The interrupt status of GPIO0 ~ GPIO31, can be configured by the software.
+ *
+ *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  - Each bit represents the status of its corresponding GPIO:
+ *
+ *  - 0: Represents the GPIO does not generate the interrupt configured by
+ *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+ *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+ *  or this bit is configured to 1 by the software.
+ *
+ */
+#define GPIO_STATUS_INTERRUPT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_M  (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S)
+#define GPIO_STATUS_INTERRUPT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_S  0
+
+/** GPIO_STATUS_W1TS_REG register
+ *  GPIO interrupt status set register
+ */
+#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78)
+/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the interrupt status register
+ *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
+ *
+ *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
+ *  register to set GPIO_STATUS_INTERRUPT.
+ */
+#define GPIO_STATUS_W1TS    0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_M  (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S)
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TS_S  0
+
+/** GPIO_STATUS_W1TC_REG register
+ *  GPIO interrupt status clear register
+ */
+#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c)
+/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the interrupt status register
+ *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
+ *
+ *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
+ *  register to clear GPIO_STATUS_INTERRUPT.
+ */
+#define GPIO_STATUS_W1TC    0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_M  (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S)
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFFU
+#define GPIO_STATUS_W1TC_S  0
+
+/** GPIO_STATUS1_REG register
+ *  GPIO interrupt status register
+ */
+#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x80)
+/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0;
+ *  The interrupt status of GPIO32 ~ GPIO63, can be configured by the software.
+ *
+ *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  - Each bit represents the status of its corresponding GPIO:
+ *
+ *  - 0: Represents the GPIO does not generate the interrupt configured by
+ *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+ *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+ *  or this bit is configured to 1 by the software.
+ *
+ */
+#define GPIO_STATUS1_INTERRUPT    0xFFFFFFFFU
+#define GPIO_STATUS1_INTERRUPT_M  (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S)
+#define GPIO_STATUS1_INTERRUPT_V  0xFFFFFFFFU
+#define GPIO_STATUS1_INTERRUPT_S  0
+
+/** GPIO_STATUS1_W1TS_REG register
+ *  GPIO interrupt status set register
+ */
+#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x84)
+/** GPIO_STATUS1_W1TS : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to set the interrupt status register
+ *  GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO63.
+ *
+ *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS1_INTERRUPT will be set to 1. \item Recommended operation: use this
+ *  register to set GPIO_STATUS1_INTERRUPT.
+ */
+#define GPIO_STATUS1_W1TS    0xFFFFFFFFU
+#define GPIO_STATUS1_W1TS_M  (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S)
+#define GPIO_STATUS1_W1TS_V  0xFFFFFFFFU
+#define GPIO_STATUS1_W1TS_S  0
+
+/** GPIO_STATUS1_W1TC_REG register
+ *  GPIO interrupt status clear register
+ */
+#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x88)
+/** GPIO_STATUS1_W1TC : WT; bitpos: [31:0]; default: 0;
+ *  Configures whether or not to clear the interrupt status register
+ *  GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO63.
+ *
+ *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS1_INTERRUPT will be cleared. \item Recommended operation: use this
+ *  register to clear GPIO_STATUS1_INTERRUPT.
+ */
+#define GPIO_STATUS1_W1TC    0xFFFFFFFFU
+#define GPIO_STATUS1_W1TC_M  (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S)
+#define GPIO_STATUS1_W1TC_V  0xFFFFFFFFU
+#define GPIO_STATUS1_W1TC_S  0
+
+/** GPIO_STATUS2_REG register
+ *  GPIO interrupt status register
+ */
+#define GPIO_STATUS2_REG (DR_REG_GPIO_BASE + 0x8c)
+/** GPIO_STATUS2_INTERRUPT : R/W/WTC; bitpos: [2:0]; default: 0;
+ *  The interrupt status of GPIO64 ~ GPIO66, can be configured by the software.
+ *
+ *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  - Each bit represents the status of its corresponding GPIO:
+ *
+ *  - 0: Represents the GPIO does not generate the interrupt configured by
+ *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+ *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+ *  or this bit is configured to 1 by the software.
+ *
+ */
+#define GPIO_STATUS2_INTERRUPT    0x00000007U
+#define GPIO_STATUS2_INTERRUPT_M  (GPIO_STATUS2_INTERRUPT_V << GPIO_STATUS2_INTERRUPT_S)
+#define GPIO_STATUS2_INTERRUPT_V  0x00000007U
+#define GPIO_STATUS2_INTERRUPT_S  0
+
+/** GPIO_STATUS2_W1TS_REG register
+ *  GPIO interrupt status set register
+ */
+#define GPIO_STATUS2_W1TS_REG (DR_REG_GPIO_BASE + 0x90)
+/** GPIO_STATUS2_W1TS : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to set the interrupt status register
+ *  GPIO_STATUS2_INTERRUPT of GPIO64 ~ GPIO66.
+ *
+ *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS2_INTERRUPT will be set to 1. \item Recommended operation: use this
+ *  register to set GPIO_STATUS2_INTERRUPT.
+ */
+#define GPIO_STATUS2_W1TS    0x00000007U
+#define GPIO_STATUS2_W1TS_M  (GPIO_STATUS2_W1TS_V << GPIO_STATUS2_W1TS_S)
+#define GPIO_STATUS2_W1TS_V  0x00000007U
+#define GPIO_STATUS2_W1TS_S  0
+
+/** GPIO_STATUS2_W1TC_REG register
+ *  GPIO interrupt status clear register
+ */
+#define GPIO_STATUS2_W1TC_REG (DR_REG_GPIO_BASE + 0x94)
+/** GPIO_STATUS2_W1TC : WT; bitpos: [2:0]; default: 0;
+ *  Configures whether or not to clear the interrupt status register
+ *  GPIO_STATUS2_INTERRUPT of GPIO64 ~ GPIO66.
+ *
+ *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+ *  - If the value 1 is written to a bit here, the corresponding bit in
+ *  GPIO_STATUS2_INTERRUPT will be cleared. \item Recommended operation: use this
+ *  register to clear GPIO_STATUS2_INTERRUPT.
+ */
+#define GPIO_STATUS2_W1TC    0x00000007U
+#define GPIO_STATUS2_W1TC_M  (GPIO_STATUS2_W1TC_V << GPIO_STATUS2_W1TC_S)
+#define GPIO_STATUS2_W1TC_V  0x00000007U
+#define GPIO_STATUS2_W1TC_S  0
+
+/** GPIO_INT_0_REG register
+ *  GPIO_INT_0 interrupt status register
+ */
+#define GPIO_INT_0_REG (DR_REG_GPIO_BASE + 0xa4)
+/** GPIO_INT_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_0 interrupt status of GPIO0 ~ GPIO31. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_0 interrupt is enabled.
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_0    0xFFFFFFFFU
+#define GPIO_INT_0_M  (GPIO_INT_0_V << GPIO_INT_0_S)
+#define GPIO_INT_0_V  0xFFFFFFFFU
+#define GPIO_INT_0_S  0
+
+/** GPIO_INT_1_REG register
+ *  GPIO_INT_1 interrupt status register
+ */
+#define GPIO_INT_1_REG (DR_REG_GPIO_BASE + 0xa8)
+/** GPIO_INT_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_1 interrupt status of GPIO0 ~ GPIO31. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_1 interrupt is enabled.
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_1    0xFFFFFFFFU
+#define GPIO_INT_1_M  (GPIO_INT_1_V << GPIO_INT_1_S)
+#define GPIO_INT_1_V  0xFFFFFFFFU
+#define GPIO_INT_1_S  0
+
+/** GPIO_INT_2_REG register
+ *  GPIO_INT_2 interrupt status register
+ */
+#define GPIO_INT_2_REG (DR_REG_GPIO_BASE + 0xac)
+/** GPIO_INT_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_2 interrupt status of GPIO0 ~ GPIO31. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_2 interrupt is enabled.
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_2    0xFFFFFFFFU
+#define GPIO_INT_2_M  (GPIO_INT_2_V << GPIO_INT_2_S)
+#define GPIO_INT_2_V  0xFFFFFFFFU
+#define GPIO_INT_2_S  0
+
+/** GPIO_INT_3_REG register
+ *  GPIO_INT_3 interrupt status register
+ */
+#define GPIO_INT_3_REG (DR_REG_GPIO_BASE + 0xb0)
+/** GPIO_INT_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_3 interrupt status of GPIO0 ~ GPIO31. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_3 interrupt is enabled.
+ *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_3    0xFFFFFFFFU
+#define GPIO_INT_3_M  (GPIO_INT_3_V << GPIO_INT_3_S)
+#define GPIO_INT_3_V  0xFFFFFFFFU
+#define GPIO_INT_3_S  0
+
+/** GPIO_INT_01_REG register
+ *  GPIO_INT_0 interrupt status register
+ */
+#define GPIO_INT_01_REG (DR_REG_GPIO_BASE + 0xb4)
+/** GPIO_INT_01 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_0 interrupt status of GPIO32 ~ GPIO63. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_0 interrupt is enabled.
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_01    0xFFFFFFFFU
+#define GPIO_INT_01_M  (GPIO_INT_01_V << GPIO_INT_01_S)
+#define GPIO_INT_01_V  0xFFFFFFFFU
+#define GPIO_INT_01_S  0
+
+/** GPIO_INT_11_REG register
+ *  GPIO_INT_1 interrupt status register
+ */
+#define GPIO_INT_11_REG (DR_REG_GPIO_BASE + 0xb8)
+/** GPIO_INT_11 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_1 interrupt status of GPIO32 ~ GPIO63. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_1 interrupt is enabled.
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_11    0xFFFFFFFFU
+#define GPIO_INT_11_M  (GPIO_INT_11_V << GPIO_INT_11_S)
+#define GPIO_INT_11_V  0xFFFFFFFFU
+#define GPIO_INT_11_S  0
+
+/** GPIO_INT_21_REG register
+ *  GPIO_INT_2 interrupt status register
+ */
+#define GPIO_INT_21_REG (DR_REG_GPIO_BASE + 0xbc)
+/** GPIO_INT_21 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_2 interrupt status of GPIO32 ~ GPIO63. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_2 interrupt is enabled.
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_21    0xFFFFFFFFU
+#define GPIO_INT_21_M  (GPIO_INT_21_V << GPIO_INT_21_S)
+#define GPIO_INT_21_V  0xFFFFFFFFU
+#define GPIO_INT_21_S  0
+
+/** GPIO_INT_31_REG register
+ *  GPIO_INT_3 interrupt status register
+ */
+#define GPIO_INT_31_REG (DR_REG_GPIO_BASE + 0xc0)
+/** GPIO_INT_31 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the GPIO_INT_3 interrupt status of GPIO32 ~ GPIO63. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_3 interrupt is enabled.
+ *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_31    0xFFFFFFFFU
+#define GPIO_INT_31_M  (GPIO_INT_31_V << GPIO_INT_31_S)
+#define GPIO_INT_31_V  0xFFFFFFFFU
+#define GPIO_INT_31_S  0
+
+/** GPIO_INT_02_REG register
+ *  GPIO_INT_0 interrupt status register
+ */
+#define GPIO_INT_02_REG (DR_REG_GPIO_BASE + 0xc4)
+/** GPIO_INT_02 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the GPIO_INT_0 interrupt status of GPIO64 ~ GPIO66. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_0 interrupt is enabled.
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_02    0x00000007U
+#define GPIO_INT_02_M  (GPIO_INT_02_V << GPIO_INT_02_S)
+#define GPIO_INT_02_V  0x00000007U
+#define GPIO_INT_02_S  0
+
+/** GPIO_INT_12_REG register
+ *  GPIO_INT_1 interrupt status register
+ */
+#define GPIO_INT_12_REG (DR_REG_GPIO_BASE + 0xc8)
+/** GPIO_INT_12 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the GPIO_INT_1 interrupt status of GPIO64 ~ GPIO66. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_1 interrupt is enabled.
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_12    0x00000007U
+#define GPIO_INT_12_M  (GPIO_INT_12_V << GPIO_INT_12_S)
+#define GPIO_INT_12_V  0x00000007U
+#define GPIO_INT_12_S  0
+
+/** GPIO_INT_22_REG register
+ *  GPIO_INT_2 interrupt status register
+ */
+#define GPIO_INT_22_REG (DR_REG_GPIO_BASE + 0xcc)
+/** GPIO_INT_22 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the GPIO_INT_2 interrupt status of GPIO64 ~ GPIO66. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_2 interrupt is enabled.
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_22    0x00000007U
+#define GPIO_INT_22_M  (GPIO_INT_22_V << GPIO_INT_22_S)
+#define GPIO_INT_22_V  0x00000007U
+#define GPIO_INT_22_S  0
+
+/** GPIO_INT_32_REG register
+ *  GPIO_INT_3 interrupt status register
+ */
+#define GPIO_INT_32_REG (DR_REG_GPIO_BASE + 0xd0)
+/** GPIO_INT_32 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the GPIO_INT_3 interrupt status of GPIO64 ~ GPIO66. Each bit
+ *  represents:(need update in different project)
+ *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+ *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+ *  after the GPIO_INT_3 interrupt is enabled.
+ *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+ *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+ *  enable signal (bit13 of GPIO_PIN$n_REG).
+ */
+#define GPIO_INT_32    0x00000007U
+#define GPIO_INT_32_M  (GPIO_INT_32_V << GPIO_INT_32_S)
+#define GPIO_INT_32_V  0x00000007U
+#define GPIO_INT_32_S  0
+
+/** GPIO_STATUS_NEXT_REG register
+ *  GPIO interrupt source register
+ */
+#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xe4)
+/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0;
+ *  Represents the interrupt source signal of GPIO0 ~ GPIO31.
+ *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. Each
+ *  bit represents:
+ *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+ *  sensitive interrupt and any edge interrupt.
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_M  (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S)
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+/** GPIO_STATUS_NEXT1_REG register
+ *  GPIO interrupt source register
+ */
+#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0xe8)
+/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the interrupt source signal of GPIO32 ~ GPIO63.
+ *  Bit0 ~ bit24 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. Each
+ *  bit represents:
+ *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+ *  sensitive interrupt and any edge interrupt.
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT1    0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S)
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0xFFFFFFFFU
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+/** GPIO_STATUS_NEXT2_REG register
+ *  GPIO interrupt source register
+ */
+#define GPIO_STATUS_NEXT2_REG (DR_REG_GPIO_BASE + 0xec)
+/** GPIO_STATUS_INTERRUPT_NEXT2 : RO; bitpos: [2:0]; default: 0;
+ *  Represents the interrupt source signal of GPIO64 ~ GPIO66.
+ *  Bit0 ~ bit24 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. Each
+ *  bit represents:
+ *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+ *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+ *  sensitive interrupt and any edge interrupt.
+ */
+#define GPIO_STATUS_INTERRUPT_NEXT2    0x00000007U
+#define GPIO_STATUS_INTERRUPT_NEXT2_M  (GPIO_STATUS_INTERRUPT_NEXT2_V << GPIO_STATUS_INTERRUPT_NEXT2_S)
+#define GPIO_STATUS_INTERRUPT_NEXT2_V  0x00000007U
+#define GPIO_STATUS_INTERRUPT_NEXT2_S  0
+
+/** GPIO_PIN0_REG register
+ *  GPIO0 configuration register
+ */
+#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xf4)
+/** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN0_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_M  (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S)
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+/** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN0_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S)
+#define GPIO_PIN0_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN0_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_M  (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S)
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN0_INT_TYPE    0x00000007U
+#define GPIO_PIN0_INT_TYPE_M  (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S)
+#define GPIO_PIN0_INT_TYPE_V  0x00000007U
+#define GPIO_PIN0_INT_TYPE_S  7
+/** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN0_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S)
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN0_INT_ENA    0x0000001FU
+#define GPIO_PIN0_INT_ENA_M  (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S)
+#define GPIO_PIN0_INT_ENA_V  0x0000001FU
+#define GPIO_PIN0_INT_ENA_S  13
+
+/** GPIO_PIN1_REG register
+ *  GPIO1 configuration register
+ */
+#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xf8)
+/** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN1_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_M  (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S)
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+/** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN1_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S)
+#define GPIO_PIN1_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN1_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_M  (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S)
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN1_INT_TYPE    0x00000007U
+#define GPIO_PIN1_INT_TYPE_M  (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S)
+#define GPIO_PIN1_INT_TYPE_V  0x00000007U
+#define GPIO_PIN1_INT_TYPE_S  7
+/** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN1_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S)
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN1_INT_ENA    0x0000001FU
+#define GPIO_PIN1_INT_ENA_M  (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S)
+#define GPIO_PIN1_INT_ENA_V  0x0000001FU
+#define GPIO_PIN1_INT_ENA_S  13
+
+/** GPIO_PIN2_REG register
+ *  GPIO2 configuration register
+ */
+#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xfc)
+/** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN2_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_M  (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S)
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+/** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN2_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S)
+#define GPIO_PIN2_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN2_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_M  (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S)
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN2_INT_TYPE    0x00000007U
+#define GPIO_PIN2_INT_TYPE_M  (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S)
+#define GPIO_PIN2_INT_TYPE_V  0x00000007U
+#define GPIO_PIN2_INT_TYPE_S  7
+/** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN2_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S)
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN2_INT_ENA    0x0000001FU
+#define GPIO_PIN2_INT_ENA_M  (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S)
+#define GPIO_PIN2_INT_ENA_V  0x0000001FU
+#define GPIO_PIN2_INT_ENA_S  13
+
+/** GPIO_PIN3_REG register
+ *  GPIO3 configuration register
+ */
+#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x100)
+/** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN3_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_M  (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S)
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+/** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN3_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S)
+#define GPIO_PIN3_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN3_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_M  (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S)
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN3_INT_TYPE    0x00000007U
+#define GPIO_PIN3_INT_TYPE_M  (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S)
+#define GPIO_PIN3_INT_TYPE_V  0x00000007U
+#define GPIO_PIN3_INT_TYPE_S  7
+/** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN3_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S)
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN3_INT_ENA    0x0000001FU
+#define GPIO_PIN3_INT_ENA_M  (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S)
+#define GPIO_PIN3_INT_ENA_V  0x0000001FU
+#define GPIO_PIN3_INT_ENA_S  13
+
+/** GPIO_PIN4_REG register
+ *  GPIO4 configuration register
+ */
+#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x104)
+/** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN4_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_M  (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S)
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+/** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN4_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S)
+#define GPIO_PIN4_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN4_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_M  (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S)
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN4_INT_TYPE    0x00000007U
+#define GPIO_PIN4_INT_TYPE_M  (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S)
+#define GPIO_PIN4_INT_TYPE_V  0x00000007U
+#define GPIO_PIN4_INT_TYPE_S  7
+/** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN4_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S)
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN4_INT_ENA    0x0000001FU
+#define GPIO_PIN4_INT_ENA_M  (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S)
+#define GPIO_PIN4_INT_ENA_V  0x0000001FU
+#define GPIO_PIN4_INT_ENA_S  13
+
+/** GPIO_PIN5_REG register
+ *  GPIO5 configuration register
+ */
+#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x108)
+/** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN5_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_M  (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S)
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+/** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN5_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S)
+#define GPIO_PIN5_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN5_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_M  (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S)
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN5_INT_TYPE    0x00000007U
+#define GPIO_PIN5_INT_TYPE_M  (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S)
+#define GPIO_PIN5_INT_TYPE_V  0x00000007U
+#define GPIO_PIN5_INT_TYPE_S  7
+/** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN5_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S)
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN5_INT_ENA    0x0000001FU
+#define GPIO_PIN5_INT_ENA_M  (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S)
+#define GPIO_PIN5_INT_ENA_V  0x0000001FU
+#define GPIO_PIN5_INT_ENA_S  13
+
+/** GPIO_PIN6_REG register
+ *  GPIO6 configuration register
+ */
+#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x10c)
+/** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN6_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_M  (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S)
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+/** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN6_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S)
+#define GPIO_PIN6_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN6_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_M  (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S)
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN6_INT_TYPE    0x00000007U
+#define GPIO_PIN6_INT_TYPE_M  (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S)
+#define GPIO_PIN6_INT_TYPE_V  0x00000007U
+#define GPIO_PIN6_INT_TYPE_S  7
+/** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN6_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S)
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN6_INT_ENA    0x0000001FU
+#define GPIO_PIN6_INT_ENA_M  (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S)
+#define GPIO_PIN6_INT_ENA_V  0x0000001FU
+#define GPIO_PIN6_INT_ENA_S  13
+
+/** GPIO_PIN7_REG register
+ *  GPIO7 configuration register
+ */
+#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x110)
+/** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN7_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_M  (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S)
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+/** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN7_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S)
+#define GPIO_PIN7_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN7_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_M  (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S)
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN7_INT_TYPE    0x00000007U
+#define GPIO_PIN7_INT_TYPE_M  (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S)
+#define GPIO_PIN7_INT_TYPE_V  0x00000007U
+#define GPIO_PIN7_INT_TYPE_S  7
+/** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN7_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S)
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN7_INT_ENA    0x0000001FU
+#define GPIO_PIN7_INT_ENA_M  (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S)
+#define GPIO_PIN7_INT_ENA_V  0x0000001FU
+#define GPIO_PIN7_INT_ENA_S  13
+
+/** GPIO_PIN8_REG register
+ *  GPIO8 configuration register
+ */
+#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x114)
+/** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN8_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_M  (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S)
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+/** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN8_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S)
+#define GPIO_PIN8_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN8_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_M  (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S)
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN8_INT_TYPE    0x00000007U
+#define GPIO_PIN8_INT_TYPE_M  (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S)
+#define GPIO_PIN8_INT_TYPE_V  0x00000007U
+#define GPIO_PIN8_INT_TYPE_S  7
+/** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN8_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S)
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN8_INT_ENA    0x0000001FU
+#define GPIO_PIN8_INT_ENA_M  (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S)
+#define GPIO_PIN8_INT_ENA_V  0x0000001FU
+#define GPIO_PIN8_INT_ENA_S  13
+
+/** GPIO_PIN9_REG register
+ *  GPIO9 configuration register
+ */
+#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x118)
+/** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN9_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_M  (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S)
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+/** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN9_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S)
+#define GPIO_PIN9_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN9_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_M  (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S)
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN9_INT_TYPE    0x00000007U
+#define GPIO_PIN9_INT_TYPE_M  (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S)
+#define GPIO_PIN9_INT_TYPE_V  0x00000007U
+#define GPIO_PIN9_INT_TYPE_S  7
+/** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN9_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S)
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN9_INT_ENA    0x0000001FU
+#define GPIO_PIN9_INT_ENA_M  (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S)
+#define GPIO_PIN9_INT_ENA_V  0x0000001FU
+#define GPIO_PIN9_INT_ENA_S  13
+
+/** GPIO_PIN10_REG register
+ *  GPIO10 configuration register
+ */
+#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x11c)
+/** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN10_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_M  (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S)
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+/** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN10_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S)
+#define GPIO_PIN10_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN10_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_M  (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S)
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN10_INT_TYPE    0x00000007U
+#define GPIO_PIN10_INT_TYPE_M  (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S)
+#define GPIO_PIN10_INT_TYPE_V  0x00000007U
+#define GPIO_PIN10_INT_TYPE_S  7
+/** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN10_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S)
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN10_INT_ENA    0x0000001FU
+#define GPIO_PIN10_INT_ENA_M  (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S)
+#define GPIO_PIN10_INT_ENA_V  0x0000001FU
+#define GPIO_PIN10_INT_ENA_S  13
+
+/** GPIO_PIN11_REG register
+ *  GPIO11 configuration register
+ */
+#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x120)
+/** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN11_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_M  (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S)
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+/** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN11_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S)
+#define GPIO_PIN11_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN11_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_M  (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S)
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN11_INT_TYPE    0x00000007U
+#define GPIO_PIN11_INT_TYPE_M  (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S)
+#define GPIO_PIN11_INT_TYPE_V  0x00000007U
+#define GPIO_PIN11_INT_TYPE_S  7
+/** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN11_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S)
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN11_INT_ENA    0x0000001FU
+#define GPIO_PIN11_INT_ENA_M  (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S)
+#define GPIO_PIN11_INT_ENA_V  0x0000001FU
+#define GPIO_PIN11_INT_ENA_S  13
+
+/** GPIO_PIN12_REG register
+ *  GPIO12 configuration register
+ */
+#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x124)
+/** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN12_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_M  (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S)
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+/** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN12_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S)
+#define GPIO_PIN12_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN12_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_M  (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S)
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN12_INT_TYPE    0x00000007U
+#define GPIO_PIN12_INT_TYPE_M  (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S)
+#define GPIO_PIN12_INT_TYPE_V  0x00000007U
+#define GPIO_PIN12_INT_TYPE_S  7
+/** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN12_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S)
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN12_INT_ENA    0x0000001FU
+#define GPIO_PIN12_INT_ENA_M  (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S)
+#define GPIO_PIN12_INT_ENA_V  0x0000001FU
+#define GPIO_PIN12_INT_ENA_S  13
+
+/** GPIO_PIN13_REG register
+ *  GPIO13 configuration register
+ */
+#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x128)
+/** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN13_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_M  (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S)
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+/** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN13_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S)
+#define GPIO_PIN13_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN13_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_M  (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S)
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN13_INT_TYPE    0x00000007U
+#define GPIO_PIN13_INT_TYPE_M  (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S)
+#define GPIO_PIN13_INT_TYPE_V  0x00000007U
+#define GPIO_PIN13_INT_TYPE_S  7
+/** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN13_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S)
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN13_INT_ENA    0x0000001FU
+#define GPIO_PIN13_INT_ENA_M  (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S)
+#define GPIO_PIN13_INT_ENA_V  0x0000001FU
+#define GPIO_PIN13_INT_ENA_S  13
+
+/** GPIO_PIN14_REG register
+ *  GPIO14 configuration register
+ */
+#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x12c)
+/** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN14_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_M  (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S)
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+/** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN14_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S)
+#define GPIO_PIN14_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN14_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_M  (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S)
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN14_INT_TYPE    0x00000007U
+#define GPIO_PIN14_INT_TYPE_M  (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S)
+#define GPIO_PIN14_INT_TYPE_V  0x00000007U
+#define GPIO_PIN14_INT_TYPE_S  7
+/** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN14_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S)
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN14_INT_ENA    0x0000001FU
+#define GPIO_PIN14_INT_ENA_M  (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S)
+#define GPIO_PIN14_INT_ENA_V  0x0000001FU
+#define GPIO_PIN14_INT_ENA_S  13
+
+/** GPIO_PIN15_REG register
+ *  GPIO15 configuration register
+ */
+#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x130)
+/** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN15_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_M  (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S)
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+/** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN15_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S)
+#define GPIO_PIN15_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN15_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_M  (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S)
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN15_INT_TYPE    0x00000007U
+#define GPIO_PIN15_INT_TYPE_M  (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S)
+#define GPIO_PIN15_INT_TYPE_V  0x00000007U
+#define GPIO_PIN15_INT_TYPE_S  7
+/** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN15_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S)
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN15_INT_ENA    0x0000001FU
+#define GPIO_PIN15_INT_ENA_M  (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S)
+#define GPIO_PIN15_INT_ENA_V  0x0000001FU
+#define GPIO_PIN15_INT_ENA_S  13
+
+/** GPIO_PIN16_REG register
+ *  GPIO16 configuration register
+ */
+#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x134)
+/** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN16_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_M  (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S)
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+/** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN16_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S)
+#define GPIO_PIN16_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN16_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_M  (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S)
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN16_INT_TYPE    0x00000007U
+#define GPIO_PIN16_INT_TYPE_M  (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S)
+#define GPIO_PIN16_INT_TYPE_V  0x00000007U
+#define GPIO_PIN16_INT_TYPE_S  7
+/** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN16_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S)
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN16_INT_ENA    0x0000001FU
+#define GPIO_PIN16_INT_ENA_M  (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S)
+#define GPIO_PIN16_INT_ENA_V  0x0000001FU
+#define GPIO_PIN16_INT_ENA_S  13
+
+/** GPIO_PIN17_REG register
+ *  GPIO17 configuration register
+ */
+#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x138)
+/** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN17_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_M  (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S)
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+/** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN17_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S)
+#define GPIO_PIN17_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN17_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_M  (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S)
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN17_INT_TYPE    0x00000007U
+#define GPIO_PIN17_INT_TYPE_M  (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S)
+#define GPIO_PIN17_INT_TYPE_V  0x00000007U
+#define GPIO_PIN17_INT_TYPE_S  7
+/** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN17_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S)
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN17_INT_ENA    0x0000001FU
+#define GPIO_PIN17_INT_ENA_M  (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S)
+#define GPIO_PIN17_INT_ENA_V  0x0000001FU
+#define GPIO_PIN17_INT_ENA_S  13
+
+/** GPIO_PIN18_REG register
+ *  GPIO18 configuration register
+ */
+#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x13c)
+/** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN18_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_M  (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S)
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+/** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN18_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S)
+#define GPIO_PIN18_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN18_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_M  (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S)
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN18_INT_TYPE    0x00000007U
+#define GPIO_PIN18_INT_TYPE_M  (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S)
+#define GPIO_PIN18_INT_TYPE_V  0x00000007U
+#define GPIO_PIN18_INT_TYPE_S  7
+/** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN18_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S)
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN18_INT_ENA    0x0000001FU
+#define GPIO_PIN18_INT_ENA_M  (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S)
+#define GPIO_PIN18_INT_ENA_V  0x0000001FU
+#define GPIO_PIN18_INT_ENA_S  13
+
+/** GPIO_PIN19_REG register
+ *  GPIO19 configuration register
+ */
+#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x140)
+/** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN19_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_M  (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S)
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+/** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN19_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S)
+#define GPIO_PIN19_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN19_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_M  (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S)
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN19_INT_TYPE    0x00000007U
+#define GPIO_PIN19_INT_TYPE_M  (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S)
+#define GPIO_PIN19_INT_TYPE_V  0x00000007U
+#define GPIO_PIN19_INT_TYPE_S  7
+/** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN19_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S)
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN19_INT_ENA    0x0000001FU
+#define GPIO_PIN19_INT_ENA_M  (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S)
+#define GPIO_PIN19_INT_ENA_V  0x0000001FU
+#define GPIO_PIN19_INT_ENA_S  13
+
+/** GPIO_PIN20_REG register
+ *  GPIO20 configuration register
+ */
+#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x144)
+/** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN20_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_M  (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S)
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+/** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN20_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S)
+#define GPIO_PIN20_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN20_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_M  (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S)
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN20_INT_TYPE    0x00000007U
+#define GPIO_PIN20_INT_TYPE_M  (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S)
+#define GPIO_PIN20_INT_TYPE_V  0x00000007U
+#define GPIO_PIN20_INT_TYPE_S  7
+/** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN20_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S)
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN20_INT_ENA    0x0000001FU
+#define GPIO_PIN20_INT_ENA_M  (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S)
+#define GPIO_PIN20_INT_ENA_V  0x0000001FU
+#define GPIO_PIN20_INT_ENA_S  13
+
+/** GPIO_PIN21_REG register
+ *  GPIO21 configuration register
+ */
+#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x148)
+/** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN21_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_M  (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S)
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+/** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN21_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S)
+#define GPIO_PIN21_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN21_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_M  (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S)
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN21_INT_TYPE    0x00000007U
+#define GPIO_PIN21_INT_TYPE_M  (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S)
+#define GPIO_PIN21_INT_TYPE_V  0x00000007U
+#define GPIO_PIN21_INT_TYPE_S  7
+/** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN21_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S)
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN21_INT_ENA    0x0000001FU
+#define GPIO_PIN21_INT_ENA_M  (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S)
+#define GPIO_PIN21_INT_ENA_V  0x0000001FU
+#define GPIO_PIN21_INT_ENA_S  13
+
+/** GPIO_PIN22_REG register
+ *  GPIO22 configuration register
+ */
+#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x14c)
+/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN22_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_M  (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN22_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
+#define GPIO_PIN22_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN22_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_M  (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN22_INT_TYPE    0x00000007U
+#define GPIO_PIN22_INT_TYPE_M  (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
+#define GPIO_PIN22_INT_TYPE_V  0x00000007U
+#define GPIO_PIN22_INT_TYPE_S  7
+/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN22_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN22_INT_ENA    0x0000001FU
+#define GPIO_PIN22_INT_ENA_M  (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
+#define GPIO_PIN22_INT_ENA_V  0x0000001FU
+#define GPIO_PIN22_INT_ENA_S  13
+
+/** GPIO_PIN23_REG register
+ *  GPIO23 configuration register
+ */
+#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x150)
+/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN23_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_M  (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN23_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
+#define GPIO_PIN23_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN23_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_M  (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN23_INT_TYPE    0x00000007U
+#define GPIO_PIN23_INT_TYPE_M  (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
+#define GPIO_PIN23_INT_TYPE_V  0x00000007U
+#define GPIO_PIN23_INT_TYPE_S  7
+/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN23_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN23_INT_ENA    0x0000001FU
+#define GPIO_PIN23_INT_ENA_M  (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
+#define GPIO_PIN23_INT_ENA_V  0x0000001FU
+#define GPIO_PIN23_INT_ENA_S  13
+
+/** GPIO_PIN24_REG register
+ *  GPIO24 configuration register
+ */
+#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x154)
+/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN24_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_M  (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN24_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
+#define GPIO_PIN24_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN24_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_M  (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN24_INT_TYPE    0x00000007U
+#define GPIO_PIN24_INT_TYPE_M  (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
+#define GPIO_PIN24_INT_TYPE_V  0x00000007U
+#define GPIO_PIN24_INT_TYPE_S  7
+/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN24_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN24_INT_ENA    0x0000001FU
+#define GPIO_PIN24_INT_ENA_M  (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
+#define GPIO_PIN24_INT_ENA_V  0x0000001FU
+#define GPIO_PIN24_INT_ENA_S  13
+
+/** GPIO_PIN25_REG register
+ *  GPIO25 configuration register
+ */
+#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x158)
+/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN25_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_M  (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN25_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
+#define GPIO_PIN25_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN25_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_M  (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN25_INT_TYPE    0x00000007U
+#define GPIO_PIN25_INT_TYPE_M  (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
+#define GPIO_PIN25_INT_TYPE_V  0x00000007U
+#define GPIO_PIN25_INT_TYPE_S  7
+/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN25_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN25_INT_ENA    0x0000001FU
+#define GPIO_PIN25_INT_ENA_M  (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
+#define GPIO_PIN25_INT_ENA_V  0x0000001FU
+#define GPIO_PIN25_INT_ENA_S  13
+
+/** GPIO_PIN26_REG register
+ *  GPIO26 configuration register
+ */
+#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x15c)
+/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN26_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_M  (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN26_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
+#define GPIO_PIN26_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN26_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_M  (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN26_INT_TYPE    0x00000007U
+#define GPIO_PIN26_INT_TYPE_M  (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
+#define GPIO_PIN26_INT_TYPE_V  0x00000007U
+#define GPIO_PIN26_INT_TYPE_S  7
+/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN26_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN26_INT_ENA    0x0000001FU
+#define GPIO_PIN26_INT_ENA_M  (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
+#define GPIO_PIN26_INT_ENA_V  0x0000001FU
+#define GPIO_PIN26_INT_ENA_S  13
+
+/** GPIO_PIN27_REG register
+ *  GPIO27 configuration register
+ */
+#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x160)
+/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN27_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_M  (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN27_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
+#define GPIO_PIN27_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN27_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_M  (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN27_INT_TYPE    0x00000007U
+#define GPIO_PIN27_INT_TYPE_M  (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
+#define GPIO_PIN27_INT_TYPE_V  0x00000007U
+#define GPIO_PIN27_INT_TYPE_S  7
+/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN27_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN27_INT_ENA    0x0000001FU
+#define GPIO_PIN27_INT_ENA_M  (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
+#define GPIO_PIN27_INT_ENA_V  0x0000001FU
+#define GPIO_PIN27_INT_ENA_S  13
+
+/** GPIO_PIN28_REG register
+ *  GPIO28 configuration register
+ */
+#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x164)
+/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN28_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_M  (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN28_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
+#define GPIO_PIN28_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN28_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_M  (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN28_INT_TYPE    0x00000007U
+#define GPIO_PIN28_INT_TYPE_M  (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
+#define GPIO_PIN28_INT_TYPE_V  0x00000007U
+#define GPIO_PIN28_INT_TYPE_S  7
+/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN28_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN28_INT_ENA    0x0000001FU
+#define GPIO_PIN28_INT_ENA_M  (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
+#define GPIO_PIN28_INT_ENA_V  0x0000001FU
+#define GPIO_PIN28_INT_ENA_S  13
+
+/** GPIO_PIN29_REG register
+ *  GPIO29 configuration register
+ */
+#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x168)
+/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN29_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_M  (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S)
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN29_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S)
+#define GPIO_PIN29_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN29_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_M  (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S)
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN29_INT_TYPE    0x00000007U
+#define GPIO_PIN29_INT_TYPE_M  (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S)
+#define GPIO_PIN29_INT_TYPE_V  0x00000007U
+#define GPIO_PIN29_INT_TYPE_S  7
+/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN29_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S)
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN29_INT_ENA    0x0000001FU
+#define GPIO_PIN29_INT_ENA_M  (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S)
+#define GPIO_PIN29_INT_ENA_V  0x0000001FU
+#define GPIO_PIN29_INT_ENA_S  13
+
+/** GPIO_PIN30_REG register
+ *  GPIO30 configuration register
+ */
+#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x16c)
+/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN30_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_M  (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S)
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN30_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S)
+#define GPIO_PIN30_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN30_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_M  (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S)
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN30_INT_TYPE    0x00000007U
+#define GPIO_PIN30_INT_TYPE_M  (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S)
+#define GPIO_PIN30_INT_TYPE_V  0x00000007U
+#define GPIO_PIN30_INT_TYPE_S  7
+/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN30_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S)
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN30_INT_ENA    0x0000001FU
+#define GPIO_PIN30_INT_ENA_M  (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S)
+#define GPIO_PIN30_INT_ENA_V  0x0000001FU
+#define GPIO_PIN30_INT_ENA_S  13
+
+/** GPIO_PIN31_REG register
+ *  GPIO31 configuration register
+ */
+#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x170)
+/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN31_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_M  (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S)
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN31_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S)
+#define GPIO_PIN31_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN31_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_M  (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S)
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN31_INT_TYPE    0x00000007U
+#define GPIO_PIN31_INT_TYPE_M  (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S)
+#define GPIO_PIN31_INT_TYPE_V  0x00000007U
+#define GPIO_PIN31_INT_TYPE_S  7
+/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN31_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S)
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN31_INT_ENA    0x0000001FU
+#define GPIO_PIN31_INT_ENA_M  (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S)
+#define GPIO_PIN31_INT_ENA_V  0x0000001FU
+#define GPIO_PIN31_INT_ENA_S  13
+
+/** GPIO_PIN32_REG register
+ *  GPIO32 configuration register
+ */
+#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x174)
+/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN32_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_M  (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S)
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN32_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S)
+#define GPIO_PIN32_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN32_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_M  (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S)
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN32_INT_TYPE    0x00000007U
+#define GPIO_PIN32_INT_TYPE_M  (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S)
+#define GPIO_PIN32_INT_TYPE_V  0x00000007U
+#define GPIO_PIN32_INT_TYPE_S  7
+/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN32_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S)
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN32_INT_ENA    0x0000001FU
+#define GPIO_PIN32_INT_ENA_M  (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S)
+#define GPIO_PIN32_INT_ENA_V  0x0000001FU
+#define GPIO_PIN32_INT_ENA_S  13
+
+/** GPIO_PIN33_REG register
+ *  GPIO33 configuration register
+ */
+#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x178)
+/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN33_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_M  (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S)
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN33_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S)
+#define GPIO_PIN33_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN33_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_M  (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S)
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN33_INT_TYPE    0x00000007U
+#define GPIO_PIN33_INT_TYPE_M  (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S)
+#define GPIO_PIN33_INT_TYPE_V  0x00000007U
+#define GPIO_PIN33_INT_TYPE_S  7
+/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN33_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S)
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN33_INT_ENA    0x0000001FU
+#define GPIO_PIN33_INT_ENA_M  (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S)
+#define GPIO_PIN33_INT_ENA_V  0x0000001FU
+#define GPIO_PIN33_INT_ENA_S  13
+
+/** GPIO_PIN34_REG register
+ *  GPIO34 configuration register
+ */
+#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0x17c)
+/** GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN34_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_M  (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S)
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+/** GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN34_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S)
+#define GPIO_PIN34_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/** GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN34_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_M  (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S)
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/** GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN34_INT_TYPE    0x00000007U
+#define GPIO_PIN34_INT_TYPE_M  (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S)
+#define GPIO_PIN34_INT_TYPE_V  0x00000007U
+#define GPIO_PIN34_INT_TYPE_S  7
+/** GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN34_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S)
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/** GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN34_INT_ENA    0x0000001FU
+#define GPIO_PIN34_INT_ENA_M  (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S)
+#define GPIO_PIN34_INT_ENA_V  0x0000001FU
+#define GPIO_PIN34_INT_ENA_S  13
+
+/** GPIO_PIN35_REG register
+ *  GPIO35 configuration register
+ */
+#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x180)
+/** GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN35_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_M  (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S)
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+/** GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN35_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S)
+#define GPIO_PIN35_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/** GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN35_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_M  (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S)
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/** GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN35_INT_TYPE    0x00000007U
+#define GPIO_PIN35_INT_TYPE_M  (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S)
+#define GPIO_PIN35_INT_TYPE_V  0x00000007U
+#define GPIO_PIN35_INT_TYPE_S  7
+/** GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN35_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S)
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/** GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN35_INT_ENA    0x0000001FU
+#define GPIO_PIN35_INT_ENA_M  (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S)
+#define GPIO_PIN35_INT_ENA_V  0x0000001FU
+#define GPIO_PIN35_INT_ENA_S  13
+
+/** GPIO_PIN36_REG register
+ *  GPIO36 configuration register
+ */
+#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x184)
+/** GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN36_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_M  (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S)
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+/** GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN36_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S)
+#define GPIO_PIN36_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/** GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN36_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_M  (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S)
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/** GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN36_INT_TYPE    0x00000007U
+#define GPIO_PIN36_INT_TYPE_M  (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S)
+#define GPIO_PIN36_INT_TYPE_V  0x00000007U
+#define GPIO_PIN36_INT_TYPE_S  7
+/** GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN36_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S)
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/** GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN36_INT_ENA    0x0000001FU
+#define GPIO_PIN36_INT_ENA_M  (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S)
+#define GPIO_PIN36_INT_ENA_V  0x0000001FU
+#define GPIO_PIN36_INT_ENA_S  13
+
+/** GPIO_PIN37_REG register
+ *  GPIO37 configuration register
+ */
+#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x188)
+/** GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN37_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_M  (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S)
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+/** GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN37_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S)
+#define GPIO_PIN37_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/** GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN37_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_M  (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S)
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/** GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN37_INT_TYPE    0x00000007U
+#define GPIO_PIN37_INT_TYPE_M  (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S)
+#define GPIO_PIN37_INT_TYPE_V  0x00000007U
+#define GPIO_PIN37_INT_TYPE_S  7
+/** GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN37_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S)
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/** GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN37_INT_ENA    0x0000001FU
+#define GPIO_PIN37_INT_ENA_M  (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S)
+#define GPIO_PIN37_INT_ENA_V  0x0000001FU
+#define GPIO_PIN37_INT_ENA_S  13
+
+/** GPIO_PIN38_REG register
+ *  GPIO38 configuration register
+ */
+#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x18c)
+/** GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN38_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_M  (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S)
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+/** GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN38_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S)
+#define GPIO_PIN38_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/** GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN38_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_M  (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S)
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/** GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN38_INT_TYPE    0x00000007U
+#define GPIO_PIN38_INT_TYPE_M  (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S)
+#define GPIO_PIN38_INT_TYPE_V  0x00000007U
+#define GPIO_PIN38_INT_TYPE_S  7
+/** GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN38_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S)
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/** GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN38_INT_ENA    0x0000001FU
+#define GPIO_PIN38_INT_ENA_M  (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S)
+#define GPIO_PIN38_INT_ENA_V  0x0000001FU
+#define GPIO_PIN38_INT_ENA_S  13
+
+/** GPIO_PIN39_REG register
+ *  GPIO39 configuration register
+ */
+#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x190)
+/** GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN39_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_M  (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S)
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+/** GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN39_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S)
+#define GPIO_PIN39_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/** GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN39_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_M  (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S)
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/** GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN39_INT_TYPE    0x00000007U
+#define GPIO_PIN39_INT_TYPE_M  (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S)
+#define GPIO_PIN39_INT_TYPE_V  0x00000007U
+#define GPIO_PIN39_INT_TYPE_S  7
+/** GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN39_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S)
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/** GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN39_INT_ENA    0x0000001FU
+#define GPIO_PIN39_INT_ENA_M  (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S)
+#define GPIO_PIN39_INT_ENA_V  0x0000001FU
+#define GPIO_PIN39_INT_ENA_S  13
+
+/** GPIO_PIN40_REG register
+ *  GPIO40 configuration register
+ */
+#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x194)
+/** GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN40_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_M  (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S)
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+/** GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN40_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S)
+#define GPIO_PIN40_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/** GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN40_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_M  (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S)
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/** GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN40_INT_TYPE    0x00000007U
+#define GPIO_PIN40_INT_TYPE_M  (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S)
+#define GPIO_PIN40_INT_TYPE_V  0x00000007U
+#define GPIO_PIN40_INT_TYPE_S  7
+/** GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN40_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S)
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/** GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN40_INT_ENA    0x0000001FU
+#define GPIO_PIN40_INT_ENA_M  (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S)
+#define GPIO_PIN40_INT_ENA_V  0x0000001FU
+#define GPIO_PIN40_INT_ENA_S  13
+
+/** GPIO_PIN41_REG register
+ *  GPIO41 configuration register
+ */
+#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x198)
+/** GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN41_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_M  (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S)
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+/** GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN41_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S)
+#define GPIO_PIN41_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/** GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN41_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_M  (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S)
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/** GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN41_INT_TYPE    0x00000007U
+#define GPIO_PIN41_INT_TYPE_M  (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S)
+#define GPIO_PIN41_INT_TYPE_V  0x00000007U
+#define GPIO_PIN41_INT_TYPE_S  7
+/** GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN41_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S)
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/** GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN41_INT_ENA    0x0000001FU
+#define GPIO_PIN41_INT_ENA_M  (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S)
+#define GPIO_PIN41_INT_ENA_V  0x0000001FU
+#define GPIO_PIN41_INT_ENA_S  13
+
+/** GPIO_PIN42_REG register
+ *  GPIO42 configuration register
+ */
+#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x19c)
+/** GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN42_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_M  (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S)
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+/** GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN42_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S)
+#define GPIO_PIN42_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/** GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN42_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_M  (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S)
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/** GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN42_INT_TYPE    0x00000007U
+#define GPIO_PIN42_INT_TYPE_M  (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S)
+#define GPIO_PIN42_INT_TYPE_V  0x00000007U
+#define GPIO_PIN42_INT_TYPE_S  7
+/** GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN42_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S)
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/** GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN42_INT_ENA    0x0000001FU
+#define GPIO_PIN42_INT_ENA_M  (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S)
+#define GPIO_PIN42_INT_ENA_V  0x0000001FU
+#define GPIO_PIN42_INT_ENA_S  13
+
+/** GPIO_PIN43_REG register
+ *  GPIO43 configuration register
+ */
+#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x1a0)
+/** GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN43_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_M  (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S)
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+/** GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN43_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S)
+#define GPIO_PIN43_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/** GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN43_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_M  (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S)
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/** GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN43_INT_TYPE    0x00000007U
+#define GPIO_PIN43_INT_TYPE_M  (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S)
+#define GPIO_PIN43_INT_TYPE_V  0x00000007U
+#define GPIO_PIN43_INT_TYPE_S  7
+/** GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN43_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S)
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/** GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN43_INT_ENA    0x0000001FU
+#define GPIO_PIN43_INT_ENA_M  (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S)
+#define GPIO_PIN43_INT_ENA_V  0x0000001FU
+#define GPIO_PIN43_INT_ENA_S  13
+
+/** GPIO_PIN44_REG register
+ *  GPIO44 configuration register
+ */
+#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x1a4)
+/** GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN44_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_M  (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S)
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+/** GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN44_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S)
+#define GPIO_PIN44_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/** GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN44_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_M  (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S)
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/** GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN44_INT_TYPE    0x00000007U
+#define GPIO_PIN44_INT_TYPE_M  (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S)
+#define GPIO_PIN44_INT_TYPE_V  0x00000007U
+#define GPIO_PIN44_INT_TYPE_S  7
+/** GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN44_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S)
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/** GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN44_INT_ENA    0x0000001FU
+#define GPIO_PIN44_INT_ENA_M  (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S)
+#define GPIO_PIN44_INT_ENA_V  0x0000001FU
+#define GPIO_PIN44_INT_ENA_S  13
+
+/** GPIO_PIN45_REG register
+ *  GPIO45 configuration register
+ */
+#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x1a8)
+/** GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN45_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_M  (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S)
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+/** GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN45_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S)
+#define GPIO_PIN45_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/** GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN45_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_M  (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S)
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/** GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN45_INT_TYPE    0x00000007U
+#define GPIO_PIN45_INT_TYPE_M  (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S)
+#define GPIO_PIN45_INT_TYPE_V  0x00000007U
+#define GPIO_PIN45_INT_TYPE_S  7
+/** GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN45_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S)
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/** GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN45_INT_ENA    0x0000001FU
+#define GPIO_PIN45_INT_ENA_M  (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S)
+#define GPIO_PIN45_INT_ENA_V  0x0000001FU
+#define GPIO_PIN45_INT_ENA_S  13
+
+/** GPIO_PIN46_REG register
+ *  GPIO46 configuration register
+ */
+#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x1ac)
+/** GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN46_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_M  (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S)
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+/** GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN46_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S)
+#define GPIO_PIN46_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/** GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN46_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_M  (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S)
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/** GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN46_INT_TYPE    0x00000007U
+#define GPIO_PIN46_INT_TYPE_M  (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S)
+#define GPIO_PIN46_INT_TYPE_V  0x00000007U
+#define GPIO_PIN46_INT_TYPE_S  7
+/** GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN46_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S)
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/** GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN46_INT_ENA    0x0000001FU
+#define GPIO_PIN46_INT_ENA_M  (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S)
+#define GPIO_PIN46_INT_ENA_V  0x0000001FU
+#define GPIO_PIN46_INT_ENA_S  13
+
+/** GPIO_PIN47_REG register
+ *  GPIO47 configuration register
+ */
+#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x1b0)
+/** GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN47_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_M  (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S)
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+/** GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN47_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S)
+#define GPIO_PIN47_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/** GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN47_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_M  (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S)
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/** GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN47_INT_TYPE    0x00000007U
+#define GPIO_PIN47_INT_TYPE_M  (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S)
+#define GPIO_PIN47_INT_TYPE_V  0x00000007U
+#define GPIO_PIN47_INT_TYPE_S  7
+/** GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN47_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S)
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/** GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN47_INT_ENA    0x0000001FU
+#define GPIO_PIN47_INT_ENA_M  (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S)
+#define GPIO_PIN47_INT_ENA_V  0x0000001FU
+#define GPIO_PIN47_INT_ENA_S  13
+
+/** GPIO_PIN48_REG register
+ *  GPIO48 configuration register
+ */
+#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x1b4)
+/** GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN48_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_M  (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S)
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+/** GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN48_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S)
+#define GPIO_PIN48_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/** GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN48_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_M  (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S)
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/** GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN48_INT_TYPE    0x00000007U
+#define GPIO_PIN48_INT_TYPE_M  (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S)
+#define GPIO_PIN48_INT_TYPE_V  0x00000007U
+#define GPIO_PIN48_INT_TYPE_S  7
+/** GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN48_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S)
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/** GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN48_INT_ENA    0x0000001FU
+#define GPIO_PIN48_INT_ENA_M  (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S)
+#define GPIO_PIN48_INT_ENA_V  0x0000001FU
+#define GPIO_PIN48_INT_ENA_S  13
+
+/** GPIO_PIN49_REG register
+ *  GPIO49 configuration register
+ */
+#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x1b8)
+/** GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN49_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_M  (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S)
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+/** GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN49_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S)
+#define GPIO_PIN49_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/** GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN49_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_M  (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S)
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/** GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN49_INT_TYPE    0x00000007U
+#define GPIO_PIN49_INT_TYPE_M  (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S)
+#define GPIO_PIN49_INT_TYPE_V  0x00000007U
+#define GPIO_PIN49_INT_TYPE_S  7
+/** GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN49_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S)
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/** GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN49_INT_ENA    0x0000001FU
+#define GPIO_PIN49_INT_ENA_M  (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S)
+#define GPIO_PIN49_INT_ENA_V  0x0000001FU
+#define GPIO_PIN49_INT_ENA_S  13
+
+/** GPIO_PIN50_REG register
+ *  GPIO50 configuration register
+ */
+#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x1bc)
+/** GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN50_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_M  (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S)
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+/** GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN50_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S)
+#define GPIO_PIN50_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/** GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN50_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_M  (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S)
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/** GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN50_INT_TYPE    0x00000007U
+#define GPIO_PIN50_INT_TYPE_M  (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S)
+#define GPIO_PIN50_INT_TYPE_V  0x00000007U
+#define GPIO_PIN50_INT_TYPE_S  7
+/** GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN50_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S)
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/** GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN50_INT_ENA    0x0000001FU
+#define GPIO_PIN50_INT_ENA_M  (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S)
+#define GPIO_PIN50_INT_ENA_V  0x0000001FU
+#define GPIO_PIN50_INT_ENA_S  13
+
+/** GPIO_PIN51_REG register
+ *  GPIO51 configuration register
+ */
+#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x1c0)
+/** GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN51_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_M  (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S)
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+/** GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN51_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S)
+#define GPIO_PIN51_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/** GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN51_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_M  (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S)
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/** GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN51_INT_TYPE    0x00000007U
+#define GPIO_PIN51_INT_TYPE_M  (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S)
+#define GPIO_PIN51_INT_TYPE_V  0x00000007U
+#define GPIO_PIN51_INT_TYPE_S  7
+/** GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN51_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S)
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/** GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN51_INT_ENA    0x0000001FU
+#define GPIO_PIN51_INT_ENA_M  (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S)
+#define GPIO_PIN51_INT_ENA_V  0x0000001FU
+#define GPIO_PIN51_INT_ENA_S  13
+
+/** GPIO_PIN52_REG register
+ *  GPIO52 configuration register
+ */
+#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x1c4)
+/** GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN52_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_M  (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S)
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+/** GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN52_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S)
+#define GPIO_PIN52_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/** GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN52_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_M  (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S)
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/** GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN52_INT_TYPE    0x00000007U
+#define GPIO_PIN52_INT_TYPE_M  (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S)
+#define GPIO_PIN52_INT_TYPE_V  0x00000007U
+#define GPIO_PIN52_INT_TYPE_S  7
+/** GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN52_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S)
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/** GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN52_INT_ENA    0x0000001FU
+#define GPIO_PIN52_INT_ENA_M  (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S)
+#define GPIO_PIN52_INT_ENA_V  0x0000001FU
+#define GPIO_PIN52_INT_ENA_S  13
+
+/** GPIO_PIN53_REG register
+ *  GPIO53 configuration register
+ */
+#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x1c8)
+/** GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN53_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_M  (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S)
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+/** GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN53_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S)
+#define GPIO_PIN53_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/** GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN53_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_M  (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S)
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/** GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN53_INT_TYPE    0x00000007U
+#define GPIO_PIN53_INT_TYPE_M  (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S)
+#define GPIO_PIN53_INT_TYPE_V  0x00000007U
+#define GPIO_PIN53_INT_TYPE_S  7
+/** GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN53_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S)
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/** GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN53_INT_ENA    0x0000001FU
+#define GPIO_PIN53_INT_ENA_M  (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S)
+#define GPIO_PIN53_INT_ENA_V  0x0000001FU
+#define GPIO_PIN53_INT_ENA_S  13
+
+/** GPIO_PIN54_REG register
+ *  GPIO54 configuration register
+ */
+#define GPIO_PIN54_REG (DR_REG_GPIO_BASE + 0x1cc)
+/** GPIO_PIN54_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN54_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_M  (GPIO_PIN54_SYNC2_BYPASS_V << GPIO_PIN54_SYNC2_BYPASS_S)
+#define GPIO_PIN54_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC2_BYPASS_S  0
+/** GPIO_PIN54_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN54_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN54_PAD_DRIVER_M  (GPIO_PIN54_PAD_DRIVER_V << GPIO_PIN54_PAD_DRIVER_S)
+#define GPIO_PIN54_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN54_PAD_DRIVER_S  2
+/** GPIO_PIN54_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN54_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_M  (GPIO_PIN54_SYNC1_BYPASS_V << GPIO_PIN54_SYNC1_BYPASS_S)
+#define GPIO_PIN54_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN54_SYNC1_BYPASS_S  3
+/** GPIO_PIN54_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN54_INT_TYPE    0x00000007U
+#define GPIO_PIN54_INT_TYPE_M  (GPIO_PIN54_INT_TYPE_V << GPIO_PIN54_INT_TYPE_S)
+#define GPIO_PIN54_INT_TYPE_V  0x00000007U
+#define GPIO_PIN54_INT_TYPE_S  7
+/** GPIO_PIN54_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN54_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN54_WAKEUP_ENABLE_M  (GPIO_PIN54_WAKEUP_ENABLE_V << GPIO_PIN54_WAKEUP_ENABLE_S)
+#define GPIO_PIN54_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN54_WAKEUP_ENABLE_S  10
+/** GPIO_PIN54_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN54_INT_ENA    0x0000001FU
+#define GPIO_PIN54_INT_ENA_M  (GPIO_PIN54_INT_ENA_V << GPIO_PIN54_INT_ENA_S)
+#define GPIO_PIN54_INT_ENA_V  0x0000001FU
+#define GPIO_PIN54_INT_ENA_S  13
+
+/** GPIO_PIN55_REG register
+ *  GPIO55 configuration register
+ */
+#define GPIO_PIN55_REG (DR_REG_GPIO_BASE + 0x1d0)
+/** GPIO_PIN55_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN55_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_M  (GPIO_PIN55_SYNC2_BYPASS_V << GPIO_PIN55_SYNC2_BYPASS_S)
+#define GPIO_PIN55_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC2_BYPASS_S  0
+/** GPIO_PIN55_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN55_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN55_PAD_DRIVER_M  (GPIO_PIN55_PAD_DRIVER_V << GPIO_PIN55_PAD_DRIVER_S)
+#define GPIO_PIN55_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN55_PAD_DRIVER_S  2
+/** GPIO_PIN55_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN55_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_M  (GPIO_PIN55_SYNC1_BYPASS_V << GPIO_PIN55_SYNC1_BYPASS_S)
+#define GPIO_PIN55_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN55_SYNC1_BYPASS_S  3
+/** GPIO_PIN55_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN55_INT_TYPE    0x00000007U
+#define GPIO_PIN55_INT_TYPE_M  (GPIO_PIN55_INT_TYPE_V << GPIO_PIN55_INT_TYPE_S)
+#define GPIO_PIN55_INT_TYPE_V  0x00000007U
+#define GPIO_PIN55_INT_TYPE_S  7
+/** GPIO_PIN55_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN55_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN55_WAKEUP_ENABLE_M  (GPIO_PIN55_WAKEUP_ENABLE_V << GPIO_PIN55_WAKEUP_ENABLE_S)
+#define GPIO_PIN55_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN55_WAKEUP_ENABLE_S  10
+/** GPIO_PIN55_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN55_INT_ENA    0x0000001FU
+#define GPIO_PIN55_INT_ENA_M  (GPIO_PIN55_INT_ENA_V << GPIO_PIN55_INT_ENA_S)
+#define GPIO_PIN55_INT_ENA_V  0x0000001FU
+#define GPIO_PIN55_INT_ENA_S  13
+
+/** GPIO_PIN56_REG register
+ *  GPIO56 configuration register
+ */
+#define GPIO_PIN56_REG (DR_REG_GPIO_BASE + 0x1d4)
+/** GPIO_PIN56_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN56_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_M  (GPIO_PIN56_SYNC2_BYPASS_V << GPIO_PIN56_SYNC2_BYPASS_S)
+#define GPIO_PIN56_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC2_BYPASS_S  0
+/** GPIO_PIN56_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN56_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN56_PAD_DRIVER_M  (GPIO_PIN56_PAD_DRIVER_V << GPIO_PIN56_PAD_DRIVER_S)
+#define GPIO_PIN56_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN56_PAD_DRIVER_S  2
+/** GPIO_PIN56_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN56_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_M  (GPIO_PIN56_SYNC1_BYPASS_V << GPIO_PIN56_SYNC1_BYPASS_S)
+#define GPIO_PIN56_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN56_SYNC1_BYPASS_S  3
+/** GPIO_PIN56_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN56_INT_TYPE    0x00000007U
+#define GPIO_PIN56_INT_TYPE_M  (GPIO_PIN56_INT_TYPE_V << GPIO_PIN56_INT_TYPE_S)
+#define GPIO_PIN56_INT_TYPE_V  0x00000007U
+#define GPIO_PIN56_INT_TYPE_S  7
+/** GPIO_PIN56_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN56_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN56_WAKEUP_ENABLE_M  (GPIO_PIN56_WAKEUP_ENABLE_V << GPIO_PIN56_WAKEUP_ENABLE_S)
+#define GPIO_PIN56_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN56_WAKEUP_ENABLE_S  10
+/** GPIO_PIN56_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN56_INT_ENA    0x0000001FU
+#define GPIO_PIN56_INT_ENA_M  (GPIO_PIN56_INT_ENA_V << GPIO_PIN56_INT_ENA_S)
+#define GPIO_PIN56_INT_ENA_V  0x0000001FU
+#define GPIO_PIN56_INT_ENA_S  13
+
+/** GPIO_PIN57_REG register
+ *  GPIO57 configuration register
+ */
+#define GPIO_PIN57_REG (DR_REG_GPIO_BASE + 0x1d8)
+/** GPIO_PIN57_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN57_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN57_SYNC2_BYPASS_M  (GPIO_PIN57_SYNC2_BYPASS_V << GPIO_PIN57_SYNC2_BYPASS_S)
+#define GPIO_PIN57_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN57_SYNC2_BYPASS_S  0
+/** GPIO_PIN57_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN57_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN57_PAD_DRIVER_M  (GPIO_PIN57_PAD_DRIVER_V << GPIO_PIN57_PAD_DRIVER_S)
+#define GPIO_PIN57_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN57_PAD_DRIVER_S  2
+/** GPIO_PIN57_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN57_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN57_SYNC1_BYPASS_M  (GPIO_PIN57_SYNC1_BYPASS_V << GPIO_PIN57_SYNC1_BYPASS_S)
+#define GPIO_PIN57_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN57_SYNC1_BYPASS_S  3
+/** GPIO_PIN57_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN57_INT_TYPE    0x00000007U
+#define GPIO_PIN57_INT_TYPE_M  (GPIO_PIN57_INT_TYPE_V << GPIO_PIN57_INT_TYPE_S)
+#define GPIO_PIN57_INT_TYPE_V  0x00000007U
+#define GPIO_PIN57_INT_TYPE_S  7
+/** GPIO_PIN57_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN57_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN57_WAKEUP_ENABLE_M  (GPIO_PIN57_WAKEUP_ENABLE_V << GPIO_PIN57_WAKEUP_ENABLE_S)
+#define GPIO_PIN57_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN57_WAKEUP_ENABLE_S  10
+/** GPIO_PIN57_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN57_INT_ENA    0x0000001FU
+#define GPIO_PIN57_INT_ENA_M  (GPIO_PIN57_INT_ENA_V << GPIO_PIN57_INT_ENA_S)
+#define GPIO_PIN57_INT_ENA_V  0x0000001FU
+#define GPIO_PIN57_INT_ENA_S  13
+
+/** GPIO_PIN58_REG register
+ *  GPIO58 configuration register
+ */
+#define GPIO_PIN58_REG (DR_REG_GPIO_BASE + 0x1dc)
+/** GPIO_PIN58_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN58_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN58_SYNC2_BYPASS_M  (GPIO_PIN58_SYNC2_BYPASS_V << GPIO_PIN58_SYNC2_BYPASS_S)
+#define GPIO_PIN58_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN58_SYNC2_BYPASS_S  0
+/** GPIO_PIN58_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN58_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN58_PAD_DRIVER_M  (GPIO_PIN58_PAD_DRIVER_V << GPIO_PIN58_PAD_DRIVER_S)
+#define GPIO_PIN58_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN58_PAD_DRIVER_S  2
+/** GPIO_PIN58_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN58_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN58_SYNC1_BYPASS_M  (GPIO_PIN58_SYNC1_BYPASS_V << GPIO_PIN58_SYNC1_BYPASS_S)
+#define GPIO_PIN58_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN58_SYNC1_BYPASS_S  3
+/** GPIO_PIN58_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN58_INT_TYPE    0x00000007U
+#define GPIO_PIN58_INT_TYPE_M  (GPIO_PIN58_INT_TYPE_V << GPIO_PIN58_INT_TYPE_S)
+#define GPIO_PIN58_INT_TYPE_V  0x00000007U
+#define GPIO_PIN58_INT_TYPE_S  7
+/** GPIO_PIN58_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN58_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN58_WAKEUP_ENABLE_M  (GPIO_PIN58_WAKEUP_ENABLE_V << GPIO_PIN58_WAKEUP_ENABLE_S)
+#define GPIO_PIN58_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN58_WAKEUP_ENABLE_S  10
+/** GPIO_PIN58_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN58_INT_ENA    0x0000001FU
+#define GPIO_PIN58_INT_ENA_M  (GPIO_PIN58_INT_ENA_V << GPIO_PIN58_INT_ENA_S)
+#define GPIO_PIN58_INT_ENA_V  0x0000001FU
+#define GPIO_PIN58_INT_ENA_S  13
+
+/** GPIO_PIN59_REG register
+ *  GPIO59 configuration register
+ */
+#define GPIO_PIN59_REG (DR_REG_GPIO_BASE + 0x1e0)
+/** GPIO_PIN59_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN59_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN59_SYNC2_BYPASS_M  (GPIO_PIN59_SYNC2_BYPASS_V << GPIO_PIN59_SYNC2_BYPASS_S)
+#define GPIO_PIN59_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN59_SYNC2_BYPASS_S  0
+/** GPIO_PIN59_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN59_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN59_PAD_DRIVER_M  (GPIO_PIN59_PAD_DRIVER_V << GPIO_PIN59_PAD_DRIVER_S)
+#define GPIO_PIN59_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN59_PAD_DRIVER_S  2
+/** GPIO_PIN59_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN59_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN59_SYNC1_BYPASS_M  (GPIO_PIN59_SYNC1_BYPASS_V << GPIO_PIN59_SYNC1_BYPASS_S)
+#define GPIO_PIN59_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN59_SYNC1_BYPASS_S  3
+/** GPIO_PIN59_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN59_INT_TYPE    0x00000007U
+#define GPIO_PIN59_INT_TYPE_M  (GPIO_PIN59_INT_TYPE_V << GPIO_PIN59_INT_TYPE_S)
+#define GPIO_PIN59_INT_TYPE_V  0x00000007U
+#define GPIO_PIN59_INT_TYPE_S  7
+/** GPIO_PIN59_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN59_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN59_WAKEUP_ENABLE_M  (GPIO_PIN59_WAKEUP_ENABLE_V << GPIO_PIN59_WAKEUP_ENABLE_S)
+#define GPIO_PIN59_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN59_WAKEUP_ENABLE_S  10
+/** GPIO_PIN59_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN59_INT_ENA    0x0000001FU
+#define GPIO_PIN59_INT_ENA_M  (GPIO_PIN59_INT_ENA_V << GPIO_PIN59_INT_ENA_S)
+#define GPIO_PIN59_INT_ENA_V  0x0000001FU
+#define GPIO_PIN59_INT_ENA_S  13
+
+/** GPIO_PIN60_REG register
+ *  GPIO60 configuration register
+ */
+#define GPIO_PIN60_REG (DR_REG_GPIO_BASE + 0x1e4)
+/** GPIO_PIN60_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN60_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN60_SYNC2_BYPASS_M  (GPIO_PIN60_SYNC2_BYPASS_V << GPIO_PIN60_SYNC2_BYPASS_S)
+#define GPIO_PIN60_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN60_SYNC2_BYPASS_S  0
+/** GPIO_PIN60_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN60_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN60_PAD_DRIVER_M  (GPIO_PIN60_PAD_DRIVER_V << GPIO_PIN60_PAD_DRIVER_S)
+#define GPIO_PIN60_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN60_PAD_DRIVER_S  2
+/** GPIO_PIN60_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN60_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN60_SYNC1_BYPASS_M  (GPIO_PIN60_SYNC1_BYPASS_V << GPIO_PIN60_SYNC1_BYPASS_S)
+#define GPIO_PIN60_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN60_SYNC1_BYPASS_S  3
+/** GPIO_PIN60_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN60_INT_TYPE    0x00000007U
+#define GPIO_PIN60_INT_TYPE_M  (GPIO_PIN60_INT_TYPE_V << GPIO_PIN60_INT_TYPE_S)
+#define GPIO_PIN60_INT_TYPE_V  0x00000007U
+#define GPIO_PIN60_INT_TYPE_S  7
+/** GPIO_PIN60_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN60_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN60_WAKEUP_ENABLE_M  (GPIO_PIN60_WAKEUP_ENABLE_V << GPIO_PIN60_WAKEUP_ENABLE_S)
+#define GPIO_PIN60_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN60_WAKEUP_ENABLE_S  10
+/** GPIO_PIN60_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN60_INT_ENA    0x0000001FU
+#define GPIO_PIN60_INT_ENA_M  (GPIO_PIN60_INT_ENA_V << GPIO_PIN60_INT_ENA_S)
+#define GPIO_PIN60_INT_ENA_V  0x0000001FU
+#define GPIO_PIN60_INT_ENA_S  13
+
+/** GPIO_PIN61_REG register
+ *  GPIO61 configuration register
+ */
+#define GPIO_PIN61_REG (DR_REG_GPIO_BASE + 0x1e8)
+/** GPIO_PIN61_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN61_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN61_SYNC2_BYPASS_M  (GPIO_PIN61_SYNC2_BYPASS_V << GPIO_PIN61_SYNC2_BYPASS_S)
+#define GPIO_PIN61_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN61_SYNC2_BYPASS_S  0
+/** GPIO_PIN61_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN61_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN61_PAD_DRIVER_M  (GPIO_PIN61_PAD_DRIVER_V << GPIO_PIN61_PAD_DRIVER_S)
+#define GPIO_PIN61_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN61_PAD_DRIVER_S  2
+/** GPIO_PIN61_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN61_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN61_SYNC1_BYPASS_M  (GPIO_PIN61_SYNC1_BYPASS_V << GPIO_PIN61_SYNC1_BYPASS_S)
+#define GPIO_PIN61_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN61_SYNC1_BYPASS_S  3
+/** GPIO_PIN61_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN61_INT_TYPE    0x00000007U
+#define GPIO_PIN61_INT_TYPE_M  (GPIO_PIN61_INT_TYPE_V << GPIO_PIN61_INT_TYPE_S)
+#define GPIO_PIN61_INT_TYPE_V  0x00000007U
+#define GPIO_PIN61_INT_TYPE_S  7
+/** GPIO_PIN61_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN61_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN61_WAKEUP_ENABLE_M  (GPIO_PIN61_WAKEUP_ENABLE_V << GPIO_PIN61_WAKEUP_ENABLE_S)
+#define GPIO_PIN61_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN61_WAKEUP_ENABLE_S  10
+/** GPIO_PIN61_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN61_INT_ENA    0x0000001FU
+#define GPIO_PIN61_INT_ENA_M  (GPIO_PIN61_INT_ENA_V << GPIO_PIN61_INT_ENA_S)
+#define GPIO_PIN61_INT_ENA_V  0x0000001FU
+#define GPIO_PIN61_INT_ENA_S  13
+
+/** GPIO_PIN62_REG register
+ *  GPIO62 configuration register
+ */
+#define GPIO_PIN62_REG (DR_REG_GPIO_BASE + 0x1ec)
+/** GPIO_PIN62_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the second-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN62_SYNC2_BYPASS    0x00000003U
+#define GPIO_PIN62_SYNC2_BYPASS_M  (GPIO_PIN62_SYNC2_BYPASS_V << GPIO_PIN62_SYNC2_BYPASS_S)
+#define GPIO_PIN62_SYNC2_BYPASS_V  0x00000003U
+#define GPIO_PIN62_SYNC2_BYPASS_S  0
+/** GPIO_PIN62_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
+ *  Configures to select pin drive mode.
+ *  0: Normal output
+ *  1: Open drain output
+ */
+#define GPIO_PIN62_PAD_DRIVER    (BIT(2))
+#define GPIO_PIN62_PAD_DRIVER_M  (GPIO_PIN62_PAD_DRIVER_V << GPIO_PIN62_PAD_DRIVER_S)
+#define GPIO_PIN62_PAD_DRIVER_V  0x00000001U
+#define GPIO_PIN62_PAD_DRIVER_S  2
+/** GPIO_PIN62_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
+ *  Configures whether or not to synchronize GPIO input data on either edge of IO MUX
+ *  operating clock for the first-level synchronization.
+ *  0: Not synchronize
+ *  1: Synchronize on falling edge
+ *  2: Synchronize on rising edge
+ *  3: Synchronize on rising edge
+ */
+#define GPIO_PIN62_SYNC1_BYPASS    0x00000003U
+#define GPIO_PIN62_SYNC1_BYPASS_M  (GPIO_PIN62_SYNC1_BYPASS_V << GPIO_PIN62_SYNC1_BYPASS_S)
+#define GPIO_PIN62_SYNC1_BYPASS_V  0x00000003U
+#define GPIO_PIN62_SYNC1_BYPASS_S  3
+/** GPIO_PIN62_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
+ *  Configures GPIO interrupt type.
+ *  0: GPIO interrupt disabled
+ *  1: Rising edge trigger
+ *  2: Falling edge trigger
+ *  3: Any edge trigger
+ *  4: Low level trigger
+ *  5: High level trigger
+ */
+#define GPIO_PIN62_INT_TYPE    0x00000007U
+#define GPIO_PIN62_INT_TYPE_M  (GPIO_PIN62_INT_TYPE_V << GPIO_PIN62_INT_TYPE_S)
+#define GPIO_PIN62_INT_TYPE_V  0x00000007U
+#define GPIO_PIN62_INT_TYPE_S  7
+/** GPIO_PIN62_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
+ *  Configures whether or not to enable GPIO wake-up function.
+ *  0: Disable
+ *  1: Enable
+ *  This function only wakes up the CPU from Light-sleep.
+ */
+#define GPIO_PIN62_WAKEUP_ENABLE    (BIT(10))
+#define GPIO_PIN62_WAKEUP_ENABLE_M  (GPIO_PIN62_WAKEUP_ENABLE_V << GPIO_PIN62_WAKEUP_ENABLE_S)
+#define GPIO_PIN62_WAKEUP_ENABLE_V  0x00000001U
+#define GPIO_PIN62_WAKEUP_ENABLE_S  10
+/** GPIO_PIN62_INT_ENA : R/W; bitpos: [17:13]; default: 0;
+ *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+ *  gpio_int_3(need update in different project).
+ *
+ *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+ *  project):
+ *  0: Disable
+ *  1: Enable
+ *  - bit17: invalid
+ */
+#define GPIO_PIN62_INT_ENA    0x0000001FU
+#define GPIO_PIN62_INT_ENA_M  (GPIO_PIN62_INT_ENA_V << GPIO_PIN62_INT_ENA_S)
+#define GPIO_PIN62_INT_ENA_V  0x0000001FU
+#define GPIO_PIN62_INT_ENA_S  13
+
+/** GPIO_FUNC0_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 0
+ */
+#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4)
+/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 0.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC0_IN_SEL    0x000000FFU
+#define GPIO_FUNC0_IN_SEL_M  (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S)
+#define GPIO_FUNC0_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC0_IN_SEL_S  0
+/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC0_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC0_IN_INV_SEL_M  (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S)
+#define GPIO_FUNC0_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_IN_INV_SEL_S  8
+/** GPIO_SIG0_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG0_IN_SEL    (BIT(9))
+#define GPIO_SIG0_IN_SEL_M  (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S)
+#define GPIO_SIG0_IN_SEL_V  0x00000001U
+#define GPIO_SIG0_IN_SEL_S  9
+
+/** GPIO_FUNC1_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 1
+ */
+#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8)
+/** GPIO_FUNC1_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 1.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC1_IN_SEL    0x000000FFU
+#define GPIO_FUNC1_IN_SEL_M  (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S)
+#define GPIO_FUNC1_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC1_IN_SEL_S  0
+/** GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC1_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC1_IN_INV_SEL_M  (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S)
+#define GPIO_FUNC1_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_IN_INV_SEL_S  8
+/** GPIO_SIG1_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG1_IN_SEL    (BIT(9))
+#define GPIO_SIG1_IN_SEL_M  (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S)
+#define GPIO_SIG1_IN_SEL_V  0x00000001U
+#define GPIO_SIG1_IN_SEL_S  9
+
+/** GPIO_FUNC2_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 2
+ */
+#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc)
+/** GPIO_FUNC2_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 2.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC2_IN_SEL    0x000000FFU
+#define GPIO_FUNC2_IN_SEL_M  (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S)
+#define GPIO_FUNC2_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC2_IN_SEL_S  0
+/** GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC2_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC2_IN_INV_SEL_M  (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S)
+#define GPIO_FUNC2_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_IN_INV_SEL_S  8
+/** GPIO_SIG2_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG2_IN_SEL    (BIT(9))
+#define GPIO_SIG2_IN_SEL_M  (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S)
+#define GPIO_SIG2_IN_SEL_V  0x00000001U
+#define GPIO_SIG2_IN_SEL_S  9
+
+/** GPIO_FUNC3_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 3
+ */
+#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300)
+/** GPIO_FUNC3_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 3.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC3_IN_SEL    0x000000FFU
+#define GPIO_FUNC3_IN_SEL_M  (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S)
+#define GPIO_FUNC3_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC3_IN_SEL_S  0
+/** GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC3_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC3_IN_INV_SEL_M  (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S)
+#define GPIO_FUNC3_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_IN_INV_SEL_S  8
+/** GPIO_SIG3_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG3_IN_SEL    (BIT(9))
+#define GPIO_SIG3_IN_SEL_M  (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S)
+#define GPIO_SIG3_IN_SEL_V  0x00000001U
+#define GPIO_SIG3_IN_SEL_S  9
+
+/** GPIO_FUNC4_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 4
+ */
+#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304)
+/** GPIO_FUNC4_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 4.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC4_IN_SEL    0x000000FFU
+#define GPIO_FUNC4_IN_SEL_M  (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S)
+#define GPIO_FUNC4_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC4_IN_SEL_S  0
+/** GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC4_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC4_IN_INV_SEL_M  (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S)
+#define GPIO_FUNC4_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_IN_INV_SEL_S  8
+/** GPIO_SIG4_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG4_IN_SEL    (BIT(9))
+#define GPIO_SIG4_IN_SEL_M  (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S)
+#define GPIO_SIG4_IN_SEL_V  0x00000001U
+#define GPIO_SIG4_IN_SEL_S  9
+
+/** GPIO_FUNC5_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 5
+ */
+#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308)
+/** GPIO_FUNC5_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 5.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC5_IN_SEL    0x000000FFU
+#define GPIO_FUNC5_IN_SEL_M  (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S)
+#define GPIO_FUNC5_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC5_IN_SEL_S  0
+/** GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC5_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC5_IN_INV_SEL_M  (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S)
+#define GPIO_FUNC5_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_IN_INV_SEL_S  8
+/** GPIO_SIG5_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG5_IN_SEL    (BIT(9))
+#define GPIO_SIG5_IN_SEL_M  (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S)
+#define GPIO_SIG5_IN_SEL_V  0x00000001U
+#define GPIO_SIG5_IN_SEL_S  9
+
+/** GPIO_FUNC6_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 6
+ */
+#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c)
+/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 6.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC6_IN_SEL    0x000000FFU
+#define GPIO_FUNC6_IN_SEL_M  (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S)
+#define GPIO_FUNC6_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC6_IN_SEL_S  0
+/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC6_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC6_IN_INV_SEL_M  (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S)
+#define GPIO_FUNC6_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_IN_INV_SEL_S  8
+/** GPIO_SIG6_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG6_IN_SEL    (BIT(9))
+#define GPIO_SIG6_IN_SEL_M  (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S)
+#define GPIO_SIG6_IN_SEL_V  0x00000001U
+#define GPIO_SIG6_IN_SEL_S  9
+
+/** GPIO_FUNC7_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 7
+ */
+#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310)
+/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 7.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC7_IN_SEL    0x000000FFU
+#define GPIO_FUNC7_IN_SEL_M  (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S)
+#define GPIO_FUNC7_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC7_IN_SEL_S  0
+/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC7_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC7_IN_INV_SEL_M  (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S)
+#define GPIO_FUNC7_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_IN_INV_SEL_S  8
+/** GPIO_SIG7_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG7_IN_SEL    (BIT(9))
+#define GPIO_SIG7_IN_SEL_M  (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S)
+#define GPIO_SIG7_IN_SEL_V  0x00000001U
+#define GPIO_SIG7_IN_SEL_S  9
+
+/** GPIO_FUNC10_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 10
+ */
+#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c)
+/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 10.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC10_IN_SEL    0x000000FFU
+#define GPIO_FUNC10_IN_SEL_M  (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S)
+#define GPIO_FUNC10_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC10_IN_SEL_S  0
+/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC10_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC10_IN_INV_SEL_M  (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S)
+#define GPIO_FUNC10_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_IN_INV_SEL_S  8
+/** GPIO_SIG10_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG10_IN_SEL    (BIT(9))
+#define GPIO_SIG10_IN_SEL_M  (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S)
+#define GPIO_SIG10_IN_SEL_V  0x00000001U
+#define GPIO_SIG10_IN_SEL_S  9
+
+/** GPIO_FUNC11_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 11
+ */
+#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320)
+/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 11.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC11_IN_SEL    0x000000FFU
+#define GPIO_FUNC11_IN_SEL_M  (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S)
+#define GPIO_FUNC11_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC11_IN_SEL_S  0
+/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC11_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC11_IN_INV_SEL_M  (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S)
+#define GPIO_FUNC11_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_IN_INV_SEL_S  8
+/** GPIO_SIG11_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG11_IN_SEL    (BIT(9))
+#define GPIO_SIG11_IN_SEL_M  (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S)
+#define GPIO_SIG11_IN_SEL_V  0x00000001U
+#define GPIO_SIG11_IN_SEL_S  9
+
+/** GPIO_FUNC12_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 12
+ */
+#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324)
+/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 12.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC12_IN_SEL    0x000000FFU
+#define GPIO_FUNC12_IN_SEL_M  (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S)
+#define GPIO_FUNC12_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC12_IN_SEL_S  0
+/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC12_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC12_IN_INV_SEL_M  (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S)
+#define GPIO_FUNC12_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_IN_INV_SEL_S  8
+/** GPIO_SIG12_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG12_IN_SEL    (BIT(9))
+#define GPIO_SIG12_IN_SEL_M  (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S)
+#define GPIO_SIG12_IN_SEL_V  0x00000001U
+#define GPIO_SIG12_IN_SEL_S  9
+
+/** GPIO_FUNC13_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 13
+ */
+#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328)
+/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 13.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC13_IN_SEL    0x000000FFU
+#define GPIO_FUNC13_IN_SEL_M  (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S)
+#define GPIO_FUNC13_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC13_IN_SEL_S  0
+/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC13_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC13_IN_INV_SEL_M  (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S)
+#define GPIO_FUNC13_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_IN_INV_SEL_S  8
+/** GPIO_SIG13_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG13_IN_SEL    (BIT(9))
+#define GPIO_SIG13_IN_SEL_M  (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S)
+#define GPIO_SIG13_IN_SEL_V  0x00000001U
+#define GPIO_SIG13_IN_SEL_S  9
+
+/** GPIO_FUNC14_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 14
+ */
+#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c)
+/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 14.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC14_IN_SEL    0x000000FFU
+#define GPIO_FUNC14_IN_SEL_M  (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S)
+#define GPIO_FUNC14_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC14_IN_SEL_S  0
+/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC14_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC14_IN_INV_SEL_M  (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S)
+#define GPIO_FUNC14_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_IN_INV_SEL_S  8
+/** GPIO_SIG14_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG14_IN_SEL    (BIT(9))
+#define GPIO_SIG14_IN_SEL_M  (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S)
+#define GPIO_SIG14_IN_SEL_V  0x00000001U
+#define GPIO_SIG14_IN_SEL_S  9
+
+/** GPIO_FUNC15_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 15
+ */
+#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330)
+/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 15.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC15_IN_SEL    0x000000FFU
+#define GPIO_FUNC15_IN_SEL_M  (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S)
+#define GPIO_FUNC15_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC15_IN_SEL_S  0
+/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC15_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC15_IN_INV_SEL_M  (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S)
+#define GPIO_FUNC15_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_IN_INV_SEL_S  8
+/** GPIO_SIG15_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG15_IN_SEL    (BIT(9))
+#define GPIO_SIG15_IN_SEL_M  (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S)
+#define GPIO_SIG15_IN_SEL_V  0x00000001U
+#define GPIO_SIG15_IN_SEL_S  9
+
+/** GPIO_FUNC16_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 16
+ */
+#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334)
+/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 16.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC16_IN_SEL    0x000000FFU
+#define GPIO_FUNC16_IN_SEL_M  (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S)
+#define GPIO_FUNC16_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC16_IN_SEL_S  0
+/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC16_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC16_IN_INV_SEL_M  (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S)
+#define GPIO_FUNC16_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_IN_INV_SEL_S  8
+/** GPIO_SIG16_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG16_IN_SEL    (BIT(9))
+#define GPIO_SIG16_IN_SEL_M  (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S)
+#define GPIO_SIG16_IN_SEL_V  0x00000001U
+#define GPIO_SIG16_IN_SEL_S  9
+
+/** GPIO_FUNC17_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 17
+ */
+#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338)
+/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 17.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC17_IN_SEL    0x000000FFU
+#define GPIO_FUNC17_IN_SEL_M  (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S)
+#define GPIO_FUNC17_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC17_IN_SEL_S  0
+/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC17_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC17_IN_INV_SEL_M  (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S)
+#define GPIO_FUNC17_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_IN_INV_SEL_S  8
+/** GPIO_SIG17_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG17_IN_SEL    (BIT(9))
+#define GPIO_SIG17_IN_SEL_M  (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S)
+#define GPIO_SIG17_IN_SEL_V  0x00000001U
+#define GPIO_SIG17_IN_SEL_S  9
+
+/** GPIO_FUNC18_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 18
+ */
+#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c)
+/** GPIO_FUNC18_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 18.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC18_IN_SEL    0x000000FFU
+#define GPIO_FUNC18_IN_SEL_M  (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S)
+#define GPIO_FUNC18_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC18_IN_SEL_S  0
+/** GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC18_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC18_IN_INV_SEL_M  (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S)
+#define GPIO_FUNC18_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_IN_INV_SEL_S  8
+/** GPIO_SIG18_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG18_IN_SEL    (BIT(9))
+#define GPIO_SIG18_IN_SEL_M  (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S)
+#define GPIO_SIG18_IN_SEL_V  0x00000001U
+#define GPIO_SIG18_IN_SEL_S  9
+
+/** GPIO_FUNC19_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 19
+ */
+#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340)
+/** GPIO_FUNC19_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 19.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC19_IN_SEL    0x000000FFU
+#define GPIO_FUNC19_IN_SEL_M  (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S)
+#define GPIO_FUNC19_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC19_IN_SEL_S  0
+/** GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC19_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC19_IN_INV_SEL_M  (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S)
+#define GPIO_FUNC19_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_IN_INV_SEL_S  8
+/** GPIO_SIG19_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG19_IN_SEL    (BIT(9))
+#define GPIO_SIG19_IN_SEL_M  (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S)
+#define GPIO_SIG19_IN_SEL_V  0x00000001U
+#define GPIO_SIG19_IN_SEL_S  9
+
+/** GPIO_FUNC20_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 20
+ */
+#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344)
+/** GPIO_FUNC20_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 20.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC20_IN_SEL    0x000000FFU
+#define GPIO_FUNC20_IN_SEL_M  (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S)
+#define GPIO_FUNC20_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC20_IN_SEL_S  0
+/** GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC20_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC20_IN_INV_SEL_M  (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S)
+#define GPIO_FUNC20_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_IN_INV_SEL_S  8
+/** GPIO_SIG20_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG20_IN_SEL    (BIT(9))
+#define GPIO_SIG20_IN_SEL_M  (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S)
+#define GPIO_SIG20_IN_SEL_V  0x00000001U
+#define GPIO_SIG20_IN_SEL_S  9
+
+/** GPIO_FUNC21_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 21
+ */
+#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348)
+/** GPIO_FUNC21_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 21.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC21_IN_SEL    0x000000FFU
+#define GPIO_FUNC21_IN_SEL_M  (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S)
+#define GPIO_FUNC21_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC21_IN_SEL_S  0
+/** GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC21_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC21_IN_INV_SEL_M  (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S)
+#define GPIO_FUNC21_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_IN_INV_SEL_S  8
+/** GPIO_SIG21_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG21_IN_SEL    (BIT(9))
+#define GPIO_SIG21_IN_SEL_M  (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S)
+#define GPIO_SIG21_IN_SEL_V  0x00000001U
+#define GPIO_SIG21_IN_SEL_S  9
+
+/** GPIO_FUNC22_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 22
+ */
+#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c)
+/** GPIO_FUNC22_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 22.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC22_IN_SEL    0x000000FFU
+#define GPIO_FUNC22_IN_SEL_M  (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S)
+#define GPIO_FUNC22_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC22_IN_SEL_S  0
+/** GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC22_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC22_IN_INV_SEL_M  (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S)
+#define GPIO_FUNC22_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_IN_INV_SEL_S  8
+/** GPIO_SIG22_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG22_IN_SEL    (BIT(9))
+#define GPIO_SIG22_IN_SEL_M  (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S)
+#define GPIO_SIG22_IN_SEL_V  0x00000001U
+#define GPIO_SIG22_IN_SEL_S  9
+
+/** GPIO_FUNC23_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 23
+ */
+#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350)
+/** GPIO_FUNC23_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 23.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC23_IN_SEL    0x000000FFU
+#define GPIO_FUNC23_IN_SEL_M  (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S)
+#define GPIO_FUNC23_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC23_IN_SEL_S  0
+/** GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC23_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC23_IN_INV_SEL_M  (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S)
+#define GPIO_FUNC23_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_IN_INV_SEL_S  8
+/** GPIO_SIG23_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG23_IN_SEL    (BIT(9))
+#define GPIO_SIG23_IN_SEL_M  (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S)
+#define GPIO_SIG23_IN_SEL_V  0x00000001U
+#define GPIO_SIG23_IN_SEL_S  9
+
+/** GPIO_FUNC24_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 24
+ */
+#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354)
+/** GPIO_FUNC24_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 24.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC24_IN_SEL    0x000000FFU
+#define GPIO_FUNC24_IN_SEL_M  (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S)
+#define GPIO_FUNC24_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC24_IN_SEL_S  0
+/** GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC24_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC24_IN_INV_SEL_M  (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S)
+#define GPIO_FUNC24_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_IN_INV_SEL_S  8
+/** GPIO_SIG24_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG24_IN_SEL    (BIT(9))
+#define GPIO_SIG24_IN_SEL_M  (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S)
+#define GPIO_SIG24_IN_SEL_V  0x00000001U
+#define GPIO_SIG24_IN_SEL_S  9
+
+/** GPIO_FUNC25_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 25
+ */
+#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358)
+/** GPIO_FUNC25_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 25.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC25_IN_SEL    0x000000FFU
+#define GPIO_FUNC25_IN_SEL_M  (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S)
+#define GPIO_FUNC25_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC25_IN_SEL_S  0
+/** GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC25_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC25_IN_INV_SEL_M  (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S)
+#define GPIO_FUNC25_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_IN_INV_SEL_S  8
+/** GPIO_SIG25_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG25_IN_SEL    (BIT(9))
+#define GPIO_SIG25_IN_SEL_M  (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S)
+#define GPIO_SIG25_IN_SEL_V  0x00000001U
+#define GPIO_SIG25_IN_SEL_S  9
+
+/** GPIO_FUNC26_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 26
+ */
+#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c)
+/** GPIO_FUNC26_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 26.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC26_IN_SEL    0x000000FFU
+#define GPIO_FUNC26_IN_SEL_M  (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S)
+#define GPIO_FUNC26_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC26_IN_SEL_S  0
+/** GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC26_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC26_IN_INV_SEL_M  (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S)
+#define GPIO_FUNC26_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_IN_INV_SEL_S  8
+/** GPIO_SIG26_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG26_IN_SEL    (BIT(9))
+#define GPIO_SIG26_IN_SEL_M  (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S)
+#define GPIO_SIG26_IN_SEL_V  0x00000001U
+#define GPIO_SIG26_IN_SEL_S  9
+
+/** GPIO_FUNC27_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 27
+ */
+#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360)
+/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 27.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC27_IN_SEL    0x000000FFU
+#define GPIO_FUNC27_IN_SEL_M  (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S)
+#define GPIO_FUNC27_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC27_IN_SEL_S  0
+/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC27_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC27_IN_INV_SEL_M  (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S)
+#define GPIO_FUNC27_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_IN_INV_SEL_S  8
+/** GPIO_SIG27_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG27_IN_SEL    (BIT(9))
+#define GPIO_SIG27_IN_SEL_M  (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S)
+#define GPIO_SIG27_IN_SEL_V  0x00000001U
+#define GPIO_SIG27_IN_SEL_S  9
+
+/** GPIO_FUNC28_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 28
+ */
+#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364)
+/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 28.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC28_IN_SEL    0x000000FFU
+#define GPIO_FUNC28_IN_SEL_M  (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S)
+#define GPIO_FUNC28_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC28_IN_SEL_S  0
+/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC28_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC28_IN_INV_SEL_M  (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S)
+#define GPIO_FUNC28_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_IN_INV_SEL_S  8
+/** GPIO_SIG28_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG28_IN_SEL    (BIT(9))
+#define GPIO_SIG28_IN_SEL_M  (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S)
+#define GPIO_SIG28_IN_SEL_V  0x00000001U
+#define GPIO_SIG28_IN_SEL_S  9
+
+/** GPIO_FUNC29_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 29
+ */
+#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368)
+/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 29.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC29_IN_SEL    0x000000FFU
+#define GPIO_FUNC29_IN_SEL_M  (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S)
+#define GPIO_FUNC29_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC29_IN_SEL_S  0
+/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC29_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC29_IN_INV_SEL_M  (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S)
+#define GPIO_FUNC29_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_IN_INV_SEL_S  8
+/** GPIO_SIG29_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG29_IN_SEL    (BIT(9))
+#define GPIO_SIG29_IN_SEL_M  (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S)
+#define GPIO_SIG29_IN_SEL_V  0x00000001U
+#define GPIO_SIG29_IN_SEL_S  9
+
+/** GPIO_FUNC30_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 30
+ */
+#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c)
+/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 30.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC30_IN_SEL    0x000000FFU
+#define GPIO_FUNC30_IN_SEL_M  (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S)
+#define GPIO_FUNC30_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC30_IN_SEL_S  0
+/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC30_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC30_IN_INV_SEL_M  (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S)
+#define GPIO_FUNC30_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_IN_INV_SEL_S  8
+/** GPIO_SIG30_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG30_IN_SEL    (BIT(9))
+#define GPIO_SIG30_IN_SEL_M  (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S)
+#define GPIO_SIG30_IN_SEL_V  0x00000001U
+#define GPIO_SIG30_IN_SEL_S  9
+
+/** GPIO_FUNC31_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 31
+ */
+#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370)
+/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 31.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC31_IN_SEL    0x000000FFU
+#define GPIO_FUNC31_IN_SEL_M  (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S)
+#define GPIO_FUNC31_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC31_IN_SEL_S  0
+/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC31_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC31_IN_INV_SEL_M  (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S)
+#define GPIO_FUNC31_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_IN_INV_SEL_S  8
+/** GPIO_SIG31_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG31_IN_SEL    (BIT(9))
+#define GPIO_SIG31_IN_SEL_M  (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S)
+#define GPIO_SIG31_IN_SEL_V  0x00000001U
+#define GPIO_SIG31_IN_SEL_S  9
+
+/** GPIO_FUNC32_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 32
+ */
+#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374)
+/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 32.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC32_IN_SEL    0x000000FFU
+#define GPIO_FUNC32_IN_SEL_M  (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S)
+#define GPIO_FUNC32_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC32_IN_SEL_S  0
+/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC32_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC32_IN_INV_SEL_M  (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S)
+#define GPIO_FUNC32_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_IN_INV_SEL_S  8
+/** GPIO_SIG32_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG32_IN_SEL    (BIT(9))
+#define GPIO_SIG32_IN_SEL_M  (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S)
+#define GPIO_SIG32_IN_SEL_V  0x00000001U
+#define GPIO_SIG32_IN_SEL_S  9
+
+/** GPIO_FUNC33_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 33
+ */
+#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378)
+/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 33.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC33_IN_SEL    0x000000FFU
+#define GPIO_FUNC33_IN_SEL_M  (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S)
+#define GPIO_FUNC33_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC33_IN_SEL_S  0
+/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC33_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC33_IN_INV_SEL_M  (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S)
+#define GPIO_FUNC33_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_IN_INV_SEL_S  8
+/** GPIO_SIG33_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG33_IN_SEL    (BIT(9))
+#define GPIO_SIG33_IN_SEL_M  (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S)
+#define GPIO_SIG33_IN_SEL_V  0x00000001U
+#define GPIO_SIG33_IN_SEL_S  9
+
+/** GPIO_FUNC34_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 34
+ */
+#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c)
+/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 34.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC34_IN_SEL    0x000000FFU
+#define GPIO_FUNC34_IN_SEL_M  (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S)
+#define GPIO_FUNC34_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC34_IN_SEL_S  0
+/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC34_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC34_IN_INV_SEL_M  (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S)
+#define GPIO_FUNC34_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_IN_INV_SEL_S  8
+/** GPIO_SIG34_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG34_IN_SEL    (BIT(9))
+#define GPIO_SIG34_IN_SEL_M  (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S)
+#define GPIO_SIG34_IN_SEL_V  0x00000001U
+#define GPIO_SIG34_IN_SEL_S  9
+
+/** GPIO_FUNC35_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 35
+ */
+#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380)
+/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 35.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC35_IN_SEL    0x000000FFU
+#define GPIO_FUNC35_IN_SEL_M  (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S)
+#define GPIO_FUNC35_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC35_IN_SEL_S  0
+/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC35_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC35_IN_INV_SEL_M  (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S)
+#define GPIO_FUNC35_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_IN_INV_SEL_S  8
+/** GPIO_SIG35_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG35_IN_SEL    (BIT(9))
+#define GPIO_SIG35_IN_SEL_M  (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S)
+#define GPIO_SIG35_IN_SEL_V  0x00000001U
+#define GPIO_SIG35_IN_SEL_S  9
+
+/** GPIO_FUNC36_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 36
+ */
+#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384)
+/** GPIO_FUNC36_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 36.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC36_IN_SEL    0x000000FFU
+#define GPIO_FUNC36_IN_SEL_M  (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S)
+#define GPIO_FUNC36_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC36_IN_SEL_S  0
+/** GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC36_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC36_IN_INV_SEL_M  (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S)
+#define GPIO_FUNC36_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_IN_INV_SEL_S  8
+/** GPIO_SIG36_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG36_IN_SEL    (BIT(9))
+#define GPIO_SIG36_IN_SEL_M  (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S)
+#define GPIO_SIG36_IN_SEL_V  0x00000001U
+#define GPIO_SIG36_IN_SEL_S  9
+
+/** GPIO_FUNC37_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 37
+ */
+#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388)
+/** GPIO_FUNC37_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 37.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC37_IN_SEL    0x000000FFU
+#define GPIO_FUNC37_IN_SEL_M  (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S)
+#define GPIO_FUNC37_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC37_IN_SEL_S  0
+/** GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC37_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC37_IN_INV_SEL_M  (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S)
+#define GPIO_FUNC37_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_IN_INV_SEL_S  8
+/** GPIO_SIG37_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG37_IN_SEL    (BIT(9))
+#define GPIO_SIG37_IN_SEL_M  (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S)
+#define GPIO_SIG37_IN_SEL_V  0x00000001U
+#define GPIO_SIG37_IN_SEL_S  9
+
+/** GPIO_FUNC38_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 38
+ */
+#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c)
+/** GPIO_FUNC38_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 38.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC38_IN_SEL    0x000000FFU
+#define GPIO_FUNC38_IN_SEL_M  (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S)
+#define GPIO_FUNC38_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC38_IN_SEL_S  0
+/** GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC38_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC38_IN_INV_SEL_M  (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S)
+#define GPIO_FUNC38_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_IN_INV_SEL_S  8
+/** GPIO_SIG38_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG38_IN_SEL    (BIT(9))
+#define GPIO_SIG38_IN_SEL_M  (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S)
+#define GPIO_SIG38_IN_SEL_V  0x00000001U
+#define GPIO_SIG38_IN_SEL_S  9
+
+/** GPIO_FUNC39_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 39
+ */
+#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390)
+/** GPIO_FUNC39_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 39.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC39_IN_SEL    0x000000FFU
+#define GPIO_FUNC39_IN_SEL_M  (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S)
+#define GPIO_FUNC39_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC39_IN_SEL_S  0
+/** GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC39_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC39_IN_INV_SEL_M  (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S)
+#define GPIO_FUNC39_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_IN_INV_SEL_S  8
+/** GPIO_SIG39_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG39_IN_SEL    (BIT(9))
+#define GPIO_SIG39_IN_SEL_M  (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S)
+#define GPIO_SIG39_IN_SEL_V  0x00000001U
+#define GPIO_SIG39_IN_SEL_S  9
+
+/** GPIO_FUNC40_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 40
+ */
+#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394)
+/** GPIO_FUNC40_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 40.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC40_IN_SEL    0x000000FFU
+#define GPIO_FUNC40_IN_SEL_M  (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S)
+#define GPIO_FUNC40_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC40_IN_SEL_S  0
+/** GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC40_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC40_IN_INV_SEL_M  (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S)
+#define GPIO_FUNC40_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_IN_INV_SEL_S  8
+/** GPIO_SIG40_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG40_IN_SEL    (BIT(9))
+#define GPIO_SIG40_IN_SEL_M  (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S)
+#define GPIO_SIG40_IN_SEL_V  0x00000001U
+#define GPIO_SIG40_IN_SEL_S  9
+
+/** GPIO_FUNC43_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 43
+ */
+#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0)
+/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 43.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC43_IN_SEL    0x000000FFU
+#define GPIO_FUNC43_IN_SEL_M  (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S)
+#define GPIO_FUNC43_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC43_IN_SEL_S  0
+/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC43_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC43_IN_INV_SEL_M  (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S)
+#define GPIO_FUNC43_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_IN_INV_SEL_S  8
+/** GPIO_SIG43_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG43_IN_SEL    (BIT(9))
+#define GPIO_SIG43_IN_SEL_M  (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S)
+#define GPIO_SIG43_IN_SEL_V  0x00000001U
+#define GPIO_SIG43_IN_SEL_S  9
+
+/** GPIO_FUNC44_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 44
+ */
+#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4)
+/** GPIO_FUNC44_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 44.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC44_IN_SEL    0x000000FFU
+#define GPIO_FUNC44_IN_SEL_M  (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S)
+#define GPIO_FUNC44_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC44_IN_SEL_S  0
+/** GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC44_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC44_IN_INV_SEL_M  (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S)
+#define GPIO_FUNC44_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_IN_INV_SEL_S  8
+/** GPIO_SIG44_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG44_IN_SEL    (BIT(9))
+#define GPIO_SIG44_IN_SEL_M  (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S)
+#define GPIO_SIG44_IN_SEL_V  0x00000001U
+#define GPIO_SIG44_IN_SEL_S  9
+
+/** GPIO_FUNC45_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 45
+ */
+#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8)
+/** GPIO_FUNC45_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 45.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC45_IN_SEL    0x000000FFU
+#define GPIO_FUNC45_IN_SEL_M  (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S)
+#define GPIO_FUNC45_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC45_IN_SEL_S  0
+/** GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC45_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC45_IN_INV_SEL_M  (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S)
+#define GPIO_FUNC45_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_IN_INV_SEL_S  8
+/** GPIO_SIG45_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG45_IN_SEL    (BIT(9))
+#define GPIO_SIG45_IN_SEL_M  (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S)
+#define GPIO_SIG45_IN_SEL_V  0x00000001U
+#define GPIO_SIG45_IN_SEL_S  9
+
+/** GPIO_FUNC47_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 47
+ */
+#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0)
+/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 47.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC47_IN_SEL    0x000000FFU
+#define GPIO_FUNC47_IN_SEL_M  (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S)
+#define GPIO_FUNC47_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC47_IN_SEL_S  0
+/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC47_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC47_IN_INV_SEL_M  (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S)
+#define GPIO_FUNC47_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_IN_INV_SEL_S  8
+/** GPIO_SIG47_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG47_IN_SEL    (BIT(9))
+#define GPIO_SIG47_IN_SEL_M  (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S)
+#define GPIO_SIG47_IN_SEL_V  0x00000001U
+#define GPIO_SIG47_IN_SEL_S  9
+
+/** GPIO_FUNC48_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 48
+ */
+#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4)
+/** GPIO_FUNC48_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 48.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC48_IN_SEL    0x000000FFU
+#define GPIO_FUNC48_IN_SEL_M  (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S)
+#define GPIO_FUNC48_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC48_IN_SEL_S  0
+/** GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC48_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC48_IN_INV_SEL_M  (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S)
+#define GPIO_FUNC48_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_IN_INV_SEL_S  8
+/** GPIO_SIG48_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG48_IN_SEL    (BIT(9))
+#define GPIO_SIG48_IN_SEL_M  (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S)
+#define GPIO_SIG48_IN_SEL_V  0x00000001U
+#define GPIO_SIG48_IN_SEL_S  9
+
+/** GPIO_FUNC49_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 49
+ */
+#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8)
+/** GPIO_FUNC49_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 49.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC49_IN_SEL    0x000000FFU
+#define GPIO_FUNC49_IN_SEL_M  (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S)
+#define GPIO_FUNC49_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC49_IN_SEL_S  0
+/** GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC49_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC49_IN_INV_SEL_M  (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S)
+#define GPIO_FUNC49_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_IN_INV_SEL_S  8
+/** GPIO_SIG49_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG49_IN_SEL    (BIT(9))
+#define GPIO_SIG49_IN_SEL_M  (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S)
+#define GPIO_SIG49_IN_SEL_V  0x00000001U
+#define GPIO_SIG49_IN_SEL_S  9
+
+/** GPIO_FUNC50_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 50
+ */
+#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc)
+/** GPIO_FUNC50_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 50.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC50_IN_SEL    0x000000FFU
+#define GPIO_FUNC50_IN_SEL_M  (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S)
+#define GPIO_FUNC50_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC50_IN_SEL_S  0
+/** GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC50_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC50_IN_INV_SEL_M  (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S)
+#define GPIO_FUNC50_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_IN_INV_SEL_S  8
+/** GPIO_SIG50_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG50_IN_SEL    (BIT(9))
+#define GPIO_SIG50_IN_SEL_M  (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S)
+#define GPIO_SIG50_IN_SEL_V  0x00000001U
+#define GPIO_SIG50_IN_SEL_S  9
+
+/** GPIO_FUNC51_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 51
+ */
+#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0)
+/** GPIO_FUNC51_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 51.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC51_IN_SEL    0x000000FFU
+#define GPIO_FUNC51_IN_SEL_M  (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S)
+#define GPIO_FUNC51_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC51_IN_SEL_S  0
+/** GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC51_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC51_IN_INV_SEL_M  (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S)
+#define GPIO_FUNC51_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_IN_INV_SEL_S  8
+/** GPIO_SIG51_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG51_IN_SEL    (BIT(9))
+#define GPIO_SIG51_IN_SEL_M  (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S)
+#define GPIO_SIG51_IN_SEL_V  0x00000001U
+#define GPIO_SIG51_IN_SEL_S  9
+
+/** GPIO_FUNC52_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 52
+ */
+#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4)
+/** GPIO_FUNC52_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 52.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC52_IN_SEL    0x000000FFU
+#define GPIO_FUNC52_IN_SEL_M  (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S)
+#define GPIO_FUNC52_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC52_IN_SEL_S  0
+/** GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC52_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC52_IN_INV_SEL_M  (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S)
+#define GPIO_FUNC52_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_IN_INV_SEL_S  8
+/** GPIO_SIG52_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG52_IN_SEL    (BIT(9))
+#define GPIO_SIG52_IN_SEL_M  (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S)
+#define GPIO_SIG52_IN_SEL_V  0x00000001U
+#define GPIO_SIG52_IN_SEL_S  9
+
+/** GPIO_FUNC53_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 53
+ */
+#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8)
+/** GPIO_FUNC53_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 53.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC53_IN_SEL    0x000000FFU
+#define GPIO_FUNC53_IN_SEL_M  (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S)
+#define GPIO_FUNC53_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC53_IN_SEL_S  0
+/** GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC53_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC53_IN_INV_SEL_M  (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S)
+#define GPIO_FUNC53_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_IN_INV_SEL_S  8
+/** GPIO_SIG53_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG53_IN_SEL    (BIT(9))
+#define GPIO_SIG53_IN_SEL_M  (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S)
+#define GPIO_SIG53_IN_SEL_V  0x00000001U
+#define GPIO_SIG53_IN_SEL_S  9
+
+/** GPIO_FUNC54_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 54
+ */
+#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc)
+/** GPIO_FUNC54_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 54.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC54_IN_SEL    0x000000FFU
+#define GPIO_FUNC54_IN_SEL_M  (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S)
+#define GPIO_FUNC54_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC54_IN_SEL_S  0
+/** GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC54_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC54_IN_INV_SEL_M  (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S)
+#define GPIO_FUNC54_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_IN_INV_SEL_S  8
+/** GPIO_SIG54_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG54_IN_SEL    (BIT(9))
+#define GPIO_SIG54_IN_SEL_M  (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S)
+#define GPIO_SIG54_IN_SEL_V  0x00000001U
+#define GPIO_SIG54_IN_SEL_S  9
+
+/** GPIO_FUNC55_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 55
+ */
+#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0)
+/** GPIO_FUNC55_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 55.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC55_IN_SEL    0x000000FFU
+#define GPIO_FUNC55_IN_SEL_M  (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S)
+#define GPIO_FUNC55_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC55_IN_SEL_S  0
+/** GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC55_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC55_IN_INV_SEL_M  (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S)
+#define GPIO_FUNC55_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_IN_INV_SEL_S  8
+/** GPIO_SIG55_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG55_IN_SEL    (BIT(9))
+#define GPIO_SIG55_IN_SEL_M  (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S)
+#define GPIO_SIG55_IN_SEL_V  0x00000001U
+#define GPIO_SIG55_IN_SEL_S  9
+
+/** GPIO_FUNC56_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 56
+ */
+#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4)
+/** GPIO_FUNC56_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 56.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC56_IN_SEL    0x000000FFU
+#define GPIO_FUNC56_IN_SEL_M  (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S)
+#define GPIO_FUNC56_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC56_IN_SEL_S  0
+/** GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC56_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC56_IN_INV_SEL_M  (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S)
+#define GPIO_FUNC56_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_IN_INV_SEL_S  8
+/** GPIO_SIG56_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG56_IN_SEL    (BIT(9))
+#define GPIO_SIG56_IN_SEL_M  (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S)
+#define GPIO_SIG56_IN_SEL_V  0x00000001U
+#define GPIO_SIG56_IN_SEL_S  9
+
+/** GPIO_FUNC57_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 57
+ */
+#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8)
+/** GPIO_FUNC57_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 57.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC57_IN_SEL    0x000000FFU
+#define GPIO_FUNC57_IN_SEL_M  (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S)
+#define GPIO_FUNC57_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC57_IN_SEL_S  0
+/** GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC57_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC57_IN_INV_SEL_M  (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S)
+#define GPIO_FUNC57_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_IN_INV_SEL_S  8
+/** GPIO_SIG57_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG57_IN_SEL    (BIT(9))
+#define GPIO_SIG57_IN_SEL_M  (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S)
+#define GPIO_SIG57_IN_SEL_V  0x00000001U
+#define GPIO_SIG57_IN_SEL_S  9
+
+/** GPIO_FUNC58_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 58
+ */
+#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc)
+/** GPIO_FUNC58_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 58.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC58_IN_SEL    0x000000FFU
+#define GPIO_FUNC58_IN_SEL_M  (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S)
+#define GPIO_FUNC58_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC58_IN_SEL_S  0
+/** GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC58_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC58_IN_INV_SEL_M  (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S)
+#define GPIO_FUNC58_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_IN_INV_SEL_S  8
+/** GPIO_SIG58_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG58_IN_SEL    (BIT(9))
+#define GPIO_SIG58_IN_SEL_M  (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S)
+#define GPIO_SIG58_IN_SEL_V  0x00000001U
+#define GPIO_SIG58_IN_SEL_S  9
+
+/** GPIO_FUNC59_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 59
+ */
+#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0)
+/** GPIO_FUNC59_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 59.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC59_IN_SEL    0x000000FFU
+#define GPIO_FUNC59_IN_SEL_M  (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S)
+#define GPIO_FUNC59_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC59_IN_SEL_S  0
+/** GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC59_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC59_IN_INV_SEL_M  (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S)
+#define GPIO_FUNC59_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_IN_INV_SEL_S  8
+/** GPIO_SIG59_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG59_IN_SEL    (BIT(9))
+#define GPIO_SIG59_IN_SEL_M  (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S)
+#define GPIO_SIG59_IN_SEL_V  0x00000001U
+#define GPIO_SIG59_IN_SEL_S  9
+
+/** GPIO_FUNC60_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 60
+ */
+#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4)
+/** GPIO_FUNC60_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 60.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC60_IN_SEL    0x000000FFU
+#define GPIO_FUNC60_IN_SEL_M  (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S)
+#define GPIO_FUNC60_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC60_IN_SEL_S  0
+/** GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC60_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC60_IN_INV_SEL_M  (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S)
+#define GPIO_FUNC60_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_IN_INV_SEL_S  8
+/** GPIO_SIG60_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG60_IN_SEL    (BIT(9))
+#define GPIO_SIG60_IN_SEL_M  (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S)
+#define GPIO_SIG60_IN_SEL_V  0x00000001U
+#define GPIO_SIG60_IN_SEL_S  9
+
+/** GPIO_FUNC61_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 61
+ */
+#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8)
+/** GPIO_FUNC61_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 61.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC61_IN_SEL    0x000000FFU
+#define GPIO_FUNC61_IN_SEL_M  (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S)
+#define GPIO_FUNC61_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC61_IN_SEL_S  0
+/** GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC61_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC61_IN_INV_SEL_M  (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S)
+#define GPIO_FUNC61_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_IN_INV_SEL_S  8
+/** GPIO_SIG61_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG61_IN_SEL    (BIT(9))
+#define GPIO_SIG61_IN_SEL_M  (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S)
+#define GPIO_SIG61_IN_SEL_V  0x00000001U
+#define GPIO_SIG61_IN_SEL_S  9
+
+/** GPIO_FUNC62_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 62
+ */
+#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec)
+/** GPIO_FUNC62_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 62.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC62_IN_SEL    0x000000FFU
+#define GPIO_FUNC62_IN_SEL_M  (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S)
+#define GPIO_FUNC62_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC62_IN_SEL_S  0
+/** GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC62_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC62_IN_INV_SEL_M  (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S)
+#define GPIO_FUNC62_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_IN_INV_SEL_S  8
+/** GPIO_SIG62_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG62_IN_SEL    (BIT(9))
+#define GPIO_SIG62_IN_SEL_M  (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S)
+#define GPIO_SIG62_IN_SEL_V  0x00000001U
+#define GPIO_SIG62_IN_SEL_S  9
+
+/** GPIO_FUNC63_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 63
+ */
+#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0)
+/** GPIO_FUNC63_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 63.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC63_IN_SEL    0x000000FFU
+#define GPIO_FUNC63_IN_SEL_M  (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S)
+#define GPIO_FUNC63_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC63_IN_SEL_S  0
+/** GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC63_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC63_IN_INV_SEL_M  (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S)
+#define GPIO_FUNC63_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC63_IN_INV_SEL_S  8
+/** GPIO_SIG63_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG63_IN_SEL    (BIT(9))
+#define GPIO_SIG63_IN_SEL_M  (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S)
+#define GPIO_SIG63_IN_SEL_V  0x00000001U
+#define GPIO_SIG63_IN_SEL_S  9
+
+/** GPIO_FUNC64_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 64
+ */
+#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4)
+/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 64.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC64_IN_SEL    0x000000FFU
+#define GPIO_FUNC64_IN_SEL_M  (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S)
+#define GPIO_FUNC64_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC64_IN_SEL_S  0
+/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC64_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC64_IN_INV_SEL_M  (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S)
+#define GPIO_FUNC64_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC64_IN_INV_SEL_S  8
+/** GPIO_SIG64_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG64_IN_SEL    (BIT(9))
+#define GPIO_SIG64_IN_SEL_M  (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S)
+#define GPIO_SIG64_IN_SEL_V  0x00000001U
+#define GPIO_SIG64_IN_SEL_S  9
+
+/** GPIO_FUNC65_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 65
+ */
+#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8)
+/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 65.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC65_IN_SEL    0x000000FFU
+#define GPIO_FUNC65_IN_SEL_M  (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S)
+#define GPIO_FUNC65_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC65_IN_SEL_S  0
+/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC65_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC65_IN_INV_SEL_M  (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S)
+#define GPIO_FUNC65_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC65_IN_INV_SEL_S  8
+/** GPIO_SIG65_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG65_IN_SEL    (BIT(9))
+#define GPIO_SIG65_IN_SEL_M  (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S)
+#define GPIO_SIG65_IN_SEL_V  0x00000001U
+#define GPIO_SIG65_IN_SEL_S  9
+
+/** GPIO_FUNC66_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 66
+ */
+#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc)
+/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 66.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC66_IN_SEL    0x000000FFU
+#define GPIO_FUNC66_IN_SEL_M  (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S)
+#define GPIO_FUNC66_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC66_IN_SEL_S  0
+/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC66_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC66_IN_INV_SEL_M  (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S)
+#define GPIO_FUNC66_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC66_IN_INV_SEL_S  8
+/** GPIO_SIG66_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG66_IN_SEL    (BIT(9))
+#define GPIO_SIG66_IN_SEL_M  (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S)
+#define GPIO_SIG66_IN_SEL_V  0x00000001U
+#define GPIO_SIG66_IN_SEL_S  9
+
+/** GPIO_FUNC68_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 68
+ */
+#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404)
+/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 68.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC68_IN_SEL    0x000000FFU
+#define GPIO_FUNC68_IN_SEL_M  (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S)
+#define GPIO_FUNC68_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC68_IN_SEL_S  0
+/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC68_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC68_IN_INV_SEL_M  (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S)
+#define GPIO_FUNC68_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC68_IN_INV_SEL_S  8
+/** GPIO_SIG68_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG68_IN_SEL    (BIT(9))
+#define GPIO_SIG68_IN_SEL_M  (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S)
+#define GPIO_SIG68_IN_SEL_V  0x00000001U
+#define GPIO_SIG68_IN_SEL_S  9
+
+/** GPIO_FUNC69_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 69
+ */
+#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408)
+/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 69.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC69_IN_SEL    0x000000FFU
+#define GPIO_FUNC69_IN_SEL_M  (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S)
+#define GPIO_FUNC69_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC69_IN_SEL_S  0
+/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC69_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC69_IN_INV_SEL_M  (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S)
+#define GPIO_FUNC69_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC69_IN_INV_SEL_S  8
+/** GPIO_SIG69_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG69_IN_SEL    (BIT(9))
+#define GPIO_SIG69_IN_SEL_M  (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S)
+#define GPIO_SIG69_IN_SEL_V  0x00000001U
+#define GPIO_SIG69_IN_SEL_S  9
+
+/** GPIO_FUNC70_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 70
+ */
+#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c)
+/** GPIO_FUNC70_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 70.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC70_IN_SEL    0x000000FFU
+#define GPIO_FUNC70_IN_SEL_M  (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S)
+#define GPIO_FUNC70_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC70_IN_SEL_S  0
+/** GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC70_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC70_IN_INV_SEL_M  (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S)
+#define GPIO_FUNC70_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC70_IN_INV_SEL_S  8
+/** GPIO_SIG70_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG70_IN_SEL    (BIT(9))
+#define GPIO_SIG70_IN_SEL_M  (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S)
+#define GPIO_SIG70_IN_SEL_V  0x00000001U
+#define GPIO_SIG70_IN_SEL_S  9
+
+/** GPIO_FUNC71_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 71
+ */
+#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410)
+/** GPIO_FUNC71_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 71.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC71_IN_SEL    0x000000FFU
+#define GPIO_FUNC71_IN_SEL_M  (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S)
+#define GPIO_FUNC71_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC71_IN_SEL_S  0
+/** GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC71_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC71_IN_INV_SEL_M  (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S)
+#define GPIO_FUNC71_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC71_IN_INV_SEL_S  8
+/** GPIO_SIG71_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG71_IN_SEL    (BIT(9))
+#define GPIO_SIG71_IN_SEL_M  (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S)
+#define GPIO_SIG71_IN_SEL_V  0x00000001U
+#define GPIO_SIG71_IN_SEL_S  9
+
+/** GPIO_FUNC72_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 72
+ */
+#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414)
+/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 72.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC72_IN_SEL    0x000000FFU
+#define GPIO_FUNC72_IN_SEL_M  (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S)
+#define GPIO_FUNC72_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC72_IN_SEL_S  0
+/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC72_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC72_IN_INV_SEL_M  (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S)
+#define GPIO_FUNC72_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC72_IN_INV_SEL_S  8
+/** GPIO_SIG72_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG72_IN_SEL    (BIT(9))
+#define GPIO_SIG72_IN_SEL_M  (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S)
+#define GPIO_SIG72_IN_SEL_V  0x00000001U
+#define GPIO_SIG72_IN_SEL_S  9
+
+/** GPIO_FUNC73_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 73
+ */
+#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418)
+/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 73.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC73_IN_SEL    0x000000FFU
+#define GPIO_FUNC73_IN_SEL_M  (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S)
+#define GPIO_FUNC73_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC73_IN_SEL_S  0
+/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC73_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC73_IN_INV_SEL_M  (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S)
+#define GPIO_FUNC73_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC73_IN_INV_SEL_S  8
+/** GPIO_SIG73_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG73_IN_SEL    (BIT(9))
+#define GPIO_SIG73_IN_SEL_M  (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S)
+#define GPIO_SIG73_IN_SEL_V  0x00000001U
+#define GPIO_SIG73_IN_SEL_S  9
+
+/** GPIO_FUNC74_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 74
+ */
+#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c)
+/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 74.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC74_IN_SEL    0x000000FFU
+#define GPIO_FUNC74_IN_SEL_M  (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S)
+#define GPIO_FUNC74_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC74_IN_SEL_S  0
+/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC74_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC74_IN_INV_SEL_M  (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S)
+#define GPIO_FUNC74_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC74_IN_INV_SEL_S  8
+/** GPIO_SIG74_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG74_IN_SEL    (BIT(9))
+#define GPIO_SIG74_IN_SEL_M  (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S)
+#define GPIO_SIG74_IN_SEL_V  0x00000001U
+#define GPIO_SIG74_IN_SEL_S  9
+
+/** GPIO_FUNC75_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 75
+ */
+#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420)
+/** GPIO_FUNC75_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 75.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC75_IN_SEL    0x000000FFU
+#define GPIO_FUNC75_IN_SEL_M  (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S)
+#define GPIO_FUNC75_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC75_IN_SEL_S  0
+/** GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC75_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC75_IN_INV_SEL_M  (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S)
+#define GPIO_FUNC75_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC75_IN_INV_SEL_S  8
+/** GPIO_SIG75_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG75_IN_SEL    (BIT(9))
+#define GPIO_SIG75_IN_SEL_M  (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S)
+#define GPIO_SIG75_IN_SEL_V  0x00000001U
+#define GPIO_SIG75_IN_SEL_S  9
+
+/** GPIO_FUNC76_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 76
+ */
+#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424)
+/** GPIO_FUNC76_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 76.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC76_IN_SEL    0x000000FFU
+#define GPIO_FUNC76_IN_SEL_M  (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S)
+#define GPIO_FUNC76_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC76_IN_SEL_S  0
+/** GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC76_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC76_IN_INV_SEL_M  (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S)
+#define GPIO_FUNC76_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC76_IN_INV_SEL_S  8
+/** GPIO_SIG76_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG76_IN_SEL    (BIT(9))
+#define GPIO_SIG76_IN_SEL_M  (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S)
+#define GPIO_SIG76_IN_SEL_V  0x00000001U
+#define GPIO_SIG76_IN_SEL_S  9
+
+/** GPIO_FUNC77_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 77
+ */
+#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428)
+/** GPIO_FUNC77_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 77.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC77_IN_SEL    0x000000FFU
+#define GPIO_FUNC77_IN_SEL_M  (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S)
+#define GPIO_FUNC77_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC77_IN_SEL_S  0
+/** GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC77_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC77_IN_INV_SEL_M  (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S)
+#define GPIO_FUNC77_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC77_IN_INV_SEL_S  8
+/** GPIO_SIG77_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG77_IN_SEL    (BIT(9))
+#define GPIO_SIG77_IN_SEL_M  (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S)
+#define GPIO_SIG77_IN_SEL_V  0x00000001U
+#define GPIO_SIG77_IN_SEL_S  9
+
+/** GPIO_FUNC78_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 78
+ */
+#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c)
+/** GPIO_FUNC78_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 78.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC78_IN_SEL    0x000000FFU
+#define GPIO_FUNC78_IN_SEL_M  (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S)
+#define GPIO_FUNC78_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC78_IN_SEL_S  0
+/** GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC78_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC78_IN_INV_SEL_M  (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S)
+#define GPIO_FUNC78_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC78_IN_INV_SEL_S  8
+/** GPIO_SIG78_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG78_IN_SEL    (BIT(9))
+#define GPIO_SIG78_IN_SEL_M  (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S)
+#define GPIO_SIG78_IN_SEL_V  0x00000001U
+#define GPIO_SIG78_IN_SEL_S  9
+
+/** GPIO_FUNC79_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 79
+ */
+#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430)
+/** GPIO_FUNC79_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 79.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC79_IN_SEL    0x000000FFU
+#define GPIO_FUNC79_IN_SEL_M  (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S)
+#define GPIO_FUNC79_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC79_IN_SEL_S  0
+/** GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC79_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC79_IN_INV_SEL_M  (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S)
+#define GPIO_FUNC79_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC79_IN_INV_SEL_S  8
+/** GPIO_SIG79_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG79_IN_SEL    (BIT(9))
+#define GPIO_SIG79_IN_SEL_M  (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S)
+#define GPIO_SIG79_IN_SEL_V  0x00000001U
+#define GPIO_SIG79_IN_SEL_S  9
+
+/** GPIO_FUNC80_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 80
+ */
+#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434)
+/** GPIO_FUNC80_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 80.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC80_IN_SEL    0x000000FFU
+#define GPIO_FUNC80_IN_SEL_M  (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S)
+#define GPIO_FUNC80_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC80_IN_SEL_S  0
+/** GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC80_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC80_IN_INV_SEL_M  (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S)
+#define GPIO_FUNC80_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC80_IN_INV_SEL_S  8
+/** GPIO_SIG80_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG80_IN_SEL    (BIT(9))
+#define GPIO_SIG80_IN_SEL_M  (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S)
+#define GPIO_SIG80_IN_SEL_V  0x00000001U
+#define GPIO_SIG80_IN_SEL_S  9
+
+/** GPIO_FUNC81_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 81
+ */
+#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438)
+/** GPIO_FUNC81_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 81.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC81_IN_SEL    0x000000FFU
+#define GPIO_FUNC81_IN_SEL_M  (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S)
+#define GPIO_FUNC81_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC81_IN_SEL_S  0
+/** GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC81_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC81_IN_INV_SEL_M  (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S)
+#define GPIO_FUNC81_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC81_IN_INV_SEL_S  8
+/** GPIO_SIG81_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG81_IN_SEL    (BIT(9))
+#define GPIO_SIG81_IN_SEL_M  (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S)
+#define GPIO_SIG81_IN_SEL_V  0x00000001U
+#define GPIO_SIG81_IN_SEL_S  9
+
+/** GPIO_FUNC82_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 82
+ */
+#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c)
+/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 82.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC82_IN_SEL    0x000000FFU
+#define GPIO_FUNC82_IN_SEL_M  (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S)
+#define GPIO_FUNC82_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC82_IN_SEL_S  0
+/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC82_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC82_IN_INV_SEL_M  (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S)
+#define GPIO_FUNC82_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC82_IN_INV_SEL_S  8
+/** GPIO_SIG82_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG82_IN_SEL    (BIT(9))
+#define GPIO_SIG82_IN_SEL_M  (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S)
+#define GPIO_SIG82_IN_SEL_V  0x00000001U
+#define GPIO_SIG82_IN_SEL_S  9
+
+/** GPIO_FUNC83_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 83
+ */
+#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440)
+/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 83.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC83_IN_SEL    0x000000FFU
+#define GPIO_FUNC83_IN_SEL_M  (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S)
+#define GPIO_FUNC83_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC83_IN_SEL_S  0
+/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC83_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC83_IN_INV_SEL_M  (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S)
+#define GPIO_FUNC83_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC83_IN_INV_SEL_S  8
+/** GPIO_SIG83_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG83_IN_SEL    (BIT(9))
+#define GPIO_SIG83_IN_SEL_M  (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S)
+#define GPIO_SIG83_IN_SEL_V  0x00000001U
+#define GPIO_SIG83_IN_SEL_S  9
+
+/** GPIO_FUNC84_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 84
+ */
+#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444)
+/** GPIO_FUNC84_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 84.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC84_IN_SEL    0x000000FFU
+#define GPIO_FUNC84_IN_SEL_M  (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S)
+#define GPIO_FUNC84_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC84_IN_SEL_S  0
+/** GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC84_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC84_IN_INV_SEL_M  (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S)
+#define GPIO_FUNC84_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC84_IN_INV_SEL_S  8
+/** GPIO_SIG84_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG84_IN_SEL    (BIT(9))
+#define GPIO_SIG84_IN_SEL_M  (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S)
+#define GPIO_SIG84_IN_SEL_V  0x00000001U
+#define GPIO_SIG84_IN_SEL_S  9
+
+/** GPIO_FUNC85_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 85
+ */
+#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448)
+/** GPIO_FUNC85_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 85.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC85_IN_SEL    0x000000FFU
+#define GPIO_FUNC85_IN_SEL_M  (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S)
+#define GPIO_FUNC85_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC85_IN_SEL_S  0
+/** GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC85_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC85_IN_INV_SEL_M  (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S)
+#define GPIO_FUNC85_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC85_IN_INV_SEL_S  8
+/** GPIO_SIG85_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG85_IN_SEL    (BIT(9))
+#define GPIO_SIG85_IN_SEL_M  (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S)
+#define GPIO_SIG85_IN_SEL_V  0x00000001U
+#define GPIO_SIG85_IN_SEL_S  9
+
+/** GPIO_FUNC86_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 86
+ */
+#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c)
+/** GPIO_FUNC86_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 86.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC86_IN_SEL    0x000000FFU
+#define GPIO_FUNC86_IN_SEL_M  (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S)
+#define GPIO_FUNC86_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC86_IN_SEL_S  0
+/** GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC86_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC86_IN_INV_SEL_M  (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S)
+#define GPIO_FUNC86_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC86_IN_INV_SEL_S  8
+/** GPIO_SIG86_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG86_IN_SEL    (BIT(9))
+#define GPIO_SIG86_IN_SEL_M  (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S)
+#define GPIO_SIG86_IN_SEL_V  0x00000001U
+#define GPIO_SIG86_IN_SEL_S  9
+
+/** GPIO_FUNC87_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 87
+ */
+#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450)
+/** GPIO_FUNC87_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 87.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC87_IN_SEL    0x000000FFU
+#define GPIO_FUNC87_IN_SEL_M  (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S)
+#define GPIO_FUNC87_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC87_IN_SEL_S  0
+/** GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC87_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC87_IN_INV_SEL_M  (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S)
+#define GPIO_FUNC87_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC87_IN_INV_SEL_S  8
+/** GPIO_SIG87_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG87_IN_SEL    (BIT(9))
+#define GPIO_SIG87_IN_SEL_M  (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S)
+#define GPIO_SIG87_IN_SEL_V  0x00000001U
+#define GPIO_SIG87_IN_SEL_S  9
+
+/** GPIO_FUNC88_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 88
+ */
+#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454)
+/** GPIO_FUNC88_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 88.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC88_IN_SEL    0x000000FFU
+#define GPIO_FUNC88_IN_SEL_M  (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S)
+#define GPIO_FUNC88_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC88_IN_SEL_S  0
+/** GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC88_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC88_IN_INV_SEL_M  (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S)
+#define GPIO_FUNC88_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC88_IN_INV_SEL_S  8
+/** GPIO_SIG88_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG88_IN_SEL    (BIT(9))
+#define GPIO_SIG88_IN_SEL_M  (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S)
+#define GPIO_SIG88_IN_SEL_V  0x00000001U
+#define GPIO_SIG88_IN_SEL_S  9
+
+/** GPIO_FUNC89_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 89
+ */
+#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458)
+/** GPIO_FUNC89_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 89.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC89_IN_SEL    0x000000FFU
+#define GPIO_FUNC89_IN_SEL_M  (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S)
+#define GPIO_FUNC89_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC89_IN_SEL_S  0
+/** GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC89_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC89_IN_INV_SEL_M  (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S)
+#define GPIO_FUNC89_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC89_IN_INV_SEL_S  8
+/** GPIO_SIG89_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG89_IN_SEL    (BIT(9))
+#define GPIO_SIG89_IN_SEL_M  (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S)
+#define GPIO_SIG89_IN_SEL_V  0x00000001U
+#define GPIO_SIG89_IN_SEL_S  9
+
+/** GPIO_FUNC90_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 90
+ */
+#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c)
+/** GPIO_FUNC90_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 90.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC90_IN_SEL    0x000000FFU
+#define GPIO_FUNC90_IN_SEL_M  (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S)
+#define GPIO_FUNC90_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC90_IN_SEL_S  0
+/** GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC90_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC90_IN_INV_SEL_M  (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S)
+#define GPIO_FUNC90_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC90_IN_INV_SEL_S  8
+/** GPIO_SIG90_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG90_IN_SEL    (BIT(9))
+#define GPIO_SIG90_IN_SEL_M  (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S)
+#define GPIO_SIG90_IN_SEL_V  0x00000001U
+#define GPIO_SIG90_IN_SEL_S  9
+
+/** GPIO_FUNC91_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 91
+ */
+#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460)
+/** GPIO_FUNC91_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 91.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC91_IN_SEL    0x000000FFU
+#define GPIO_FUNC91_IN_SEL_M  (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S)
+#define GPIO_FUNC91_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC91_IN_SEL_S  0
+/** GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC91_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC91_IN_INV_SEL_M  (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S)
+#define GPIO_FUNC91_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC91_IN_INV_SEL_S  8
+/** GPIO_SIG91_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG91_IN_SEL    (BIT(9))
+#define GPIO_SIG91_IN_SEL_M  (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S)
+#define GPIO_SIG91_IN_SEL_V  0x00000001U
+#define GPIO_SIG91_IN_SEL_S  9
+
+/** GPIO_FUNC92_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 92
+ */
+#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464)
+/** GPIO_FUNC92_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 92.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC92_IN_SEL    0x000000FFU
+#define GPIO_FUNC92_IN_SEL_M  (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S)
+#define GPIO_FUNC92_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC92_IN_SEL_S  0
+/** GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC92_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC92_IN_INV_SEL_M  (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S)
+#define GPIO_FUNC92_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC92_IN_INV_SEL_S  8
+/** GPIO_SIG92_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG92_IN_SEL    (BIT(9))
+#define GPIO_SIG92_IN_SEL_M  (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S)
+#define GPIO_SIG92_IN_SEL_V  0x00000001U
+#define GPIO_SIG92_IN_SEL_S  9
+
+/** GPIO_FUNC93_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 93
+ */
+#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468)
+/** GPIO_FUNC93_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 93.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC93_IN_SEL    0x000000FFU
+#define GPIO_FUNC93_IN_SEL_M  (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S)
+#define GPIO_FUNC93_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC93_IN_SEL_S  0
+/** GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC93_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC93_IN_INV_SEL_M  (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S)
+#define GPIO_FUNC93_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC93_IN_INV_SEL_S  8
+/** GPIO_SIG93_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG93_IN_SEL    (BIT(9))
+#define GPIO_SIG93_IN_SEL_M  (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S)
+#define GPIO_SIG93_IN_SEL_V  0x00000001U
+#define GPIO_SIG93_IN_SEL_S  9
+
+/** GPIO_FUNC94_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 94
+ */
+#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c)
+/** GPIO_FUNC94_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 94.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC94_IN_SEL    0x000000FFU
+#define GPIO_FUNC94_IN_SEL_M  (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S)
+#define GPIO_FUNC94_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC94_IN_SEL_S  0
+/** GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC94_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC94_IN_INV_SEL_M  (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S)
+#define GPIO_FUNC94_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC94_IN_INV_SEL_S  8
+/** GPIO_SIG94_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG94_IN_SEL    (BIT(9))
+#define GPIO_SIG94_IN_SEL_M  (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S)
+#define GPIO_SIG94_IN_SEL_V  0x00000001U
+#define GPIO_SIG94_IN_SEL_S  9
+
+/** GPIO_FUNC95_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 95
+ */
+#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470)
+/** GPIO_FUNC95_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 95.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC95_IN_SEL    0x000000FFU
+#define GPIO_FUNC95_IN_SEL_M  (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S)
+#define GPIO_FUNC95_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC95_IN_SEL_S  0
+/** GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC95_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC95_IN_INV_SEL_M  (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S)
+#define GPIO_FUNC95_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC95_IN_INV_SEL_S  8
+/** GPIO_SIG95_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG95_IN_SEL    (BIT(9))
+#define GPIO_SIG95_IN_SEL_M  (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S)
+#define GPIO_SIG95_IN_SEL_V  0x00000001U
+#define GPIO_SIG95_IN_SEL_S  9
+
+/** GPIO_FUNC96_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 96
+ */
+#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474)
+/** GPIO_FUNC96_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 96.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC96_IN_SEL    0x000000FFU
+#define GPIO_FUNC96_IN_SEL_M  (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S)
+#define GPIO_FUNC96_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC96_IN_SEL_S  0
+/** GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC96_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC96_IN_INV_SEL_M  (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S)
+#define GPIO_FUNC96_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC96_IN_INV_SEL_S  8
+/** GPIO_SIG96_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG96_IN_SEL    (BIT(9))
+#define GPIO_SIG96_IN_SEL_M  (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S)
+#define GPIO_SIG96_IN_SEL_V  0x00000001U
+#define GPIO_SIG96_IN_SEL_S  9
+
+/** GPIO_FUNC97_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 97
+ */
+#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478)
+/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 97.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC97_IN_SEL    0x000000FFU
+#define GPIO_FUNC97_IN_SEL_M  (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S)
+#define GPIO_FUNC97_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC97_IN_SEL_S  0
+/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC97_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC97_IN_INV_SEL_M  (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S)
+#define GPIO_FUNC97_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC97_IN_INV_SEL_S  8
+/** GPIO_SIG97_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG97_IN_SEL    (BIT(9))
+#define GPIO_SIG97_IN_SEL_M  (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S)
+#define GPIO_SIG97_IN_SEL_V  0x00000001U
+#define GPIO_SIG97_IN_SEL_S  9
+
+/** GPIO_FUNC98_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 98
+ */
+#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c)
+/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 98.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC98_IN_SEL    0x000000FFU
+#define GPIO_FUNC98_IN_SEL_M  (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S)
+#define GPIO_FUNC98_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC98_IN_SEL_S  0
+/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC98_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC98_IN_INV_SEL_M  (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S)
+#define GPIO_FUNC98_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC98_IN_INV_SEL_S  8
+/** GPIO_SIG98_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG98_IN_SEL    (BIT(9))
+#define GPIO_SIG98_IN_SEL_M  (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S)
+#define GPIO_SIG98_IN_SEL_V  0x00000001U
+#define GPIO_SIG98_IN_SEL_S  9
+
+/** GPIO_FUNC99_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 99
+ */
+#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480)
+/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 99.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC99_IN_SEL    0x000000FFU
+#define GPIO_FUNC99_IN_SEL_M  (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S)
+#define GPIO_FUNC99_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC99_IN_SEL_S  0
+/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC99_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC99_IN_INV_SEL_M  (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S)
+#define GPIO_FUNC99_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC99_IN_INV_SEL_S  8
+/** GPIO_SIG99_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG99_IN_SEL    (BIT(9))
+#define GPIO_SIG99_IN_SEL_M  (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S)
+#define GPIO_SIG99_IN_SEL_V  0x00000001U
+#define GPIO_SIG99_IN_SEL_S  9
+
+/** GPIO_FUNC100_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 100
+ */
+#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484)
+/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 100.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC100_IN_SEL    0x000000FFU
+#define GPIO_FUNC100_IN_SEL_M  (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S)
+#define GPIO_FUNC100_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC100_IN_SEL_S  0
+/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC100_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC100_IN_INV_SEL_M  (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S)
+#define GPIO_FUNC100_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC100_IN_INV_SEL_S  8
+/** GPIO_SIG100_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG100_IN_SEL    (BIT(9))
+#define GPIO_SIG100_IN_SEL_M  (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S)
+#define GPIO_SIG100_IN_SEL_V  0x00000001U
+#define GPIO_SIG100_IN_SEL_S  9
+
+/** GPIO_FUNC101_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 101
+ */
+#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488)
+/** GPIO_FUNC101_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 101.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC101_IN_SEL    0x000000FFU
+#define GPIO_FUNC101_IN_SEL_M  (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S)
+#define GPIO_FUNC101_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC101_IN_SEL_S  0
+/** GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC101_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC101_IN_INV_SEL_M  (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S)
+#define GPIO_FUNC101_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC101_IN_INV_SEL_S  8
+/** GPIO_SIG101_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG101_IN_SEL    (BIT(9))
+#define GPIO_SIG101_IN_SEL_M  (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S)
+#define GPIO_SIG101_IN_SEL_V  0x00000001U
+#define GPIO_SIG101_IN_SEL_S  9
+
+/** GPIO_FUNC102_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 102
+ */
+#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48c)
+/** GPIO_FUNC102_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 102.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC102_IN_SEL    0x000000FFU
+#define GPIO_FUNC102_IN_SEL_M  (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S)
+#define GPIO_FUNC102_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC102_IN_SEL_S  0
+/** GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC102_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC102_IN_INV_SEL_M  (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S)
+#define GPIO_FUNC102_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC102_IN_INV_SEL_S  8
+/** GPIO_SIG102_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG102_IN_SEL    (BIT(9))
+#define GPIO_SIG102_IN_SEL_M  (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S)
+#define GPIO_SIG102_IN_SEL_V  0x00000001U
+#define GPIO_SIG102_IN_SEL_S  9
+
+/** GPIO_FUNC103_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 103
+ */
+#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490)
+/** GPIO_FUNC103_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 103.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC103_IN_SEL    0x000000FFU
+#define GPIO_FUNC103_IN_SEL_M  (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S)
+#define GPIO_FUNC103_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC103_IN_SEL_S  0
+/** GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC103_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC103_IN_INV_SEL_M  (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S)
+#define GPIO_FUNC103_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC103_IN_INV_SEL_S  8
+/** GPIO_SIG103_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG103_IN_SEL    (BIT(9))
+#define GPIO_SIG103_IN_SEL_M  (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S)
+#define GPIO_SIG103_IN_SEL_V  0x00000001U
+#define GPIO_SIG103_IN_SEL_S  9
+
+/** GPIO_FUNC104_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 104
+ */
+#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494)
+/** GPIO_FUNC104_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 104.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC104_IN_SEL    0x000000FFU
+#define GPIO_FUNC104_IN_SEL_M  (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S)
+#define GPIO_FUNC104_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC104_IN_SEL_S  0
+/** GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC104_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC104_IN_INV_SEL_M  (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S)
+#define GPIO_FUNC104_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC104_IN_INV_SEL_S  8
+/** GPIO_SIG104_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG104_IN_SEL    (BIT(9))
+#define GPIO_SIG104_IN_SEL_M  (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S)
+#define GPIO_SIG104_IN_SEL_V  0x00000001U
+#define GPIO_SIG104_IN_SEL_S  9
+
+/** GPIO_FUNC105_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 105
+ */
+#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x498)
+/** GPIO_FUNC105_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 105.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC105_IN_SEL    0x000000FFU
+#define GPIO_FUNC105_IN_SEL_M  (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S)
+#define GPIO_FUNC105_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC105_IN_SEL_S  0
+/** GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC105_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC105_IN_INV_SEL_M  (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S)
+#define GPIO_FUNC105_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC105_IN_INV_SEL_S  8
+/** GPIO_SIG105_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG105_IN_SEL    (BIT(9))
+#define GPIO_SIG105_IN_SEL_M  (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S)
+#define GPIO_SIG105_IN_SEL_V  0x00000001U
+#define GPIO_SIG105_IN_SEL_S  9
+
+/** GPIO_FUNC106_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 106
+ */
+#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c)
+/** GPIO_FUNC106_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 106.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC106_IN_SEL    0x000000FFU
+#define GPIO_FUNC106_IN_SEL_M  (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S)
+#define GPIO_FUNC106_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC106_IN_SEL_S  0
+/** GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC106_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC106_IN_INV_SEL_M  (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S)
+#define GPIO_FUNC106_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC106_IN_INV_SEL_S  8
+/** GPIO_SIG106_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG106_IN_SEL    (BIT(9))
+#define GPIO_SIG106_IN_SEL_M  (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S)
+#define GPIO_SIG106_IN_SEL_V  0x00000001U
+#define GPIO_SIG106_IN_SEL_S  9
+
+/** GPIO_FUNC107_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 107
+ */
+#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0)
+/** GPIO_FUNC107_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 107.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC107_IN_SEL    0x000000FFU
+#define GPIO_FUNC107_IN_SEL_M  (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S)
+#define GPIO_FUNC107_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC107_IN_SEL_S  0
+/** GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC107_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC107_IN_INV_SEL_M  (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S)
+#define GPIO_FUNC107_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC107_IN_INV_SEL_S  8
+/** GPIO_SIG107_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG107_IN_SEL    (BIT(9))
+#define GPIO_SIG107_IN_SEL_M  (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S)
+#define GPIO_SIG107_IN_SEL_V  0x00000001U
+#define GPIO_SIG107_IN_SEL_S  9
+
+/** GPIO_FUNC108_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 108
+ */
+#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4)
+/** GPIO_FUNC108_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 108.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC108_IN_SEL    0x000000FFU
+#define GPIO_FUNC108_IN_SEL_M  (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S)
+#define GPIO_FUNC108_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC108_IN_SEL_S  0
+/** GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC108_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC108_IN_INV_SEL_M  (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S)
+#define GPIO_FUNC108_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC108_IN_INV_SEL_S  8
+/** GPIO_SIG108_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG108_IN_SEL    (BIT(9))
+#define GPIO_SIG108_IN_SEL_M  (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S)
+#define GPIO_SIG108_IN_SEL_V  0x00000001U
+#define GPIO_SIG108_IN_SEL_S  9
+
+/** GPIO_FUNC109_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 109
+ */
+#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8)
+/** GPIO_FUNC109_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 109.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC109_IN_SEL    0x000000FFU
+#define GPIO_FUNC109_IN_SEL_M  (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S)
+#define GPIO_FUNC109_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC109_IN_SEL_S  0
+/** GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC109_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC109_IN_INV_SEL_M  (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S)
+#define GPIO_FUNC109_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC109_IN_INV_SEL_S  8
+/** GPIO_SIG109_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG109_IN_SEL    (BIT(9))
+#define GPIO_SIG109_IN_SEL_M  (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S)
+#define GPIO_SIG109_IN_SEL_V  0x00000001U
+#define GPIO_SIG109_IN_SEL_S  9
+
+/** GPIO_FUNC110_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 110
+ */
+#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ac)
+/** GPIO_FUNC110_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 110.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC110_IN_SEL    0x000000FFU
+#define GPIO_FUNC110_IN_SEL_M  (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S)
+#define GPIO_FUNC110_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC110_IN_SEL_S  0
+/** GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC110_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC110_IN_INV_SEL_M  (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S)
+#define GPIO_FUNC110_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC110_IN_INV_SEL_S  8
+/** GPIO_SIG110_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG110_IN_SEL    (BIT(9))
+#define GPIO_SIG110_IN_SEL_M  (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S)
+#define GPIO_SIG110_IN_SEL_V  0x00000001U
+#define GPIO_SIG110_IN_SEL_S  9
+
+/** GPIO_FUNC111_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 111
+ */
+#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0)
+/** GPIO_FUNC111_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 111.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC111_IN_SEL    0x000000FFU
+#define GPIO_FUNC111_IN_SEL_M  (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S)
+#define GPIO_FUNC111_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC111_IN_SEL_S  0
+/** GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC111_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC111_IN_INV_SEL_M  (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S)
+#define GPIO_FUNC111_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC111_IN_INV_SEL_S  8
+/** GPIO_SIG111_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG111_IN_SEL    (BIT(9))
+#define GPIO_SIG111_IN_SEL_M  (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S)
+#define GPIO_SIG111_IN_SEL_V  0x00000001U
+#define GPIO_SIG111_IN_SEL_S  9
+
+/** GPIO_FUNC112_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 112
+ */
+#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4)
+/** GPIO_FUNC112_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 112.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC112_IN_SEL    0x000000FFU
+#define GPIO_FUNC112_IN_SEL_M  (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S)
+#define GPIO_FUNC112_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC112_IN_SEL_S  0
+/** GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC112_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC112_IN_INV_SEL_M  (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S)
+#define GPIO_FUNC112_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC112_IN_INV_SEL_S  8
+/** GPIO_SIG112_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG112_IN_SEL    (BIT(9))
+#define GPIO_SIG112_IN_SEL_M  (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S)
+#define GPIO_SIG112_IN_SEL_V  0x00000001U
+#define GPIO_SIG112_IN_SEL_S  9
+
+/** GPIO_FUNC113_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 113
+ */
+#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8)
+/** GPIO_FUNC113_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 113.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC113_IN_SEL    0x000000FFU
+#define GPIO_FUNC113_IN_SEL_M  (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S)
+#define GPIO_FUNC113_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC113_IN_SEL_S  0
+/** GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC113_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC113_IN_INV_SEL_M  (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S)
+#define GPIO_FUNC113_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC113_IN_INV_SEL_S  8
+/** GPIO_SIG113_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG113_IN_SEL    (BIT(9))
+#define GPIO_SIG113_IN_SEL_M  (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S)
+#define GPIO_SIG113_IN_SEL_V  0x00000001U
+#define GPIO_SIG113_IN_SEL_S  9
+
+/** GPIO_FUNC114_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 114
+ */
+#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc)
+/** GPIO_FUNC114_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 114.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC114_IN_SEL    0x000000FFU
+#define GPIO_FUNC114_IN_SEL_M  (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S)
+#define GPIO_FUNC114_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC114_IN_SEL_S  0
+/** GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC114_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC114_IN_INV_SEL_M  (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S)
+#define GPIO_FUNC114_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC114_IN_INV_SEL_S  8
+/** GPIO_SIG114_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG114_IN_SEL    (BIT(9))
+#define GPIO_SIG114_IN_SEL_M  (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S)
+#define GPIO_SIG114_IN_SEL_V  0x00000001U
+#define GPIO_SIG114_IN_SEL_S  9
+
+/** GPIO_FUNC115_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 115
+ */
+#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0)
+/** GPIO_FUNC115_IN_SEL : R/W; bitpos: [7:0]; default: 128;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 115.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC115_IN_SEL    0x000000FFU
+#define GPIO_FUNC115_IN_SEL_M  (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S)
+#define GPIO_FUNC115_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC115_IN_SEL_S  0
+/** GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC115_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC115_IN_INV_SEL_M  (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S)
+#define GPIO_FUNC115_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC115_IN_INV_SEL_S  8
+/** GPIO_SIG115_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG115_IN_SEL    (BIT(9))
+#define GPIO_SIG115_IN_SEL_M  (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S)
+#define GPIO_SIG115_IN_SEL_V  0x00000001U
+#define GPIO_SIG115_IN_SEL_S  9
+
+/** GPIO_FUNC118_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 118
+ */
+#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc)
+/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 118.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC118_IN_SEL    0x000000FFU
+#define GPIO_FUNC118_IN_SEL_M  (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S)
+#define GPIO_FUNC118_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC118_IN_SEL_S  0
+/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC118_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC118_IN_INV_SEL_M  (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S)
+#define GPIO_FUNC118_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC118_IN_INV_SEL_S  8
+/** GPIO_SIG118_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG118_IN_SEL    (BIT(9))
+#define GPIO_SIG118_IN_SEL_M  (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S)
+#define GPIO_SIG118_IN_SEL_V  0x00000001U
+#define GPIO_SIG118_IN_SEL_S  9
+
+/** GPIO_FUNC119_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 119
+ */
+#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0)
+/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 119.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC119_IN_SEL    0x000000FFU
+#define GPIO_FUNC119_IN_SEL_M  (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S)
+#define GPIO_FUNC119_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC119_IN_SEL_S  0
+/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC119_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC119_IN_INV_SEL_M  (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S)
+#define GPIO_FUNC119_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC119_IN_INV_SEL_S  8
+/** GPIO_SIG119_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG119_IN_SEL    (BIT(9))
+#define GPIO_SIG119_IN_SEL_M  (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S)
+#define GPIO_SIG119_IN_SEL_V  0x00000001U
+#define GPIO_SIG119_IN_SEL_S  9
+
+/** GPIO_FUNC120_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 120
+ */
+#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4)
+/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 120.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC120_IN_SEL    0x000000FFU
+#define GPIO_FUNC120_IN_SEL_M  (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S)
+#define GPIO_FUNC120_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC120_IN_SEL_S  0
+/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC120_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC120_IN_INV_SEL_M  (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S)
+#define GPIO_FUNC120_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC120_IN_INV_SEL_S  8
+/** GPIO_SIG120_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG120_IN_SEL    (BIT(9))
+#define GPIO_SIG120_IN_SEL_M  (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S)
+#define GPIO_SIG120_IN_SEL_V  0x00000001U
+#define GPIO_SIG120_IN_SEL_S  9
+
+/** GPIO_FUNC121_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 121
+ */
+#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8)
+/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 121.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC121_IN_SEL    0x000000FFU
+#define GPIO_FUNC121_IN_SEL_M  (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S)
+#define GPIO_FUNC121_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC121_IN_SEL_S  0
+/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC121_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC121_IN_INV_SEL_M  (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S)
+#define GPIO_FUNC121_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC121_IN_INV_SEL_S  8
+/** GPIO_SIG121_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG121_IN_SEL    (BIT(9))
+#define GPIO_SIG121_IN_SEL_M  (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S)
+#define GPIO_SIG121_IN_SEL_V  0x00000001U
+#define GPIO_SIG121_IN_SEL_S  9
+
+/** GPIO_FUNC122_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 122
+ */
+#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc)
+/** GPIO_FUNC122_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 122.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC122_IN_SEL    0x000000FFU
+#define GPIO_FUNC122_IN_SEL_M  (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S)
+#define GPIO_FUNC122_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC122_IN_SEL_S  0
+/** GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC122_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC122_IN_INV_SEL_M  (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S)
+#define GPIO_FUNC122_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC122_IN_INV_SEL_S  8
+/** GPIO_SIG122_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG122_IN_SEL    (BIT(9))
+#define GPIO_SIG122_IN_SEL_M  (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S)
+#define GPIO_SIG122_IN_SEL_V  0x00000001U
+#define GPIO_SIG122_IN_SEL_S  9
+
+/** GPIO_FUNC123_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 123
+ */
+#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0)
+/** GPIO_FUNC123_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 123.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC123_IN_SEL    0x000000FFU
+#define GPIO_FUNC123_IN_SEL_M  (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S)
+#define GPIO_FUNC123_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC123_IN_SEL_S  0
+/** GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC123_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC123_IN_INV_SEL_M  (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S)
+#define GPIO_FUNC123_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC123_IN_INV_SEL_S  8
+/** GPIO_SIG123_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG123_IN_SEL    (BIT(9))
+#define GPIO_SIG123_IN_SEL_M  (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S)
+#define GPIO_SIG123_IN_SEL_V  0x00000001U
+#define GPIO_SIG123_IN_SEL_S  9
+
+/** GPIO_FUNC124_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 124
+ */
+#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4)
+/** GPIO_FUNC124_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 124.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC124_IN_SEL    0x000000FFU
+#define GPIO_FUNC124_IN_SEL_M  (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S)
+#define GPIO_FUNC124_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC124_IN_SEL_S  0
+/** GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC124_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC124_IN_INV_SEL_M  (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S)
+#define GPIO_FUNC124_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC124_IN_INV_SEL_S  8
+/** GPIO_SIG124_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG124_IN_SEL    (BIT(9))
+#define GPIO_SIG124_IN_SEL_M  (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S)
+#define GPIO_SIG124_IN_SEL_V  0x00000001U
+#define GPIO_SIG124_IN_SEL_S  9
+
+/** GPIO_FUNC125_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 125
+ */
+#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8)
+/** GPIO_FUNC125_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 125.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC125_IN_SEL    0x000000FFU
+#define GPIO_FUNC125_IN_SEL_M  (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S)
+#define GPIO_FUNC125_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC125_IN_SEL_S  0
+/** GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC125_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC125_IN_INV_SEL_M  (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S)
+#define GPIO_FUNC125_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC125_IN_INV_SEL_S  8
+/** GPIO_SIG125_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG125_IN_SEL    (BIT(9))
+#define GPIO_SIG125_IN_SEL_M  (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S)
+#define GPIO_SIG125_IN_SEL_V  0x00000001U
+#define GPIO_SIG125_IN_SEL_S  9
+
+/** GPIO_FUNC126_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 126
+ */
+#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec)
+/** GPIO_FUNC126_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 126.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC126_IN_SEL    0x000000FFU
+#define GPIO_FUNC126_IN_SEL_M  (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S)
+#define GPIO_FUNC126_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC126_IN_SEL_S  0
+/** GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC126_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC126_IN_INV_SEL_M  (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S)
+#define GPIO_FUNC126_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC126_IN_INV_SEL_S  8
+/** GPIO_SIG126_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG126_IN_SEL    (BIT(9))
+#define GPIO_SIG126_IN_SEL_M  (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S)
+#define GPIO_SIG126_IN_SEL_V  0x00000001U
+#define GPIO_SIG126_IN_SEL_S  9
+
+/** GPIO_FUNC127_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 127
+ */
+#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0)
+/** GPIO_FUNC127_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 127.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC127_IN_SEL    0x000000FFU
+#define GPIO_FUNC127_IN_SEL_M  (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S)
+#define GPIO_FUNC127_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC127_IN_SEL_S  0
+/** GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC127_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC127_IN_INV_SEL_M  (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S)
+#define GPIO_FUNC127_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC127_IN_INV_SEL_S  8
+/** GPIO_SIG127_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG127_IN_SEL    (BIT(9))
+#define GPIO_SIG127_IN_SEL_M  (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S)
+#define GPIO_SIG127_IN_SEL_V  0x00000001U
+#define GPIO_SIG127_IN_SEL_S  9
+
+/** GPIO_FUNC128_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 128
+ */
+#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4)
+/** GPIO_FUNC128_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 128.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC128_IN_SEL    0x000000FFU
+#define GPIO_FUNC128_IN_SEL_M  (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S)
+#define GPIO_FUNC128_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC128_IN_SEL_S  0
+/** GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC128_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC128_IN_INV_SEL_M  (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S)
+#define GPIO_FUNC128_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC128_IN_INV_SEL_S  8
+/** GPIO_SIG128_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG128_IN_SEL    (BIT(9))
+#define GPIO_SIG128_IN_SEL_M  (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S)
+#define GPIO_SIG128_IN_SEL_V  0x00000001U
+#define GPIO_SIG128_IN_SEL_S  9
+
+/** GPIO_FUNC129_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 129
+ */
+#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8)
+/** GPIO_FUNC129_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 129.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC129_IN_SEL    0x000000FFU
+#define GPIO_FUNC129_IN_SEL_M  (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S)
+#define GPIO_FUNC129_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC129_IN_SEL_S  0
+/** GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC129_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC129_IN_INV_SEL_M  (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S)
+#define GPIO_FUNC129_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC129_IN_INV_SEL_S  8
+/** GPIO_SIG129_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG129_IN_SEL    (BIT(9))
+#define GPIO_SIG129_IN_SEL_M  (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S)
+#define GPIO_SIG129_IN_SEL_V  0x00000001U
+#define GPIO_SIG129_IN_SEL_S  9
+
+/** GPIO_FUNC130_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 130
+ */
+#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc)
+/** GPIO_FUNC130_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 130.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC130_IN_SEL    0x000000FFU
+#define GPIO_FUNC130_IN_SEL_M  (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S)
+#define GPIO_FUNC130_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC130_IN_SEL_S  0
+/** GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC130_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC130_IN_INV_SEL_M  (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S)
+#define GPIO_FUNC130_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC130_IN_INV_SEL_S  8
+/** GPIO_SIG130_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG130_IN_SEL    (BIT(9))
+#define GPIO_SIG130_IN_SEL_M  (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S)
+#define GPIO_SIG130_IN_SEL_V  0x00000001U
+#define GPIO_SIG130_IN_SEL_S  9
+
+/** GPIO_FUNC131_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 131
+ */
+#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500)
+/** GPIO_FUNC131_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 131.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC131_IN_SEL    0x000000FFU
+#define GPIO_FUNC131_IN_SEL_M  (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S)
+#define GPIO_FUNC131_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC131_IN_SEL_S  0
+/** GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC131_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC131_IN_INV_SEL_M  (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S)
+#define GPIO_FUNC131_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC131_IN_INV_SEL_S  8
+/** GPIO_SIG131_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG131_IN_SEL    (BIT(9))
+#define GPIO_SIG131_IN_SEL_M  (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S)
+#define GPIO_SIG131_IN_SEL_V  0x00000001U
+#define GPIO_SIG131_IN_SEL_S  9
+
+/** GPIO_FUNC132_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 132
+ */
+#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504)
+/** GPIO_FUNC132_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 132.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC132_IN_SEL    0x000000FFU
+#define GPIO_FUNC132_IN_SEL_M  (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S)
+#define GPIO_FUNC132_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC132_IN_SEL_S  0
+/** GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC132_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC132_IN_INV_SEL_M  (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S)
+#define GPIO_FUNC132_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC132_IN_INV_SEL_S  8
+/** GPIO_SIG132_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG132_IN_SEL    (BIT(9))
+#define GPIO_SIG132_IN_SEL_M  (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S)
+#define GPIO_SIG132_IN_SEL_V  0x00000001U
+#define GPIO_SIG132_IN_SEL_S  9
+
+/** GPIO_FUNC133_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 133
+ */
+#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508)
+/** GPIO_FUNC133_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 133.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC133_IN_SEL    0x000000FFU
+#define GPIO_FUNC133_IN_SEL_M  (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S)
+#define GPIO_FUNC133_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC133_IN_SEL_S  0
+/** GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC133_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC133_IN_INV_SEL_M  (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S)
+#define GPIO_FUNC133_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC133_IN_INV_SEL_S  8
+/** GPIO_SIG133_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG133_IN_SEL    (BIT(9))
+#define GPIO_SIG133_IN_SEL_M  (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S)
+#define GPIO_SIG133_IN_SEL_V  0x00000001U
+#define GPIO_SIG133_IN_SEL_S  9
+
+/** GPIO_FUNC134_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 134
+ */
+#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c)
+/** GPIO_FUNC134_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 134.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC134_IN_SEL    0x000000FFU
+#define GPIO_FUNC134_IN_SEL_M  (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S)
+#define GPIO_FUNC134_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC134_IN_SEL_S  0
+/** GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC134_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC134_IN_INV_SEL_M  (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S)
+#define GPIO_FUNC134_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC134_IN_INV_SEL_S  8
+/** GPIO_SIG134_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG134_IN_SEL    (BIT(9))
+#define GPIO_SIG134_IN_SEL_M  (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S)
+#define GPIO_SIG134_IN_SEL_V  0x00000001U
+#define GPIO_SIG134_IN_SEL_S  9
+
+/** GPIO_FUNC135_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 135
+ */
+#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510)
+/** GPIO_FUNC135_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 135.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC135_IN_SEL    0x000000FFU
+#define GPIO_FUNC135_IN_SEL_M  (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S)
+#define GPIO_FUNC135_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC135_IN_SEL_S  0
+/** GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC135_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC135_IN_INV_SEL_M  (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S)
+#define GPIO_FUNC135_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC135_IN_INV_SEL_S  8
+/** GPIO_SIG135_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG135_IN_SEL    (BIT(9))
+#define GPIO_SIG135_IN_SEL_M  (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S)
+#define GPIO_SIG135_IN_SEL_V  0x00000001U
+#define GPIO_SIG135_IN_SEL_S  9
+
+/** GPIO_FUNC137_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 137
+ */
+#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518)
+/** GPIO_FUNC137_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 137.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC137_IN_SEL    0x000000FFU
+#define GPIO_FUNC137_IN_SEL_M  (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S)
+#define GPIO_FUNC137_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC137_IN_SEL_S  0
+/** GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC137_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC137_IN_INV_SEL_M  (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S)
+#define GPIO_FUNC137_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC137_IN_INV_SEL_S  8
+/** GPIO_SIG137_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG137_IN_SEL    (BIT(9))
+#define GPIO_SIG137_IN_SEL_M  (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S)
+#define GPIO_SIG137_IN_SEL_V  0x00000001U
+#define GPIO_SIG137_IN_SEL_S  9
+
+/** GPIO_FUNC138_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 138
+ */
+#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c)
+/** GPIO_FUNC138_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 138.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC138_IN_SEL    0x000000FFU
+#define GPIO_FUNC138_IN_SEL_M  (GPIO_FUNC138_IN_SEL_V << GPIO_FUNC138_IN_SEL_S)
+#define GPIO_FUNC138_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC138_IN_SEL_S  0
+/** GPIO_FUNC138_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC138_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC138_IN_INV_SEL_M  (GPIO_FUNC138_IN_INV_SEL_V << GPIO_FUNC138_IN_INV_SEL_S)
+#define GPIO_FUNC138_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC138_IN_INV_SEL_S  8
+/** GPIO_SIG138_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG138_IN_SEL    (BIT(9))
+#define GPIO_SIG138_IN_SEL_M  (GPIO_SIG138_IN_SEL_V << GPIO_SIG138_IN_SEL_S)
+#define GPIO_SIG138_IN_SEL_V  0x00000001U
+#define GPIO_SIG138_IN_SEL_S  9
+
+/** GPIO_FUNC139_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 139
+ */
+#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520)
+/** GPIO_FUNC139_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 139.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC139_IN_SEL    0x000000FFU
+#define GPIO_FUNC139_IN_SEL_M  (GPIO_FUNC139_IN_SEL_V << GPIO_FUNC139_IN_SEL_S)
+#define GPIO_FUNC139_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC139_IN_SEL_S  0
+/** GPIO_FUNC139_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC139_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC139_IN_INV_SEL_M  (GPIO_FUNC139_IN_INV_SEL_V << GPIO_FUNC139_IN_INV_SEL_S)
+#define GPIO_FUNC139_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC139_IN_INV_SEL_S  8
+/** GPIO_SIG139_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG139_IN_SEL    (BIT(9))
+#define GPIO_SIG139_IN_SEL_M  (GPIO_SIG139_IN_SEL_V << GPIO_SIG139_IN_SEL_S)
+#define GPIO_SIG139_IN_SEL_V  0x00000001U
+#define GPIO_SIG139_IN_SEL_S  9
+
+/** GPIO_FUNC140_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 140
+ */
+#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524)
+/** GPIO_FUNC140_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 140.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC140_IN_SEL    0x000000FFU
+#define GPIO_FUNC140_IN_SEL_M  (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S)
+#define GPIO_FUNC140_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC140_IN_SEL_S  0
+/** GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC140_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC140_IN_INV_SEL_M  (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S)
+#define GPIO_FUNC140_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC140_IN_INV_SEL_S  8
+/** GPIO_SIG140_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG140_IN_SEL    (BIT(9))
+#define GPIO_SIG140_IN_SEL_M  (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S)
+#define GPIO_SIG140_IN_SEL_V  0x00000001U
+#define GPIO_SIG140_IN_SEL_S  9
+
+/** GPIO_FUNC141_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 141
+ */
+#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528)
+/** GPIO_FUNC141_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 141.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC141_IN_SEL    0x000000FFU
+#define GPIO_FUNC141_IN_SEL_M  (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S)
+#define GPIO_FUNC141_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC141_IN_SEL_S  0
+/** GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC141_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC141_IN_INV_SEL_M  (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S)
+#define GPIO_FUNC141_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC141_IN_INV_SEL_S  8
+/** GPIO_SIG141_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG141_IN_SEL    (BIT(9))
+#define GPIO_SIG141_IN_SEL_M  (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S)
+#define GPIO_SIG141_IN_SEL_V  0x00000001U
+#define GPIO_SIG141_IN_SEL_S  9
+
+/** GPIO_FUNC142_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 142
+ */
+#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c)
+/** GPIO_FUNC142_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 142.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC142_IN_SEL    0x000000FFU
+#define GPIO_FUNC142_IN_SEL_M  (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S)
+#define GPIO_FUNC142_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC142_IN_SEL_S  0
+/** GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC142_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC142_IN_INV_SEL_M  (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S)
+#define GPIO_FUNC142_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC142_IN_INV_SEL_S  8
+/** GPIO_SIG142_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG142_IN_SEL    (BIT(9))
+#define GPIO_SIG142_IN_SEL_M  (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S)
+#define GPIO_SIG142_IN_SEL_V  0x00000001U
+#define GPIO_SIG142_IN_SEL_S  9
+
+/** GPIO_FUNC143_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 143
+ */
+#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530)
+/** GPIO_FUNC143_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 143.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC143_IN_SEL    0x000000FFU
+#define GPIO_FUNC143_IN_SEL_M  (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S)
+#define GPIO_FUNC143_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC143_IN_SEL_S  0
+/** GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC143_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC143_IN_INV_SEL_M  (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S)
+#define GPIO_FUNC143_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC143_IN_INV_SEL_S  8
+/** GPIO_SIG143_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG143_IN_SEL    (BIT(9))
+#define GPIO_SIG143_IN_SEL_M  (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S)
+#define GPIO_SIG143_IN_SEL_V  0x00000001U
+#define GPIO_SIG143_IN_SEL_S  9
+
+/** GPIO_FUNC144_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 144
+ */
+#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534)
+/** GPIO_FUNC144_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 144.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC144_IN_SEL    0x000000FFU
+#define GPIO_FUNC144_IN_SEL_M  (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S)
+#define GPIO_FUNC144_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC144_IN_SEL_S  0
+/** GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC144_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC144_IN_INV_SEL_M  (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S)
+#define GPIO_FUNC144_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC144_IN_INV_SEL_S  8
+/** GPIO_SIG144_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG144_IN_SEL    (BIT(9))
+#define GPIO_SIG144_IN_SEL_M  (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S)
+#define GPIO_SIG144_IN_SEL_V  0x00000001U
+#define GPIO_SIG144_IN_SEL_S  9
+
+/** GPIO_FUNC145_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 145
+ */
+#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538)
+/** GPIO_FUNC145_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 145.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC145_IN_SEL    0x000000FFU
+#define GPIO_FUNC145_IN_SEL_M  (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S)
+#define GPIO_FUNC145_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC145_IN_SEL_S  0
+/** GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC145_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC145_IN_INV_SEL_M  (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S)
+#define GPIO_FUNC145_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC145_IN_INV_SEL_S  8
+/** GPIO_SIG145_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG145_IN_SEL    (BIT(9))
+#define GPIO_SIG145_IN_SEL_M  (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S)
+#define GPIO_SIG145_IN_SEL_V  0x00000001U
+#define GPIO_SIG145_IN_SEL_S  9
+
+/** GPIO_FUNC146_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 146
+ */
+#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c)
+/** GPIO_FUNC146_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 146.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC146_IN_SEL    0x000000FFU
+#define GPIO_FUNC146_IN_SEL_M  (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S)
+#define GPIO_FUNC146_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC146_IN_SEL_S  0
+/** GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC146_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC146_IN_INV_SEL_M  (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S)
+#define GPIO_FUNC146_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC146_IN_INV_SEL_S  8
+/** GPIO_SIG146_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG146_IN_SEL    (BIT(9))
+#define GPIO_SIG146_IN_SEL_M  (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S)
+#define GPIO_SIG146_IN_SEL_V  0x00000001U
+#define GPIO_SIG146_IN_SEL_S  9
+
+/** GPIO_FUNC147_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 147
+ */
+#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540)
+/** GPIO_FUNC147_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 147.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC147_IN_SEL    0x000000FFU
+#define GPIO_FUNC147_IN_SEL_M  (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S)
+#define GPIO_FUNC147_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC147_IN_SEL_S  0
+/** GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC147_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC147_IN_INV_SEL_M  (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S)
+#define GPIO_FUNC147_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC147_IN_INV_SEL_S  8
+/** GPIO_SIG147_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG147_IN_SEL    (BIT(9))
+#define GPIO_SIG147_IN_SEL_M  (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S)
+#define GPIO_SIG147_IN_SEL_V  0x00000001U
+#define GPIO_SIG147_IN_SEL_S  9
+
+/** GPIO_FUNC148_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 148
+ */
+#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544)
+/** GPIO_FUNC148_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 148.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC148_IN_SEL    0x000000FFU
+#define GPIO_FUNC148_IN_SEL_M  (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S)
+#define GPIO_FUNC148_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC148_IN_SEL_S  0
+/** GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC148_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC148_IN_INV_SEL_M  (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S)
+#define GPIO_FUNC148_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC148_IN_INV_SEL_S  8
+/** GPIO_SIG148_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG148_IN_SEL    (BIT(9))
+#define GPIO_SIG148_IN_SEL_M  (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S)
+#define GPIO_SIG148_IN_SEL_V  0x00000001U
+#define GPIO_SIG148_IN_SEL_S  9
+
+/** GPIO_FUNC149_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 149
+ */
+#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548)
+/** GPIO_FUNC149_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 149.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC149_IN_SEL    0x000000FFU
+#define GPIO_FUNC149_IN_SEL_M  (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S)
+#define GPIO_FUNC149_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC149_IN_SEL_S  0
+/** GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC149_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC149_IN_INV_SEL_M  (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S)
+#define GPIO_FUNC149_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC149_IN_INV_SEL_S  8
+/** GPIO_SIG149_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG149_IN_SEL    (BIT(9))
+#define GPIO_SIG149_IN_SEL_M  (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S)
+#define GPIO_SIG149_IN_SEL_V  0x00000001U
+#define GPIO_SIG149_IN_SEL_S  9
+
+/** GPIO_FUNC150_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 150
+ */
+#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c)
+/** GPIO_FUNC150_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 150.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC150_IN_SEL    0x000000FFU
+#define GPIO_FUNC150_IN_SEL_M  (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S)
+#define GPIO_FUNC150_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC150_IN_SEL_S  0
+/** GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC150_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC150_IN_INV_SEL_M  (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S)
+#define GPIO_FUNC150_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC150_IN_INV_SEL_S  8
+/** GPIO_SIG150_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG150_IN_SEL    (BIT(9))
+#define GPIO_SIG150_IN_SEL_M  (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S)
+#define GPIO_SIG150_IN_SEL_V  0x00000001U
+#define GPIO_SIG150_IN_SEL_S  9
+
+/** GPIO_FUNC151_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 151
+ */
+#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550)
+/** GPIO_FUNC151_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 151.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC151_IN_SEL    0x000000FFU
+#define GPIO_FUNC151_IN_SEL_M  (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S)
+#define GPIO_FUNC151_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC151_IN_SEL_S  0
+/** GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC151_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC151_IN_INV_SEL_M  (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S)
+#define GPIO_FUNC151_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC151_IN_INV_SEL_S  8
+/** GPIO_SIG151_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG151_IN_SEL    (BIT(9))
+#define GPIO_SIG151_IN_SEL_M  (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S)
+#define GPIO_SIG151_IN_SEL_V  0x00000001U
+#define GPIO_SIG151_IN_SEL_S  9
+
+/** GPIO_FUNC152_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 152
+ */
+#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554)
+/** GPIO_FUNC152_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 152.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC152_IN_SEL    0x000000FFU
+#define GPIO_FUNC152_IN_SEL_M  (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S)
+#define GPIO_FUNC152_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC152_IN_SEL_S  0
+/** GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC152_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC152_IN_INV_SEL_M  (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S)
+#define GPIO_FUNC152_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC152_IN_INV_SEL_S  8
+/** GPIO_SIG152_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG152_IN_SEL    (BIT(9))
+#define GPIO_SIG152_IN_SEL_M  (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S)
+#define GPIO_SIG152_IN_SEL_V  0x00000001U
+#define GPIO_SIG152_IN_SEL_S  9
+
+/** GPIO_FUNC153_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 153
+ */
+#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558)
+/** GPIO_FUNC153_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 153.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC153_IN_SEL    0x000000FFU
+#define GPIO_FUNC153_IN_SEL_M  (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S)
+#define GPIO_FUNC153_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC153_IN_SEL_S  0
+/** GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC153_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC153_IN_INV_SEL_M  (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S)
+#define GPIO_FUNC153_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC153_IN_INV_SEL_S  8
+/** GPIO_SIG153_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG153_IN_SEL    (BIT(9))
+#define GPIO_SIG153_IN_SEL_M  (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S)
+#define GPIO_SIG153_IN_SEL_V  0x00000001U
+#define GPIO_SIG153_IN_SEL_S  9
+
+/** GPIO_FUNC154_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 154
+ */
+#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c)
+/** GPIO_FUNC154_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 154.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC154_IN_SEL    0x000000FFU
+#define GPIO_FUNC154_IN_SEL_M  (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S)
+#define GPIO_FUNC154_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC154_IN_SEL_S  0
+/** GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC154_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC154_IN_INV_SEL_M  (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S)
+#define GPIO_FUNC154_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC154_IN_INV_SEL_S  8
+/** GPIO_SIG154_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG154_IN_SEL    (BIT(9))
+#define GPIO_SIG154_IN_SEL_M  (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S)
+#define GPIO_SIG154_IN_SEL_V  0x00000001U
+#define GPIO_SIG154_IN_SEL_S  9
+
+/** GPIO_FUNC155_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 155
+ */
+#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560)
+/** GPIO_FUNC155_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 155.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC155_IN_SEL    0x000000FFU
+#define GPIO_FUNC155_IN_SEL_M  (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S)
+#define GPIO_FUNC155_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC155_IN_SEL_S  0
+/** GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC155_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC155_IN_INV_SEL_M  (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S)
+#define GPIO_FUNC155_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC155_IN_INV_SEL_S  8
+/** GPIO_SIG155_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG155_IN_SEL    (BIT(9))
+#define GPIO_SIG155_IN_SEL_M  (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S)
+#define GPIO_SIG155_IN_SEL_V  0x00000001U
+#define GPIO_SIG155_IN_SEL_S  9
+
+/** GPIO_FUNC156_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 156
+ */
+#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564)
+/** GPIO_FUNC156_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 156.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC156_IN_SEL    0x000000FFU
+#define GPIO_FUNC156_IN_SEL_M  (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S)
+#define GPIO_FUNC156_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC156_IN_SEL_S  0
+/** GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC156_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC156_IN_INV_SEL_M  (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S)
+#define GPIO_FUNC156_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC156_IN_INV_SEL_S  8
+/** GPIO_SIG156_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG156_IN_SEL    (BIT(9))
+#define GPIO_SIG156_IN_SEL_M  (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S)
+#define GPIO_SIG156_IN_SEL_V  0x00000001U
+#define GPIO_SIG156_IN_SEL_S  9
+
+/** GPIO_FUNC158_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 158
+ */
+#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c)
+/** GPIO_FUNC158_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 158.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC158_IN_SEL    0x000000FFU
+#define GPIO_FUNC158_IN_SEL_M  (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S)
+#define GPIO_FUNC158_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC158_IN_SEL_S  0
+/** GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC158_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC158_IN_INV_SEL_M  (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S)
+#define GPIO_FUNC158_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC158_IN_INV_SEL_S  8
+/** GPIO_SIG158_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG158_IN_SEL    (BIT(9))
+#define GPIO_SIG158_IN_SEL_M  (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S)
+#define GPIO_SIG158_IN_SEL_V  0x00000001U
+#define GPIO_SIG158_IN_SEL_S  9
+
+/** GPIO_FUNC159_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 159
+ */
+#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570)
+/** GPIO_FUNC159_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 159.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC159_IN_SEL    0x000000FFU
+#define GPIO_FUNC159_IN_SEL_M  (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S)
+#define GPIO_FUNC159_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC159_IN_SEL_S  0
+/** GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC159_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC159_IN_INV_SEL_M  (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S)
+#define GPIO_FUNC159_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC159_IN_INV_SEL_S  8
+/** GPIO_SIG159_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG159_IN_SEL    (BIT(9))
+#define GPIO_SIG159_IN_SEL_M  (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S)
+#define GPIO_SIG159_IN_SEL_V  0x00000001U
+#define GPIO_SIG159_IN_SEL_S  9
+
+/** GPIO_FUNC160_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 160
+ */
+#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574)
+/** GPIO_FUNC160_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 160.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC160_IN_SEL    0x000000FFU
+#define GPIO_FUNC160_IN_SEL_M  (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S)
+#define GPIO_FUNC160_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC160_IN_SEL_S  0
+/** GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC160_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC160_IN_INV_SEL_M  (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S)
+#define GPIO_FUNC160_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC160_IN_INV_SEL_S  8
+/** GPIO_SIG160_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG160_IN_SEL    (BIT(9))
+#define GPIO_SIG160_IN_SEL_M  (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S)
+#define GPIO_SIG160_IN_SEL_V  0x00000001U
+#define GPIO_SIG160_IN_SEL_S  9
+
+/** GPIO_FUNC161_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 161
+ */
+#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578)
+/** GPIO_FUNC161_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 161.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC161_IN_SEL    0x000000FFU
+#define GPIO_FUNC161_IN_SEL_M  (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S)
+#define GPIO_FUNC161_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC161_IN_SEL_S  0
+/** GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC161_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC161_IN_INV_SEL_M  (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S)
+#define GPIO_FUNC161_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC161_IN_INV_SEL_S  8
+/** GPIO_SIG161_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG161_IN_SEL    (BIT(9))
+#define GPIO_SIG161_IN_SEL_M  (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S)
+#define GPIO_SIG161_IN_SEL_V  0x00000001U
+#define GPIO_SIG161_IN_SEL_S  9
+
+/** GPIO_FUNC162_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 162
+ */
+#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c)
+/** GPIO_FUNC162_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 162.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC162_IN_SEL    0x000000FFU
+#define GPIO_FUNC162_IN_SEL_M  (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S)
+#define GPIO_FUNC162_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC162_IN_SEL_S  0
+/** GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC162_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC162_IN_INV_SEL_M  (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S)
+#define GPIO_FUNC162_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC162_IN_INV_SEL_S  8
+/** GPIO_SIG162_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG162_IN_SEL    (BIT(9))
+#define GPIO_SIG162_IN_SEL_M  (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S)
+#define GPIO_SIG162_IN_SEL_V  0x00000001U
+#define GPIO_SIG162_IN_SEL_S  9
+
+/** GPIO_FUNC163_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 163
+ */
+#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580)
+/** GPIO_FUNC163_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 163.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC163_IN_SEL    0x000000FFU
+#define GPIO_FUNC163_IN_SEL_M  (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S)
+#define GPIO_FUNC163_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC163_IN_SEL_S  0
+/** GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC163_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC163_IN_INV_SEL_M  (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S)
+#define GPIO_FUNC163_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC163_IN_INV_SEL_S  8
+/** GPIO_SIG163_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG163_IN_SEL    (BIT(9))
+#define GPIO_SIG163_IN_SEL_M  (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S)
+#define GPIO_SIG163_IN_SEL_V  0x00000001U
+#define GPIO_SIG163_IN_SEL_S  9
+
+/** GPIO_FUNC164_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 164
+ */
+#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584)
+/** GPIO_FUNC164_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 164.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC164_IN_SEL    0x000000FFU
+#define GPIO_FUNC164_IN_SEL_M  (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S)
+#define GPIO_FUNC164_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC164_IN_SEL_S  0
+/** GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC164_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC164_IN_INV_SEL_M  (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S)
+#define GPIO_FUNC164_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC164_IN_INV_SEL_S  8
+/** GPIO_SIG164_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG164_IN_SEL    (BIT(9))
+#define GPIO_SIG164_IN_SEL_M  (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S)
+#define GPIO_SIG164_IN_SEL_V  0x00000001U
+#define GPIO_SIG164_IN_SEL_S  9
+
+/** GPIO_FUNC165_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 165
+ */
+#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588)
+/** GPIO_FUNC165_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 165.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC165_IN_SEL    0x000000FFU
+#define GPIO_FUNC165_IN_SEL_M  (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S)
+#define GPIO_FUNC165_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC165_IN_SEL_S  0
+/** GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC165_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC165_IN_INV_SEL_M  (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S)
+#define GPIO_FUNC165_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC165_IN_INV_SEL_S  8
+/** GPIO_SIG165_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG165_IN_SEL    (BIT(9))
+#define GPIO_SIG165_IN_SEL_M  (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S)
+#define GPIO_SIG165_IN_SEL_V  0x00000001U
+#define GPIO_SIG165_IN_SEL_S  9
+
+/** GPIO_FUNC166_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 166
+ */
+#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c)
+/** GPIO_FUNC166_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 166.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC166_IN_SEL    0x000000FFU
+#define GPIO_FUNC166_IN_SEL_M  (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S)
+#define GPIO_FUNC166_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC166_IN_SEL_S  0
+/** GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC166_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC166_IN_INV_SEL_M  (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S)
+#define GPIO_FUNC166_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC166_IN_INV_SEL_S  8
+/** GPIO_SIG166_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG166_IN_SEL    (BIT(9))
+#define GPIO_SIG166_IN_SEL_M  (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S)
+#define GPIO_SIG166_IN_SEL_V  0x00000001U
+#define GPIO_SIG166_IN_SEL_S  9
+
+/** GPIO_FUNC167_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 167
+ */
+#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590)
+/** GPIO_FUNC167_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 167.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC167_IN_SEL    0x000000FFU
+#define GPIO_FUNC167_IN_SEL_M  (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S)
+#define GPIO_FUNC167_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC167_IN_SEL_S  0
+/** GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC167_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC167_IN_INV_SEL_M  (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S)
+#define GPIO_FUNC167_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC167_IN_INV_SEL_S  8
+/** GPIO_SIG167_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG167_IN_SEL    (BIT(9))
+#define GPIO_SIG167_IN_SEL_M  (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S)
+#define GPIO_SIG167_IN_SEL_V  0x00000001U
+#define GPIO_SIG167_IN_SEL_S  9
+
+/** GPIO_FUNC168_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 168
+ */
+#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594)
+/** GPIO_FUNC168_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 168.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC168_IN_SEL    0x000000FFU
+#define GPIO_FUNC168_IN_SEL_M  (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S)
+#define GPIO_FUNC168_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC168_IN_SEL_S  0
+/** GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC168_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC168_IN_INV_SEL_M  (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S)
+#define GPIO_FUNC168_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC168_IN_INV_SEL_S  8
+/** GPIO_SIG168_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG168_IN_SEL    (BIT(9))
+#define GPIO_SIG168_IN_SEL_M  (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S)
+#define GPIO_SIG168_IN_SEL_V  0x00000001U
+#define GPIO_SIG168_IN_SEL_S  9
+
+/** GPIO_FUNC169_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 169
+ */
+#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598)
+/** GPIO_FUNC169_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 169.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC169_IN_SEL    0x000000FFU
+#define GPIO_FUNC169_IN_SEL_M  (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S)
+#define GPIO_FUNC169_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC169_IN_SEL_S  0
+/** GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC169_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC169_IN_INV_SEL_M  (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S)
+#define GPIO_FUNC169_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC169_IN_INV_SEL_S  8
+/** GPIO_SIG169_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG169_IN_SEL    (BIT(9))
+#define GPIO_SIG169_IN_SEL_M  (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S)
+#define GPIO_SIG169_IN_SEL_V  0x00000001U
+#define GPIO_SIG169_IN_SEL_S  9
+
+/** GPIO_FUNC170_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 170
+ */
+#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c)
+/** GPIO_FUNC170_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 170.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC170_IN_SEL    0x000000FFU
+#define GPIO_FUNC170_IN_SEL_M  (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S)
+#define GPIO_FUNC170_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC170_IN_SEL_S  0
+/** GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC170_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC170_IN_INV_SEL_M  (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S)
+#define GPIO_FUNC170_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC170_IN_INV_SEL_S  8
+/** GPIO_SIG170_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG170_IN_SEL    (BIT(9))
+#define GPIO_SIG170_IN_SEL_M  (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S)
+#define GPIO_SIG170_IN_SEL_V  0x00000001U
+#define GPIO_SIG170_IN_SEL_S  9
+
+/** GPIO_FUNC171_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 171
+ */
+#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0)
+/** GPIO_FUNC171_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 171.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC171_IN_SEL    0x000000FFU
+#define GPIO_FUNC171_IN_SEL_M  (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S)
+#define GPIO_FUNC171_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC171_IN_SEL_S  0
+/** GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC171_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC171_IN_INV_SEL_M  (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S)
+#define GPIO_FUNC171_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC171_IN_INV_SEL_S  8
+/** GPIO_SIG171_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG171_IN_SEL    (BIT(9))
+#define GPIO_SIG171_IN_SEL_M  (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S)
+#define GPIO_SIG171_IN_SEL_V  0x00000001U
+#define GPIO_SIG171_IN_SEL_S  9
+
+/** GPIO_FUNC172_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 172
+ */
+#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4)
+/** GPIO_FUNC172_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 172.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC172_IN_SEL    0x000000FFU
+#define GPIO_FUNC172_IN_SEL_M  (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S)
+#define GPIO_FUNC172_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC172_IN_SEL_S  0
+/** GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC172_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC172_IN_INV_SEL_M  (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S)
+#define GPIO_FUNC172_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC172_IN_INV_SEL_S  8
+/** GPIO_SIG172_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG172_IN_SEL    (BIT(9))
+#define GPIO_SIG172_IN_SEL_M  (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S)
+#define GPIO_SIG172_IN_SEL_V  0x00000001U
+#define GPIO_SIG172_IN_SEL_S  9
+
+/** GPIO_FUNC173_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 173
+ */
+#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8)
+/** GPIO_FUNC173_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 173.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC173_IN_SEL    0x000000FFU
+#define GPIO_FUNC173_IN_SEL_M  (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S)
+#define GPIO_FUNC173_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC173_IN_SEL_S  0
+/** GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC173_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC173_IN_INV_SEL_M  (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S)
+#define GPIO_FUNC173_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC173_IN_INV_SEL_S  8
+/** GPIO_SIG173_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG173_IN_SEL    (BIT(9))
+#define GPIO_SIG173_IN_SEL_M  (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S)
+#define GPIO_SIG173_IN_SEL_V  0x00000001U
+#define GPIO_SIG173_IN_SEL_S  9
+
+/** GPIO_FUNC174_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 174
+ */
+#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac)
+/** GPIO_FUNC174_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 174.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC174_IN_SEL    0x000000FFU
+#define GPIO_FUNC174_IN_SEL_M  (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S)
+#define GPIO_FUNC174_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC174_IN_SEL_S  0
+/** GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC174_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC174_IN_INV_SEL_M  (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S)
+#define GPIO_FUNC174_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC174_IN_INV_SEL_S  8
+/** GPIO_SIG174_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG174_IN_SEL    (BIT(9))
+#define GPIO_SIG174_IN_SEL_M  (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S)
+#define GPIO_SIG174_IN_SEL_V  0x00000001U
+#define GPIO_SIG174_IN_SEL_S  9
+
+/** GPIO_FUNC175_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 175
+ */
+#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0)
+/** GPIO_FUNC175_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 175.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC175_IN_SEL    0x000000FFU
+#define GPIO_FUNC175_IN_SEL_M  (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S)
+#define GPIO_FUNC175_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC175_IN_SEL_S  0
+/** GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC175_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC175_IN_INV_SEL_M  (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S)
+#define GPIO_FUNC175_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC175_IN_INV_SEL_S  8
+/** GPIO_SIG175_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG175_IN_SEL    (BIT(9))
+#define GPIO_SIG175_IN_SEL_M  (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S)
+#define GPIO_SIG175_IN_SEL_V  0x00000001U
+#define GPIO_SIG175_IN_SEL_S  9
+
+/** GPIO_FUNC176_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 176
+ */
+#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4)
+/** GPIO_FUNC176_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 176.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC176_IN_SEL    0x000000FFU
+#define GPIO_FUNC176_IN_SEL_M  (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S)
+#define GPIO_FUNC176_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC176_IN_SEL_S  0
+/** GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC176_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC176_IN_INV_SEL_M  (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S)
+#define GPIO_FUNC176_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC176_IN_INV_SEL_S  8
+/** GPIO_SIG176_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG176_IN_SEL    (BIT(9))
+#define GPIO_SIG176_IN_SEL_M  (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S)
+#define GPIO_SIG176_IN_SEL_V  0x00000001U
+#define GPIO_SIG176_IN_SEL_S  9
+
+/** GPIO_FUNC177_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 177
+ */
+#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8)
+/** GPIO_FUNC177_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 177.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC177_IN_SEL    0x000000FFU
+#define GPIO_FUNC177_IN_SEL_M  (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S)
+#define GPIO_FUNC177_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC177_IN_SEL_S  0
+/** GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC177_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC177_IN_INV_SEL_M  (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S)
+#define GPIO_FUNC177_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC177_IN_INV_SEL_S  8
+/** GPIO_SIG177_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG177_IN_SEL    (BIT(9))
+#define GPIO_SIG177_IN_SEL_M  (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S)
+#define GPIO_SIG177_IN_SEL_V  0x00000001U
+#define GPIO_SIG177_IN_SEL_S  9
+
+/** GPIO_FUNC178_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 178
+ */
+#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc)
+/** GPIO_FUNC178_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 178.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC178_IN_SEL    0x000000FFU
+#define GPIO_FUNC178_IN_SEL_M  (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S)
+#define GPIO_FUNC178_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC178_IN_SEL_S  0
+/** GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC178_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC178_IN_INV_SEL_M  (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S)
+#define GPIO_FUNC178_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC178_IN_INV_SEL_S  8
+/** GPIO_SIG178_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG178_IN_SEL    (BIT(9))
+#define GPIO_SIG178_IN_SEL_M  (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S)
+#define GPIO_SIG178_IN_SEL_V  0x00000001U
+#define GPIO_SIG178_IN_SEL_S  9
+
+/** GPIO_FUNC179_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 179
+ */
+#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0)
+/** GPIO_FUNC179_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 179.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC179_IN_SEL    0x000000FFU
+#define GPIO_FUNC179_IN_SEL_M  (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S)
+#define GPIO_FUNC179_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC179_IN_SEL_S  0
+/** GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC179_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC179_IN_INV_SEL_M  (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S)
+#define GPIO_FUNC179_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC179_IN_INV_SEL_S  8
+/** GPIO_SIG179_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG179_IN_SEL    (BIT(9))
+#define GPIO_SIG179_IN_SEL_M  (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S)
+#define GPIO_SIG179_IN_SEL_V  0x00000001U
+#define GPIO_SIG179_IN_SEL_S  9
+
+/** GPIO_FUNC180_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 180
+ */
+#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4)
+/** GPIO_FUNC180_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 180.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC180_IN_SEL    0x000000FFU
+#define GPIO_FUNC180_IN_SEL_M  (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S)
+#define GPIO_FUNC180_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC180_IN_SEL_S  0
+/** GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC180_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC180_IN_INV_SEL_M  (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S)
+#define GPIO_FUNC180_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC180_IN_INV_SEL_S  8
+/** GPIO_SIG180_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG180_IN_SEL    (BIT(9))
+#define GPIO_SIG180_IN_SEL_M  (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S)
+#define GPIO_SIG180_IN_SEL_V  0x00000001U
+#define GPIO_SIG180_IN_SEL_S  9
+
+/** GPIO_FUNC181_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 181
+ */
+#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8)
+/** GPIO_FUNC181_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 181.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC181_IN_SEL    0x000000FFU
+#define GPIO_FUNC181_IN_SEL_M  (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S)
+#define GPIO_FUNC181_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC181_IN_SEL_S  0
+/** GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC181_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC181_IN_INV_SEL_M  (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S)
+#define GPIO_FUNC181_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC181_IN_INV_SEL_S  8
+/** GPIO_SIG181_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG181_IN_SEL    (BIT(9))
+#define GPIO_SIG181_IN_SEL_M  (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S)
+#define GPIO_SIG181_IN_SEL_V  0x00000001U
+#define GPIO_SIG181_IN_SEL_S  9
+
+/** GPIO_FUNC182_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 182
+ */
+#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc)
+/** GPIO_FUNC182_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 182.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC182_IN_SEL    0x000000FFU
+#define GPIO_FUNC182_IN_SEL_M  (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S)
+#define GPIO_FUNC182_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC182_IN_SEL_S  0
+/** GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC182_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC182_IN_INV_SEL_M  (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S)
+#define GPIO_FUNC182_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC182_IN_INV_SEL_S  8
+/** GPIO_SIG182_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG182_IN_SEL    (BIT(9))
+#define GPIO_SIG182_IN_SEL_M  (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S)
+#define GPIO_SIG182_IN_SEL_V  0x00000001U
+#define GPIO_SIG182_IN_SEL_S  9
+
+/** GPIO_FUNC183_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 183
+ */
+#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0)
+/** GPIO_FUNC183_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 183.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC183_IN_SEL    0x000000FFU
+#define GPIO_FUNC183_IN_SEL_M  (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S)
+#define GPIO_FUNC183_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC183_IN_SEL_S  0
+/** GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC183_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC183_IN_INV_SEL_M  (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S)
+#define GPIO_FUNC183_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC183_IN_INV_SEL_S  8
+/** GPIO_SIG183_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG183_IN_SEL    (BIT(9))
+#define GPIO_SIG183_IN_SEL_M  (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S)
+#define GPIO_SIG183_IN_SEL_V  0x00000001U
+#define GPIO_SIG183_IN_SEL_S  9
+
+/** GPIO_FUNC184_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 184
+ */
+#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4)
+/** GPIO_FUNC184_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 184.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC184_IN_SEL    0x000000FFU
+#define GPIO_FUNC184_IN_SEL_M  (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S)
+#define GPIO_FUNC184_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC184_IN_SEL_S  0
+/** GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC184_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC184_IN_INV_SEL_M  (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S)
+#define GPIO_FUNC184_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC184_IN_INV_SEL_S  8
+/** GPIO_SIG184_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG184_IN_SEL    (BIT(9))
+#define GPIO_SIG184_IN_SEL_M  (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S)
+#define GPIO_SIG184_IN_SEL_V  0x00000001U
+#define GPIO_SIG184_IN_SEL_S  9
+
+/** GPIO_FUNC185_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 185
+ */
+#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8)
+/** GPIO_FUNC185_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 185.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC185_IN_SEL    0x000000FFU
+#define GPIO_FUNC185_IN_SEL_M  (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S)
+#define GPIO_FUNC185_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC185_IN_SEL_S  0
+/** GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC185_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC185_IN_INV_SEL_M  (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S)
+#define GPIO_FUNC185_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC185_IN_INV_SEL_S  8
+/** GPIO_SIG185_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG185_IN_SEL    (BIT(9))
+#define GPIO_SIG185_IN_SEL_M  (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S)
+#define GPIO_SIG185_IN_SEL_V  0x00000001U
+#define GPIO_SIG185_IN_SEL_S  9
+
+/** GPIO_FUNC186_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 186
+ */
+#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc)
+/** GPIO_FUNC186_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 186.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC186_IN_SEL    0x000000FFU
+#define GPIO_FUNC186_IN_SEL_M  (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S)
+#define GPIO_FUNC186_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC186_IN_SEL_S  0
+/** GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC186_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC186_IN_INV_SEL_M  (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S)
+#define GPIO_FUNC186_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC186_IN_INV_SEL_S  8
+/** GPIO_SIG186_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG186_IN_SEL    (BIT(9))
+#define GPIO_SIG186_IN_SEL_M  (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S)
+#define GPIO_SIG186_IN_SEL_V  0x00000001U
+#define GPIO_SIG186_IN_SEL_S  9
+
+/** GPIO_FUNC187_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 187
+ */
+#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0)
+/** GPIO_FUNC187_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 187.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC187_IN_SEL    0x000000FFU
+#define GPIO_FUNC187_IN_SEL_M  (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S)
+#define GPIO_FUNC187_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC187_IN_SEL_S  0
+/** GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC187_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC187_IN_INV_SEL_M  (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S)
+#define GPIO_FUNC187_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC187_IN_INV_SEL_S  8
+/** GPIO_SIG187_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG187_IN_SEL    (BIT(9))
+#define GPIO_SIG187_IN_SEL_M  (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S)
+#define GPIO_SIG187_IN_SEL_V  0x00000001U
+#define GPIO_SIG187_IN_SEL_S  9
+
+/** GPIO_FUNC188_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 188
+ */
+#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4)
+/** GPIO_FUNC188_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 188.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC188_IN_SEL    0x000000FFU
+#define GPIO_FUNC188_IN_SEL_M  (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S)
+#define GPIO_FUNC188_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC188_IN_SEL_S  0
+/** GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC188_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC188_IN_INV_SEL_M  (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S)
+#define GPIO_FUNC188_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC188_IN_INV_SEL_S  8
+/** GPIO_SIG188_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG188_IN_SEL    (BIT(9))
+#define GPIO_SIG188_IN_SEL_M  (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S)
+#define GPIO_SIG188_IN_SEL_V  0x00000001U
+#define GPIO_SIG188_IN_SEL_S  9
+
+/** GPIO_FUNC189_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 189
+ */
+#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8)
+/** GPIO_FUNC189_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 189.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC189_IN_SEL    0x000000FFU
+#define GPIO_FUNC189_IN_SEL_M  (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S)
+#define GPIO_FUNC189_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC189_IN_SEL_S  0
+/** GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC189_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC189_IN_INV_SEL_M  (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S)
+#define GPIO_FUNC189_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC189_IN_INV_SEL_S  8
+/** GPIO_SIG189_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG189_IN_SEL    (BIT(9))
+#define GPIO_SIG189_IN_SEL_M  (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S)
+#define GPIO_SIG189_IN_SEL_V  0x00000001U
+#define GPIO_SIG189_IN_SEL_S  9
+
+/** GPIO_FUNC190_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 190
+ */
+#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec)
+/** GPIO_FUNC190_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 190.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC190_IN_SEL    0x000000FFU
+#define GPIO_FUNC190_IN_SEL_M  (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S)
+#define GPIO_FUNC190_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC190_IN_SEL_S  0
+/** GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC190_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC190_IN_INV_SEL_M  (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S)
+#define GPIO_FUNC190_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC190_IN_INV_SEL_S  8
+/** GPIO_SIG190_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG190_IN_SEL    (BIT(9))
+#define GPIO_SIG190_IN_SEL_M  (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S)
+#define GPIO_SIG190_IN_SEL_V  0x00000001U
+#define GPIO_SIG190_IN_SEL_S  9
+
+/** GPIO_FUNC191_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 191
+ */
+#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0)
+/** GPIO_FUNC191_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 191.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC191_IN_SEL    0x000000FFU
+#define GPIO_FUNC191_IN_SEL_M  (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S)
+#define GPIO_FUNC191_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC191_IN_SEL_S  0
+/** GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC191_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC191_IN_INV_SEL_M  (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S)
+#define GPIO_FUNC191_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC191_IN_INV_SEL_S  8
+/** GPIO_SIG191_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG191_IN_SEL    (BIT(9))
+#define GPIO_SIG191_IN_SEL_M  (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S)
+#define GPIO_SIG191_IN_SEL_V  0x00000001U
+#define GPIO_SIG191_IN_SEL_S  9
+
+/** GPIO_FUNC192_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 192
+ */
+#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4)
+/** GPIO_FUNC192_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 192.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC192_IN_SEL    0x000000FFU
+#define GPIO_FUNC192_IN_SEL_M  (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S)
+#define GPIO_FUNC192_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC192_IN_SEL_S  0
+/** GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC192_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC192_IN_INV_SEL_M  (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S)
+#define GPIO_FUNC192_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC192_IN_INV_SEL_S  8
+/** GPIO_SIG192_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG192_IN_SEL    (BIT(9))
+#define GPIO_SIG192_IN_SEL_M  (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S)
+#define GPIO_SIG192_IN_SEL_V  0x00000001U
+#define GPIO_SIG192_IN_SEL_S  9
+
+/** GPIO_FUNC193_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 193
+ */
+#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8)
+/** GPIO_FUNC193_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 193.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC193_IN_SEL    0x000000FFU
+#define GPIO_FUNC193_IN_SEL_M  (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S)
+#define GPIO_FUNC193_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC193_IN_SEL_S  0
+/** GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC193_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC193_IN_INV_SEL_M  (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S)
+#define GPIO_FUNC193_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC193_IN_INV_SEL_S  8
+/** GPIO_SIG193_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG193_IN_SEL    (BIT(9))
+#define GPIO_SIG193_IN_SEL_M  (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S)
+#define GPIO_SIG193_IN_SEL_V  0x00000001U
+#define GPIO_SIG193_IN_SEL_S  9
+
+/** GPIO_FUNC194_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 194
+ */
+#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc)
+/** GPIO_FUNC194_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 194.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC194_IN_SEL    0x000000FFU
+#define GPIO_FUNC194_IN_SEL_M  (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S)
+#define GPIO_FUNC194_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC194_IN_SEL_S  0
+/** GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC194_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC194_IN_INV_SEL_M  (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S)
+#define GPIO_FUNC194_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC194_IN_INV_SEL_S  8
+/** GPIO_SIG194_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG194_IN_SEL    (BIT(9))
+#define GPIO_SIG194_IN_SEL_M  (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S)
+#define GPIO_SIG194_IN_SEL_V  0x00000001U
+#define GPIO_SIG194_IN_SEL_S  9
+
+/** GPIO_FUNC195_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 195
+ */
+#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600)
+/** GPIO_FUNC195_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 195.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC195_IN_SEL    0x000000FFU
+#define GPIO_FUNC195_IN_SEL_M  (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S)
+#define GPIO_FUNC195_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC195_IN_SEL_S  0
+/** GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC195_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC195_IN_INV_SEL_M  (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S)
+#define GPIO_FUNC195_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC195_IN_INV_SEL_S  8
+/** GPIO_SIG195_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG195_IN_SEL    (BIT(9))
+#define GPIO_SIG195_IN_SEL_M  (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S)
+#define GPIO_SIG195_IN_SEL_V  0x00000001U
+#define GPIO_SIG195_IN_SEL_S  9
+
+/** GPIO_FUNC196_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 196
+ */
+#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604)
+/** GPIO_FUNC196_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 196.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC196_IN_SEL    0x000000FFU
+#define GPIO_FUNC196_IN_SEL_M  (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S)
+#define GPIO_FUNC196_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC196_IN_SEL_S  0
+/** GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC196_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC196_IN_INV_SEL_M  (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S)
+#define GPIO_FUNC196_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC196_IN_INV_SEL_S  8
+/** GPIO_SIG196_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG196_IN_SEL    (BIT(9))
+#define GPIO_SIG196_IN_SEL_M  (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S)
+#define GPIO_SIG196_IN_SEL_V  0x00000001U
+#define GPIO_SIG196_IN_SEL_S  9
+
+/** GPIO_FUNC197_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 197
+ */
+#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608)
+/** GPIO_FUNC197_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 197.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC197_IN_SEL    0x000000FFU
+#define GPIO_FUNC197_IN_SEL_M  (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S)
+#define GPIO_FUNC197_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC197_IN_SEL_S  0
+/** GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC197_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC197_IN_INV_SEL_M  (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S)
+#define GPIO_FUNC197_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC197_IN_INV_SEL_S  8
+/** GPIO_SIG197_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG197_IN_SEL    (BIT(9))
+#define GPIO_SIG197_IN_SEL_M  (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S)
+#define GPIO_SIG197_IN_SEL_V  0x00000001U
+#define GPIO_SIG197_IN_SEL_S  9
+
+/** GPIO_FUNC198_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 198
+ */
+#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c)
+/** GPIO_FUNC198_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 198.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC198_IN_SEL    0x000000FFU
+#define GPIO_FUNC198_IN_SEL_M  (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S)
+#define GPIO_FUNC198_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC198_IN_SEL_S  0
+/** GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC198_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC198_IN_INV_SEL_M  (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S)
+#define GPIO_FUNC198_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC198_IN_INV_SEL_S  8
+/** GPIO_SIG198_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG198_IN_SEL    (BIT(9))
+#define GPIO_SIG198_IN_SEL_M  (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S)
+#define GPIO_SIG198_IN_SEL_V  0x00000001U
+#define GPIO_SIG198_IN_SEL_S  9
+
+/** GPIO_FUNC199_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 199
+ */
+#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610)
+/** GPIO_FUNC199_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 199.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC199_IN_SEL    0x000000FFU
+#define GPIO_FUNC199_IN_SEL_M  (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S)
+#define GPIO_FUNC199_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC199_IN_SEL_S  0
+/** GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC199_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC199_IN_INV_SEL_M  (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S)
+#define GPIO_FUNC199_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC199_IN_INV_SEL_S  8
+/** GPIO_SIG199_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG199_IN_SEL    (BIT(9))
+#define GPIO_SIG199_IN_SEL_M  (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S)
+#define GPIO_SIG199_IN_SEL_V  0x00000001U
+#define GPIO_SIG199_IN_SEL_S  9
+
+/** GPIO_FUNC200_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 200
+ */
+#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614)
+/** GPIO_FUNC200_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 200.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC200_IN_SEL    0x000000FFU
+#define GPIO_FUNC200_IN_SEL_M  (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S)
+#define GPIO_FUNC200_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC200_IN_SEL_S  0
+/** GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC200_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC200_IN_INV_SEL_M  (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S)
+#define GPIO_FUNC200_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC200_IN_INV_SEL_S  8
+/** GPIO_SIG200_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG200_IN_SEL    (BIT(9))
+#define GPIO_SIG200_IN_SEL_M  (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S)
+#define GPIO_SIG200_IN_SEL_V  0x00000001U
+#define GPIO_SIG200_IN_SEL_S  9
+
+/** GPIO_FUNC201_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 201
+ */
+#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618)
+/** GPIO_FUNC201_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 201.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC201_IN_SEL    0x000000FFU
+#define GPIO_FUNC201_IN_SEL_M  (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S)
+#define GPIO_FUNC201_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC201_IN_SEL_S  0
+/** GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC201_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC201_IN_INV_SEL_M  (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S)
+#define GPIO_FUNC201_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC201_IN_INV_SEL_S  8
+/** GPIO_SIG201_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG201_IN_SEL    (BIT(9))
+#define GPIO_SIG201_IN_SEL_M  (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S)
+#define GPIO_SIG201_IN_SEL_V  0x00000001U
+#define GPIO_SIG201_IN_SEL_S  9
+
+/** GPIO_FUNC202_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 202
+ */
+#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c)
+/** GPIO_FUNC202_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 202.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC202_IN_SEL    0x000000FFU
+#define GPIO_FUNC202_IN_SEL_M  (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S)
+#define GPIO_FUNC202_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC202_IN_SEL_S  0
+/** GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC202_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC202_IN_INV_SEL_M  (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S)
+#define GPIO_FUNC202_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC202_IN_INV_SEL_S  8
+/** GPIO_SIG202_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG202_IN_SEL    (BIT(9))
+#define GPIO_SIG202_IN_SEL_M  (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S)
+#define GPIO_SIG202_IN_SEL_V  0x00000001U
+#define GPIO_SIG202_IN_SEL_S  9
+
+/** GPIO_FUNC203_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 203
+ */
+#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620)
+/** GPIO_FUNC203_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 203.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC203_IN_SEL    0x000000FFU
+#define GPIO_FUNC203_IN_SEL_M  (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S)
+#define GPIO_FUNC203_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC203_IN_SEL_S  0
+/** GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC203_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC203_IN_INV_SEL_M  (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S)
+#define GPIO_FUNC203_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC203_IN_INV_SEL_S  8
+/** GPIO_SIG203_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG203_IN_SEL    (BIT(9))
+#define GPIO_SIG203_IN_SEL_M  (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S)
+#define GPIO_SIG203_IN_SEL_V  0x00000001U
+#define GPIO_SIG203_IN_SEL_S  9
+
+/** GPIO_FUNC204_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 204
+ */
+#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624)
+/** GPIO_FUNC204_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 204.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC204_IN_SEL    0x000000FFU
+#define GPIO_FUNC204_IN_SEL_M  (GPIO_FUNC204_IN_SEL_V << GPIO_FUNC204_IN_SEL_S)
+#define GPIO_FUNC204_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC204_IN_SEL_S  0
+/** GPIO_FUNC204_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC204_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC204_IN_INV_SEL_M  (GPIO_FUNC204_IN_INV_SEL_V << GPIO_FUNC204_IN_INV_SEL_S)
+#define GPIO_FUNC204_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC204_IN_INV_SEL_S  8
+/** GPIO_SIG204_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG204_IN_SEL    (BIT(9))
+#define GPIO_SIG204_IN_SEL_M  (GPIO_SIG204_IN_SEL_V << GPIO_SIG204_IN_SEL_S)
+#define GPIO_SIG204_IN_SEL_V  0x00000001U
+#define GPIO_SIG204_IN_SEL_S  9
+
+/** GPIO_FUNC205_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 205
+ */
+#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628)
+/** GPIO_FUNC205_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 205.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC205_IN_SEL    0x000000FFU
+#define GPIO_FUNC205_IN_SEL_M  (GPIO_FUNC205_IN_SEL_V << GPIO_FUNC205_IN_SEL_S)
+#define GPIO_FUNC205_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC205_IN_SEL_S  0
+/** GPIO_FUNC205_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC205_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC205_IN_INV_SEL_M  (GPIO_FUNC205_IN_INV_SEL_V << GPIO_FUNC205_IN_INV_SEL_S)
+#define GPIO_FUNC205_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC205_IN_INV_SEL_S  8
+/** GPIO_SIG205_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG205_IN_SEL    (BIT(9))
+#define GPIO_SIG205_IN_SEL_M  (GPIO_SIG205_IN_SEL_V << GPIO_SIG205_IN_SEL_S)
+#define GPIO_SIG205_IN_SEL_V  0x00000001U
+#define GPIO_SIG205_IN_SEL_S  9
+
+/** GPIO_FUNC206_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 206
+ */
+#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x62c)
+/** GPIO_FUNC206_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 206.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC206_IN_SEL    0x000000FFU
+#define GPIO_FUNC206_IN_SEL_M  (GPIO_FUNC206_IN_SEL_V << GPIO_FUNC206_IN_SEL_S)
+#define GPIO_FUNC206_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC206_IN_SEL_S  0
+/** GPIO_FUNC206_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC206_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC206_IN_INV_SEL_M  (GPIO_FUNC206_IN_INV_SEL_V << GPIO_FUNC206_IN_INV_SEL_S)
+#define GPIO_FUNC206_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC206_IN_INV_SEL_S  8
+/** GPIO_SIG206_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG206_IN_SEL    (BIT(9))
+#define GPIO_SIG206_IN_SEL_M  (GPIO_SIG206_IN_SEL_V << GPIO_SIG206_IN_SEL_S)
+#define GPIO_SIG206_IN_SEL_V  0x00000001U
+#define GPIO_SIG206_IN_SEL_S  9
+
+/** GPIO_FUNC207_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 207
+ */
+#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x630)
+/** GPIO_FUNC207_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 207.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC207_IN_SEL    0x000000FFU
+#define GPIO_FUNC207_IN_SEL_M  (GPIO_FUNC207_IN_SEL_V << GPIO_FUNC207_IN_SEL_S)
+#define GPIO_FUNC207_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC207_IN_SEL_S  0
+/** GPIO_FUNC207_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC207_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC207_IN_INV_SEL_M  (GPIO_FUNC207_IN_INV_SEL_V << GPIO_FUNC207_IN_INV_SEL_S)
+#define GPIO_FUNC207_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC207_IN_INV_SEL_S  8
+/** GPIO_SIG207_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG207_IN_SEL    (BIT(9))
+#define GPIO_SIG207_IN_SEL_M  (GPIO_SIG207_IN_SEL_V << GPIO_SIG207_IN_SEL_S)
+#define GPIO_SIG207_IN_SEL_V  0x00000001U
+#define GPIO_SIG207_IN_SEL_S  9
+
+/** GPIO_FUNC208_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 208
+ */
+#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x634)
+/** GPIO_FUNC208_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 208.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC208_IN_SEL    0x000000FFU
+#define GPIO_FUNC208_IN_SEL_M  (GPIO_FUNC208_IN_SEL_V << GPIO_FUNC208_IN_SEL_S)
+#define GPIO_FUNC208_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC208_IN_SEL_S  0
+/** GPIO_FUNC208_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC208_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC208_IN_INV_SEL_M  (GPIO_FUNC208_IN_INV_SEL_V << GPIO_FUNC208_IN_INV_SEL_S)
+#define GPIO_FUNC208_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC208_IN_INV_SEL_S  8
+/** GPIO_SIG208_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG208_IN_SEL    (BIT(9))
+#define GPIO_SIG208_IN_SEL_M  (GPIO_SIG208_IN_SEL_V << GPIO_SIG208_IN_SEL_S)
+#define GPIO_SIG208_IN_SEL_V  0x00000001U
+#define GPIO_SIG208_IN_SEL_S  9
+
+/** GPIO_FUNC209_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 209
+ */
+#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x638)
+/** GPIO_FUNC209_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 209.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC209_IN_SEL    0x000000FFU
+#define GPIO_FUNC209_IN_SEL_M  (GPIO_FUNC209_IN_SEL_V << GPIO_FUNC209_IN_SEL_S)
+#define GPIO_FUNC209_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC209_IN_SEL_S  0
+/** GPIO_FUNC209_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC209_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC209_IN_INV_SEL_M  (GPIO_FUNC209_IN_INV_SEL_V << GPIO_FUNC209_IN_INV_SEL_S)
+#define GPIO_FUNC209_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC209_IN_INV_SEL_S  8
+/** GPIO_SIG209_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG209_IN_SEL    (BIT(9))
+#define GPIO_SIG209_IN_SEL_M  (GPIO_SIG209_IN_SEL_V << GPIO_SIG209_IN_SEL_S)
+#define GPIO_SIG209_IN_SEL_V  0x00000001U
+#define GPIO_SIG209_IN_SEL_S  9
+
+/** GPIO_FUNC210_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 210
+ */
+#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x63c)
+/** GPIO_FUNC210_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 210.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC210_IN_SEL    0x000000FFU
+#define GPIO_FUNC210_IN_SEL_M  (GPIO_FUNC210_IN_SEL_V << GPIO_FUNC210_IN_SEL_S)
+#define GPIO_FUNC210_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC210_IN_SEL_S  0
+/** GPIO_FUNC210_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC210_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC210_IN_INV_SEL_M  (GPIO_FUNC210_IN_INV_SEL_V << GPIO_FUNC210_IN_INV_SEL_S)
+#define GPIO_FUNC210_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC210_IN_INV_SEL_S  8
+/** GPIO_SIG210_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG210_IN_SEL    (BIT(9))
+#define GPIO_SIG210_IN_SEL_M  (GPIO_SIG210_IN_SEL_V << GPIO_SIG210_IN_SEL_S)
+#define GPIO_SIG210_IN_SEL_V  0x00000001U
+#define GPIO_SIG210_IN_SEL_S  9
+
+/** GPIO_FUNC211_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 211
+ */
+#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x640)
+/** GPIO_FUNC211_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 211.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC211_IN_SEL    0x000000FFU
+#define GPIO_FUNC211_IN_SEL_M  (GPIO_FUNC211_IN_SEL_V << GPIO_FUNC211_IN_SEL_S)
+#define GPIO_FUNC211_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC211_IN_SEL_S  0
+/** GPIO_FUNC211_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC211_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC211_IN_INV_SEL_M  (GPIO_FUNC211_IN_INV_SEL_V << GPIO_FUNC211_IN_INV_SEL_S)
+#define GPIO_FUNC211_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC211_IN_INV_SEL_S  8
+/** GPIO_SIG211_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG211_IN_SEL    (BIT(9))
+#define GPIO_SIG211_IN_SEL_M  (GPIO_SIG211_IN_SEL_V << GPIO_SIG211_IN_SEL_S)
+#define GPIO_SIG211_IN_SEL_V  0x00000001U
+#define GPIO_SIG211_IN_SEL_S  9
+
+/** GPIO_FUNC214_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 214
+ */
+#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x64c)
+/** GPIO_FUNC214_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 214.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC214_IN_SEL    0x000000FFU
+#define GPIO_FUNC214_IN_SEL_M  (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S)
+#define GPIO_FUNC214_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC214_IN_SEL_S  0
+/** GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC214_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC214_IN_INV_SEL_M  (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S)
+#define GPIO_FUNC214_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC214_IN_INV_SEL_S  8
+/** GPIO_SIG214_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG214_IN_SEL    (BIT(9))
+#define GPIO_SIG214_IN_SEL_M  (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S)
+#define GPIO_SIG214_IN_SEL_V  0x00000001U
+#define GPIO_SIG214_IN_SEL_S  9
+
+/** GPIO_FUNC215_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 215
+ */
+#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x650)
+/** GPIO_FUNC215_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 215.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC215_IN_SEL    0x000000FFU
+#define GPIO_FUNC215_IN_SEL_M  (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S)
+#define GPIO_FUNC215_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC215_IN_SEL_S  0
+/** GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC215_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC215_IN_INV_SEL_M  (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S)
+#define GPIO_FUNC215_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC215_IN_INV_SEL_S  8
+/** GPIO_SIG215_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG215_IN_SEL    (BIT(9))
+#define GPIO_SIG215_IN_SEL_M  (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S)
+#define GPIO_SIG215_IN_SEL_V  0x00000001U
+#define GPIO_SIG215_IN_SEL_S  9
+
+/** GPIO_FUNC216_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 216
+ */
+#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x654)
+/** GPIO_FUNC216_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 216.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC216_IN_SEL    0x000000FFU
+#define GPIO_FUNC216_IN_SEL_M  (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S)
+#define GPIO_FUNC216_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC216_IN_SEL_S  0
+/** GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC216_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC216_IN_INV_SEL_M  (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S)
+#define GPIO_FUNC216_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC216_IN_INV_SEL_S  8
+/** GPIO_SIG216_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG216_IN_SEL    (BIT(9))
+#define GPIO_SIG216_IN_SEL_M  (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S)
+#define GPIO_SIG216_IN_SEL_V  0x00000001U
+#define GPIO_SIG216_IN_SEL_S  9
+
+/** GPIO_FUNC217_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 217
+ */
+#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x658)
+/** GPIO_FUNC217_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 217.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC217_IN_SEL    0x000000FFU
+#define GPIO_FUNC217_IN_SEL_M  (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S)
+#define GPIO_FUNC217_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC217_IN_SEL_S  0
+/** GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC217_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC217_IN_INV_SEL_M  (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S)
+#define GPIO_FUNC217_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC217_IN_INV_SEL_S  8
+/** GPIO_SIG217_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG217_IN_SEL    (BIT(9))
+#define GPIO_SIG217_IN_SEL_M  (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S)
+#define GPIO_SIG217_IN_SEL_V  0x00000001U
+#define GPIO_SIG217_IN_SEL_S  9
+
+/** GPIO_FUNC218_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 218
+ */
+#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x65c)
+/** GPIO_FUNC218_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 218.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC218_IN_SEL    0x000000FFU
+#define GPIO_FUNC218_IN_SEL_M  (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S)
+#define GPIO_FUNC218_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC218_IN_SEL_S  0
+/** GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC218_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC218_IN_INV_SEL_M  (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S)
+#define GPIO_FUNC218_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC218_IN_INV_SEL_S  8
+/** GPIO_SIG218_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG218_IN_SEL    (BIT(9))
+#define GPIO_SIG218_IN_SEL_M  (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S)
+#define GPIO_SIG218_IN_SEL_V  0x00000001U
+#define GPIO_SIG218_IN_SEL_S  9
+
+/** GPIO_FUNC219_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 219
+ */
+#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x660)
+/** GPIO_FUNC219_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 219.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC219_IN_SEL    0x000000FFU
+#define GPIO_FUNC219_IN_SEL_M  (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S)
+#define GPIO_FUNC219_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC219_IN_SEL_S  0
+/** GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC219_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC219_IN_INV_SEL_M  (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S)
+#define GPIO_FUNC219_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC219_IN_INV_SEL_S  8
+/** GPIO_SIG219_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG219_IN_SEL    (BIT(9))
+#define GPIO_SIG219_IN_SEL_M  (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S)
+#define GPIO_SIG219_IN_SEL_V  0x00000001U
+#define GPIO_SIG219_IN_SEL_S  9
+
+/** GPIO_FUNC220_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 220
+ */
+#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x664)
+/** GPIO_FUNC220_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 220.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC220_IN_SEL    0x000000FFU
+#define GPIO_FUNC220_IN_SEL_M  (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S)
+#define GPIO_FUNC220_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC220_IN_SEL_S  0
+/** GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC220_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC220_IN_INV_SEL_M  (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S)
+#define GPIO_FUNC220_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC220_IN_INV_SEL_S  8
+/** GPIO_SIG220_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG220_IN_SEL    (BIT(9))
+#define GPIO_SIG220_IN_SEL_M  (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S)
+#define GPIO_SIG220_IN_SEL_V  0x00000001U
+#define GPIO_SIG220_IN_SEL_S  9
+
+/** GPIO_FUNC221_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 221
+ */
+#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x668)
+/** GPIO_FUNC221_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 221.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC221_IN_SEL    0x000000FFU
+#define GPIO_FUNC221_IN_SEL_M  (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S)
+#define GPIO_FUNC221_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC221_IN_SEL_S  0
+/** GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC221_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC221_IN_INV_SEL_M  (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S)
+#define GPIO_FUNC221_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC221_IN_INV_SEL_S  8
+/** GPIO_SIG221_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG221_IN_SEL    (BIT(9))
+#define GPIO_SIG221_IN_SEL_M  (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S)
+#define GPIO_SIG221_IN_SEL_V  0x00000001U
+#define GPIO_SIG221_IN_SEL_S  9
+
+/** GPIO_FUNC222_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 222
+ */
+#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x66c)
+/** GPIO_FUNC222_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 222.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC222_IN_SEL    0x000000FFU
+#define GPIO_FUNC222_IN_SEL_M  (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S)
+#define GPIO_FUNC222_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC222_IN_SEL_S  0
+/** GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC222_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC222_IN_INV_SEL_M  (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S)
+#define GPIO_FUNC222_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC222_IN_INV_SEL_S  8
+/** GPIO_SIG222_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG222_IN_SEL    (BIT(9))
+#define GPIO_SIG222_IN_SEL_M  (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S)
+#define GPIO_SIG222_IN_SEL_V  0x00000001U
+#define GPIO_SIG222_IN_SEL_S  9
+
+/** GPIO_FUNC223_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 223
+ */
+#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x670)
+/** GPIO_FUNC223_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 223.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC223_IN_SEL    0x000000FFU
+#define GPIO_FUNC223_IN_SEL_M  (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S)
+#define GPIO_FUNC223_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC223_IN_SEL_S  0
+/** GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC223_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC223_IN_INV_SEL_M  (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S)
+#define GPIO_FUNC223_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC223_IN_INV_SEL_S  8
+/** GPIO_SIG223_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG223_IN_SEL    (BIT(9))
+#define GPIO_SIG223_IN_SEL_M  (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S)
+#define GPIO_SIG223_IN_SEL_V  0x00000001U
+#define GPIO_SIG223_IN_SEL_S  9
+
+/** GPIO_FUNC224_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 224
+ */
+#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x674)
+/** GPIO_FUNC224_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 224.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC224_IN_SEL    0x000000FFU
+#define GPIO_FUNC224_IN_SEL_M  (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S)
+#define GPIO_FUNC224_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC224_IN_SEL_S  0
+/** GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC224_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC224_IN_INV_SEL_M  (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S)
+#define GPIO_FUNC224_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC224_IN_INV_SEL_S  8
+/** GPIO_SIG224_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG224_IN_SEL    (BIT(9))
+#define GPIO_SIG224_IN_SEL_M  (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S)
+#define GPIO_SIG224_IN_SEL_V  0x00000001U
+#define GPIO_SIG224_IN_SEL_S  9
+
+/** GPIO_FUNC225_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 225
+ */
+#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x678)
+/** GPIO_FUNC225_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 225.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC225_IN_SEL    0x000000FFU
+#define GPIO_FUNC225_IN_SEL_M  (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S)
+#define GPIO_FUNC225_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC225_IN_SEL_S  0
+/** GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC225_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC225_IN_INV_SEL_M  (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S)
+#define GPIO_FUNC225_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC225_IN_INV_SEL_S  8
+/** GPIO_SIG225_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG225_IN_SEL    (BIT(9))
+#define GPIO_SIG225_IN_SEL_M  (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S)
+#define GPIO_SIG225_IN_SEL_V  0x00000001U
+#define GPIO_SIG225_IN_SEL_S  9
+
+/** GPIO_FUNC226_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 226
+ */
+#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x67c)
+/** GPIO_FUNC226_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 226.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC226_IN_SEL    0x000000FFU
+#define GPIO_FUNC226_IN_SEL_M  (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S)
+#define GPIO_FUNC226_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC226_IN_SEL_S  0
+/** GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC226_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC226_IN_INV_SEL_M  (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S)
+#define GPIO_FUNC226_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC226_IN_INV_SEL_S  8
+/** GPIO_SIG226_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG226_IN_SEL    (BIT(9))
+#define GPIO_SIG226_IN_SEL_M  (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S)
+#define GPIO_SIG226_IN_SEL_V  0x00000001U
+#define GPIO_SIG226_IN_SEL_S  9
+
+/** GPIO_FUNC227_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 227
+ */
+#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x680)
+/** GPIO_FUNC227_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 227.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC227_IN_SEL    0x000000FFU
+#define GPIO_FUNC227_IN_SEL_M  (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S)
+#define GPIO_FUNC227_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC227_IN_SEL_S  0
+/** GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC227_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC227_IN_INV_SEL_M  (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S)
+#define GPIO_FUNC227_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC227_IN_INV_SEL_S  8
+/** GPIO_SIG227_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG227_IN_SEL    (BIT(9))
+#define GPIO_SIG227_IN_SEL_M  (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S)
+#define GPIO_SIG227_IN_SEL_V  0x00000001U
+#define GPIO_SIG227_IN_SEL_S  9
+
+/** GPIO_FUNC228_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 228
+ */
+#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x684)
+/** GPIO_FUNC228_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 228.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC228_IN_SEL    0x000000FFU
+#define GPIO_FUNC228_IN_SEL_M  (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S)
+#define GPIO_FUNC228_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC228_IN_SEL_S  0
+/** GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC228_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC228_IN_INV_SEL_M  (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S)
+#define GPIO_FUNC228_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC228_IN_INV_SEL_S  8
+/** GPIO_SIG228_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG228_IN_SEL    (BIT(9))
+#define GPIO_SIG228_IN_SEL_M  (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S)
+#define GPIO_SIG228_IN_SEL_V  0x00000001U
+#define GPIO_SIG228_IN_SEL_S  9
+
+/** GPIO_FUNC229_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 229
+ */
+#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x688)
+/** GPIO_FUNC229_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 229.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC229_IN_SEL    0x000000FFU
+#define GPIO_FUNC229_IN_SEL_M  (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S)
+#define GPIO_FUNC229_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC229_IN_SEL_S  0
+/** GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC229_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC229_IN_INV_SEL_M  (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S)
+#define GPIO_FUNC229_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC229_IN_INV_SEL_S  8
+/** GPIO_SIG229_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG229_IN_SEL    (BIT(9))
+#define GPIO_SIG229_IN_SEL_M  (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S)
+#define GPIO_SIG229_IN_SEL_V  0x00000001U
+#define GPIO_SIG229_IN_SEL_S  9
+
+/** GPIO_FUNC230_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 230
+ */
+#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x68c)
+/** GPIO_FUNC230_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 230.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC230_IN_SEL    0x000000FFU
+#define GPIO_FUNC230_IN_SEL_M  (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S)
+#define GPIO_FUNC230_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC230_IN_SEL_S  0
+/** GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC230_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC230_IN_INV_SEL_M  (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S)
+#define GPIO_FUNC230_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC230_IN_INV_SEL_S  8
+/** GPIO_SIG230_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG230_IN_SEL    (BIT(9))
+#define GPIO_SIG230_IN_SEL_M  (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S)
+#define GPIO_SIG230_IN_SEL_V  0x00000001U
+#define GPIO_SIG230_IN_SEL_S  9
+
+/** GPIO_FUNC231_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 231
+ */
+#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x690)
+/** GPIO_FUNC231_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 231.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC231_IN_SEL    0x000000FFU
+#define GPIO_FUNC231_IN_SEL_M  (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S)
+#define GPIO_FUNC231_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC231_IN_SEL_S  0
+/** GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC231_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC231_IN_INV_SEL_M  (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S)
+#define GPIO_FUNC231_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC231_IN_INV_SEL_S  8
+/** GPIO_SIG231_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG231_IN_SEL    (BIT(9))
+#define GPIO_SIG231_IN_SEL_M  (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S)
+#define GPIO_SIG231_IN_SEL_V  0x00000001U
+#define GPIO_SIG231_IN_SEL_S  9
+
+/** GPIO_FUNC232_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 232
+ */
+#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x694)
+/** GPIO_FUNC232_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 232.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC232_IN_SEL    0x000000FFU
+#define GPIO_FUNC232_IN_SEL_M  (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S)
+#define GPIO_FUNC232_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC232_IN_SEL_S  0
+/** GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC232_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC232_IN_INV_SEL_M  (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S)
+#define GPIO_FUNC232_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC232_IN_INV_SEL_S  8
+/** GPIO_SIG232_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG232_IN_SEL    (BIT(9))
+#define GPIO_SIG232_IN_SEL_M  (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S)
+#define GPIO_SIG232_IN_SEL_V  0x00000001U
+#define GPIO_SIG232_IN_SEL_S  9
+
+/** GPIO_FUNC233_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 233
+ */
+#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x698)
+/** GPIO_FUNC233_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 233.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC233_IN_SEL    0x000000FFU
+#define GPIO_FUNC233_IN_SEL_M  (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S)
+#define GPIO_FUNC233_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC233_IN_SEL_S  0
+/** GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC233_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC233_IN_INV_SEL_M  (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S)
+#define GPIO_FUNC233_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC233_IN_INV_SEL_S  8
+/** GPIO_SIG233_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG233_IN_SEL    (BIT(9))
+#define GPIO_SIG233_IN_SEL_M  (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S)
+#define GPIO_SIG233_IN_SEL_V  0x00000001U
+#define GPIO_SIG233_IN_SEL_S  9
+
+/** GPIO_FUNC234_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 234
+ */
+#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x69c)
+/** GPIO_FUNC234_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 234.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC234_IN_SEL    0x000000FFU
+#define GPIO_FUNC234_IN_SEL_M  (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S)
+#define GPIO_FUNC234_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC234_IN_SEL_S  0
+/** GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC234_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC234_IN_INV_SEL_M  (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S)
+#define GPIO_FUNC234_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC234_IN_INV_SEL_S  8
+/** GPIO_SIG234_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG234_IN_SEL    (BIT(9))
+#define GPIO_SIG234_IN_SEL_M  (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S)
+#define GPIO_SIG234_IN_SEL_V  0x00000001U
+#define GPIO_SIG234_IN_SEL_S  9
+
+/** GPIO_FUNC235_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 235
+ */
+#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6a0)
+/** GPIO_FUNC235_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 235.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC235_IN_SEL    0x000000FFU
+#define GPIO_FUNC235_IN_SEL_M  (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S)
+#define GPIO_FUNC235_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC235_IN_SEL_S  0
+/** GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC235_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC235_IN_INV_SEL_M  (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S)
+#define GPIO_FUNC235_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC235_IN_INV_SEL_S  8
+/** GPIO_SIG235_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG235_IN_SEL    (BIT(9))
+#define GPIO_SIG235_IN_SEL_M  (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S)
+#define GPIO_SIG235_IN_SEL_V  0x00000001U
+#define GPIO_SIG235_IN_SEL_S  9
+
+/** GPIO_FUNC236_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 236
+ */
+#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6a4)
+/** GPIO_FUNC236_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 236.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC236_IN_SEL    0x000000FFU
+#define GPIO_FUNC236_IN_SEL_M  (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S)
+#define GPIO_FUNC236_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC236_IN_SEL_S  0
+/** GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC236_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC236_IN_INV_SEL_M  (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S)
+#define GPIO_FUNC236_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC236_IN_INV_SEL_S  8
+/** GPIO_SIG236_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG236_IN_SEL    (BIT(9))
+#define GPIO_SIG236_IN_SEL_M  (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S)
+#define GPIO_SIG236_IN_SEL_V  0x00000001U
+#define GPIO_SIG236_IN_SEL_S  9
+
+/** GPIO_FUNC237_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 237
+ */
+#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6a8)
+/** GPIO_FUNC237_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 237.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC237_IN_SEL    0x000000FFU
+#define GPIO_FUNC237_IN_SEL_M  (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S)
+#define GPIO_FUNC237_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC237_IN_SEL_S  0
+/** GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC237_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC237_IN_INV_SEL_M  (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S)
+#define GPIO_FUNC237_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC237_IN_INV_SEL_S  8
+/** GPIO_SIG237_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG237_IN_SEL    (BIT(9))
+#define GPIO_SIG237_IN_SEL_M  (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S)
+#define GPIO_SIG237_IN_SEL_V  0x00000001U
+#define GPIO_SIG237_IN_SEL_S  9
+
+/** GPIO_FUNC238_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 238
+ */
+#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6ac)
+/** GPIO_FUNC238_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 238.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC238_IN_SEL    0x000000FFU
+#define GPIO_FUNC238_IN_SEL_M  (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S)
+#define GPIO_FUNC238_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC238_IN_SEL_S  0
+/** GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC238_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC238_IN_INV_SEL_M  (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S)
+#define GPIO_FUNC238_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC238_IN_INV_SEL_S  8
+/** GPIO_SIG238_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG238_IN_SEL    (BIT(9))
+#define GPIO_SIG238_IN_SEL_M  (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S)
+#define GPIO_SIG238_IN_SEL_V  0x00000001U
+#define GPIO_SIG238_IN_SEL_S  9
+
+/** GPIO_FUNC239_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 239
+ */
+#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6b0)
+/** GPIO_FUNC239_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 239.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC239_IN_SEL    0x000000FFU
+#define GPIO_FUNC239_IN_SEL_M  (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S)
+#define GPIO_FUNC239_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC239_IN_SEL_S  0
+/** GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC239_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC239_IN_INV_SEL_M  (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S)
+#define GPIO_FUNC239_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC239_IN_INV_SEL_S  8
+/** GPIO_SIG239_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG239_IN_SEL    (BIT(9))
+#define GPIO_SIG239_IN_SEL_M  (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S)
+#define GPIO_SIG239_IN_SEL_V  0x00000001U
+#define GPIO_SIG239_IN_SEL_S  9
+
+/** GPIO_FUNC240_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 240
+ */
+#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6b4)
+/** GPIO_FUNC240_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 240.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC240_IN_SEL    0x000000FFU
+#define GPIO_FUNC240_IN_SEL_M  (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S)
+#define GPIO_FUNC240_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC240_IN_SEL_S  0
+/** GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC240_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC240_IN_INV_SEL_M  (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S)
+#define GPIO_FUNC240_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC240_IN_INV_SEL_S  8
+/** GPIO_SIG240_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG240_IN_SEL    (BIT(9))
+#define GPIO_SIG240_IN_SEL_M  (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S)
+#define GPIO_SIG240_IN_SEL_V  0x00000001U
+#define GPIO_SIG240_IN_SEL_S  9
+
+/** GPIO_FUNC241_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 241
+ */
+#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6b8)
+/** GPIO_FUNC241_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 241.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC241_IN_SEL    0x000000FFU
+#define GPIO_FUNC241_IN_SEL_M  (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S)
+#define GPIO_FUNC241_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC241_IN_SEL_S  0
+/** GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC241_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC241_IN_INV_SEL_M  (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S)
+#define GPIO_FUNC241_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC241_IN_INV_SEL_S  8
+/** GPIO_SIG241_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG241_IN_SEL    (BIT(9))
+#define GPIO_SIG241_IN_SEL_M  (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S)
+#define GPIO_SIG241_IN_SEL_V  0x00000001U
+#define GPIO_SIG241_IN_SEL_S  9
+
+/** GPIO_FUNC242_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 242
+ */
+#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6bc)
+/** GPIO_FUNC242_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 242.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC242_IN_SEL    0x000000FFU
+#define GPIO_FUNC242_IN_SEL_M  (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S)
+#define GPIO_FUNC242_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC242_IN_SEL_S  0
+/** GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC242_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC242_IN_INV_SEL_M  (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S)
+#define GPIO_FUNC242_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC242_IN_INV_SEL_S  8
+/** GPIO_SIG242_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG242_IN_SEL    (BIT(9))
+#define GPIO_SIG242_IN_SEL_M  (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S)
+#define GPIO_SIG242_IN_SEL_V  0x00000001U
+#define GPIO_SIG242_IN_SEL_S  9
+
+/** GPIO_FUNC243_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 243
+ */
+#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6c0)
+/** GPIO_FUNC243_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 243.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC243_IN_SEL    0x000000FFU
+#define GPIO_FUNC243_IN_SEL_M  (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S)
+#define GPIO_FUNC243_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC243_IN_SEL_S  0
+/** GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC243_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC243_IN_INV_SEL_M  (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S)
+#define GPIO_FUNC243_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC243_IN_INV_SEL_S  8
+/** GPIO_SIG243_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG243_IN_SEL    (BIT(9))
+#define GPIO_SIG243_IN_SEL_M  (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S)
+#define GPIO_SIG243_IN_SEL_V  0x00000001U
+#define GPIO_SIG243_IN_SEL_S  9
+
+/** GPIO_FUNC244_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 244
+ */
+#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6c4)
+/** GPIO_FUNC244_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 244.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC244_IN_SEL    0x000000FFU
+#define GPIO_FUNC244_IN_SEL_M  (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S)
+#define GPIO_FUNC244_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC244_IN_SEL_S  0
+/** GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC244_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC244_IN_INV_SEL_M  (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S)
+#define GPIO_FUNC244_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC244_IN_INV_SEL_S  8
+/** GPIO_SIG244_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG244_IN_SEL    (BIT(9))
+#define GPIO_SIG244_IN_SEL_M  (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S)
+#define GPIO_SIG244_IN_SEL_V  0x00000001U
+#define GPIO_SIG244_IN_SEL_S  9
+
+/** GPIO_FUNC245_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 245
+ */
+#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6c8)
+/** GPIO_FUNC245_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 245.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC245_IN_SEL    0x000000FFU
+#define GPIO_FUNC245_IN_SEL_M  (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S)
+#define GPIO_FUNC245_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC245_IN_SEL_S  0
+/** GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC245_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC245_IN_INV_SEL_M  (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S)
+#define GPIO_FUNC245_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC245_IN_INV_SEL_S  8
+/** GPIO_SIG245_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG245_IN_SEL    (BIT(9))
+#define GPIO_SIG245_IN_SEL_M  (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S)
+#define GPIO_SIG245_IN_SEL_V  0x00000001U
+#define GPIO_SIG245_IN_SEL_S  9
+
+/** GPIO_FUNC246_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 246
+ */
+#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6cc)
+/** GPIO_FUNC246_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 246.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC246_IN_SEL    0x000000FFU
+#define GPIO_FUNC246_IN_SEL_M  (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S)
+#define GPIO_FUNC246_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC246_IN_SEL_S  0
+/** GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC246_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC246_IN_INV_SEL_M  (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S)
+#define GPIO_FUNC246_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC246_IN_INV_SEL_S  8
+/** GPIO_SIG246_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG246_IN_SEL    (BIT(9))
+#define GPIO_SIG246_IN_SEL_M  (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S)
+#define GPIO_SIG246_IN_SEL_V  0x00000001U
+#define GPIO_SIG246_IN_SEL_S  9
+
+/** GPIO_FUNC247_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 247
+ */
+#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6d0)
+/** GPIO_FUNC247_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 247.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC247_IN_SEL    0x000000FFU
+#define GPIO_FUNC247_IN_SEL_M  (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S)
+#define GPIO_FUNC247_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC247_IN_SEL_S  0
+/** GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC247_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC247_IN_INV_SEL_M  (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S)
+#define GPIO_FUNC247_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC247_IN_INV_SEL_S  8
+/** GPIO_SIG247_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG247_IN_SEL    (BIT(9))
+#define GPIO_SIG247_IN_SEL_M  (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S)
+#define GPIO_SIG247_IN_SEL_V  0x00000001U
+#define GPIO_SIG247_IN_SEL_S  9
+
+/** GPIO_FUNC248_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 248
+ */
+#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6d4)
+/** GPIO_FUNC248_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 248.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC248_IN_SEL    0x000000FFU
+#define GPIO_FUNC248_IN_SEL_M  (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S)
+#define GPIO_FUNC248_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC248_IN_SEL_S  0
+/** GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC248_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC248_IN_INV_SEL_M  (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S)
+#define GPIO_FUNC248_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC248_IN_INV_SEL_S  8
+/** GPIO_SIG248_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG248_IN_SEL    (BIT(9))
+#define GPIO_SIG248_IN_SEL_M  (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S)
+#define GPIO_SIG248_IN_SEL_V  0x00000001U
+#define GPIO_SIG248_IN_SEL_S  9
+
+/** GPIO_FUNC249_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 249
+ */
+#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6d8)
+/** GPIO_FUNC249_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 249.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC249_IN_SEL    0x000000FFU
+#define GPIO_FUNC249_IN_SEL_M  (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S)
+#define GPIO_FUNC249_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC249_IN_SEL_S  0
+/** GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC249_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC249_IN_INV_SEL_M  (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S)
+#define GPIO_FUNC249_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC249_IN_INV_SEL_S  8
+/** GPIO_SIG249_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG249_IN_SEL    (BIT(9))
+#define GPIO_SIG249_IN_SEL_M  (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S)
+#define GPIO_SIG249_IN_SEL_V  0x00000001U
+#define GPIO_SIG249_IN_SEL_S  9
+
+/** GPIO_FUNC251_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 251
+ */
+#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6e0)
+/** GPIO_FUNC251_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 251.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC251_IN_SEL    0x000000FFU
+#define GPIO_FUNC251_IN_SEL_M  (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S)
+#define GPIO_FUNC251_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC251_IN_SEL_S  0
+/** GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC251_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC251_IN_INV_SEL_M  (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S)
+#define GPIO_FUNC251_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC251_IN_INV_SEL_S  8
+/** GPIO_SIG251_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG251_IN_SEL    (BIT(9))
+#define GPIO_SIG251_IN_SEL_M  (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S)
+#define GPIO_SIG251_IN_SEL_V  0x00000001U
+#define GPIO_SIG251_IN_SEL_S  9
+
+/** GPIO_FUNC252_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 252
+ */
+#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6e4)
+/** GPIO_FUNC252_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 252.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC252_IN_SEL    0x000000FFU
+#define GPIO_FUNC252_IN_SEL_M  (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S)
+#define GPIO_FUNC252_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC252_IN_SEL_S  0
+/** GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC252_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC252_IN_INV_SEL_M  (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S)
+#define GPIO_FUNC252_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC252_IN_INV_SEL_S  8
+/** GPIO_SIG252_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG252_IN_SEL    (BIT(9))
+#define GPIO_SIG252_IN_SEL_M  (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S)
+#define GPIO_SIG252_IN_SEL_V  0x00000001U
+#define GPIO_SIG252_IN_SEL_S  9
+
+/** GPIO_FUNC253_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 253
+ */
+#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6e8)
+/** GPIO_FUNC253_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 253.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC253_IN_SEL    0x000000FFU
+#define GPIO_FUNC253_IN_SEL_M  (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S)
+#define GPIO_FUNC253_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC253_IN_SEL_S  0
+/** GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC253_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC253_IN_INV_SEL_M  (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S)
+#define GPIO_FUNC253_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC253_IN_INV_SEL_S  8
+/** GPIO_SIG253_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG253_IN_SEL    (BIT(9))
+#define GPIO_SIG253_IN_SEL_M  (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S)
+#define GPIO_SIG253_IN_SEL_V  0x00000001U
+#define GPIO_SIG253_IN_SEL_S  9
+
+/** GPIO_FUNC254_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 254
+ */
+#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6ec)
+/** GPIO_FUNC254_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 254.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC254_IN_SEL    0x000000FFU
+#define GPIO_FUNC254_IN_SEL_M  (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S)
+#define GPIO_FUNC254_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC254_IN_SEL_S  0
+/** GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC254_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC254_IN_INV_SEL_M  (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S)
+#define GPIO_FUNC254_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC254_IN_INV_SEL_S  8
+/** GPIO_SIG254_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG254_IN_SEL    (BIT(9))
+#define GPIO_SIG254_IN_SEL_M  (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S)
+#define GPIO_SIG254_IN_SEL_V  0x00000001U
+#define GPIO_SIG254_IN_SEL_S  9
+
+/** GPIO_FUNC255_IN_SEL_CFG_REG register
+ *  Configuration register for input signal 255
+ */
+#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x6f0)
+/** GPIO_FUNC255_IN_SEL : R/W; bitpos: [7:0]; default: 192;
+ *  Configures to select a pin from the 63 GPIO pins to connect the input signal 255.
+ *  0: Select GPIO0
+ *  1: Select GPIO1
+ *  ......
+ *  61: Select GPIO61
+ *  62: Select GPIO62
+ *  Or
+ *  0x80: A constantly high input
+ *  0xc0: A constantly low input
+ */
+#define GPIO_FUNC255_IN_SEL    0x000000FFU
+#define GPIO_FUNC255_IN_SEL_M  (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S)
+#define GPIO_FUNC255_IN_SEL_V  0x000000FFU
+#define GPIO_FUNC255_IN_SEL_S  0
+/** GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [8]; default: 0;
+ *  Configures whether or not to invert the input value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC255_IN_INV_SEL    (BIT(8))
+#define GPIO_FUNC255_IN_INV_SEL_M  (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S)
+#define GPIO_FUNC255_IN_INV_SEL_V  0x00000001U
+#define GPIO_FUNC255_IN_INV_SEL_S  8
+/** GPIO_SIG255_IN_SEL : R/W; bitpos: [9]; default: 0;
+ *  Configures whether or not to route signals via GPIO matrix.
+ *  0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in
+ *  IO MUX.
+ *  1: Route signals via GPIO matrix.
+ */
+#define GPIO_SIG255_IN_SEL    (BIT(9))
+#define GPIO_SIG255_IN_SEL_M  (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S)
+#define GPIO_SIG255_IN_SEL_V  0x00000001U
+#define GPIO_SIG255_IN_SEL_S  9
+
+/** GPIO_FUNC0_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO0 output
+ */
+#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4)
+/** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO0.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC0_OUT_SEL    0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_M  (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S)
+#define GPIO_FUNC0_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC0_OUT_SEL_S  0
+/** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC0_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S)
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC0_OE_SEL    (BIT(10))
+#define GPIO_FUNC0_OE_SEL_M  (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S)
+#define GPIO_FUNC0_OE_SEL_V  0x00000001U
+#define GPIO_FUNC0_OE_SEL_S  10
+/** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC0_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC0_OE_INV_SEL_M  (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S)
+#define GPIO_FUNC0_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC0_OE_INV_SEL_S  11
+
+/** GPIO_FUNC1_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO1 output
+ */
+#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8)
+/** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO1.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC1_OUT_SEL    0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_M  (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S)
+#define GPIO_FUNC1_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC1_OUT_SEL_S  0
+/** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC1_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S)
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC1_OE_SEL    (BIT(10))
+#define GPIO_FUNC1_OE_SEL_M  (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S)
+#define GPIO_FUNC1_OE_SEL_V  0x00000001U
+#define GPIO_FUNC1_OE_SEL_S  10
+/** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC1_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC1_OE_INV_SEL_M  (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S)
+#define GPIO_FUNC1_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC1_OE_INV_SEL_S  11
+
+/** GPIO_FUNC2_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO2 output
+ */
+#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc)
+/** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO2.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC2_OUT_SEL    0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_M  (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S)
+#define GPIO_FUNC2_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC2_OUT_SEL_S  0
+/** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC2_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S)
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC2_OE_SEL    (BIT(10))
+#define GPIO_FUNC2_OE_SEL_M  (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S)
+#define GPIO_FUNC2_OE_SEL_V  0x00000001U
+#define GPIO_FUNC2_OE_SEL_S  10
+/** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC2_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC2_OE_INV_SEL_M  (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S)
+#define GPIO_FUNC2_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC2_OE_INV_SEL_S  11
+
+/** GPIO_FUNC3_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO3 output
+ */
+#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00)
+/** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO3.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC3_OUT_SEL    0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_M  (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S)
+#define GPIO_FUNC3_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC3_OUT_SEL_S  0
+/** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC3_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S)
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC3_OE_SEL    (BIT(10))
+#define GPIO_FUNC3_OE_SEL_M  (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S)
+#define GPIO_FUNC3_OE_SEL_V  0x00000001U
+#define GPIO_FUNC3_OE_SEL_S  10
+/** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC3_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC3_OE_INV_SEL_M  (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S)
+#define GPIO_FUNC3_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC3_OE_INV_SEL_S  11
+
+/** GPIO_FUNC4_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO4 output
+ */
+#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04)
+/** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO4.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC4_OUT_SEL    0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_M  (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S)
+#define GPIO_FUNC4_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC4_OUT_SEL_S  0
+/** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC4_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S)
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC4_OE_SEL    (BIT(10))
+#define GPIO_FUNC4_OE_SEL_M  (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S)
+#define GPIO_FUNC4_OE_SEL_V  0x00000001U
+#define GPIO_FUNC4_OE_SEL_S  10
+/** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC4_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC4_OE_INV_SEL_M  (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S)
+#define GPIO_FUNC4_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC4_OE_INV_SEL_S  11
+
+/** GPIO_FUNC5_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO5 output
+ */
+#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08)
+/** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO5.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC5_OUT_SEL    0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_M  (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S)
+#define GPIO_FUNC5_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC5_OUT_SEL_S  0
+/** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC5_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S)
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC5_OE_SEL    (BIT(10))
+#define GPIO_FUNC5_OE_SEL_M  (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S)
+#define GPIO_FUNC5_OE_SEL_V  0x00000001U
+#define GPIO_FUNC5_OE_SEL_S  10
+/** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC5_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC5_OE_INV_SEL_M  (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S)
+#define GPIO_FUNC5_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC5_OE_INV_SEL_S  11
+
+/** GPIO_FUNC6_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO6 output
+ */
+#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c)
+/** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO6.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC6_OUT_SEL    0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_M  (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S)
+#define GPIO_FUNC6_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC6_OUT_SEL_S  0
+/** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC6_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S)
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC6_OE_SEL    (BIT(10))
+#define GPIO_FUNC6_OE_SEL_M  (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S)
+#define GPIO_FUNC6_OE_SEL_V  0x00000001U
+#define GPIO_FUNC6_OE_SEL_S  10
+/** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC6_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC6_OE_INV_SEL_M  (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S)
+#define GPIO_FUNC6_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC6_OE_INV_SEL_S  11
+
+/** GPIO_FUNC7_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO7 output
+ */
+#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10)
+/** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO7.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC7_OUT_SEL    0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_M  (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S)
+#define GPIO_FUNC7_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC7_OUT_SEL_S  0
+/** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC7_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S)
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC7_OE_SEL    (BIT(10))
+#define GPIO_FUNC7_OE_SEL_M  (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S)
+#define GPIO_FUNC7_OE_SEL_V  0x00000001U
+#define GPIO_FUNC7_OE_SEL_S  10
+/** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC7_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC7_OE_INV_SEL_M  (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S)
+#define GPIO_FUNC7_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC7_OE_INV_SEL_S  11
+
+/** GPIO_FUNC8_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO8 output
+ */
+#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14)
+/** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO8.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC8_OUT_SEL    0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_M  (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S)
+#define GPIO_FUNC8_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC8_OUT_SEL_S  0
+/** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC8_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S)
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC8_OE_SEL    (BIT(10))
+#define GPIO_FUNC8_OE_SEL_M  (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S)
+#define GPIO_FUNC8_OE_SEL_V  0x00000001U
+#define GPIO_FUNC8_OE_SEL_S  10
+/** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC8_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC8_OE_INV_SEL_M  (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S)
+#define GPIO_FUNC8_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC8_OE_INV_SEL_S  11
+
+/** GPIO_FUNC9_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO9 output
+ */
+#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18)
+/** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO9.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and
+ *  output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC9_OUT_SEL    0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_M  (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S)
+#define GPIO_FUNC9_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC9_OUT_SEL_S  0
+/** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC9_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S)
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC9_OE_SEL    (BIT(10))
+#define GPIO_FUNC9_OE_SEL_M  (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S)
+#define GPIO_FUNC9_OE_SEL_V  0x00000001U
+#define GPIO_FUNC9_OE_SEL_S  10
+/** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC9_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC9_OE_INV_SEL_M  (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S)
+#define GPIO_FUNC9_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC9_OE_INV_SEL_S  11
+
+/** GPIO_FUNC10_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO10 output
+ */
+#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
+/** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO10.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC10_OUT_SEL    0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_M  (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S)
+#define GPIO_FUNC10_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC10_OUT_SEL_S  0
+/** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC10_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S)
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC10_OE_SEL    (BIT(10))
+#define GPIO_FUNC10_OE_SEL_M  (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S)
+#define GPIO_FUNC10_OE_SEL_V  0x00000001U
+#define GPIO_FUNC10_OE_SEL_S  10
+/** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC10_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC10_OE_INV_SEL_M  (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S)
+#define GPIO_FUNC10_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC10_OE_INV_SEL_S  11
+
+/** GPIO_FUNC11_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO11 output
+ */
+#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
+/** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO11.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC11_OUT_SEL    0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_M  (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S)
+#define GPIO_FUNC11_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC11_OUT_SEL_S  0
+/** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC11_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S)
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC11_OE_SEL    (BIT(10))
+#define GPIO_FUNC11_OE_SEL_M  (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S)
+#define GPIO_FUNC11_OE_SEL_V  0x00000001U
+#define GPIO_FUNC11_OE_SEL_S  10
+/** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC11_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC11_OE_INV_SEL_M  (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S)
+#define GPIO_FUNC11_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC11_OE_INV_SEL_S  11
+
+/** GPIO_FUNC12_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO12 output
+ */
+#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
+/** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO12.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC12_OUT_SEL    0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_M  (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S)
+#define GPIO_FUNC12_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC12_OUT_SEL_S  0
+/** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC12_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S)
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC12_OE_SEL    (BIT(10))
+#define GPIO_FUNC12_OE_SEL_M  (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S)
+#define GPIO_FUNC12_OE_SEL_V  0x00000001U
+#define GPIO_FUNC12_OE_SEL_S  10
+/** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC12_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC12_OE_INV_SEL_M  (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S)
+#define GPIO_FUNC12_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC12_OE_INV_SEL_S  11
+
+/** GPIO_FUNC13_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO13 output
+ */
+#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28)
+/** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO13.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC13_OUT_SEL    0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_M  (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S)
+#define GPIO_FUNC13_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC13_OUT_SEL_S  0
+/** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC13_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S)
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC13_OE_SEL    (BIT(10))
+#define GPIO_FUNC13_OE_SEL_M  (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S)
+#define GPIO_FUNC13_OE_SEL_V  0x00000001U
+#define GPIO_FUNC13_OE_SEL_S  10
+/** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC13_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC13_OE_INV_SEL_M  (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S)
+#define GPIO_FUNC13_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC13_OE_INV_SEL_S  11
+
+/** GPIO_FUNC14_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO14 output
+ */
+#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c)
+/** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO14.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC14_OUT_SEL    0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_M  (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S)
+#define GPIO_FUNC14_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC14_OUT_SEL_S  0
+/** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC14_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S)
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC14_OE_SEL    (BIT(10))
+#define GPIO_FUNC14_OE_SEL_M  (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S)
+#define GPIO_FUNC14_OE_SEL_V  0x00000001U
+#define GPIO_FUNC14_OE_SEL_S  10
+/** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC14_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC14_OE_INV_SEL_M  (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S)
+#define GPIO_FUNC14_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC14_OE_INV_SEL_S  11
+
+/** GPIO_FUNC15_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO15 output
+ */
+#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30)
+/** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO15.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC15_OUT_SEL    0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_M  (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S)
+#define GPIO_FUNC15_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC15_OUT_SEL_S  0
+/** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC15_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S)
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC15_OE_SEL    (BIT(10))
+#define GPIO_FUNC15_OE_SEL_M  (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S)
+#define GPIO_FUNC15_OE_SEL_V  0x00000001U
+#define GPIO_FUNC15_OE_SEL_S  10
+/** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC15_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC15_OE_INV_SEL_M  (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S)
+#define GPIO_FUNC15_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC15_OE_INV_SEL_S  11
+
+/** GPIO_FUNC16_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO16 output
+ */
+#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34)
+/** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO16.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC16_OUT_SEL    0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_M  (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S)
+#define GPIO_FUNC16_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC16_OUT_SEL_S  0
+/** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC16_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S)
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC16_OE_SEL    (BIT(10))
+#define GPIO_FUNC16_OE_SEL_M  (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S)
+#define GPIO_FUNC16_OE_SEL_V  0x00000001U
+#define GPIO_FUNC16_OE_SEL_S  10
+/** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC16_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC16_OE_INV_SEL_M  (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S)
+#define GPIO_FUNC16_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC16_OE_INV_SEL_S  11
+
+/** GPIO_FUNC17_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO17 output
+ */
+#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb38)
+/** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO17.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC17_OUT_SEL    0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_M  (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S)
+#define GPIO_FUNC17_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC17_OUT_SEL_S  0
+/** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC17_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S)
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC17_OE_SEL    (BIT(10))
+#define GPIO_FUNC17_OE_SEL_M  (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S)
+#define GPIO_FUNC17_OE_SEL_V  0x00000001U
+#define GPIO_FUNC17_OE_SEL_S  10
+/** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC17_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC17_OE_INV_SEL_M  (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S)
+#define GPIO_FUNC17_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC17_OE_INV_SEL_S  11
+
+/** GPIO_FUNC18_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO18 output
+ */
+#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb3c)
+/** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO18.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC18_OUT_SEL    0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_M  (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S)
+#define GPIO_FUNC18_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC18_OUT_SEL_S  0
+/** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC18_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S)
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC18_OE_SEL    (BIT(10))
+#define GPIO_FUNC18_OE_SEL_M  (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S)
+#define GPIO_FUNC18_OE_SEL_V  0x00000001U
+#define GPIO_FUNC18_OE_SEL_S  10
+/** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC18_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC18_OE_INV_SEL_M  (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S)
+#define GPIO_FUNC18_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC18_OE_INV_SEL_S  11
+
+/** GPIO_FUNC19_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO19 output
+ */
+#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb40)
+/** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO19.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC19_OUT_SEL    0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_M  (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S)
+#define GPIO_FUNC19_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC19_OUT_SEL_S  0
+/** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC19_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S)
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC19_OE_SEL    (BIT(10))
+#define GPIO_FUNC19_OE_SEL_M  (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S)
+#define GPIO_FUNC19_OE_SEL_V  0x00000001U
+#define GPIO_FUNC19_OE_SEL_S  10
+/** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC19_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC19_OE_INV_SEL_M  (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S)
+#define GPIO_FUNC19_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC19_OE_INV_SEL_S  11
+
+/** GPIO_FUNC20_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO20 output
+ */
+#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb44)
+/** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO20.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC20_OUT_SEL    0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_M  (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S)
+#define GPIO_FUNC20_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC20_OUT_SEL_S  0
+/** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC20_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S)
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC20_OE_SEL    (BIT(10))
+#define GPIO_FUNC20_OE_SEL_M  (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S)
+#define GPIO_FUNC20_OE_SEL_V  0x00000001U
+#define GPIO_FUNC20_OE_SEL_S  10
+/** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC20_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC20_OE_INV_SEL_M  (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S)
+#define GPIO_FUNC20_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC20_OE_INV_SEL_S  11
+
+/** GPIO_FUNC21_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO21 output
+ */
+#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb48)
+/** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO21.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC21_OUT_SEL    0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_M  (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S)
+#define GPIO_FUNC21_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC21_OUT_SEL_S  0
+/** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC21_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S)
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC21_OE_SEL    (BIT(10))
+#define GPIO_FUNC21_OE_SEL_M  (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S)
+#define GPIO_FUNC21_OE_SEL_V  0x00000001U
+#define GPIO_FUNC21_OE_SEL_S  10
+/** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC21_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC21_OE_INV_SEL_M  (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S)
+#define GPIO_FUNC21_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC21_OE_INV_SEL_S  11
+
+/** GPIO_FUNC22_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO22 output
+ */
+#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb4c)
+/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO22.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC22_OUT_SEL    0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_M  (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
+#define GPIO_FUNC22_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC22_OUT_SEL_S  0
+/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC22_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC22_OE_SEL    (BIT(10))
+#define GPIO_FUNC22_OE_SEL_M  (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
+#define GPIO_FUNC22_OE_SEL_V  0x00000001U
+#define GPIO_FUNC22_OE_SEL_S  10
+/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC22_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC22_OE_INV_SEL_M  (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
+#define GPIO_FUNC22_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC22_OE_INV_SEL_S  11
+
+/** GPIO_FUNC23_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO23 output
+ */
+#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb50)
+/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO23.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC23_OUT_SEL    0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_M  (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
+#define GPIO_FUNC23_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC23_OUT_SEL_S  0
+/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC23_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC23_OE_SEL    (BIT(10))
+#define GPIO_FUNC23_OE_SEL_M  (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
+#define GPIO_FUNC23_OE_SEL_V  0x00000001U
+#define GPIO_FUNC23_OE_SEL_S  10
+/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC23_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC23_OE_INV_SEL_M  (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
+#define GPIO_FUNC23_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC23_OE_INV_SEL_S  11
+
+/** GPIO_FUNC24_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO24 output
+ */
+#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb54)
+/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO24.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC24_OUT_SEL    0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_M  (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
+#define GPIO_FUNC24_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC24_OUT_SEL_S  0
+/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC24_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC24_OE_SEL    (BIT(10))
+#define GPIO_FUNC24_OE_SEL_M  (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
+#define GPIO_FUNC24_OE_SEL_V  0x00000001U
+#define GPIO_FUNC24_OE_SEL_S  10
+/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC24_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC24_OE_INV_SEL_M  (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
+#define GPIO_FUNC24_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC24_OE_INV_SEL_S  11
+
+/** GPIO_FUNC25_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO25 output
+ */
+#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb58)
+/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO25.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 25 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC25_OUT_SEL    0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_M  (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
+#define GPIO_FUNC25_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC25_OUT_SEL_S  0
+/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC25_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 25 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC25_OE_SEL    (BIT(10))
+#define GPIO_FUNC25_OE_SEL_M  (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S)
+#define GPIO_FUNC25_OE_SEL_V  0x00000001U
+#define GPIO_FUNC25_OE_SEL_S  10
+/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC25_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC25_OE_INV_SEL_M  (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S)
+#define GPIO_FUNC25_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC25_OE_INV_SEL_S  11
+
+/** GPIO_FUNC26_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO26 output
+ */
+#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb5c)
+/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO26.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 26 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC26_OUT_SEL    0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_M  (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
+#define GPIO_FUNC26_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC26_OUT_SEL_S  0
+/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC26_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 26 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC26_OE_SEL    (BIT(10))
+#define GPIO_FUNC26_OE_SEL_M  (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S)
+#define GPIO_FUNC26_OE_SEL_V  0x00000001U
+#define GPIO_FUNC26_OE_SEL_S  10
+/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC26_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC26_OE_INV_SEL_M  (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S)
+#define GPIO_FUNC26_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC26_OE_INV_SEL_S  11
+
+/** GPIO_FUNC27_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO27 output
+ */
+#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb60)
+/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO27.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 27 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC27_OUT_SEL    0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_M  (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
+#define GPIO_FUNC27_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC27_OUT_SEL_S  0
+/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC27_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 27 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC27_OE_SEL    (BIT(10))
+#define GPIO_FUNC27_OE_SEL_M  (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S)
+#define GPIO_FUNC27_OE_SEL_V  0x00000001U
+#define GPIO_FUNC27_OE_SEL_S  10
+/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC27_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC27_OE_INV_SEL_M  (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S)
+#define GPIO_FUNC27_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC27_OE_INV_SEL_S  11
+
+/** GPIO_FUNC28_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO28 output
+ */
+#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb64)
+/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO28.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 28 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC28_OUT_SEL    0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_M  (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
+#define GPIO_FUNC28_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC28_OUT_SEL_S  0
+/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC28_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 28 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC28_OE_SEL    (BIT(10))
+#define GPIO_FUNC28_OE_SEL_M  (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S)
+#define GPIO_FUNC28_OE_SEL_V  0x00000001U
+#define GPIO_FUNC28_OE_SEL_S  10
+/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC28_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC28_OE_INV_SEL_M  (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S)
+#define GPIO_FUNC28_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC28_OE_INV_SEL_S  11
+
+/** GPIO_FUNC29_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO29 output
+ */
+#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb68)
+/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO29.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 29 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC29_OUT_SEL    0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_M  (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S)
+#define GPIO_FUNC29_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC29_OUT_SEL_S  0
+/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC29_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S)
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/** GPIO_FUNC29_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 29 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC29_OE_SEL    (BIT(10))
+#define GPIO_FUNC29_OE_SEL_M  (GPIO_FUNC29_OE_SEL_V << GPIO_FUNC29_OE_SEL_S)
+#define GPIO_FUNC29_OE_SEL_V  0x00000001U
+#define GPIO_FUNC29_OE_SEL_S  10
+/** GPIO_FUNC29_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC29_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC29_OE_INV_SEL_M  (GPIO_FUNC29_OE_INV_SEL_V << GPIO_FUNC29_OE_INV_SEL_S)
+#define GPIO_FUNC29_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC29_OE_INV_SEL_S  11
+
+/** GPIO_FUNC30_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO30 output
+ */
+#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb6c)
+/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO30.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 30 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC30_OUT_SEL    0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_M  (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S)
+#define GPIO_FUNC30_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC30_OUT_SEL_S  0
+/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC30_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S)
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/** GPIO_FUNC30_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 30 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC30_OE_SEL    (BIT(10))
+#define GPIO_FUNC30_OE_SEL_M  (GPIO_FUNC30_OE_SEL_V << GPIO_FUNC30_OE_SEL_S)
+#define GPIO_FUNC30_OE_SEL_V  0x00000001U
+#define GPIO_FUNC30_OE_SEL_S  10
+/** GPIO_FUNC30_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC30_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC30_OE_INV_SEL_M  (GPIO_FUNC30_OE_INV_SEL_V << GPIO_FUNC30_OE_INV_SEL_S)
+#define GPIO_FUNC30_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC30_OE_INV_SEL_S  11
+
+/** GPIO_FUNC31_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO31 output
+ */
+#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb70)
+/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO31.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 31 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC31_OUT_SEL    0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_M  (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S)
+#define GPIO_FUNC31_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC31_OUT_SEL_S  0
+/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC31_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S)
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/** GPIO_FUNC31_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 31 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC31_OE_SEL    (BIT(10))
+#define GPIO_FUNC31_OE_SEL_M  (GPIO_FUNC31_OE_SEL_V << GPIO_FUNC31_OE_SEL_S)
+#define GPIO_FUNC31_OE_SEL_V  0x00000001U
+#define GPIO_FUNC31_OE_SEL_S  10
+/** GPIO_FUNC31_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC31_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC31_OE_INV_SEL_M  (GPIO_FUNC31_OE_INV_SEL_V << GPIO_FUNC31_OE_INV_SEL_S)
+#define GPIO_FUNC31_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC31_OE_INV_SEL_S  11
+
+/** GPIO_FUNC32_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO32 output
+ */
+#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb74)
+/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO32.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 32 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC32_OUT_SEL    0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_M  (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S)
+#define GPIO_FUNC32_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC32_OUT_SEL_S  0
+/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC32_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S)
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/** GPIO_FUNC32_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 32 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC32_OE_SEL    (BIT(10))
+#define GPIO_FUNC32_OE_SEL_M  (GPIO_FUNC32_OE_SEL_V << GPIO_FUNC32_OE_SEL_S)
+#define GPIO_FUNC32_OE_SEL_V  0x00000001U
+#define GPIO_FUNC32_OE_SEL_S  10
+/** GPIO_FUNC32_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC32_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC32_OE_INV_SEL_M  (GPIO_FUNC32_OE_INV_SEL_V << GPIO_FUNC32_OE_INV_SEL_S)
+#define GPIO_FUNC32_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC32_OE_INV_SEL_S  11
+
+/** GPIO_FUNC33_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO33 output
+ */
+#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb78)
+/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO33.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 33 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC33_OUT_SEL    0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_M  (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S)
+#define GPIO_FUNC33_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC33_OUT_SEL_S  0
+/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC33_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S)
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/** GPIO_FUNC33_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 33 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC33_OE_SEL    (BIT(10))
+#define GPIO_FUNC33_OE_SEL_M  (GPIO_FUNC33_OE_SEL_V << GPIO_FUNC33_OE_SEL_S)
+#define GPIO_FUNC33_OE_SEL_V  0x00000001U
+#define GPIO_FUNC33_OE_SEL_S  10
+/** GPIO_FUNC33_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC33_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC33_OE_INV_SEL_M  (GPIO_FUNC33_OE_INV_SEL_V << GPIO_FUNC33_OE_INV_SEL_S)
+#define GPIO_FUNC33_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC33_OE_INV_SEL_S  11
+
+/** GPIO_FUNC34_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO34 output
+ */
+#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb7c)
+/** GPIO_FUNC34_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO34.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 34 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC34_OUT_SEL    0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_M  (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S)
+#define GPIO_FUNC34_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC34_OUT_SEL_S  0
+/** GPIO_FUNC34_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC34_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S)
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/** GPIO_FUNC34_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 34 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC34_OE_SEL    (BIT(10))
+#define GPIO_FUNC34_OE_SEL_M  (GPIO_FUNC34_OE_SEL_V << GPIO_FUNC34_OE_SEL_S)
+#define GPIO_FUNC34_OE_SEL_V  0x00000001U
+#define GPIO_FUNC34_OE_SEL_S  10
+/** GPIO_FUNC34_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC34_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC34_OE_INV_SEL_M  (GPIO_FUNC34_OE_INV_SEL_V << GPIO_FUNC34_OE_INV_SEL_S)
+#define GPIO_FUNC34_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC34_OE_INV_SEL_S  11
+
+/** GPIO_FUNC35_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO35 output
+ */
+#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb80)
+/** GPIO_FUNC35_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO35.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 35 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC35_OUT_SEL    0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_M  (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S)
+#define GPIO_FUNC35_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC35_OUT_SEL_S  0
+/** GPIO_FUNC35_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC35_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S)
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/** GPIO_FUNC35_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 35 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC35_OE_SEL    (BIT(10))
+#define GPIO_FUNC35_OE_SEL_M  (GPIO_FUNC35_OE_SEL_V << GPIO_FUNC35_OE_SEL_S)
+#define GPIO_FUNC35_OE_SEL_V  0x00000001U
+#define GPIO_FUNC35_OE_SEL_S  10
+/** GPIO_FUNC35_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC35_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC35_OE_INV_SEL_M  (GPIO_FUNC35_OE_INV_SEL_V << GPIO_FUNC35_OE_INV_SEL_S)
+#define GPIO_FUNC35_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC35_OE_INV_SEL_S  11
+
+/** GPIO_FUNC36_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO36 output
+ */
+#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb84)
+/** GPIO_FUNC36_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO36.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 36 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC36_OUT_SEL    0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_M  (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S)
+#define GPIO_FUNC36_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC36_OUT_SEL_S  0
+/** GPIO_FUNC36_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC36_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S)
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/** GPIO_FUNC36_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 36 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC36_OE_SEL    (BIT(10))
+#define GPIO_FUNC36_OE_SEL_M  (GPIO_FUNC36_OE_SEL_V << GPIO_FUNC36_OE_SEL_S)
+#define GPIO_FUNC36_OE_SEL_V  0x00000001U
+#define GPIO_FUNC36_OE_SEL_S  10
+/** GPIO_FUNC36_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC36_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC36_OE_INV_SEL_M  (GPIO_FUNC36_OE_INV_SEL_V << GPIO_FUNC36_OE_INV_SEL_S)
+#define GPIO_FUNC36_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC36_OE_INV_SEL_S  11
+
+/** GPIO_FUNC37_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO37 output
+ */
+#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb88)
+/** GPIO_FUNC37_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO37.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 37 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC37_OUT_SEL    0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_M  (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S)
+#define GPIO_FUNC37_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC37_OUT_SEL_S  0
+/** GPIO_FUNC37_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC37_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S)
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/** GPIO_FUNC37_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 37 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC37_OE_SEL    (BIT(10))
+#define GPIO_FUNC37_OE_SEL_M  (GPIO_FUNC37_OE_SEL_V << GPIO_FUNC37_OE_SEL_S)
+#define GPIO_FUNC37_OE_SEL_V  0x00000001U
+#define GPIO_FUNC37_OE_SEL_S  10
+/** GPIO_FUNC37_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC37_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC37_OE_INV_SEL_M  (GPIO_FUNC37_OE_INV_SEL_V << GPIO_FUNC37_OE_INV_SEL_S)
+#define GPIO_FUNC37_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC37_OE_INV_SEL_S  11
+
+/** GPIO_FUNC38_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO38 output
+ */
+#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb8c)
+/** GPIO_FUNC38_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO38.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 38 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC38_OUT_SEL    0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_M  (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S)
+#define GPIO_FUNC38_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC38_OUT_SEL_S  0
+/** GPIO_FUNC38_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC38_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S)
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/** GPIO_FUNC38_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 38 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC38_OE_SEL    (BIT(10))
+#define GPIO_FUNC38_OE_SEL_M  (GPIO_FUNC38_OE_SEL_V << GPIO_FUNC38_OE_SEL_S)
+#define GPIO_FUNC38_OE_SEL_V  0x00000001U
+#define GPIO_FUNC38_OE_SEL_S  10
+/** GPIO_FUNC38_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC38_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC38_OE_INV_SEL_M  (GPIO_FUNC38_OE_INV_SEL_V << GPIO_FUNC38_OE_INV_SEL_S)
+#define GPIO_FUNC38_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC38_OE_INV_SEL_S  11
+
+/** GPIO_FUNC39_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO39 output
+ */
+#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb90)
+/** GPIO_FUNC39_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO39.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 39 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC39_OUT_SEL    0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_M  (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S)
+#define GPIO_FUNC39_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC39_OUT_SEL_S  0
+/** GPIO_FUNC39_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC39_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S)
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/** GPIO_FUNC39_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 39 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC39_OE_SEL    (BIT(10))
+#define GPIO_FUNC39_OE_SEL_M  (GPIO_FUNC39_OE_SEL_V << GPIO_FUNC39_OE_SEL_S)
+#define GPIO_FUNC39_OE_SEL_V  0x00000001U
+#define GPIO_FUNC39_OE_SEL_S  10
+/** GPIO_FUNC39_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC39_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC39_OE_INV_SEL_M  (GPIO_FUNC39_OE_INV_SEL_V << GPIO_FUNC39_OE_INV_SEL_S)
+#define GPIO_FUNC39_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC39_OE_INV_SEL_S  11
+
+/** GPIO_FUNC40_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO40 output
+ */
+#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb94)
+/** GPIO_FUNC40_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO40.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 40 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC40_OUT_SEL    0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_M  (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S)
+#define GPIO_FUNC40_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC40_OUT_SEL_S  0
+/** GPIO_FUNC40_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC40_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S)
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/** GPIO_FUNC40_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 40 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC40_OE_SEL    (BIT(10))
+#define GPIO_FUNC40_OE_SEL_M  (GPIO_FUNC40_OE_SEL_V << GPIO_FUNC40_OE_SEL_S)
+#define GPIO_FUNC40_OE_SEL_V  0x00000001U
+#define GPIO_FUNC40_OE_SEL_S  10
+/** GPIO_FUNC40_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC40_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC40_OE_INV_SEL_M  (GPIO_FUNC40_OE_INV_SEL_V << GPIO_FUNC40_OE_INV_SEL_S)
+#define GPIO_FUNC40_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC40_OE_INV_SEL_S  11
+
+/** GPIO_FUNC41_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO41 output
+ */
+#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb98)
+/** GPIO_FUNC41_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO41.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 41 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC41_OUT_SEL    0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_M  (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S)
+#define GPIO_FUNC41_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC41_OUT_SEL_S  0
+/** GPIO_FUNC41_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC41_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S)
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/** GPIO_FUNC41_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 41 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC41_OE_SEL    (BIT(10))
+#define GPIO_FUNC41_OE_SEL_M  (GPIO_FUNC41_OE_SEL_V << GPIO_FUNC41_OE_SEL_S)
+#define GPIO_FUNC41_OE_SEL_V  0x00000001U
+#define GPIO_FUNC41_OE_SEL_S  10
+/** GPIO_FUNC41_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC41_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC41_OE_INV_SEL_M  (GPIO_FUNC41_OE_INV_SEL_V << GPIO_FUNC41_OE_INV_SEL_S)
+#define GPIO_FUNC41_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC41_OE_INV_SEL_S  11
+
+/** GPIO_FUNC42_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO42 output
+ */
+#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb9c)
+/** GPIO_FUNC42_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO42.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 42 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC42_OUT_SEL    0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_M  (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S)
+#define GPIO_FUNC42_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC42_OUT_SEL_S  0
+/** GPIO_FUNC42_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC42_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S)
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/** GPIO_FUNC42_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 42 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC42_OE_SEL    (BIT(10))
+#define GPIO_FUNC42_OE_SEL_M  (GPIO_FUNC42_OE_SEL_V << GPIO_FUNC42_OE_SEL_S)
+#define GPIO_FUNC42_OE_SEL_V  0x00000001U
+#define GPIO_FUNC42_OE_SEL_S  10
+/** GPIO_FUNC42_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC42_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC42_OE_INV_SEL_M  (GPIO_FUNC42_OE_INV_SEL_V << GPIO_FUNC42_OE_INV_SEL_S)
+#define GPIO_FUNC42_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC42_OE_INV_SEL_S  11
+
+/** GPIO_FUNC43_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO43 output
+ */
+#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xba0)
+/** GPIO_FUNC43_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO43.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 43 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC43_OUT_SEL    0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_M  (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S)
+#define GPIO_FUNC43_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC43_OUT_SEL_S  0
+/** GPIO_FUNC43_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC43_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S)
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/** GPIO_FUNC43_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 43 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC43_OE_SEL    (BIT(10))
+#define GPIO_FUNC43_OE_SEL_M  (GPIO_FUNC43_OE_SEL_V << GPIO_FUNC43_OE_SEL_S)
+#define GPIO_FUNC43_OE_SEL_V  0x00000001U
+#define GPIO_FUNC43_OE_SEL_S  10
+/** GPIO_FUNC43_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC43_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC43_OE_INV_SEL_M  (GPIO_FUNC43_OE_INV_SEL_V << GPIO_FUNC43_OE_INV_SEL_S)
+#define GPIO_FUNC43_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC43_OE_INV_SEL_S  11
+
+/** GPIO_FUNC44_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO44 output
+ */
+#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xba4)
+/** GPIO_FUNC44_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO44.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 44 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC44_OUT_SEL    0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_M  (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S)
+#define GPIO_FUNC44_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC44_OUT_SEL_S  0
+/** GPIO_FUNC44_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC44_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S)
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/** GPIO_FUNC44_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 44 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC44_OE_SEL    (BIT(10))
+#define GPIO_FUNC44_OE_SEL_M  (GPIO_FUNC44_OE_SEL_V << GPIO_FUNC44_OE_SEL_S)
+#define GPIO_FUNC44_OE_SEL_V  0x00000001U
+#define GPIO_FUNC44_OE_SEL_S  10
+/** GPIO_FUNC44_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC44_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC44_OE_INV_SEL_M  (GPIO_FUNC44_OE_INV_SEL_V << GPIO_FUNC44_OE_INV_SEL_S)
+#define GPIO_FUNC44_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC44_OE_INV_SEL_S  11
+
+/** GPIO_FUNC45_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO45 output
+ */
+#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xba8)
+/** GPIO_FUNC45_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO45.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 45 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC45_OUT_SEL    0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_M  (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S)
+#define GPIO_FUNC45_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC45_OUT_SEL_S  0
+/** GPIO_FUNC45_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC45_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S)
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/** GPIO_FUNC45_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 45 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC45_OE_SEL    (BIT(10))
+#define GPIO_FUNC45_OE_SEL_M  (GPIO_FUNC45_OE_SEL_V << GPIO_FUNC45_OE_SEL_S)
+#define GPIO_FUNC45_OE_SEL_V  0x00000001U
+#define GPIO_FUNC45_OE_SEL_S  10
+/** GPIO_FUNC45_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC45_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC45_OE_INV_SEL_M  (GPIO_FUNC45_OE_INV_SEL_V << GPIO_FUNC45_OE_INV_SEL_S)
+#define GPIO_FUNC45_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC45_OE_INV_SEL_S  11
+
+/** GPIO_FUNC46_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO46 output
+ */
+#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbac)
+/** GPIO_FUNC46_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO46.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 46 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC46_OUT_SEL    0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_M  (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S)
+#define GPIO_FUNC46_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC46_OUT_SEL_S  0
+/** GPIO_FUNC46_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC46_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S)
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/** GPIO_FUNC46_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 46 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC46_OE_SEL    (BIT(10))
+#define GPIO_FUNC46_OE_SEL_M  (GPIO_FUNC46_OE_SEL_V << GPIO_FUNC46_OE_SEL_S)
+#define GPIO_FUNC46_OE_SEL_V  0x00000001U
+#define GPIO_FUNC46_OE_SEL_S  10
+/** GPIO_FUNC46_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC46_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC46_OE_INV_SEL_M  (GPIO_FUNC46_OE_INV_SEL_V << GPIO_FUNC46_OE_INV_SEL_S)
+#define GPIO_FUNC46_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC46_OE_INV_SEL_S  11
+
+/** GPIO_FUNC47_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO47 output
+ */
+#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbb0)
+/** GPIO_FUNC47_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO47.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 47 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC47_OUT_SEL    0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_M  (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S)
+#define GPIO_FUNC47_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC47_OUT_SEL_S  0
+/** GPIO_FUNC47_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC47_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S)
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/** GPIO_FUNC47_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 47 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC47_OE_SEL    (BIT(10))
+#define GPIO_FUNC47_OE_SEL_M  (GPIO_FUNC47_OE_SEL_V << GPIO_FUNC47_OE_SEL_S)
+#define GPIO_FUNC47_OE_SEL_V  0x00000001U
+#define GPIO_FUNC47_OE_SEL_S  10
+/** GPIO_FUNC47_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC47_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC47_OE_INV_SEL_M  (GPIO_FUNC47_OE_INV_SEL_V << GPIO_FUNC47_OE_INV_SEL_S)
+#define GPIO_FUNC47_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC47_OE_INV_SEL_S  11
+
+/** GPIO_FUNC48_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO48 output
+ */
+#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbb4)
+/** GPIO_FUNC48_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO48.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 48 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC48_OUT_SEL    0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_M  (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S)
+#define GPIO_FUNC48_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC48_OUT_SEL_S  0
+/** GPIO_FUNC48_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC48_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S)
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/** GPIO_FUNC48_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 48 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC48_OE_SEL    (BIT(10))
+#define GPIO_FUNC48_OE_SEL_M  (GPIO_FUNC48_OE_SEL_V << GPIO_FUNC48_OE_SEL_S)
+#define GPIO_FUNC48_OE_SEL_V  0x00000001U
+#define GPIO_FUNC48_OE_SEL_S  10
+/** GPIO_FUNC48_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC48_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC48_OE_INV_SEL_M  (GPIO_FUNC48_OE_INV_SEL_V << GPIO_FUNC48_OE_INV_SEL_S)
+#define GPIO_FUNC48_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC48_OE_INV_SEL_S  11
+
+/** GPIO_FUNC49_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO49 output
+ */
+#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbb8)
+/** GPIO_FUNC49_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO49.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 49 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC49_OUT_SEL    0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_M  (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S)
+#define GPIO_FUNC49_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC49_OUT_SEL_S  0
+/** GPIO_FUNC49_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC49_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S)
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/** GPIO_FUNC49_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 49 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC49_OE_SEL    (BIT(10))
+#define GPIO_FUNC49_OE_SEL_M  (GPIO_FUNC49_OE_SEL_V << GPIO_FUNC49_OE_SEL_S)
+#define GPIO_FUNC49_OE_SEL_V  0x00000001U
+#define GPIO_FUNC49_OE_SEL_S  10
+/** GPIO_FUNC49_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC49_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC49_OE_INV_SEL_M  (GPIO_FUNC49_OE_INV_SEL_V << GPIO_FUNC49_OE_INV_SEL_S)
+#define GPIO_FUNC49_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC49_OE_INV_SEL_S  11
+
+/** GPIO_FUNC50_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO50 output
+ */
+#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbbc)
+/** GPIO_FUNC50_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO50.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 50 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC50_OUT_SEL    0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_M  (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S)
+#define GPIO_FUNC50_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC50_OUT_SEL_S  0
+/** GPIO_FUNC50_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC50_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S)
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/** GPIO_FUNC50_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 50 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC50_OE_SEL    (BIT(10))
+#define GPIO_FUNC50_OE_SEL_M  (GPIO_FUNC50_OE_SEL_V << GPIO_FUNC50_OE_SEL_S)
+#define GPIO_FUNC50_OE_SEL_V  0x00000001U
+#define GPIO_FUNC50_OE_SEL_S  10
+/** GPIO_FUNC50_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC50_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC50_OE_INV_SEL_M  (GPIO_FUNC50_OE_INV_SEL_V << GPIO_FUNC50_OE_INV_SEL_S)
+#define GPIO_FUNC50_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC50_OE_INV_SEL_S  11
+
+/** GPIO_FUNC51_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO51 output
+ */
+#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbc0)
+/** GPIO_FUNC51_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO51.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 51 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC51_OUT_SEL    0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_M  (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S)
+#define GPIO_FUNC51_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC51_OUT_SEL_S  0
+/** GPIO_FUNC51_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC51_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S)
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/** GPIO_FUNC51_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 51 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC51_OE_SEL    (BIT(10))
+#define GPIO_FUNC51_OE_SEL_M  (GPIO_FUNC51_OE_SEL_V << GPIO_FUNC51_OE_SEL_S)
+#define GPIO_FUNC51_OE_SEL_V  0x00000001U
+#define GPIO_FUNC51_OE_SEL_S  10
+/** GPIO_FUNC51_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC51_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC51_OE_INV_SEL_M  (GPIO_FUNC51_OE_INV_SEL_V << GPIO_FUNC51_OE_INV_SEL_S)
+#define GPIO_FUNC51_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC51_OE_INV_SEL_S  11
+
+/** GPIO_FUNC52_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO52 output
+ */
+#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbc4)
+/** GPIO_FUNC52_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO52.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 52 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC52_OUT_SEL    0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_M  (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S)
+#define GPIO_FUNC52_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC52_OUT_SEL_S  0
+/** GPIO_FUNC52_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC52_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S)
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/** GPIO_FUNC52_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 52 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC52_OE_SEL    (BIT(10))
+#define GPIO_FUNC52_OE_SEL_M  (GPIO_FUNC52_OE_SEL_V << GPIO_FUNC52_OE_SEL_S)
+#define GPIO_FUNC52_OE_SEL_V  0x00000001U
+#define GPIO_FUNC52_OE_SEL_S  10
+/** GPIO_FUNC52_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC52_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC52_OE_INV_SEL_M  (GPIO_FUNC52_OE_INV_SEL_V << GPIO_FUNC52_OE_INV_SEL_S)
+#define GPIO_FUNC52_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC52_OE_INV_SEL_S  11
+
+/** GPIO_FUNC53_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO53 output
+ */
+#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbc8)
+/** GPIO_FUNC53_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO53.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 53 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC53_OUT_SEL    0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_M  (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S)
+#define GPIO_FUNC53_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC53_OUT_SEL_S  0
+/** GPIO_FUNC53_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC53_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S)
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/** GPIO_FUNC53_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 53 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC53_OE_SEL    (BIT(10))
+#define GPIO_FUNC53_OE_SEL_M  (GPIO_FUNC53_OE_SEL_V << GPIO_FUNC53_OE_SEL_S)
+#define GPIO_FUNC53_OE_SEL_V  0x00000001U
+#define GPIO_FUNC53_OE_SEL_S  10
+/** GPIO_FUNC53_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC53_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC53_OE_INV_SEL_M  (GPIO_FUNC53_OE_INV_SEL_V << GPIO_FUNC53_OE_INV_SEL_S)
+#define GPIO_FUNC53_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC53_OE_INV_SEL_S  11
+
+/** GPIO_FUNC54_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO54 output
+ */
+#define GPIO_FUNC54_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbcc)
+/** GPIO_FUNC54_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO54.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 54 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC54_OUT_SEL    0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_M  (GPIO_FUNC54_OUT_SEL_V << GPIO_FUNC54_OUT_SEL_S)
+#define GPIO_FUNC54_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC54_OUT_SEL_S  0
+/** GPIO_FUNC54_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC54_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC54_OUT_INV_SEL_M  (GPIO_FUNC54_OUT_INV_SEL_V << GPIO_FUNC54_OUT_INV_SEL_S)
+#define GPIO_FUNC54_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OUT_INV_SEL_S  9
+/** GPIO_FUNC54_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 54 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC54_OE_SEL    (BIT(10))
+#define GPIO_FUNC54_OE_SEL_M  (GPIO_FUNC54_OE_SEL_V << GPIO_FUNC54_OE_SEL_S)
+#define GPIO_FUNC54_OE_SEL_V  0x00000001U
+#define GPIO_FUNC54_OE_SEL_S  10
+/** GPIO_FUNC54_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC54_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC54_OE_INV_SEL_M  (GPIO_FUNC54_OE_INV_SEL_V << GPIO_FUNC54_OE_INV_SEL_S)
+#define GPIO_FUNC54_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC54_OE_INV_SEL_S  11
+
+/** GPIO_FUNC55_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO55 output
+ */
+#define GPIO_FUNC55_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbd0)
+/** GPIO_FUNC55_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO55.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 55 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC55_OUT_SEL    0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_M  (GPIO_FUNC55_OUT_SEL_V << GPIO_FUNC55_OUT_SEL_S)
+#define GPIO_FUNC55_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC55_OUT_SEL_S  0
+/** GPIO_FUNC55_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC55_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC55_OUT_INV_SEL_M  (GPIO_FUNC55_OUT_INV_SEL_V << GPIO_FUNC55_OUT_INV_SEL_S)
+#define GPIO_FUNC55_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OUT_INV_SEL_S  9
+/** GPIO_FUNC55_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 55 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC55_OE_SEL    (BIT(10))
+#define GPIO_FUNC55_OE_SEL_M  (GPIO_FUNC55_OE_SEL_V << GPIO_FUNC55_OE_SEL_S)
+#define GPIO_FUNC55_OE_SEL_V  0x00000001U
+#define GPIO_FUNC55_OE_SEL_S  10
+/** GPIO_FUNC55_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC55_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC55_OE_INV_SEL_M  (GPIO_FUNC55_OE_INV_SEL_V << GPIO_FUNC55_OE_INV_SEL_S)
+#define GPIO_FUNC55_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC55_OE_INV_SEL_S  11
+
+/** GPIO_FUNC56_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO56 output
+ */
+#define GPIO_FUNC56_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbd4)
+/** GPIO_FUNC56_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO56.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 56 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC56_OUT_SEL    0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_M  (GPIO_FUNC56_OUT_SEL_V << GPIO_FUNC56_OUT_SEL_S)
+#define GPIO_FUNC56_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC56_OUT_SEL_S  0
+/** GPIO_FUNC56_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC56_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC56_OUT_INV_SEL_M  (GPIO_FUNC56_OUT_INV_SEL_V << GPIO_FUNC56_OUT_INV_SEL_S)
+#define GPIO_FUNC56_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OUT_INV_SEL_S  9
+/** GPIO_FUNC56_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 56 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC56_OE_SEL    (BIT(10))
+#define GPIO_FUNC56_OE_SEL_M  (GPIO_FUNC56_OE_SEL_V << GPIO_FUNC56_OE_SEL_S)
+#define GPIO_FUNC56_OE_SEL_V  0x00000001U
+#define GPIO_FUNC56_OE_SEL_S  10
+/** GPIO_FUNC56_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC56_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC56_OE_INV_SEL_M  (GPIO_FUNC56_OE_INV_SEL_V << GPIO_FUNC56_OE_INV_SEL_S)
+#define GPIO_FUNC56_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC56_OE_INV_SEL_S  11
+
+/** GPIO_FUNC57_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO57 output
+ */
+#define GPIO_FUNC57_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbd8)
+/** GPIO_FUNC57_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO57.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 57 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC57_OUT_SEL    0x000001FFU
+#define GPIO_FUNC57_OUT_SEL_M  (GPIO_FUNC57_OUT_SEL_V << GPIO_FUNC57_OUT_SEL_S)
+#define GPIO_FUNC57_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC57_OUT_SEL_S  0
+/** GPIO_FUNC57_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC57_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC57_OUT_INV_SEL_M  (GPIO_FUNC57_OUT_INV_SEL_V << GPIO_FUNC57_OUT_INV_SEL_S)
+#define GPIO_FUNC57_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_OUT_INV_SEL_S  9
+/** GPIO_FUNC57_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 57 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC57_OE_SEL    (BIT(10))
+#define GPIO_FUNC57_OE_SEL_M  (GPIO_FUNC57_OE_SEL_V << GPIO_FUNC57_OE_SEL_S)
+#define GPIO_FUNC57_OE_SEL_V  0x00000001U
+#define GPIO_FUNC57_OE_SEL_S  10
+/** GPIO_FUNC57_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC57_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC57_OE_INV_SEL_M  (GPIO_FUNC57_OE_INV_SEL_V << GPIO_FUNC57_OE_INV_SEL_S)
+#define GPIO_FUNC57_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC57_OE_INV_SEL_S  11
+
+/** GPIO_FUNC58_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO58 output
+ */
+#define GPIO_FUNC58_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbdc)
+/** GPIO_FUNC58_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO58.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 58 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC58_OUT_SEL    0x000001FFU
+#define GPIO_FUNC58_OUT_SEL_M  (GPIO_FUNC58_OUT_SEL_V << GPIO_FUNC58_OUT_SEL_S)
+#define GPIO_FUNC58_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC58_OUT_SEL_S  0
+/** GPIO_FUNC58_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC58_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC58_OUT_INV_SEL_M  (GPIO_FUNC58_OUT_INV_SEL_V << GPIO_FUNC58_OUT_INV_SEL_S)
+#define GPIO_FUNC58_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_OUT_INV_SEL_S  9
+/** GPIO_FUNC58_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 58 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC58_OE_SEL    (BIT(10))
+#define GPIO_FUNC58_OE_SEL_M  (GPIO_FUNC58_OE_SEL_V << GPIO_FUNC58_OE_SEL_S)
+#define GPIO_FUNC58_OE_SEL_V  0x00000001U
+#define GPIO_FUNC58_OE_SEL_S  10
+/** GPIO_FUNC58_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC58_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC58_OE_INV_SEL_M  (GPIO_FUNC58_OE_INV_SEL_V << GPIO_FUNC58_OE_INV_SEL_S)
+#define GPIO_FUNC58_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC58_OE_INV_SEL_S  11
+
+/** GPIO_FUNC59_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO59 output
+ */
+#define GPIO_FUNC59_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbe0)
+/** GPIO_FUNC59_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO59.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 59 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC59_OUT_SEL    0x000001FFU
+#define GPIO_FUNC59_OUT_SEL_M  (GPIO_FUNC59_OUT_SEL_V << GPIO_FUNC59_OUT_SEL_S)
+#define GPIO_FUNC59_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC59_OUT_SEL_S  0
+/** GPIO_FUNC59_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC59_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC59_OUT_INV_SEL_M  (GPIO_FUNC59_OUT_INV_SEL_V << GPIO_FUNC59_OUT_INV_SEL_S)
+#define GPIO_FUNC59_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_OUT_INV_SEL_S  9
+/** GPIO_FUNC59_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 59 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC59_OE_SEL    (BIT(10))
+#define GPIO_FUNC59_OE_SEL_M  (GPIO_FUNC59_OE_SEL_V << GPIO_FUNC59_OE_SEL_S)
+#define GPIO_FUNC59_OE_SEL_V  0x00000001U
+#define GPIO_FUNC59_OE_SEL_S  10
+/** GPIO_FUNC59_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC59_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC59_OE_INV_SEL_M  (GPIO_FUNC59_OE_INV_SEL_V << GPIO_FUNC59_OE_INV_SEL_S)
+#define GPIO_FUNC59_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC59_OE_INV_SEL_S  11
+
+/** GPIO_FUNC60_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO60 output
+ */
+#define GPIO_FUNC60_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbe4)
+/** GPIO_FUNC60_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO60.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 60 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC60_OUT_SEL    0x000001FFU
+#define GPIO_FUNC60_OUT_SEL_M  (GPIO_FUNC60_OUT_SEL_V << GPIO_FUNC60_OUT_SEL_S)
+#define GPIO_FUNC60_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC60_OUT_SEL_S  0
+/** GPIO_FUNC60_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC60_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC60_OUT_INV_SEL_M  (GPIO_FUNC60_OUT_INV_SEL_V << GPIO_FUNC60_OUT_INV_SEL_S)
+#define GPIO_FUNC60_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_OUT_INV_SEL_S  9
+/** GPIO_FUNC60_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 60 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC60_OE_SEL    (BIT(10))
+#define GPIO_FUNC60_OE_SEL_M  (GPIO_FUNC60_OE_SEL_V << GPIO_FUNC60_OE_SEL_S)
+#define GPIO_FUNC60_OE_SEL_V  0x00000001U
+#define GPIO_FUNC60_OE_SEL_S  10
+/** GPIO_FUNC60_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC60_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC60_OE_INV_SEL_M  (GPIO_FUNC60_OE_INV_SEL_V << GPIO_FUNC60_OE_INV_SEL_S)
+#define GPIO_FUNC60_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC60_OE_INV_SEL_S  11
+
+/** GPIO_FUNC61_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO61 output
+ */
+#define GPIO_FUNC61_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbe8)
+/** GPIO_FUNC61_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO61.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 61 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC61_OUT_SEL    0x000001FFU
+#define GPIO_FUNC61_OUT_SEL_M  (GPIO_FUNC61_OUT_SEL_V << GPIO_FUNC61_OUT_SEL_S)
+#define GPIO_FUNC61_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC61_OUT_SEL_S  0
+/** GPIO_FUNC61_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC61_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC61_OUT_INV_SEL_M  (GPIO_FUNC61_OUT_INV_SEL_V << GPIO_FUNC61_OUT_INV_SEL_S)
+#define GPIO_FUNC61_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_OUT_INV_SEL_S  9
+/** GPIO_FUNC61_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 61 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC61_OE_SEL    (BIT(10))
+#define GPIO_FUNC61_OE_SEL_M  (GPIO_FUNC61_OE_SEL_V << GPIO_FUNC61_OE_SEL_S)
+#define GPIO_FUNC61_OE_SEL_V  0x00000001U
+#define GPIO_FUNC61_OE_SEL_S  10
+/** GPIO_FUNC61_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC61_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC61_OE_INV_SEL_M  (GPIO_FUNC61_OE_INV_SEL_V << GPIO_FUNC61_OE_INV_SEL_S)
+#define GPIO_FUNC61_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC61_OE_INV_SEL_S  11
+
+/** GPIO_FUNC62_OUT_SEL_CFG_REG register
+ *  Configuration register for GPIO62 output
+ */
+#define GPIO_FUNC62_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xbec)
+/** GPIO_FUNC62_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
+ *  Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
+ *  output from GPIO62.
+ *  0: Select signal 0
+ *  1: Select signal 1
+ *  ......
+ *  254: Select signal 254
+ *  255: Select signal 255
+ *  Or
+ *  256: Bit 62 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
+ *  and output enable.
+ *
+ *  For the detailed signal list, see Table .
+ *  "
+ */
+#define GPIO_FUNC62_OUT_SEL    0x000001FFU
+#define GPIO_FUNC62_OUT_SEL_M  (GPIO_FUNC62_OUT_SEL_V << GPIO_FUNC62_OUT_SEL_S)
+#define GPIO_FUNC62_OUT_SEL_V  0x000001FFU
+#define GPIO_FUNC62_OUT_SEL_S  0
+/** GPIO_FUNC62_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
+ *  Configures whether or not to invert the output value.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC62_OUT_INV_SEL    (BIT(9))
+#define GPIO_FUNC62_OUT_INV_SEL_M  (GPIO_FUNC62_OUT_INV_SEL_V << GPIO_FUNC62_OUT_INV_SEL_S)
+#define GPIO_FUNC62_OUT_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_OUT_INV_SEL_S  9
+/** GPIO_FUNC62_OE_SEL : R/W; bitpos: [10]; default: 0;
+ *  Configures to select the source of output enable signal.
+ *  0: Use output enable signal from peripheral.
+ *  1: Force the output enable signal to be sourced from bit 62 of GPIO_ENABLE_REG.
+ */
+#define GPIO_FUNC62_OE_SEL    (BIT(10))
+#define GPIO_FUNC62_OE_SEL_M  (GPIO_FUNC62_OE_SEL_V << GPIO_FUNC62_OE_SEL_S)
+#define GPIO_FUNC62_OE_SEL_V  0x00000001U
+#define GPIO_FUNC62_OE_SEL_S  10
+/** GPIO_FUNC62_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
+ *  Configures whether or not to invert the output enable signal.
+ *  0: Not invert
+ *  1: Invert
+ */
+#define GPIO_FUNC62_OE_INV_SEL    (BIT(11))
+#define GPIO_FUNC62_OE_INV_SEL_M  (GPIO_FUNC62_OE_INV_SEL_V << GPIO_FUNC62_OE_INV_SEL_S)
+#define GPIO_FUNC62_OE_INV_SEL_V  0x00000001U
+#define GPIO_FUNC62_OE_INV_SEL_S  11
+
+/** GPIO_CLOCK_GATE_REG register
+ *  GPIO clock gate register
+ */
+#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8)
+/** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether or not to enable clock gate.
+ *  0: Not enable
+ *  1: Enable, the clock is free running.
+ */
+#define GPIO_CLK_EN    (BIT(0))
+#define GPIO_CLK_EN_M  (GPIO_CLK_EN_V << GPIO_CLK_EN_S)
+#define GPIO_CLK_EN_V  0x00000001U
+#define GPIO_CLK_EN_S  0
+
+/** GPIO_DATE_REG register
+ *  GPIO version register
+ */
+#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc)
+/** GPIO_DATE : R/W; bitpos: [27:0]; default: 38830416;
+ *  Version control register.
+ */
+#define GPIO_DATE    0x0FFFFFFFU
+#define GPIO_DATE_M  (GPIO_DATE_V << GPIO_DATE_S)
+#define GPIO_DATE_V  0x0FFFFFFFU
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/gpio_struct.h b/components/soc/esp32s31/register/soc/gpio_struct.h
new file mode 100644
index 00000000000..599ceccc188
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/gpio_struct.h
@@ -0,0 +1,1129 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of strap register
+ *  Strapping pin register
+ */
+typedef union {
+    struct {
+        /** strapping : RO; bitpos: [15:0]; default: 0;
+         *  Represents the values of GPIO strapping pins. (need update the description, for
+         *  example)
+         *
+         *  - bit0: invalid
+         *  - bit1: MTMS
+         *  - bit2: MTDI
+         *  - bit3: GPIO27
+         *  - bit4: GPIO28
+         *  - bit5: GPIO7
+         *  - bit6 ~ bit15: invalid
+         */
+        uint32_t strapping:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} gpio_strap_reg_t;
+
+/** Type of out register
+ *  GPIO output register
+ */
+typedef union {
+    struct {
+        /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+         *  Configures the output value of GPIO0 ~ 31 output in simple GPIO output mode.
+         *  0: Low level
+         *  1: High level
+         *  The value of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31
+         *  respectively. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t out_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out_reg_t;
+
+/** Type of out_w1ts register
+ *  GPIO output set register
+ */
+typedef union {
+    struct {
+        /** out_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ GPIO31.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_OUT_REG will be set to 1
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_OUT_REG.
+         */
+        uint32_t out_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out_w1ts_reg_t;
+
+/** Type of out_w1tc register
+ *  GPIO output clear register
+ */
+typedef union {
+    struct {
+        /** out_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~
+         *  GPIO31 output.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_OUT_REG will be cleared.
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_OUT_REG.
+         */
+        uint32_t out_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out_w1tc_reg_t;
+
+/** Type of out1 register
+ *  GPIO output register
+ */
+typedef union {
+    struct {
+        /** out1_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0;
+         *  Configures the output value of GPIO32 ~ 63 output in simple GPIO output mode.
+         *  0: Low level
+         *  1: High level
+         *  The value of bit32 ~ bit63 correspond to the output value of GPIO32 ~ GPIO63
+         *  respectively. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t out1_data_orig:32;
+    };
+    uint32_t val;
+} gpio_out1_reg_t;
+
+/** Type of out1_w1ts register
+ *  GPIO output set register
+ */
+typedef union {
+    struct {
+        /** out1_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the output register GPIO_OUT1_REG of GPIO32 ~
+         *  GPIO63.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_OUT1_REG will be set to 1
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_OUT1_REG.
+         */
+        uint32_t out1_w1ts:32;
+    };
+    uint32_t val;
+} gpio_out1_w1ts_reg_t;
+
+/** Type of out1_w1tc register
+ *  GPIO output clear register
+ */
+typedef union {
+    struct {
+        /** out1_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the output register GPIO_OUT1_REG of GPIO32 ~
+         *  GPIO63 output.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_OUT1_REG will be cleared.
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_OUT1_REG.
+         */
+        uint32_t out1_w1tc:32;
+    };
+    uint32_t val;
+} gpio_out1_w1tc_reg_t;
+
+/** Type of out2 register
+ *  GPIO output register
+ */
+typedef union {
+    struct {
+        /** out2_data_orig : R/W/SC/WTC; bitpos: [2:0]; default: 0;
+         *  Configures the output value of GPIO64 ~ 66 output in simple GPIO output mode.
+         *  0: Low level
+         *  1: High level
+         *  The value of bit64 ~ bit66 correspond to the output value of GPIO64 ~ GPIO66
+         *  respectively. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t out2_data_orig:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_out2_reg_t;
+
+/** Type of out2_w1ts register
+ *  GPIO output set register
+ */
+typedef union {
+    struct {
+        /** out2_w1ts : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to set the output register GPIO_OUT2_REG of GPIO64 ~
+         *  GPIO66.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_OUT2_REG will be set to 1
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_OUT2_REG.
+         */
+        uint32_t out2_w1ts:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_out2_w1ts_reg_t;
+
+/** Type of out2_w1tc register
+ *  GPIO output clear register
+ */
+typedef union {
+    struct {
+        /** out2_w1tc : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to clear the output register GPIO_OUT2_REG of GPIO64 ~
+         *  GPIO66 output.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_OUT2_REG will be cleared.
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_OUT2_REG.
+         */
+        uint32_t out2_w1tc:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_out2_w1tc_reg_t;
+
+/** Type of enable register
+ *  GPIO output enable register
+ */
+typedef union {
+    struct {
+        /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to enable the output of GPIO0 ~ GPIO31.
+         *  0: Not enable
+         *  1: Enable
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t enable_data:32;
+    };
+    uint32_t val;
+} gpio_enable_reg_t;
+
+/** Type of enable_w1ts register
+ *  GPIO output enable set register
+ */
+typedef union {
+    struct {
+        /** enable_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the output enable register GPIO_ENABLE_REG of
+         *  GPIO0 ~ GPIO31.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_ENABLE_REG will be set to 1
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_ENABLE_REG.
+         */
+        uint32_t enable_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable_w1ts_reg_t;
+
+/** Type of enable_w1tc register
+ *  GPIO output enable clear register
+ */
+typedef union {
+    struct {
+        /** enable_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the output enable register GPIO_ENABLE_REG of
+         *  GPIO0 ~ GPIO31.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_ENABLE_REG will be cleared
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_ENABLE_REG.
+         */
+        uint32_t enable_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable_w1tc_reg_t;
+
+/** Type of enable1 register
+ *  GPIO output enable register
+ */
+typedef union {
+    struct {
+        /** enable1_data : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to enable the output of GPIO32 ~ GPIO63.
+         *  0: Not enable
+         *  1: Enable
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t enable1_data:32;
+    };
+    uint32_t val;
+} gpio_enable1_reg_t;
+
+/** Type of enable1_w1ts register
+ *  GPIO output enable set register
+ */
+typedef union {
+    struct {
+        /** enable1_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the output enable register GPIO_ENABLE1_REG of
+         *  GPIO32 ~ GPIO63.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_ENABLE1_REG will be set to 1
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_ENABLE1_REG.
+         */
+        uint32_t enable1_w1ts:32;
+    };
+    uint32_t val;
+} gpio_enable1_w1ts_reg_t;
+
+/** Type of enable1_w1tc register
+ *  GPIO output enable clear register
+ */
+typedef union {
+    struct {
+        /** enable1_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the output enable register GPIO_ENABLE1_REG of
+         *  GPIO32 ~ GPIO63.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_ENABLE1_REG will be cleared
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_ENABLE1_REG.
+         */
+        uint32_t enable1_w1tc:32;
+    };
+    uint32_t val;
+} gpio_enable1_w1tc_reg_t;
+
+/** Type of enable2 register
+ *  GPIO output enable register
+ */
+typedef union {
+    struct {
+        /** enable2_data : R/W/WTC; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to enable the output of GPIO64 ~ GPIO66.
+         *  0: Not enable
+         *  1: Enable
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t enable2_data:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_enable2_reg_t;
+
+/** Type of enable2_w1ts register
+ *  GPIO output enable set register
+ */
+typedef union {
+    struct {
+        /** enable2_w1ts : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to set the output enable register GPIO_ENABLE2_REG of
+         *  GPIO64 ~ GPIO66.
+         *  0: Not set
+         *  1: The corresponding bit in GPIO_ENABLE2_REG will be set to 1
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to set GPIO_ENABLE2_REG.
+         */
+        uint32_t enable2_w1ts:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_enable2_w1ts_reg_t;
+
+/** Type of enable2_w1tc register
+ *  GPIO output enable clear register
+ */
+typedef union {
+    struct {
+        /** enable2_w1tc : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to clear the output enable register GPIO_ENABLE2_REG of
+         *  GPIO64 ~ GPIO66.
+         *  0: Not clear
+         *  1: The corresponding bit in GPIO_ENABLE2_REG will be cleared
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  Recommended operation: use this register to clear GPIO_ENABLE2_REG.
+         */
+        uint32_t enable2_w1tc:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_enable2_w1tc_reg_t;
+
+/** Type of in register
+ *  GPIO input register
+ */
+typedef union {
+    struct {
+        /** in_data_next : RO; bitpos: [31:0]; default: 0;
+         *  Represents the input value of GPIO0 ~ GPIO31. Each bit represents a pin input value:
+         *  0: Low level
+         *  1: High level
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t in_data_next:32;
+    };
+    uint32_t val;
+} gpio_in_reg_t;
+
+/** Type of in1 register
+ *  GPIO input register
+ */
+typedef union {
+    struct {
+        /** in1_data_next : RO; bitpos: [31:0]; default: 0;
+         *  Represents the input value of GPIO32 ~ GPIO63. Each bit represents a pin input
+         *  value:
+         *  0: Low level
+         *  1: High level
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t in1_data_next:32;
+    };
+    uint32_t val;
+} gpio_in1_reg_t;
+
+/** Type of in2 register
+ *  GPIO input register
+ */
+typedef union {
+    struct {
+        /** in2_data_next : RO; bitpos: [2:0]; default: 0;
+         *  Represents the input value of GPIO64 ~ GPIO66. Each bit represents a pin input
+         *  value:
+         *  0: Low level
+         *  1: High level
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         */
+        uint32_t in2_data_next:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_in2_reg_t;
+
+
+/** Group: Interrupt Status Registers */
+/** Type of status register
+ *  GPIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  The interrupt status of GPIO0 ~ GPIO31, can be configured by the software.
+         *
+         *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  - Each bit represents the status of its corresponding GPIO:
+         *
+         *  - 0: Represents the GPIO does not generate the interrupt configured by
+         *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+         *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+         *  or this bit is configured to 1 by the software.
+         *
+         */
+        uint32_t status_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status_reg_t;
+
+/** Type of status_w1ts register
+ *  GPIO interrupt status set register
+ */
+typedef union {
+    struct {
+        /** status_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the interrupt status register
+         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
+         *
+         *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
+         *  register to set GPIO_STATUS_INTERRUPT.
+         */
+        uint32_t status_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status_w1ts_reg_t;
+
+/** Type of status_w1tc register
+ *  GPIO interrupt status clear register
+ */
+typedef union {
+    struct {
+        /** status_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the interrupt status register
+         *  GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO31.
+         *
+         *  - Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
+         *  register to clear GPIO_STATUS_INTERRUPT.
+         */
+        uint32_t status_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status_w1tc_reg_t;
+
+/** Type of status1 register
+ *  GPIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** status1_interrupt : R/W/WTC; bitpos: [31:0]; default: 0;
+         *  The interrupt status of GPIO32 ~ GPIO63, can be configured by the software.
+         *
+         *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  - Each bit represents the status of its corresponding GPIO:
+         *
+         *  - 0: Represents the GPIO does not generate the interrupt configured by
+         *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+         *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+         *  or this bit is configured to 1 by the software.
+         *
+         */
+        uint32_t status1_interrupt:32;
+    };
+    uint32_t val;
+} gpio_status1_reg_t;
+
+/** Type of status1_w1ts register
+ *  GPIO interrupt status set register
+ */
+typedef union {
+    struct {
+        /** status1_w1ts : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to set the interrupt status register
+         *  GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO63.
+         *
+         *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS1_INTERRUPT will be set to 1. \item Recommended operation: use this
+         *  register to set GPIO_STATUS1_INTERRUPT.
+         */
+        uint32_t status1_w1ts:32;
+    };
+    uint32_t val;
+} gpio_status1_w1ts_reg_t;
+
+/** Type of status1_w1tc register
+ *  GPIO interrupt status clear register
+ */
+typedef union {
+    struct {
+        /** status1_w1tc : WT; bitpos: [31:0]; default: 0;
+         *  Configures whether or not to clear the interrupt status register
+         *  GPIO_STATUS1_INTERRUPT of GPIO32 ~ GPIO63.
+         *
+         *  - Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS1_INTERRUPT will be cleared. \item Recommended operation: use this
+         *  register to clear GPIO_STATUS1_INTERRUPT.
+         */
+        uint32_t status1_w1tc:32;
+    };
+    uint32_t val;
+} gpio_status1_w1tc_reg_t;
+
+/** Type of status2 register
+ *  GPIO interrupt status register
+ */
+typedef union {
+    struct {
+        /** status2_interrupt : R/W/WTC; bitpos: [2:0]; default: 0;
+         *  The interrupt status of GPIO64 ~ GPIO66, can be configured by the software.
+         *
+         *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  - Each bit represents the status of its corresponding GPIO:
+         *
+         *  - 0: Represents the GPIO does not generate the interrupt configured by
+         *  GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
+         *  - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE,
+         *  or this bit is configured to 1 by the software.
+         *
+         */
+        uint32_t status2_interrupt:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_status2_reg_t;
+
+/** Type of status2_w1ts register
+ *  GPIO interrupt status set register
+ */
+typedef union {
+    struct {
+        /** status2_w1ts : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to set the interrupt status register
+         *  GPIO_STATUS2_INTERRUPT of GPIO64 ~ GPIO66.
+         *
+         *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS2_INTERRUPT will be set to 1. \item Recommended operation: use this
+         *  register to set GPIO_STATUS2_INTERRUPT.
+         */
+        uint32_t status2_w1ts:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_status2_w1ts_reg_t;
+
+/** Type of status2_w1tc register
+ *  GPIO interrupt status clear register
+ */
+typedef union {
+    struct {
+        /** status2_w1tc : WT; bitpos: [2:0]; default: 0;
+         *  Configures whether or not to clear the interrupt status register
+         *  GPIO_STATUS2_INTERRUPT of GPIO64 ~ GPIO66.
+         *
+         *  - Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid.
+         *  - If the value 1 is written to a bit here, the corresponding bit in
+         *  GPIO_STATUS2_INTERRUPT will be cleared. \item Recommended operation: use this
+         *  register to clear GPIO_STATUS2_INTERRUPT.
+         */
+        uint32_t status2_w1tc:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_status2_w1tc_reg_t;
+
+/** Type of int_0 register
+ *  GPIO_INT_0 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_0 interrupt status of GPIO0 ~ GPIO31. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_0 interrupt is enabled.
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_0:32;
+    };
+    uint32_t val;
+} gpio_int_0_reg_t;
+
+/** Type of int_1 register
+ *  GPIO_INT_1 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_1 interrupt status of GPIO0 ~ GPIO31. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_1 interrupt is enabled.
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_1:32;
+    };
+    uint32_t val;
+} gpio_int_1_reg_t;
+
+/** Type of int_2 register
+ *  GPIO_INT_2 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_2 interrupt status of GPIO0 ~ GPIO31. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_2 interrupt is enabled.
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_2:32;
+    };
+    uint32_t val;
+} gpio_int_2_reg_t;
+
+/** Type of int_3 register
+ *  GPIO_INT_3 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_3 interrupt status of GPIO0 ~ GPIO31. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_3 interrupt is enabled.
+         *  Bit0 ~ bit31 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_3:32;
+    };
+    uint32_t val;
+} gpio_int_3_reg_t;
+
+/** Type of int_01 register
+ *  GPIO_INT_0 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_01 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_0 interrupt status of GPIO32 ~ GPIO63. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_0 interrupt is enabled.
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_01:32;
+    };
+    uint32_t val;
+} gpio_int_01_reg_t;
+
+/** Type of int_11 register
+ *  GPIO_INT_1 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_11 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_1 interrupt status of GPIO32 ~ GPIO63. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_1 interrupt is enabled.
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_11:32;
+    };
+    uint32_t val;
+} gpio_int_11_reg_t;
+
+/** Type of int_21 register
+ *  GPIO_INT_2 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_21 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_2 interrupt status of GPIO32 ~ GPIO63. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_2 interrupt is enabled.
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_21:32;
+    };
+    uint32_t val;
+} gpio_int_21_reg_t;
+
+/** Type of int_31 register
+ *  GPIO_INT_3 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_31 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the GPIO_INT_3 interrupt status of GPIO32 ~ GPIO63. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_3 interrupt is enabled.
+         *  Bit32 ~ bit63 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_31:32;
+    };
+    uint32_t val;
+} gpio_int_31_reg_t;
+
+/** Type of int_02 register
+ *  GPIO_INT_0 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_02 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the GPIO_INT_0 interrupt status of GPIO64 ~ GPIO66. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_0 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_0 interrupt is enabled.
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_02:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_int_02_reg_t;
+
+/** Type of int_12 register
+ *  GPIO_INT_1 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_12 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the GPIO_INT_1 interrupt status of GPIO64 ~ GPIO66. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_1 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_1 interrupt is enabled.
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_12:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_int_12_reg_t;
+
+/** Type of int_22 register
+ *  GPIO_INT_2 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_22 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the GPIO_INT_2 interrupt status of GPIO64 ~ GPIO66. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_2 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_2 interrupt is enabled.
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_22:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_int_22_reg_t;
+
+/** Type of int_32 register
+ *  GPIO_INT_3 interrupt status register
+ */
+typedef union {
+    struct {
+        /** int_32 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the GPIO_INT_3 interrupt status of GPIO64 ~ GPIO66. Each bit
+         *  represents:(need update in different project)
+         *  0: Represents GPIO_INT_3 interrupt is not enabled, or the GPIO does not generate
+         *  the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE
+         *  after the GPIO_INT_3 interrupt is enabled.
+         *  Bit64 ~ bit66 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. This
+         *  interrupt status is corresponding to the bit in GPIO_STATUS2_REG when assert (high)
+         *  enable signal (bit13 of GPIO_PIN$n_REG).
+         */
+        uint32_t int_32:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_int_32_reg_t;
+
+/** Type of status_next register
+ *  GPIO interrupt source register
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next : RO; bitpos: [31:0]; default: 0;
+         *  Represents the interrupt source signal of GPIO0 ~ GPIO31.
+         *  Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO31. Bitxx ~ bitxx is invalid. Each
+         *  bit represents:
+         *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+         *  sensitive interrupt and any edge interrupt.
+         */
+        uint32_t status_interrupt_next:32;
+    };
+    uint32_t val;
+} gpio_status_next_reg_t;
+
+/** Type of status_next1 register
+ *  GPIO interrupt source register
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the interrupt source signal of GPIO32 ~ GPIO63.
+         *  Bit0 ~ bit24 are corresponding to GPIO32 ~ GPIO63. Bitxx ~ bitxx is invalid. Each
+         *  bit represents:
+         *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+         *  sensitive interrupt and any edge interrupt.
+         */
+        uint32_t status_interrupt_next1:32;
+    };
+    uint32_t val;
+} gpio_status_next1_reg_t;
+
+/** Type of status_next2 register
+ *  GPIO interrupt source register
+ */
+typedef union {
+    struct {
+        /** status_interrupt_next2 : RO; bitpos: [2:0]; default: 0;
+         *  Represents the interrupt source signal of GPIO64 ~ GPIO66.
+         *  Bit0 ~ bit24 are corresponding to GPIO64 ~ GPIO66. Bitxx ~ bitxx is invalid. Each
+         *  bit represents:
+         *  0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.
+         *  The interrupt could be rising edge interrupt, falling edge interrupt, level
+         *  sensitive interrupt and any edge interrupt.
+         */
+        uint32_t status_interrupt_next2:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} gpio_status_next2_reg_t;
+
+
+/** Group: Pin Configuration Registers */
+/** Type of pinn register
+ *  GPIOn configuration register
+ */
+typedef union {
+    struct {
+        /** sync2_bypass : R/W; bitpos: [1:0]; default: 0;
+         *  set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync2_bypass:2;
+        /** pad_driver : R/W; bitpos: [2]; default: 0;
+         *  set this bit to select pad driver. 1:open-drain. 0:normal.
+         */
+        uint32_t pad_driver:1;
+        /** sync1_bypass : R/W; bitpos: [4:3]; default: 0;
+         *  set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at
+         *  posedge.
+         */
+        uint32_t sync1_bypass:2;
+        uint32_t reserved_5:2;
+        /** pinn_int_type : R/W; bitpos: [9:7]; default: 0;
+         *  Configures GPIO interrupt type.
+         *  0: GPIO interrupt disabled
+         *  1: Rising edge trigger
+         *  2: Falling edge trigger
+         *  3: Any edge trigger
+         *  4: Low level trigger
+         *  5: High level trigger
+         */
+        uint32_t int_type:3;
+        /** wakeup_enable : R/W; bitpos: [10]; default: 0;
+         *  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+         */
+        uint32_t wakeup_enable:1;
+        uint32_t reserved_11:2;
+        /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0;
+         *  Configures whether or not to enable gpio_int_0 or gpio_int_1 or gpio_int_2 or
+         *  gpio_int_3(need update in different project).
+         *
+         *  - bit13: Configures whether or not to enable gpio_int_0(need update in different
+         *  project):
+         *  0: Disable
+         *  1: Enable
+         *  - bit14: Configures whether or not to enable gpio_int_1(need update in different
+         *  project):
+         *  0: Disable
+         *  1: Enable
+         *  - bit15: Configures whether or not to enable gpio_int_2(need update in different
+         *  project):
+         *  0: Disable
+         *  1: Enable
+         *  - bit16: Configures whether or not to enable gpio_int_3(need update in different
+         *  project):
+         *  0: Disable
+         *  1: Enable
+         *  - bit17: invalid
+         */
+        uint32_t int_ena:5;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} gpio_pin_reg_t;
+
+/** Type of func_in_sel_cfg register
+ *  GPIO input function configuration register
+ */
+typedef union {
+    struct {
+        /** in_sel : R/W; bitpos: [7:0]; default: 63;
+         *  set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always
+         *  high level. s=0x3E: set this port always low level.
+         */
+        uint32_t in_sel:8;
+        /** in_inv_sel : R/W; bitpos: [8]; default: 0;
+         *  set this bit to invert input signal. 1:invert. 0:not invert.
+         */
+        uint32_t in_inv_sel:1;
+        /** sig_in_sel : R/W; bitpos: [9]; default: 0;
+         *  set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO.
+         */
+        uint32_t sig_in_sel:1;
+        uint32_t reserved_9:22;
+    };
+    uint32_t val;
+} gpio_func_in_sel_cfg_reg_t;
+
+/** Type of funcb_in_sel_cfg register
+ *  Configuration register for input signal b
+ */
+typedef union {
+    struct {
+        /** out_sel : R/W/SC; bitpos: [8:0]; default: 256;
+         *  The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255:
+         *  output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+         *  GPIO_OUT_REG[n].
+         */
+        uint32_t out_sel:9;
+        /** out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
+         *  set this bit to invert output signal.1:invert.0:not invert.
+         */
+        uint32_t out_inv_sel:1;
+        /** oen_sel : R/W; bitpos: [10]; default: 0;
+         *  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+         *  enable signal.0:use peripheral output enable signal.
+         */
+        uint32_t oen_sel:1;
+        /** oen_inv_sel : R/W; bitpos: [11]; default: 0;
+         *  set this bit to invert output enable signal.1:invert.0:not invert.
+         */
+        uint32_t oen_inv_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} gpio_func_out_sel_cfg_reg_t;
+
+
+/** Group: Clock Gate Register */
+/** Type of clock_gate register
+ *  GPIO clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether or not to enable clock gate.
+         *  0: Not enable
+         *  1: Enable, the clock is free running.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} gpio_clock_gate_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  GPIO version register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38830416;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} gpio_date_reg_t;
+
+typedef struct gpio_dev_t {
+    volatile gpio_strap_reg_t strap;
+    volatile gpio_out_reg_t out;
+    volatile gpio_out_w1ts_reg_t out_w1ts;
+    volatile gpio_out_w1tc_reg_t out_w1tc;
+    volatile gpio_out1_reg_t out1;
+    volatile gpio_out1_w1ts_reg_t out1_w1ts;
+    volatile gpio_out1_w1tc_reg_t out1_w1tc;
+    volatile gpio_out2_reg_t out2;
+    volatile gpio_out2_w1ts_reg_t out2_w1ts;
+    volatile gpio_out2_w1tc_reg_t out2_w1tc;
+    uint32_t reserved_028[3];
+    volatile gpio_enable_reg_t enable;
+    volatile gpio_enable_w1ts_reg_t enable_w1ts;
+    volatile gpio_enable_w1tc_reg_t enable_w1tc;
+    volatile gpio_enable1_reg_t enable1;
+    volatile gpio_enable1_w1ts_reg_t enable1_w1ts;
+    volatile gpio_enable1_w1tc_reg_t enable1_w1tc;
+    volatile gpio_enable2_reg_t enable2;
+    volatile gpio_enable2_w1ts_reg_t enable2_w1ts;
+    volatile gpio_enable2_w1tc_reg_t enable2_w1tc;
+    uint32_t reserved_058[3];
+    volatile gpio_in_reg_t in;
+    volatile gpio_in1_reg_t in1;
+    volatile gpio_in2_reg_t in2;
+    uint32_t reserved_070;
+    volatile gpio_status_reg_t status;
+    volatile gpio_status_w1ts_reg_t status_w1ts;
+    volatile gpio_status_w1tc_reg_t status_w1tc;
+    volatile gpio_status1_reg_t status1;
+    volatile gpio_status1_w1ts_reg_t status1_w1ts;
+    volatile gpio_status1_w1tc_reg_t status1_w1tc;
+    volatile gpio_status2_reg_t status2;
+    volatile gpio_status2_w1ts_reg_t status2_w1ts;
+    volatile gpio_status2_w1tc_reg_t status2_w1tc;
+    uint32_t reserved_098[3];
+    volatile gpio_int_0_reg_t intr_0;
+    volatile gpio_int_1_reg_t intr_1;
+    volatile gpio_int_2_reg_t intr_2;
+    volatile gpio_int_3_reg_t intr_3;
+    volatile gpio_int_01_reg_t intr_01;
+    volatile gpio_int_11_reg_t intr_11;
+    volatile gpio_int_21_reg_t intr_21;
+    volatile gpio_int_31_reg_t intr_31;
+    volatile gpio_int_02_reg_t int_02;
+    volatile gpio_int_12_reg_t int_12;
+    volatile gpio_int_22_reg_t int_22;
+    volatile gpio_int_32_reg_t int_32;
+    uint32_t reserved_0d4[4];
+    volatile gpio_status_next_reg_t status_next;
+    volatile gpio_status_next1_reg_t status_next1;
+    volatile gpio_status_next2_reg_t status_next2;
+    uint32_t reserved_0f0;
+    volatile gpio_pin_reg_t pin[63];
+    uint32_t reserved_200[65];
+    volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256];
+    uint32_t reserved_6f4[256];
+    volatile gpio_func_out_sel_cfg_reg_t func_out_sel_cfg[63];
+    uint32_t reserved_bf0[130];
+    volatile gpio_clock_gate_reg_t clock_gate;
+    volatile gpio_date_reg_t date;
+} gpio_dev_t;
+
+extern gpio_dev_t GPIO;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(gpio_dev_t) == 0xe00, "Invalid size of gpio_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hmac_reg.h b/components/soc/esp32s31/register/soc/hmac_reg.h
new file mode 100644
index 00000000000..ad45045248f
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hmac_reg.h
@@ -0,0 +1,294 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HMAC_SET_START_REG register
+ *  HMAC start control register
+ */
+#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
+/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable HMAC.
+ *
+ *  0: Disable HMAC
+ *
+ *  1: Enable HMAC
+ */
+#define HMAC_SET_START    (BIT(0))
+#define HMAC_SET_START_M  (HMAC_SET_START_V << HMAC_SET_START_S)
+#define HMAC_SET_START_V  0x00000001U
+#define HMAC_SET_START_S  0
+
+/** HMAC_SET_PARA_PURPOSE_REG register
+ *  HMAC parameter configuration register
+ */
+#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
+/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
+ *  Configures the HMAC purpose, refer to the Table . "
+ */
+#define HMAC_PURPOSE_SET    0x0000000FU
+#define HMAC_PURPOSE_SET_M  (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
+#define HMAC_PURPOSE_SET_V  0x0000000FU
+#define HMAC_PURPOSE_SET_S  0
+
+/** HMAC_SET_PARA_KEY_REG register
+ *  HMAC parameters configuration register
+ */
+#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
+/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
+ *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+ *  selected key to this field.
+ */
+#define HMAC_KEY_SET    0x00000007U
+#define HMAC_KEY_SET_M  (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
+#define HMAC_KEY_SET_V  0x00000007U
+#define HMAC_KEY_SET_S  0
+
+/** HMAC_SET_PARA_FINISH_REG register
+ *  HMAC configuration completion register
+ */
+#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
+/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to finish HMAC configuration.
+ *
+ *  0: No effect
+ *
+ *  1: Finish configuration
+ */
+#define HMAC_SET_PARA_END    (BIT(0))
+#define HMAC_SET_PARA_END_M  (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
+#define HMAC_SET_PARA_END_V  0x00000001U
+#define HMAC_SET_PARA_END_S  0
+
+/** HMAC_SET_MESSAGE_ONE_REG register
+ *  HMAC message control register
+ */
+#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
+/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
+ *  Calls SHA to calculate one message block.
+ */
+#define HMAC_SET_TEXT_ONE    (BIT(0))
+#define HMAC_SET_TEXT_ONE_M  (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
+#define HMAC_SET_TEXT_ONE_V  0x00000001U
+#define HMAC_SET_TEXT_ONE_S  0
+
+/** HMAC_SET_MESSAGE_ING_REG register
+ *  HMAC message continue register
+ */
+#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
+/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not there are unprocessed message blocks.
+ *
+ *  0: No unprocessed message block
+ *
+ *  1: There are still some message blocks to be processed.
+ */
+#define HMAC_SET_TEXT_ING    (BIT(0))
+#define HMAC_SET_TEXT_ING_M  (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
+#define HMAC_SET_TEXT_ING_V  0x00000001U
+#define HMAC_SET_TEXT_ING_S  0
+
+/** HMAC_SET_MESSAGE_END_REG register
+ *  HMAC message end register
+ */
+#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
+/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to start hardware padding.
+ *
+ *  0: No effect
+ *
+ *  1: Start hardware padding
+ */
+#define HMAC_SET_TEXT_END    (BIT(0))
+#define HMAC_SET_TEXT_END_M  (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
+#define HMAC_SET_TEXT_END_V  0x00000001U
+#define HMAC_SET_TEXT_END_S  0
+
+/** HMAC_SET_RESULT_FINISH_REG register
+ *  HMAC result reading finish register
+ */
+#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
+/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
+ *  Configures whether to exit upstream mode and clear calculation results.
+ *
+ *  0: Not exit
+ *
+ *  1: Exit upstream mode and clear calculation results.
+ */
+#define HMAC_SET_RESULT_END    (BIT(0))
+#define HMAC_SET_RESULT_END_M  (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
+#define HMAC_SET_RESULT_END_V  0x00000001U
+#define HMAC_SET_RESULT_END_S  0
+
+/** HMAC_SET_INVALIDATE_JTAG_REG register
+ *  Invalidate JTAG result register
+ */
+#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
+/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results when re-enabling JTAG in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_JTAG    (BIT(0))
+#define HMAC_SET_INVALIDATE_JTAG_M  (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
+#define HMAC_SET_INVALIDATE_JTAG_V  0x00000001U
+#define HMAC_SET_INVALIDATE_JTAG_S  0
+
+/** HMAC_SET_INVALIDATE_DS_REG register
+ *  Invalidate digital signature result register
+ */
+#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
+/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear calculation results of the DS module in
+ *  downstream mode.
+ *
+ *  0: Not clear
+ *
+ *  1: Clear calculation results
+ */
+#define HMAC_SET_INVALIDATE_DS    (BIT(0))
+#define HMAC_SET_INVALIDATE_DS_M  (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
+#define HMAC_SET_INVALIDATE_DS_V  0x00000001U
+#define HMAC_SET_INVALIDATE_DS_S  0
+
+/** HMAC_QUERY_ERROR_REG register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
+/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not an HMAC key matches the purpose.
+ *
+ *  0: Match
+ *
+ *  1: Error
+ */
+#define HMAC_QUREY_CHECK    (BIT(0))
+#define HMAC_QUREY_CHECK_M  (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
+#define HMAC_QUREY_CHECK_V  0x00000001U
+#define HMAC_QUREY_CHECK_S  0
+
+/** HMAC_QUERY_BUSY_REG register
+ *  Busy state of HMAC module
+ */
+#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
+/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
+ *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+ *  make sure HMAC is in an IDLE state.
+ *
+ *  0: Idle
+ *
+ *  1: HMAC is still working on the calculation
+ */
+#define HMAC_BUSY_STATE    (BIT(0))
+#define HMAC_BUSY_STATE_M  (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
+#define HMAC_BUSY_STATE_V  0x00000001U
+#define HMAC_BUSY_STATE_S  0
+
+/** HMAC_TIMEOUT_LIMIT_REG register
+ *  HMAC timeout limit configure register
+ */
+#define HMAC_TIMEOUT_LIMIT_REG (DR_REG_HMAC_BASE + 0x70)
+/** HMAC_TIMEOUT_LIMIT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  The timeout limitation for waiting sub-IP.
+ */
+#define HMAC_TIMEOUT_LIMIT    0xFFFFFFFFU
+#define HMAC_TIMEOUT_LIMIT_M  (HMAC_TIMEOUT_LIMIT_V << HMAC_TIMEOUT_LIMIT_S)
+#define HMAC_TIMEOUT_LIMIT_V  0xFFFFFFFFU
+#define HMAC_TIMEOUT_LIMIT_S  0
+
+/** HMAC_WR_MESSAGE_MEM register
+ *  Message block memory.
+ */
+#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
+#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
+
+/** HMAC_RD_RESULT_MEM register
+ *  Result from upstream.
+ */
+#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
+#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
+
+/** HMAC_SET_MESSAGE_PAD_REG register
+ *  Software padding register
+ */
+#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
+/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
+ *  Configures whether or not the padding is applied by software.
+ *
+ *  0: Not applied by software
+ *
+ *  1: Applied by software
+ */
+#define HMAC_SET_TEXT_PAD    (BIT(0))
+#define HMAC_SET_TEXT_PAD_M  (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
+#define HMAC_SET_TEXT_PAD_V  0x00000001U
+#define HMAC_SET_TEXT_PAD_S  0
+
+/** HMAC_ONE_BLOCK_REG register
+ *  One block message register
+ */
+#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
+/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
+ *  Write 1 to indicate there is only one block which already contains padding bits and
+ *  there is no need for padding.
+ */
+#define HMAC_SET_ONE_BLOCK    (BIT(0))
+#define HMAC_SET_ONE_BLOCK_M  (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
+#define HMAC_SET_ONE_BLOCK_V  0x00000001U
+#define HMAC_SET_ONE_BLOCK_S  0
+
+/** HMAC_SOFT_JTAG_CTRL_REG register
+ *  Jtag register 0.
+ */
+#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
+/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
+ *  Configures whether or not to enable JTAG authentication mode.
+ *
+ *  0: Disable
+ *
+ *  1: Enable
+ *
+ */
+#define HMAC_SOFT_JTAG_CTRL    (BIT(0))
+#define HMAC_SOFT_JTAG_CTRL_M  (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
+#define HMAC_SOFT_JTAG_CTRL_V  0x00000001U
+#define HMAC_SOFT_JTAG_CTRL_S  0
+
+/** HMAC_WR_JTAG_REG register
+ *  Re-enable JTAG register 1
+ */
+#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
+/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
+ *  Writes the comparing input used for re-enabling JTAG.
+ */
+#define HMAC_WR_JTAG    0xFFFFFFFFU
+#define HMAC_WR_JTAG_M  (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
+#define HMAC_WR_JTAG_V  0xFFFFFFFFU
+#define HMAC_WR_JTAG_S  0
+
+/** HMAC_DATE_REG register
+ *  Version control register
+ */
+#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
+/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539297817;
+ *  Hmac date information/ hmac version information.
+ */
+#define HMAC_DATE    0x3FFFFFFFU
+#define HMAC_DATE_M  (HMAC_DATE_V << HMAC_DATE_S)
+#define HMAC_DATE_V  0x3FFFFFFFU
+#define HMAC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hmac_struct.h b/components/soc/esp32s31/register/soc/hmac_struct.h
new file mode 100644
index 00000000000..6d4dadab71a
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hmac_struct.h
@@ -0,0 +1,359 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Control/Status Registers */
+/** Type of set_start register
+ *  HMAC start control register
+ */
+typedef union {
+    struct {
+        /** set_start : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable HMAC.
+         *
+         *  0: Disable HMAC
+         *
+         *  1: Enable HMAC
+         */
+        uint32_t set_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_start_reg_t;
+
+/** Type of set_para_finish register
+ *  HMAC configuration completion register
+ */
+typedef union {
+    struct {
+        /** set_para_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to finish HMAC configuration.
+         *
+         *  0: No effect
+         *
+         *  1: Finish configuration
+         */
+        uint32_t set_para_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_para_finish_reg_t;
+
+/** Type of set_message_one register
+ *  HMAC message control register
+ */
+typedef union {
+    struct {
+        /** set_text_one : WS; bitpos: [0]; default: 0;
+         *  Calls SHA to calculate one message block.
+         */
+        uint32_t set_text_one:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_one_reg_t;
+
+/** Type of set_message_ing register
+ *  HMAC message continue register
+ */
+typedef union {
+    struct {
+        /** set_text_ing : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not there are unprocessed message blocks.
+         *
+         *  0: No unprocessed message block
+         *
+         *  1: There are still some message blocks to be processed.
+         */
+        uint32_t set_text_ing:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_ing_reg_t;
+
+/** Type of set_message_end register
+ *  HMAC message end register
+ */
+typedef union {
+    struct {
+        /** set_text_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to start hardware padding.
+         *
+         *  0: No effect
+         *
+         *  1: Start hardware padding
+         */
+        uint32_t set_text_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_end_reg_t;
+
+/** Type of set_result_finish register
+ *  HMAC result reading finish register
+ */
+typedef union {
+    struct {
+        /** set_result_end : WS; bitpos: [0]; default: 0;
+         *  Configures whether to exit upstream mode and clear calculation results.
+         *
+         *  0: Not exit
+         *
+         *  1: Exit upstream mode and clear calculation results.
+         */
+        uint32_t set_result_end:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_result_finish_reg_t;
+
+/** Type of set_invalidate_jtag register
+ *  Invalidate JTAG result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results when re-enabling JTAG in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_jtag:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_jtag_reg_t;
+
+/** Type of set_invalidate_ds register
+ *  Invalidate digital signature result register
+ */
+typedef union {
+    struct {
+        /** set_invalidate_ds : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear calculation results of the DS module in
+         *  downstream mode.
+         *
+         *  0: Not clear
+         *
+         *  1: Clear calculation results
+         */
+        uint32_t set_invalidate_ds:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_invalidate_ds_reg_t;
+
+/** Type of query_error register
+ *  Stores matching results between keys generated by users and corresponding purposes
+ */
+typedef union {
+    struct {
+        /** qurey_check : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not an HMAC key matches the purpose.
+         *
+         *  0: Match
+         *
+         *  1: Error
+         */
+        uint32_t qurey_check:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_error_reg_t;
+
+/** Type of query_busy register
+ *  Busy state of HMAC module
+ */
+typedef union {
+    struct {
+        /** busy_state : RO; bitpos: [0]; default: 0;
+         *  Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
+         *  make sure HMAC is in an IDLE state.
+         *
+         *  0: Idle
+         *
+         *  1: HMAC is still working on the calculation
+         */
+        uint32_t busy_state:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_query_busy_reg_t;
+
+/** Type of set_message_pad register
+ *  Software padding register
+ */
+typedef union {
+    struct {
+        /** set_text_pad : WO; bitpos: [0]; default: 0;
+         *  Configures whether or not the padding is applied by software.
+         *
+         *  0: Not applied by software
+         *
+         *  1: Applied by software
+         */
+        uint32_t set_text_pad:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_set_message_pad_reg_t;
+
+/** Type of one_block register
+ *  One block message register
+ */
+typedef union {
+    struct {
+        /** set_one_block : WS; bitpos: [0]; default: 0;
+         *  Write 1 to indicate there is only one block which already contains padding bits and
+         *  there is no need for padding.
+         */
+        uint32_t set_one_block:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_one_block_reg_t;
+
+
+/** Group: Configuration Registers */
+/** Type of set_para_purpose register
+ *  HMAC parameter configuration register
+ */
+typedef union {
+    struct {
+        /** purpose_set : WO; bitpos: [3:0]; default: 0;
+         *  Configures the HMAC purpose, refer to the Table . "
+         */
+        uint32_t purpose_set:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hmac_set_para_purpose_reg_t;
+
+/** Type of set_para_key register
+ *  HMAC parameters configuration register
+ */
+typedef union {
+    struct {
+        /** key_set : WO; bitpos: [2:0]; default: 0;
+         *  Configures HMAC key. There are six keys with index 0~5. Write the index of the
+         *  selected key to this field.
+         */
+        uint32_t key_set:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hmac_set_para_key_reg_t;
+
+/** Type of wr_jtag register
+ *  Re-enable JTAG register 1
+ */
+typedef union {
+    struct {
+        /** wr_jtag : WO; bitpos: [31:0]; default: 0;
+         *  Writes the comparing input used for re-enabling JTAG.
+         */
+        uint32_t wr_jtag:32;
+    };
+    uint32_t val;
+} hmac_wr_jtag_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of timeout_limit register
+ *  HMAC timeout limit configure register
+ */
+typedef union {
+    struct {
+        /** timeout_limit : R/W; bitpos: [31:0]; default: 4294967295;
+         *  The timeout limitation for waiting sub-IP.
+         */
+        uint32_t timeout_limit:32;
+    };
+    uint32_t val;
+} hmac_timeout_limit_reg_t;
+
+
+/** Group: Memory Type */
+
+/** Group: Configuration Register */
+/** Type of soft_jtag_ctrl register
+ *  Jtag register 0.
+ */
+typedef union {
+    struct {
+        /** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable JTAG authentication mode.
+         *
+         *  0: Disable
+         *
+         *  1: Enable
+         *
+         */
+        uint32_t soft_jtag_ctrl:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hmac_soft_jtag_ctrl_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [29:0]; default: 539297817;
+         *  Hmac date information/ hmac version information.
+         */
+        uint32_t date:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hmac_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[16];
+    volatile hmac_set_start_reg_t set_start;
+    volatile hmac_set_para_purpose_reg_t set_para_purpose;
+    volatile hmac_set_para_key_reg_t set_para_key;
+    volatile hmac_set_para_finish_reg_t set_para_finish;
+    volatile hmac_set_message_one_reg_t set_message_one;
+    volatile hmac_set_message_ing_reg_t set_message_ing;
+    volatile hmac_set_message_end_reg_t set_message_end;
+    volatile hmac_set_result_finish_reg_t set_result_finish;
+    volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
+    volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
+    volatile hmac_query_error_reg_t query_error;
+    volatile hmac_query_busy_reg_t query_busy;
+    volatile hmac_timeout_limit_reg_t timeout_limit;
+    uint32_t reserved_074[3];
+    volatile uint32_t wr_message[16];
+    volatile uint32_t rd_result[8];
+    uint32_t reserved_0e0[4];
+    volatile hmac_set_message_pad_reg_t set_message_pad;
+    volatile hmac_one_block_reg_t one_block;
+    volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
+    volatile hmac_wr_jtag_reg_t wr_jtag;
+    uint32_t reserved_100[63];
+    volatile hmac_date_reg_t date;
+} hmac_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_alive_sys_reg.h b/components/soc/esp32s31/register/soc/hp_alive_sys_reg.h
new file mode 100644
index 00000000000..827d548345b
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_alive_sys_reg.h
@@ -0,0 +1,839 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_ALIVE_SYS_HP_CLK_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_CLK_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x0)
+/** HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN : R/W; bitpos: [17]; default: 1;
+ *  XTALx2 80M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN    (BIT(17))
+#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_M  (HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V << HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN_S  17
+/** HP_ALIVE_SYS_HP_ROOT_CLK_EN : R/W; bitpos: [18]; default: 1;
+ *  HP SoC Root Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_ROOT_CLK_EN    (BIT(18))
+#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_M  (HP_ALIVE_SYS_HP_ROOT_CLK_EN_V << HP_ALIVE_SYS_HP_ROOT_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_ROOT_CLK_EN_S  18
+/** HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN : R/W; bitpos: [19]; default: 1;
+ *  XTAL 32K Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN    (BIT(19))
+#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_M  (HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_XTAL_32K_CLK_EN_S  19
+/** HP_ALIVE_SYS_HP_RC_32K_CLK_EN : R/W; bitpos: [20]; default: 1;
+ *  RC 32K Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN    (BIT(20))
+#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_M  (HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V << HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_RC_32K_CLK_EN_S  20
+/** HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN : R/W; bitpos: [21]; default: 1;
+ *  SOSC 150K Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN    (BIT(21))
+#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_M  (HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V << HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_SOSC_150K_CLK_EN_S  21
+/** HP_ALIVE_SYS_HP_PLL_80M_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  PLL 8M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN    (BIT(22))
+#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_M  (HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V << HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PLL_80M_CLK_EN_S  22
+/** HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  AUDIO PLL Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN    (BIT(23))
+#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_M  (HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V << HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_AUDIO_PLL_CLK_EN_S  23
+/** HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN    (BIT(24))
+#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_SDIO_PLL2_CLK_EN_S  24
+/** HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN : R/W; bitpos: [25]; default: 1;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN    (BIT(25))
+#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_SDIO_PLL1_CLK_EN_S  25
+/** HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN : R/W; bitpos: [26]; default: 1;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN    (BIT(26))
+#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_M  (HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V << HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_SDIO_PLL0_CLK_EN_S  26
+/** HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  FOSC 20M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN    (BIT(27))
+#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_M  (HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V << HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_FOSC_20M_CLK_EN_S  27
+/** HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  XTAL 40M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN    (BIT(28))
+#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_M  (HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V << HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_XTAL_40M_CLK_EN_S  28
+/** HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  CPLL 300M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN    (BIT(29))
+#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_M  (HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V << HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN_S  29
+/** HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  SPLL 480M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN    (BIT(30))
+#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_M  (HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V << HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_SPLL_480M_CLK_EN_S  30
+/** HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  MPLL 500M Clock Enable.
+ */
+#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_M  (HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V << HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_MPLL_500M_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x4)
+/** HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  PARLIO TX Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN    (BIT(30))
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_TX_CLK_EN_S  30
+/** HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  PARLIO RX Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_PARLIO_RX_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_I2S0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8)
+/** HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN : R/W; bitpos: [31]; default: 1;
+ *  I2S0 MCLK Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_M  (HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_I2S0_MCLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_I2S1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xc)
+/** HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN : R/W; bitpos: [31]; default: 1;
+ *  I2S1 MCLK Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_M  (HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V << HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_I2S1_MCLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART0_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x10)
+/** HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  UART0 SLP Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_UART0_SLP_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART1_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x14)
+/** HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  UART1 SLP Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_UART1_SLP_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART2_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x18)
+/** HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  UART2 SLP Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_UART2_SLP_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG register
+ *  HP Clock Control Register.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART3_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x1c)
+/** HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  UART3 SLP Clock From Pad Enable.
+ */
+#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_M  (HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V << HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S)
+#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_PAD_UART3_SLP_CLK_EN_S  31
+
+/** HP_ALIVE_SYS_MODEM_CLK_AON_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_MODEM_CLK_AON_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x20)
+/** HP_ALIVE_SYS_MODEM_CLK_AON_SEL : R/W; bitpos: [31]; default: 1;
+ *  Modem clk aon sel. 0: foscl  1:xtal
+ */
+#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL    (BIT(31))
+#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_M  (HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V << HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S)
+#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_V  0x00000001U
+#define HP_ALIVE_SYS_MODEM_CLK_AON_SEL_S  31
+
+/** HP_ALIVE_SYS_USB_CTRL_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_USB_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x24)
+/** HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS : R/W; bitpos: [0]; default: 0;
+ *  phy chrgvbus
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS    (BIT(0))
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S)
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_V  0x00000001U
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_CHRGVBUS_S  0
+/** HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS : R/W; bitpos: [1]; default: 0;
+ *  phy dischrgvbus
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS    (BIT(1))
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S)
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_V  0x00000001U
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DISCHRGVBUS_S  1
+/** HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN : R/W; bitpos: [2]; default: 0;
+ *  phy dmpulldown
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN    (BIT(2))
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S)
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_V  0x00000001U
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DMPULLDOWN_S  2
+/** HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN : R/W; bitpos: [3]; default: 0;
+ *  phy dppulldown
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN    (BIT(3))
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V << HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S)
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_V  0x00000001U
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_DPPULLDOWN_S  3
+/** HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP : R/W; bitpos: [4]; default: 0;
+ *  phy idpullup
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP    (BIT(4))
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_M  (HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V << HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S)
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_V  0x00000001U
+#define HP_ALIVE_SYS_USB_OTGHS_PHY_IDPULLUP_S  4
+
+/** HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG register
+ *  configure rmemory power in lp system register
+ */
+#define HP_ALIVE_SYS_HP_TCM_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x28)
+/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures layer0  hp_sram memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_MODE_S  0
+/** HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down layer0 hp_sram memory.
+ */
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN    (BIT(2))
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_L0_MEM_LP_EN_S  2
+/** HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control layer0 hp_sram memory, disable hardware
+ *  control.
+ */
+#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL    (BIT(3))
+#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_MEM_L0_LP_FORCE_CTRL_S  3
+/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  Configures layer1  hp_sram memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_MODE_S  4
+/** HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to power down layer1 hp_sram memory.
+ */
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN    (BIT(6))
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_L1_MEM_LP_EN_S  6
+/** HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to force software control layer1 hp_sram memory, disable hardware
+ *  control.
+ */
+#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL    (BIT(7))
+#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_MEM_L1_LP_FORCE_CTRL_S  7
+/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE : R/W; bitpos: [9:8]; default: 0;
+ *  Configures layer2  hp_sram memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_MODE_S  8
+/** HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN : R/W; bitpos: [10]; default: 0;
+ *  Set this bit to power down layer2 hp_sram memory.
+ */
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN    (BIT(10))
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_L2_MEM_LP_EN_S  10
+/** HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL : R/W; bitpos: [11]; default: 0;
+ *  Set this bit to force software control layer2 hp_sram memory, disable hardware
+ *  control.
+ */
+#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL    (BIT(11))
+#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_MEM_L2_LP_FORCE_CTRL_S  11
+/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE : R/W; bitpos: [13:12]; default: 0;
+ *  Configures layer3  hp_sram memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_M  (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_MODE_S  12
+/** HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN : R/W; bitpos: [14]; default: 0;
+ *  Set this bit to power down layer3 hp_sram memory.
+ */
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN    (BIT(14))
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_M  (HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V << HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_L3_MEM_LP_EN_S  14
+/** HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL : R/W; bitpos: [15]; default: 0;
+ *  Set this bit to force software control layer3 hp_sram memory, disable hardware
+ *  control.
+ */
+#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL    (BIT(15))
+#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V << HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_HP_TCM_MEM_L3_LP_FORCE_CTRL_S  15
+
+/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG register
+ *  configure rmemory power in lp system register
+ */
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x2c)
+/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures flash_mmu memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_MODE_S  0
+/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down flash_mmu memory.
+ */
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN    (BIT(2))
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_EN_S  2
+/** HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control flash_mmu memory, disable hardware control.
+ */
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_FLASH_MMU_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG register
+ *  configure rmemory power in lp system register
+ */
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x30)
+/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures psram_mmu memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE    0x00000003U
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S)
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_MODE_S  0
+/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down psram_mmu memory.
+ */
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN    (BIT(2))
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S)
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_V  0x00000001U
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_EN_S  2
+/** HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control psram_mmu memory, disable hardware control.
+ */
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_M  (HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V << HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S)
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_ALIVE_SYS_PSRAM_MMU_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG register
+ *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
+ */
+#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x34)
+/** HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
+ */
+#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_SPRAM_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG register
+ *  sprf mem aux ctrl , control TOP/CNNT power domain
+ */
+#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x38)
+/** HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  sprf mem aux ctrl , control TOP/CNNT/MODEM power domain
+ */
+#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_SPRF_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x40)
+/** HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
+ *  sdprf mem aux ctrl , control TOP/CNNT/MODEM power domain
+ */
+#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_SDPRF_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x44)
+/** HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
+ *  sprom mem aux ctrl , control CPU power domain
+ */
+#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPROM_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x48)
+/** HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  need_des
+ */
+#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPRF_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG register
+ *  intr hp2lp configuration register 0
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_CONF_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x7c)
+/** HP_ALIVE_SYS_INTR_HP2LP_EN_0 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_0    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_0_V << HP_ALIVE_SYS_INTR_HP2LP_EN_0_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_0_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG register
+ *  intr hp2lp configuration register 1
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_CONF_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x80)
+/** HP_ALIVE_SYS_INTR_HP2LP_EN_1 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_1    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_1_V << HP_ALIVE_SYS_INTR_HP2LP_EN_1_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_1_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG register
+ *  intr hp2lp configuration register 2
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_CONF_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x84)
+/** HP_ALIVE_SYS_INTR_HP2LP_EN_2 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_2    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_2_V << HP_ALIVE_SYS_INTR_HP2LP_EN_2_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_2_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG register
+ *  intr hp2lp configuration register 3
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_CONF_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x88)
+/** HP_ALIVE_SYS_INTR_HP2LP_EN_3 : R/W; bitpos: [31:0]; default: 4294967295;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_3    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_3_V << HP_ALIVE_SYS_INTR_HP2LP_EN_3_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_3_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG register
+ *  intr hp2lp configuration register 4
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_CONF_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x8c)
+/** HP_ALIVE_SYS_INTR_HP2LP_EN_4 : R/W; bitpos: [7:0]; default: 255;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_4    0x000000FFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_M  (HP_ALIVE_SYS_INTR_HP2LP_EN_4_V << HP_ALIVE_SYS_INTR_HP2LP_EN_4_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_V  0x000000FFU
+#define HP_ALIVE_SYS_INTR_HP2LP_EN_4_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG register
+ *  intr hp2lp status register 0
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x90)
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_0_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG register
+ *  intr hp2lp status register 1
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x94)
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_1_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG register
+ *  intr hp2lp status register 2
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x98)
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_2_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG register
+ *  intr hp2lp status register 3
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x9c)
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3    0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_3_S  0
+
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG register
+ *  intr hp2lp status register 4
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa0)
+/** HP_ALIVE_SYS_INTR_HP2LP_STATUS_4 : RO; bitpos: [7:0]; default: 0;
+ *  reserved
+ */
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4    0x000000FFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_M  (HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V << HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S)
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_V  0x000000FFU
+#define HP_ALIVE_SYS_INTR_HP2LP_STATUS_4_S  0
+
+/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG register
+ *  spram mem aux ctrl , control CPU power domain
+ */
+#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa4)
+/** HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
+ *  spram mem aux ctrl , control CPU power domain
+ */
+#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL    0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_M  (HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V << HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S)
+#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_V  0xFFFFFFFFU
+#define HP_ALIVE_SYS_CPU_SPRAM_MEM_AUX_CTRL_S  0
+
+/** HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG register
+ *  bus clock gating bypass configuration register
+ */
+#define HP_ALIVE_SYS_BUS_CLOCK_GATE_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xa8)
+/** HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to bypass the clock gating for ahb bus
+ */
+#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS    (BIT(0))
+#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S)
+#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_V  0x00000001U
+#define HP_ALIVE_SYS_AHB_CLK_GATING_BYPASS_S  0
+/** HP_ALIVE_SYS_APB_CLK_GATING_BYPASS : R/W; bitpos: [1]; default: 1;
+ *  Set 1 to bypass the clock gating for apb bus
+ */
+#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS    (BIT(1))
+#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S)
+#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_V  0x00000001U
+#define HP_ALIVE_SYS_APB_CLK_GATING_BYPASS_S  1
+/** HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS : R/W; bitpos: [2]; default: 1;
+ *  Set 1 to bypass the clock gating for axi bus
+ */
+#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS    (BIT(2))
+#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S)
+#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_V  0x00000001U
+#define HP_ALIVE_SYS_AXI_CLK_GATING_BYPASS_S  2
+/** HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to bypass the clock gating for mem bus
+ */
+#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS    (BIT(3))
+#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S)
+#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_V  0x00000001U
+#define HP_ALIVE_SYS_MEM_CLK_GATING_BYPASS_S  3
+/** HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS : R/W; bitpos: [4]; default: 1;
+ *  Set 1 to bypass the clock gating for ahb mtx
+ */
+#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS    (BIT(4))
+#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_M  (HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V << HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S)
+#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_V  0x00000001U
+#define HP_ALIVE_SYS_AHB_MTX_CLK_GATING_BYPASS_S  4
+
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_REG register
+ *  bus clock gating bypass configuration register
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xac)
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB    (BIT(0))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMAPB_S  0
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS : R/W; bitpos: [1]; default: 0;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS    (BIT(1))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMSYS_S  1
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU : R/W; bitpos: [2]; default: 0;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU    (BIT(2))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_ICMCPU_S  2
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST : R/W; bitpos: [3]; default: 1;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST    (BIT(3))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_S  3
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG : R/W; bitpos: [4]; default: 0;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG    (BIT(4))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_CLKRST_REG_S  4
+/** HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX : R/W; bitpos: [5]; default: 0;
+ *  Set 1 to bypass none-power_on reset source
+ */
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX    (BIT(5))
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_M  (HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V << HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S)
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_V  0x00000001U
+#define HP_ALIVE_SYS_RST_EVENT_BYPASS_IOMUX_S  5
+/** HP_ALIVE_SYS_RST_BYPASS_LOCK : R/W; bitpos: [6]; default: 0;
+ *  Set 1 to lock reset event bypass configuration
+ */
+#define HP_ALIVE_SYS_RST_BYPASS_LOCK    (BIT(6))
+#define HP_ALIVE_SYS_RST_BYPASS_LOCK_M  (HP_ALIVE_SYS_RST_BYPASS_LOCK_V << HP_ALIVE_SYS_RST_BYPASS_LOCK_S)
+#define HP_ALIVE_SYS_RST_BYPASS_LOCK_V  0x00000001U
+#define HP_ALIVE_SYS_RST_BYPASS_LOCK_S  6
+
+/** HP_ALIVE_SYS_USB_OTGHS_CTRL_REG register
+ *  usb_otghs Control configuration register
+ */
+#define HP_ALIVE_SYS_USB_OTGHS_CTRL_REG (DR_REG_HP_ALIVE_SYS_BASE + 0xb0)
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit as 1 to force use reg_usb_otghs_phy_pll_en
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN    (BIT(0))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_FORCE_EN_S  0
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN : R/W; bitpos: [1]; default: 0;
+ *  pll_en for phy inf
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN    (BIT(1))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_PLL_EN_S  1
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit as 1 to force use reg_usb_otghs_phy_suspendm
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN    (BIT(2))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_FORCE_EN_S  2
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM : R/W; bitpos: [3]; default: 0;
+ *  phy suspendm
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM    (BIT(3))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SUSPENDM_S  3
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN : R/W; bitpos: [4]; default: 0;
+ *  Set this bit as 1 to force use reg_usb_otghs_phy_reset
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN    (BIT(4))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_FORCE_EN_S  4
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET : R/W; bitpos: [5]; default: 0;
+ *  phy reset
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET    (BIT(5))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_RESET_S  5
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN : R/W; bitpos: [6]; default: 0;
+ *  phy txbitstuff_en
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN    (BIT(6))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TXBITSTUFF_EN_S  6
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM : R/W; bitpos: [7]; default: 0;
+ *  phy otg_suspendm
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM    (BIT(7))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_OTG_SUSPENDM_S  7
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE : R/W; bitpos: [8]; default: 1;
+ *  phy refclk_mode
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE    (BIT(8))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_REFCLK_MODE_S  8
+/** HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE : R/W; bitpos: [10:9]; default: 0;
+ *  usb otghs core ss_scaledown_mode
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE    0x00000003U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V << HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_V  0x00000003U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_CORE_SS_SCALEDOWN_MODE_S  9
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST : R/W; bitpos: [11]; default: 0;
+ *  phy self_test
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST    (BIT(11))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_SELF_TEST_S  11
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE : RO; bitpos: [12]; default: 0;
+ *  phy test_bist
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE    (BIT(12))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_TEST_DONE_S  12
+/** HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO : RO; bitpos: [13]; default: 0;
+ *  phy dto
+ */
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO    (BIT(13))
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_M  (HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V << HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S)
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_V  0x00000001U
+#define HP_ALIVE_SYS_REG_USB_OTGHS_PHY_DTO_S  13
+
+/** HP_ALIVE_SYS_DATE_REG register
+ *  need_des
+ */
+#define HP_ALIVE_SYS_DATE_REG (DR_REG_HP_ALIVE_SYS_BASE + 0x3fc)
+/** HP_ALIVE_SYS_DATE : R/W; bitpos: [30:0]; default: 38834448;
+ *  need_des
+ */
+#define HP_ALIVE_SYS_DATE    0x7FFFFFFFU
+#define HP_ALIVE_SYS_DATE_M  (HP_ALIVE_SYS_DATE_V << HP_ALIVE_SYS_DATE_S)
+#define HP_ALIVE_SYS_DATE_V  0x7FFFFFFFU
+#define HP_ALIVE_SYS_DATE_S  0
+/** HP_ALIVE_SYS_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  need_des
+ */
+#define HP_ALIVE_SYS_CLK_EN    (BIT(31))
+#define HP_ALIVE_SYS_CLK_EN_M  (HP_ALIVE_SYS_CLK_EN_V << HP_ALIVE_SYS_CLK_EN_S)
+#define HP_ALIVE_SYS_CLK_EN_V  0x00000001U
+#define HP_ALIVE_SYS_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_alive_sys_struct.h b/components/soc/esp32s31/register/soc/hp_alive_sys_struct.h
new file mode 100644
index 00000000000..2f7750a68f7
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_alive_sys_struct.h
@@ -0,0 +1,769 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: configure_register */
+/** Type of hp_clk_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** hp_xtalx2_80m_clk_en : R/W; bitpos: [17]; default: 1;
+         *  XTALx2 80M Clock Enable.
+         */
+        uint32_t hp_xtalx2_80m_clk_en:1;
+        /** hp_root_clk_en : R/W; bitpos: [18]; default: 1;
+         *  HP SoC Root Clock Enable.
+         */
+        uint32_t hp_root_clk_en:1;
+        /** hp_xtal_32k_clk_en : R/W; bitpos: [19]; default: 1;
+         *  XTAL 32K Clock Enable.
+         */
+        uint32_t hp_xtal_32k_clk_en:1;
+        /** hp_rc_32k_clk_en : R/W; bitpos: [20]; default: 1;
+         *  RC 32K Clock Enable.
+         */
+        uint32_t hp_rc_32k_clk_en:1;
+        /** hp_sosc_150k_clk_en : R/W; bitpos: [21]; default: 1;
+         *  SOSC 150K Clock Enable.
+         */
+        uint32_t hp_sosc_150k_clk_en:1;
+        /** hp_pll_80m_clk_en : R/W; bitpos: [22]; default: 1;
+         *  PLL 8M Clock Enable.
+         */
+        uint32_t hp_pll_80m_clk_en:1;
+        /** hp_audio_pll_clk_en : R/W; bitpos: [23]; default: 1;
+         *  AUDIO PLL Clock Enable.
+         */
+        uint32_t hp_audio_pll_clk_en:1;
+        /** hp_sdio_pll2_clk_en : R/W; bitpos: [24]; default: 1;
+         *  reserved
+         */
+        uint32_t hp_sdio_pll2_clk_en:1;
+        /** hp_sdio_pll1_clk_en : R/W; bitpos: [25]; default: 1;
+         *  reserved
+         */
+        uint32_t hp_sdio_pll1_clk_en:1;
+        /** hp_sdio_pll0_clk_en : R/W; bitpos: [26]; default: 1;
+         *  reserved
+         */
+        uint32_t hp_sdio_pll0_clk_en:1;
+        /** hp_fosc_20m_clk_en : R/W; bitpos: [27]; default: 1;
+         *  FOSC 20M Clock Enable.
+         */
+        uint32_t hp_fosc_20m_clk_en:1;
+        /** hp_xtal_40m_clk_en : R/W; bitpos: [28]; default: 1;
+         *  XTAL 40M Clock Enable.
+         */
+        uint32_t hp_xtal_40m_clk_en:1;
+        /** hp_cpll_300m_clk_en : R/W; bitpos: [29]; default: 1;
+         *  CPLL 300M Clock Enable.
+         */
+        uint32_t hp_cpll_300m_clk_en:1;
+        /** hp_spll_480m_clk_en : R/W; bitpos: [30]; default: 1;
+         *  SPLL 480M Clock Enable.
+         */
+        uint32_t hp_spll_480m_clk_en:1;
+        /** hp_mpll_500m_clk_en : R/W; bitpos: [31]; default: 1;
+         *  MPLL 500M Clock Enable.
+         */
+        uint32_t hp_mpll_500m_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_clk_ctrl_reg_t;
+
+/** Type of hp_pad_parlio_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** hp_pad_parlio_tx_clk_en : R/W; bitpos: [30]; default: 1;
+         *  PARLIO TX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_tx_clk_en:1;
+        /** hp_pad_parlio_rx_clk_en : R/W; bitpos: [31]; default: 1;
+         *  PARLIO RX Clock From Pad Enable.
+         */
+        uint32_t hp_pad_parlio_rx_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_parlio_ctrl_reg_t;
+
+/** Type of hp_pad_i2s0_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_i2s0_mclk_en : R/W; bitpos: [31]; default: 1;
+         *  I2S0 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s0_mclk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_i2s0_ctrl_reg_t;
+
+/** Type of hp_pad_i2s1_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_i2s1_mclk_en : R/W; bitpos: [31]; default: 1;
+         *  I2S1 MCLK Clock From Pad Enable.
+         */
+        uint32_t hp_pad_i2s1_mclk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_i2s1_ctrl_reg_t;
+
+/** Type of hp_pad_uart0_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_uart0_slp_clk_en : R/W; bitpos: [31]; default: 1;
+         *  UART0 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart0_slp_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_uart0_ctrl_reg_t;
+
+/** Type of hp_pad_uart1_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_uart1_slp_clk_en : R/W; bitpos: [31]; default: 1;
+         *  UART1 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart1_slp_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_uart1_ctrl_reg_t;
+
+/** Type of hp_pad_uart2_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_uart2_slp_clk_en : R/W; bitpos: [31]; default: 1;
+         *  UART2 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart2_slp_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_uart2_ctrl_reg_t;
+
+/** Type of hp_pad_uart3_ctrl register
+ *  HP Clock Control Register.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** hp_pad_uart3_slp_clk_en : R/W; bitpos: [31]; default: 1;
+         *  UART3 SLP Clock From Pad Enable.
+         */
+        uint32_t hp_pad_uart3_slp_clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_pad_uart3_ctrl_reg_t;
+
+/** Type of modem_clk_aon register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** modem_clk_aon_sel : R/W; bitpos: [31]; default: 1;
+         *  Modem clk aon sel. 0: foscl  1:xtal
+         */
+        uint32_t modem_clk_aon_sel:1;
+    };
+    uint32_t val;
+} hp_alive_sys_modem_clk_aon_reg_t;
+
+/** Type of usb_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** usb_otghs_phy_chrgvbus : R/W; bitpos: [0]; default: 0;
+         *  phy chrgvbus
+         */
+        uint32_t usb_otghs_phy_chrgvbus:1;
+        /** usb_otghs_phy_dischrgvbus : R/W; bitpos: [1]; default: 0;
+         *  phy dischrgvbus
+         */
+        uint32_t usb_otghs_phy_dischrgvbus:1;
+        /** usb_otghs_phy_dmpulldown : R/W; bitpos: [2]; default: 0;
+         *  phy dmpulldown
+         */
+        uint32_t usb_otghs_phy_dmpulldown:1;
+        /** usb_otghs_phy_dppulldown : R/W; bitpos: [3]; default: 0;
+         *  phy dppulldown
+         */
+        uint32_t usb_otghs_phy_dppulldown:1;
+        /** usb_otghs_phy_idpullup : R/W; bitpos: [4]; default: 0;
+         *  phy idpullup
+         */
+        uint32_t usb_otghs_phy_idpullup:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_alive_sys_usb_ctrl_reg_t;
+
+/** Type of hp_tcm_mem_lp_ctrl register
+ *  configure rmemory power in lp system register
+ */
+typedef union {
+    struct {
+        /** hp_tcm_l0_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures layer0  hp_sram memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t hp_tcm_l0_mem_lp_mode:2;
+        /** hp_tcm_l0_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down layer0 hp_sram memory.
+         */
+        uint32_t hp_tcm_l0_mem_lp_en:1;
+        /** hp_tcm_mem_l0_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control layer0 hp_sram memory, disable hardware
+         *  control.
+         */
+        uint32_t hp_tcm_mem_l0_lp_force_ctrl:1;
+        /** hp_tcm_l1_mem_lp_mode : R/W; bitpos: [5:4]; default: 0;
+         *  Configures layer1  hp_sram memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t hp_tcm_l1_mem_lp_mode:2;
+        /** hp_tcm_l1_mem_lp_en : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to power down layer1 hp_sram memory.
+         */
+        uint32_t hp_tcm_l1_mem_lp_en:1;
+        /** hp_tcm_mem_l1_lp_force_ctrl : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to force software control layer1 hp_sram memory, disable hardware
+         *  control.
+         */
+        uint32_t hp_tcm_mem_l1_lp_force_ctrl:1;
+        /** hp_tcm_l2_mem_lp_mode : R/W; bitpos: [9:8]; default: 0;
+         *  Configures layer2  hp_sram memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t hp_tcm_l2_mem_lp_mode:2;
+        /** hp_tcm_l2_mem_lp_en : R/W; bitpos: [10]; default: 0;
+         *  Set this bit to power down layer2 hp_sram memory.
+         */
+        uint32_t hp_tcm_l2_mem_lp_en:1;
+        /** hp_tcm_mem_l2_lp_force_ctrl : R/W; bitpos: [11]; default: 0;
+         *  Set this bit to force software control layer2 hp_sram memory, disable hardware
+         *  control.
+         */
+        uint32_t hp_tcm_mem_l2_lp_force_ctrl:1;
+        /** hp_tcm_l3_mem_lp_mode : R/W; bitpos: [13:12]; default: 0;
+         *  Configures layer3  hp_sram memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t hp_tcm_l3_mem_lp_mode:2;
+        /** hp_tcm_l3_mem_lp_en : R/W; bitpos: [14]; default: 0;
+         *  Set this bit to power down layer3 hp_sram memory.
+         */
+        uint32_t hp_tcm_l3_mem_lp_en:1;
+        /** hp_tcm_mem_l3_lp_force_ctrl : R/W; bitpos: [15]; default: 0;
+         *  Set this bit to force software control layer3 hp_sram memory, disable hardware
+         *  control.
+         */
+        uint32_t hp_tcm_mem_l3_lp_force_ctrl:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} hp_alive_sys_hp_tcm_mem_lp_ctrl_reg_t;
+
+/** Type of flash_mmu_mem_lp_ctrl register
+ *  configure rmemory power in lp system register
+ */
+typedef union {
+    struct {
+        /** flash_mmu_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures flash_mmu memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t flash_mmu_mem_lp_mode:2;
+        /** flash_mmu_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down flash_mmu memory.
+         */
+        uint32_t flash_mmu_mem_lp_en:1;
+        /** flash_mmu_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control flash_mmu memory, disable hardware control.
+         */
+        uint32_t flash_mmu_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_alive_sys_flash_mmu_mem_lp_ctrl_reg_t;
+
+/** Type of psram_mmu_mem_lp_ctrl register
+ *  configure rmemory power in lp system register
+ */
+typedef union {
+    struct {
+        /** psram_mmu_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures psram_mmu memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t psram_mmu_mem_lp_mode:2;
+        /** psram_mmu_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down psram_mmu memory.
+         */
+        uint32_t psram_mmu_mem_lp_en:1;
+        /** psram_mmu_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control psram_mmu memory, disable hardware control.
+         */
+        uint32_t psram_mmu_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_alive_sys_psram_mmu_mem_lp_ctrl_reg_t;
+
+/** Type of spram_mem_aux_ctrl register
+ *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
+ */
+typedef union {
+    struct {
+        /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  spram mem aux ctrl , control TOP/CNNT/MODEM power domain
+         */
+        uint32_t spram_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_spram_mem_aux_ctrl_reg_t;
+
+/** Type of sprf_mem_aux_ctrl register
+ *  sprf mem aux ctrl , control TOP/CNNT power domain
+ */
+typedef union {
+    struct {
+        /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  sprf mem aux ctrl , control TOP/CNNT/MODEM power domain
+         */
+        uint32_t sprf_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_sprf_mem_aux_ctrl_reg_t;
+
+/** Type of sdprf_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
+         *  sdprf mem aux ctrl , control TOP/CNNT/MODEM power domain
+         */
+        uint32_t sdprf_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_sdprf_mem_aux_ctrl_reg_t;
+
+/** Type of cpu_sprom_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
+         *  sprom mem aux ctrl , control CPU power domain
+         */
+        uint32_t cpu_sprom_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_cpu_sprom_mem_aux_ctrl_reg_t;
+
+/** Type of cpu_sprf_mem_aux_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  need_des
+         */
+        uint32_t cpu_sprf_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_cpu_sprf_mem_aux_ctrl_reg_t;
+
+/** Type of cpu_spram_mem_aux_ctrl register
+ *  spram mem aux ctrl , control CPU power domain
+ */
+typedef union {
+    struct {
+        /** cpu_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
+         *  spram mem aux ctrl , control CPU power domain
+         */
+        uint32_t cpu_spram_mem_aux_ctrl:32;
+    };
+    uint32_t val;
+} hp_alive_sys_cpu_spram_mem_aux_ctrl_reg_t;
+
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [30:0]; default: 38834448;
+         *  need_des
+         */
+        uint32_t date:31;
+        /** clk_en : R/W; bitpos: [31]; default: 0;
+         *  need_des
+         */
+        uint32_t clk_en:1;
+    };
+    uint32_t val;
+} hp_alive_sys_date_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of intr_hp2lp_conf_0 register
+ *  intr hp2lp configuration register 0
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_en_0 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_en_0:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_conf_0_reg_t;
+
+/** Type of intr_hp2lp_conf_1 register
+ *  intr hp2lp configuration register 1
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_en_1 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_en_1:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_conf_1_reg_t;
+
+/** Type of intr_hp2lp_conf_2 register
+ *  intr hp2lp configuration register 2
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_en_2 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_en_2:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_conf_2_reg_t;
+
+/** Type of intr_hp2lp_conf_3 register
+ *  intr hp2lp configuration register 3
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_en_3 : R/W; bitpos: [31:0]; default: 4294967295;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_en_3:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_conf_3_reg_t;
+
+/** Type of intr_hp2lp_conf_4 register
+ *  intr hp2lp configuration register 4
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_en_4 : R/W; bitpos: [7:0]; default: 255;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_en_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_conf_4_reg_t;
+
+/** Type of bus_clock_gate_bypass register
+ *  bus clock gating bypass configuration register
+ */
+typedef union {
+    struct {
+        /** ahb_clk_gating_bypass : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to bypass the clock gating for ahb bus
+         */
+        uint32_t ahb_clk_gating_bypass:1;
+        /** apb_clk_gating_bypass : R/W; bitpos: [1]; default: 1;
+         *  Set 1 to bypass the clock gating for apb bus
+         */
+        uint32_t apb_clk_gating_bypass:1;
+        /** axi_clk_gating_bypass : R/W; bitpos: [2]; default: 1;
+         *  Set 1 to bypass the clock gating for axi bus
+         */
+        uint32_t axi_clk_gating_bypass:1;
+        /** mem_clk_gating_bypass : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to bypass the clock gating for mem bus
+         */
+        uint32_t mem_clk_gating_bypass:1;
+        /** ahb_mtx_clk_gating_bypass : R/W; bitpos: [4]; default: 1;
+         *  Set 1 to bypass the clock gating for ahb mtx
+         */
+        uint32_t ahb_mtx_clk_gating_bypass:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_alive_sys_bus_clock_gate_bypass_reg_t;
+
+/** Type of rst_event_bypass register
+ *  bus clock gating bypass configuration register
+ */
+typedef union {
+    struct {
+        /** rst_event_bypass_icmapb : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_icmapb:1;
+        /** rst_event_bypass_icmsys : R/W; bitpos: [1]; default: 0;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_icmsys:1;
+        /** rst_event_bypass_icmcpu : R/W; bitpos: [2]; default: 0;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_icmcpu:1;
+        /** rst_event_bypass_clkrst : R/W; bitpos: [3]; default: 1;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_clkrst:1;
+        /** rst_event_bypass_clkrst_reg : R/W; bitpos: [4]; default: 0;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_clkrst_reg:1;
+        /** rst_event_bypass_iomux : R/W; bitpos: [5]; default: 0;
+         *  Set 1 to bypass none-power_on reset source
+         */
+        uint32_t rst_event_bypass_iomux:1;
+        /** rst_bypass_lock : R/W; bitpos: [6]; default: 0;
+         *  Set 1 to lock reset event bypass configuration
+         */
+        uint32_t rst_bypass_lock:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_alive_sys_rst_event_bypass_reg_t;
+
+/** Type of usb_otghs_ctrl register
+ *  usb_otghs Control configuration register
+ */
+typedef union {
+    struct {
+        /** reg_usb_otghs_phy_pll_force_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit as 1 to force use reg_usb_otghs_phy_pll_en
+         */
+        uint32_t reg_usb_otghs_phy_pll_force_en:1;
+        /** reg_usb_otghs_phy_pll_en : R/W; bitpos: [1]; default: 0;
+         *  pll_en for phy inf
+         */
+        uint32_t reg_usb_otghs_phy_pll_en:1;
+        /** reg_usb_otghs_phy_suspendm_force_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit as 1 to force use reg_usb_otghs_phy_suspendm
+         */
+        uint32_t reg_usb_otghs_phy_suspendm_force_en:1;
+        /** reg_usb_otghs_phy_suspendm : R/W; bitpos: [3]; default: 0;
+         *  phy suspendm
+         */
+        uint32_t reg_usb_otghs_phy_suspendm:1;
+        /** reg_usb_otghs_phy_reset_force_en : R/W; bitpos: [4]; default: 0;
+         *  Set this bit as 1 to force use reg_usb_otghs_phy_reset
+         */
+        uint32_t reg_usb_otghs_phy_reset_force_en:1;
+        /** reg_usb_otghs_phy_reset : R/W; bitpos: [5]; default: 0;
+         *  phy reset
+         */
+        uint32_t reg_usb_otghs_phy_reset:1;
+        /** reg_usb_otghs_phy_txbitstuff_en : R/W; bitpos: [6]; default: 0;
+         *  phy txbitstuff_en
+         */
+        uint32_t reg_usb_otghs_phy_txbitstuff_en:1;
+        /** reg_usb_otghs_phy_otg_suspendm : R/W; bitpos: [7]; default: 0;
+         *  phy otg_suspendm
+         */
+        uint32_t reg_usb_otghs_phy_otg_suspendm:1;
+        /** reg_usb_otghs_phy_refclk_mode : R/W; bitpos: [8]; default: 1;
+         *  phy refclk_mode
+         */
+        uint32_t reg_usb_otghs_phy_refclk_mode:1;
+        /** reg_usb_otghs_core_ss_scaledown_mode : R/W; bitpos: [10:9]; default: 0;
+         *  usb otghs core ss_scaledown_mode
+         */
+        uint32_t reg_usb_otghs_core_ss_scaledown_mode:2;
+        /** reg_usb_otghs_phy_self_test : R/W; bitpos: [11]; default: 0;
+         *  phy self_test
+         */
+        uint32_t reg_usb_otghs_phy_self_test:1;
+        /** reg_usb_otghs_phy_test_done : RO; bitpos: [12]; default: 0;
+         *  phy test_bist
+         */
+        uint32_t reg_usb_otghs_phy_test_done:1;
+        /** reg_usb_otghs_phy_dto : RO; bitpos: [13]; default: 0;
+         *  phy dto
+         */
+        uint32_t reg_usb_otghs_phy_dto:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_alive_sys_usb_otghs_ctrl_reg_t;
+
+
+/** Group: Status Register */
+/** Type of intr_hp2lp_status_0 register
+ *  intr hp2lp status register 0
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_status_0:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_status_0_reg_t;
+
+/** Type of intr_hp2lp_status_1 register
+ *  intr hp2lp status register 1
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_status_1:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_status_1_reg_t;
+
+/** Type of intr_hp2lp_status_2 register
+ *  intr hp2lp status register 2
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_status_2:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_status_2_reg_t;
+
+/** Type of intr_hp2lp_status_3 register
+ *  intr hp2lp status register 3
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_status_3:32;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_status_3_reg_t;
+
+/** Type of intr_hp2lp_status_4 register
+ *  intr hp2lp status register 4
+ */
+typedef union {
+    struct {
+        /** intr_hp2lp_status_4 : RO; bitpos: [7:0]; default: 0;
+         *  reserved
+         */
+        uint32_t intr_hp2lp_status_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_alive_sys_intr_hp2lp_status_4_reg_t;
+
+
+typedef struct {
+    volatile hp_alive_sys_hp_clk_ctrl_reg_t hp_clk_ctrl;
+    volatile hp_alive_sys_hp_pad_parlio_ctrl_reg_t hp_pad_parlio_ctrl;
+    volatile hp_alive_sys_hp_pad_i2s0_ctrl_reg_t hp_pad_i2s0_ctrl;
+    volatile hp_alive_sys_hp_pad_i2s1_ctrl_reg_t hp_pad_i2s1_ctrl;
+    volatile hp_alive_sys_hp_pad_uart0_ctrl_reg_t hp_pad_uart0_ctrl;
+    volatile hp_alive_sys_hp_pad_uart1_ctrl_reg_t hp_pad_uart1_ctrl;
+    volatile hp_alive_sys_hp_pad_uart2_ctrl_reg_t hp_pad_uart2_ctrl;
+    volatile hp_alive_sys_hp_pad_uart3_ctrl_reg_t hp_pad_uart3_ctrl;
+    volatile hp_alive_sys_modem_clk_aon_reg_t modem_clk_aon;
+    volatile hp_alive_sys_usb_ctrl_reg_t usb_ctrl;
+    volatile hp_alive_sys_hp_tcm_mem_lp_ctrl_reg_t hp_tcm_mem_lp_ctrl;
+    volatile hp_alive_sys_flash_mmu_mem_lp_ctrl_reg_t flash_mmu_mem_lp_ctrl;
+    volatile hp_alive_sys_psram_mmu_mem_lp_ctrl_reg_t psram_mmu_mem_lp_ctrl;
+    volatile hp_alive_sys_spram_mem_aux_ctrl_reg_t spram_mem_aux_ctrl;
+    volatile hp_alive_sys_sprf_mem_aux_ctrl_reg_t sprf_mem_aux_ctrl;
+    uint32_t reserved_03c;
+    volatile hp_alive_sys_sdprf_mem_aux_ctrl_reg_t sdprf_mem_aux_ctrl;
+    volatile hp_alive_sys_cpu_sprom_mem_aux_ctrl_reg_t cpu_sprom_mem_aux_ctrl;
+    volatile hp_alive_sys_cpu_sprf_mem_aux_ctrl_reg_t cpu_sprf_mem_aux_ctrl;
+    uint32_t reserved_04c[12];
+    volatile hp_alive_sys_intr_hp2lp_conf_0_reg_t intr_hp2lp_conf_0;
+    volatile hp_alive_sys_intr_hp2lp_conf_1_reg_t intr_hp2lp_conf_1;
+    volatile hp_alive_sys_intr_hp2lp_conf_2_reg_t intr_hp2lp_conf_2;
+    volatile hp_alive_sys_intr_hp2lp_conf_3_reg_t intr_hp2lp_conf_3;
+    volatile hp_alive_sys_intr_hp2lp_conf_4_reg_t intr_hp2lp_conf_4;
+    volatile hp_alive_sys_intr_hp2lp_status_0_reg_t intr_hp2lp_status_0;
+    volatile hp_alive_sys_intr_hp2lp_status_1_reg_t intr_hp2lp_status_1;
+    volatile hp_alive_sys_intr_hp2lp_status_2_reg_t intr_hp2lp_status_2;
+    volatile hp_alive_sys_intr_hp2lp_status_3_reg_t intr_hp2lp_status_3;
+    volatile hp_alive_sys_intr_hp2lp_status_4_reg_t intr_hp2lp_status_4;
+    volatile hp_alive_sys_cpu_spram_mem_aux_ctrl_reg_t cpu_spram_mem_aux_ctrl;
+    volatile hp_alive_sys_bus_clock_gate_bypass_reg_t bus_clock_gate_bypass;
+    volatile hp_alive_sys_rst_event_bypass_reg_t rst_event_bypass;
+    volatile hp_alive_sys_usb_otghs_ctrl_reg_t usb_otghs_ctrl;
+    uint32_t reserved_0b4[210];
+    volatile hp_alive_sys_date_reg_t date;
+} hp_alive_sys_dev_t;
+
+extern hp_alive_sys_dev_t HP_ALIVE_SYS;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_alive_sys_dev_t) == 0x400, "Invalid size of hp_alive_sys_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_apm_reg.h b/components/soc/esp32s31/register/soc/hp_apm_reg.h
new file mode 100644
index 00000000000..a02de342ee1
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_apm_reg.h
@@ -0,0 +1,2574 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_APM_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0)
+/** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1;
+ *  Configure bit $n (0-15) to enable region $n.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_REGION_FILTER_EN    0x0000FFFFU
+#define HP_APM_REGION_FILTER_EN_M  (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S)
+#define HP_APM_REGION_FILTER_EN_V  0x0000FFFFU
+#define HP_APM_REGION_FILTER_EN_S  0
+
+/** HP_APM_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4)
+/** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 0.
+ */
+#define HP_APM_REGION0_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_START_M  (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S)
+#define HP_APM_REGION0_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_START_S  0
+
+/** HP_APM_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8)
+/** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 0.
+ */
+#define HP_APM_REGION0_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_END_M  (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S)
+#define HP_APM_REGION0_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION0_ADDR_END_S  0
+
+/** HP_APM_REGION0_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc)
+/** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 0.
+ */
+#define HP_APM_REGION0_R0_X    (BIT(0))
+#define HP_APM_REGION0_R0_X_M  (HP_APM_REGION0_R0_X_V << HP_APM_REGION0_R0_X_S)
+#define HP_APM_REGION0_R0_X_V  0x00000001U
+#define HP_APM_REGION0_R0_X_S  0
+/** HP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 0.
+ */
+#define HP_APM_REGION0_R0_W    (BIT(1))
+#define HP_APM_REGION0_R0_W_M  (HP_APM_REGION0_R0_W_V << HP_APM_REGION0_R0_W_S)
+#define HP_APM_REGION0_R0_W_V  0x00000001U
+#define HP_APM_REGION0_R0_W_S  1
+/** HP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 0.
+ */
+#define HP_APM_REGION0_R0_R    (BIT(2))
+#define HP_APM_REGION0_R0_R_M  (HP_APM_REGION0_R0_R_V << HP_APM_REGION0_R0_R_S)
+#define HP_APM_REGION0_R0_R_V  0x00000001U
+#define HP_APM_REGION0_R0_R_S  2
+/** HP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 0.
+ */
+#define HP_APM_REGION0_R1_X    (BIT(4))
+#define HP_APM_REGION0_R1_X_M  (HP_APM_REGION0_R1_X_V << HP_APM_REGION0_R1_X_S)
+#define HP_APM_REGION0_R1_X_V  0x00000001U
+#define HP_APM_REGION0_R1_X_S  4
+/** HP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 0.
+ */
+#define HP_APM_REGION0_R1_W    (BIT(5))
+#define HP_APM_REGION0_R1_W_M  (HP_APM_REGION0_R1_W_V << HP_APM_REGION0_R1_W_S)
+#define HP_APM_REGION0_R1_W_V  0x00000001U
+#define HP_APM_REGION0_R1_W_S  5
+/** HP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 0.
+ */
+#define HP_APM_REGION0_R1_R    (BIT(6))
+#define HP_APM_REGION0_R1_R_M  (HP_APM_REGION0_R1_R_V << HP_APM_REGION0_R1_R_S)
+#define HP_APM_REGION0_R1_R_V  0x00000001U
+#define HP_APM_REGION0_R1_R_S  6
+/** HP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 0.
+ */
+#define HP_APM_REGION0_R2_X    (BIT(8))
+#define HP_APM_REGION0_R2_X_M  (HP_APM_REGION0_R2_X_V << HP_APM_REGION0_R2_X_S)
+#define HP_APM_REGION0_R2_X_V  0x00000001U
+#define HP_APM_REGION0_R2_X_S  8
+/** HP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 0.
+ */
+#define HP_APM_REGION0_R2_W    (BIT(9))
+#define HP_APM_REGION0_R2_W_M  (HP_APM_REGION0_R2_W_V << HP_APM_REGION0_R2_W_S)
+#define HP_APM_REGION0_R2_W_V  0x00000001U
+#define HP_APM_REGION0_R2_W_S  9
+/** HP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 0.
+ */
+#define HP_APM_REGION0_R2_R    (BIT(10))
+#define HP_APM_REGION0_R2_R_M  (HP_APM_REGION0_R2_R_V << HP_APM_REGION0_R2_R_S)
+#define HP_APM_REGION0_R2_R_V  0x00000001U
+#define HP_APM_REGION0_R2_R_S  10
+/** HP_APM_REGION0_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 0.
+ */
+#define HP_APM_REGION0_TEE_X    (BIT(12))
+#define HP_APM_REGION0_TEE_X_M  (HP_APM_REGION0_TEE_X_V << HP_APM_REGION0_TEE_X_S)
+#define HP_APM_REGION0_TEE_X_V  0x00000001U
+#define HP_APM_REGION0_TEE_X_S  12
+/** HP_APM_REGION0_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 0.
+ */
+#define HP_APM_REGION0_TEE_W    (BIT(13))
+#define HP_APM_REGION0_TEE_W_M  (HP_APM_REGION0_TEE_W_V << HP_APM_REGION0_TEE_W_S)
+#define HP_APM_REGION0_TEE_W_V  0x00000001U
+#define HP_APM_REGION0_TEE_W_S  13
+/** HP_APM_REGION0_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 0.
+ */
+#define HP_APM_REGION0_TEE_R    (BIT(14))
+#define HP_APM_REGION0_TEE_R_M  (HP_APM_REGION0_TEE_R_V << HP_APM_REGION0_TEE_R_S)
+#define HP_APM_REGION0_TEE_R_V  0x00000001U
+#define HP_APM_REGION0_TEE_R_S  14
+/** HP_APM_REGION0_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION0_LOCK    (BIT(16))
+#define HP_APM_REGION0_LOCK_M  (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S)
+#define HP_APM_REGION0_LOCK_V  0x00000001U
+#define HP_APM_REGION0_LOCK_S  16
+
+/** HP_APM_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10)
+/** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 1.
+ */
+#define HP_APM_REGION1_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_START_M  (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S)
+#define HP_APM_REGION1_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_START_S  0
+
+/** HP_APM_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14)
+/** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 1.
+ */
+#define HP_APM_REGION1_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_END_M  (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S)
+#define HP_APM_REGION1_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION1_ADDR_END_S  0
+
+/** HP_APM_REGION1_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18)
+/** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 1.
+ */
+#define HP_APM_REGION1_R0_X    (BIT(0))
+#define HP_APM_REGION1_R0_X_M  (HP_APM_REGION1_R0_X_V << HP_APM_REGION1_R0_X_S)
+#define HP_APM_REGION1_R0_X_V  0x00000001U
+#define HP_APM_REGION1_R0_X_S  0
+/** HP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 1.
+ */
+#define HP_APM_REGION1_R0_W    (BIT(1))
+#define HP_APM_REGION1_R0_W_M  (HP_APM_REGION1_R0_W_V << HP_APM_REGION1_R0_W_S)
+#define HP_APM_REGION1_R0_W_V  0x00000001U
+#define HP_APM_REGION1_R0_W_S  1
+/** HP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 1.
+ */
+#define HP_APM_REGION1_R0_R    (BIT(2))
+#define HP_APM_REGION1_R0_R_M  (HP_APM_REGION1_R0_R_V << HP_APM_REGION1_R0_R_S)
+#define HP_APM_REGION1_R0_R_V  0x00000001U
+#define HP_APM_REGION1_R0_R_S  2
+/** HP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 1.
+ */
+#define HP_APM_REGION1_R1_X    (BIT(4))
+#define HP_APM_REGION1_R1_X_M  (HP_APM_REGION1_R1_X_V << HP_APM_REGION1_R1_X_S)
+#define HP_APM_REGION1_R1_X_V  0x00000001U
+#define HP_APM_REGION1_R1_X_S  4
+/** HP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 1.
+ */
+#define HP_APM_REGION1_R1_W    (BIT(5))
+#define HP_APM_REGION1_R1_W_M  (HP_APM_REGION1_R1_W_V << HP_APM_REGION1_R1_W_S)
+#define HP_APM_REGION1_R1_W_V  0x00000001U
+#define HP_APM_REGION1_R1_W_S  5
+/** HP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 1.
+ */
+#define HP_APM_REGION1_R1_R    (BIT(6))
+#define HP_APM_REGION1_R1_R_M  (HP_APM_REGION1_R1_R_V << HP_APM_REGION1_R1_R_S)
+#define HP_APM_REGION1_R1_R_V  0x00000001U
+#define HP_APM_REGION1_R1_R_S  6
+/** HP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 1.
+ */
+#define HP_APM_REGION1_R2_X    (BIT(8))
+#define HP_APM_REGION1_R2_X_M  (HP_APM_REGION1_R2_X_V << HP_APM_REGION1_R2_X_S)
+#define HP_APM_REGION1_R2_X_V  0x00000001U
+#define HP_APM_REGION1_R2_X_S  8
+/** HP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 1.
+ */
+#define HP_APM_REGION1_R2_W    (BIT(9))
+#define HP_APM_REGION1_R2_W_M  (HP_APM_REGION1_R2_W_V << HP_APM_REGION1_R2_W_S)
+#define HP_APM_REGION1_R2_W_V  0x00000001U
+#define HP_APM_REGION1_R2_W_S  9
+/** HP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 1.
+ */
+#define HP_APM_REGION1_R2_R    (BIT(10))
+#define HP_APM_REGION1_R2_R_M  (HP_APM_REGION1_R2_R_V << HP_APM_REGION1_R2_R_S)
+#define HP_APM_REGION1_R2_R_V  0x00000001U
+#define HP_APM_REGION1_R2_R_S  10
+/** HP_APM_REGION1_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 1.
+ */
+#define HP_APM_REGION1_TEE_X    (BIT(12))
+#define HP_APM_REGION1_TEE_X_M  (HP_APM_REGION1_TEE_X_V << HP_APM_REGION1_TEE_X_S)
+#define HP_APM_REGION1_TEE_X_V  0x00000001U
+#define HP_APM_REGION1_TEE_X_S  12
+/** HP_APM_REGION1_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 1.
+ */
+#define HP_APM_REGION1_TEE_W    (BIT(13))
+#define HP_APM_REGION1_TEE_W_M  (HP_APM_REGION1_TEE_W_V << HP_APM_REGION1_TEE_W_S)
+#define HP_APM_REGION1_TEE_W_V  0x00000001U
+#define HP_APM_REGION1_TEE_W_S  13
+/** HP_APM_REGION1_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 1.
+ */
+#define HP_APM_REGION1_TEE_R    (BIT(14))
+#define HP_APM_REGION1_TEE_R_M  (HP_APM_REGION1_TEE_R_V << HP_APM_REGION1_TEE_R_S)
+#define HP_APM_REGION1_TEE_R_V  0x00000001U
+#define HP_APM_REGION1_TEE_R_S  14
+/** HP_APM_REGION1_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION1_LOCK    (BIT(16))
+#define HP_APM_REGION1_LOCK_M  (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S)
+#define HP_APM_REGION1_LOCK_V  0x00000001U
+#define HP_APM_REGION1_LOCK_S  16
+
+/** HP_APM_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c)
+/** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 2.
+ */
+#define HP_APM_REGION2_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_START_M  (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S)
+#define HP_APM_REGION2_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_START_S  0
+
+/** HP_APM_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20)
+/** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 2.
+ */
+#define HP_APM_REGION2_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_END_M  (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S)
+#define HP_APM_REGION2_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION2_ADDR_END_S  0
+
+/** HP_APM_REGION2_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24)
+/** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 2.
+ */
+#define HP_APM_REGION2_R0_X    (BIT(0))
+#define HP_APM_REGION2_R0_X_M  (HP_APM_REGION2_R0_X_V << HP_APM_REGION2_R0_X_S)
+#define HP_APM_REGION2_R0_X_V  0x00000001U
+#define HP_APM_REGION2_R0_X_S  0
+/** HP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 2.
+ */
+#define HP_APM_REGION2_R0_W    (BIT(1))
+#define HP_APM_REGION2_R0_W_M  (HP_APM_REGION2_R0_W_V << HP_APM_REGION2_R0_W_S)
+#define HP_APM_REGION2_R0_W_V  0x00000001U
+#define HP_APM_REGION2_R0_W_S  1
+/** HP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 2.
+ */
+#define HP_APM_REGION2_R0_R    (BIT(2))
+#define HP_APM_REGION2_R0_R_M  (HP_APM_REGION2_R0_R_V << HP_APM_REGION2_R0_R_S)
+#define HP_APM_REGION2_R0_R_V  0x00000001U
+#define HP_APM_REGION2_R0_R_S  2
+/** HP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 2.
+ */
+#define HP_APM_REGION2_R1_X    (BIT(4))
+#define HP_APM_REGION2_R1_X_M  (HP_APM_REGION2_R1_X_V << HP_APM_REGION2_R1_X_S)
+#define HP_APM_REGION2_R1_X_V  0x00000001U
+#define HP_APM_REGION2_R1_X_S  4
+/** HP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 2.
+ */
+#define HP_APM_REGION2_R1_W    (BIT(5))
+#define HP_APM_REGION2_R1_W_M  (HP_APM_REGION2_R1_W_V << HP_APM_REGION2_R1_W_S)
+#define HP_APM_REGION2_R1_W_V  0x00000001U
+#define HP_APM_REGION2_R1_W_S  5
+/** HP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 2.
+ */
+#define HP_APM_REGION2_R1_R    (BIT(6))
+#define HP_APM_REGION2_R1_R_M  (HP_APM_REGION2_R1_R_V << HP_APM_REGION2_R1_R_S)
+#define HP_APM_REGION2_R1_R_V  0x00000001U
+#define HP_APM_REGION2_R1_R_S  6
+/** HP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 2.
+ */
+#define HP_APM_REGION2_R2_X    (BIT(8))
+#define HP_APM_REGION2_R2_X_M  (HP_APM_REGION2_R2_X_V << HP_APM_REGION2_R2_X_S)
+#define HP_APM_REGION2_R2_X_V  0x00000001U
+#define HP_APM_REGION2_R2_X_S  8
+/** HP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 2.
+ */
+#define HP_APM_REGION2_R2_W    (BIT(9))
+#define HP_APM_REGION2_R2_W_M  (HP_APM_REGION2_R2_W_V << HP_APM_REGION2_R2_W_S)
+#define HP_APM_REGION2_R2_W_V  0x00000001U
+#define HP_APM_REGION2_R2_W_S  9
+/** HP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 2.
+ */
+#define HP_APM_REGION2_R2_R    (BIT(10))
+#define HP_APM_REGION2_R2_R_M  (HP_APM_REGION2_R2_R_V << HP_APM_REGION2_R2_R_S)
+#define HP_APM_REGION2_R2_R_V  0x00000001U
+#define HP_APM_REGION2_R2_R_S  10
+/** HP_APM_REGION2_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 2.
+ */
+#define HP_APM_REGION2_TEE_X    (BIT(12))
+#define HP_APM_REGION2_TEE_X_M  (HP_APM_REGION2_TEE_X_V << HP_APM_REGION2_TEE_X_S)
+#define HP_APM_REGION2_TEE_X_V  0x00000001U
+#define HP_APM_REGION2_TEE_X_S  12
+/** HP_APM_REGION2_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 2.
+ */
+#define HP_APM_REGION2_TEE_W    (BIT(13))
+#define HP_APM_REGION2_TEE_W_M  (HP_APM_REGION2_TEE_W_V << HP_APM_REGION2_TEE_W_S)
+#define HP_APM_REGION2_TEE_W_V  0x00000001U
+#define HP_APM_REGION2_TEE_W_S  13
+/** HP_APM_REGION2_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 2.
+ */
+#define HP_APM_REGION2_TEE_R    (BIT(14))
+#define HP_APM_REGION2_TEE_R_M  (HP_APM_REGION2_TEE_R_V << HP_APM_REGION2_TEE_R_S)
+#define HP_APM_REGION2_TEE_R_V  0x00000001U
+#define HP_APM_REGION2_TEE_R_S  14
+/** HP_APM_REGION2_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION2_LOCK    (BIT(16))
+#define HP_APM_REGION2_LOCK_M  (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S)
+#define HP_APM_REGION2_LOCK_V  0x00000001U
+#define HP_APM_REGION2_LOCK_S  16
+
+/** HP_APM_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28)
+/** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 3.
+ */
+#define HP_APM_REGION3_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_START_M  (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S)
+#define HP_APM_REGION3_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_START_S  0
+
+/** HP_APM_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c)
+/** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 3.
+ */
+#define HP_APM_REGION3_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_END_M  (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S)
+#define HP_APM_REGION3_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION3_ADDR_END_S  0
+
+/** HP_APM_REGION3_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30)
+/** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 3.
+ */
+#define HP_APM_REGION3_R0_X    (BIT(0))
+#define HP_APM_REGION3_R0_X_M  (HP_APM_REGION3_R0_X_V << HP_APM_REGION3_R0_X_S)
+#define HP_APM_REGION3_R0_X_V  0x00000001U
+#define HP_APM_REGION3_R0_X_S  0
+/** HP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 3.
+ */
+#define HP_APM_REGION3_R0_W    (BIT(1))
+#define HP_APM_REGION3_R0_W_M  (HP_APM_REGION3_R0_W_V << HP_APM_REGION3_R0_W_S)
+#define HP_APM_REGION3_R0_W_V  0x00000001U
+#define HP_APM_REGION3_R0_W_S  1
+/** HP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 3.
+ */
+#define HP_APM_REGION3_R0_R    (BIT(2))
+#define HP_APM_REGION3_R0_R_M  (HP_APM_REGION3_R0_R_V << HP_APM_REGION3_R0_R_S)
+#define HP_APM_REGION3_R0_R_V  0x00000001U
+#define HP_APM_REGION3_R0_R_S  2
+/** HP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 3.
+ */
+#define HP_APM_REGION3_R1_X    (BIT(4))
+#define HP_APM_REGION3_R1_X_M  (HP_APM_REGION3_R1_X_V << HP_APM_REGION3_R1_X_S)
+#define HP_APM_REGION3_R1_X_V  0x00000001U
+#define HP_APM_REGION3_R1_X_S  4
+/** HP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 3.
+ */
+#define HP_APM_REGION3_R1_W    (BIT(5))
+#define HP_APM_REGION3_R1_W_M  (HP_APM_REGION3_R1_W_V << HP_APM_REGION3_R1_W_S)
+#define HP_APM_REGION3_R1_W_V  0x00000001U
+#define HP_APM_REGION3_R1_W_S  5
+/** HP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 3.
+ */
+#define HP_APM_REGION3_R1_R    (BIT(6))
+#define HP_APM_REGION3_R1_R_M  (HP_APM_REGION3_R1_R_V << HP_APM_REGION3_R1_R_S)
+#define HP_APM_REGION3_R1_R_V  0x00000001U
+#define HP_APM_REGION3_R1_R_S  6
+/** HP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 3.
+ */
+#define HP_APM_REGION3_R2_X    (BIT(8))
+#define HP_APM_REGION3_R2_X_M  (HP_APM_REGION3_R2_X_V << HP_APM_REGION3_R2_X_S)
+#define HP_APM_REGION3_R2_X_V  0x00000001U
+#define HP_APM_REGION3_R2_X_S  8
+/** HP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 3.
+ */
+#define HP_APM_REGION3_R2_W    (BIT(9))
+#define HP_APM_REGION3_R2_W_M  (HP_APM_REGION3_R2_W_V << HP_APM_REGION3_R2_W_S)
+#define HP_APM_REGION3_R2_W_V  0x00000001U
+#define HP_APM_REGION3_R2_W_S  9
+/** HP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 3.
+ */
+#define HP_APM_REGION3_R2_R    (BIT(10))
+#define HP_APM_REGION3_R2_R_M  (HP_APM_REGION3_R2_R_V << HP_APM_REGION3_R2_R_S)
+#define HP_APM_REGION3_R2_R_V  0x00000001U
+#define HP_APM_REGION3_R2_R_S  10
+/** HP_APM_REGION3_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 3.
+ */
+#define HP_APM_REGION3_TEE_X    (BIT(12))
+#define HP_APM_REGION3_TEE_X_M  (HP_APM_REGION3_TEE_X_V << HP_APM_REGION3_TEE_X_S)
+#define HP_APM_REGION3_TEE_X_V  0x00000001U
+#define HP_APM_REGION3_TEE_X_S  12
+/** HP_APM_REGION3_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 3.
+ */
+#define HP_APM_REGION3_TEE_W    (BIT(13))
+#define HP_APM_REGION3_TEE_W_M  (HP_APM_REGION3_TEE_W_V << HP_APM_REGION3_TEE_W_S)
+#define HP_APM_REGION3_TEE_W_V  0x00000001U
+#define HP_APM_REGION3_TEE_W_S  13
+/** HP_APM_REGION3_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 3.
+ */
+#define HP_APM_REGION3_TEE_R    (BIT(14))
+#define HP_APM_REGION3_TEE_R_M  (HP_APM_REGION3_TEE_R_V << HP_APM_REGION3_TEE_R_S)
+#define HP_APM_REGION3_TEE_R_V  0x00000001U
+#define HP_APM_REGION3_TEE_R_S  14
+/** HP_APM_REGION3_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION3_LOCK    (BIT(16))
+#define HP_APM_REGION3_LOCK_M  (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S)
+#define HP_APM_REGION3_LOCK_V  0x00000001U
+#define HP_APM_REGION3_LOCK_S  16
+
+/** HP_APM_REGION4_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34)
+/** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 4.
+ */
+#define HP_APM_REGION4_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_START_M  (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S)
+#define HP_APM_REGION4_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_START_S  0
+
+/** HP_APM_REGION4_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38)
+/** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 4.
+ */
+#define HP_APM_REGION4_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_END_M  (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S)
+#define HP_APM_REGION4_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION4_ADDR_END_S  0
+
+/** HP_APM_REGION4_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c)
+/** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 4.
+ */
+#define HP_APM_REGION4_R0_X    (BIT(0))
+#define HP_APM_REGION4_R0_X_M  (HP_APM_REGION4_R0_X_V << HP_APM_REGION4_R0_X_S)
+#define HP_APM_REGION4_R0_X_V  0x00000001U
+#define HP_APM_REGION4_R0_X_S  0
+/** HP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 4.
+ */
+#define HP_APM_REGION4_R0_W    (BIT(1))
+#define HP_APM_REGION4_R0_W_M  (HP_APM_REGION4_R0_W_V << HP_APM_REGION4_R0_W_S)
+#define HP_APM_REGION4_R0_W_V  0x00000001U
+#define HP_APM_REGION4_R0_W_S  1
+/** HP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 4.
+ */
+#define HP_APM_REGION4_R0_R    (BIT(2))
+#define HP_APM_REGION4_R0_R_M  (HP_APM_REGION4_R0_R_V << HP_APM_REGION4_R0_R_S)
+#define HP_APM_REGION4_R0_R_V  0x00000001U
+#define HP_APM_REGION4_R0_R_S  2
+/** HP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 4.
+ */
+#define HP_APM_REGION4_R1_X    (BIT(4))
+#define HP_APM_REGION4_R1_X_M  (HP_APM_REGION4_R1_X_V << HP_APM_REGION4_R1_X_S)
+#define HP_APM_REGION4_R1_X_V  0x00000001U
+#define HP_APM_REGION4_R1_X_S  4
+/** HP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 4.
+ */
+#define HP_APM_REGION4_R1_W    (BIT(5))
+#define HP_APM_REGION4_R1_W_M  (HP_APM_REGION4_R1_W_V << HP_APM_REGION4_R1_W_S)
+#define HP_APM_REGION4_R1_W_V  0x00000001U
+#define HP_APM_REGION4_R1_W_S  5
+/** HP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 4.
+ */
+#define HP_APM_REGION4_R1_R    (BIT(6))
+#define HP_APM_REGION4_R1_R_M  (HP_APM_REGION4_R1_R_V << HP_APM_REGION4_R1_R_S)
+#define HP_APM_REGION4_R1_R_V  0x00000001U
+#define HP_APM_REGION4_R1_R_S  6
+/** HP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 4.
+ */
+#define HP_APM_REGION4_R2_X    (BIT(8))
+#define HP_APM_REGION4_R2_X_M  (HP_APM_REGION4_R2_X_V << HP_APM_REGION4_R2_X_S)
+#define HP_APM_REGION4_R2_X_V  0x00000001U
+#define HP_APM_REGION4_R2_X_S  8
+/** HP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 4.
+ */
+#define HP_APM_REGION4_R2_W    (BIT(9))
+#define HP_APM_REGION4_R2_W_M  (HP_APM_REGION4_R2_W_V << HP_APM_REGION4_R2_W_S)
+#define HP_APM_REGION4_R2_W_V  0x00000001U
+#define HP_APM_REGION4_R2_W_S  9
+/** HP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 4.
+ */
+#define HP_APM_REGION4_R2_R    (BIT(10))
+#define HP_APM_REGION4_R2_R_M  (HP_APM_REGION4_R2_R_V << HP_APM_REGION4_R2_R_S)
+#define HP_APM_REGION4_R2_R_V  0x00000001U
+#define HP_APM_REGION4_R2_R_S  10
+/** HP_APM_REGION4_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 4.
+ */
+#define HP_APM_REGION4_TEE_X    (BIT(12))
+#define HP_APM_REGION4_TEE_X_M  (HP_APM_REGION4_TEE_X_V << HP_APM_REGION4_TEE_X_S)
+#define HP_APM_REGION4_TEE_X_V  0x00000001U
+#define HP_APM_REGION4_TEE_X_S  12
+/** HP_APM_REGION4_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 4.
+ */
+#define HP_APM_REGION4_TEE_W    (BIT(13))
+#define HP_APM_REGION4_TEE_W_M  (HP_APM_REGION4_TEE_W_V << HP_APM_REGION4_TEE_W_S)
+#define HP_APM_REGION4_TEE_W_V  0x00000001U
+#define HP_APM_REGION4_TEE_W_S  13
+/** HP_APM_REGION4_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 4.
+ */
+#define HP_APM_REGION4_TEE_R    (BIT(14))
+#define HP_APM_REGION4_TEE_R_M  (HP_APM_REGION4_TEE_R_V << HP_APM_REGION4_TEE_R_S)
+#define HP_APM_REGION4_TEE_R_V  0x00000001U
+#define HP_APM_REGION4_TEE_R_S  14
+/** HP_APM_REGION4_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION4_LOCK    (BIT(16))
+#define HP_APM_REGION4_LOCK_M  (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S)
+#define HP_APM_REGION4_LOCK_V  0x00000001U
+#define HP_APM_REGION4_LOCK_S  16
+
+/** HP_APM_REGION5_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40)
+/** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 5.
+ */
+#define HP_APM_REGION5_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_START_M  (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S)
+#define HP_APM_REGION5_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_START_S  0
+
+/** HP_APM_REGION5_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44)
+/** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 5.
+ */
+#define HP_APM_REGION5_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_END_M  (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S)
+#define HP_APM_REGION5_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION5_ADDR_END_S  0
+
+/** HP_APM_REGION5_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48)
+/** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 5.
+ */
+#define HP_APM_REGION5_R0_X    (BIT(0))
+#define HP_APM_REGION5_R0_X_M  (HP_APM_REGION5_R0_X_V << HP_APM_REGION5_R0_X_S)
+#define HP_APM_REGION5_R0_X_V  0x00000001U
+#define HP_APM_REGION5_R0_X_S  0
+/** HP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 5.
+ */
+#define HP_APM_REGION5_R0_W    (BIT(1))
+#define HP_APM_REGION5_R0_W_M  (HP_APM_REGION5_R0_W_V << HP_APM_REGION5_R0_W_S)
+#define HP_APM_REGION5_R0_W_V  0x00000001U
+#define HP_APM_REGION5_R0_W_S  1
+/** HP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 5.
+ */
+#define HP_APM_REGION5_R0_R    (BIT(2))
+#define HP_APM_REGION5_R0_R_M  (HP_APM_REGION5_R0_R_V << HP_APM_REGION5_R0_R_S)
+#define HP_APM_REGION5_R0_R_V  0x00000001U
+#define HP_APM_REGION5_R0_R_S  2
+/** HP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 5.
+ */
+#define HP_APM_REGION5_R1_X    (BIT(4))
+#define HP_APM_REGION5_R1_X_M  (HP_APM_REGION5_R1_X_V << HP_APM_REGION5_R1_X_S)
+#define HP_APM_REGION5_R1_X_V  0x00000001U
+#define HP_APM_REGION5_R1_X_S  4
+/** HP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 5.
+ */
+#define HP_APM_REGION5_R1_W    (BIT(5))
+#define HP_APM_REGION5_R1_W_M  (HP_APM_REGION5_R1_W_V << HP_APM_REGION5_R1_W_S)
+#define HP_APM_REGION5_R1_W_V  0x00000001U
+#define HP_APM_REGION5_R1_W_S  5
+/** HP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 5.
+ */
+#define HP_APM_REGION5_R1_R    (BIT(6))
+#define HP_APM_REGION5_R1_R_M  (HP_APM_REGION5_R1_R_V << HP_APM_REGION5_R1_R_S)
+#define HP_APM_REGION5_R1_R_V  0x00000001U
+#define HP_APM_REGION5_R1_R_S  6
+/** HP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 5.
+ */
+#define HP_APM_REGION5_R2_X    (BIT(8))
+#define HP_APM_REGION5_R2_X_M  (HP_APM_REGION5_R2_X_V << HP_APM_REGION5_R2_X_S)
+#define HP_APM_REGION5_R2_X_V  0x00000001U
+#define HP_APM_REGION5_R2_X_S  8
+/** HP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 5.
+ */
+#define HP_APM_REGION5_R2_W    (BIT(9))
+#define HP_APM_REGION5_R2_W_M  (HP_APM_REGION5_R2_W_V << HP_APM_REGION5_R2_W_S)
+#define HP_APM_REGION5_R2_W_V  0x00000001U
+#define HP_APM_REGION5_R2_W_S  9
+/** HP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 5.
+ */
+#define HP_APM_REGION5_R2_R    (BIT(10))
+#define HP_APM_REGION5_R2_R_M  (HP_APM_REGION5_R2_R_V << HP_APM_REGION5_R2_R_S)
+#define HP_APM_REGION5_R2_R_V  0x00000001U
+#define HP_APM_REGION5_R2_R_S  10
+/** HP_APM_REGION5_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 5.
+ */
+#define HP_APM_REGION5_TEE_X    (BIT(12))
+#define HP_APM_REGION5_TEE_X_M  (HP_APM_REGION5_TEE_X_V << HP_APM_REGION5_TEE_X_S)
+#define HP_APM_REGION5_TEE_X_V  0x00000001U
+#define HP_APM_REGION5_TEE_X_S  12
+/** HP_APM_REGION5_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 5.
+ */
+#define HP_APM_REGION5_TEE_W    (BIT(13))
+#define HP_APM_REGION5_TEE_W_M  (HP_APM_REGION5_TEE_W_V << HP_APM_REGION5_TEE_W_S)
+#define HP_APM_REGION5_TEE_W_V  0x00000001U
+#define HP_APM_REGION5_TEE_W_S  13
+/** HP_APM_REGION5_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 5.
+ */
+#define HP_APM_REGION5_TEE_R    (BIT(14))
+#define HP_APM_REGION5_TEE_R_M  (HP_APM_REGION5_TEE_R_V << HP_APM_REGION5_TEE_R_S)
+#define HP_APM_REGION5_TEE_R_V  0x00000001U
+#define HP_APM_REGION5_TEE_R_S  14
+/** HP_APM_REGION5_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION5_LOCK    (BIT(16))
+#define HP_APM_REGION5_LOCK_M  (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S)
+#define HP_APM_REGION5_LOCK_V  0x00000001U
+#define HP_APM_REGION5_LOCK_S  16
+
+/** HP_APM_REGION6_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c)
+/** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 6.
+ */
+#define HP_APM_REGION6_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_START_M  (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S)
+#define HP_APM_REGION6_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_START_S  0
+
+/** HP_APM_REGION6_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50)
+/** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 6.
+ */
+#define HP_APM_REGION6_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_END_M  (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S)
+#define HP_APM_REGION6_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION6_ADDR_END_S  0
+
+/** HP_APM_REGION6_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54)
+/** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 6.
+ */
+#define HP_APM_REGION6_R0_X    (BIT(0))
+#define HP_APM_REGION6_R0_X_M  (HP_APM_REGION6_R0_X_V << HP_APM_REGION6_R0_X_S)
+#define HP_APM_REGION6_R0_X_V  0x00000001U
+#define HP_APM_REGION6_R0_X_S  0
+/** HP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 6.
+ */
+#define HP_APM_REGION6_R0_W    (BIT(1))
+#define HP_APM_REGION6_R0_W_M  (HP_APM_REGION6_R0_W_V << HP_APM_REGION6_R0_W_S)
+#define HP_APM_REGION6_R0_W_V  0x00000001U
+#define HP_APM_REGION6_R0_W_S  1
+/** HP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 6.
+ */
+#define HP_APM_REGION6_R0_R    (BIT(2))
+#define HP_APM_REGION6_R0_R_M  (HP_APM_REGION6_R0_R_V << HP_APM_REGION6_R0_R_S)
+#define HP_APM_REGION6_R0_R_V  0x00000001U
+#define HP_APM_REGION6_R0_R_S  2
+/** HP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 6.
+ */
+#define HP_APM_REGION6_R1_X    (BIT(4))
+#define HP_APM_REGION6_R1_X_M  (HP_APM_REGION6_R1_X_V << HP_APM_REGION6_R1_X_S)
+#define HP_APM_REGION6_R1_X_V  0x00000001U
+#define HP_APM_REGION6_R1_X_S  4
+/** HP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 6.
+ */
+#define HP_APM_REGION6_R1_W    (BIT(5))
+#define HP_APM_REGION6_R1_W_M  (HP_APM_REGION6_R1_W_V << HP_APM_REGION6_R1_W_S)
+#define HP_APM_REGION6_R1_W_V  0x00000001U
+#define HP_APM_REGION6_R1_W_S  5
+/** HP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 6.
+ */
+#define HP_APM_REGION6_R1_R    (BIT(6))
+#define HP_APM_REGION6_R1_R_M  (HP_APM_REGION6_R1_R_V << HP_APM_REGION6_R1_R_S)
+#define HP_APM_REGION6_R1_R_V  0x00000001U
+#define HP_APM_REGION6_R1_R_S  6
+/** HP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 6.
+ */
+#define HP_APM_REGION6_R2_X    (BIT(8))
+#define HP_APM_REGION6_R2_X_M  (HP_APM_REGION6_R2_X_V << HP_APM_REGION6_R2_X_S)
+#define HP_APM_REGION6_R2_X_V  0x00000001U
+#define HP_APM_REGION6_R2_X_S  8
+/** HP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 6.
+ */
+#define HP_APM_REGION6_R2_W    (BIT(9))
+#define HP_APM_REGION6_R2_W_M  (HP_APM_REGION6_R2_W_V << HP_APM_REGION6_R2_W_S)
+#define HP_APM_REGION6_R2_W_V  0x00000001U
+#define HP_APM_REGION6_R2_W_S  9
+/** HP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 6.
+ */
+#define HP_APM_REGION6_R2_R    (BIT(10))
+#define HP_APM_REGION6_R2_R_M  (HP_APM_REGION6_R2_R_V << HP_APM_REGION6_R2_R_S)
+#define HP_APM_REGION6_R2_R_V  0x00000001U
+#define HP_APM_REGION6_R2_R_S  10
+/** HP_APM_REGION6_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 6.
+ */
+#define HP_APM_REGION6_TEE_X    (BIT(12))
+#define HP_APM_REGION6_TEE_X_M  (HP_APM_REGION6_TEE_X_V << HP_APM_REGION6_TEE_X_S)
+#define HP_APM_REGION6_TEE_X_V  0x00000001U
+#define HP_APM_REGION6_TEE_X_S  12
+/** HP_APM_REGION6_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 6.
+ */
+#define HP_APM_REGION6_TEE_W    (BIT(13))
+#define HP_APM_REGION6_TEE_W_M  (HP_APM_REGION6_TEE_W_V << HP_APM_REGION6_TEE_W_S)
+#define HP_APM_REGION6_TEE_W_V  0x00000001U
+#define HP_APM_REGION6_TEE_W_S  13
+/** HP_APM_REGION6_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 6.
+ */
+#define HP_APM_REGION6_TEE_R    (BIT(14))
+#define HP_APM_REGION6_TEE_R_M  (HP_APM_REGION6_TEE_R_V << HP_APM_REGION6_TEE_R_S)
+#define HP_APM_REGION6_TEE_R_V  0x00000001U
+#define HP_APM_REGION6_TEE_R_S  14
+/** HP_APM_REGION6_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION6_LOCK    (BIT(16))
+#define HP_APM_REGION6_LOCK_M  (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S)
+#define HP_APM_REGION6_LOCK_V  0x00000001U
+#define HP_APM_REGION6_LOCK_S  16
+
+/** HP_APM_REGION7_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58)
+/** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 7.
+ */
+#define HP_APM_REGION7_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_START_M  (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S)
+#define HP_APM_REGION7_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_START_S  0
+
+/** HP_APM_REGION7_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c)
+/** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 7.
+ */
+#define HP_APM_REGION7_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_END_M  (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S)
+#define HP_APM_REGION7_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION7_ADDR_END_S  0
+
+/** HP_APM_REGION7_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60)
+/** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 7.
+ */
+#define HP_APM_REGION7_R0_X    (BIT(0))
+#define HP_APM_REGION7_R0_X_M  (HP_APM_REGION7_R0_X_V << HP_APM_REGION7_R0_X_S)
+#define HP_APM_REGION7_R0_X_V  0x00000001U
+#define HP_APM_REGION7_R0_X_S  0
+/** HP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 7.
+ */
+#define HP_APM_REGION7_R0_W    (BIT(1))
+#define HP_APM_REGION7_R0_W_M  (HP_APM_REGION7_R0_W_V << HP_APM_REGION7_R0_W_S)
+#define HP_APM_REGION7_R0_W_V  0x00000001U
+#define HP_APM_REGION7_R0_W_S  1
+/** HP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 7.
+ */
+#define HP_APM_REGION7_R0_R    (BIT(2))
+#define HP_APM_REGION7_R0_R_M  (HP_APM_REGION7_R0_R_V << HP_APM_REGION7_R0_R_S)
+#define HP_APM_REGION7_R0_R_V  0x00000001U
+#define HP_APM_REGION7_R0_R_S  2
+/** HP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 7.
+ */
+#define HP_APM_REGION7_R1_X    (BIT(4))
+#define HP_APM_REGION7_R1_X_M  (HP_APM_REGION7_R1_X_V << HP_APM_REGION7_R1_X_S)
+#define HP_APM_REGION7_R1_X_V  0x00000001U
+#define HP_APM_REGION7_R1_X_S  4
+/** HP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 7.
+ */
+#define HP_APM_REGION7_R1_W    (BIT(5))
+#define HP_APM_REGION7_R1_W_M  (HP_APM_REGION7_R1_W_V << HP_APM_REGION7_R1_W_S)
+#define HP_APM_REGION7_R1_W_V  0x00000001U
+#define HP_APM_REGION7_R1_W_S  5
+/** HP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 7.
+ */
+#define HP_APM_REGION7_R1_R    (BIT(6))
+#define HP_APM_REGION7_R1_R_M  (HP_APM_REGION7_R1_R_V << HP_APM_REGION7_R1_R_S)
+#define HP_APM_REGION7_R1_R_V  0x00000001U
+#define HP_APM_REGION7_R1_R_S  6
+/** HP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 7.
+ */
+#define HP_APM_REGION7_R2_X    (BIT(8))
+#define HP_APM_REGION7_R2_X_M  (HP_APM_REGION7_R2_X_V << HP_APM_REGION7_R2_X_S)
+#define HP_APM_REGION7_R2_X_V  0x00000001U
+#define HP_APM_REGION7_R2_X_S  8
+/** HP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 7.
+ */
+#define HP_APM_REGION7_R2_W    (BIT(9))
+#define HP_APM_REGION7_R2_W_M  (HP_APM_REGION7_R2_W_V << HP_APM_REGION7_R2_W_S)
+#define HP_APM_REGION7_R2_W_V  0x00000001U
+#define HP_APM_REGION7_R2_W_S  9
+/** HP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 7.
+ */
+#define HP_APM_REGION7_R2_R    (BIT(10))
+#define HP_APM_REGION7_R2_R_M  (HP_APM_REGION7_R2_R_V << HP_APM_REGION7_R2_R_S)
+#define HP_APM_REGION7_R2_R_V  0x00000001U
+#define HP_APM_REGION7_R2_R_S  10
+/** HP_APM_REGION7_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 7.
+ */
+#define HP_APM_REGION7_TEE_X    (BIT(12))
+#define HP_APM_REGION7_TEE_X_M  (HP_APM_REGION7_TEE_X_V << HP_APM_REGION7_TEE_X_S)
+#define HP_APM_REGION7_TEE_X_V  0x00000001U
+#define HP_APM_REGION7_TEE_X_S  12
+/** HP_APM_REGION7_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 7.
+ */
+#define HP_APM_REGION7_TEE_W    (BIT(13))
+#define HP_APM_REGION7_TEE_W_M  (HP_APM_REGION7_TEE_W_V << HP_APM_REGION7_TEE_W_S)
+#define HP_APM_REGION7_TEE_W_V  0x00000001U
+#define HP_APM_REGION7_TEE_W_S  13
+/** HP_APM_REGION7_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 7.
+ */
+#define HP_APM_REGION7_TEE_R    (BIT(14))
+#define HP_APM_REGION7_TEE_R_M  (HP_APM_REGION7_TEE_R_V << HP_APM_REGION7_TEE_R_S)
+#define HP_APM_REGION7_TEE_R_V  0x00000001U
+#define HP_APM_REGION7_TEE_R_S  14
+/** HP_APM_REGION7_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION7_LOCK    (BIT(16))
+#define HP_APM_REGION7_LOCK_M  (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S)
+#define HP_APM_REGION7_LOCK_V  0x00000001U
+#define HP_APM_REGION7_LOCK_S  16
+
+/** HP_APM_REGION8_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64)
+/** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 8.
+ */
+#define HP_APM_REGION8_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_START_M  (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S)
+#define HP_APM_REGION8_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_START_S  0
+
+/** HP_APM_REGION8_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68)
+/** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 8.
+ */
+#define HP_APM_REGION8_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_END_M  (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S)
+#define HP_APM_REGION8_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION8_ADDR_END_S  0
+
+/** HP_APM_REGION8_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c)
+/** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 8.
+ */
+#define HP_APM_REGION8_R0_X    (BIT(0))
+#define HP_APM_REGION8_R0_X_M  (HP_APM_REGION8_R0_X_V << HP_APM_REGION8_R0_X_S)
+#define HP_APM_REGION8_R0_X_V  0x00000001U
+#define HP_APM_REGION8_R0_X_S  0
+/** HP_APM_REGION8_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 8.
+ */
+#define HP_APM_REGION8_R0_W    (BIT(1))
+#define HP_APM_REGION8_R0_W_M  (HP_APM_REGION8_R0_W_V << HP_APM_REGION8_R0_W_S)
+#define HP_APM_REGION8_R0_W_V  0x00000001U
+#define HP_APM_REGION8_R0_W_S  1
+/** HP_APM_REGION8_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 8.
+ */
+#define HP_APM_REGION8_R0_R    (BIT(2))
+#define HP_APM_REGION8_R0_R_M  (HP_APM_REGION8_R0_R_V << HP_APM_REGION8_R0_R_S)
+#define HP_APM_REGION8_R0_R_V  0x00000001U
+#define HP_APM_REGION8_R0_R_S  2
+/** HP_APM_REGION8_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 8.
+ */
+#define HP_APM_REGION8_R1_X    (BIT(4))
+#define HP_APM_REGION8_R1_X_M  (HP_APM_REGION8_R1_X_V << HP_APM_REGION8_R1_X_S)
+#define HP_APM_REGION8_R1_X_V  0x00000001U
+#define HP_APM_REGION8_R1_X_S  4
+/** HP_APM_REGION8_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 8.
+ */
+#define HP_APM_REGION8_R1_W    (BIT(5))
+#define HP_APM_REGION8_R1_W_M  (HP_APM_REGION8_R1_W_V << HP_APM_REGION8_R1_W_S)
+#define HP_APM_REGION8_R1_W_V  0x00000001U
+#define HP_APM_REGION8_R1_W_S  5
+/** HP_APM_REGION8_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 8.
+ */
+#define HP_APM_REGION8_R1_R    (BIT(6))
+#define HP_APM_REGION8_R1_R_M  (HP_APM_REGION8_R1_R_V << HP_APM_REGION8_R1_R_S)
+#define HP_APM_REGION8_R1_R_V  0x00000001U
+#define HP_APM_REGION8_R1_R_S  6
+/** HP_APM_REGION8_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 8.
+ */
+#define HP_APM_REGION8_R2_X    (BIT(8))
+#define HP_APM_REGION8_R2_X_M  (HP_APM_REGION8_R2_X_V << HP_APM_REGION8_R2_X_S)
+#define HP_APM_REGION8_R2_X_V  0x00000001U
+#define HP_APM_REGION8_R2_X_S  8
+/** HP_APM_REGION8_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 8.
+ */
+#define HP_APM_REGION8_R2_W    (BIT(9))
+#define HP_APM_REGION8_R2_W_M  (HP_APM_REGION8_R2_W_V << HP_APM_REGION8_R2_W_S)
+#define HP_APM_REGION8_R2_W_V  0x00000001U
+#define HP_APM_REGION8_R2_W_S  9
+/** HP_APM_REGION8_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 8.
+ */
+#define HP_APM_REGION8_R2_R    (BIT(10))
+#define HP_APM_REGION8_R2_R_M  (HP_APM_REGION8_R2_R_V << HP_APM_REGION8_R2_R_S)
+#define HP_APM_REGION8_R2_R_V  0x00000001U
+#define HP_APM_REGION8_R2_R_S  10
+/** HP_APM_REGION8_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 8.
+ */
+#define HP_APM_REGION8_TEE_X    (BIT(12))
+#define HP_APM_REGION8_TEE_X_M  (HP_APM_REGION8_TEE_X_V << HP_APM_REGION8_TEE_X_S)
+#define HP_APM_REGION8_TEE_X_V  0x00000001U
+#define HP_APM_REGION8_TEE_X_S  12
+/** HP_APM_REGION8_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 8.
+ */
+#define HP_APM_REGION8_TEE_W    (BIT(13))
+#define HP_APM_REGION8_TEE_W_M  (HP_APM_REGION8_TEE_W_V << HP_APM_REGION8_TEE_W_S)
+#define HP_APM_REGION8_TEE_W_V  0x00000001U
+#define HP_APM_REGION8_TEE_W_S  13
+/** HP_APM_REGION8_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 8.
+ */
+#define HP_APM_REGION8_TEE_R    (BIT(14))
+#define HP_APM_REGION8_TEE_R_M  (HP_APM_REGION8_TEE_R_V << HP_APM_REGION8_TEE_R_S)
+#define HP_APM_REGION8_TEE_R_V  0x00000001U
+#define HP_APM_REGION8_TEE_R_S  14
+/** HP_APM_REGION8_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION8_LOCK    (BIT(16))
+#define HP_APM_REGION8_LOCK_M  (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S)
+#define HP_APM_REGION8_LOCK_V  0x00000001U
+#define HP_APM_REGION8_LOCK_S  16
+
+/** HP_APM_REGION9_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70)
+/** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 9.
+ */
+#define HP_APM_REGION9_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_START_M  (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S)
+#define HP_APM_REGION9_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_START_S  0
+
+/** HP_APM_REGION9_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74)
+/** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 9.
+ */
+#define HP_APM_REGION9_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_END_M  (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S)
+#define HP_APM_REGION9_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION9_ADDR_END_S  0
+
+/** HP_APM_REGION9_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78)
+/** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 9.
+ */
+#define HP_APM_REGION9_R0_X    (BIT(0))
+#define HP_APM_REGION9_R0_X_M  (HP_APM_REGION9_R0_X_V << HP_APM_REGION9_R0_X_S)
+#define HP_APM_REGION9_R0_X_V  0x00000001U
+#define HP_APM_REGION9_R0_X_S  0
+/** HP_APM_REGION9_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 9.
+ */
+#define HP_APM_REGION9_R0_W    (BIT(1))
+#define HP_APM_REGION9_R0_W_M  (HP_APM_REGION9_R0_W_V << HP_APM_REGION9_R0_W_S)
+#define HP_APM_REGION9_R0_W_V  0x00000001U
+#define HP_APM_REGION9_R0_W_S  1
+/** HP_APM_REGION9_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 9.
+ */
+#define HP_APM_REGION9_R0_R    (BIT(2))
+#define HP_APM_REGION9_R0_R_M  (HP_APM_REGION9_R0_R_V << HP_APM_REGION9_R0_R_S)
+#define HP_APM_REGION9_R0_R_V  0x00000001U
+#define HP_APM_REGION9_R0_R_S  2
+/** HP_APM_REGION9_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 9.
+ */
+#define HP_APM_REGION9_R1_X    (BIT(4))
+#define HP_APM_REGION9_R1_X_M  (HP_APM_REGION9_R1_X_V << HP_APM_REGION9_R1_X_S)
+#define HP_APM_REGION9_R1_X_V  0x00000001U
+#define HP_APM_REGION9_R1_X_S  4
+/** HP_APM_REGION9_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 9.
+ */
+#define HP_APM_REGION9_R1_W    (BIT(5))
+#define HP_APM_REGION9_R1_W_M  (HP_APM_REGION9_R1_W_V << HP_APM_REGION9_R1_W_S)
+#define HP_APM_REGION9_R1_W_V  0x00000001U
+#define HP_APM_REGION9_R1_W_S  5
+/** HP_APM_REGION9_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 9.
+ */
+#define HP_APM_REGION9_R1_R    (BIT(6))
+#define HP_APM_REGION9_R1_R_M  (HP_APM_REGION9_R1_R_V << HP_APM_REGION9_R1_R_S)
+#define HP_APM_REGION9_R1_R_V  0x00000001U
+#define HP_APM_REGION9_R1_R_S  6
+/** HP_APM_REGION9_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 9.
+ */
+#define HP_APM_REGION9_R2_X    (BIT(8))
+#define HP_APM_REGION9_R2_X_M  (HP_APM_REGION9_R2_X_V << HP_APM_REGION9_R2_X_S)
+#define HP_APM_REGION9_R2_X_V  0x00000001U
+#define HP_APM_REGION9_R2_X_S  8
+/** HP_APM_REGION9_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 9.
+ */
+#define HP_APM_REGION9_R2_W    (BIT(9))
+#define HP_APM_REGION9_R2_W_M  (HP_APM_REGION9_R2_W_V << HP_APM_REGION9_R2_W_S)
+#define HP_APM_REGION9_R2_W_V  0x00000001U
+#define HP_APM_REGION9_R2_W_S  9
+/** HP_APM_REGION9_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 9.
+ */
+#define HP_APM_REGION9_R2_R    (BIT(10))
+#define HP_APM_REGION9_R2_R_M  (HP_APM_REGION9_R2_R_V << HP_APM_REGION9_R2_R_S)
+#define HP_APM_REGION9_R2_R_V  0x00000001U
+#define HP_APM_REGION9_R2_R_S  10
+/** HP_APM_REGION9_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 9.
+ */
+#define HP_APM_REGION9_TEE_X    (BIT(12))
+#define HP_APM_REGION9_TEE_X_M  (HP_APM_REGION9_TEE_X_V << HP_APM_REGION9_TEE_X_S)
+#define HP_APM_REGION9_TEE_X_V  0x00000001U
+#define HP_APM_REGION9_TEE_X_S  12
+/** HP_APM_REGION9_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 9.
+ */
+#define HP_APM_REGION9_TEE_W    (BIT(13))
+#define HP_APM_REGION9_TEE_W_M  (HP_APM_REGION9_TEE_W_V << HP_APM_REGION9_TEE_W_S)
+#define HP_APM_REGION9_TEE_W_V  0x00000001U
+#define HP_APM_REGION9_TEE_W_S  13
+/** HP_APM_REGION9_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 9.
+ */
+#define HP_APM_REGION9_TEE_R    (BIT(14))
+#define HP_APM_REGION9_TEE_R_M  (HP_APM_REGION9_TEE_R_V << HP_APM_REGION9_TEE_R_S)
+#define HP_APM_REGION9_TEE_R_V  0x00000001U
+#define HP_APM_REGION9_TEE_R_S  14
+/** HP_APM_REGION9_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION9_LOCK    (BIT(16))
+#define HP_APM_REGION9_LOCK_M  (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S)
+#define HP_APM_REGION9_LOCK_V  0x00000001U
+#define HP_APM_REGION9_LOCK_S  16
+
+/** HP_APM_REGION10_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c)
+/** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 10.
+ */
+#define HP_APM_REGION10_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_START_M  (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S)
+#define HP_APM_REGION10_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_START_S  0
+
+/** HP_APM_REGION10_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80)
+/** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 10.
+ */
+#define HP_APM_REGION10_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_END_M  (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S)
+#define HP_APM_REGION10_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION10_ADDR_END_S  0
+
+/** HP_APM_REGION10_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84)
+/** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 10.
+ */
+#define HP_APM_REGION10_R0_X    (BIT(0))
+#define HP_APM_REGION10_R0_X_M  (HP_APM_REGION10_R0_X_V << HP_APM_REGION10_R0_X_S)
+#define HP_APM_REGION10_R0_X_V  0x00000001U
+#define HP_APM_REGION10_R0_X_S  0
+/** HP_APM_REGION10_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 10.
+ */
+#define HP_APM_REGION10_R0_W    (BIT(1))
+#define HP_APM_REGION10_R0_W_M  (HP_APM_REGION10_R0_W_V << HP_APM_REGION10_R0_W_S)
+#define HP_APM_REGION10_R0_W_V  0x00000001U
+#define HP_APM_REGION10_R0_W_S  1
+/** HP_APM_REGION10_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 10.
+ */
+#define HP_APM_REGION10_R0_R    (BIT(2))
+#define HP_APM_REGION10_R0_R_M  (HP_APM_REGION10_R0_R_V << HP_APM_REGION10_R0_R_S)
+#define HP_APM_REGION10_R0_R_V  0x00000001U
+#define HP_APM_REGION10_R0_R_S  2
+/** HP_APM_REGION10_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 10.
+ */
+#define HP_APM_REGION10_R1_X    (BIT(4))
+#define HP_APM_REGION10_R1_X_M  (HP_APM_REGION10_R1_X_V << HP_APM_REGION10_R1_X_S)
+#define HP_APM_REGION10_R1_X_V  0x00000001U
+#define HP_APM_REGION10_R1_X_S  4
+/** HP_APM_REGION10_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 10.
+ */
+#define HP_APM_REGION10_R1_W    (BIT(5))
+#define HP_APM_REGION10_R1_W_M  (HP_APM_REGION10_R1_W_V << HP_APM_REGION10_R1_W_S)
+#define HP_APM_REGION10_R1_W_V  0x00000001U
+#define HP_APM_REGION10_R1_W_S  5
+/** HP_APM_REGION10_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 10.
+ */
+#define HP_APM_REGION10_R1_R    (BIT(6))
+#define HP_APM_REGION10_R1_R_M  (HP_APM_REGION10_R1_R_V << HP_APM_REGION10_R1_R_S)
+#define HP_APM_REGION10_R1_R_V  0x00000001U
+#define HP_APM_REGION10_R1_R_S  6
+/** HP_APM_REGION10_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 10.
+ */
+#define HP_APM_REGION10_R2_X    (BIT(8))
+#define HP_APM_REGION10_R2_X_M  (HP_APM_REGION10_R2_X_V << HP_APM_REGION10_R2_X_S)
+#define HP_APM_REGION10_R2_X_V  0x00000001U
+#define HP_APM_REGION10_R2_X_S  8
+/** HP_APM_REGION10_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 10.
+ */
+#define HP_APM_REGION10_R2_W    (BIT(9))
+#define HP_APM_REGION10_R2_W_M  (HP_APM_REGION10_R2_W_V << HP_APM_REGION10_R2_W_S)
+#define HP_APM_REGION10_R2_W_V  0x00000001U
+#define HP_APM_REGION10_R2_W_S  9
+/** HP_APM_REGION10_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 10.
+ */
+#define HP_APM_REGION10_R2_R    (BIT(10))
+#define HP_APM_REGION10_R2_R_M  (HP_APM_REGION10_R2_R_V << HP_APM_REGION10_R2_R_S)
+#define HP_APM_REGION10_R2_R_V  0x00000001U
+#define HP_APM_REGION10_R2_R_S  10
+/** HP_APM_REGION10_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 10.
+ */
+#define HP_APM_REGION10_TEE_X    (BIT(12))
+#define HP_APM_REGION10_TEE_X_M  (HP_APM_REGION10_TEE_X_V << HP_APM_REGION10_TEE_X_S)
+#define HP_APM_REGION10_TEE_X_V  0x00000001U
+#define HP_APM_REGION10_TEE_X_S  12
+/** HP_APM_REGION10_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 10.
+ */
+#define HP_APM_REGION10_TEE_W    (BIT(13))
+#define HP_APM_REGION10_TEE_W_M  (HP_APM_REGION10_TEE_W_V << HP_APM_REGION10_TEE_W_S)
+#define HP_APM_REGION10_TEE_W_V  0x00000001U
+#define HP_APM_REGION10_TEE_W_S  13
+/** HP_APM_REGION10_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 10.
+ */
+#define HP_APM_REGION10_TEE_R    (BIT(14))
+#define HP_APM_REGION10_TEE_R_M  (HP_APM_REGION10_TEE_R_V << HP_APM_REGION10_TEE_R_S)
+#define HP_APM_REGION10_TEE_R_V  0x00000001U
+#define HP_APM_REGION10_TEE_R_S  14
+/** HP_APM_REGION10_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION10_LOCK    (BIT(16))
+#define HP_APM_REGION10_LOCK_M  (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S)
+#define HP_APM_REGION10_LOCK_V  0x00000001U
+#define HP_APM_REGION10_LOCK_S  16
+
+/** HP_APM_REGION11_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88)
+/** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 11.
+ */
+#define HP_APM_REGION11_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_START_M  (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S)
+#define HP_APM_REGION11_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_START_S  0
+
+/** HP_APM_REGION11_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c)
+/** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 11.
+ */
+#define HP_APM_REGION11_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_END_M  (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S)
+#define HP_APM_REGION11_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION11_ADDR_END_S  0
+
+/** HP_APM_REGION11_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90)
+/** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 11.
+ */
+#define HP_APM_REGION11_R0_X    (BIT(0))
+#define HP_APM_REGION11_R0_X_M  (HP_APM_REGION11_R0_X_V << HP_APM_REGION11_R0_X_S)
+#define HP_APM_REGION11_R0_X_V  0x00000001U
+#define HP_APM_REGION11_R0_X_S  0
+/** HP_APM_REGION11_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 11.
+ */
+#define HP_APM_REGION11_R0_W    (BIT(1))
+#define HP_APM_REGION11_R0_W_M  (HP_APM_REGION11_R0_W_V << HP_APM_REGION11_R0_W_S)
+#define HP_APM_REGION11_R0_W_V  0x00000001U
+#define HP_APM_REGION11_R0_W_S  1
+/** HP_APM_REGION11_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 11.
+ */
+#define HP_APM_REGION11_R0_R    (BIT(2))
+#define HP_APM_REGION11_R0_R_M  (HP_APM_REGION11_R0_R_V << HP_APM_REGION11_R0_R_S)
+#define HP_APM_REGION11_R0_R_V  0x00000001U
+#define HP_APM_REGION11_R0_R_S  2
+/** HP_APM_REGION11_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 11.
+ */
+#define HP_APM_REGION11_R1_X    (BIT(4))
+#define HP_APM_REGION11_R1_X_M  (HP_APM_REGION11_R1_X_V << HP_APM_REGION11_R1_X_S)
+#define HP_APM_REGION11_R1_X_V  0x00000001U
+#define HP_APM_REGION11_R1_X_S  4
+/** HP_APM_REGION11_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 11.
+ */
+#define HP_APM_REGION11_R1_W    (BIT(5))
+#define HP_APM_REGION11_R1_W_M  (HP_APM_REGION11_R1_W_V << HP_APM_REGION11_R1_W_S)
+#define HP_APM_REGION11_R1_W_V  0x00000001U
+#define HP_APM_REGION11_R1_W_S  5
+/** HP_APM_REGION11_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 11.
+ */
+#define HP_APM_REGION11_R1_R    (BIT(6))
+#define HP_APM_REGION11_R1_R_M  (HP_APM_REGION11_R1_R_V << HP_APM_REGION11_R1_R_S)
+#define HP_APM_REGION11_R1_R_V  0x00000001U
+#define HP_APM_REGION11_R1_R_S  6
+/** HP_APM_REGION11_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 11.
+ */
+#define HP_APM_REGION11_R2_X    (BIT(8))
+#define HP_APM_REGION11_R2_X_M  (HP_APM_REGION11_R2_X_V << HP_APM_REGION11_R2_X_S)
+#define HP_APM_REGION11_R2_X_V  0x00000001U
+#define HP_APM_REGION11_R2_X_S  8
+/** HP_APM_REGION11_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 11.
+ */
+#define HP_APM_REGION11_R2_W    (BIT(9))
+#define HP_APM_REGION11_R2_W_M  (HP_APM_REGION11_R2_W_V << HP_APM_REGION11_R2_W_S)
+#define HP_APM_REGION11_R2_W_V  0x00000001U
+#define HP_APM_REGION11_R2_W_S  9
+/** HP_APM_REGION11_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 11.
+ */
+#define HP_APM_REGION11_R2_R    (BIT(10))
+#define HP_APM_REGION11_R2_R_M  (HP_APM_REGION11_R2_R_V << HP_APM_REGION11_R2_R_S)
+#define HP_APM_REGION11_R2_R_V  0x00000001U
+#define HP_APM_REGION11_R2_R_S  10
+/** HP_APM_REGION11_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 11.
+ */
+#define HP_APM_REGION11_TEE_X    (BIT(12))
+#define HP_APM_REGION11_TEE_X_M  (HP_APM_REGION11_TEE_X_V << HP_APM_REGION11_TEE_X_S)
+#define HP_APM_REGION11_TEE_X_V  0x00000001U
+#define HP_APM_REGION11_TEE_X_S  12
+/** HP_APM_REGION11_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 11.
+ */
+#define HP_APM_REGION11_TEE_W    (BIT(13))
+#define HP_APM_REGION11_TEE_W_M  (HP_APM_REGION11_TEE_W_V << HP_APM_REGION11_TEE_W_S)
+#define HP_APM_REGION11_TEE_W_V  0x00000001U
+#define HP_APM_REGION11_TEE_W_S  13
+/** HP_APM_REGION11_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 11.
+ */
+#define HP_APM_REGION11_TEE_R    (BIT(14))
+#define HP_APM_REGION11_TEE_R_M  (HP_APM_REGION11_TEE_R_V << HP_APM_REGION11_TEE_R_S)
+#define HP_APM_REGION11_TEE_R_V  0x00000001U
+#define HP_APM_REGION11_TEE_R_S  14
+/** HP_APM_REGION11_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION11_LOCK    (BIT(16))
+#define HP_APM_REGION11_LOCK_M  (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S)
+#define HP_APM_REGION11_LOCK_V  0x00000001U
+#define HP_APM_REGION11_LOCK_S  16
+
+/** HP_APM_REGION12_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94)
+/** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 12.
+ */
+#define HP_APM_REGION12_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_START_M  (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S)
+#define HP_APM_REGION12_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_START_S  0
+
+/** HP_APM_REGION12_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98)
+/** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 12.
+ */
+#define HP_APM_REGION12_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_END_M  (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S)
+#define HP_APM_REGION12_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION12_ADDR_END_S  0
+
+/** HP_APM_REGION12_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c)
+/** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 12.
+ */
+#define HP_APM_REGION12_R0_X    (BIT(0))
+#define HP_APM_REGION12_R0_X_M  (HP_APM_REGION12_R0_X_V << HP_APM_REGION12_R0_X_S)
+#define HP_APM_REGION12_R0_X_V  0x00000001U
+#define HP_APM_REGION12_R0_X_S  0
+/** HP_APM_REGION12_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 12.
+ */
+#define HP_APM_REGION12_R0_W    (BIT(1))
+#define HP_APM_REGION12_R0_W_M  (HP_APM_REGION12_R0_W_V << HP_APM_REGION12_R0_W_S)
+#define HP_APM_REGION12_R0_W_V  0x00000001U
+#define HP_APM_REGION12_R0_W_S  1
+/** HP_APM_REGION12_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 12.
+ */
+#define HP_APM_REGION12_R0_R    (BIT(2))
+#define HP_APM_REGION12_R0_R_M  (HP_APM_REGION12_R0_R_V << HP_APM_REGION12_R0_R_S)
+#define HP_APM_REGION12_R0_R_V  0x00000001U
+#define HP_APM_REGION12_R0_R_S  2
+/** HP_APM_REGION12_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 12.
+ */
+#define HP_APM_REGION12_R1_X    (BIT(4))
+#define HP_APM_REGION12_R1_X_M  (HP_APM_REGION12_R1_X_V << HP_APM_REGION12_R1_X_S)
+#define HP_APM_REGION12_R1_X_V  0x00000001U
+#define HP_APM_REGION12_R1_X_S  4
+/** HP_APM_REGION12_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 12.
+ */
+#define HP_APM_REGION12_R1_W    (BIT(5))
+#define HP_APM_REGION12_R1_W_M  (HP_APM_REGION12_R1_W_V << HP_APM_REGION12_R1_W_S)
+#define HP_APM_REGION12_R1_W_V  0x00000001U
+#define HP_APM_REGION12_R1_W_S  5
+/** HP_APM_REGION12_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 12.
+ */
+#define HP_APM_REGION12_R1_R    (BIT(6))
+#define HP_APM_REGION12_R1_R_M  (HP_APM_REGION12_R1_R_V << HP_APM_REGION12_R1_R_S)
+#define HP_APM_REGION12_R1_R_V  0x00000001U
+#define HP_APM_REGION12_R1_R_S  6
+/** HP_APM_REGION12_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 12.
+ */
+#define HP_APM_REGION12_R2_X    (BIT(8))
+#define HP_APM_REGION12_R2_X_M  (HP_APM_REGION12_R2_X_V << HP_APM_REGION12_R2_X_S)
+#define HP_APM_REGION12_R2_X_V  0x00000001U
+#define HP_APM_REGION12_R2_X_S  8
+/** HP_APM_REGION12_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 12.
+ */
+#define HP_APM_REGION12_R2_W    (BIT(9))
+#define HP_APM_REGION12_R2_W_M  (HP_APM_REGION12_R2_W_V << HP_APM_REGION12_R2_W_S)
+#define HP_APM_REGION12_R2_W_V  0x00000001U
+#define HP_APM_REGION12_R2_W_S  9
+/** HP_APM_REGION12_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 12.
+ */
+#define HP_APM_REGION12_R2_R    (BIT(10))
+#define HP_APM_REGION12_R2_R_M  (HP_APM_REGION12_R2_R_V << HP_APM_REGION12_R2_R_S)
+#define HP_APM_REGION12_R2_R_V  0x00000001U
+#define HP_APM_REGION12_R2_R_S  10
+/** HP_APM_REGION12_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 12.
+ */
+#define HP_APM_REGION12_TEE_X    (BIT(12))
+#define HP_APM_REGION12_TEE_X_M  (HP_APM_REGION12_TEE_X_V << HP_APM_REGION12_TEE_X_S)
+#define HP_APM_REGION12_TEE_X_V  0x00000001U
+#define HP_APM_REGION12_TEE_X_S  12
+/** HP_APM_REGION12_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 12.
+ */
+#define HP_APM_REGION12_TEE_W    (BIT(13))
+#define HP_APM_REGION12_TEE_W_M  (HP_APM_REGION12_TEE_W_V << HP_APM_REGION12_TEE_W_S)
+#define HP_APM_REGION12_TEE_W_V  0x00000001U
+#define HP_APM_REGION12_TEE_W_S  13
+/** HP_APM_REGION12_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 12.
+ */
+#define HP_APM_REGION12_TEE_R    (BIT(14))
+#define HP_APM_REGION12_TEE_R_M  (HP_APM_REGION12_TEE_R_V << HP_APM_REGION12_TEE_R_S)
+#define HP_APM_REGION12_TEE_R_V  0x00000001U
+#define HP_APM_REGION12_TEE_R_S  14
+/** HP_APM_REGION12_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION12_LOCK    (BIT(16))
+#define HP_APM_REGION12_LOCK_M  (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S)
+#define HP_APM_REGION12_LOCK_V  0x00000001U
+#define HP_APM_REGION12_LOCK_S  16
+
+/** HP_APM_REGION13_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0)
+/** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 13.
+ */
+#define HP_APM_REGION13_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_START_M  (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S)
+#define HP_APM_REGION13_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_START_S  0
+
+/** HP_APM_REGION13_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4)
+/** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 13.
+ */
+#define HP_APM_REGION13_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_END_M  (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S)
+#define HP_APM_REGION13_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION13_ADDR_END_S  0
+
+/** HP_APM_REGION13_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8)
+/** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 13.
+ */
+#define HP_APM_REGION13_R0_X    (BIT(0))
+#define HP_APM_REGION13_R0_X_M  (HP_APM_REGION13_R0_X_V << HP_APM_REGION13_R0_X_S)
+#define HP_APM_REGION13_R0_X_V  0x00000001U
+#define HP_APM_REGION13_R0_X_S  0
+/** HP_APM_REGION13_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 13.
+ */
+#define HP_APM_REGION13_R0_W    (BIT(1))
+#define HP_APM_REGION13_R0_W_M  (HP_APM_REGION13_R0_W_V << HP_APM_REGION13_R0_W_S)
+#define HP_APM_REGION13_R0_W_V  0x00000001U
+#define HP_APM_REGION13_R0_W_S  1
+/** HP_APM_REGION13_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 13.
+ */
+#define HP_APM_REGION13_R0_R    (BIT(2))
+#define HP_APM_REGION13_R0_R_M  (HP_APM_REGION13_R0_R_V << HP_APM_REGION13_R0_R_S)
+#define HP_APM_REGION13_R0_R_V  0x00000001U
+#define HP_APM_REGION13_R0_R_S  2
+/** HP_APM_REGION13_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 13.
+ */
+#define HP_APM_REGION13_R1_X    (BIT(4))
+#define HP_APM_REGION13_R1_X_M  (HP_APM_REGION13_R1_X_V << HP_APM_REGION13_R1_X_S)
+#define HP_APM_REGION13_R1_X_V  0x00000001U
+#define HP_APM_REGION13_R1_X_S  4
+/** HP_APM_REGION13_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 13.
+ */
+#define HP_APM_REGION13_R1_W    (BIT(5))
+#define HP_APM_REGION13_R1_W_M  (HP_APM_REGION13_R1_W_V << HP_APM_REGION13_R1_W_S)
+#define HP_APM_REGION13_R1_W_V  0x00000001U
+#define HP_APM_REGION13_R1_W_S  5
+/** HP_APM_REGION13_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 13.
+ */
+#define HP_APM_REGION13_R1_R    (BIT(6))
+#define HP_APM_REGION13_R1_R_M  (HP_APM_REGION13_R1_R_V << HP_APM_REGION13_R1_R_S)
+#define HP_APM_REGION13_R1_R_V  0x00000001U
+#define HP_APM_REGION13_R1_R_S  6
+/** HP_APM_REGION13_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 13.
+ */
+#define HP_APM_REGION13_R2_X    (BIT(8))
+#define HP_APM_REGION13_R2_X_M  (HP_APM_REGION13_R2_X_V << HP_APM_REGION13_R2_X_S)
+#define HP_APM_REGION13_R2_X_V  0x00000001U
+#define HP_APM_REGION13_R2_X_S  8
+/** HP_APM_REGION13_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 13.
+ */
+#define HP_APM_REGION13_R2_W    (BIT(9))
+#define HP_APM_REGION13_R2_W_M  (HP_APM_REGION13_R2_W_V << HP_APM_REGION13_R2_W_S)
+#define HP_APM_REGION13_R2_W_V  0x00000001U
+#define HP_APM_REGION13_R2_W_S  9
+/** HP_APM_REGION13_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 13.
+ */
+#define HP_APM_REGION13_R2_R    (BIT(10))
+#define HP_APM_REGION13_R2_R_M  (HP_APM_REGION13_R2_R_V << HP_APM_REGION13_R2_R_S)
+#define HP_APM_REGION13_R2_R_V  0x00000001U
+#define HP_APM_REGION13_R2_R_S  10
+/** HP_APM_REGION13_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 13.
+ */
+#define HP_APM_REGION13_TEE_X    (BIT(12))
+#define HP_APM_REGION13_TEE_X_M  (HP_APM_REGION13_TEE_X_V << HP_APM_REGION13_TEE_X_S)
+#define HP_APM_REGION13_TEE_X_V  0x00000001U
+#define HP_APM_REGION13_TEE_X_S  12
+/** HP_APM_REGION13_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 13.
+ */
+#define HP_APM_REGION13_TEE_W    (BIT(13))
+#define HP_APM_REGION13_TEE_W_M  (HP_APM_REGION13_TEE_W_V << HP_APM_REGION13_TEE_W_S)
+#define HP_APM_REGION13_TEE_W_V  0x00000001U
+#define HP_APM_REGION13_TEE_W_S  13
+/** HP_APM_REGION13_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 13.
+ */
+#define HP_APM_REGION13_TEE_R    (BIT(14))
+#define HP_APM_REGION13_TEE_R_M  (HP_APM_REGION13_TEE_R_V << HP_APM_REGION13_TEE_R_S)
+#define HP_APM_REGION13_TEE_R_V  0x00000001U
+#define HP_APM_REGION13_TEE_R_S  14
+/** HP_APM_REGION13_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION13_LOCK    (BIT(16))
+#define HP_APM_REGION13_LOCK_M  (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S)
+#define HP_APM_REGION13_LOCK_V  0x00000001U
+#define HP_APM_REGION13_LOCK_S  16
+
+/** HP_APM_REGION14_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac)
+/** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 14.
+ */
+#define HP_APM_REGION14_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_START_M  (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S)
+#define HP_APM_REGION14_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_START_S  0
+
+/** HP_APM_REGION14_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0)
+/** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 14.
+ */
+#define HP_APM_REGION14_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_END_M  (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S)
+#define HP_APM_REGION14_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION14_ADDR_END_S  0
+
+/** HP_APM_REGION14_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4)
+/** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 14.
+ */
+#define HP_APM_REGION14_R0_X    (BIT(0))
+#define HP_APM_REGION14_R0_X_M  (HP_APM_REGION14_R0_X_V << HP_APM_REGION14_R0_X_S)
+#define HP_APM_REGION14_R0_X_V  0x00000001U
+#define HP_APM_REGION14_R0_X_S  0
+/** HP_APM_REGION14_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 14.
+ */
+#define HP_APM_REGION14_R0_W    (BIT(1))
+#define HP_APM_REGION14_R0_W_M  (HP_APM_REGION14_R0_W_V << HP_APM_REGION14_R0_W_S)
+#define HP_APM_REGION14_R0_W_V  0x00000001U
+#define HP_APM_REGION14_R0_W_S  1
+/** HP_APM_REGION14_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 14.
+ */
+#define HP_APM_REGION14_R0_R    (BIT(2))
+#define HP_APM_REGION14_R0_R_M  (HP_APM_REGION14_R0_R_V << HP_APM_REGION14_R0_R_S)
+#define HP_APM_REGION14_R0_R_V  0x00000001U
+#define HP_APM_REGION14_R0_R_S  2
+/** HP_APM_REGION14_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 14.
+ */
+#define HP_APM_REGION14_R1_X    (BIT(4))
+#define HP_APM_REGION14_R1_X_M  (HP_APM_REGION14_R1_X_V << HP_APM_REGION14_R1_X_S)
+#define HP_APM_REGION14_R1_X_V  0x00000001U
+#define HP_APM_REGION14_R1_X_S  4
+/** HP_APM_REGION14_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 14.
+ */
+#define HP_APM_REGION14_R1_W    (BIT(5))
+#define HP_APM_REGION14_R1_W_M  (HP_APM_REGION14_R1_W_V << HP_APM_REGION14_R1_W_S)
+#define HP_APM_REGION14_R1_W_V  0x00000001U
+#define HP_APM_REGION14_R1_W_S  5
+/** HP_APM_REGION14_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 14.
+ */
+#define HP_APM_REGION14_R1_R    (BIT(6))
+#define HP_APM_REGION14_R1_R_M  (HP_APM_REGION14_R1_R_V << HP_APM_REGION14_R1_R_S)
+#define HP_APM_REGION14_R1_R_V  0x00000001U
+#define HP_APM_REGION14_R1_R_S  6
+/** HP_APM_REGION14_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 14.
+ */
+#define HP_APM_REGION14_R2_X    (BIT(8))
+#define HP_APM_REGION14_R2_X_M  (HP_APM_REGION14_R2_X_V << HP_APM_REGION14_R2_X_S)
+#define HP_APM_REGION14_R2_X_V  0x00000001U
+#define HP_APM_REGION14_R2_X_S  8
+/** HP_APM_REGION14_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 14.
+ */
+#define HP_APM_REGION14_R2_W    (BIT(9))
+#define HP_APM_REGION14_R2_W_M  (HP_APM_REGION14_R2_W_V << HP_APM_REGION14_R2_W_S)
+#define HP_APM_REGION14_R2_W_V  0x00000001U
+#define HP_APM_REGION14_R2_W_S  9
+/** HP_APM_REGION14_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 14.
+ */
+#define HP_APM_REGION14_R2_R    (BIT(10))
+#define HP_APM_REGION14_R2_R_M  (HP_APM_REGION14_R2_R_V << HP_APM_REGION14_R2_R_S)
+#define HP_APM_REGION14_R2_R_V  0x00000001U
+#define HP_APM_REGION14_R2_R_S  10
+/** HP_APM_REGION14_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 14.
+ */
+#define HP_APM_REGION14_TEE_X    (BIT(12))
+#define HP_APM_REGION14_TEE_X_M  (HP_APM_REGION14_TEE_X_V << HP_APM_REGION14_TEE_X_S)
+#define HP_APM_REGION14_TEE_X_V  0x00000001U
+#define HP_APM_REGION14_TEE_X_S  12
+/** HP_APM_REGION14_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 14.
+ */
+#define HP_APM_REGION14_TEE_W    (BIT(13))
+#define HP_APM_REGION14_TEE_W_M  (HP_APM_REGION14_TEE_W_V << HP_APM_REGION14_TEE_W_S)
+#define HP_APM_REGION14_TEE_W_V  0x00000001U
+#define HP_APM_REGION14_TEE_W_S  13
+/** HP_APM_REGION14_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 14.
+ */
+#define HP_APM_REGION14_TEE_R    (BIT(14))
+#define HP_APM_REGION14_TEE_R_M  (HP_APM_REGION14_TEE_R_V << HP_APM_REGION14_TEE_R_S)
+#define HP_APM_REGION14_TEE_R_V  0x00000001U
+#define HP_APM_REGION14_TEE_R_S  14
+/** HP_APM_REGION14_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION14_LOCK    (BIT(16))
+#define HP_APM_REGION14_LOCK_M  (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S)
+#define HP_APM_REGION14_LOCK_V  0x00000001U
+#define HP_APM_REGION14_LOCK_S  16
+
+/** HP_APM_REGION15_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8)
+/** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0;
+ *  Configures start address of region 15.
+ */
+#define HP_APM_REGION15_ADDR_START    0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_START_M  (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S)
+#define HP_APM_REGION15_ADDR_START_V  0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_START_S  0
+
+/** HP_APM_REGION15_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc)
+/** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Configures end address of region 15.
+ */
+#define HP_APM_REGION15_ADDR_END    0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_END_M  (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S)
+#define HP_APM_REGION15_ADDR_END_V  0xFFFFFFFFU
+#define HP_APM_REGION15_ADDR_END_S  0
+
+/** HP_APM_REGION15_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0)
+/** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 15.
+ */
+#define HP_APM_REGION15_R0_X    (BIT(0))
+#define HP_APM_REGION15_R0_X_M  (HP_APM_REGION15_R0_X_V << HP_APM_REGION15_R0_X_S)
+#define HP_APM_REGION15_R0_X_V  0x00000001U
+#define HP_APM_REGION15_R0_X_S  0
+/** HP_APM_REGION15_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 15.
+ */
+#define HP_APM_REGION15_R0_W    (BIT(1))
+#define HP_APM_REGION15_R0_W_M  (HP_APM_REGION15_R0_W_V << HP_APM_REGION15_R0_W_S)
+#define HP_APM_REGION15_R0_W_V  0x00000001U
+#define HP_APM_REGION15_R0_W_S  1
+/** HP_APM_REGION15_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 15.
+ */
+#define HP_APM_REGION15_R0_R    (BIT(2))
+#define HP_APM_REGION15_R0_R_M  (HP_APM_REGION15_R0_R_V << HP_APM_REGION15_R0_R_S)
+#define HP_APM_REGION15_R0_R_V  0x00000001U
+#define HP_APM_REGION15_R0_R_S  2
+/** HP_APM_REGION15_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 15.
+ */
+#define HP_APM_REGION15_R1_X    (BIT(4))
+#define HP_APM_REGION15_R1_X_M  (HP_APM_REGION15_R1_X_V << HP_APM_REGION15_R1_X_S)
+#define HP_APM_REGION15_R1_X_V  0x00000001U
+#define HP_APM_REGION15_R1_X_S  4
+/** HP_APM_REGION15_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 15.
+ */
+#define HP_APM_REGION15_R1_W    (BIT(5))
+#define HP_APM_REGION15_R1_W_M  (HP_APM_REGION15_R1_W_V << HP_APM_REGION15_R1_W_S)
+#define HP_APM_REGION15_R1_W_V  0x00000001U
+#define HP_APM_REGION15_R1_W_S  5
+/** HP_APM_REGION15_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 15.
+ */
+#define HP_APM_REGION15_R1_R    (BIT(6))
+#define HP_APM_REGION15_R1_R_M  (HP_APM_REGION15_R1_R_V << HP_APM_REGION15_R1_R_S)
+#define HP_APM_REGION15_R1_R_V  0x00000001U
+#define HP_APM_REGION15_R1_R_S  6
+/** HP_APM_REGION15_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 15.
+ */
+#define HP_APM_REGION15_R2_X    (BIT(8))
+#define HP_APM_REGION15_R2_X_M  (HP_APM_REGION15_R2_X_V << HP_APM_REGION15_R2_X_S)
+#define HP_APM_REGION15_R2_X_V  0x00000001U
+#define HP_APM_REGION15_R2_X_S  8
+/** HP_APM_REGION15_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 15.
+ */
+#define HP_APM_REGION15_R2_W    (BIT(9))
+#define HP_APM_REGION15_R2_W_M  (HP_APM_REGION15_R2_W_V << HP_APM_REGION15_R2_W_S)
+#define HP_APM_REGION15_R2_W_V  0x00000001U
+#define HP_APM_REGION15_R2_W_S  9
+/** HP_APM_REGION15_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 15.
+ */
+#define HP_APM_REGION15_R2_R    (BIT(10))
+#define HP_APM_REGION15_R2_R_M  (HP_APM_REGION15_R2_R_V << HP_APM_REGION15_R2_R_S)
+#define HP_APM_REGION15_R2_R_V  0x00000001U
+#define HP_APM_REGION15_R2_R_S  10
+/** HP_APM_REGION15_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 15.
+ */
+#define HP_APM_REGION15_TEE_X    (BIT(12))
+#define HP_APM_REGION15_TEE_X_M  (HP_APM_REGION15_TEE_X_V << HP_APM_REGION15_TEE_X_S)
+#define HP_APM_REGION15_TEE_X_V  0x00000001U
+#define HP_APM_REGION15_TEE_X_S  12
+/** HP_APM_REGION15_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 15.
+ */
+#define HP_APM_REGION15_TEE_W    (BIT(13))
+#define HP_APM_REGION15_TEE_W_M  (HP_APM_REGION15_TEE_W_V << HP_APM_REGION15_TEE_W_S)
+#define HP_APM_REGION15_TEE_W_V  0x00000001U
+#define HP_APM_REGION15_TEE_W_S  13
+/** HP_APM_REGION15_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 15.
+ */
+#define HP_APM_REGION15_TEE_R    (BIT(14))
+#define HP_APM_REGION15_TEE_R_M  (HP_APM_REGION15_TEE_R_V << HP_APM_REGION15_TEE_R_S)
+#define HP_APM_REGION15_TEE_R_V  0x00000001U
+#define HP_APM_REGION15_TEE_R_S  14
+/** HP_APM_REGION15_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_APM_REGION15_LOCK    (BIT(16))
+#define HP_APM_REGION15_LOCK_M  (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S)
+#define HP_APM_REGION15_LOCK_V  0x00000001U
+#define HP_APM_REGION15_LOCK_S  16
+
+/** HP_APM_FUNC_CTRL_REG register
+ *  APM function control register
+ */
+#define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4)
+/** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define HP_APM_M0_FUNC_EN    (BIT(0))
+#define HP_APM_M0_FUNC_EN_M  (HP_APM_M0_FUNC_EN_V << HP_APM_M0_FUNC_EN_S)
+#define HP_APM_M0_FUNC_EN_V  0x00000001U
+#define HP_APM_M0_FUNC_EN_S  0
+/** HP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1;
+ *  PMS M1 function enable
+ */
+#define HP_APM_M1_FUNC_EN    (BIT(1))
+#define HP_APM_M1_FUNC_EN_M  (HP_APM_M1_FUNC_EN_V << HP_APM_M1_FUNC_EN_S)
+#define HP_APM_M1_FUNC_EN_V  0x00000001U
+#define HP_APM_M1_FUNC_EN_S  1
+/** HP_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1;
+ *  PMS M2 function enable
+ */
+#define HP_APM_M2_FUNC_EN    (BIT(2))
+#define HP_APM_M2_FUNC_EN_M  (HP_APM_M2_FUNC_EN_V << HP_APM_M2_FUNC_EN_S)
+#define HP_APM_M2_FUNC_EN_V  0x00000001U
+#define HP_APM_M2_FUNC_EN_S  2
+/** HP_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1;
+ *  PMS M3 function enable
+ */
+#define HP_APM_M3_FUNC_EN    (BIT(3))
+#define HP_APM_M3_FUNC_EN_M  (HP_APM_M3_FUNC_EN_V << HP_APM_M3_FUNC_EN_S)
+#define HP_APM_M3_FUNC_EN_V  0x00000001U
+#define HP_APM_M3_FUNC_EN_S  3
+/** HP_APM_M4_FUNC_EN : R/W; bitpos: [4]; default: 1;
+ *  PMS M4 function enable
+ */
+#define HP_APM_M4_FUNC_EN    (BIT(4))
+#define HP_APM_M4_FUNC_EN_M  (HP_APM_M4_FUNC_EN_V << HP_APM_M4_FUNC_EN_S)
+#define HP_APM_M4_FUNC_EN_V  0x00000001U
+#define HP_APM_M4_FUNC_EN_S  4
+/** HP_APM_M5_FUNC_EN : R/W; bitpos: [5]; default: 1;
+ *  PMS M5 function enable
+ */
+#define HP_APM_M5_FUNC_EN    (BIT(5))
+#define HP_APM_M5_FUNC_EN_M  (HP_APM_M5_FUNC_EN_V << HP_APM_M5_FUNC_EN_S)
+#define HP_APM_M5_FUNC_EN_V  0x00000001U
+#define HP_APM_M5_FUNC_EN_S  5
+/** HP_APM_M6_FUNC_EN : R/W; bitpos: [6]; default: 1;
+ *  PMS M6 function enable
+ */
+#define HP_APM_M6_FUNC_EN    (BIT(6))
+#define HP_APM_M6_FUNC_EN_M  (HP_APM_M6_FUNC_EN_V << HP_APM_M6_FUNC_EN_S)
+#define HP_APM_M6_FUNC_EN_V  0x00000001U
+#define HP_APM_M6_FUNC_EN_S  6
+
+/** HP_APM_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8)
+/** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M0_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M0_EXCEPTION_STATUS_M  (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S)
+#define HP_APM_M0_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M0_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc)
+/** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M0_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M0_EXCEPTION_STATUS_CLR_M  (HP_APM_M0_EXCEPTION_STATUS_CLR_V << HP_APM_M0_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M0_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M0_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0)
+/** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M0_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M0_EXCEPTION_REGION_M  (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S)
+#define HP_APM_M0_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M0_EXCEPTION_REGION_S  0
+/** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M0_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M0_EXCEPTION_MODE_M  (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S)
+#define HP_APM_M0_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M0_EXCEPTION_MODE_S  16
+/** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M0_EXCEPTION_ID    0x0000003FU
+#define HP_APM_M0_EXCEPTION_ID_M  (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S)
+#define HP_APM_M0_EXCEPTION_ID_V  0x0000003FU
+#define HP_APM_M0_EXCEPTION_ID_S  18
+
+/** HP_APM_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4)
+/** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M0_EXCEPTION_ADDR_M  (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S)
+#define HP_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M0_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M1_STATUS_REG register
+ *  M1 status register
+ */
+#define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8)
+/** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M1_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M1_EXCEPTION_STATUS_M  (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S)
+#define HP_APM_M1_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M1_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M1_STATUS_CLR_REG register
+ *  M1 status clear register
+ */
+#define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc)
+/** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M1_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M1_EXCEPTION_STATUS_CLR_M  (HP_APM_M1_EXCEPTION_STATUS_CLR_V << HP_APM_M1_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M1_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M1_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M1_EXCEPTION_INFO0_REG register
+ *  M1 exception_info0 register
+ */
+#define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0)
+/** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M1_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M1_EXCEPTION_REGION_M  (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S)
+#define HP_APM_M1_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M1_EXCEPTION_REGION_S  0
+/** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M1_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M1_EXCEPTION_MODE_M  (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S)
+#define HP_APM_M1_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M1_EXCEPTION_MODE_S  16
+/** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M1_EXCEPTION_ID    0x0000003FU
+#define HP_APM_M1_EXCEPTION_ID_M  (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S)
+#define HP_APM_M1_EXCEPTION_ID_V  0x0000003FU
+#define HP_APM_M1_EXCEPTION_ID_S  18
+
+/** HP_APM_M1_EXCEPTION_INFO1_REG register
+ *  M1 exception_info1 register
+ */
+#define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4)
+/** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M1_EXCEPTION_ADDR_M  (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S)
+#define HP_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M1_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M2_STATUS_REG register
+ *  M2 status register
+ */
+#define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8)
+/** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M2_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M2_EXCEPTION_STATUS_M  (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S)
+#define HP_APM_M2_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M2_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M2_STATUS_CLR_REG register
+ *  M2 status clear register
+ */
+#define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec)
+/** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M2_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M2_EXCEPTION_STATUS_CLR_M  (HP_APM_M2_EXCEPTION_STATUS_CLR_V << HP_APM_M2_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M2_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M2_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M2_EXCEPTION_INFO0_REG register
+ *  M2 exception_info0 register
+ */
+#define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0)
+/** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M2_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M2_EXCEPTION_REGION_M  (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S)
+#define HP_APM_M2_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M2_EXCEPTION_REGION_S  0
+/** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M2_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M2_EXCEPTION_MODE_M  (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S)
+#define HP_APM_M2_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M2_EXCEPTION_MODE_S  16
+/** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M2_EXCEPTION_ID    0x0000003FU
+#define HP_APM_M2_EXCEPTION_ID_M  (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S)
+#define HP_APM_M2_EXCEPTION_ID_V  0x0000003FU
+#define HP_APM_M2_EXCEPTION_ID_S  18
+
+/** HP_APM_M2_EXCEPTION_INFO1_REG register
+ *  M2 exception_info1 register
+ */
+#define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4)
+/** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M2_EXCEPTION_ADDR_M  (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S)
+#define HP_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M2_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M3_STATUS_REG register
+ *  M3 status register
+ */
+#define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8)
+/** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M3_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M3_EXCEPTION_STATUS_M  (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S)
+#define HP_APM_M3_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M3_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M3_STATUS_CLR_REG register
+ *  M3 status clear register
+ */
+#define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc)
+/** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M3_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M3_EXCEPTION_STATUS_CLR_M  (HP_APM_M3_EXCEPTION_STATUS_CLR_V << HP_APM_M3_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M3_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M3_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M3_EXCEPTION_INFO0_REG register
+ *  M3 exception_info0 register
+ */
+#define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100)
+/** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M3_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M3_EXCEPTION_REGION_M  (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S)
+#define HP_APM_M3_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M3_EXCEPTION_REGION_S  0
+/** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M3_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M3_EXCEPTION_MODE_M  (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S)
+#define HP_APM_M3_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M3_EXCEPTION_MODE_S  16
+/** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M3_EXCEPTION_ID    0x0000003FU
+#define HP_APM_M3_EXCEPTION_ID_M  (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S)
+#define HP_APM_M3_EXCEPTION_ID_V  0x0000003FU
+#define HP_APM_M3_EXCEPTION_ID_S  18
+
+/** HP_APM_M3_EXCEPTION_INFO1_REG register
+ *  M3 exception_info1 register
+ */
+#define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104)
+/** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M3_EXCEPTION_ADDR_M  (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S)
+#define HP_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M3_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M4_STATUS_REG register
+ *  M4 status register
+ */
+#define HP_APM_M4_STATUS_REG (DR_REG_HP_APM_BASE + 0x108)
+/** HP_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M4_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M4_EXCEPTION_STATUS_M  (HP_APM_M4_EXCEPTION_STATUS_V << HP_APM_M4_EXCEPTION_STATUS_S)
+#define HP_APM_M4_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M4_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M4_STATUS_CLR_REG register
+ *  M4 status clear register
+ */
+#define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x10c)
+/** HP_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M4_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M4_EXCEPTION_STATUS_CLR_M  (HP_APM_M4_EXCEPTION_STATUS_CLR_V << HP_APM_M4_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M4_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M4_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M4_EXCEPTION_INFO0_REG register
+ *  M4 exception_info0 register
+ */
+#define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x110)
+/** HP_APM_M4_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M4_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M4_EXCEPTION_REGION_M  (HP_APM_M4_EXCEPTION_REGION_V << HP_APM_M4_EXCEPTION_REGION_S)
+#define HP_APM_M4_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M4_EXCEPTION_REGION_S  0
+/** HP_APM_M4_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M4_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M4_EXCEPTION_MODE_M  (HP_APM_M4_EXCEPTION_MODE_V << HP_APM_M4_EXCEPTION_MODE_S)
+#define HP_APM_M4_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M4_EXCEPTION_MODE_S  16
+/** HP_APM_M4_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M4_EXCEPTION_ID    0x0000003FU
+#define HP_APM_M4_EXCEPTION_ID_M  (HP_APM_M4_EXCEPTION_ID_V << HP_APM_M4_EXCEPTION_ID_S)
+#define HP_APM_M4_EXCEPTION_ID_V  0x0000003FU
+#define HP_APM_M4_EXCEPTION_ID_S  18
+
+/** HP_APM_M4_EXCEPTION_INFO1_REG register
+ *  M4 exception_info1 register
+ */
+#define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x114)
+/** HP_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M4_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M4_EXCEPTION_ADDR_M  (HP_APM_M4_EXCEPTION_ADDR_V << HP_APM_M4_EXCEPTION_ADDR_S)
+#define HP_APM_M4_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M4_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M5_STATUS_REG register
+ *  M5 status register
+ */
+#define HP_APM_M5_STATUS_REG (DR_REG_HP_APM_BASE + 0x118)
+/** HP_APM_M5_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M5_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M5_EXCEPTION_STATUS_M  (HP_APM_M5_EXCEPTION_STATUS_V << HP_APM_M5_EXCEPTION_STATUS_S)
+#define HP_APM_M5_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M5_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M5_STATUS_CLR_REG register
+ *  M5 status clear register
+ */
+#define HP_APM_M5_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x11c)
+/** HP_APM_M5_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M5_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M5_EXCEPTION_STATUS_CLR_M  (HP_APM_M5_EXCEPTION_STATUS_CLR_V << HP_APM_M5_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M5_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M5_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M5_EXCEPTION_INFO0_REG register
+ *  M5 exception_info0 register
+ */
+#define HP_APM_M5_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x120)
+/** HP_APM_M5_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M5_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M5_EXCEPTION_REGION_M  (HP_APM_M5_EXCEPTION_REGION_V << HP_APM_M5_EXCEPTION_REGION_S)
+#define HP_APM_M5_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M5_EXCEPTION_REGION_S  0
+/** HP_APM_M5_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M5_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M5_EXCEPTION_MODE_M  (HP_APM_M5_EXCEPTION_MODE_V << HP_APM_M5_EXCEPTION_MODE_S)
+#define HP_APM_M5_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M5_EXCEPTION_MODE_S  16
+/** HP_APM_M5_EXCEPTION_ID : RO; bitpos: [24:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M5_EXCEPTION_ID    0x0000007FU
+#define HP_APM_M5_EXCEPTION_ID_M  (HP_APM_M5_EXCEPTION_ID_V << HP_APM_M5_EXCEPTION_ID_S)
+#define HP_APM_M5_EXCEPTION_ID_V  0x0000007FU
+#define HP_APM_M5_EXCEPTION_ID_S  18
+
+/** HP_APM_M5_EXCEPTION_INFO1_REG register
+ *  M5 exception_info1 register
+ */
+#define HP_APM_M5_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x124)
+/** HP_APM_M5_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M5_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M5_EXCEPTION_ADDR_M  (HP_APM_M5_EXCEPTION_ADDR_V << HP_APM_M5_EXCEPTION_ADDR_S)
+#define HP_APM_M5_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M5_EXCEPTION_ADDR_S  0
+
+/** HP_APM_M6_STATUS_REG register
+ *  M6 status register
+ */
+#define HP_APM_M6_STATUS_REG (DR_REG_HP_APM_BASE + 0x12c)
+/** HP_APM_M6_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_APM_M6_EXCEPTION_STATUS    0x00000003U
+#define HP_APM_M6_EXCEPTION_STATUS_M  (HP_APM_M6_EXCEPTION_STATUS_V << HP_APM_M6_EXCEPTION_STATUS_S)
+#define HP_APM_M6_EXCEPTION_STATUS_V  0x00000003U
+#define HP_APM_M6_EXCEPTION_STATUS_S  0
+
+/** HP_APM_M6_STATUS_CLR_REG register
+ *  M6 status clear register
+ */
+#define HP_APM_M6_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x130)
+/** HP_APM_M6_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_APM_M6_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_APM_M6_EXCEPTION_STATUS_CLR_M  (HP_APM_M6_EXCEPTION_STATUS_CLR_V << HP_APM_M6_EXCEPTION_STATUS_CLR_S)
+#define HP_APM_M6_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_APM_M6_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_APM_M6_EXCEPTION_INFO0_REG register
+ *  M6 exception_info0 register
+ */
+#define HP_APM_M6_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x134)
+/** HP_APM_M6_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_APM_M6_EXCEPTION_REGION    0x0000FFFFU
+#define HP_APM_M6_EXCEPTION_REGION_M  (HP_APM_M6_EXCEPTION_REGION_V << HP_APM_M6_EXCEPTION_REGION_S)
+#define HP_APM_M6_EXCEPTION_REGION_V  0x0000FFFFU
+#define HP_APM_M6_EXCEPTION_REGION_S  0
+/** HP_APM_M6_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_APM_M6_EXCEPTION_MODE    0x00000003U
+#define HP_APM_M6_EXCEPTION_MODE_M  (HP_APM_M6_EXCEPTION_MODE_V << HP_APM_M6_EXCEPTION_MODE_S)
+#define HP_APM_M6_EXCEPTION_MODE_V  0x00000003U
+#define HP_APM_M6_EXCEPTION_MODE_S  16
+/** HP_APM_M6_EXCEPTION_ID : RO; bitpos: [24:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_APM_M6_EXCEPTION_ID    0x0000007FU
+#define HP_APM_M6_EXCEPTION_ID_M  (HP_APM_M6_EXCEPTION_ID_V << HP_APM_M6_EXCEPTION_ID_S)
+#define HP_APM_M6_EXCEPTION_ID_V  0x0000007FU
+#define HP_APM_M6_EXCEPTION_ID_S  18
+
+/** HP_APM_M6_EXCEPTION_INFO1_REG register
+ *  M6 exception_info1 register
+ */
+#define HP_APM_M6_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x138)
+/** HP_APM_M6_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_APM_M6_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_APM_M6_EXCEPTION_ADDR_M  (HP_APM_M6_EXCEPTION_ADDR_V << HP_APM_M6_EXCEPTION_ADDR_S)
+#define HP_APM_M6_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_APM_M6_EXCEPTION_ADDR_S  0
+
+/** HP_APM_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x14c)
+/** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures to enable APM M0 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M0_APM_INT_EN    (BIT(0))
+#define HP_APM_M0_APM_INT_EN_M  (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S)
+#define HP_APM_M0_APM_INT_EN_V  0x00000001U
+#define HP_APM_M0_APM_INT_EN_S  0
+/** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures to enable APM M1 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M1_APM_INT_EN    (BIT(1))
+#define HP_APM_M1_APM_INT_EN_M  (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S)
+#define HP_APM_M1_APM_INT_EN_V  0x00000001U
+#define HP_APM_M1_APM_INT_EN_S  1
+/** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures to enable APM M2 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M2_APM_INT_EN    (BIT(2))
+#define HP_APM_M2_APM_INT_EN_M  (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S)
+#define HP_APM_M2_APM_INT_EN_V  0x00000001U
+#define HP_APM_M2_APM_INT_EN_S  2
+/** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures to enable APM M3 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M3_APM_INT_EN    (BIT(3))
+#define HP_APM_M3_APM_INT_EN_M  (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S)
+#define HP_APM_M3_APM_INT_EN_V  0x00000001U
+#define HP_APM_M3_APM_INT_EN_S  3
+/** HP_APM_M4_APM_INT_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures to enable APM M4 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M4_APM_INT_EN    (BIT(4))
+#define HP_APM_M4_APM_INT_EN_M  (HP_APM_M4_APM_INT_EN_V << HP_APM_M4_APM_INT_EN_S)
+#define HP_APM_M4_APM_INT_EN_V  0x00000001U
+#define HP_APM_M4_APM_INT_EN_S  4
+/** HP_APM_M5_APM_INT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures to enable APM M5 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M5_APM_INT_EN    (BIT(5))
+#define HP_APM_M5_APM_INT_EN_M  (HP_APM_M5_APM_INT_EN_V << HP_APM_M5_APM_INT_EN_S)
+#define HP_APM_M5_APM_INT_EN_V  0x00000001U
+#define HP_APM_M5_APM_INT_EN_S  5
+/** HP_APM_M6_APM_INT_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures to enable APM M6 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_APM_M6_APM_INT_EN    (BIT(6))
+#define HP_APM_M6_APM_INT_EN_M  (HP_APM_M6_APM_INT_EN_V << HP_APM_M6_APM_INT_EN_S)
+#define HP_APM_M6_APM_INT_EN_V  0x00000001U
+#define HP_APM_M6_APM_INT_EN_S  6
+
+/** HP_APM_AXI_BLOCK_EN_REG register
+ *  M6 status clear register
+ */
+#define HP_APM_AXI_BLOCK_EN_REG (DR_REG_HP_APM_BASE + 0x150)
+/** HP_APM_AXI_BLOCK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures to if block transmission when get exceltion.
+ *  0: transparent transmission to slave
+ *  1: don't transparent transmission to slave
+ */
+#define HP_APM_AXI_BLOCK_EN    (BIT(0))
+#define HP_APM_AXI_BLOCK_EN_M  (HP_APM_AXI_BLOCK_EN_V << HP_APM_AXI_BLOCK_EN_S)
+#define HP_APM_AXI_BLOCK_EN_V  0x00000001U
+#define HP_APM_AXI_BLOCK_EN_S  0
+
+/** HP_APM_BUS_ERR_CONF_REG register
+ *  APM interrupt enable register
+ */
+#define HP_APM_BUS_ERR_CONF_REG (DR_REG_HP_APM_BASE + 0x154)
+/** HP_APM_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether return error response to cpu when access blocked
+ *  0: disable error response
+ *  1: enable error response
+ */
+#define HP_APM_BUS_ERR_RESP_EN    (BIT(0))
+#define HP_APM_BUS_ERR_RESP_EN_M  (HP_APM_BUS_ERR_RESP_EN_V << HP_APM_BUS_ERR_RESP_EN_S)
+#define HP_APM_BUS_ERR_RESP_EN_V  0x00000001U
+#define HP_APM_BUS_ERR_RESP_EN_S  0
+
+/** HP_APM_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x3f8)
+/** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: enable automatic clock gating
+ *  1: keep the clock always on
+ */
+#define HP_APM_CLK_EN    (BIT(0))
+#define HP_APM_CLK_EN_M  (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S)
+#define HP_APM_CLK_EN_V  0x00000001U
+#define HP_APM_CLK_EN_S  0
+
+/** HP_APM_DATE_REG register
+ *  Version control register
+ */
+#define HP_APM_DATE_REG (DR_REG_HP_APM_BASE + 0x3fc)
+/** HP_APM_DATE : R/W; bitpos: [27:0]; default: 38822496;
+ *  Version control register.
+ */
+#define HP_APM_DATE    0x0FFFFFFFU
+#define HP_APM_DATE_M  (HP_APM_DATE_V << HP_APM_DATE_S)
+#define HP_APM_DATE_V  0x0FFFFFFFU
+#define HP_APM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_apm_struct.h b/components/soc/esp32s31/register/soc/hp_apm_struct.h
new file mode 100644
index 00000000000..ed137de4fc4
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_apm_struct.h
@@ -0,0 +1,896 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [15:0]; default: 1;
+         *  Configure bit $n (0-15) to enable region $n.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t region_filter_en:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} hp_apm_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of regionn_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0;
+         *  Configures start address of region n.
+         */
+        uint32_t regionn_addr_start:32;
+    };
+    uint32_t val;
+} hp_apm_regionn_addr_start_reg_t;
+
+/** Type of regionn_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295;
+         *  Configures end address of region n.
+         */
+        uint32_t regionn_addr_end:32;
+    };
+    uint32_t val;
+} hp_apm_regionn_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of regionn_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** regionn_r0_x : R/W; bitpos: [0]; default: 0;
+         *  Configures the execution authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_x:1;
+        /** regionn_r0_w : R/W; bitpos: [1]; default: 0;
+         *  Configures the write authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_w:1;
+        /** regionn_r0_r : R/W; bitpos: [2]; default: 0;
+         *  Configures the read authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_r:1;
+        uint32_t reserved_3:1;
+        /** regionn_r1_x : R/W; bitpos: [4]; default: 0;
+         *  Configures the execution authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_x:1;
+        /** regionn_r1_w : R/W; bitpos: [5]; default: 0;
+         *  Configures the write authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_w:1;
+        /** regionn_r1_r : R/W; bitpos: [6]; default: 0;
+         *  Configures the read authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_r:1;
+        uint32_t reserved_7:1;
+        /** regionn_r2_x : R/W; bitpos: [8]; default: 0;
+         *  Configures the execution authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_x:1;
+        /** regionn_r2_w : R/W; bitpos: [9]; default: 0;
+         *  Configures the write authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_w:1;
+        /** regionn_r2_r : R/W; bitpos: [10]; default: 0;
+         *  Configures the read authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_r:1;
+        uint32_t reserved_11:1;
+        /** regionn_tee_x : R/W; bitpos: [12]; default: 1;
+         *  Configures the execution authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_x:1;
+        /** regionn_tee_w : R/W; bitpos: [13]; default: 1;
+         *  Configures the write authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_w:1;
+        /** regionn_tee_r : R/W; bitpos: [14]; default: 1;
+         *  Configures the read authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_r:1;
+        uint32_t reserved_15:1;
+        /** regionn_lock : R/W; bitpos: [16]; default: 0;
+         *  Set 1 to lock region0 configuration
+         */
+        uint32_t regionn_lock:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_apm_regionn_attr_reg_t;
+
+
+/** Group: function control register */
+/** Type of func_ctrl register
+ *  APM function control register
+ */
+typedef union {
+    struct {
+        /** m0_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_func_en:1;
+        /** m1_func_en : R/W; bitpos: [1]; default: 1;
+         *  PMS M1 function enable
+         */
+        uint32_t m1_func_en:1;
+        /** m2_func_en : R/W; bitpos: [2]; default: 1;
+         *  PMS M2 function enable
+         */
+        uint32_t m2_func_en:1;
+        /** m3_func_en : R/W; bitpos: [3]; default: 1;
+         *  PMS M3 function enable
+         */
+        uint32_t m3_func_en:1;
+        /** m4_func_en : R/W; bitpos: [4]; default: 1;
+         *  PMS M4 function enable
+         */
+        uint32_t m4_func_en:1;
+        /** m5_func_en : R/W; bitpos: [5]; default: 1;
+         *  PMS M5 function enable
+         */
+        uint32_t m5_func_en:1;
+        /** m6_func_en : R/W; bitpos: [6]; default: 1;
+         *  PMS M6 function enable
+         */
+        uint32_t m6_func_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_apm_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m0_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m0_exception_region:16;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m0_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_apm_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m0_exception_info1_reg_t;
+
+
+/** Group: M1 status register */
+/** Type of m1_status register
+ *  M1 status register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m1_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m1_status_reg_t;
+
+
+/** Group: M1 status clear register */
+/** Type of m1_status_clr register
+ *  M1 status clear register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m1_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m1_status_clr_reg_t;
+
+
+/** Group: M1 exception_info0 register */
+/** Type of m1_exception_info0 register
+ *  M1 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m1_exception_region:16;
+        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m1_exception_mode:2;
+        /** m1_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m1_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_apm_m1_exception_info0_reg_t;
+
+
+/** Group: M1 exception_info1 register */
+/** Type of m1_exception_info1 register
+ *  M1 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m1_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m1_exception_info1_reg_t;
+
+
+/** Group: M2 status register */
+/** Type of m2_status register
+ *  M2 status register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m2_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m2_status_reg_t;
+
+
+/** Group: M2 status clear register */
+/** Type of m2_status_clr register
+ *  M2 status clear register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m2_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m2_status_clr_reg_t;
+
+
+/** Group: M2 exception_info0 register */
+/** Type of m2_exception_info0 register
+ *  M2 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m2_exception_region:16;
+        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m2_exception_mode:2;
+        /** m2_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m2_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_apm_m2_exception_info0_reg_t;
+
+
+/** Group: M2 exception_info1 register */
+/** Type of m2_exception_info1 register
+ *  M2 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m2_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m2_exception_info1_reg_t;
+
+
+/** Group: M3 status register */
+/** Type of m3_status register
+ *  M3 status register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m3_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m3_status_reg_t;
+
+
+/** Group: M3 status clear register */
+/** Type of m3_status_clr register
+ *  M3 status clear register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m3_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m3_status_clr_reg_t;
+
+
+/** Group: M3 exception_info0 register */
+/** Type of m3_exception_info0 register
+ *  M3 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m3_exception_region:16;
+        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m3_exception_mode:2;
+        /** m3_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m3_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_apm_m3_exception_info0_reg_t;
+
+
+/** Group: M3 exception_info1 register */
+/** Type of m3_exception_info1 register
+ *  M3 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m3_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m3_exception_info1_reg_t;
+
+
+/** Group: M4 status register */
+/** Type of m4_status register
+ *  M4 status register
+ */
+typedef union {
+    struct {
+        /** m4_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m4_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m4_status_reg_t;
+
+
+/** Group: M4 status clear register */
+/** Type of m4_status_clr register
+ *  M4 status clear register
+ */
+typedef union {
+    struct {
+        /** m4_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m4_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m4_status_clr_reg_t;
+
+
+/** Group: M4 exception_info0 register */
+/** Type of m4_exception_info0 register
+ *  M4 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m4_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m4_exception_region:16;
+        /** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m4_exception_mode:2;
+        /** m4_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m4_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_apm_m4_exception_info0_reg_t;
+
+
+/** Group: M4 exception_info1 register */
+/** Type of m4_exception_info1 register
+ *  M4 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m4_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m4_exception_info1_reg_t;
+
+
+/** Group: M5 status register */
+/** Type of m5_status register
+ *  M5 status register
+ */
+typedef union {
+    struct {
+        /** m5_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m5_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m5_status_reg_t;
+
+
+/** Group: M5 status clear register */
+/** Type of m5_status_clr register
+ *  M5 status clear register
+ */
+typedef union {
+    struct {
+        /** m5_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m5_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m5_status_clr_reg_t;
+
+
+/** Group: M5 exception_info0 register */
+/** Type of m5_exception_info0 register
+ *  M5 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m5_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m5_exception_region:16;
+        /** m5_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m5_exception_mode:2;
+        /** m5_exception_id : RO; bitpos: [24:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m5_exception_id:7;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_apm_m5_exception_info0_reg_t;
+
+
+/** Group: M5 exception_info1 register */
+/** Type of m5_exception_info1 register
+ *  M5 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m5_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m5_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m5_exception_info1_reg_t;
+
+
+/** Group: M6 status register */
+/** Type of m6_status register
+ *  M6 status register
+ */
+typedef union {
+    struct {
+        /** m6_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m6_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_apm_m6_status_reg_t;
+
+
+/** Group: M6 status clear register */
+/** Type of m6_status_clr register
+ *  M6 status clear register
+ */
+typedef union {
+    struct {
+        /** m6_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m6_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_m6_status_clr_reg_t;
+
+
+/** Group: M6 exception_info0 register */
+/** Type of m6_exception_info0 register
+ *  M6 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m6_exception_region : RO; bitpos: [15:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m6_exception_region:16;
+        /** m6_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m6_exception_mode:2;
+        /** m6_exception_id : RO; bitpos: [24:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m6_exception_id:7;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_apm_m6_exception_info0_reg_t;
+
+
+/** Group: M6 exception_info1 register */
+/** Type of m6_exception_info1 register
+ *  M6 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m6_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m6_exception_addr:32;
+    };
+    uint32_t val;
+} hp_apm_m6_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  Configures to enable APM M0 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m0_apm_int_en:1;
+        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
+         *  Configures to enable APM M1 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m1_apm_int_en:1;
+        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
+         *  Configures to enable APM M2 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m2_apm_int_en:1;
+        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
+         *  Configures to enable APM M3 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m3_apm_int_en:1;
+        /** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
+         *  Configures to enable APM M4 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m4_apm_int_en:1;
+        /** m5_apm_int_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable APM M5 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m5_apm_int_en:1;
+        /** m6_apm_int_en : R/W; bitpos: [6]; default: 0;
+         *  Configures to enable APM M6 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m6_apm_int_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_apm_int_en_reg_t;
+
+/** Type of bus_err_conf register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether return error response to cpu when access blocked
+         *  0: disable error response
+         *  1: enable error response
+         */
+        uint32_t bus_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_bus_err_conf_reg_t;
+
+
+/** Group: APM transmission config register */
+/** Type of axi_block_en register
+ *  M6 status clear register
+ */
+typedef union {
+    struct {
+        /** axi_block_en : R/W; bitpos: [0]; default: 1;
+         *  Configures to if block transmission when get exceltion.
+         *  0: transparent transmission to slave
+         *  1: don't transparent transmission to slave
+         */
+        uint32_t axi_block_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_axi_block_en_reg_t;
+
+
+/** Group: Clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: enable automatic clock gating
+         *  1: keep the clock always on
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_apm_clock_gate_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38822496;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_apm_date_reg_t;
+
+
+typedef struct {
+    volatile hp_apm_region_filter_en_reg_t region_filter_en;
+    volatile hp_apm_regionn_addr_start_reg_t region0_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region0_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region0_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region1_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region1_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region1_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region2_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region2_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region2_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region3_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region3_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region3_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region4_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region4_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region4_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region5_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region5_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region5_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region6_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region6_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region6_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region7_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region7_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region7_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region8_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region8_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region8_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region9_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region9_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region9_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region10_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region10_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region10_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region11_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region11_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region11_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region12_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region12_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region12_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region13_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region13_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region13_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region14_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region14_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region14_attr;
+    volatile hp_apm_regionn_addr_start_reg_t region15_addr_start;
+    volatile hp_apm_regionn_addr_end_reg_t region15_addr_end;
+    volatile hp_apm_regionn_attr_reg_t region15_attr;
+    volatile hp_apm_func_ctrl_reg_t func_ctrl;
+    volatile hp_apm_m0_status_reg_t m0_status;
+    volatile hp_apm_m0_status_clr_reg_t m0_status_clr;
+    volatile hp_apm_m0_exception_info0_reg_t m0_exception_info0;
+    volatile hp_apm_m0_exception_info1_reg_t m0_exception_info1;
+    volatile hp_apm_m1_status_reg_t m1_status;
+    volatile hp_apm_m1_status_clr_reg_t m1_status_clr;
+    volatile hp_apm_m1_exception_info0_reg_t m1_exception_info0;
+    volatile hp_apm_m1_exception_info1_reg_t m1_exception_info1;
+    volatile hp_apm_m2_status_reg_t m2_status;
+    volatile hp_apm_m2_status_clr_reg_t m2_status_clr;
+    volatile hp_apm_m2_exception_info0_reg_t m2_exception_info0;
+    volatile hp_apm_m2_exception_info1_reg_t m2_exception_info1;
+    volatile hp_apm_m3_status_reg_t m3_status;
+    volatile hp_apm_m3_status_clr_reg_t m3_status_clr;
+    volatile hp_apm_m3_exception_info0_reg_t m3_exception_info0;
+    volatile hp_apm_m3_exception_info1_reg_t m3_exception_info1;
+    volatile hp_apm_m4_status_reg_t m4_status;
+    volatile hp_apm_m4_status_clr_reg_t m4_status_clr;
+    volatile hp_apm_m4_exception_info0_reg_t m4_exception_info0;
+    volatile hp_apm_m4_exception_info1_reg_t m4_exception_info1;
+    volatile hp_apm_m5_status_reg_t m5_status;
+    volatile hp_apm_m5_status_clr_reg_t m5_status_clr;
+    volatile hp_apm_m5_exception_info0_reg_t m5_exception_info0;
+    volatile hp_apm_m5_exception_info1_reg_t m5_exception_info1;
+    uint32_t reserved_128;
+    volatile hp_apm_m6_status_reg_t m6_status;
+    volatile hp_apm_m6_status_clr_reg_t m6_status_clr;
+    volatile hp_apm_m6_exception_info0_reg_t m6_exception_info0;
+    volatile hp_apm_m6_exception_info1_reg_t m6_exception_info1;
+    uint32_t reserved_13c[4];
+    volatile hp_apm_int_en_reg_t int_en;
+    volatile hp_apm_axi_block_en_reg_t axi_block_en;
+    volatile hp_apm_bus_err_conf_reg_t bus_err_conf;
+    uint32_t reserved_158[168];
+    volatile hp_apm_clock_gate_reg_t clock_gate;
+    volatile hp_apm_date_reg_t date;
+} hp_apm_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_apm_dev_t) == 0x400, "Invalid size of hp_apm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_mem_apm_reg.h b/components/soc/esp32s31/register/soc/hp_mem_apm_reg.h
new file mode 100644
index 00000000000..e0c4a8b6c77
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_mem_apm_reg.h
@@ -0,0 +1,1744 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_MEM_APM_REGION_FILTER_EN_REG register
+ *  Region filter enable register
+ */
+#define HP_MEM_APM_REGION_FILTER_EN_REG (DR_REG_HP_MEM_APM_BASE + 0x0)
+/** HP_MEM_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1;
+ *  Configure bit $n (0-7) to enable region $n.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_REGION_FILTER_EN    0x000000FFU
+#define HP_MEM_APM_REGION_FILTER_EN_M  (HP_MEM_APM_REGION_FILTER_EN_V << HP_MEM_APM_REGION_FILTER_EN_S)
+#define HP_MEM_APM_REGION_FILTER_EN_V  0x000000FFU
+#define HP_MEM_APM_REGION_FILTER_EN_S  0
+
+/** HP_MEM_APM_REGION0_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION0_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x4)
+/** HP_MEM_APM_REGION0_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION0_ADDR_START_L_M  (HP_MEM_APM_REGION0_ADDR_START_L_V << HP_MEM_APM_REGION0_ADDR_START_L_S)
+#define HP_MEM_APM_REGION0_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION0_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION0_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION0_ADDR_START_M  (HP_MEM_APM_REGION0_ADDR_START_V << HP_MEM_APM_REGION0_ADDR_START_S)
+#define HP_MEM_APM_REGION0_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION0_ADDR_START_S  7
+/** HP_MEM_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION0_ADDR_START_H_M  (HP_MEM_APM_REGION0_ADDR_START_H_V << HP_MEM_APM_REGION0_ADDR_START_H_S)
+#define HP_MEM_APM_REGION0_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION0_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION0_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION0_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x8)
+/** HP_MEM_APM_REGION0_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION0_ADDR_END_L_M  (HP_MEM_APM_REGION0_ADDR_END_L_V << HP_MEM_APM_REGION0_ADDR_END_L_S)
+#define HP_MEM_APM_REGION0_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION0_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION0_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION0_ADDR_END_M  (HP_MEM_APM_REGION0_ADDR_END_V << HP_MEM_APM_REGION0_ADDR_END_S)
+#define HP_MEM_APM_REGION0_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION0_ADDR_END_S  7
+/** HP_MEM_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 0.
+ */
+#define HP_MEM_APM_REGION0_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION0_ADDR_END_H_M  (HP_MEM_APM_REGION0_ADDR_END_H_V << HP_MEM_APM_REGION0_ADDR_END_H_S)
+#define HP_MEM_APM_REGION0_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION0_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION0_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION0_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0xc)
+/** HP_MEM_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION0_R0_X_M  (HP_MEM_APM_REGION0_R0_X_V << HP_MEM_APM_REGION0_R0_X_S)
+#define HP_MEM_APM_REGION0_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION0_R0_X_S  0
+/** HP_MEM_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION0_R0_W_M  (HP_MEM_APM_REGION0_R0_W_V << HP_MEM_APM_REGION0_R0_W_S)
+#define HP_MEM_APM_REGION0_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION0_R0_W_S  1
+/** HP_MEM_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION0_R0_R_M  (HP_MEM_APM_REGION0_R0_R_V << HP_MEM_APM_REGION0_R0_R_S)
+#define HP_MEM_APM_REGION0_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION0_R0_R_S  2
+/** HP_MEM_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION0_R1_X_M  (HP_MEM_APM_REGION0_R1_X_V << HP_MEM_APM_REGION0_R1_X_S)
+#define HP_MEM_APM_REGION0_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION0_R1_X_S  4
+/** HP_MEM_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION0_R1_W_M  (HP_MEM_APM_REGION0_R1_W_V << HP_MEM_APM_REGION0_R1_W_S)
+#define HP_MEM_APM_REGION0_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION0_R1_W_S  5
+/** HP_MEM_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION0_R1_R_M  (HP_MEM_APM_REGION0_R1_R_V << HP_MEM_APM_REGION0_R1_R_S)
+#define HP_MEM_APM_REGION0_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION0_R1_R_S  6
+/** HP_MEM_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION0_R2_X_M  (HP_MEM_APM_REGION0_R2_X_V << HP_MEM_APM_REGION0_R2_X_S)
+#define HP_MEM_APM_REGION0_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION0_R2_X_S  8
+/** HP_MEM_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION0_R2_W_M  (HP_MEM_APM_REGION0_R2_W_V << HP_MEM_APM_REGION0_R2_W_S)
+#define HP_MEM_APM_REGION0_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION0_R2_W_S  9
+/** HP_MEM_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 0.
+ */
+#define HP_MEM_APM_REGION0_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION0_R2_R_M  (HP_MEM_APM_REGION0_R2_R_V << HP_MEM_APM_REGION0_R2_R_S)
+#define HP_MEM_APM_REGION0_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION0_R2_R_S  10
+/** HP_MEM_APM_REGION0_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 0.
+ */
+#define HP_MEM_APM_REGION0_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION0_TEE_X_M  (HP_MEM_APM_REGION0_TEE_X_V << HP_MEM_APM_REGION0_TEE_X_S)
+#define HP_MEM_APM_REGION0_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION0_TEE_X_S  12
+/** HP_MEM_APM_REGION0_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 0.
+ */
+#define HP_MEM_APM_REGION0_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION0_TEE_W_M  (HP_MEM_APM_REGION0_TEE_W_V << HP_MEM_APM_REGION0_TEE_W_S)
+#define HP_MEM_APM_REGION0_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION0_TEE_W_S  13
+/** HP_MEM_APM_REGION0_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 0.
+ */
+#define HP_MEM_APM_REGION0_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION0_TEE_R_M  (HP_MEM_APM_REGION0_TEE_R_V << HP_MEM_APM_REGION0_TEE_R_S)
+#define HP_MEM_APM_REGION0_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION0_TEE_R_S  14
+/** HP_MEM_APM_REGION0_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION0_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION0_LOCK_M  (HP_MEM_APM_REGION0_LOCK_V << HP_MEM_APM_REGION0_LOCK_S)
+#define HP_MEM_APM_REGION0_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION0_LOCK_S  16
+
+/** HP_MEM_APM_REGION1_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION1_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x10)
+/** HP_MEM_APM_REGION1_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION1_ADDR_START_L_M  (HP_MEM_APM_REGION1_ADDR_START_L_V << HP_MEM_APM_REGION1_ADDR_START_L_S)
+#define HP_MEM_APM_REGION1_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION1_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION1_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION1_ADDR_START_M  (HP_MEM_APM_REGION1_ADDR_START_V << HP_MEM_APM_REGION1_ADDR_START_S)
+#define HP_MEM_APM_REGION1_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION1_ADDR_START_S  7
+/** HP_MEM_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION1_ADDR_START_H_M  (HP_MEM_APM_REGION1_ADDR_START_H_V << HP_MEM_APM_REGION1_ADDR_START_H_S)
+#define HP_MEM_APM_REGION1_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION1_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION1_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION1_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x14)
+/** HP_MEM_APM_REGION1_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION1_ADDR_END_L_M  (HP_MEM_APM_REGION1_ADDR_END_L_V << HP_MEM_APM_REGION1_ADDR_END_L_S)
+#define HP_MEM_APM_REGION1_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION1_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION1_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION1_ADDR_END_M  (HP_MEM_APM_REGION1_ADDR_END_V << HP_MEM_APM_REGION1_ADDR_END_S)
+#define HP_MEM_APM_REGION1_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION1_ADDR_END_S  7
+/** HP_MEM_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 1.
+ */
+#define HP_MEM_APM_REGION1_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION1_ADDR_END_H_M  (HP_MEM_APM_REGION1_ADDR_END_H_V << HP_MEM_APM_REGION1_ADDR_END_H_S)
+#define HP_MEM_APM_REGION1_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION1_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION1_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION1_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x18)
+/** HP_MEM_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION1_R0_X_M  (HP_MEM_APM_REGION1_R0_X_V << HP_MEM_APM_REGION1_R0_X_S)
+#define HP_MEM_APM_REGION1_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION1_R0_X_S  0
+/** HP_MEM_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION1_R0_W_M  (HP_MEM_APM_REGION1_R0_W_V << HP_MEM_APM_REGION1_R0_W_S)
+#define HP_MEM_APM_REGION1_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION1_R0_W_S  1
+/** HP_MEM_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION1_R0_R_M  (HP_MEM_APM_REGION1_R0_R_V << HP_MEM_APM_REGION1_R0_R_S)
+#define HP_MEM_APM_REGION1_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION1_R0_R_S  2
+/** HP_MEM_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION1_R1_X_M  (HP_MEM_APM_REGION1_R1_X_V << HP_MEM_APM_REGION1_R1_X_S)
+#define HP_MEM_APM_REGION1_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION1_R1_X_S  4
+/** HP_MEM_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION1_R1_W_M  (HP_MEM_APM_REGION1_R1_W_V << HP_MEM_APM_REGION1_R1_W_S)
+#define HP_MEM_APM_REGION1_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION1_R1_W_S  5
+/** HP_MEM_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION1_R1_R_M  (HP_MEM_APM_REGION1_R1_R_V << HP_MEM_APM_REGION1_R1_R_S)
+#define HP_MEM_APM_REGION1_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION1_R1_R_S  6
+/** HP_MEM_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION1_R2_X_M  (HP_MEM_APM_REGION1_R2_X_V << HP_MEM_APM_REGION1_R2_X_S)
+#define HP_MEM_APM_REGION1_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION1_R2_X_S  8
+/** HP_MEM_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION1_R2_W_M  (HP_MEM_APM_REGION1_R2_W_V << HP_MEM_APM_REGION1_R2_W_S)
+#define HP_MEM_APM_REGION1_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION1_R2_W_S  9
+/** HP_MEM_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 1.
+ */
+#define HP_MEM_APM_REGION1_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION1_R2_R_M  (HP_MEM_APM_REGION1_R2_R_V << HP_MEM_APM_REGION1_R2_R_S)
+#define HP_MEM_APM_REGION1_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION1_R2_R_S  10
+/** HP_MEM_APM_REGION1_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 1.
+ */
+#define HP_MEM_APM_REGION1_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION1_TEE_X_M  (HP_MEM_APM_REGION1_TEE_X_V << HP_MEM_APM_REGION1_TEE_X_S)
+#define HP_MEM_APM_REGION1_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION1_TEE_X_S  12
+/** HP_MEM_APM_REGION1_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 1.
+ */
+#define HP_MEM_APM_REGION1_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION1_TEE_W_M  (HP_MEM_APM_REGION1_TEE_W_V << HP_MEM_APM_REGION1_TEE_W_S)
+#define HP_MEM_APM_REGION1_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION1_TEE_W_S  13
+/** HP_MEM_APM_REGION1_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 1.
+ */
+#define HP_MEM_APM_REGION1_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION1_TEE_R_M  (HP_MEM_APM_REGION1_TEE_R_V << HP_MEM_APM_REGION1_TEE_R_S)
+#define HP_MEM_APM_REGION1_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION1_TEE_R_S  14
+/** HP_MEM_APM_REGION1_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION1_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION1_LOCK_M  (HP_MEM_APM_REGION1_LOCK_V << HP_MEM_APM_REGION1_LOCK_S)
+#define HP_MEM_APM_REGION1_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION1_LOCK_S  16
+
+/** HP_MEM_APM_REGION2_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION2_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x1c)
+/** HP_MEM_APM_REGION2_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION2_ADDR_START_L_M  (HP_MEM_APM_REGION2_ADDR_START_L_V << HP_MEM_APM_REGION2_ADDR_START_L_S)
+#define HP_MEM_APM_REGION2_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION2_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION2_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION2_ADDR_START_M  (HP_MEM_APM_REGION2_ADDR_START_V << HP_MEM_APM_REGION2_ADDR_START_S)
+#define HP_MEM_APM_REGION2_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION2_ADDR_START_S  7
+/** HP_MEM_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION2_ADDR_START_H_M  (HP_MEM_APM_REGION2_ADDR_START_H_V << HP_MEM_APM_REGION2_ADDR_START_H_S)
+#define HP_MEM_APM_REGION2_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION2_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION2_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION2_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x20)
+/** HP_MEM_APM_REGION2_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION2_ADDR_END_L_M  (HP_MEM_APM_REGION2_ADDR_END_L_V << HP_MEM_APM_REGION2_ADDR_END_L_S)
+#define HP_MEM_APM_REGION2_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION2_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION2_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION2_ADDR_END_M  (HP_MEM_APM_REGION2_ADDR_END_V << HP_MEM_APM_REGION2_ADDR_END_S)
+#define HP_MEM_APM_REGION2_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION2_ADDR_END_S  7
+/** HP_MEM_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 2.
+ */
+#define HP_MEM_APM_REGION2_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION2_ADDR_END_H_M  (HP_MEM_APM_REGION2_ADDR_END_H_V << HP_MEM_APM_REGION2_ADDR_END_H_S)
+#define HP_MEM_APM_REGION2_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION2_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION2_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION2_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x24)
+/** HP_MEM_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION2_R0_X_M  (HP_MEM_APM_REGION2_R0_X_V << HP_MEM_APM_REGION2_R0_X_S)
+#define HP_MEM_APM_REGION2_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION2_R0_X_S  0
+/** HP_MEM_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION2_R0_W_M  (HP_MEM_APM_REGION2_R0_W_V << HP_MEM_APM_REGION2_R0_W_S)
+#define HP_MEM_APM_REGION2_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION2_R0_W_S  1
+/** HP_MEM_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION2_R0_R_M  (HP_MEM_APM_REGION2_R0_R_V << HP_MEM_APM_REGION2_R0_R_S)
+#define HP_MEM_APM_REGION2_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION2_R0_R_S  2
+/** HP_MEM_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION2_R1_X_M  (HP_MEM_APM_REGION2_R1_X_V << HP_MEM_APM_REGION2_R1_X_S)
+#define HP_MEM_APM_REGION2_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION2_R1_X_S  4
+/** HP_MEM_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION2_R1_W_M  (HP_MEM_APM_REGION2_R1_W_V << HP_MEM_APM_REGION2_R1_W_S)
+#define HP_MEM_APM_REGION2_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION2_R1_W_S  5
+/** HP_MEM_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION2_R1_R_M  (HP_MEM_APM_REGION2_R1_R_V << HP_MEM_APM_REGION2_R1_R_S)
+#define HP_MEM_APM_REGION2_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION2_R1_R_S  6
+/** HP_MEM_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION2_R2_X_M  (HP_MEM_APM_REGION2_R2_X_V << HP_MEM_APM_REGION2_R2_X_S)
+#define HP_MEM_APM_REGION2_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION2_R2_X_S  8
+/** HP_MEM_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION2_R2_W_M  (HP_MEM_APM_REGION2_R2_W_V << HP_MEM_APM_REGION2_R2_W_S)
+#define HP_MEM_APM_REGION2_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION2_R2_W_S  9
+/** HP_MEM_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 2.
+ */
+#define HP_MEM_APM_REGION2_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION2_R2_R_M  (HP_MEM_APM_REGION2_R2_R_V << HP_MEM_APM_REGION2_R2_R_S)
+#define HP_MEM_APM_REGION2_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION2_R2_R_S  10
+/** HP_MEM_APM_REGION2_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 2.
+ */
+#define HP_MEM_APM_REGION2_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION2_TEE_X_M  (HP_MEM_APM_REGION2_TEE_X_V << HP_MEM_APM_REGION2_TEE_X_S)
+#define HP_MEM_APM_REGION2_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION2_TEE_X_S  12
+/** HP_MEM_APM_REGION2_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 2.
+ */
+#define HP_MEM_APM_REGION2_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION2_TEE_W_M  (HP_MEM_APM_REGION2_TEE_W_V << HP_MEM_APM_REGION2_TEE_W_S)
+#define HP_MEM_APM_REGION2_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION2_TEE_W_S  13
+/** HP_MEM_APM_REGION2_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 2.
+ */
+#define HP_MEM_APM_REGION2_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION2_TEE_R_M  (HP_MEM_APM_REGION2_TEE_R_V << HP_MEM_APM_REGION2_TEE_R_S)
+#define HP_MEM_APM_REGION2_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION2_TEE_R_S  14
+/** HP_MEM_APM_REGION2_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION2_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION2_LOCK_M  (HP_MEM_APM_REGION2_LOCK_V << HP_MEM_APM_REGION2_LOCK_S)
+#define HP_MEM_APM_REGION2_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION2_LOCK_S  16
+
+/** HP_MEM_APM_REGION3_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION3_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x28)
+/** HP_MEM_APM_REGION3_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION3_ADDR_START_L_M  (HP_MEM_APM_REGION3_ADDR_START_L_V << HP_MEM_APM_REGION3_ADDR_START_L_S)
+#define HP_MEM_APM_REGION3_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION3_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION3_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION3_ADDR_START_M  (HP_MEM_APM_REGION3_ADDR_START_V << HP_MEM_APM_REGION3_ADDR_START_S)
+#define HP_MEM_APM_REGION3_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION3_ADDR_START_S  7
+/** HP_MEM_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION3_ADDR_START_H_M  (HP_MEM_APM_REGION3_ADDR_START_H_V << HP_MEM_APM_REGION3_ADDR_START_H_S)
+#define HP_MEM_APM_REGION3_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION3_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION3_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION3_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x2c)
+/** HP_MEM_APM_REGION3_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION3_ADDR_END_L_M  (HP_MEM_APM_REGION3_ADDR_END_L_V << HP_MEM_APM_REGION3_ADDR_END_L_S)
+#define HP_MEM_APM_REGION3_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION3_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION3_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION3_ADDR_END_M  (HP_MEM_APM_REGION3_ADDR_END_V << HP_MEM_APM_REGION3_ADDR_END_S)
+#define HP_MEM_APM_REGION3_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION3_ADDR_END_S  7
+/** HP_MEM_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 3.
+ */
+#define HP_MEM_APM_REGION3_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION3_ADDR_END_H_M  (HP_MEM_APM_REGION3_ADDR_END_H_V << HP_MEM_APM_REGION3_ADDR_END_H_S)
+#define HP_MEM_APM_REGION3_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION3_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION3_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION3_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x30)
+/** HP_MEM_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION3_R0_X_M  (HP_MEM_APM_REGION3_R0_X_V << HP_MEM_APM_REGION3_R0_X_S)
+#define HP_MEM_APM_REGION3_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION3_R0_X_S  0
+/** HP_MEM_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION3_R0_W_M  (HP_MEM_APM_REGION3_R0_W_V << HP_MEM_APM_REGION3_R0_W_S)
+#define HP_MEM_APM_REGION3_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION3_R0_W_S  1
+/** HP_MEM_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION3_R0_R_M  (HP_MEM_APM_REGION3_R0_R_V << HP_MEM_APM_REGION3_R0_R_S)
+#define HP_MEM_APM_REGION3_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION3_R0_R_S  2
+/** HP_MEM_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION3_R1_X_M  (HP_MEM_APM_REGION3_R1_X_V << HP_MEM_APM_REGION3_R1_X_S)
+#define HP_MEM_APM_REGION3_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION3_R1_X_S  4
+/** HP_MEM_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION3_R1_W_M  (HP_MEM_APM_REGION3_R1_W_V << HP_MEM_APM_REGION3_R1_W_S)
+#define HP_MEM_APM_REGION3_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION3_R1_W_S  5
+/** HP_MEM_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION3_R1_R_M  (HP_MEM_APM_REGION3_R1_R_V << HP_MEM_APM_REGION3_R1_R_S)
+#define HP_MEM_APM_REGION3_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION3_R1_R_S  6
+/** HP_MEM_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION3_R2_X_M  (HP_MEM_APM_REGION3_R2_X_V << HP_MEM_APM_REGION3_R2_X_S)
+#define HP_MEM_APM_REGION3_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION3_R2_X_S  8
+/** HP_MEM_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION3_R2_W_M  (HP_MEM_APM_REGION3_R2_W_V << HP_MEM_APM_REGION3_R2_W_S)
+#define HP_MEM_APM_REGION3_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION3_R2_W_S  9
+/** HP_MEM_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 3.
+ */
+#define HP_MEM_APM_REGION3_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION3_R2_R_M  (HP_MEM_APM_REGION3_R2_R_V << HP_MEM_APM_REGION3_R2_R_S)
+#define HP_MEM_APM_REGION3_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION3_R2_R_S  10
+/** HP_MEM_APM_REGION3_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 3.
+ */
+#define HP_MEM_APM_REGION3_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION3_TEE_X_M  (HP_MEM_APM_REGION3_TEE_X_V << HP_MEM_APM_REGION3_TEE_X_S)
+#define HP_MEM_APM_REGION3_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION3_TEE_X_S  12
+/** HP_MEM_APM_REGION3_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 3.
+ */
+#define HP_MEM_APM_REGION3_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION3_TEE_W_M  (HP_MEM_APM_REGION3_TEE_W_V << HP_MEM_APM_REGION3_TEE_W_S)
+#define HP_MEM_APM_REGION3_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION3_TEE_W_S  13
+/** HP_MEM_APM_REGION3_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 3.
+ */
+#define HP_MEM_APM_REGION3_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION3_TEE_R_M  (HP_MEM_APM_REGION3_TEE_R_V << HP_MEM_APM_REGION3_TEE_R_S)
+#define HP_MEM_APM_REGION3_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION3_TEE_R_S  14
+/** HP_MEM_APM_REGION3_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION3_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION3_LOCK_M  (HP_MEM_APM_REGION3_LOCK_V << HP_MEM_APM_REGION3_LOCK_S)
+#define HP_MEM_APM_REGION3_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION3_LOCK_S  16
+
+/** HP_MEM_APM_REGION4_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION4_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x34)
+/** HP_MEM_APM_REGION4_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION4_ADDR_START_L_M  (HP_MEM_APM_REGION4_ADDR_START_L_V << HP_MEM_APM_REGION4_ADDR_START_L_S)
+#define HP_MEM_APM_REGION4_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION4_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION4_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION4_ADDR_START_M  (HP_MEM_APM_REGION4_ADDR_START_V << HP_MEM_APM_REGION4_ADDR_START_S)
+#define HP_MEM_APM_REGION4_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION4_ADDR_START_S  7
+/** HP_MEM_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION4_ADDR_START_H_M  (HP_MEM_APM_REGION4_ADDR_START_H_V << HP_MEM_APM_REGION4_ADDR_START_H_S)
+#define HP_MEM_APM_REGION4_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION4_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION4_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION4_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x38)
+/** HP_MEM_APM_REGION4_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION4_ADDR_END_L_M  (HP_MEM_APM_REGION4_ADDR_END_L_V << HP_MEM_APM_REGION4_ADDR_END_L_S)
+#define HP_MEM_APM_REGION4_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION4_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION4_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION4_ADDR_END_M  (HP_MEM_APM_REGION4_ADDR_END_V << HP_MEM_APM_REGION4_ADDR_END_S)
+#define HP_MEM_APM_REGION4_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION4_ADDR_END_S  7
+/** HP_MEM_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 4.
+ */
+#define HP_MEM_APM_REGION4_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION4_ADDR_END_H_M  (HP_MEM_APM_REGION4_ADDR_END_H_V << HP_MEM_APM_REGION4_ADDR_END_H_S)
+#define HP_MEM_APM_REGION4_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION4_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION4_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION4_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x3c)
+/** HP_MEM_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION4_R0_X_M  (HP_MEM_APM_REGION4_R0_X_V << HP_MEM_APM_REGION4_R0_X_S)
+#define HP_MEM_APM_REGION4_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION4_R0_X_S  0
+/** HP_MEM_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION4_R0_W_M  (HP_MEM_APM_REGION4_R0_W_V << HP_MEM_APM_REGION4_R0_W_S)
+#define HP_MEM_APM_REGION4_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION4_R0_W_S  1
+/** HP_MEM_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION4_R0_R_M  (HP_MEM_APM_REGION4_R0_R_V << HP_MEM_APM_REGION4_R0_R_S)
+#define HP_MEM_APM_REGION4_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION4_R0_R_S  2
+/** HP_MEM_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION4_R1_X_M  (HP_MEM_APM_REGION4_R1_X_V << HP_MEM_APM_REGION4_R1_X_S)
+#define HP_MEM_APM_REGION4_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION4_R1_X_S  4
+/** HP_MEM_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION4_R1_W_M  (HP_MEM_APM_REGION4_R1_W_V << HP_MEM_APM_REGION4_R1_W_S)
+#define HP_MEM_APM_REGION4_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION4_R1_W_S  5
+/** HP_MEM_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION4_R1_R_M  (HP_MEM_APM_REGION4_R1_R_V << HP_MEM_APM_REGION4_R1_R_S)
+#define HP_MEM_APM_REGION4_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION4_R1_R_S  6
+/** HP_MEM_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION4_R2_X_M  (HP_MEM_APM_REGION4_R2_X_V << HP_MEM_APM_REGION4_R2_X_S)
+#define HP_MEM_APM_REGION4_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION4_R2_X_S  8
+/** HP_MEM_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION4_R2_W_M  (HP_MEM_APM_REGION4_R2_W_V << HP_MEM_APM_REGION4_R2_W_S)
+#define HP_MEM_APM_REGION4_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION4_R2_W_S  9
+/** HP_MEM_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 4.
+ */
+#define HP_MEM_APM_REGION4_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION4_R2_R_M  (HP_MEM_APM_REGION4_R2_R_V << HP_MEM_APM_REGION4_R2_R_S)
+#define HP_MEM_APM_REGION4_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION4_R2_R_S  10
+/** HP_MEM_APM_REGION4_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 4.
+ */
+#define HP_MEM_APM_REGION4_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION4_TEE_X_M  (HP_MEM_APM_REGION4_TEE_X_V << HP_MEM_APM_REGION4_TEE_X_S)
+#define HP_MEM_APM_REGION4_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION4_TEE_X_S  12
+/** HP_MEM_APM_REGION4_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 4.
+ */
+#define HP_MEM_APM_REGION4_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION4_TEE_W_M  (HP_MEM_APM_REGION4_TEE_W_V << HP_MEM_APM_REGION4_TEE_W_S)
+#define HP_MEM_APM_REGION4_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION4_TEE_W_S  13
+/** HP_MEM_APM_REGION4_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 4.
+ */
+#define HP_MEM_APM_REGION4_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION4_TEE_R_M  (HP_MEM_APM_REGION4_TEE_R_V << HP_MEM_APM_REGION4_TEE_R_S)
+#define HP_MEM_APM_REGION4_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION4_TEE_R_S  14
+/** HP_MEM_APM_REGION4_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION4_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION4_LOCK_M  (HP_MEM_APM_REGION4_LOCK_V << HP_MEM_APM_REGION4_LOCK_S)
+#define HP_MEM_APM_REGION4_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION4_LOCK_S  16
+
+/** HP_MEM_APM_REGION5_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION5_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x40)
+/** HP_MEM_APM_REGION5_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION5_ADDR_START_L_M  (HP_MEM_APM_REGION5_ADDR_START_L_V << HP_MEM_APM_REGION5_ADDR_START_L_S)
+#define HP_MEM_APM_REGION5_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION5_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION5_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION5_ADDR_START_M  (HP_MEM_APM_REGION5_ADDR_START_V << HP_MEM_APM_REGION5_ADDR_START_S)
+#define HP_MEM_APM_REGION5_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION5_ADDR_START_S  7
+/** HP_MEM_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION5_ADDR_START_H_M  (HP_MEM_APM_REGION5_ADDR_START_H_V << HP_MEM_APM_REGION5_ADDR_START_H_S)
+#define HP_MEM_APM_REGION5_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION5_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION5_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION5_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x44)
+/** HP_MEM_APM_REGION5_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION5_ADDR_END_L_M  (HP_MEM_APM_REGION5_ADDR_END_L_V << HP_MEM_APM_REGION5_ADDR_END_L_S)
+#define HP_MEM_APM_REGION5_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION5_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION5_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION5_ADDR_END_M  (HP_MEM_APM_REGION5_ADDR_END_V << HP_MEM_APM_REGION5_ADDR_END_S)
+#define HP_MEM_APM_REGION5_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION5_ADDR_END_S  7
+/** HP_MEM_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 5.
+ */
+#define HP_MEM_APM_REGION5_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION5_ADDR_END_H_M  (HP_MEM_APM_REGION5_ADDR_END_H_V << HP_MEM_APM_REGION5_ADDR_END_H_S)
+#define HP_MEM_APM_REGION5_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION5_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION5_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION5_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x48)
+/** HP_MEM_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION5_R0_X_M  (HP_MEM_APM_REGION5_R0_X_V << HP_MEM_APM_REGION5_R0_X_S)
+#define HP_MEM_APM_REGION5_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION5_R0_X_S  0
+/** HP_MEM_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION5_R0_W_M  (HP_MEM_APM_REGION5_R0_W_V << HP_MEM_APM_REGION5_R0_W_S)
+#define HP_MEM_APM_REGION5_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION5_R0_W_S  1
+/** HP_MEM_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION5_R0_R_M  (HP_MEM_APM_REGION5_R0_R_V << HP_MEM_APM_REGION5_R0_R_S)
+#define HP_MEM_APM_REGION5_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION5_R0_R_S  2
+/** HP_MEM_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION5_R1_X_M  (HP_MEM_APM_REGION5_R1_X_V << HP_MEM_APM_REGION5_R1_X_S)
+#define HP_MEM_APM_REGION5_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION5_R1_X_S  4
+/** HP_MEM_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION5_R1_W_M  (HP_MEM_APM_REGION5_R1_W_V << HP_MEM_APM_REGION5_R1_W_S)
+#define HP_MEM_APM_REGION5_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION5_R1_W_S  5
+/** HP_MEM_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION5_R1_R_M  (HP_MEM_APM_REGION5_R1_R_V << HP_MEM_APM_REGION5_R1_R_S)
+#define HP_MEM_APM_REGION5_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION5_R1_R_S  6
+/** HP_MEM_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION5_R2_X_M  (HP_MEM_APM_REGION5_R2_X_V << HP_MEM_APM_REGION5_R2_X_S)
+#define HP_MEM_APM_REGION5_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION5_R2_X_S  8
+/** HP_MEM_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION5_R2_W_M  (HP_MEM_APM_REGION5_R2_W_V << HP_MEM_APM_REGION5_R2_W_S)
+#define HP_MEM_APM_REGION5_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION5_R2_W_S  9
+/** HP_MEM_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 5.
+ */
+#define HP_MEM_APM_REGION5_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION5_R2_R_M  (HP_MEM_APM_REGION5_R2_R_V << HP_MEM_APM_REGION5_R2_R_S)
+#define HP_MEM_APM_REGION5_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION5_R2_R_S  10
+/** HP_MEM_APM_REGION5_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 5.
+ */
+#define HP_MEM_APM_REGION5_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION5_TEE_X_M  (HP_MEM_APM_REGION5_TEE_X_V << HP_MEM_APM_REGION5_TEE_X_S)
+#define HP_MEM_APM_REGION5_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION5_TEE_X_S  12
+/** HP_MEM_APM_REGION5_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 5.
+ */
+#define HP_MEM_APM_REGION5_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION5_TEE_W_M  (HP_MEM_APM_REGION5_TEE_W_V << HP_MEM_APM_REGION5_TEE_W_S)
+#define HP_MEM_APM_REGION5_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION5_TEE_W_S  13
+/** HP_MEM_APM_REGION5_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 5.
+ */
+#define HP_MEM_APM_REGION5_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION5_TEE_R_M  (HP_MEM_APM_REGION5_TEE_R_V << HP_MEM_APM_REGION5_TEE_R_S)
+#define HP_MEM_APM_REGION5_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION5_TEE_R_S  14
+/** HP_MEM_APM_REGION5_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION5_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION5_LOCK_M  (HP_MEM_APM_REGION5_LOCK_V << HP_MEM_APM_REGION5_LOCK_S)
+#define HP_MEM_APM_REGION5_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION5_LOCK_S  16
+
+/** HP_MEM_APM_REGION6_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION6_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x4c)
+/** HP_MEM_APM_REGION6_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION6_ADDR_START_L_M  (HP_MEM_APM_REGION6_ADDR_START_L_V << HP_MEM_APM_REGION6_ADDR_START_L_S)
+#define HP_MEM_APM_REGION6_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION6_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION6_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION6_ADDR_START_M  (HP_MEM_APM_REGION6_ADDR_START_V << HP_MEM_APM_REGION6_ADDR_START_S)
+#define HP_MEM_APM_REGION6_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION6_ADDR_START_S  7
+/** HP_MEM_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION6_ADDR_START_H_M  (HP_MEM_APM_REGION6_ADDR_START_H_V << HP_MEM_APM_REGION6_ADDR_START_H_S)
+#define HP_MEM_APM_REGION6_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION6_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION6_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION6_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x50)
+/** HP_MEM_APM_REGION6_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION6_ADDR_END_L_M  (HP_MEM_APM_REGION6_ADDR_END_L_V << HP_MEM_APM_REGION6_ADDR_END_L_S)
+#define HP_MEM_APM_REGION6_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION6_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION6_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION6_ADDR_END_M  (HP_MEM_APM_REGION6_ADDR_END_V << HP_MEM_APM_REGION6_ADDR_END_S)
+#define HP_MEM_APM_REGION6_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION6_ADDR_END_S  7
+/** HP_MEM_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 6.
+ */
+#define HP_MEM_APM_REGION6_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION6_ADDR_END_H_M  (HP_MEM_APM_REGION6_ADDR_END_H_V << HP_MEM_APM_REGION6_ADDR_END_H_S)
+#define HP_MEM_APM_REGION6_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION6_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION6_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION6_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x54)
+/** HP_MEM_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION6_R0_X_M  (HP_MEM_APM_REGION6_R0_X_V << HP_MEM_APM_REGION6_R0_X_S)
+#define HP_MEM_APM_REGION6_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION6_R0_X_S  0
+/** HP_MEM_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION6_R0_W_M  (HP_MEM_APM_REGION6_R0_W_V << HP_MEM_APM_REGION6_R0_W_S)
+#define HP_MEM_APM_REGION6_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION6_R0_W_S  1
+/** HP_MEM_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION6_R0_R_M  (HP_MEM_APM_REGION6_R0_R_V << HP_MEM_APM_REGION6_R0_R_S)
+#define HP_MEM_APM_REGION6_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION6_R0_R_S  2
+/** HP_MEM_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION6_R1_X_M  (HP_MEM_APM_REGION6_R1_X_V << HP_MEM_APM_REGION6_R1_X_S)
+#define HP_MEM_APM_REGION6_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION6_R1_X_S  4
+/** HP_MEM_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION6_R1_W_M  (HP_MEM_APM_REGION6_R1_W_V << HP_MEM_APM_REGION6_R1_W_S)
+#define HP_MEM_APM_REGION6_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION6_R1_W_S  5
+/** HP_MEM_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION6_R1_R_M  (HP_MEM_APM_REGION6_R1_R_V << HP_MEM_APM_REGION6_R1_R_S)
+#define HP_MEM_APM_REGION6_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION6_R1_R_S  6
+/** HP_MEM_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION6_R2_X_M  (HP_MEM_APM_REGION6_R2_X_V << HP_MEM_APM_REGION6_R2_X_S)
+#define HP_MEM_APM_REGION6_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION6_R2_X_S  8
+/** HP_MEM_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION6_R2_W_M  (HP_MEM_APM_REGION6_R2_W_V << HP_MEM_APM_REGION6_R2_W_S)
+#define HP_MEM_APM_REGION6_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION6_R2_W_S  9
+/** HP_MEM_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 6.
+ */
+#define HP_MEM_APM_REGION6_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION6_R2_R_M  (HP_MEM_APM_REGION6_R2_R_V << HP_MEM_APM_REGION6_R2_R_S)
+#define HP_MEM_APM_REGION6_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION6_R2_R_S  10
+/** HP_MEM_APM_REGION6_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 6.
+ */
+#define HP_MEM_APM_REGION6_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION6_TEE_X_M  (HP_MEM_APM_REGION6_TEE_X_V << HP_MEM_APM_REGION6_TEE_X_S)
+#define HP_MEM_APM_REGION6_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION6_TEE_X_S  12
+/** HP_MEM_APM_REGION6_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 6.
+ */
+#define HP_MEM_APM_REGION6_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION6_TEE_W_M  (HP_MEM_APM_REGION6_TEE_W_V << HP_MEM_APM_REGION6_TEE_W_S)
+#define HP_MEM_APM_REGION6_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION6_TEE_W_S  13
+/** HP_MEM_APM_REGION6_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 6.
+ */
+#define HP_MEM_APM_REGION6_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION6_TEE_R_M  (HP_MEM_APM_REGION6_TEE_R_V << HP_MEM_APM_REGION6_TEE_R_S)
+#define HP_MEM_APM_REGION6_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION6_TEE_R_S  14
+/** HP_MEM_APM_REGION6_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION6_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION6_LOCK_M  (HP_MEM_APM_REGION6_LOCK_V << HP_MEM_APM_REGION6_LOCK_S)
+#define HP_MEM_APM_REGION6_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION6_LOCK_S  16
+
+/** HP_MEM_APM_REGION7_ADDR_START_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION7_ADDR_START_REG (DR_REG_HP_MEM_APM_BASE + 0x58)
+/** HP_MEM_APM_REGION7_ADDR_START_L : HRO; bitpos: [6:0]; default: 0;
+ *  Low 12 bit, start address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_START_L    0x0000007FU
+#define HP_MEM_APM_REGION7_ADDR_START_L_M  (HP_MEM_APM_REGION7_ADDR_START_L_V << HP_MEM_APM_REGION7_ADDR_START_L_S)
+#define HP_MEM_APM_REGION7_ADDR_START_L_V  0x0000007FU
+#define HP_MEM_APM_REGION7_ADDR_START_L_S  0
+/** HP_MEM_APM_REGION7_ADDR_START : R/W; bitpos: [18:7]; default: 0;
+ *  Configures start address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_START    0x00000FFFU
+#define HP_MEM_APM_REGION7_ADDR_START_M  (HP_MEM_APM_REGION7_ADDR_START_V << HP_MEM_APM_REGION7_ADDR_START_S)
+#define HP_MEM_APM_REGION7_ADDR_START_V  0x00000FFFU
+#define HP_MEM_APM_REGION7_ADDR_START_S  7
+/** HP_MEM_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  start address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_START_H    0x00001FFFU
+#define HP_MEM_APM_REGION7_ADDR_START_H_M  (HP_MEM_APM_REGION7_ADDR_START_H_V << HP_MEM_APM_REGION7_ADDR_START_H_S)
+#define HP_MEM_APM_REGION7_ADDR_START_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION7_ADDR_START_H_S  19
+
+/** HP_MEM_APM_REGION7_ADDR_END_REG register
+ *  Region address register
+ */
+#define HP_MEM_APM_REGION7_ADDR_END_REG (DR_REG_HP_MEM_APM_BASE + 0x5c)
+/** HP_MEM_APM_REGION7_ADDR_END_L : HRO; bitpos: [6:0]; default: 127;
+ *  Low 12 bit, end address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_END_L    0x0000007FU
+#define HP_MEM_APM_REGION7_ADDR_END_L_M  (HP_MEM_APM_REGION7_ADDR_END_L_V << HP_MEM_APM_REGION7_ADDR_END_L_S)
+#define HP_MEM_APM_REGION7_ADDR_END_L_V  0x0000007FU
+#define HP_MEM_APM_REGION7_ADDR_END_L_S  0
+/** HP_MEM_APM_REGION7_ADDR_END : R/W; bitpos: [18:7]; default: 4095;
+ *  Configures end address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_END    0x00000FFFU
+#define HP_MEM_APM_REGION7_ADDR_END_M  (HP_MEM_APM_REGION7_ADDR_END_V << HP_MEM_APM_REGION7_ADDR_END_S)
+#define HP_MEM_APM_REGION7_ADDR_END_V  0x00000FFFU
+#define HP_MEM_APM_REGION7_ADDR_END_S  7
+/** HP_MEM_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 1504;
+ *  High 13 bit,  end address of region 7.
+ */
+#define HP_MEM_APM_REGION7_ADDR_END_H    0x00001FFFU
+#define HP_MEM_APM_REGION7_ADDR_END_H_M  (HP_MEM_APM_REGION7_ADDR_END_H_V << HP_MEM_APM_REGION7_ADDR_END_H_S)
+#define HP_MEM_APM_REGION7_ADDR_END_H_V  0x00001FFFU
+#define HP_MEM_APM_REGION7_ADDR_END_H_S  19
+
+/** HP_MEM_APM_REGION7_ATTR_REG register
+ *  Region access authority attribute register
+ */
+#define HP_MEM_APM_REGION7_ATTR_REG (DR_REG_HP_MEM_APM_BASE + 0x60)
+/** HP_MEM_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0;
+ *  Configures the execution authority of REE_MODE 0 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R0_X    (BIT(0))
+#define HP_MEM_APM_REGION7_R0_X_M  (HP_MEM_APM_REGION7_R0_X_V << HP_MEM_APM_REGION7_R0_X_S)
+#define HP_MEM_APM_REGION7_R0_X_V  0x00000001U
+#define HP_MEM_APM_REGION7_R0_X_S  0
+/** HP_MEM_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0;
+ *  Configures the write authority of REE_MODE 0 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R0_W    (BIT(1))
+#define HP_MEM_APM_REGION7_R0_W_M  (HP_MEM_APM_REGION7_R0_W_V << HP_MEM_APM_REGION7_R0_W_S)
+#define HP_MEM_APM_REGION7_R0_W_V  0x00000001U
+#define HP_MEM_APM_REGION7_R0_W_S  1
+/** HP_MEM_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0;
+ *  Configures the read authority of REE_MODE 0 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R0_R    (BIT(2))
+#define HP_MEM_APM_REGION7_R0_R_M  (HP_MEM_APM_REGION7_R0_R_V << HP_MEM_APM_REGION7_R0_R_S)
+#define HP_MEM_APM_REGION7_R0_R_V  0x00000001U
+#define HP_MEM_APM_REGION7_R0_R_S  2
+/** HP_MEM_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0;
+ *  Configures the execution authority of REE_MODE 1 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R1_X    (BIT(4))
+#define HP_MEM_APM_REGION7_R1_X_M  (HP_MEM_APM_REGION7_R1_X_V << HP_MEM_APM_REGION7_R1_X_S)
+#define HP_MEM_APM_REGION7_R1_X_V  0x00000001U
+#define HP_MEM_APM_REGION7_R1_X_S  4
+/** HP_MEM_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0;
+ *  Configures the write authority of REE_MODE 1 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R1_W    (BIT(5))
+#define HP_MEM_APM_REGION7_R1_W_M  (HP_MEM_APM_REGION7_R1_W_V << HP_MEM_APM_REGION7_R1_W_S)
+#define HP_MEM_APM_REGION7_R1_W_V  0x00000001U
+#define HP_MEM_APM_REGION7_R1_W_S  5
+/** HP_MEM_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0;
+ *  Configures the read authority of REE_MODE 1 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R1_R    (BIT(6))
+#define HP_MEM_APM_REGION7_R1_R_M  (HP_MEM_APM_REGION7_R1_R_V << HP_MEM_APM_REGION7_R1_R_S)
+#define HP_MEM_APM_REGION7_R1_R_V  0x00000001U
+#define HP_MEM_APM_REGION7_R1_R_S  6
+/** HP_MEM_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0;
+ *  Configures the execution authority of REE_MODE 2 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R2_X    (BIT(8))
+#define HP_MEM_APM_REGION7_R2_X_M  (HP_MEM_APM_REGION7_R2_X_V << HP_MEM_APM_REGION7_R2_X_S)
+#define HP_MEM_APM_REGION7_R2_X_V  0x00000001U
+#define HP_MEM_APM_REGION7_R2_X_S  8
+/** HP_MEM_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0;
+ *  Configures the write authority of REE_MODE 2 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R2_W    (BIT(9))
+#define HP_MEM_APM_REGION7_R2_W_M  (HP_MEM_APM_REGION7_R2_W_V << HP_MEM_APM_REGION7_R2_W_S)
+#define HP_MEM_APM_REGION7_R2_W_V  0x00000001U
+#define HP_MEM_APM_REGION7_R2_W_S  9
+/** HP_MEM_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0;
+ *  Configures the read authority of REE_MODE 2 in region 7.
+ */
+#define HP_MEM_APM_REGION7_R2_R    (BIT(10))
+#define HP_MEM_APM_REGION7_R2_R_M  (HP_MEM_APM_REGION7_R2_R_V << HP_MEM_APM_REGION7_R2_R_S)
+#define HP_MEM_APM_REGION7_R2_R_V  0x00000001U
+#define HP_MEM_APM_REGION7_R2_R_S  10
+/** HP_MEM_APM_REGION7_TEE_X : R/W; bitpos: [12]; default: 1;
+ *  Configures the execution authority of TEE_MODE in region 7.
+ */
+#define HP_MEM_APM_REGION7_TEE_X    (BIT(12))
+#define HP_MEM_APM_REGION7_TEE_X_M  (HP_MEM_APM_REGION7_TEE_X_V << HP_MEM_APM_REGION7_TEE_X_S)
+#define HP_MEM_APM_REGION7_TEE_X_V  0x00000001U
+#define HP_MEM_APM_REGION7_TEE_X_S  12
+/** HP_MEM_APM_REGION7_TEE_W : R/W; bitpos: [13]; default: 1;
+ *  Configures the write authority of TEE_MODE in region 7.
+ */
+#define HP_MEM_APM_REGION7_TEE_W    (BIT(13))
+#define HP_MEM_APM_REGION7_TEE_W_M  (HP_MEM_APM_REGION7_TEE_W_V << HP_MEM_APM_REGION7_TEE_W_S)
+#define HP_MEM_APM_REGION7_TEE_W_V  0x00000001U
+#define HP_MEM_APM_REGION7_TEE_W_S  13
+/** HP_MEM_APM_REGION7_TEE_R : R/W; bitpos: [14]; default: 1;
+ *  Configures the read authority of TEE_MODE in region 7.
+ */
+#define HP_MEM_APM_REGION7_TEE_R    (BIT(14))
+#define HP_MEM_APM_REGION7_TEE_R_M  (HP_MEM_APM_REGION7_TEE_R_V << HP_MEM_APM_REGION7_TEE_R_S)
+#define HP_MEM_APM_REGION7_TEE_R_V  0x00000001U
+#define HP_MEM_APM_REGION7_TEE_R_S  14
+/** HP_MEM_APM_REGION7_LOCK : R/W; bitpos: [16]; default: 0;
+ *  Set 1 to lock region0 configuration
+ */
+#define HP_MEM_APM_REGION7_LOCK    (BIT(16))
+#define HP_MEM_APM_REGION7_LOCK_M  (HP_MEM_APM_REGION7_LOCK_V << HP_MEM_APM_REGION7_LOCK_S)
+#define HP_MEM_APM_REGION7_LOCK_V  0x00000001U
+#define HP_MEM_APM_REGION7_LOCK_S  16
+
+/** HP_MEM_APM_FUNC_CTRL_REG register
+ *  APM function control register
+ */
+#define HP_MEM_APM_FUNC_CTRL_REG (DR_REG_HP_MEM_APM_BASE + 0xc4)
+/** HP_MEM_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1;
+ *  PMS M0 function enable
+ */
+#define HP_MEM_APM_M0_FUNC_EN    (BIT(0))
+#define HP_MEM_APM_M0_FUNC_EN_M  (HP_MEM_APM_M0_FUNC_EN_V << HP_MEM_APM_M0_FUNC_EN_S)
+#define HP_MEM_APM_M0_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M0_FUNC_EN_S  0
+/** HP_MEM_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1;
+ *  PMS M1 function enable
+ */
+#define HP_MEM_APM_M1_FUNC_EN    (BIT(1))
+#define HP_MEM_APM_M1_FUNC_EN_M  (HP_MEM_APM_M1_FUNC_EN_V << HP_MEM_APM_M1_FUNC_EN_S)
+#define HP_MEM_APM_M1_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M1_FUNC_EN_S  1
+/** HP_MEM_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1;
+ *  PMS M2 function enable
+ */
+#define HP_MEM_APM_M2_FUNC_EN    (BIT(2))
+#define HP_MEM_APM_M2_FUNC_EN_M  (HP_MEM_APM_M2_FUNC_EN_V << HP_MEM_APM_M2_FUNC_EN_S)
+#define HP_MEM_APM_M2_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M2_FUNC_EN_S  2
+/** HP_MEM_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1;
+ *  PMS M3 function enable
+ */
+#define HP_MEM_APM_M3_FUNC_EN    (BIT(3))
+#define HP_MEM_APM_M3_FUNC_EN_M  (HP_MEM_APM_M3_FUNC_EN_V << HP_MEM_APM_M3_FUNC_EN_S)
+#define HP_MEM_APM_M3_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M3_FUNC_EN_S  3
+/** HP_MEM_APM_M4_FUNC_EN : R/W; bitpos: [4]; default: 1;
+ *  PMS M4 function enable
+ */
+#define HP_MEM_APM_M4_FUNC_EN    (BIT(4))
+#define HP_MEM_APM_M4_FUNC_EN_M  (HP_MEM_APM_M4_FUNC_EN_V << HP_MEM_APM_M4_FUNC_EN_S)
+#define HP_MEM_APM_M4_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M4_FUNC_EN_S  4
+/** HP_MEM_APM_M5_FUNC_EN : R/W; bitpos: [5]; default: 1;
+ *  PMS M5 function enable
+ */
+#define HP_MEM_APM_M5_FUNC_EN    (BIT(5))
+#define HP_MEM_APM_M5_FUNC_EN_M  (HP_MEM_APM_M5_FUNC_EN_V << HP_MEM_APM_M5_FUNC_EN_S)
+#define HP_MEM_APM_M5_FUNC_EN_V  0x00000001U
+#define HP_MEM_APM_M5_FUNC_EN_S  5
+
+/** HP_MEM_APM_M0_STATUS_REG register
+ *  M0 status register
+ */
+#define HP_MEM_APM_M0_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xc8)
+/** HP_MEM_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M0_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_M  (HP_MEM_APM_M0_EXCEPTION_STATUS_V << HP_MEM_APM_M0_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M0_STATUS_CLR_REG register
+ *  M0 status clear register
+ */
+#define HP_MEM_APM_M0_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xcc)
+/** HP_MEM_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M0_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M0_EXCEPTION_INFO0_REG register
+ *  M0 exception_info0 register
+ */
+#define HP_MEM_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xd0)
+/** HP_MEM_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M0_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M0_EXCEPTION_REGION_M  (HP_MEM_APM_M0_EXCEPTION_REGION_V << HP_MEM_APM_M0_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M0_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M0_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M0_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M0_EXCEPTION_MODE_M  (HP_MEM_APM_M0_EXCEPTION_MODE_V << HP_MEM_APM_M0_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M0_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M0_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M0_EXCEPTION_ID    0x0000001FU
+#define HP_MEM_APM_M0_EXCEPTION_ID_M  (HP_MEM_APM_M0_EXCEPTION_ID_V << HP_MEM_APM_M0_EXCEPTION_ID_S)
+#define HP_MEM_APM_M0_EXCEPTION_ID_V  0x0000001FU
+#define HP_MEM_APM_M0_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M0_EXCEPTION_INFO1_REG register
+ *  M0 exception_info1 register
+ */
+#define HP_MEM_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xd4)
+/** HP_MEM_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M0_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M0_EXCEPTION_ADDR_M  (HP_MEM_APM_M0_EXCEPTION_ADDR_V << HP_MEM_APM_M0_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M0_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M0_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_M1_STATUS_REG register
+ *  M1 status register
+ */
+#define HP_MEM_APM_M1_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xd8)
+/** HP_MEM_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M1_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_M  (HP_MEM_APM_M1_EXCEPTION_STATUS_V << HP_MEM_APM_M1_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M1_STATUS_CLR_REG register
+ *  M1 status clear register
+ */
+#define HP_MEM_APM_M1_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xdc)
+/** HP_MEM_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M1_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M1_EXCEPTION_INFO0_REG register
+ *  M1 exception_info0 register
+ */
+#define HP_MEM_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xe0)
+/** HP_MEM_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M1_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M1_EXCEPTION_REGION_M  (HP_MEM_APM_M1_EXCEPTION_REGION_V << HP_MEM_APM_M1_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M1_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M1_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M1_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M1_EXCEPTION_MODE_M  (HP_MEM_APM_M1_EXCEPTION_MODE_V << HP_MEM_APM_M1_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M1_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M1_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M1_EXCEPTION_ID    0x0000001FU
+#define HP_MEM_APM_M1_EXCEPTION_ID_M  (HP_MEM_APM_M1_EXCEPTION_ID_V << HP_MEM_APM_M1_EXCEPTION_ID_S)
+#define HP_MEM_APM_M1_EXCEPTION_ID_V  0x0000001FU
+#define HP_MEM_APM_M1_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M1_EXCEPTION_INFO1_REG register
+ *  M1 exception_info1 register
+ */
+#define HP_MEM_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xe4)
+/** HP_MEM_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M1_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M1_EXCEPTION_ADDR_M  (HP_MEM_APM_M1_EXCEPTION_ADDR_V << HP_MEM_APM_M1_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M1_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M1_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_M2_STATUS_REG register
+ *  M2 status register
+ */
+#define HP_MEM_APM_M2_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xe8)
+/** HP_MEM_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M2_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_M  (HP_MEM_APM_M2_EXCEPTION_STATUS_V << HP_MEM_APM_M2_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M2_STATUS_CLR_REG register
+ *  M2 status clear register
+ */
+#define HP_MEM_APM_M2_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xec)
+/** HP_MEM_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M2_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M2_EXCEPTION_INFO0_REG register
+ *  M2 exception_info0 register
+ */
+#define HP_MEM_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0xf0)
+/** HP_MEM_APM_M2_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M2_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M2_EXCEPTION_REGION_M  (HP_MEM_APM_M2_EXCEPTION_REGION_V << HP_MEM_APM_M2_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M2_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M2_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M2_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M2_EXCEPTION_MODE_M  (HP_MEM_APM_M2_EXCEPTION_MODE_V << HP_MEM_APM_M2_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M2_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M2_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M2_EXCEPTION_ID    0x0000001FU
+#define HP_MEM_APM_M2_EXCEPTION_ID_M  (HP_MEM_APM_M2_EXCEPTION_ID_V << HP_MEM_APM_M2_EXCEPTION_ID_S)
+#define HP_MEM_APM_M2_EXCEPTION_ID_V  0x0000001FU
+#define HP_MEM_APM_M2_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M2_EXCEPTION_INFO1_REG register
+ *  M2 exception_info1 register
+ */
+#define HP_MEM_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0xf4)
+/** HP_MEM_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M2_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M2_EXCEPTION_ADDR_M  (HP_MEM_APM_M2_EXCEPTION_ADDR_V << HP_MEM_APM_M2_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M2_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M2_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_M3_STATUS_REG register
+ *  M3 status register
+ */
+#define HP_MEM_APM_M3_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0xf8)
+/** HP_MEM_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M3_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_M  (HP_MEM_APM_M3_EXCEPTION_STATUS_V << HP_MEM_APM_M3_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M3_STATUS_CLR_REG register
+ *  M3 status clear register
+ */
+#define HP_MEM_APM_M3_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0xfc)
+/** HP_MEM_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M3_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M3_EXCEPTION_INFO0_REG register
+ *  M3 exception_info0 register
+ */
+#define HP_MEM_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0x100)
+/** HP_MEM_APM_M3_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M3_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M3_EXCEPTION_REGION_M  (HP_MEM_APM_M3_EXCEPTION_REGION_V << HP_MEM_APM_M3_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M3_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M3_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M3_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M3_EXCEPTION_MODE_M  (HP_MEM_APM_M3_EXCEPTION_MODE_V << HP_MEM_APM_M3_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M3_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M3_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M3_EXCEPTION_ID    0x0000001FU
+#define HP_MEM_APM_M3_EXCEPTION_ID_M  (HP_MEM_APM_M3_EXCEPTION_ID_V << HP_MEM_APM_M3_EXCEPTION_ID_S)
+#define HP_MEM_APM_M3_EXCEPTION_ID_V  0x0000001FU
+#define HP_MEM_APM_M3_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M3_EXCEPTION_INFO1_REG register
+ *  M3 exception_info1 register
+ */
+#define HP_MEM_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0x104)
+/** HP_MEM_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M3_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M3_EXCEPTION_ADDR_M  (HP_MEM_APM_M3_EXCEPTION_ADDR_V << HP_MEM_APM_M3_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M3_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M3_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_M4_STATUS_REG register
+ *  M4 status register
+ */
+#define HP_MEM_APM_M4_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0x108)
+/** HP_MEM_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M4_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_M  (HP_MEM_APM_M4_EXCEPTION_STATUS_V << HP_MEM_APM_M4_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M4_STATUS_CLR_REG register
+ *  M4 status clear register
+ */
+#define HP_MEM_APM_M4_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0x10c)
+/** HP_MEM_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M4_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M4_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M4_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M4_EXCEPTION_INFO0_REG register
+ *  M4 exception_info0 register
+ */
+#define HP_MEM_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0x110)
+/** HP_MEM_APM_M4_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M4_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M4_EXCEPTION_REGION_M  (HP_MEM_APM_M4_EXCEPTION_REGION_V << HP_MEM_APM_M4_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M4_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M4_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M4_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M4_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M4_EXCEPTION_MODE_M  (HP_MEM_APM_M4_EXCEPTION_MODE_V << HP_MEM_APM_M4_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M4_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M4_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M4_EXCEPTION_ID : RO; bitpos: [24:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M4_EXCEPTION_ID    0x0000007FU
+#define HP_MEM_APM_M4_EXCEPTION_ID_M  (HP_MEM_APM_M4_EXCEPTION_ID_V << HP_MEM_APM_M4_EXCEPTION_ID_S)
+#define HP_MEM_APM_M4_EXCEPTION_ID_V  0x0000007FU
+#define HP_MEM_APM_M4_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M4_EXCEPTION_INFO1_REG register
+ *  M4 exception_info1 register
+ */
+#define HP_MEM_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0x114)
+/** HP_MEM_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M4_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M4_EXCEPTION_ADDR_M  (HP_MEM_APM_M4_EXCEPTION_ADDR_V << HP_MEM_APM_M4_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M4_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M4_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_M5_STATUS_REG register
+ *  M5 status register
+ */
+#define HP_MEM_APM_M5_STATUS_REG (DR_REG_HP_MEM_APM_BASE + 0x118)
+/** HP_MEM_APM_M5_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  Represents exception status.
+ *  bit0: 1 represents authority_exception
+ *  bit1: 1 represents space_exception
+ */
+#define HP_MEM_APM_M5_EXCEPTION_STATUS    0x00000003U
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_M  (HP_MEM_APM_M5_EXCEPTION_STATUS_V << HP_MEM_APM_M5_EXCEPTION_STATUS_S)
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_V  0x00000003U
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_S  0
+
+/** HP_MEM_APM_M5_STATUS_CLR_REG register
+ *  M5 status clear register
+ */
+#define HP_MEM_APM_M5_STATUS_CLR_REG (DR_REG_HP_MEM_APM_BASE + 0x11c)
+/** HP_MEM_APM_M5_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures to clear exception status.
+ */
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_CLR    (BIT(0))
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_CLR_M  (HP_MEM_APM_M5_EXCEPTION_STATUS_CLR_V << HP_MEM_APM_M5_EXCEPTION_STATUS_CLR_S)
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_CLR_V  0x00000001U
+#define HP_MEM_APM_M5_EXCEPTION_STATUS_CLR_S  0
+
+/** HP_MEM_APM_M5_EXCEPTION_INFO0_REG register
+ *  M5 exception_info0 register
+ */
+#define HP_MEM_APM_M5_EXCEPTION_INFO0_REG (DR_REG_HP_MEM_APM_BASE + 0x120)
+/** HP_MEM_APM_M5_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0;
+ *  Represents exception region.
+ */
+#define HP_MEM_APM_M5_EXCEPTION_REGION    0x000000FFU
+#define HP_MEM_APM_M5_EXCEPTION_REGION_M  (HP_MEM_APM_M5_EXCEPTION_REGION_V << HP_MEM_APM_M5_EXCEPTION_REGION_S)
+#define HP_MEM_APM_M5_EXCEPTION_REGION_V  0x000000FFU
+#define HP_MEM_APM_M5_EXCEPTION_REGION_S  0
+/** HP_MEM_APM_M5_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0;
+ *  Represents exception mode.
+ */
+#define HP_MEM_APM_M5_EXCEPTION_MODE    0x00000003U
+#define HP_MEM_APM_M5_EXCEPTION_MODE_M  (HP_MEM_APM_M5_EXCEPTION_MODE_V << HP_MEM_APM_M5_EXCEPTION_MODE_S)
+#define HP_MEM_APM_M5_EXCEPTION_MODE_V  0x00000003U
+#define HP_MEM_APM_M5_EXCEPTION_MODE_S  16
+/** HP_MEM_APM_M5_EXCEPTION_ID : RO; bitpos: [23:18]; default: 0;
+ *  Represents exception id information.
+ */
+#define HP_MEM_APM_M5_EXCEPTION_ID    0x0000003FU
+#define HP_MEM_APM_M5_EXCEPTION_ID_M  (HP_MEM_APM_M5_EXCEPTION_ID_V << HP_MEM_APM_M5_EXCEPTION_ID_S)
+#define HP_MEM_APM_M5_EXCEPTION_ID_V  0x0000003FU
+#define HP_MEM_APM_M5_EXCEPTION_ID_S  18
+
+/** HP_MEM_APM_M5_EXCEPTION_INFO1_REG register
+ *  M5 exception_info1 register
+ */
+#define HP_MEM_APM_M5_EXCEPTION_INFO1_REG (DR_REG_HP_MEM_APM_BASE + 0x124)
+/** HP_MEM_APM_M5_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents exception addr.
+ */
+#define HP_MEM_APM_M5_EXCEPTION_ADDR    0xFFFFFFFFU
+#define HP_MEM_APM_M5_EXCEPTION_ADDR_M  (HP_MEM_APM_M5_EXCEPTION_ADDR_V << HP_MEM_APM_M5_EXCEPTION_ADDR_S)
+#define HP_MEM_APM_M5_EXCEPTION_ADDR_V  0xFFFFFFFFU
+#define HP_MEM_APM_M5_EXCEPTION_ADDR_S  0
+
+/** HP_MEM_APM_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define HP_MEM_APM_INT_EN_REG (DR_REG_HP_MEM_APM_BASE + 0x128)
+/** HP_MEM_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures to enable APM M0 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M0_APM_INT_EN    (BIT(0))
+#define HP_MEM_APM_M0_APM_INT_EN_M  (HP_MEM_APM_M0_APM_INT_EN_V << HP_MEM_APM_M0_APM_INT_EN_S)
+#define HP_MEM_APM_M0_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M0_APM_INT_EN_S  0
+/** HP_MEM_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures to enable APM M1 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M1_APM_INT_EN    (BIT(1))
+#define HP_MEM_APM_M1_APM_INT_EN_M  (HP_MEM_APM_M1_APM_INT_EN_V << HP_MEM_APM_M1_APM_INT_EN_S)
+#define HP_MEM_APM_M1_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M1_APM_INT_EN_S  1
+/** HP_MEM_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures to enable APM M2 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M2_APM_INT_EN    (BIT(2))
+#define HP_MEM_APM_M2_APM_INT_EN_M  (HP_MEM_APM_M2_APM_INT_EN_V << HP_MEM_APM_M2_APM_INT_EN_S)
+#define HP_MEM_APM_M2_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M2_APM_INT_EN_S  2
+/** HP_MEM_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0;
+ *  Configures to enable APM M3 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M3_APM_INT_EN    (BIT(3))
+#define HP_MEM_APM_M3_APM_INT_EN_M  (HP_MEM_APM_M3_APM_INT_EN_V << HP_MEM_APM_M3_APM_INT_EN_S)
+#define HP_MEM_APM_M3_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M3_APM_INT_EN_S  3
+/** HP_MEM_APM_M4_APM_INT_EN : R/W; bitpos: [4]; default: 0;
+ *  Configures to enable APM M4 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M4_APM_INT_EN    (BIT(4))
+#define HP_MEM_APM_M4_APM_INT_EN_M  (HP_MEM_APM_M4_APM_INT_EN_V << HP_MEM_APM_M4_APM_INT_EN_S)
+#define HP_MEM_APM_M4_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M4_APM_INT_EN_S  4
+/** HP_MEM_APM_M5_APM_INT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures to enable APM M5 interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_MEM_APM_M5_APM_INT_EN    (BIT(5))
+#define HP_MEM_APM_M5_APM_INT_EN_M  (HP_MEM_APM_M5_APM_INT_EN_V << HP_MEM_APM_M5_APM_INT_EN_S)
+#define HP_MEM_APM_M5_APM_INT_EN_V  0x00000001U
+#define HP_MEM_APM_M5_APM_INT_EN_S  5
+
+/** HP_MEM_APM_BUS_ERR_CONF_REG register
+ *  APM interrupt enable register
+ */
+#define HP_MEM_APM_BUS_ERR_CONF_REG (DR_REG_HP_MEM_APM_BASE + 0x12c)
+/** HP_MEM_APM_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether return error response to cpu when access blocked
+ *  0: disable error response
+ *  1: enable error response
+ */
+#define HP_MEM_APM_BUS_ERR_RESP_EN    (BIT(0))
+#define HP_MEM_APM_BUS_ERR_RESP_EN_M  (HP_MEM_APM_BUS_ERR_RESP_EN_V << HP_MEM_APM_BUS_ERR_RESP_EN_S)
+#define HP_MEM_APM_BUS_ERR_RESP_EN_V  0x00000001U
+#define HP_MEM_APM_BUS_ERR_RESP_EN_S  0
+
+/** HP_MEM_APM_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define HP_MEM_APM_CLOCK_GATE_REG (DR_REG_HP_MEM_APM_BASE + 0x3f8)
+/** HP_MEM_APM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: enable automatic clock gating
+ *  1: keep the clock always on
+ */
+#define HP_MEM_APM_CLK_EN    (BIT(0))
+#define HP_MEM_APM_CLK_EN_M  (HP_MEM_APM_CLK_EN_V << HP_MEM_APM_CLK_EN_S)
+#define HP_MEM_APM_CLK_EN_V  0x00000001U
+#define HP_MEM_APM_CLK_EN_S  0
+
+/** HP_MEM_APM_DATE_REG register
+ *  Version control register
+ */
+#define HP_MEM_APM_DATE_REG (DR_REG_HP_MEM_APM_BASE + 0x3fc)
+/** HP_MEM_APM_DATE : R/W; bitpos: [27:0]; default: 38822496;
+ *  Version control register.
+ */
+#define HP_MEM_APM_DATE    0x0FFFFFFFU
+#define HP_MEM_APM_DATE_M  (HP_MEM_APM_DATE_V << HP_MEM_APM_DATE_S)
+#define HP_MEM_APM_DATE_V  0x0FFFFFFFU
+#define HP_MEM_APM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
new file mode 100644
index 00000000000..3f2cdf5fa73
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_mem_apm_struct.h
@@ -0,0 +1,787 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Region filter enable register */
+/** Type of region_filter_en register
+ *  Region filter enable register
+ */
+typedef union {
+    struct {
+        /** region_filter_en : R/W; bitpos: [7:0]; default: 1;
+         *  Configure bit $n (0-7) to enable region $n.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t region_filter_en:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_mem_apm_region_filter_en_reg_t;
+
+
+/** Group: Region address register */
+/** Type of regionn_addr_start register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_start_l : HRO; bitpos: [6:0]; default: 0;
+         *  Low 12 bit, start address of region n.
+         */
+        uint32_t regionn_addr_start_l:7;
+        /** regionn_addr_start : R/W; bitpos: [18:7]; default: 0;
+         *  Configures start address of region n.
+         */
+        uint32_t regionn_addr_start:12;
+        /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 1504;
+         *  High 13 bit,  start address of region n.
+         */
+        uint32_t regionn_addr_start_h:13;
+    };
+    uint32_t val;
+} hp_mem_apm_regionn_addr_start_reg_t;
+
+/** Type of regionn_addr_end register
+ *  Region address register
+ */
+typedef union {
+    struct {
+        /** regionn_addr_end_l : HRO; bitpos: [6:0]; default: 127;
+         *  Low 12 bit, end address of region n.
+         */
+        uint32_t regionn_addr_end_l:7;
+        /** regionn_addr_end : R/W; bitpos: [18:7]; default: 4095;
+         *  Configures end address of region n.
+         */
+        uint32_t regionn_addr_end:12;
+        /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 1504;
+         *  High 13 bit,  end address of region n.
+         */
+        uint32_t regionn_addr_end_h:13;
+    };
+    uint32_t val;
+} hp_mem_apm_regionn_addr_end_reg_t;
+
+
+/** Group: Region access authority attribute register */
+/** Type of regionn_attr register
+ *  Region access authority attribute register
+ */
+typedef union {
+    struct {
+        /** regionn_r0_x : R/W; bitpos: [0]; default: 0;
+         *  Configures the execution authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_x:1;
+        /** regionn_r0_w : R/W; bitpos: [1]; default: 0;
+         *  Configures the write authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_w:1;
+        /** regionn_r0_r : R/W; bitpos: [2]; default: 0;
+         *  Configures the read authority of REE_MODE 0 in region n.
+         */
+        uint32_t regionn_r0_r:1;
+        uint32_t reserved_3:1;
+        /** regionn_r1_x : R/W; bitpos: [4]; default: 0;
+         *  Configures the execution authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_x:1;
+        /** regionn_r1_w : R/W; bitpos: [5]; default: 0;
+         *  Configures the write authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_w:1;
+        /** regionn_r1_r : R/W; bitpos: [6]; default: 0;
+         *  Configures the read authority of REE_MODE 1 in region n.
+         */
+        uint32_t regionn_r1_r:1;
+        uint32_t reserved_7:1;
+        /** regionn_r2_x : R/W; bitpos: [8]; default: 0;
+         *  Configures the execution authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_x:1;
+        /** regionn_r2_w : R/W; bitpos: [9]; default: 0;
+         *  Configures the write authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_w:1;
+        /** regionn_r2_r : R/W; bitpos: [10]; default: 0;
+         *  Configures the read authority of REE_MODE 2 in region n.
+         */
+        uint32_t regionn_r2_r:1;
+        uint32_t reserved_11:1;
+        /** regionn_tee_x : R/W; bitpos: [12]; default: 1;
+         *  Configures the execution authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_x:1;
+        /** regionn_tee_w : R/W; bitpos: [13]; default: 1;
+         *  Configures the write authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_w:1;
+        /** regionn_tee_r : R/W; bitpos: [14]; default: 1;
+         *  Configures the read authority of TEE_MODE in region n.
+         */
+        uint32_t regionn_tee_r:1;
+        uint32_t reserved_15:1;
+        /** regionn_lock : R/W; bitpos: [16]; default: 0;
+         *  Set 1 to lock region0 configuration
+         */
+        uint32_t regionn_lock:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_mem_apm_regionn_attr_reg_t;
+
+
+/** Group: function control register */
+/** Type of func_ctrl register
+ *  APM function control register
+ */
+typedef union {
+    struct {
+        /** m0_func_en : R/W; bitpos: [0]; default: 1;
+         *  PMS M0 function enable
+         */
+        uint32_t m0_func_en:1;
+        /** m1_func_en : R/W; bitpos: [1]; default: 1;
+         *  PMS M1 function enable
+         */
+        uint32_t m1_func_en:1;
+        /** m2_func_en : R/W; bitpos: [2]; default: 1;
+         *  PMS M2 function enable
+         */
+        uint32_t m2_func_en:1;
+        /** m3_func_en : R/W; bitpos: [3]; default: 1;
+         *  PMS M3 function enable
+         */
+        uint32_t m3_func_en:1;
+        /** m4_func_en : R/W; bitpos: [4]; default: 1;
+         *  PMS M4 function enable
+         */
+        uint32_t m4_func_en:1;
+        /** m5_func_en : R/W; bitpos: [5]; default: 1;
+         *  PMS M5 function enable
+         */
+        uint32_t m5_func_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_mem_apm_func_ctrl_reg_t;
+
+
+/** Group: M0 status register */
+/** Type of m0_status register
+ *  M0 status register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m0_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m0_status_reg_t;
+
+
+/** Group: M0 status clear register */
+/** Type of m0_status_clr register
+ *  M0 status clear register
+ */
+typedef union {
+    struct {
+        /** m0_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m0_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m0_status_clr_reg_t;
+
+
+/** Group: M0 exception_info0 register */
+/** Type of m0_exception_info0 register
+ *  M0 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m0_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m0_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m0_exception_mode:2;
+        /** m0_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m0_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_mem_apm_m0_exception_info0_reg_t;
+
+
+/** Group: M0 exception_info1 register */
+/** Type of m0_exception_info1 register
+ *  M0 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m0_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m0_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m0_exception_info1_reg_t;
+
+
+/** Group: M1 status register */
+/** Type of m1_status register
+ *  M1 status register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m1_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m1_status_reg_t;
+
+
+/** Group: M1 status clear register */
+/** Type of m1_status_clr register
+ *  M1 status clear register
+ */
+typedef union {
+    struct {
+        /** m1_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m1_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m1_status_clr_reg_t;
+
+
+/** Group: M1 exception_info0 register */
+/** Type of m1_exception_info0 register
+ *  M1 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m1_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m1_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m1_exception_mode:2;
+        /** m1_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m1_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_mem_apm_m1_exception_info0_reg_t;
+
+
+/** Group: M1 exception_info1 register */
+/** Type of m1_exception_info1 register
+ *  M1 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m1_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m1_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m1_exception_info1_reg_t;
+
+
+/** Group: M2 status register */
+/** Type of m2_status register
+ *  M2 status register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m2_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m2_status_reg_t;
+
+
+/** Group: M2 status clear register */
+/** Type of m2_status_clr register
+ *  M2 status clear register
+ */
+typedef union {
+    struct {
+        /** m2_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m2_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m2_status_clr_reg_t;
+
+
+/** Group: M2 exception_info0 register */
+/** Type of m2_exception_info0 register
+ *  M2 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m2_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m2_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m2_exception_mode:2;
+        /** m2_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m2_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_mem_apm_m2_exception_info0_reg_t;
+
+
+/** Group: M2 exception_info1 register */
+/** Type of m2_exception_info1 register
+ *  M2 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m2_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m2_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m2_exception_info1_reg_t;
+
+
+/** Group: M3 status register */
+/** Type of m3_status register
+ *  M3 status register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m3_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m3_status_reg_t;
+
+
+/** Group: M3 status clear register */
+/** Type of m3_status_clr register
+ *  M3 status clear register
+ */
+typedef union {
+    struct {
+        /** m3_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m3_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m3_status_clr_reg_t;
+
+
+/** Group: M3 exception_info0 register */
+/** Type of m3_exception_info0 register
+ *  M3 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m3_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m3_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m3_exception_mode:2;
+        /** m3_exception_id : RO; bitpos: [22:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m3_exception_id:5;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} hp_mem_apm_m3_exception_info0_reg_t;
+
+
+/** Group: M3 exception_info1 register */
+/** Type of m3_exception_info1 register
+ *  M3 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m3_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m3_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m3_exception_info1_reg_t;
+
+
+/** Group: M4 status register */
+/** Type of m4_status register
+ *  M4 status register
+ */
+typedef union {
+    struct {
+        /** m4_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m4_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m4_status_reg_t;
+
+
+/** Group: M4 status clear register */
+/** Type of m4_status_clr register
+ *  M4 status clear register
+ */
+typedef union {
+    struct {
+        /** m4_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m4_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m4_status_clr_reg_t;
+
+
+/** Group: M4 exception_info0 register */
+/** Type of m4_exception_info0 register
+ *  M4 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m4_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m4_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m4_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m4_exception_mode:2;
+        /** m4_exception_id : RO; bitpos: [24:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m4_exception_id:7;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_mem_apm_m4_exception_info0_reg_t;
+
+
+/** Group: M4 exception_info1 register */
+/** Type of m4_exception_info1 register
+ *  M4 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m4_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m4_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m4_exception_info1_reg_t;
+
+
+/** Group: M5 status register */
+/** Type of m5_status register
+ *  M5 status register
+ */
+typedef union {
+    struct {
+        /** m5_exception_status : RO; bitpos: [1:0]; default: 0;
+         *  Represents exception status.
+         *  bit0: 1 represents authority_exception
+         *  bit1: 1 represents space_exception
+         */
+        uint32_t m5_exception_status:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_mem_apm_m5_status_reg_t;
+
+
+/** Group: M5 status clear register */
+/** Type of m5_status_clr register
+ *  M5 status clear register
+ */
+typedef union {
+    struct {
+        /** m5_exception_status_clr : WT; bitpos: [0]; default: 0;
+         *  Configures to clear exception status.
+         */
+        uint32_t m5_exception_status_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_m5_status_clr_reg_t;
+
+
+/** Group: M5 exception_info0 register */
+/** Type of m5_exception_info0 register
+ *  M5 exception_info0 register
+ */
+typedef union {
+    struct {
+        /** m5_exception_region : RO; bitpos: [7:0]; default: 0;
+         *  Represents exception region.
+         */
+        uint32_t m5_exception_region:8;
+        uint32_t reserved_8:8;
+        /** m5_exception_mode : RO; bitpos: [17:16]; default: 0;
+         *  Represents exception mode.
+         */
+        uint32_t m5_exception_mode:2;
+        /** m5_exception_id : RO; bitpos: [23:18]; default: 0;
+         *  Represents exception id information.
+         */
+        uint32_t m5_exception_id:6;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_mem_apm_m5_exception_info0_reg_t;
+
+
+/** Group: M5 exception_info1 register */
+/** Type of m5_exception_info1 register
+ *  M5 exception_info1 register
+ */
+typedef union {
+    struct {
+        /** m5_exception_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents exception addr.
+         */
+        uint32_t m5_exception_addr:32;
+    };
+    uint32_t val;
+} hp_mem_apm_m5_exception_info1_reg_t;
+
+
+/** Group: APM interrupt enable register */
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** m0_apm_int_en : R/W; bitpos: [0]; default: 0;
+         *  Configures to enable APM M0 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m0_apm_int_en:1;
+        /** m1_apm_int_en : R/W; bitpos: [1]; default: 0;
+         *  Configures to enable APM M1 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m1_apm_int_en:1;
+        /** m2_apm_int_en : R/W; bitpos: [2]; default: 0;
+         *  Configures to enable APM M2 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m2_apm_int_en:1;
+        /** m3_apm_int_en : R/W; bitpos: [3]; default: 0;
+         *  Configures to enable APM M3 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m3_apm_int_en:1;
+        /** m4_apm_int_en : R/W; bitpos: [4]; default: 0;
+         *  Configures to enable APM M4 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m4_apm_int_en:1;
+        /** m5_apm_int_en : R/W; bitpos: [5]; default: 0;
+         *  Configures to enable APM M5 interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t m5_apm_int_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_mem_apm_int_en_reg_t;
+
+/** Type of bus_err_conf register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether return error response to cpu when access blocked
+         *  0: disable error response
+         *  1: enable error response
+         */
+        uint32_t bus_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_bus_err_conf_reg_t;
+
+
+/** Group: Clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: enable automatic clock gating
+         *  1: keep the clock always on
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_mem_apm_clock_gate_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38822496;
+         *  Version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_mem_apm_date_reg_t;
+
+
+typedef struct {
+    volatile hp_mem_apm_region_filter_en_reg_t region_filter_en;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region0_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region0_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region0_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region1_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region1_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region1_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region2_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region2_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region2_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region3_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region3_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region3_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region4_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region4_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region4_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region5_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region5_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region5_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region6_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region6_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region6_attr;
+    volatile hp_mem_apm_regionn_addr_start_reg_t region7_addr_start;
+    volatile hp_mem_apm_regionn_addr_end_reg_t region7_addr_end;
+    volatile hp_mem_apm_regionn_attr_reg_t region7_attr;
+    uint32_t reserved_064[24];
+    volatile hp_mem_apm_func_ctrl_reg_t func_ctrl;
+    volatile hp_mem_apm_m0_status_reg_t m0_status;
+    volatile hp_mem_apm_m0_status_clr_reg_t m0_status_clr;
+    volatile hp_mem_apm_m0_exception_info0_reg_t m0_exception_info0;
+    volatile hp_mem_apm_m0_exception_info1_reg_t m0_exception_info1;
+    volatile hp_mem_apm_m1_status_reg_t m1_status;
+    volatile hp_mem_apm_m1_status_clr_reg_t m1_status_clr;
+    volatile hp_mem_apm_m1_exception_info0_reg_t m1_exception_info0;
+    volatile hp_mem_apm_m1_exception_info1_reg_t m1_exception_info1;
+    volatile hp_mem_apm_m2_status_reg_t m2_status;
+    volatile hp_mem_apm_m2_status_clr_reg_t m2_status_clr;
+    volatile hp_mem_apm_m2_exception_info0_reg_t m2_exception_info0;
+    volatile hp_mem_apm_m2_exception_info1_reg_t m2_exception_info1;
+    volatile hp_mem_apm_m3_status_reg_t m3_status;
+    volatile hp_mem_apm_m3_status_clr_reg_t m3_status_clr;
+    volatile hp_mem_apm_m3_exception_info0_reg_t m3_exception_info0;
+    volatile hp_mem_apm_m3_exception_info1_reg_t m3_exception_info1;
+    volatile hp_mem_apm_m4_status_reg_t m4_status;
+    volatile hp_mem_apm_m4_status_clr_reg_t m4_status_clr;
+    volatile hp_mem_apm_m4_exception_info0_reg_t m4_exception_info0;
+    volatile hp_mem_apm_m4_exception_info1_reg_t m4_exception_info1;
+    volatile hp_mem_apm_m5_status_reg_t m5_status;
+    volatile hp_mem_apm_m5_status_clr_reg_t m5_status_clr;
+    volatile hp_mem_apm_m5_exception_info0_reg_t m5_exception_info0;
+    volatile hp_mem_apm_m5_exception_info1_reg_t m5_exception_info1;
+    volatile hp_mem_apm_int_en_reg_t int_en;
+    volatile hp_mem_apm_bus_err_conf_reg_t bus_err_conf;
+    uint32_t reserved_130[178];
+    volatile hp_mem_apm_clock_gate_reg_t clock_gate;
+    volatile hp_mem_apm_date_reg_t date;
+} hp_mem_apm_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_mem_apm_dev_t) == 0x400, "Invalid size of hp_mem_apm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h b/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h
new file mode 100644
index 00000000000..a6e08d90792
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_peri0_pms_reg.h
@@ -0,0 +1,2862 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_PERI0_PMS_TRACE0_CTRL_REG register
+ *  trace0 read/write control register
+ */
+#define HP_PERI0_PMS_TRACE0_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x0)
+/** HP_PERI0_PMS_READ_TEE_TRACE0 : R/W; bitpos: [0]; default: 1;
+ *  Configures trace0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_TRACE0    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_TRACE0_M  (HP_PERI0_PMS_READ_TEE_TRACE0_V << HP_PERI0_PMS_READ_TEE_TRACE0_S)
+#define HP_PERI0_PMS_READ_TEE_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_TRACE0_S  0
+/** HP_PERI0_PMS_READ_REE0_TRACE0 : R/W; bitpos: [1]; default: 0;
+ *  Configures trace0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_TRACE0    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_TRACE0_M  (HP_PERI0_PMS_READ_REE0_TRACE0_V << HP_PERI0_PMS_READ_REE0_TRACE0_S)
+#define HP_PERI0_PMS_READ_REE0_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_TRACE0_S  1
+/** HP_PERI0_PMS_READ_REE1_TRACE0 : R/W; bitpos: [2]; default: 0;
+ *  Configures trace0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_TRACE0    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_TRACE0_M  (HP_PERI0_PMS_READ_REE1_TRACE0_V << HP_PERI0_PMS_READ_REE1_TRACE0_S)
+#define HP_PERI0_PMS_READ_REE1_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_TRACE0_S  2
+/** HP_PERI0_PMS_READ_REE2_TRACE0 : R/W; bitpos: [3]; default: 0;
+ *  Configures trace0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_TRACE0    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_TRACE0_M  (HP_PERI0_PMS_READ_REE2_TRACE0_V << HP_PERI0_PMS_READ_REE2_TRACE0_S)
+#define HP_PERI0_PMS_READ_REE2_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_TRACE0_S  3
+/** HP_PERI0_PMS_WRITE_TEE_TRACE0 : R/W; bitpos: [4]; default: 1;
+ *  Configures trace0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_TRACE0    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_TRACE0_M  (HP_PERI0_PMS_WRITE_TEE_TRACE0_V << HP_PERI0_PMS_WRITE_TEE_TRACE0_S)
+#define HP_PERI0_PMS_WRITE_TEE_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_TRACE0_S  4
+/** HP_PERI0_PMS_WRITE_REE0_TRACE0 : R/W; bitpos: [5]; default: 0;
+ *  Configures trace0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_TRACE0    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_TRACE0_M  (HP_PERI0_PMS_WRITE_REE0_TRACE0_V << HP_PERI0_PMS_WRITE_REE0_TRACE0_S)
+#define HP_PERI0_PMS_WRITE_REE0_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_TRACE0_S  5
+/** HP_PERI0_PMS_WRITE_REE1_TRACE0 : R/W; bitpos: [6]; default: 0;
+ *  Configures trace0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_TRACE0    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_TRACE0_M  (HP_PERI0_PMS_WRITE_REE1_TRACE0_V << HP_PERI0_PMS_WRITE_REE1_TRACE0_S)
+#define HP_PERI0_PMS_WRITE_REE1_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_TRACE0_S  6
+/** HP_PERI0_PMS_WRITE_REE2_TRACE0 : R/W; bitpos: [7]; default: 0;
+ *  Configures trace0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_TRACE0    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_TRACE0_M  (HP_PERI0_PMS_WRITE_REE2_TRACE0_V << HP_PERI0_PMS_WRITE_REE2_TRACE0_S)
+#define HP_PERI0_PMS_WRITE_REE2_TRACE0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_TRACE0_S  7
+/** HP_PERI0_PMS_TRACE0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock trace0 peri_apm configuration
+ */
+#define HP_PERI0_PMS_TRACE0_LOCK    (BIT(8))
+#define HP_PERI0_PMS_TRACE0_LOCK_M  (HP_PERI0_PMS_TRACE0_LOCK_V << HP_PERI0_PMS_TRACE0_LOCK_S)
+#define HP_PERI0_PMS_TRACE0_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_TRACE0_LOCK_S  8
+
+/** HP_PERI0_PMS_TRACE1_CTRL_REG register
+ *  trace1 read/write control register
+ */
+#define HP_PERI0_PMS_TRACE1_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x4)
+/** HP_PERI0_PMS_READ_TEE_TRACE1 : R/W; bitpos: [0]; default: 1;
+ *  Configures trace1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_TRACE1    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_TRACE1_M  (HP_PERI0_PMS_READ_TEE_TRACE1_V << HP_PERI0_PMS_READ_TEE_TRACE1_S)
+#define HP_PERI0_PMS_READ_TEE_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_TRACE1_S  0
+/** HP_PERI0_PMS_READ_REE0_TRACE1 : R/W; bitpos: [1]; default: 0;
+ *  Configures trace1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_TRACE1    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_TRACE1_M  (HP_PERI0_PMS_READ_REE0_TRACE1_V << HP_PERI0_PMS_READ_REE0_TRACE1_S)
+#define HP_PERI0_PMS_READ_REE0_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_TRACE1_S  1
+/** HP_PERI0_PMS_READ_REE1_TRACE1 : R/W; bitpos: [2]; default: 0;
+ *  Configures trace1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_TRACE1    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_TRACE1_M  (HP_PERI0_PMS_READ_REE1_TRACE1_V << HP_PERI0_PMS_READ_REE1_TRACE1_S)
+#define HP_PERI0_PMS_READ_REE1_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_TRACE1_S  2
+/** HP_PERI0_PMS_READ_REE2_TRACE1 : R/W; bitpos: [3]; default: 0;
+ *  Configures trace1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_TRACE1    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_TRACE1_M  (HP_PERI0_PMS_READ_REE2_TRACE1_V << HP_PERI0_PMS_READ_REE2_TRACE1_S)
+#define HP_PERI0_PMS_READ_REE2_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_TRACE1_S  3
+/** HP_PERI0_PMS_WRITE_TEE_TRACE1 : R/W; bitpos: [4]; default: 1;
+ *  Configures trace1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_TRACE1    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_TRACE1_M  (HP_PERI0_PMS_WRITE_TEE_TRACE1_V << HP_PERI0_PMS_WRITE_TEE_TRACE1_S)
+#define HP_PERI0_PMS_WRITE_TEE_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_TRACE1_S  4
+/** HP_PERI0_PMS_WRITE_REE0_TRACE1 : R/W; bitpos: [5]; default: 0;
+ *  Configures trace1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_TRACE1    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_TRACE1_M  (HP_PERI0_PMS_WRITE_REE0_TRACE1_V << HP_PERI0_PMS_WRITE_REE0_TRACE1_S)
+#define HP_PERI0_PMS_WRITE_REE0_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_TRACE1_S  5
+/** HP_PERI0_PMS_WRITE_REE1_TRACE1 : R/W; bitpos: [6]; default: 0;
+ *  Configures trace1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_TRACE1    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_TRACE1_M  (HP_PERI0_PMS_WRITE_REE1_TRACE1_V << HP_PERI0_PMS_WRITE_REE1_TRACE1_S)
+#define HP_PERI0_PMS_WRITE_REE1_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_TRACE1_S  6
+/** HP_PERI0_PMS_WRITE_REE2_TRACE1 : R/W; bitpos: [7]; default: 0;
+ *  Configures trace1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_TRACE1    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_TRACE1_M  (HP_PERI0_PMS_WRITE_REE2_TRACE1_V << HP_PERI0_PMS_WRITE_REE2_TRACE1_S)
+#define HP_PERI0_PMS_WRITE_REE2_TRACE1_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_TRACE1_S  7
+/** HP_PERI0_PMS_TRACE1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock trace1 peri_apm configuration
+ */
+#define HP_PERI0_PMS_TRACE1_LOCK    (BIT(8))
+#define HP_PERI0_PMS_TRACE1_LOCK_M  (HP_PERI0_PMS_TRACE1_LOCK_V << HP_PERI0_PMS_TRACE1_LOCK_S)
+#define HP_PERI0_PMS_TRACE1_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_TRACE1_LOCK_S  8
+
+/** HP_PERI0_PMS_CPU_BUS_MON_CTRL_REG register
+ *  cpu_bus_mon read/write control register
+ */
+#define HP_PERI0_PMS_CPU_BUS_MON_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x8)
+/** HP_PERI0_PMS_READ_TEE_CPU_BUS_MON : R/W; bitpos: [0]; default: 1;
+ *  Configures cpu_bus_mon registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_CPU_BUS_MON    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_CPU_BUS_MON_M  (HP_PERI0_PMS_READ_TEE_CPU_BUS_MON_V << HP_PERI0_PMS_READ_TEE_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_READ_TEE_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_CPU_BUS_MON_S  0
+/** HP_PERI0_PMS_READ_REE0_CPU_BUS_MON : R/W; bitpos: [1]; default: 0;
+ *  Configures cpu_bus_mon registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_CPU_BUS_MON    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_CPU_BUS_MON_M  (HP_PERI0_PMS_READ_REE0_CPU_BUS_MON_V << HP_PERI0_PMS_READ_REE0_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_READ_REE0_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_CPU_BUS_MON_S  1
+/** HP_PERI0_PMS_READ_REE1_CPU_BUS_MON : R/W; bitpos: [2]; default: 0;
+ *  Configures cpu_bus_mon registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_CPU_BUS_MON    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_CPU_BUS_MON_M  (HP_PERI0_PMS_READ_REE1_CPU_BUS_MON_V << HP_PERI0_PMS_READ_REE1_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_READ_REE1_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_CPU_BUS_MON_S  2
+/** HP_PERI0_PMS_READ_REE2_CPU_BUS_MON : R/W; bitpos: [3]; default: 0;
+ *  Configures cpu_bus_mon registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_CPU_BUS_MON    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_CPU_BUS_MON_M  (HP_PERI0_PMS_READ_REE2_CPU_BUS_MON_V << HP_PERI0_PMS_READ_REE2_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_READ_REE2_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_CPU_BUS_MON_S  3
+/** HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON : R/W; bitpos: [4]; default: 1;
+ *  Configures cpu_bus_mon registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON_M  (HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON_V << HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_CPU_BUS_MON_S  4
+/** HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON : R/W; bitpos: [5]; default: 0;
+ *  Configures cpu_bus_mon registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON_M  (HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON_V << HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_CPU_BUS_MON_S  5
+/** HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON : R/W; bitpos: [6]; default: 0;
+ *  Configures cpu_bus_mon registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON_M  (HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON_V << HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_CPU_BUS_MON_S  6
+/** HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON : R/W; bitpos: [7]; default: 0;
+ *  Configures cpu_bus_mon registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON_M  (HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON_V << HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON_S)
+#define HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_CPU_BUS_MON_S  7
+/** HP_PERI0_PMS_CPU_BUS_MON_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock cpu_bus_mon peri_apm configuration
+ */
+#define HP_PERI0_PMS_CPU_BUS_MON_LOCK    (BIT(8))
+#define HP_PERI0_PMS_CPU_BUS_MON_LOCK_M  (HP_PERI0_PMS_CPU_BUS_MON_LOCK_V << HP_PERI0_PMS_CPU_BUS_MON_LOCK_S)
+#define HP_PERI0_PMS_CPU_BUS_MON_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_CPU_BUS_MON_LOCK_S  8
+
+/** HP_PERI0_PMS_PSRAM_MON_CTRL_REG register
+ *  psram_mon read/write control register
+ */
+#define HP_PERI0_PMS_PSRAM_MON_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0xc)
+/** HP_PERI0_PMS_READ_TEE_PSRAM_MON : R/W; bitpos: [0]; default: 1;
+ *  Configures psram_mon registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_PSRAM_MON    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_PSRAM_MON_M  (HP_PERI0_PMS_READ_TEE_PSRAM_MON_V << HP_PERI0_PMS_READ_TEE_PSRAM_MON_S)
+#define HP_PERI0_PMS_READ_TEE_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_PSRAM_MON_S  0
+/** HP_PERI0_PMS_READ_REE0_PSRAM_MON : R/W; bitpos: [1]; default: 0;
+ *  Configures psram_mon registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_PSRAM_MON    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_PSRAM_MON_M  (HP_PERI0_PMS_READ_REE0_PSRAM_MON_V << HP_PERI0_PMS_READ_REE0_PSRAM_MON_S)
+#define HP_PERI0_PMS_READ_REE0_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_PSRAM_MON_S  1
+/** HP_PERI0_PMS_READ_REE1_PSRAM_MON : R/W; bitpos: [2]; default: 0;
+ *  Configures psram_mon registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_PSRAM_MON    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_PSRAM_MON_M  (HP_PERI0_PMS_READ_REE1_PSRAM_MON_V << HP_PERI0_PMS_READ_REE1_PSRAM_MON_S)
+#define HP_PERI0_PMS_READ_REE1_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_PSRAM_MON_S  2
+/** HP_PERI0_PMS_READ_REE2_PSRAM_MON : R/W; bitpos: [3]; default: 0;
+ *  Configures psram_mon registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_PSRAM_MON    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_PSRAM_MON_M  (HP_PERI0_PMS_READ_REE2_PSRAM_MON_V << HP_PERI0_PMS_READ_REE2_PSRAM_MON_S)
+#define HP_PERI0_PMS_READ_REE2_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_PSRAM_MON_S  3
+/** HP_PERI0_PMS_WRITE_TEE_PSRAM_MON : R/W; bitpos: [4]; default: 1;
+ *  Configures psram_mon registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_PSRAM_MON    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_PSRAM_MON_M  (HP_PERI0_PMS_WRITE_TEE_PSRAM_MON_V << HP_PERI0_PMS_WRITE_TEE_PSRAM_MON_S)
+#define HP_PERI0_PMS_WRITE_TEE_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_PSRAM_MON_S  4
+/** HP_PERI0_PMS_WRITE_REE0_PSRAM_MON : R/W; bitpos: [5]; default: 0;
+ *  Configures psram_mon registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_PSRAM_MON    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_PSRAM_MON_M  (HP_PERI0_PMS_WRITE_REE0_PSRAM_MON_V << HP_PERI0_PMS_WRITE_REE0_PSRAM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE0_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_PSRAM_MON_S  5
+/** HP_PERI0_PMS_WRITE_REE1_PSRAM_MON : R/W; bitpos: [6]; default: 0;
+ *  Configures psram_mon registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_PSRAM_MON    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_PSRAM_MON_M  (HP_PERI0_PMS_WRITE_REE1_PSRAM_MON_V << HP_PERI0_PMS_WRITE_REE1_PSRAM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE1_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_PSRAM_MON_S  6
+/** HP_PERI0_PMS_WRITE_REE2_PSRAM_MON : R/W; bitpos: [7]; default: 0;
+ *  Configures psram_mon registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_PSRAM_MON    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_PSRAM_MON_M  (HP_PERI0_PMS_WRITE_REE2_PSRAM_MON_V << HP_PERI0_PMS_WRITE_REE2_PSRAM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE2_PSRAM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_PSRAM_MON_S  7
+/** HP_PERI0_PMS_PSRAM_MON_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock psram_mon peri_apm configuration
+ */
+#define HP_PERI0_PMS_PSRAM_MON_LOCK    (BIT(8))
+#define HP_PERI0_PMS_PSRAM_MON_LOCK_M  (HP_PERI0_PMS_PSRAM_MON_LOCK_V << HP_PERI0_PMS_PSRAM_MON_LOCK_S)
+#define HP_PERI0_PMS_PSRAM_MON_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_PSRAM_MON_LOCK_S  8
+
+/** HP_PERI0_PMS_TCM_MON_CTRL_REG register
+ *  tcm_mon read/write control register
+ */
+#define HP_PERI0_PMS_TCM_MON_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x10)
+/** HP_PERI0_PMS_READ_TEE_TCM_MON : R/W; bitpos: [0]; default: 1;
+ *  Configures tcm_mon registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_TCM_MON    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_TCM_MON_M  (HP_PERI0_PMS_READ_TEE_TCM_MON_V << HP_PERI0_PMS_READ_TEE_TCM_MON_S)
+#define HP_PERI0_PMS_READ_TEE_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_TCM_MON_S  0
+/** HP_PERI0_PMS_READ_REE0_TCM_MON : R/W; bitpos: [1]; default: 0;
+ *  Configures tcm_mon registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_TCM_MON    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_TCM_MON_M  (HP_PERI0_PMS_READ_REE0_TCM_MON_V << HP_PERI0_PMS_READ_REE0_TCM_MON_S)
+#define HP_PERI0_PMS_READ_REE0_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_TCM_MON_S  1
+/** HP_PERI0_PMS_READ_REE1_TCM_MON : R/W; bitpos: [2]; default: 0;
+ *  Configures tcm_mon registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_TCM_MON    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_TCM_MON_M  (HP_PERI0_PMS_READ_REE1_TCM_MON_V << HP_PERI0_PMS_READ_REE1_TCM_MON_S)
+#define HP_PERI0_PMS_READ_REE1_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_TCM_MON_S  2
+/** HP_PERI0_PMS_READ_REE2_TCM_MON : R/W; bitpos: [3]; default: 0;
+ *  Configures tcm_mon registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_TCM_MON    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_TCM_MON_M  (HP_PERI0_PMS_READ_REE2_TCM_MON_V << HP_PERI0_PMS_READ_REE2_TCM_MON_S)
+#define HP_PERI0_PMS_READ_REE2_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_TCM_MON_S  3
+/** HP_PERI0_PMS_WRITE_TEE_TCM_MON : R/W; bitpos: [4]; default: 1;
+ *  Configures tcm_mon registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_TCM_MON    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_TCM_MON_M  (HP_PERI0_PMS_WRITE_TEE_TCM_MON_V << HP_PERI0_PMS_WRITE_TEE_TCM_MON_S)
+#define HP_PERI0_PMS_WRITE_TEE_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_TCM_MON_S  4
+/** HP_PERI0_PMS_WRITE_REE0_TCM_MON : R/W; bitpos: [5]; default: 0;
+ *  Configures tcm_mon registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_TCM_MON    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_TCM_MON_M  (HP_PERI0_PMS_WRITE_REE0_TCM_MON_V << HP_PERI0_PMS_WRITE_REE0_TCM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE0_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_TCM_MON_S  5
+/** HP_PERI0_PMS_WRITE_REE1_TCM_MON : R/W; bitpos: [6]; default: 0;
+ *  Configures tcm_mon registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_TCM_MON    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_TCM_MON_M  (HP_PERI0_PMS_WRITE_REE1_TCM_MON_V << HP_PERI0_PMS_WRITE_REE1_TCM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE1_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_TCM_MON_S  6
+/** HP_PERI0_PMS_WRITE_REE2_TCM_MON : R/W; bitpos: [7]; default: 0;
+ *  Configures tcm_mon registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_TCM_MON    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_TCM_MON_M  (HP_PERI0_PMS_WRITE_REE2_TCM_MON_V << HP_PERI0_PMS_WRITE_REE2_TCM_MON_S)
+#define HP_PERI0_PMS_WRITE_REE2_TCM_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_TCM_MON_S  7
+/** HP_PERI0_PMS_TCM_MON_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock tcm_mon peri_apm configuration
+ */
+#define HP_PERI0_PMS_TCM_MON_LOCK    (BIT(8))
+#define HP_PERI0_PMS_TCM_MON_LOCK_M  (HP_PERI0_PMS_TCM_MON_LOCK_V << HP_PERI0_PMS_TCM_MON_LOCK_S)
+#define HP_PERI0_PMS_TCM_MON_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_TCM_MON_LOCK_S  8
+
+/** HP_PERI0_PMS_CACHE_CTRL_REG register
+ *  cache read/write control register
+ */
+#define HP_PERI0_PMS_CACHE_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x14)
+/** HP_PERI0_PMS_READ_TEE_CACHE : R/W; bitpos: [0]; default: 1;
+ *  Configures cache registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_CACHE    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_CACHE_M  (HP_PERI0_PMS_READ_TEE_CACHE_V << HP_PERI0_PMS_READ_TEE_CACHE_S)
+#define HP_PERI0_PMS_READ_TEE_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_CACHE_S  0
+/** HP_PERI0_PMS_READ_REE0_CACHE : R/W; bitpos: [1]; default: 0;
+ *  Configures cache registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_CACHE    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_CACHE_M  (HP_PERI0_PMS_READ_REE0_CACHE_V << HP_PERI0_PMS_READ_REE0_CACHE_S)
+#define HP_PERI0_PMS_READ_REE0_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_CACHE_S  1
+/** HP_PERI0_PMS_READ_REE1_CACHE : R/W; bitpos: [2]; default: 0;
+ *  Configures cache registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_CACHE    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_CACHE_M  (HP_PERI0_PMS_READ_REE1_CACHE_V << HP_PERI0_PMS_READ_REE1_CACHE_S)
+#define HP_PERI0_PMS_READ_REE1_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_CACHE_S  2
+/** HP_PERI0_PMS_READ_REE2_CACHE : R/W; bitpos: [3]; default: 0;
+ *  Configures cache registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_CACHE    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_CACHE_M  (HP_PERI0_PMS_READ_REE2_CACHE_V << HP_PERI0_PMS_READ_REE2_CACHE_S)
+#define HP_PERI0_PMS_READ_REE2_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_CACHE_S  3
+/** HP_PERI0_PMS_WRITE_TEE_CACHE : R/W; bitpos: [4]; default: 1;
+ *  Configures cache registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_CACHE    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_CACHE_M  (HP_PERI0_PMS_WRITE_TEE_CACHE_V << HP_PERI0_PMS_WRITE_TEE_CACHE_S)
+#define HP_PERI0_PMS_WRITE_TEE_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_CACHE_S  4
+/** HP_PERI0_PMS_WRITE_REE0_CACHE : R/W; bitpos: [5]; default: 0;
+ *  Configures cache registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_CACHE    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_CACHE_M  (HP_PERI0_PMS_WRITE_REE0_CACHE_V << HP_PERI0_PMS_WRITE_REE0_CACHE_S)
+#define HP_PERI0_PMS_WRITE_REE0_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_CACHE_S  5
+/** HP_PERI0_PMS_WRITE_REE1_CACHE : R/W; bitpos: [6]; default: 0;
+ *  Configures cache registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_CACHE    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_CACHE_M  (HP_PERI0_PMS_WRITE_REE1_CACHE_V << HP_PERI0_PMS_WRITE_REE1_CACHE_S)
+#define HP_PERI0_PMS_WRITE_REE1_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_CACHE_S  6
+/** HP_PERI0_PMS_WRITE_REE2_CACHE : R/W; bitpos: [7]; default: 0;
+ *  Configures cache registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_CACHE    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_CACHE_M  (HP_PERI0_PMS_WRITE_REE2_CACHE_V << HP_PERI0_PMS_WRITE_REE2_CACHE_S)
+#define HP_PERI0_PMS_WRITE_REE2_CACHE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_CACHE_S  7
+/** HP_PERI0_PMS_CACHE_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock cache peri_apm configuration
+ */
+#define HP_PERI0_PMS_CACHE_LOCK    (BIT(8))
+#define HP_PERI0_PMS_CACHE_LOCK_M  (HP_PERI0_PMS_CACHE_LOCK_V << HP_PERI0_PMS_CACHE_LOCK_S)
+#define HP_PERI0_PMS_CACHE_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_CACHE_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_USBOTG_CORE_CTRL_REG register
+ *  hp_usbotg_core read/write control register
+ */
+#define HP_PERI0_PMS_HP_USBOTG_CORE_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x18)
+/** HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_usbotg_core registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE_M  (HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE_V << HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_USBOTG_CORE_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_usbotg_core registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE_M  (HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE_V << HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_USBOTG_CORE_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_usbotg_core registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE_M  (HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE_V << HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_USBOTG_CORE_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_usbotg_core registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE_M  (HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE_V << HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_USBOTG_CORE_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_usbotg_core registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE_M  (HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE_V << HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_USBOTG_CORE_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_usbotg_core registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE_M  (HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE_V << HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_USBOTG_CORE_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_usbotg_core registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE_M  (HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE_V << HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_USBOTG_CORE_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_usbotg_core registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE_M  (HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE_V << HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_USBOTG_CORE_S  7
+/** HP_PERI0_PMS_HP_USBOTG_CORE_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_usbotg_core peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_USBOTG_CORE_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_USBOTG_CORE_LOCK_M  (HP_PERI0_PMS_HP_USBOTG_CORE_LOCK_V << HP_PERI0_PMS_HP_USBOTG_CORE_LOCK_S)
+#define HP_PERI0_PMS_HP_USBOTG_CORE_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_USBOTG_CORE_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_REGDMA_CTRL_REG register
+ *  hp_regdma read/write control register
+ */
+#define HP_PERI0_PMS_HP_REGDMA_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x1c)
+/** HP_PERI0_PMS_READ_TEE_HP_REGDMA : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_regdma registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_REGDMA    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_REGDMA_M  (HP_PERI0_PMS_READ_TEE_HP_REGDMA_V << HP_PERI0_PMS_READ_TEE_HP_REGDMA_S)
+#define HP_PERI0_PMS_READ_TEE_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_REGDMA_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_REGDMA : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_regdma registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_REGDMA    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_REGDMA_M  (HP_PERI0_PMS_READ_REE0_HP_REGDMA_V << HP_PERI0_PMS_READ_REE0_HP_REGDMA_S)
+#define HP_PERI0_PMS_READ_REE0_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_REGDMA_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_REGDMA : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_regdma registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_REGDMA    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_REGDMA_M  (HP_PERI0_PMS_READ_REE1_HP_REGDMA_V << HP_PERI0_PMS_READ_REE1_HP_REGDMA_S)
+#define HP_PERI0_PMS_READ_REE1_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_REGDMA_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_REGDMA : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_regdma registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_REGDMA    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_REGDMA_M  (HP_PERI0_PMS_READ_REE2_HP_REGDMA_V << HP_PERI0_PMS_READ_REE2_HP_REGDMA_S)
+#define HP_PERI0_PMS_READ_REE2_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_REGDMA_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_REGDMA : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_regdma registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_REGDMA    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_REGDMA_M  (HP_PERI0_PMS_WRITE_TEE_HP_REGDMA_V << HP_PERI0_PMS_WRITE_TEE_HP_REGDMA_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_REGDMA_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_REGDMA : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_regdma registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_REGDMA    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_REGDMA_M  (HP_PERI0_PMS_WRITE_REE0_HP_REGDMA_V << HP_PERI0_PMS_WRITE_REE0_HP_REGDMA_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_REGDMA_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_REGDMA : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_regdma registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_REGDMA    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_REGDMA_M  (HP_PERI0_PMS_WRITE_REE1_HP_REGDMA_V << HP_PERI0_PMS_WRITE_REE1_HP_REGDMA_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_REGDMA_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_REGDMA : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_regdma registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_REGDMA    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_REGDMA_M  (HP_PERI0_PMS_WRITE_REE2_HP_REGDMA_V << HP_PERI0_PMS_WRITE_REE2_HP_REGDMA_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_REGDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_REGDMA_S  7
+/** HP_PERI0_PMS_HP_REGDMA_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_regdma peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_REGDMA_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_REGDMA_LOCK_M  (HP_PERI0_PMS_HP_REGDMA_LOCK_V << HP_PERI0_PMS_HP_REGDMA_LOCK_S)
+#define HP_PERI0_PMS_HP_REGDMA_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_REGDMA_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_SDMMC_CTRL_REG register
+ *  hp_sdmmc read/write control register
+ */
+#define HP_PERI0_PMS_HP_SDMMC_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x20)
+/** HP_PERI0_PMS_READ_TEE_HP_SDMMC : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_sdmmc registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_SDMMC    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_SDMMC_M  (HP_PERI0_PMS_READ_TEE_HP_SDMMC_V << HP_PERI0_PMS_READ_TEE_HP_SDMMC_S)
+#define HP_PERI0_PMS_READ_TEE_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_SDMMC_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_SDMMC : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_sdmmc registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_SDMMC    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_SDMMC_M  (HP_PERI0_PMS_READ_REE0_HP_SDMMC_V << HP_PERI0_PMS_READ_REE0_HP_SDMMC_S)
+#define HP_PERI0_PMS_READ_REE0_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_SDMMC_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_SDMMC : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_sdmmc registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_SDMMC    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_SDMMC_M  (HP_PERI0_PMS_READ_REE1_HP_SDMMC_V << HP_PERI0_PMS_READ_REE1_HP_SDMMC_S)
+#define HP_PERI0_PMS_READ_REE1_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_SDMMC_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_SDMMC : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_sdmmc registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_SDMMC    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_SDMMC_M  (HP_PERI0_PMS_READ_REE2_HP_SDMMC_V << HP_PERI0_PMS_READ_REE2_HP_SDMMC_S)
+#define HP_PERI0_PMS_READ_REE2_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_SDMMC_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_SDMMC : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_sdmmc registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_SDMMC    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_SDMMC_M  (HP_PERI0_PMS_WRITE_TEE_HP_SDMMC_V << HP_PERI0_PMS_WRITE_TEE_HP_SDMMC_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_SDMMC_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_SDMMC : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_sdmmc registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_SDMMC    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_SDMMC_M  (HP_PERI0_PMS_WRITE_REE0_HP_SDMMC_V << HP_PERI0_PMS_WRITE_REE0_HP_SDMMC_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_SDMMC_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_SDMMC : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_sdmmc registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_SDMMC    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_SDMMC_M  (HP_PERI0_PMS_WRITE_REE1_HP_SDMMC_V << HP_PERI0_PMS_WRITE_REE1_HP_SDMMC_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_SDMMC_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_SDMMC : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_sdmmc registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_SDMMC    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_SDMMC_M  (HP_PERI0_PMS_WRITE_REE2_HP_SDMMC_V << HP_PERI0_PMS_WRITE_REE2_HP_SDMMC_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_SDMMC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_SDMMC_S  7
+/** HP_PERI0_PMS_HP_SDMMC_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_sdmmc peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_SDMMC_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_SDMMC_LOCK_M  (HP_PERI0_PMS_HP_SDMMC_LOCK_V << HP_PERI0_PMS_HP_SDMMC_LOCK_S)
+#define HP_PERI0_PMS_HP_SDMMC_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_SDMMC_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_AHB_PDMA_CTRL_REG register
+ *  hp_ahb_pdma read/write control register
+ */
+#define HP_PERI0_PMS_HP_AHB_PDMA_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x24)
+/** HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_ahb_pdma registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA_M  (HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA_V << HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_AHB_PDMA_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_ahb_pdma registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA_M  (HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA_V << HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_AHB_PDMA_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_ahb_pdma registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA_M  (HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA_V << HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_AHB_PDMA_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_ahb_pdma registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA_M  (HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA_V << HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_AHB_PDMA_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_ahb_pdma registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA_M  (HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA_V << HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_AHB_PDMA_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_ahb_pdma registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA_M  (HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA_V << HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_AHB_PDMA_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_ahb_pdma registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA_M  (HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA_V << HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_AHB_PDMA_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_ahb_pdma registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA_M  (HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA_V << HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_AHB_PDMA_S  7
+/** HP_PERI0_PMS_HP_AHB_PDMA_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_ahb_pdma peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_AHB_PDMA_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_AHB_PDMA_LOCK_M  (HP_PERI0_PMS_HP_AHB_PDMA_LOCK_V << HP_PERI0_PMS_HP_AHB_PDMA_LOCK_S)
+#define HP_PERI0_PMS_HP_AHB_PDMA_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_AHB_PDMA_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_JPEG_CTRL_REG register
+ *  hp_jpeg read/write control register
+ */
+#define HP_PERI0_PMS_HP_JPEG_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x28)
+/** HP_PERI0_PMS_READ_TEE_HP_JPEG : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_jpeg registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_JPEG    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_JPEG_M  (HP_PERI0_PMS_READ_TEE_HP_JPEG_V << HP_PERI0_PMS_READ_TEE_HP_JPEG_S)
+#define HP_PERI0_PMS_READ_TEE_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_JPEG_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_JPEG : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_jpeg registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_JPEG    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_JPEG_M  (HP_PERI0_PMS_READ_REE0_HP_JPEG_V << HP_PERI0_PMS_READ_REE0_HP_JPEG_S)
+#define HP_PERI0_PMS_READ_REE0_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_JPEG_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_JPEG : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_jpeg registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_JPEG    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_JPEG_M  (HP_PERI0_PMS_READ_REE1_HP_JPEG_V << HP_PERI0_PMS_READ_REE1_HP_JPEG_S)
+#define HP_PERI0_PMS_READ_REE1_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_JPEG_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_JPEG : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_jpeg registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_JPEG    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_JPEG_M  (HP_PERI0_PMS_READ_REE2_HP_JPEG_V << HP_PERI0_PMS_READ_REE2_HP_JPEG_S)
+#define HP_PERI0_PMS_READ_REE2_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_JPEG_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_JPEG : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_jpeg registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_JPEG    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_JPEG_M  (HP_PERI0_PMS_WRITE_TEE_HP_JPEG_V << HP_PERI0_PMS_WRITE_TEE_HP_JPEG_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_JPEG_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_JPEG : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_jpeg registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_JPEG    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_JPEG_M  (HP_PERI0_PMS_WRITE_REE0_HP_JPEG_V << HP_PERI0_PMS_WRITE_REE0_HP_JPEG_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_JPEG_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_JPEG : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_jpeg registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_JPEG    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_JPEG_M  (HP_PERI0_PMS_WRITE_REE1_HP_JPEG_V << HP_PERI0_PMS_WRITE_REE1_HP_JPEG_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_JPEG_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_JPEG : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_jpeg registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_JPEG    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_JPEG_M  (HP_PERI0_PMS_WRITE_REE2_HP_JPEG_V << HP_PERI0_PMS_WRITE_REE2_HP_JPEG_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_JPEG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_JPEG_S  7
+/** HP_PERI0_PMS_HP_JPEG_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_jpeg peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_JPEG_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_JPEG_LOCK_M  (HP_PERI0_PMS_HP_JPEG_LOCK_V << HP_PERI0_PMS_HP_JPEG_LOCK_S)
+#define HP_PERI0_PMS_HP_JPEG_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_JPEG_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_PPA_CTRL_REG register
+ *  hp_ppa read/write control register
+ */
+#define HP_PERI0_PMS_HP_PPA_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x2c)
+/** HP_PERI0_PMS_READ_TEE_HP_PPA : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_ppa registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_PPA    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_PPA_M  (HP_PERI0_PMS_READ_TEE_HP_PPA_V << HP_PERI0_PMS_READ_TEE_HP_PPA_S)
+#define HP_PERI0_PMS_READ_TEE_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_PPA_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_PPA : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_ppa registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_PPA    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_PPA_M  (HP_PERI0_PMS_READ_REE0_HP_PPA_V << HP_PERI0_PMS_READ_REE0_HP_PPA_S)
+#define HP_PERI0_PMS_READ_REE0_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_PPA_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_PPA : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_ppa registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_PPA    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_PPA_M  (HP_PERI0_PMS_READ_REE1_HP_PPA_V << HP_PERI0_PMS_READ_REE1_HP_PPA_S)
+#define HP_PERI0_PMS_READ_REE1_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_PPA_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_PPA : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_ppa registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_PPA    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_PPA_M  (HP_PERI0_PMS_READ_REE2_HP_PPA_V << HP_PERI0_PMS_READ_REE2_HP_PPA_S)
+#define HP_PERI0_PMS_READ_REE2_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_PPA_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_PPA : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_ppa registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_PPA    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_PPA_M  (HP_PERI0_PMS_WRITE_TEE_HP_PPA_V << HP_PERI0_PMS_WRITE_TEE_HP_PPA_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_PPA_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_PPA : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_ppa registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_PPA    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_PPA_M  (HP_PERI0_PMS_WRITE_REE0_HP_PPA_V << HP_PERI0_PMS_WRITE_REE0_HP_PPA_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_PPA_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_PPA : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_ppa registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_PPA    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_PPA_M  (HP_PERI0_PMS_WRITE_REE1_HP_PPA_V << HP_PERI0_PMS_WRITE_REE1_HP_PPA_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_PPA_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_PPA : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_ppa registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_PPA    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_PPA_M  (HP_PERI0_PMS_WRITE_REE2_HP_PPA_V << HP_PERI0_PMS_WRITE_REE2_HP_PPA_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_PPA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_PPA_S  7
+/** HP_PERI0_PMS_HP_PPA_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_ppa peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_PPA_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_PPA_LOCK_M  (HP_PERI0_PMS_HP_PPA_LOCK_V << HP_PERI0_PMS_HP_PPA_LOCK_S)
+#define HP_PERI0_PMS_HP_PPA_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_PPA_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_DMA2D_CTRL_REG register
+ *  hp_dma2d read/write control register
+ */
+#define HP_PERI0_PMS_HP_DMA2D_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x30)
+/** HP_PERI0_PMS_READ_TEE_HP_DMA2D : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_dma2d registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_DMA2D    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_DMA2D_M  (HP_PERI0_PMS_READ_TEE_HP_DMA2D_V << HP_PERI0_PMS_READ_TEE_HP_DMA2D_S)
+#define HP_PERI0_PMS_READ_TEE_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_DMA2D_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_DMA2D : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_dma2d registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_DMA2D    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_DMA2D_M  (HP_PERI0_PMS_READ_REE0_HP_DMA2D_V << HP_PERI0_PMS_READ_REE0_HP_DMA2D_S)
+#define HP_PERI0_PMS_READ_REE0_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_DMA2D_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_DMA2D : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_dma2d registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_DMA2D    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_DMA2D_M  (HP_PERI0_PMS_READ_REE1_HP_DMA2D_V << HP_PERI0_PMS_READ_REE1_HP_DMA2D_S)
+#define HP_PERI0_PMS_READ_REE1_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_DMA2D_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_DMA2D : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_dma2d registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_DMA2D    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_DMA2D_M  (HP_PERI0_PMS_READ_REE2_HP_DMA2D_V << HP_PERI0_PMS_READ_REE2_HP_DMA2D_S)
+#define HP_PERI0_PMS_READ_REE2_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_DMA2D_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_DMA2D : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_dma2d registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_DMA2D    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_DMA2D_M  (HP_PERI0_PMS_WRITE_TEE_HP_DMA2D_V << HP_PERI0_PMS_WRITE_TEE_HP_DMA2D_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_DMA2D_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_DMA2D : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_dma2d registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_DMA2D    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_DMA2D_M  (HP_PERI0_PMS_WRITE_REE0_HP_DMA2D_V << HP_PERI0_PMS_WRITE_REE0_HP_DMA2D_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_DMA2D_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_DMA2D : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_dma2d registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_DMA2D    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_DMA2D_M  (HP_PERI0_PMS_WRITE_REE1_HP_DMA2D_V << HP_PERI0_PMS_WRITE_REE1_HP_DMA2D_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_DMA2D_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_DMA2D : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_dma2d registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_DMA2D    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_DMA2D_M  (HP_PERI0_PMS_WRITE_REE2_HP_DMA2D_V << HP_PERI0_PMS_WRITE_REE2_HP_DMA2D_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_DMA2D_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_DMA2D_S  7
+/** HP_PERI0_PMS_HP_DMA2D_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_dma2d peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_DMA2D_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_DMA2D_LOCK_M  (HP_PERI0_PMS_HP_DMA2D_LOCK_V << HP_PERI0_PMS_HP_DMA2D_LOCK_S)
+#define HP_PERI0_PMS_HP_DMA2D_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_DMA2D_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_AXI_PDMA_CTRL_REG register
+ *  hp_axi_pdma read/write control register
+ */
+#define HP_PERI0_PMS_HP_AXI_PDMA_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x34)
+/** HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_axi_pdma registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA_M  (HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA_V << HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_PDMA_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_axi_pdma registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA_M  (HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA_V << HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_PDMA_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_axi_pdma registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA_M  (HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA_V << HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_PDMA_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_axi_pdma registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA_M  (HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA_V << HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_PDMA_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_axi_pdma registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA_M  (HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA_V << HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_PDMA_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_axi_pdma registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA_M  (HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA_V << HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_PDMA_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_axi_pdma registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA_M  (HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA_V << HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_PDMA_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_axi_pdma registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA_M  (HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA_V << HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_PDMA_S  7
+/** HP_PERI0_PMS_HP_AXI_PDMA_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_axi_pdma peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_AXI_PDMA_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_AXI_PDMA_LOCK_M  (HP_PERI0_PMS_HP_AXI_PDMA_LOCK_V << HP_PERI0_PMS_HP_AXI_PDMA_LOCK_S)
+#define HP_PERI0_PMS_HP_AXI_PDMA_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_AXI_PDMA_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_GMAC_CTRL_REG register
+ *  hp_gmac read/write control register
+ */
+#define HP_PERI0_PMS_HP_GMAC_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x38)
+/** HP_PERI0_PMS_READ_TEE_HP_GMAC : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_gmac registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_GMAC    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_GMAC_M  (HP_PERI0_PMS_READ_TEE_HP_GMAC_V << HP_PERI0_PMS_READ_TEE_HP_GMAC_S)
+#define HP_PERI0_PMS_READ_TEE_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_GMAC_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_GMAC : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_gmac registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_GMAC    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_GMAC_M  (HP_PERI0_PMS_READ_REE0_HP_GMAC_V << HP_PERI0_PMS_READ_REE0_HP_GMAC_S)
+#define HP_PERI0_PMS_READ_REE0_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_GMAC_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_GMAC : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_gmac registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_GMAC    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_GMAC_M  (HP_PERI0_PMS_READ_REE1_HP_GMAC_V << HP_PERI0_PMS_READ_REE1_HP_GMAC_S)
+#define HP_PERI0_PMS_READ_REE1_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_GMAC_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_GMAC : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_gmac registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_GMAC    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_GMAC_M  (HP_PERI0_PMS_READ_REE2_HP_GMAC_V << HP_PERI0_PMS_READ_REE2_HP_GMAC_S)
+#define HP_PERI0_PMS_READ_REE2_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_GMAC_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_GMAC : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_gmac registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_GMAC    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_GMAC_M  (HP_PERI0_PMS_WRITE_TEE_HP_GMAC_V << HP_PERI0_PMS_WRITE_TEE_HP_GMAC_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_GMAC_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_GMAC : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_gmac registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_GMAC    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_GMAC_M  (HP_PERI0_PMS_WRITE_REE0_HP_GMAC_V << HP_PERI0_PMS_WRITE_REE0_HP_GMAC_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_GMAC_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_GMAC : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_gmac registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_GMAC    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_GMAC_M  (HP_PERI0_PMS_WRITE_REE1_HP_GMAC_V << HP_PERI0_PMS_WRITE_REE1_HP_GMAC_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_GMAC_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_GMAC : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_gmac registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_GMAC    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_GMAC_M  (HP_PERI0_PMS_WRITE_REE2_HP_GMAC_V << HP_PERI0_PMS_WRITE_REE2_HP_GMAC_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_GMAC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_GMAC_S  7
+/** HP_PERI0_PMS_HP_GMAC_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_gmac peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_GMAC_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_GMAC_LOCK_M  (HP_PERI0_PMS_HP_GMAC_LOCK_V << HP_PERI0_PMS_HP_GMAC_LOCK_S)
+#define HP_PERI0_PMS_HP_GMAC_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_GMAC_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_PVT0_CTRL_REG register
+ *  hp_pvt0 read/write control register
+ */
+#define HP_PERI0_PMS_HP_PVT0_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x3c)
+/** HP_PERI0_PMS_READ_TEE_HP_PVT0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_pvt0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_PVT0    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_PVT0_M  (HP_PERI0_PMS_READ_TEE_HP_PVT0_V << HP_PERI0_PMS_READ_TEE_HP_PVT0_S)
+#define HP_PERI0_PMS_READ_TEE_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_PVT0_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_PVT0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_pvt0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_PVT0    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_PVT0_M  (HP_PERI0_PMS_READ_REE0_HP_PVT0_V << HP_PERI0_PMS_READ_REE0_HP_PVT0_S)
+#define HP_PERI0_PMS_READ_REE0_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_PVT0_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_PVT0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_pvt0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_PVT0    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_PVT0_M  (HP_PERI0_PMS_READ_REE1_HP_PVT0_V << HP_PERI0_PMS_READ_REE1_HP_PVT0_S)
+#define HP_PERI0_PMS_READ_REE1_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_PVT0_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_PVT0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_pvt0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_PVT0    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_PVT0_M  (HP_PERI0_PMS_READ_REE2_HP_PVT0_V << HP_PERI0_PMS_READ_REE2_HP_PVT0_S)
+#define HP_PERI0_PMS_READ_REE2_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_PVT0_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_PVT0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_pvt0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_PVT0    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_PVT0_M  (HP_PERI0_PMS_WRITE_TEE_HP_PVT0_V << HP_PERI0_PMS_WRITE_TEE_HP_PVT0_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_PVT0_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_PVT0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_pvt0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_PVT0    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_PVT0_M  (HP_PERI0_PMS_WRITE_REE0_HP_PVT0_V << HP_PERI0_PMS_WRITE_REE0_HP_PVT0_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_PVT0_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_PVT0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_pvt0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_PVT0    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_PVT0_M  (HP_PERI0_PMS_WRITE_REE1_HP_PVT0_V << HP_PERI0_PMS_WRITE_REE1_HP_PVT0_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_PVT0_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_PVT0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_pvt0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_PVT0    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_PVT0_M  (HP_PERI0_PMS_WRITE_REE2_HP_PVT0_V << HP_PERI0_PMS_WRITE_REE2_HP_PVT0_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_PVT0_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_PVT0_S  7
+/** HP_PERI0_PMS_HP_PVT0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_pvt0 peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_PVT0_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_PVT0_LOCK_M  (HP_PERI0_PMS_HP_PVT0_LOCK_V << HP_PERI0_PMS_HP_PVT0_LOCK_S)
+#define HP_PERI0_PMS_HP_PVT0_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_PVT0_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_RMT_CTRL_REG register
+ *  hp_rmt read/write control register
+ */
+#define HP_PERI0_PMS_HP_RMT_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x40)
+/** HP_PERI0_PMS_READ_TEE_HP_RMT : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_rmt registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_RMT    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_RMT_M  (HP_PERI0_PMS_READ_TEE_HP_RMT_V << HP_PERI0_PMS_READ_TEE_HP_RMT_S)
+#define HP_PERI0_PMS_READ_TEE_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_RMT_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_RMT : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_rmt registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_RMT    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_RMT_M  (HP_PERI0_PMS_READ_REE0_HP_RMT_V << HP_PERI0_PMS_READ_REE0_HP_RMT_S)
+#define HP_PERI0_PMS_READ_REE0_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_RMT_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_RMT : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_rmt registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_RMT    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_RMT_M  (HP_PERI0_PMS_READ_REE1_HP_RMT_V << HP_PERI0_PMS_READ_REE1_HP_RMT_S)
+#define HP_PERI0_PMS_READ_REE1_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_RMT_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_RMT : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_rmt registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_RMT    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_RMT_M  (HP_PERI0_PMS_READ_REE2_HP_RMT_V << HP_PERI0_PMS_READ_REE2_HP_RMT_S)
+#define HP_PERI0_PMS_READ_REE2_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_RMT_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_RMT : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_rmt registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_RMT    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_RMT_M  (HP_PERI0_PMS_WRITE_TEE_HP_RMT_V << HP_PERI0_PMS_WRITE_TEE_HP_RMT_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_RMT_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_RMT : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_rmt registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_RMT    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_RMT_M  (HP_PERI0_PMS_WRITE_REE0_HP_RMT_V << HP_PERI0_PMS_WRITE_REE0_HP_RMT_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_RMT_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_RMT : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_rmt registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_RMT    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_RMT_M  (HP_PERI0_PMS_WRITE_REE1_HP_RMT_V << HP_PERI0_PMS_WRITE_REE1_HP_RMT_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_RMT_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_RMT : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_rmt registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_RMT    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_RMT_M  (HP_PERI0_PMS_WRITE_REE2_HP_RMT_V << HP_PERI0_PMS_WRITE_REE2_HP_RMT_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_RMT_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_RMT_S  7
+/** HP_PERI0_PMS_HP_RMT_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_rmt peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_RMT_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_RMT_LOCK_M  (HP_PERI0_PMS_HP_RMT_LOCK_V << HP_PERI0_PMS_HP_RMT_LOCK_S)
+#define HP_PERI0_PMS_HP_RMT_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_RMT_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_BITSRAMBLER_CTRL_REG register
+ *  hp_bitsrambler read/write control register
+ */
+#define HP_PERI0_PMS_HP_BITSRAMBLER_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x44)
+/** HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_bitsrambler registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_M  (HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_BITSRAMBLER_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_bitsrambler registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_M  (HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_BITSRAMBLER_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_bitsrambler registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_M  (HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_BITSRAMBLER_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_bitsrambler registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_M  (HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_V << HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_BITSRAMBLER_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_bitsrambler registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_M  (HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_BITSRAMBLER_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_bitsrambler registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_M  (HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_BITSRAMBLER_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_bitsrambler registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_M  (HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_BITSRAMBLER_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_bitsrambler registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_M  (HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_V << HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_BITSRAMBLER_S  7
+/** HP_PERI0_PMS_HP_BITSRAMBLER_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_bitsrambler peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_M  (HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_V << HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_S)
+#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_BITSRAMBLER_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_ASRC_CTRL_REG register
+ *  hp_asrc read/write control register
+ */
+#define HP_PERI0_PMS_HP_ASRC_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x48)
+/** HP_PERI0_PMS_READ_TEE_HP_ASRC : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_asrc registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_ASRC    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_ASRC_M  (HP_PERI0_PMS_READ_TEE_HP_ASRC_V << HP_PERI0_PMS_READ_TEE_HP_ASRC_S)
+#define HP_PERI0_PMS_READ_TEE_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_ASRC_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_ASRC : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_asrc registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_ASRC    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_ASRC_M  (HP_PERI0_PMS_READ_REE0_HP_ASRC_V << HP_PERI0_PMS_READ_REE0_HP_ASRC_S)
+#define HP_PERI0_PMS_READ_REE0_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_ASRC_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_ASRC : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_asrc registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_ASRC    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_ASRC_M  (HP_PERI0_PMS_READ_REE1_HP_ASRC_V << HP_PERI0_PMS_READ_REE1_HP_ASRC_S)
+#define HP_PERI0_PMS_READ_REE1_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_ASRC_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_ASRC : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_asrc registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_ASRC    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_ASRC_M  (HP_PERI0_PMS_READ_REE2_HP_ASRC_V << HP_PERI0_PMS_READ_REE2_HP_ASRC_S)
+#define HP_PERI0_PMS_READ_REE2_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_ASRC_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_ASRC : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_asrc registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_ASRC    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_ASRC_M  (HP_PERI0_PMS_WRITE_TEE_HP_ASRC_V << HP_PERI0_PMS_WRITE_TEE_HP_ASRC_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_ASRC_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_ASRC : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_asrc registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_ASRC    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_ASRC_M  (HP_PERI0_PMS_WRITE_REE0_HP_ASRC_V << HP_PERI0_PMS_WRITE_REE0_HP_ASRC_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_ASRC_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_ASRC : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_asrc registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_ASRC    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_ASRC_M  (HP_PERI0_PMS_WRITE_REE1_HP_ASRC_V << HP_PERI0_PMS_WRITE_REE1_HP_ASRC_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_ASRC_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_ASRC : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_asrc registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_ASRC    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_ASRC_M  (HP_PERI0_PMS_WRITE_REE2_HP_ASRC_V << HP_PERI0_PMS_WRITE_REE2_HP_ASRC_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_ASRC_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_ASRC_S  7
+/** HP_PERI0_PMS_HP_ASRC_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_asrc peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_ASRC_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_ASRC_LOCK_M  (HP_PERI0_PMS_HP_ASRC_LOCK_V << HP_PERI0_PMS_HP_ASRC_LOCK_S)
+#define HP_PERI0_PMS_HP_ASRC_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_ASRC_LOCK_S  8
+
+/** HP_PERI0_PMS_CNNT_SYS_REG_CTRL_REG register
+ *  cnnt_sys_reg read/write control register
+ */
+#define HP_PERI0_PMS_CNNT_SYS_REG_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x4c)
+/** HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG : R/W; bitpos: [0]; default: 1;
+ *  Configures cnnt_sys_reg registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG_M  (HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG_V << HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_CNNT_SYS_REG_S  0
+/** HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG : R/W; bitpos: [1]; default: 0;
+ *  Configures cnnt_sys_reg registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG_M  (HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG_V << HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_CNNT_SYS_REG_S  1
+/** HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG : R/W; bitpos: [2]; default: 0;
+ *  Configures cnnt_sys_reg registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG_M  (HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG_V << HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_CNNT_SYS_REG_S  2
+/** HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG : R/W; bitpos: [3]; default: 0;
+ *  Configures cnnt_sys_reg registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG_M  (HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG_V << HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_CNNT_SYS_REG_S  3
+/** HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG : R/W; bitpos: [4]; default: 1;
+ *  Configures cnnt_sys_reg registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG_M  (HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG_V << HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_CNNT_SYS_REG_S  4
+/** HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG : R/W; bitpos: [5]; default: 0;
+ *  Configures cnnt_sys_reg registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG_M  (HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG_V << HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_CNNT_SYS_REG_S  5
+/** HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG : R/W; bitpos: [6]; default: 0;
+ *  Configures cnnt_sys_reg registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG_M  (HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG_V << HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_CNNT_SYS_REG_S  6
+/** HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG : R/W; bitpos: [7]; default: 0;
+ *  Configures cnnt_sys_reg registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG_M  (HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG_V << HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG_S)
+#define HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_CNNT_SYS_REG_S  7
+/** HP_PERI0_PMS_CNNT_SYS_REG_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock cnnt_sys_reg peri_apm configuration
+ */
+#define HP_PERI0_PMS_CNNT_SYS_REG_LOCK    (BIT(8))
+#define HP_PERI0_PMS_CNNT_SYS_REG_LOCK_M  (HP_PERI0_PMS_CNNT_SYS_REG_LOCK_V << HP_PERI0_PMS_CNNT_SYS_REG_LOCK_S)
+#define HP_PERI0_PMS_CNNT_SYS_REG_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_CNNT_SYS_REG_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_FLASH_CTRL_REG register
+ *  hp_flash read/write control register
+ */
+#define HP_PERI0_PMS_HP_FLASH_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x50)
+/** HP_PERI0_PMS_READ_TEE_HP_FLASH : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_flash registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_FLASH    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_FLASH_M  (HP_PERI0_PMS_READ_TEE_HP_FLASH_V << HP_PERI0_PMS_READ_TEE_HP_FLASH_S)
+#define HP_PERI0_PMS_READ_TEE_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_FLASH_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_FLASH : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_flash registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_FLASH    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_FLASH_M  (HP_PERI0_PMS_READ_REE0_HP_FLASH_V << HP_PERI0_PMS_READ_REE0_HP_FLASH_S)
+#define HP_PERI0_PMS_READ_REE0_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_FLASH_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_FLASH : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_flash registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_FLASH    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_FLASH_M  (HP_PERI0_PMS_READ_REE1_HP_FLASH_V << HP_PERI0_PMS_READ_REE1_HP_FLASH_S)
+#define HP_PERI0_PMS_READ_REE1_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_FLASH_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_FLASH : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_flash registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_FLASH    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_FLASH_M  (HP_PERI0_PMS_READ_REE2_HP_FLASH_V << HP_PERI0_PMS_READ_REE2_HP_FLASH_S)
+#define HP_PERI0_PMS_READ_REE2_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_FLASH_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_FLASH : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_flash registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_FLASH    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_FLASH_M  (HP_PERI0_PMS_WRITE_TEE_HP_FLASH_V << HP_PERI0_PMS_WRITE_TEE_HP_FLASH_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_FLASH_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_FLASH : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_flash registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_FLASH    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_FLASH_M  (HP_PERI0_PMS_WRITE_REE0_HP_FLASH_V << HP_PERI0_PMS_WRITE_REE0_HP_FLASH_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_FLASH_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_FLASH : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_flash registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_FLASH    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_FLASH_M  (HP_PERI0_PMS_WRITE_REE1_HP_FLASH_V << HP_PERI0_PMS_WRITE_REE1_HP_FLASH_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_FLASH_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_FLASH : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_flash registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_FLASH    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_FLASH_M  (HP_PERI0_PMS_WRITE_REE2_HP_FLASH_V << HP_PERI0_PMS_WRITE_REE2_HP_FLASH_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_FLASH_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_FLASH_S  7
+/** HP_PERI0_PMS_HP_FLASH_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_flash peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_FLASH_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_FLASH_LOCK_M  (HP_PERI0_PMS_HP_FLASH_LOCK_V << HP_PERI0_PMS_HP_FLASH_LOCK_S)
+#define HP_PERI0_PMS_HP_FLASH_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_FLASH_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_PSRAM_CTRL_REG register
+ *  hp_psram read/write control register
+ */
+#define HP_PERI0_PMS_HP_PSRAM_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x54)
+/** HP_PERI0_PMS_READ_TEE_HP_PSRAM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_psram registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_PSRAM    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_PSRAM_M  (HP_PERI0_PMS_READ_TEE_HP_PSRAM_V << HP_PERI0_PMS_READ_TEE_HP_PSRAM_S)
+#define HP_PERI0_PMS_READ_TEE_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_PSRAM_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_PSRAM : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_psram registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_PSRAM    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_PSRAM_M  (HP_PERI0_PMS_READ_REE0_HP_PSRAM_V << HP_PERI0_PMS_READ_REE0_HP_PSRAM_S)
+#define HP_PERI0_PMS_READ_REE0_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_PSRAM_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_PSRAM : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_psram registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_PSRAM    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_PSRAM_M  (HP_PERI0_PMS_READ_REE1_HP_PSRAM_V << HP_PERI0_PMS_READ_REE1_HP_PSRAM_S)
+#define HP_PERI0_PMS_READ_REE1_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_PSRAM_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_PSRAM : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_psram registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_PSRAM    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_PSRAM_M  (HP_PERI0_PMS_READ_REE2_HP_PSRAM_V << HP_PERI0_PMS_READ_REE2_HP_PSRAM_S)
+#define HP_PERI0_PMS_READ_REE2_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_PSRAM_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_PSRAM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_psram registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_PSRAM    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_PSRAM_M  (HP_PERI0_PMS_WRITE_TEE_HP_PSRAM_V << HP_PERI0_PMS_WRITE_TEE_HP_PSRAM_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_PSRAM_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_PSRAM : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_psram registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_PSRAM    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_PSRAM_M  (HP_PERI0_PMS_WRITE_REE0_HP_PSRAM_V << HP_PERI0_PMS_WRITE_REE0_HP_PSRAM_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_PSRAM_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_PSRAM : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_psram registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_PSRAM    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_PSRAM_M  (HP_PERI0_PMS_WRITE_REE1_HP_PSRAM_V << HP_PERI0_PMS_WRITE_REE1_HP_PSRAM_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_PSRAM_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_PSRAM : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_psram registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_PSRAM    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_PSRAM_M  (HP_PERI0_PMS_WRITE_REE2_HP_PSRAM_V << HP_PERI0_PMS_WRITE_REE2_HP_PSRAM_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_PSRAM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_PSRAM_S  7
+/** HP_PERI0_PMS_HP_PSRAM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_psram peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_PSRAM_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_PSRAM_LOCK_M  (HP_PERI0_PMS_HP_PSRAM_LOCK_V << HP_PERI0_PMS_HP_PSRAM_LOCK_S)
+#define HP_PERI0_PMS_HP_PSRAM_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_PSRAM_LOCK_S  8
+
+/** HP_PERI0_PMS_TEE_CTRL_REG register
+ *  tee read/write control register
+ */
+#define HP_PERI0_PMS_TEE_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x58)
+/** HP_PERI0_PMS_READ_TEE_TEE : R/W; bitpos: [0]; default: 1;
+ *  Configures tee registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_TEE    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_TEE_M  (HP_PERI0_PMS_READ_TEE_TEE_V << HP_PERI0_PMS_READ_TEE_TEE_S)
+#define HP_PERI0_PMS_READ_TEE_TEE_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_TEE_S  0
+/** HP_PERI0_PMS_READ_REE0_TEE : HRO; bitpos: [1]; default: 0;
+ *  Configures tee registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_TEE    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_TEE_M  (HP_PERI0_PMS_READ_REE0_TEE_V << HP_PERI0_PMS_READ_REE0_TEE_S)
+#define HP_PERI0_PMS_READ_REE0_TEE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_TEE_S  1
+/** HP_PERI0_PMS_READ_REE1_TEE : HRO; bitpos: [2]; default: 0;
+ *  Configures tee registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_TEE    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_TEE_M  (HP_PERI0_PMS_READ_REE1_TEE_V << HP_PERI0_PMS_READ_REE1_TEE_S)
+#define HP_PERI0_PMS_READ_REE1_TEE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_TEE_S  2
+/** HP_PERI0_PMS_READ_REE2_TEE : HRO; bitpos: [3]; default: 0;
+ *  Configures tee registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_TEE    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_TEE_M  (HP_PERI0_PMS_READ_REE2_TEE_V << HP_PERI0_PMS_READ_REE2_TEE_S)
+#define HP_PERI0_PMS_READ_REE2_TEE_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_TEE_S  3
+/** HP_PERI0_PMS_WRITE_TEE_TEE : R/W; bitpos: [4]; default: 1;
+ *  Configures tee registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_TEE    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_TEE_M  (HP_PERI0_PMS_WRITE_TEE_TEE_V << HP_PERI0_PMS_WRITE_TEE_TEE_S)
+#define HP_PERI0_PMS_WRITE_TEE_TEE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_TEE_S  4
+/** HP_PERI0_PMS_WRITE_REE0_TEE : HRO; bitpos: [5]; default: 0;
+ *  Configures tee registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_TEE    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_TEE_M  (HP_PERI0_PMS_WRITE_REE0_TEE_V << HP_PERI0_PMS_WRITE_REE0_TEE_S)
+#define HP_PERI0_PMS_WRITE_REE0_TEE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_TEE_S  5
+/** HP_PERI0_PMS_WRITE_REE1_TEE : HRO; bitpos: [6]; default: 0;
+ *  Configures tee registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_TEE    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_TEE_M  (HP_PERI0_PMS_WRITE_REE1_TEE_V << HP_PERI0_PMS_WRITE_REE1_TEE_S)
+#define HP_PERI0_PMS_WRITE_REE1_TEE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_TEE_S  6
+/** HP_PERI0_PMS_WRITE_REE2_TEE : HRO; bitpos: [7]; default: 0;
+ *  Configures tee registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_TEE    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_TEE_M  (HP_PERI0_PMS_WRITE_REE2_TEE_V << HP_PERI0_PMS_WRITE_REE2_TEE_S)
+#define HP_PERI0_PMS_WRITE_REE2_TEE_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_TEE_S  7
+/** HP_PERI0_PMS_TEE_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock tee peri_apm configuration
+ */
+#define HP_PERI0_PMS_TEE_LOCK    (BIT(8))
+#define HP_PERI0_PMS_TEE_LOCK_M  (HP_PERI0_PMS_TEE_LOCK_V << HP_PERI0_PMS_TEE_LOCK_S)
+#define HP_PERI0_PMS_TEE_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_TEE_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_APM_CTRL_REG register
+ *  hp_apm read/write control register
+ */
+#define HP_PERI0_PMS_HP_APM_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x5c)
+/** HP_PERI0_PMS_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_apm registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_APM    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_APM_M  (HP_PERI0_PMS_READ_TEE_HP_APM_V << HP_PERI0_PMS_READ_TEE_HP_APM_S)
+#define HP_PERI0_PMS_READ_TEE_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_APM_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_APM : HRO; bitpos: [1]; default: 0;
+ *  Configures hp_apm registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_APM    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_APM_M  (HP_PERI0_PMS_READ_REE0_HP_APM_V << HP_PERI0_PMS_READ_REE0_HP_APM_S)
+#define HP_PERI0_PMS_READ_REE0_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_APM_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_APM : HRO; bitpos: [2]; default: 0;
+ *  Configures hp_apm registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_APM    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_APM_M  (HP_PERI0_PMS_READ_REE1_HP_APM_V << HP_PERI0_PMS_READ_REE1_HP_APM_S)
+#define HP_PERI0_PMS_READ_REE1_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_APM_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_APM : HRO; bitpos: [3]; default: 0;
+ *  Configures hp_apm registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_APM    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_APM_M  (HP_PERI0_PMS_READ_REE2_HP_APM_V << HP_PERI0_PMS_READ_REE2_HP_APM_S)
+#define HP_PERI0_PMS_READ_REE2_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_APM_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_APM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_apm registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_APM    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_APM_M  (HP_PERI0_PMS_WRITE_TEE_HP_APM_V << HP_PERI0_PMS_WRITE_TEE_HP_APM_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_APM_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_APM : HRO; bitpos: [5]; default: 0;
+ *  Configures hp_apm registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_APM    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_APM_M  (HP_PERI0_PMS_WRITE_REE0_HP_APM_V << HP_PERI0_PMS_WRITE_REE0_HP_APM_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_APM_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_APM : HRO; bitpos: [6]; default: 0;
+ *  Configures hp_apm registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_APM    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_APM_M  (HP_PERI0_PMS_WRITE_REE1_HP_APM_V << HP_PERI0_PMS_WRITE_REE1_HP_APM_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_APM_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_APM : HRO; bitpos: [7]; default: 0;
+ *  Configures hp_apm registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_APM    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_APM_M  (HP_PERI0_PMS_WRITE_REE2_HP_APM_V << HP_PERI0_PMS_WRITE_REE2_HP_APM_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_APM_S  7
+/** HP_PERI0_PMS_HP_APM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_apm peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_APM_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_APM_LOCK_M  (HP_PERI0_PMS_HP_APM_LOCK_V << HP_PERI0_PMS_HP_APM_LOCK_S)
+#define HP_PERI0_PMS_HP_APM_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_APM_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_MEM_APM_CTRL_REG register
+ *  hp_mem_apm read/write control register
+ */
+#define HP_PERI0_PMS_HP_MEM_APM_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x60)
+/** HP_PERI0_PMS_READ_TEE_HP_MEM_APM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mem_apm registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_MEM_APM    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_MEM_APM_M  (HP_PERI0_PMS_READ_TEE_HP_MEM_APM_V << HP_PERI0_PMS_READ_TEE_HP_MEM_APM_S)
+#define HP_PERI0_PMS_READ_TEE_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_MEM_APM_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_MEM_APM : HRO; bitpos: [1]; default: 0;
+ *  Configures hp_mem_apm registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_MEM_APM    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_MEM_APM_M  (HP_PERI0_PMS_READ_REE0_HP_MEM_APM_V << HP_PERI0_PMS_READ_REE0_HP_MEM_APM_S)
+#define HP_PERI0_PMS_READ_REE0_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_MEM_APM_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_MEM_APM : HRO; bitpos: [2]; default: 0;
+ *  Configures hp_mem_apm registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_MEM_APM    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_MEM_APM_M  (HP_PERI0_PMS_READ_REE1_HP_MEM_APM_V << HP_PERI0_PMS_READ_REE1_HP_MEM_APM_S)
+#define HP_PERI0_PMS_READ_REE1_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_MEM_APM_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_MEM_APM : HRO; bitpos: [3]; default: 0;
+ *  Configures hp_mem_apm registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_MEM_APM    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_MEM_APM_M  (HP_PERI0_PMS_READ_REE2_HP_MEM_APM_V << HP_PERI0_PMS_READ_REE2_HP_MEM_APM_S)
+#define HP_PERI0_PMS_READ_REE2_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_MEM_APM_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mem_apm registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM_M  (HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM_V << HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_MEM_APM_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM : HRO; bitpos: [5]; default: 0;
+ *  Configures hp_mem_apm registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM_M  (HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM_V << HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_MEM_APM_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM : HRO; bitpos: [6]; default: 0;
+ *  Configures hp_mem_apm registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM_M  (HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM_V << HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_MEM_APM_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM : HRO; bitpos: [7]; default: 0;
+ *  Configures hp_mem_apm registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM_M  (HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM_V << HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_MEM_APM_S  7
+/** HP_PERI0_PMS_HP_MEM_APM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mem_apm peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_MEM_APM_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_MEM_APM_LOCK_M  (HP_PERI0_PMS_HP_MEM_APM_LOCK_V << HP_PERI0_PMS_HP_MEM_APM_LOCK_S)
+#define HP_PERI0_PMS_HP_MEM_APM_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_MEM_APM_LOCK_S  8
+
+/** HP_PERI0_PMS_CPU_APM_CTRL_REG register
+ *  cpu_apm read/write control register
+ */
+#define HP_PERI0_PMS_CPU_APM_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x64)
+/** HP_PERI0_PMS_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1;
+ *  Configures cpu_apm registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_CPU_APM    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_CPU_APM_M  (HP_PERI0_PMS_READ_TEE_CPU_APM_V << HP_PERI0_PMS_READ_TEE_CPU_APM_S)
+#define HP_PERI0_PMS_READ_TEE_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_CPU_APM_S  0
+/** HP_PERI0_PMS_READ_REE0_CPU_APM : HRO; bitpos: [1]; default: 0;
+ *  Configures cpu_apm registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_CPU_APM    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_CPU_APM_M  (HP_PERI0_PMS_READ_REE0_CPU_APM_V << HP_PERI0_PMS_READ_REE0_CPU_APM_S)
+#define HP_PERI0_PMS_READ_REE0_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_CPU_APM_S  1
+/** HP_PERI0_PMS_READ_REE1_CPU_APM : HRO; bitpos: [2]; default: 0;
+ *  Configures cpu_apm registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_CPU_APM    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_CPU_APM_M  (HP_PERI0_PMS_READ_REE1_CPU_APM_V << HP_PERI0_PMS_READ_REE1_CPU_APM_S)
+#define HP_PERI0_PMS_READ_REE1_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_CPU_APM_S  2
+/** HP_PERI0_PMS_READ_REE2_CPU_APM : HRO; bitpos: [3]; default: 0;
+ *  Configures cpu_apm registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_CPU_APM    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_CPU_APM_M  (HP_PERI0_PMS_READ_REE2_CPU_APM_V << HP_PERI0_PMS_READ_REE2_CPU_APM_S)
+#define HP_PERI0_PMS_READ_REE2_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_CPU_APM_S  3
+/** HP_PERI0_PMS_WRITE_TEE_CPU_APM : R/W; bitpos: [4]; default: 1;
+ *  Configures cpu_apm registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_CPU_APM    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_CPU_APM_M  (HP_PERI0_PMS_WRITE_TEE_CPU_APM_V << HP_PERI0_PMS_WRITE_TEE_CPU_APM_S)
+#define HP_PERI0_PMS_WRITE_TEE_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_CPU_APM_S  4
+/** HP_PERI0_PMS_WRITE_REE0_CPU_APM : HRO; bitpos: [5]; default: 0;
+ *  Configures cpu_apm registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_CPU_APM    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_CPU_APM_M  (HP_PERI0_PMS_WRITE_REE0_CPU_APM_V << HP_PERI0_PMS_WRITE_REE0_CPU_APM_S)
+#define HP_PERI0_PMS_WRITE_REE0_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_CPU_APM_S  5
+/** HP_PERI0_PMS_WRITE_REE1_CPU_APM : HRO; bitpos: [6]; default: 0;
+ *  Configures cpu_apm registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_CPU_APM    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_CPU_APM_M  (HP_PERI0_PMS_WRITE_REE1_CPU_APM_V << HP_PERI0_PMS_WRITE_REE1_CPU_APM_S)
+#define HP_PERI0_PMS_WRITE_REE1_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_CPU_APM_S  6
+/** HP_PERI0_PMS_WRITE_REE2_CPU_APM : HRO; bitpos: [7]; default: 0;
+ *  Configures cpu_apm registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_CPU_APM    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_CPU_APM_M  (HP_PERI0_PMS_WRITE_REE2_CPU_APM_V << HP_PERI0_PMS_WRITE_REE2_CPU_APM_S)
+#define HP_PERI0_PMS_WRITE_REE2_CPU_APM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_CPU_APM_S  7
+/** HP_PERI0_PMS_CPU_APM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock cpu_apm peri_apm configuration
+ */
+#define HP_PERI0_PMS_CPU_APM_LOCK    (BIT(8))
+#define HP_PERI0_PMS_CPU_APM_LOCK_M  (HP_PERI0_PMS_CPU_APM_LOCK_V << HP_PERI0_PMS_CPU_APM_LOCK_S)
+#define HP_PERI0_PMS_CPU_APM_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_CPU_APM_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_PERI0_PMS_CTRL_REG register
+ *  hp_peri0_pms read/write control register
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x68)
+/** HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_peri0_pms registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS_M  (HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS_V << HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_PERI0_PMS_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS : HRO; bitpos: [1]; default: 0;
+ *  Configures hp_peri0_pms registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS_M  (HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS_V << HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_PERI0_PMS_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS : HRO; bitpos: [2]; default: 0;
+ *  Configures hp_peri0_pms registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS_M  (HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS_V << HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_PERI0_PMS_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS : HRO; bitpos: [3]; default: 0;
+ *  Configures hp_peri0_pms registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS_M  (HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS_V << HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_PERI0_PMS_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_peri0_pms registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS_M  (HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS_V << HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_PERI0_PMS_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS : HRO; bitpos: [5]; default: 0;
+ *  Configures hp_peri0_pms registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS_M  (HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS_V << HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_PERI0_PMS_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS : HRO; bitpos: [6]; default: 0;
+ *  Configures hp_peri0_pms registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS_M  (HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS_V << HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_PERI0_PMS_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS : HRO; bitpos: [7]; default: 0;
+ *  Configures hp_peri0_pms registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS_M  (HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS_V << HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_PERI0_PMS_S  7
+/** HP_PERI0_PMS_HP_PERI0_PMS_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_peri0_pms peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_PERI0_PMS_LOCK_M  (HP_PERI0_PMS_HP_PERI0_PMS_LOCK_V << HP_PERI0_PMS_HP_PERI0_PMS_LOCK_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_PERI0_PMS_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_KEY_MANAGER_CTRL_REG register
+ *  hp_key_manager read/write control register
+ */
+#define HP_PERI0_PMS_HP_KEY_MANAGER_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x6c)
+/** HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_key_manager registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER_M  (HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER_V << HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_KEY_MANAGER_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_key_manager registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER_M  (HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER_V << HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_KEY_MANAGER_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_key_manager registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER_M  (HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER_V << HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_KEY_MANAGER_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_key_manager registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER_M  (HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER_V << HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_KEY_MANAGER_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_key_manager registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER_M  (HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER_V << HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_KEY_MANAGER_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_key_manager registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER_M  (HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER_V << HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_KEY_MANAGER_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_key_manager registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER_M  (HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER_V << HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_KEY_MANAGER_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_key_manager registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER_M  (HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER_V << HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_KEY_MANAGER_S  7
+/** HP_PERI0_PMS_HP_KEY_MANAGER_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_key_manager peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_KEY_MANAGER_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_KEY_MANAGER_LOCK_M  (HP_PERI0_PMS_HP_KEY_MANAGER_LOCK_V << HP_PERI0_PMS_HP_KEY_MANAGER_LOCK_S)
+#define HP_PERI0_PMS_HP_KEY_MANAGER_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_KEY_MANAGER_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_CRYPTO_CTRL_REG register
+ *  hp_crypto read/write control register
+ */
+#define HP_PERI0_PMS_HP_CRYPTO_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x70)
+/** HP_PERI0_PMS_READ_TEE_HP_CRYPTO : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_crypto registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_CRYPTO    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_CRYPTO_M  (HP_PERI0_PMS_READ_TEE_HP_CRYPTO_V << HP_PERI0_PMS_READ_TEE_HP_CRYPTO_S)
+#define HP_PERI0_PMS_READ_TEE_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_CRYPTO_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_CRYPTO : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_crypto registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_CRYPTO    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_CRYPTO_M  (HP_PERI0_PMS_READ_REE0_HP_CRYPTO_V << HP_PERI0_PMS_READ_REE0_HP_CRYPTO_S)
+#define HP_PERI0_PMS_READ_REE0_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_CRYPTO_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_CRYPTO : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_crypto registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_CRYPTO    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_CRYPTO_M  (HP_PERI0_PMS_READ_REE1_HP_CRYPTO_V << HP_PERI0_PMS_READ_REE1_HP_CRYPTO_S)
+#define HP_PERI0_PMS_READ_REE1_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_CRYPTO_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_CRYPTO : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_crypto registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_CRYPTO    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_CRYPTO_M  (HP_PERI0_PMS_READ_REE2_HP_CRYPTO_V << HP_PERI0_PMS_READ_REE2_HP_CRYPTO_S)
+#define HP_PERI0_PMS_READ_REE2_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_CRYPTO_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_crypto registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO_M  (HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO_V << HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_CRYPTO_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_crypto registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO_M  (HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO_V << HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_CRYPTO_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_crypto registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO_M  (HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO_V << HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_CRYPTO_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_crypto registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO_M  (HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO_V << HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_CRYPTO_S  7
+/** HP_PERI0_PMS_HP_CRYPTO_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_crypto peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_CRYPTO_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_CRYPTO_LOCK_M  (HP_PERI0_PMS_HP_CRYPTO_LOCK_V << HP_PERI0_PMS_HP_CRYPTO_LOCK_S)
+#define HP_PERI0_PMS_HP_CRYPTO_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_CRYPTO_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_AXI_ICM_CTRL_REG register
+ *  hp_axi_icm read/write control register
+ */
+#define HP_PERI0_PMS_HP_AXI_ICM_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x74)
+/** HP_PERI0_PMS_READ_TEE_HP_AXI_ICM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_axi_icm registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_ICM    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_ICM_M  (HP_PERI0_PMS_READ_TEE_HP_AXI_ICM_V << HP_PERI0_PMS_READ_TEE_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_HP_AXI_ICM_S  0
+/** HP_PERI0_PMS_READ_REE0_HP_AXI_ICM : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_axi_icm registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_ICM    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_ICM_M  (HP_PERI0_PMS_READ_REE0_HP_AXI_ICM_V << HP_PERI0_PMS_READ_REE0_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_HP_AXI_ICM_S  1
+/** HP_PERI0_PMS_READ_REE1_HP_AXI_ICM : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_axi_icm registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_ICM    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_ICM_M  (HP_PERI0_PMS_READ_REE1_HP_AXI_ICM_V << HP_PERI0_PMS_READ_REE1_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_HP_AXI_ICM_S  2
+/** HP_PERI0_PMS_READ_REE2_HP_AXI_ICM : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_axi_icm registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_ICM    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_ICM_M  (HP_PERI0_PMS_READ_REE2_HP_AXI_ICM_V << HP_PERI0_PMS_READ_REE2_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_HP_AXI_ICM_S  3
+/** HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_axi_icm registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM_M  (HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM_V << HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_HP_AXI_ICM_S  4
+/** HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_axi_icm registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM_M  (HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM_V << HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_HP_AXI_ICM_S  5
+/** HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_axi_icm registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM_M  (HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM_V << HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_HP_AXI_ICM_S  6
+/** HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_axi_icm registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM_M  (HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM_V << HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM_S)
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_HP_AXI_ICM_S  7
+/** HP_PERI0_PMS_HP_AXI_ICM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_axi_icm peri_apm configuration
+ */
+#define HP_PERI0_PMS_HP_AXI_ICM_LOCK    (BIT(8))
+#define HP_PERI0_PMS_HP_AXI_ICM_LOCK_M  (HP_PERI0_PMS_HP_AXI_ICM_LOCK_V << HP_PERI0_PMS_HP_AXI_ICM_LOCK_S)
+#define HP_PERI0_PMS_HP_AXI_ICM_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_HP_AXI_ICM_LOCK_S  8
+
+/** HP_PERI0_PMS_AXI_PERF_MON_CTRL_REG register
+ *  axi_perf_mon read/write control register
+ */
+#define HP_PERI0_PMS_AXI_PERF_MON_CTRL_REG (DR_REG_HP_PERI0_PMS_BASE + 0x78)
+/** HP_PERI0_PMS_READ_TEE_AXI_PERF_MON : R/W; bitpos: [0]; default: 1;
+ *  Configures axi_perf_mon registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_TEE_AXI_PERF_MON    (BIT(0))
+#define HP_PERI0_PMS_READ_TEE_AXI_PERF_MON_M  (HP_PERI0_PMS_READ_TEE_AXI_PERF_MON_V << HP_PERI0_PMS_READ_TEE_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_READ_TEE_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_TEE_AXI_PERF_MON_S  0
+/** HP_PERI0_PMS_READ_REE0_AXI_PERF_MON : R/W; bitpos: [1]; default: 0;
+ *  Configures axi_perf_mon registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE0_AXI_PERF_MON    (BIT(1))
+#define HP_PERI0_PMS_READ_REE0_AXI_PERF_MON_M  (HP_PERI0_PMS_READ_REE0_AXI_PERF_MON_V << HP_PERI0_PMS_READ_REE0_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_READ_REE0_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE0_AXI_PERF_MON_S  1
+/** HP_PERI0_PMS_READ_REE1_AXI_PERF_MON : R/W; bitpos: [2]; default: 0;
+ *  Configures axi_perf_mon registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE1_AXI_PERF_MON    (BIT(2))
+#define HP_PERI0_PMS_READ_REE1_AXI_PERF_MON_M  (HP_PERI0_PMS_READ_REE1_AXI_PERF_MON_V << HP_PERI0_PMS_READ_REE1_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_READ_REE1_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE1_AXI_PERF_MON_S  2
+/** HP_PERI0_PMS_READ_REE2_AXI_PERF_MON : R/W; bitpos: [3]; default: 0;
+ *  Configures axi_perf_mon registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI0_PMS_READ_REE2_AXI_PERF_MON    (BIT(3))
+#define HP_PERI0_PMS_READ_REE2_AXI_PERF_MON_M  (HP_PERI0_PMS_READ_REE2_AXI_PERF_MON_V << HP_PERI0_PMS_READ_REE2_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_READ_REE2_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_READ_REE2_AXI_PERF_MON_S  3
+/** HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON : R/W; bitpos: [4]; default: 1;
+ *  Configures axi_perf_mon registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON    (BIT(4))
+#define HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON_M  (HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON_V << HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_TEE_AXI_PERF_MON_S  4
+/** HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON : R/W; bitpos: [5]; default: 0;
+ *  Configures axi_perf_mon registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON    (BIT(5))
+#define HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON_M  (HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON_V << HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE0_AXI_PERF_MON_S  5
+/** HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON : R/W; bitpos: [6]; default: 0;
+ *  Configures axi_perf_mon registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON    (BIT(6))
+#define HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON_M  (HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON_V << HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE1_AXI_PERF_MON_S  6
+/** HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON : R/W; bitpos: [7]; default: 0;
+ *  Configures axi_perf_mon registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON    (BIT(7))
+#define HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON_M  (HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON_V << HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON_S)
+#define HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON_V  0x00000001U
+#define HP_PERI0_PMS_WRITE_REE2_AXI_PERF_MON_S  7
+/** HP_PERI0_PMS_AXI_PERF_MON_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock axi_perf_mon peri_apm configuration
+ */
+#define HP_PERI0_PMS_AXI_PERF_MON_LOCK    (BIT(8))
+#define HP_PERI0_PMS_AXI_PERF_MON_LOCK_M  (HP_PERI0_PMS_AXI_PERF_MON_LOCK_V << HP_PERI0_PMS_AXI_PERF_MON_LOCK_S)
+#define HP_PERI0_PMS_AXI_PERF_MON_LOCK_V  0x00000001U
+#define HP_PERI0_PMS_AXI_PERF_MON_LOCK_S  8
+
+/** HP_PERI0_PMS_HP_CPUPERI0_0_REG register
+ *  HP_CPUPERI0 PMS configuration & info register
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_0_REG (DR_REG_HP_PERI0_PMS_BASE + 0x200)
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear hp_cpuperi0 peri_pms_record_reg.
+ *  0: No clear
+ *  1: Clear peri_pms_record_reg
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR    (BIT(0))
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_CLR_S  0
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET : RO; bitpos: [1]; default: 0;
+ *  Represents whether the hp_cpuperi0 pms has been triggered.
+ *  0: No triggered
+ *  1: Has been triggered
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET    (BIT(1))
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_DET_S  1
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID : RO; bitpos: [7:2]; default: 0;
+ *  Represents the master id when hp_cpuperi0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID    0x0000003FU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID_V  0x0000003FU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ID_S  2
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE : RO; bitpos: [9:8]; default: 0;
+ *  Represents the security mode when hp_cpuperi0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE    0x00000003U
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE_V  0x00000003U
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_MODE_S  8
+
+/** HP_PERI0_PMS_HP_CPUPERI0_1_REG register
+ *  HP_CPUPERI0 PMS exception addr record register
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_1_REG (DR_REG_HP_PERI0_PMS_BASE + 0x204)
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR : RO; bitpos: [27:0]; default: 0;
+ *  Represents the access address (bit27~bit0) when hp_cpuperi0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR    0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_V  0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_S  0
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST : HRO; bitpos: [31:28]; default:
+ *  2;
+ *  Represents the access address (bit31~bit28) when hp_cpuperi0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST    0x0000000FU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST_V  0x0000000FU
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_EXCEPTION_ADDR_CONST_S  28
+
+/** HP_PERI0_PMS_HP_CPUPERI1_0_REG register
+ *  HP_CPUPERI1 PMS configuration & info register
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_0_REG (DR_REG_HP_PERI0_PMS_BASE + 0x208)
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear hp_cpuperi1 peri_pms_record_reg.
+ *  0: No clear
+ *  1: Clear peri_pms_record_reg
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR    (BIT(0))
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_CLR_S  0
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET : RO; bitpos: [1]; default: 0;
+ *  Represents whether the hp_cpuperi1 pms has been triggered.
+ *  0: No triggered
+ *  1: Has been triggered
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET    (BIT(1))
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_DET_S  1
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID : RO; bitpos: [7:2]; default: 0;
+ *  Represents the master id when hp_cpuperi1 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID    0x0000003FU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID_V  0x0000003FU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ID_S  2
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE : RO; bitpos: [9:8]; default: 0;
+ *  Represents the security mode when hp_cpuperi1 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE    0x00000003U
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE_V  0x00000003U
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_MODE_S  8
+
+/** HP_PERI0_PMS_HP_CPUPERI1_1_REG register
+ *  HP_CPUPERI1 PMS exception addr record register
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_1_REG (DR_REG_HP_PERI0_PMS_BASE + 0x20c)
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR : RO; bitpos: [27:0]; default: 0;
+ *  Represents the access address (bit27~bit0) when hp_cpuperi1 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR    0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_V  0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_S  0
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST : HRO; bitpos: [31:28]; default:
+ *  2;
+ *  Represents the access address (bit31~bit28) when hp_cpuperi1 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST    0x0000000FU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST_V  0x0000000FU
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_EXCEPTION_ADDR_CONST_S  28
+
+/** HP_PERI0_PMS_HP_PERI0_0_REG register
+ *  HP_PERI0 PMS configuration & info register
+ */
+#define HP_PERI0_PMS_HP_PERI0_0_REG (DR_REG_HP_PERI0_PMS_BASE + 0x210)
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear hp_peri0 peri_pms_record_reg.
+ *  0: No clear
+ *  1: Clear peri_pms_record_reg
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR    (BIT(0))
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR_V  0x00000001U
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_CLR_S  0
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET : RO; bitpos: [1]; default: 0;
+ *  Represents whether the hp_peri0 pms has been triggered.
+ *  0: No triggered
+ *  1: Has been triggered
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET    (BIT(1))
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET_V  0x00000001U
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_DET_S  1
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID : RO; bitpos: [7:2]; default: 0;
+ *  Represents the master id when hp_peri0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID    0x0000003FU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID_V  0x0000003FU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ID_S  2
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE : RO; bitpos: [9:8]; default: 0;
+ *  Represents the security mode when hp_peri0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE    0x00000003U
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE_V  0x00000003U
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_MODE_S  8
+
+/** HP_PERI0_PMS_HP_PERI0_1_REG register
+ *  HP_PERI0 PMS exception addr record register
+ */
+#define HP_PERI0_PMS_HP_PERI0_1_REG (DR_REG_HP_PERI0_PMS_BASE + 0x214)
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR : RO; bitpos: [27:0]; default: 0;
+ *  Represents the access address (bit27~bit0) when hp_peri0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR    0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_V  0x0FFFFFFFU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_S  0
+/** HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST : HRO; bitpos: [31:28]; default: 2;
+ *  Represents the access address (bit31~bit28) when hp_peri0 pms has been triggered.
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST    0x0000000FU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST_M  (HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST_V << HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST_V  0x0000000FU
+#define HP_PERI0_PMS_HP_PERI0_PMS_EXCEPTION_ADDR_CONST_S  28
+
+/** HP_PERI0_PMS_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define HP_PERI0_PMS_INT_EN_REG (DR_REG_HP_PERI0_PMS_BASE + 0x300)
+/** HP_PERI0_PMS_HP_PERI0_PMS_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures to enable hp_peri0 pms interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_PERI0_PMS_HP_PERI0_PMS_INT_EN    (BIT(0))
+#define HP_PERI0_PMS_HP_PERI0_PMS_INT_EN_M  (HP_PERI0_PMS_HP_PERI0_PMS_INT_EN_V << HP_PERI0_PMS_HP_PERI0_PMS_INT_EN_S)
+#define HP_PERI0_PMS_HP_PERI0_PMS_INT_EN_V  0x00000001U
+#define HP_PERI0_PMS_HP_PERI0_PMS_INT_EN_S  0
+/** HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN : R/W; bitpos: [1]; default: 0;
+ *  Configures to enable hp_cpuperi1 pms interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN    (BIT(1))
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN_M  (HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN_V << HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN_S)
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI1_PMS_INT_EN_S  1
+/** HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN : R/W; bitpos: [2]; default: 0;
+ *  Configures to enable hp_cpuperi0 pms interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN    (BIT(2))
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN_M  (HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN_V << HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN_S)
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN_V  0x00000001U
+#define HP_PERI0_PMS_HP_CPUPERI0_PMS_INT_EN_S  2
+
+/** HP_PERI0_PMS_BUS_ERR_CONF_REG register
+ *  Clock gating register
+ */
+#define HP_PERI0_PMS_BUS_ERR_CONF_REG (DR_REG_HP_PERI0_PMS_BASE + 0xff0)
+/** HP_PERI0_PMS_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether return error response to cpu when access blocked
+ *  0: disable error response
+ *  1: enable error response
+ */
+#define HP_PERI0_PMS_BUS_ERR_RESP_EN    (BIT(0))
+#define HP_PERI0_PMS_BUS_ERR_RESP_EN_M  (HP_PERI0_PMS_BUS_ERR_RESP_EN_V << HP_PERI0_PMS_BUS_ERR_RESP_EN_S)
+#define HP_PERI0_PMS_BUS_ERR_RESP_EN_V  0x00000001U
+#define HP_PERI0_PMS_BUS_ERR_RESP_EN_S  0
+
+/** HP_PERI0_PMS_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define HP_PERI0_PMS_CLOCK_GATE_REG (DR_REG_HP_PERI0_PMS_BASE + 0xff8)
+/** HP_PERI0_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: enable automatic clock gating
+ *  1: keep the clock always on
+ */
+#define HP_PERI0_PMS_CLK_EN    (BIT(0))
+#define HP_PERI0_PMS_CLK_EN_M  (HP_PERI0_PMS_CLK_EN_V << HP_PERI0_PMS_CLK_EN_S)
+#define HP_PERI0_PMS_CLK_EN_V  0x00000001U
+#define HP_PERI0_PMS_CLK_EN_S  0
+
+/** HP_PERI0_PMS_DATE_REG register
+ *  Version control register
+ */
+#define HP_PERI0_PMS_DATE_REG (DR_REG_HP_PERI0_PMS_BASE + 0xffc)
+/** HP_PERI0_PMS_DATE : R/W; bitpos: [27:0]; default: 38834736;
+ *  Version control register
+ */
+#define HP_PERI0_PMS_DATE    0x0FFFFFFFU
+#define HP_PERI0_PMS_DATE_M  (HP_PERI0_PMS_DATE_V << HP_PERI0_PMS_DATE_S)
+#define HP_PERI0_PMS_DATE_V  0x0FFFFFFFU
+#define HP_PERI0_PMS_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_peri0_pms_struct.h b/components/soc/esp32s31/register/soc/hp_peri0_pms_struct.h
new file mode 100644
index 00000000000..cce58d54fa5
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_peri0_pms_struct.h
@@ -0,0 +1,2215 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: read write control register */
+/** Type of trace0_ctrl register
+ *  trace0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_trace0 : R/W; bitpos: [0]; default: 1;
+         *  Configures trace0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_trace0:1;
+        /** read_ree0_trace0 : R/W; bitpos: [1]; default: 0;
+         *  Configures trace0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_trace0:1;
+        /** read_ree1_trace0 : R/W; bitpos: [2]; default: 0;
+         *  Configures trace0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_trace0:1;
+        /** read_ree2_trace0 : R/W; bitpos: [3]; default: 0;
+         *  Configures trace0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_trace0:1;
+        /** write_tee_trace0 : R/W; bitpos: [4]; default: 1;
+         *  Configures trace0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_trace0:1;
+        /** write_ree0_trace0 : R/W; bitpos: [5]; default: 0;
+         *  Configures trace0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_trace0:1;
+        /** write_ree1_trace0 : R/W; bitpos: [6]; default: 0;
+         *  Configures trace0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_trace0:1;
+        /** write_ree2_trace0 : R/W; bitpos: [7]; default: 0;
+         *  Configures trace0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_trace0:1;
+        /** trace0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock trace0 peri_apm configuration
+         */
+        uint32_t trace0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_trace0_ctrl_reg_t;
+
+/** Type of trace1_ctrl register
+ *  trace1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_trace1 : R/W; bitpos: [0]; default: 1;
+         *  Configures trace1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_trace1:1;
+        /** read_ree0_trace1 : R/W; bitpos: [1]; default: 0;
+         *  Configures trace1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_trace1:1;
+        /** read_ree1_trace1 : R/W; bitpos: [2]; default: 0;
+         *  Configures trace1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_trace1:1;
+        /** read_ree2_trace1 : R/W; bitpos: [3]; default: 0;
+         *  Configures trace1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_trace1:1;
+        /** write_tee_trace1 : R/W; bitpos: [4]; default: 1;
+         *  Configures trace1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_trace1:1;
+        /** write_ree0_trace1 : R/W; bitpos: [5]; default: 0;
+         *  Configures trace1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_trace1:1;
+        /** write_ree1_trace1 : R/W; bitpos: [6]; default: 0;
+         *  Configures trace1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_trace1:1;
+        /** write_ree2_trace1 : R/W; bitpos: [7]; default: 0;
+         *  Configures trace1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_trace1:1;
+        /** trace1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock trace1 peri_apm configuration
+         */
+        uint32_t trace1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_trace1_ctrl_reg_t;
+
+/** Type of cpu_bus_mon_ctrl register
+ *  cpu_bus_mon read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_cpu_bus_mon : R/W; bitpos: [0]; default: 1;
+         *  Configures cpu_bus_mon registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_cpu_bus_mon:1;
+        /** read_ree0_cpu_bus_mon : R/W; bitpos: [1]; default: 0;
+         *  Configures cpu_bus_mon registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_cpu_bus_mon:1;
+        /** read_ree1_cpu_bus_mon : R/W; bitpos: [2]; default: 0;
+         *  Configures cpu_bus_mon registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_cpu_bus_mon:1;
+        /** read_ree2_cpu_bus_mon : R/W; bitpos: [3]; default: 0;
+         *  Configures cpu_bus_mon registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_cpu_bus_mon:1;
+        /** write_tee_cpu_bus_mon : R/W; bitpos: [4]; default: 1;
+         *  Configures cpu_bus_mon registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_cpu_bus_mon:1;
+        /** write_ree0_cpu_bus_mon : R/W; bitpos: [5]; default: 0;
+         *  Configures cpu_bus_mon registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_cpu_bus_mon:1;
+        /** write_ree1_cpu_bus_mon : R/W; bitpos: [6]; default: 0;
+         *  Configures cpu_bus_mon registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_cpu_bus_mon:1;
+        /** write_ree2_cpu_bus_mon : R/W; bitpos: [7]; default: 0;
+         *  Configures cpu_bus_mon registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_cpu_bus_mon:1;
+        /** cpu_bus_mon_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock cpu_bus_mon peri_apm configuration
+         */
+        uint32_t cpu_bus_mon_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_cpu_bus_mon_ctrl_reg_t;
+
+/** Type of psram_mon_ctrl register
+ *  psram_mon read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_psram_mon : R/W; bitpos: [0]; default: 1;
+         *  Configures psram_mon registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_psram_mon:1;
+        /** read_ree0_psram_mon : R/W; bitpos: [1]; default: 0;
+         *  Configures psram_mon registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_psram_mon:1;
+        /** read_ree1_psram_mon : R/W; bitpos: [2]; default: 0;
+         *  Configures psram_mon registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_psram_mon:1;
+        /** read_ree2_psram_mon : R/W; bitpos: [3]; default: 0;
+         *  Configures psram_mon registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_psram_mon:1;
+        /** write_tee_psram_mon : R/W; bitpos: [4]; default: 1;
+         *  Configures psram_mon registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_psram_mon:1;
+        /** write_ree0_psram_mon : R/W; bitpos: [5]; default: 0;
+         *  Configures psram_mon registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_psram_mon:1;
+        /** write_ree1_psram_mon : R/W; bitpos: [6]; default: 0;
+         *  Configures psram_mon registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_psram_mon:1;
+        /** write_ree2_psram_mon : R/W; bitpos: [7]; default: 0;
+         *  Configures psram_mon registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_psram_mon:1;
+        /** psram_mon_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock psram_mon peri_apm configuration
+         */
+        uint32_t psram_mon_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_psram_mon_ctrl_reg_t;
+
+/** Type of tcm_mon_ctrl register
+ *  tcm_mon read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_tcm_mon : R/W; bitpos: [0]; default: 1;
+         *  Configures tcm_mon registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_tcm_mon:1;
+        /** read_ree0_tcm_mon : R/W; bitpos: [1]; default: 0;
+         *  Configures tcm_mon registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_tcm_mon:1;
+        /** read_ree1_tcm_mon : R/W; bitpos: [2]; default: 0;
+         *  Configures tcm_mon registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_tcm_mon:1;
+        /** read_ree2_tcm_mon : R/W; bitpos: [3]; default: 0;
+         *  Configures tcm_mon registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_tcm_mon:1;
+        /** write_tee_tcm_mon : R/W; bitpos: [4]; default: 1;
+         *  Configures tcm_mon registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_tcm_mon:1;
+        /** write_ree0_tcm_mon : R/W; bitpos: [5]; default: 0;
+         *  Configures tcm_mon registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_tcm_mon:1;
+        /** write_ree1_tcm_mon : R/W; bitpos: [6]; default: 0;
+         *  Configures tcm_mon registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_tcm_mon:1;
+        /** write_ree2_tcm_mon : R/W; bitpos: [7]; default: 0;
+         *  Configures tcm_mon registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_tcm_mon:1;
+        /** tcm_mon_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock tcm_mon peri_apm configuration
+         */
+        uint32_t tcm_mon_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_tcm_mon_ctrl_reg_t;
+
+/** Type of cache_ctrl register
+ *  cache read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_cache : R/W; bitpos: [0]; default: 1;
+         *  Configures cache registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_cache:1;
+        /** read_ree0_cache : R/W; bitpos: [1]; default: 0;
+         *  Configures cache registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_cache:1;
+        /** read_ree1_cache : R/W; bitpos: [2]; default: 0;
+         *  Configures cache registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_cache:1;
+        /** read_ree2_cache : R/W; bitpos: [3]; default: 0;
+         *  Configures cache registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_cache:1;
+        /** write_tee_cache : R/W; bitpos: [4]; default: 1;
+         *  Configures cache registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_cache:1;
+        /** write_ree0_cache : R/W; bitpos: [5]; default: 0;
+         *  Configures cache registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_cache:1;
+        /** write_ree1_cache : R/W; bitpos: [6]; default: 0;
+         *  Configures cache registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_cache:1;
+        /** write_ree2_cache : R/W; bitpos: [7]; default: 0;
+         *  Configures cache registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_cache:1;
+        /** cache_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock cache peri_apm configuration
+         */
+        uint32_t cache_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_cache_ctrl_reg_t;
+
+/** Type of hp_usbotg_core_ctrl register
+ *  hp_usbotg_core read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_usbotg_core : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_usbotg_core registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_usbotg_core:1;
+        /** read_ree0_hp_usbotg_core : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_usbotg_core registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_usbotg_core:1;
+        /** read_ree1_hp_usbotg_core : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_usbotg_core registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_usbotg_core:1;
+        /** read_ree2_hp_usbotg_core : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_usbotg_core registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_usbotg_core:1;
+        /** write_tee_hp_usbotg_core : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_usbotg_core registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_usbotg_core:1;
+        /** write_ree0_hp_usbotg_core : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_usbotg_core registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_usbotg_core:1;
+        /** write_ree1_hp_usbotg_core : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_usbotg_core registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_usbotg_core:1;
+        /** write_ree2_hp_usbotg_core : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_usbotg_core registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_usbotg_core:1;
+        /** hp_usbotg_core_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_usbotg_core peri_apm configuration
+         */
+        uint32_t hp_usbotg_core_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_usbotg_core_ctrl_reg_t;
+
+/** Type of hp_regdma_ctrl register
+ *  hp_regdma read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_regdma : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_regdma registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_regdma:1;
+        /** read_ree0_hp_regdma : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_regdma registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_regdma:1;
+        /** read_ree1_hp_regdma : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_regdma registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_regdma:1;
+        /** read_ree2_hp_regdma : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_regdma registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_regdma:1;
+        /** write_tee_hp_regdma : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_regdma registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_regdma:1;
+        /** write_ree0_hp_regdma : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_regdma registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_regdma:1;
+        /** write_ree1_hp_regdma : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_regdma registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_regdma:1;
+        /** write_ree2_hp_regdma : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_regdma registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_regdma:1;
+        /** hp_regdma_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_regdma peri_apm configuration
+         */
+        uint32_t hp_regdma_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_regdma_ctrl_reg_t;
+
+/** Type of hp_sdmmc_ctrl register
+ *  hp_sdmmc read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_sdmmc : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_sdmmc registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_sdmmc:1;
+        /** read_ree0_hp_sdmmc : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_sdmmc registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_sdmmc:1;
+        /** read_ree1_hp_sdmmc : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_sdmmc registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_sdmmc:1;
+        /** read_ree2_hp_sdmmc : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_sdmmc registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_sdmmc:1;
+        /** write_tee_hp_sdmmc : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_sdmmc registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_sdmmc:1;
+        /** write_ree0_hp_sdmmc : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_sdmmc registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_sdmmc:1;
+        /** write_ree1_hp_sdmmc : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_sdmmc registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_sdmmc:1;
+        /** write_ree2_hp_sdmmc : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_sdmmc registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_sdmmc:1;
+        /** hp_sdmmc_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_sdmmc peri_apm configuration
+         */
+        uint32_t hp_sdmmc_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_sdmmc_ctrl_reg_t;
+
+/** Type of hp_ahb_pdma_ctrl register
+ *  hp_ahb_pdma read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_ahb_pdma : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_ahb_pdma registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_ahb_pdma:1;
+        /** read_ree0_hp_ahb_pdma : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_ahb_pdma registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_ahb_pdma:1;
+        /** read_ree1_hp_ahb_pdma : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_ahb_pdma registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_ahb_pdma:1;
+        /** read_ree2_hp_ahb_pdma : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_ahb_pdma registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_ahb_pdma:1;
+        /** write_tee_hp_ahb_pdma : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_ahb_pdma registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_ahb_pdma:1;
+        /** write_ree0_hp_ahb_pdma : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_ahb_pdma registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_ahb_pdma:1;
+        /** write_ree1_hp_ahb_pdma : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_ahb_pdma registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_ahb_pdma:1;
+        /** write_ree2_hp_ahb_pdma : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_ahb_pdma registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_ahb_pdma:1;
+        /** hp_ahb_pdma_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_ahb_pdma peri_apm configuration
+         */
+        uint32_t hp_ahb_pdma_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_ahb_pdma_ctrl_reg_t;
+
+/** Type of hp_jpeg_ctrl register
+ *  hp_jpeg read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_jpeg : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_jpeg registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_jpeg:1;
+        /** read_ree0_hp_jpeg : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_jpeg registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_jpeg:1;
+        /** read_ree1_hp_jpeg : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_jpeg registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_jpeg:1;
+        /** read_ree2_hp_jpeg : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_jpeg registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_jpeg:1;
+        /** write_tee_hp_jpeg : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_jpeg registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_jpeg:1;
+        /** write_ree0_hp_jpeg : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_jpeg registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_jpeg:1;
+        /** write_ree1_hp_jpeg : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_jpeg registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_jpeg:1;
+        /** write_ree2_hp_jpeg : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_jpeg registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_jpeg:1;
+        /** hp_jpeg_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_jpeg peri_apm configuration
+         */
+        uint32_t hp_jpeg_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_jpeg_ctrl_reg_t;
+
+/** Type of hp_ppa_ctrl register
+ *  hp_ppa read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_ppa : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_ppa registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_ppa:1;
+        /** read_ree0_hp_ppa : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_ppa registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_ppa:1;
+        /** read_ree1_hp_ppa : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_ppa registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_ppa:1;
+        /** read_ree2_hp_ppa : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_ppa registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_ppa:1;
+        /** write_tee_hp_ppa : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_ppa registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_ppa:1;
+        /** write_ree0_hp_ppa : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_ppa registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_ppa:1;
+        /** write_ree1_hp_ppa : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_ppa registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_ppa:1;
+        /** write_ree2_hp_ppa : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_ppa registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_ppa:1;
+        /** hp_ppa_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_ppa peri_apm configuration
+         */
+        uint32_t hp_ppa_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_ppa_ctrl_reg_t;
+
+/** Type of hp_dma2d_ctrl register
+ *  hp_dma2d read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_dma2d : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_dma2d registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_dma2d:1;
+        /** read_ree0_hp_dma2d : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_dma2d registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_dma2d:1;
+        /** read_ree1_hp_dma2d : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_dma2d registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_dma2d:1;
+        /** read_ree2_hp_dma2d : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_dma2d registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_dma2d:1;
+        /** write_tee_hp_dma2d : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_dma2d registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_dma2d:1;
+        /** write_ree0_hp_dma2d : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_dma2d registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_dma2d:1;
+        /** write_ree1_hp_dma2d : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_dma2d registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_dma2d:1;
+        /** write_ree2_hp_dma2d : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_dma2d registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_dma2d:1;
+        /** hp_dma2d_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_dma2d peri_apm configuration
+         */
+        uint32_t hp_dma2d_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_dma2d_ctrl_reg_t;
+
+/** Type of hp_axi_pdma_ctrl register
+ *  hp_axi_pdma read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_axi_pdma : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_axi_pdma registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_axi_pdma:1;
+        /** read_ree0_hp_axi_pdma : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_axi_pdma registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_axi_pdma:1;
+        /** read_ree1_hp_axi_pdma : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_axi_pdma registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_axi_pdma:1;
+        /** read_ree2_hp_axi_pdma : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_axi_pdma registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_axi_pdma:1;
+        /** write_tee_hp_axi_pdma : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_axi_pdma registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_axi_pdma:1;
+        /** write_ree0_hp_axi_pdma : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_axi_pdma registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_axi_pdma:1;
+        /** write_ree1_hp_axi_pdma : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_axi_pdma registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_axi_pdma:1;
+        /** write_ree2_hp_axi_pdma : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_axi_pdma registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_axi_pdma:1;
+        /** hp_axi_pdma_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_axi_pdma peri_apm configuration
+         */
+        uint32_t hp_axi_pdma_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_axi_pdma_ctrl_reg_t;
+
+/** Type of hp_gmac_ctrl register
+ *  hp_gmac read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_gmac : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_gmac registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_gmac:1;
+        /** read_ree0_hp_gmac : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_gmac registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_gmac:1;
+        /** read_ree1_hp_gmac : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_gmac registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_gmac:1;
+        /** read_ree2_hp_gmac : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_gmac registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_gmac:1;
+        /** write_tee_hp_gmac : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_gmac registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_gmac:1;
+        /** write_ree0_hp_gmac : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_gmac registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_gmac:1;
+        /** write_ree1_hp_gmac : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_gmac registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_gmac:1;
+        /** write_ree2_hp_gmac : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_gmac registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_gmac:1;
+        /** hp_gmac_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_gmac peri_apm configuration
+         */
+        uint32_t hp_gmac_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_gmac_ctrl_reg_t;
+
+/** Type of hp_pvt0_ctrl register
+ *  hp_pvt0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_pvt0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_pvt0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_pvt0:1;
+        /** read_ree0_hp_pvt0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_pvt0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_pvt0:1;
+        /** read_ree1_hp_pvt0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_pvt0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_pvt0:1;
+        /** read_ree2_hp_pvt0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_pvt0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_pvt0:1;
+        /** write_tee_hp_pvt0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_pvt0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_pvt0:1;
+        /** write_ree0_hp_pvt0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_pvt0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_pvt0:1;
+        /** write_ree1_hp_pvt0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_pvt0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_pvt0:1;
+        /** write_ree2_hp_pvt0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_pvt0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_pvt0:1;
+        /** hp_pvt0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_pvt0 peri_apm configuration
+         */
+        uint32_t hp_pvt0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_pvt0_ctrl_reg_t;
+
+/** Type of hp_rmt_ctrl register
+ *  hp_rmt read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_rmt : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_rmt registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_rmt:1;
+        /** read_ree0_hp_rmt : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_rmt registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_rmt:1;
+        /** read_ree1_hp_rmt : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_rmt registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_rmt:1;
+        /** read_ree2_hp_rmt : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_rmt registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_rmt:1;
+        /** write_tee_hp_rmt : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_rmt registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_rmt:1;
+        /** write_ree0_hp_rmt : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_rmt registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_rmt:1;
+        /** write_ree1_hp_rmt : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_rmt registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_rmt:1;
+        /** write_ree2_hp_rmt : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_rmt registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_rmt:1;
+        /** hp_rmt_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_rmt peri_apm configuration
+         */
+        uint32_t hp_rmt_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_rmt_ctrl_reg_t;
+
+/** Type of hp_bitsrambler_ctrl register
+ *  hp_bitsrambler read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_bitsrambler : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_bitsrambler registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_bitsrambler:1;
+        /** read_ree0_hp_bitsrambler : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_bitsrambler registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_bitsrambler:1;
+        /** read_ree1_hp_bitsrambler : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_bitsrambler registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_bitsrambler:1;
+        /** read_ree2_hp_bitsrambler : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_bitsrambler registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_bitsrambler:1;
+        /** write_tee_hp_bitsrambler : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_bitsrambler registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_bitsrambler:1;
+        /** write_ree0_hp_bitsrambler : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_bitsrambler registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_bitsrambler:1;
+        /** write_ree1_hp_bitsrambler : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_bitsrambler registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_bitsrambler:1;
+        /** write_ree2_hp_bitsrambler : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_bitsrambler registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_bitsrambler:1;
+        /** hp_bitsrambler_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_bitsrambler peri_apm configuration
+         */
+        uint32_t hp_bitsrambler_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_bitsrambler_ctrl_reg_t;
+
+/** Type of hp_asrc_ctrl register
+ *  hp_asrc read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_asrc : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_asrc registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_asrc:1;
+        /** read_ree0_hp_asrc : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_asrc registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_asrc:1;
+        /** read_ree1_hp_asrc : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_asrc registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_asrc:1;
+        /** read_ree2_hp_asrc : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_asrc registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_asrc:1;
+        /** write_tee_hp_asrc : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_asrc registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_asrc:1;
+        /** write_ree0_hp_asrc : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_asrc registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_asrc:1;
+        /** write_ree1_hp_asrc : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_asrc registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_asrc:1;
+        /** write_ree2_hp_asrc : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_asrc registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_asrc:1;
+        /** hp_asrc_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_asrc peri_apm configuration
+         */
+        uint32_t hp_asrc_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_asrc_ctrl_reg_t;
+
+/** Type of cnnt_sys_reg_ctrl register
+ *  cnnt_sys_reg read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_cnnt_sys_reg : R/W; bitpos: [0]; default: 1;
+         *  Configures cnnt_sys_reg registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_cnnt_sys_reg:1;
+        /** read_ree0_cnnt_sys_reg : R/W; bitpos: [1]; default: 0;
+         *  Configures cnnt_sys_reg registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_cnnt_sys_reg:1;
+        /** read_ree1_cnnt_sys_reg : R/W; bitpos: [2]; default: 0;
+         *  Configures cnnt_sys_reg registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_cnnt_sys_reg:1;
+        /** read_ree2_cnnt_sys_reg : R/W; bitpos: [3]; default: 0;
+         *  Configures cnnt_sys_reg registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_cnnt_sys_reg:1;
+        /** write_tee_cnnt_sys_reg : R/W; bitpos: [4]; default: 1;
+         *  Configures cnnt_sys_reg registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_cnnt_sys_reg:1;
+        /** write_ree0_cnnt_sys_reg : R/W; bitpos: [5]; default: 0;
+         *  Configures cnnt_sys_reg registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_cnnt_sys_reg:1;
+        /** write_ree1_cnnt_sys_reg : R/W; bitpos: [6]; default: 0;
+         *  Configures cnnt_sys_reg registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_cnnt_sys_reg:1;
+        /** write_ree2_cnnt_sys_reg : R/W; bitpos: [7]; default: 0;
+         *  Configures cnnt_sys_reg registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_cnnt_sys_reg:1;
+        /** cnnt_sys_reg_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock cnnt_sys_reg peri_apm configuration
+         */
+        uint32_t cnnt_sys_reg_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_cnnt_sys_reg_ctrl_reg_t;
+
+/** Type of hp_flash_ctrl register
+ *  hp_flash read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_flash : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_flash registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_flash:1;
+        /** read_ree0_hp_flash : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_flash registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_flash:1;
+        /** read_ree1_hp_flash : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_flash registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_flash:1;
+        /** read_ree2_hp_flash : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_flash registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_flash:1;
+        /** write_tee_hp_flash : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_flash registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_flash:1;
+        /** write_ree0_hp_flash : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_flash registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_flash:1;
+        /** write_ree1_hp_flash : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_flash registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_flash:1;
+        /** write_ree2_hp_flash : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_flash registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_flash:1;
+        /** hp_flash_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_flash peri_apm configuration
+         */
+        uint32_t hp_flash_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_flash_ctrl_reg_t;
+
+/** Type of hp_psram_ctrl register
+ *  hp_psram read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_psram : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_psram registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_psram:1;
+        /** read_ree0_hp_psram : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_psram registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_psram:1;
+        /** read_ree1_hp_psram : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_psram registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_psram:1;
+        /** read_ree2_hp_psram : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_psram registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_psram:1;
+        /** write_tee_hp_psram : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_psram registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_psram:1;
+        /** write_ree0_hp_psram : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_psram registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_psram:1;
+        /** write_ree1_hp_psram : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_psram registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_psram:1;
+        /** write_ree2_hp_psram : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_psram registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_psram:1;
+        /** hp_psram_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_psram peri_apm configuration
+         */
+        uint32_t hp_psram_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_psram_ctrl_reg_t;
+
+/** Type of tee_ctrl register
+ *  tee read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_tee : R/W; bitpos: [0]; default: 1;
+         *  Configures tee registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_tee:1;
+        /** read_ree0_tee : HRO; bitpos: [1]; default: 0;
+         *  Configures tee registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_tee:1;
+        /** read_ree1_tee : HRO; bitpos: [2]; default: 0;
+         *  Configures tee registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_tee:1;
+        /** read_ree2_tee : HRO; bitpos: [3]; default: 0;
+         *  Configures tee registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_tee:1;
+        /** write_tee_tee : R/W; bitpos: [4]; default: 1;
+         *  Configures tee registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_tee:1;
+        /** write_ree0_tee : HRO; bitpos: [5]; default: 0;
+         *  Configures tee registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_tee:1;
+        /** write_ree1_tee : HRO; bitpos: [6]; default: 0;
+         *  Configures tee registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_tee:1;
+        /** write_ree2_tee : HRO; bitpos: [7]; default: 0;
+         *  Configures tee registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_tee:1;
+        /** tee_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock tee peri_apm configuration
+         */
+        uint32_t tee_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_tee_ctrl_reg_t;
+
+/** Type of hp_apm_ctrl register
+ *  hp_apm read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_apm : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_apm registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_apm:1;
+        /** read_ree0_hp_apm : HRO; bitpos: [1]; default: 0;
+         *  Configures hp_apm registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_apm:1;
+        /** read_ree1_hp_apm : HRO; bitpos: [2]; default: 0;
+         *  Configures hp_apm registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_apm:1;
+        /** read_ree2_hp_apm : HRO; bitpos: [3]; default: 0;
+         *  Configures hp_apm registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_apm:1;
+        /** write_tee_hp_apm : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_apm registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_apm:1;
+        /** write_ree0_hp_apm : HRO; bitpos: [5]; default: 0;
+         *  Configures hp_apm registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_apm:1;
+        /** write_ree1_hp_apm : HRO; bitpos: [6]; default: 0;
+         *  Configures hp_apm registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_apm:1;
+        /** write_ree2_hp_apm : HRO; bitpos: [7]; default: 0;
+         *  Configures hp_apm registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_apm:1;
+        /** hp_apm_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_apm peri_apm configuration
+         */
+        uint32_t hp_apm_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_apm_ctrl_reg_t;
+
+/** Type of hp_mem_apm_ctrl register
+ *  hp_mem_apm read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mem_apm : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mem_apm registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mem_apm:1;
+        /** read_ree0_hp_mem_apm : HRO; bitpos: [1]; default: 0;
+         *  Configures hp_mem_apm registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mem_apm:1;
+        /** read_ree1_hp_mem_apm : HRO; bitpos: [2]; default: 0;
+         *  Configures hp_mem_apm registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mem_apm:1;
+        /** read_ree2_hp_mem_apm : HRO; bitpos: [3]; default: 0;
+         *  Configures hp_mem_apm registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mem_apm:1;
+        /** write_tee_hp_mem_apm : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mem_apm registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mem_apm:1;
+        /** write_ree0_hp_mem_apm : HRO; bitpos: [5]; default: 0;
+         *  Configures hp_mem_apm registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mem_apm:1;
+        /** write_ree1_hp_mem_apm : HRO; bitpos: [6]; default: 0;
+         *  Configures hp_mem_apm registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mem_apm:1;
+        /** write_ree2_hp_mem_apm : HRO; bitpos: [7]; default: 0;
+         *  Configures hp_mem_apm registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mem_apm:1;
+        /** hp_mem_apm_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mem_apm peri_apm configuration
+         */
+        uint32_t hp_mem_apm_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_mem_apm_ctrl_reg_t;
+
+/** Type of cpu_apm_ctrl register
+ *  cpu_apm read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_cpu_apm : R/W; bitpos: [0]; default: 1;
+         *  Configures cpu_apm registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_cpu_apm:1;
+        /** read_ree0_cpu_apm : HRO; bitpos: [1]; default: 0;
+         *  Configures cpu_apm registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_cpu_apm:1;
+        /** read_ree1_cpu_apm : HRO; bitpos: [2]; default: 0;
+         *  Configures cpu_apm registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_cpu_apm:1;
+        /** read_ree2_cpu_apm : HRO; bitpos: [3]; default: 0;
+         *  Configures cpu_apm registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_cpu_apm:1;
+        /** write_tee_cpu_apm : R/W; bitpos: [4]; default: 1;
+         *  Configures cpu_apm registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_cpu_apm:1;
+        /** write_ree0_cpu_apm : HRO; bitpos: [5]; default: 0;
+         *  Configures cpu_apm registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_cpu_apm:1;
+        /** write_ree1_cpu_apm : HRO; bitpos: [6]; default: 0;
+         *  Configures cpu_apm registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_cpu_apm:1;
+        /** write_ree2_cpu_apm : HRO; bitpos: [7]; default: 0;
+         *  Configures cpu_apm registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_cpu_apm:1;
+        /** cpu_apm_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock cpu_apm peri_apm configuration
+         */
+        uint32_t cpu_apm_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_cpu_apm_ctrl_reg_t;
+
+/** Type of hp_peri0_pms_ctrl register
+ *  hp_peri0_pms read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_peri0_pms : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_peri0_pms registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_peri0_pms:1;
+        /** read_ree0_hp_peri0_pms : HRO; bitpos: [1]; default: 0;
+         *  Configures hp_peri0_pms registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_peri0_pms:1;
+        /** read_ree1_hp_peri0_pms : HRO; bitpos: [2]; default: 0;
+         *  Configures hp_peri0_pms registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_peri0_pms:1;
+        /** read_ree2_hp_peri0_pms : HRO; bitpos: [3]; default: 0;
+         *  Configures hp_peri0_pms registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_peri0_pms:1;
+        /** write_tee_hp_peri0_pms : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_peri0_pms registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_peri0_pms:1;
+        /** write_ree0_hp_peri0_pms : HRO; bitpos: [5]; default: 0;
+         *  Configures hp_peri0_pms registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_peri0_pms:1;
+        /** write_ree1_hp_peri0_pms : HRO; bitpos: [6]; default: 0;
+         *  Configures hp_peri0_pms registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_peri0_pms:1;
+        /** write_ree2_hp_peri0_pms : HRO; bitpos: [7]; default: 0;
+         *  Configures hp_peri0_pms registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_peri0_pms:1;
+        /** hp_peri0_pms_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_peri0_pms peri_apm configuration
+         */
+        uint32_t hp_peri0_pms_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_peri0_pms_ctrl_reg_t;
+
+/** Type of hp_key_manager_ctrl register
+ *  hp_key_manager read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_key_manager : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_key_manager registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_key_manager:1;
+        /** read_ree0_hp_key_manager : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_key_manager registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_key_manager:1;
+        /** read_ree1_hp_key_manager : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_key_manager registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_key_manager:1;
+        /** read_ree2_hp_key_manager : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_key_manager registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_key_manager:1;
+        /** write_tee_hp_key_manager : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_key_manager registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_key_manager:1;
+        /** write_ree0_hp_key_manager : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_key_manager registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_key_manager:1;
+        /** write_ree1_hp_key_manager : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_key_manager registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_key_manager:1;
+        /** write_ree2_hp_key_manager : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_key_manager registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_key_manager:1;
+        /** hp_key_manager_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_key_manager peri_apm configuration
+         */
+        uint32_t hp_key_manager_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_key_manager_ctrl_reg_t;
+
+/** Type of hp_crypto_ctrl register
+ *  hp_crypto read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_crypto : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_crypto registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_crypto:1;
+        /** read_ree0_hp_crypto : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_crypto registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_crypto:1;
+        /** read_ree1_hp_crypto : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_crypto registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_crypto:1;
+        /** read_ree2_hp_crypto : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_crypto registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_crypto:1;
+        /** write_tee_hp_crypto : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_crypto registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_crypto:1;
+        /** write_ree0_hp_crypto : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_crypto registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_crypto:1;
+        /** write_ree1_hp_crypto : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_crypto registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_crypto:1;
+        /** write_ree2_hp_crypto : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_crypto registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_crypto:1;
+        /** hp_crypto_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_crypto peri_apm configuration
+         */
+        uint32_t hp_crypto_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_crypto_ctrl_reg_t;
+
+/** Type of hp_axi_icm_ctrl register
+ *  hp_axi_icm read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_axi_icm : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_axi_icm registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_axi_icm:1;
+        /** read_ree0_hp_axi_icm : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_axi_icm registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_axi_icm:1;
+        /** read_ree1_hp_axi_icm : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_axi_icm registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_axi_icm:1;
+        /** read_ree2_hp_axi_icm : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_axi_icm registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_axi_icm:1;
+        /** write_tee_hp_axi_icm : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_axi_icm registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_axi_icm:1;
+        /** write_ree0_hp_axi_icm : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_axi_icm registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_axi_icm:1;
+        /** write_ree1_hp_axi_icm : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_axi_icm registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_axi_icm:1;
+        /** write_ree2_hp_axi_icm : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_axi_icm registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_axi_icm:1;
+        /** hp_axi_icm_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_axi_icm peri_apm configuration
+         */
+        uint32_t hp_axi_icm_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_axi_icm_ctrl_reg_t;
+
+/** Type of axi_perf_mon_ctrl register
+ *  axi_perf_mon read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_axi_perf_mon : R/W; bitpos: [0]; default: 1;
+         *  Configures axi_perf_mon registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_axi_perf_mon:1;
+        /** read_ree0_axi_perf_mon : R/W; bitpos: [1]; default: 0;
+         *  Configures axi_perf_mon registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_axi_perf_mon:1;
+        /** read_ree1_axi_perf_mon : R/W; bitpos: [2]; default: 0;
+         *  Configures axi_perf_mon registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_axi_perf_mon:1;
+        /** read_ree2_axi_perf_mon : R/W; bitpos: [3]; default: 0;
+         *  Configures axi_perf_mon registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_axi_perf_mon:1;
+        /** write_tee_axi_perf_mon : R/W; bitpos: [4]; default: 1;
+         *  Configures axi_perf_mon registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_axi_perf_mon:1;
+        /** write_ree0_axi_perf_mon : R/W; bitpos: [5]; default: 0;
+         *  Configures axi_perf_mon registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_axi_perf_mon:1;
+        /** write_ree1_axi_perf_mon : R/W; bitpos: [6]; default: 0;
+         *  Configures axi_perf_mon registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_axi_perf_mon:1;
+        /** write_ree2_axi_perf_mon : R/W; bitpos: [7]; default: 0;
+         *  Configures axi_perf_mon registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_axi_perf_mon:1;
+        /** axi_perf_mon_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock axi_perf_mon peri_apm configuration
+         */
+        uint32_t axi_perf_mon_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri0_pms_axi_perf_mon_ctrl_reg_t;
+
+
+/** Group: PMS Register */
+/** Type of hp_cpuperi0_0 register
+ *  HP_CPUPERI0 PMS configuration & info register
+ */
+typedef union {
+    struct {
+        /** hp_cpuperi0_pms_exception_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear hp_cpuperi0 peri_pms_record_reg.
+         *  0: No clear
+         *  1: Clear peri_pms_record_reg
+         */
+        uint32_t hp_cpuperi0_pms_exception_clr:1;
+        /** hp_cpuperi0_pms_exception_det : RO; bitpos: [1]; default: 0;
+         *  Represents whether the hp_cpuperi0 pms has been triggered.
+         *  0: No triggered
+         *  1: Has been triggered
+         */
+        uint32_t hp_cpuperi0_pms_exception_det:1;
+        /** hp_cpuperi0_pms_exception_id : RO; bitpos: [7:2]; default: 0;
+         *  Represents the master id when hp_cpuperi0 pms has been triggered.
+         */
+        uint32_t hp_cpuperi0_pms_exception_id:6;
+        /** hp_cpuperi0_pms_exception_mode : RO; bitpos: [9:8]; default: 0;
+         *  Represents the security mode when hp_cpuperi0 pms has been triggered.
+         */
+        uint32_t hp_cpuperi0_pms_exception_mode:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_cpuperi0_0_reg_t;
+
+/** Type of hp_cpuperi0_1 register
+ *  HP_CPUPERI0 PMS exception addr record register
+ */
+typedef union {
+    struct {
+        /** hp_cpuperi0_pms_exception_addr : RO; bitpos: [27:0]; default: 0;
+         *  Represents the access address (bit27~bit0) when hp_cpuperi0 pms has been triggered.
+         */
+        uint32_t hp_cpuperi0_pms_exception_addr:28;
+        /** hp_cpuperi0_pms_exception_addr_const : HRO; bitpos: [31:28]; default: 2;
+         *  Represents the access address (bit31~bit28) when hp_cpuperi0 pms has been triggered.
+         */
+        uint32_t hp_cpuperi0_pms_exception_addr_const:4;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_cpuperi0_1_reg_t;
+
+/** Type of hp_cpuperi1_0 register
+ *  HP_CPUPERI1 PMS configuration & info register
+ */
+typedef union {
+    struct {
+        /** hp_cpuperi1_pms_exception_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear hp_cpuperi1 peri_pms_record_reg.
+         *  0: No clear
+         *  1: Clear peri_pms_record_reg
+         */
+        uint32_t hp_cpuperi1_pms_exception_clr:1;
+        /** hp_cpuperi1_pms_exception_det : RO; bitpos: [1]; default: 0;
+         *  Represents whether the hp_cpuperi1 pms has been triggered.
+         *  0: No triggered
+         *  1: Has been triggered
+         */
+        uint32_t hp_cpuperi1_pms_exception_det:1;
+        /** hp_cpuperi1_pms_exception_id : RO; bitpos: [7:2]; default: 0;
+         *  Represents the master id when hp_cpuperi1 pms has been triggered.
+         */
+        uint32_t hp_cpuperi1_pms_exception_id:6;
+        /** hp_cpuperi1_pms_exception_mode : RO; bitpos: [9:8]; default: 0;
+         *  Represents the security mode when hp_cpuperi1 pms has been triggered.
+         */
+        uint32_t hp_cpuperi1_pms_exception_mode:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_cpuperi1_0_reg_t;
+
+/** Type of hp_cpuperi1_1 register
+ *  HP_CPUPERI1 PMS exception addr record register
+ */
+typedef union {
+    struct {
+        /** hp_cpuperi1_pms_exception_addr : RO; bitpos: [27:0]; default: 0;
+         *  Represents the access address (bit27~bit0) when hp_cpuperi1 pms has been triggered.
+         */
+        uint32_t hp_cpuperi1_pms_exception_addr:28;
+        /** hp_cpuperi1_pms_exception_addr_const : HRO; bitpos: [31:28]; default: 2;
+         *  Represents the access address (bit31~bit28) when hp_cpuperi1 pms has been triggered.
+         */
+        uint32_t hp_cpuperi1_pms_exception_addr_const:4;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_cpuperi1_1_reg_t;
+
+/** Type of hp_peri0_0 register
+ *  HP_PERI0 PMS configuration & info register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_pms_exception_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear hp_peri0 peri_pms_record_reg.
+         *  0: No clear
+         *  1: Clear peri_pms_record_reg
+         */
+        uint32_t hp_peri0_pms_exception_clr:1;
+        /** hp_peri0_pms_exception_det : RO; bitpos: [1]; default: 0;
+         *  Represents whether the hp_peri0 pms has been triggered.
+         *  0: No triggered
+         *  1: Has been triggered
+         */
+        uint32_t hp_peri0_pms_exception_det:1;
+        /** hp_peri0_pms_exception_id : RO; bitpos: [7:2]; default: 0;
+         *  Represents the master id when hp_peri0 pms has been triggered.
+         */
+        uint32_t hp_peri0_pms_exception_id:6;
+        /** hp_peri0_pms_exception_mode : RO; bitpos: [9:8]; default: 0;
+         *  Represents the security mode when hp_peri0 pms has been triggered.
+         */
+        uint32_t hp_peri0_pms_exception_mode:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_peri0_0_reg_t;
+
+/** Type of hp_peri0_1 register
+ *  HP_PERI0 PMS exception addr record register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_pms_exception_addr : RO; bitpos: [27:0]; default: 0;
+         *  Represents the access address (bit27~bit0) when hp_peri0 pms has been triggered.
+         */
+        uint32_t hp_peri0_pms_exception_addr:28;
+        /** hp_peri0_pms_exception_addr_const : HRO; bitpos: [31:28]; default: 2;
+         *  Represents the access address (bit31~bit28) when hp_peri0 pms has been triggered.
+         */
+        uint32_t hp_peri0_pms_exception_addr_const:4;
+    };
+    uint32_t val;
+} hp_peri0_pms_hp_peri0_1_reg_t;
+
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_pms_int_en : R/W; bitpos: [0]; default: 0;
+         *  Configures to enable hp_peri0 pms interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t hp_peri0_pms_int_en:1;
+        /** hp_cpuperi1_pms_int_en : R/W; bitpos: [1]; default: 0;
+         *  Configures to enable hp_cpuperi1 pms interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t hp_cpuperi1_pms_int_en:1;
+        /** hp_cpuperi0_pms_int_en : R/W; bitpos: [2]; default: 0;
+         *  Configures to enable hp_cpuperi0 pms interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t hp_cpuperi0_pms_int_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_peri0_pms_int_en_reg_t;
+
+
+/** Group: config register */
+/** Type of bus_err_conf register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether return error response to cpu when access blocked
+         *  0: disable error response
+         *  1: enable error response
+         */
+        uint32_t bus_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri0_pms_bus_err_conf_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: enable automatic clock gating
+         *  1: keep the clock always on
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri0_pms_clock_gate_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38834736;
+         *  Version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_peri0_pms_date_reg_t;
+
+
+typedef struct {
+    volatile hp_peri0_pms_trace0_ctrl_reg_t trace0_ctrl;
+    volatile hp_peri0_pms_trace1_ctrl_reg_t trace1_ctrl;
+    volatile hp_peri0_pms_cpu_bus_mon_ctrl_reg_t cpu_bus_mon_ctrl;
+    volatile hp_peri0_pms_psram_mon_ctrl_reg_t psram_mon_ctrl;
+    volatile hp_peri0_pms_tcm_mon_ctrl_reg_t tcm_mon_ctrl;
+    volatile hp_peri0_pms_cache_ctrl_reg_t cache_ctrl;
+    volatile hp_peri0_pms_hp_usbotg_core_ctrl_reg_t hp_usbotg_core_ctrl;
+    volatile hp_peri0_pms_hp_regdma_ctrl_reg_t hp_regdma_ctrl;
+    volatile hp_peri0_pms_hp_sdmmc_ctrl_reg_t hp_sdmmc_ctrl;
+    volatile hp_peri0_pms_hp_ahb_pdma_ctrl_reg_t hp_ahb_pdma_ctrl;
+    volatile hp_peri0_pms_hp_jpeg_ctrl_reg_t hp_jpeg_ctrl;
+    volatile hp_peri0_pms_hp_ppa_ctrl_reg_t hp_ppa_ctrl;
+    volatile hp_peri0_pms_hp_dma2d_ctrl_reg_t hp_dma2d_ctrl;
+    volatile hp_peri0_pms_hp_axi_pdma_ctrl_reg_t hp_axi_pdma_ctrl;
+    volatile hp_peri0_pms_hp_gmac_ctrl_reg_t hp_gmac_ctrl;
+    volatile hp_peri0_pms_hp_pvt0_ctrl_reg_t hp_pvt0_ctrl;
+    volatile hp_peri0_pms_hp_rmt_ctrl_reg_t hp_rmt_ctrl;
+    volatile hp_peri0_pms_hp_bitsrambler_ctrl_reg_t hp_bitsrambler_ctrl;
+    volatile hp_peri0_pms_hp_asrc_ctrl_reg_t hp_asrc_ctrl;
+    volatile hp_peri0_pms_cnnt_sys_reg_ctrl_reg_t cnnt_sys_reg_ctrl;
+    volatile hp_peri0_pms_hp_flash_ctrl_reg_t hp_flash_ctrl;
+    volatile hp_peri0_pms_hp_psram_ctrl_reg_t hp_psram_ctrl;
+    volatile hp_peri0_pms_tee_ctrl_reg_t tee_ctrl;
+    volatile hp_peri0_pms_hp_apm_ctrl_reg_t hp_apm_ctrl;
+    volatile hp_peri0_pms_hp_mem_apm_ctrl_reg_t hp_mem_apm_ctrl;
+    volatile hp_peri0_pms_cpu_apm_ctrl_reg_t cpu_apm_ctrl;
+    volatile hp_peri0_pms_hp_peri0_pms_ctrl_reg_t hp_peri0_pms_ctrl;
+    volatile hp_peri0_pms_hp_key_manager_ctrl_reg_t hp_key_manager_ctrl;
+    volatile hp_peri0_pms_hp_crypto_ctrl_reg_t hp_crypto_ctrl;
+    volatile hp_peri0_pms_hp_axi_icm_ctrl_reg_t hp_axi_icm_ctrl;
+    volatile hp_peri0_pms_axi_perf_mon_ctrl_reg_t axi_perf_mon_ctrl;
+    uint32_t reserved_07c[97];
+    volatile hp_peri0_pms_hp_cpuperi0_0_reg_t hp_cpuperi0_0;
+    volatile hp_peri0_pms_hp_cpuperi0_1_reg_t hp_cpuperi0_1;
+    volatile hp_peri0_pms_hp_cpuperi1_0_reg_t hp_cpuperi1_0;
+    volatile hp_peri0_pms_hp_cpuperi1_1_reg_t hp_cpuperi1_1;
+    volatile hp_peri0_pms_hp_peri0_0_reg_t hp_peri0_0;
+    volatile hp_peri0_pms_hp_peri0_1_reg_t hp_peri0_1;
+    uint32_t reserved_218[58];
+    volatile hp_peri0_pms_int_en_reg_t int_en;
+    uint32_t reserved_304[827];
+    volatile hp_peri0_pms_bus_err_conf_reg_t bus_err_conf;
+    uint32_t reserved_ff4;
+    volatile hp_peri0_pms_clock_gate_reg_t clock_gate;
+    volatile hp_peri0_pms_date_reg_t date;
+} hp_peri0_pms_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_peri0_pms_dev_t) == 0x1000, "Invalid size of hp_peri0_pms_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_peri1_pms_reg.h b/components/soc/esp32s31/register/soc/hp_peri1_pms_reg.h
new file mode 100644
index 00000000000..06cff8e3ff5
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_peri1_pms_reg.h
@@ -0,0 +1,3402 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG register
+ *  hp_usbotg_phy read/write control register
+ */
+#define HP_PERI1_PMS_HP_USBOTG_PHY_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x0)
+/** HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_usbotg_phy registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY_M  (HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY_V << HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_USBOTG_PHY_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_usbotg_phy registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY_M  (HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY_V << HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_USBOTG_PHY_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_usbotg_phy registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY_M  (HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY_V << HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_USBOTG_PHY_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_usbotg_phy registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY_M  (HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY_V << HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_USBOTG_PHY_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_usbotg_phy registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY_M  (HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY_V << HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBOTG_PHY_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_usbotg_phy registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY_M  (HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY_V << HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBOTG_PHY_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_usbotg_phy registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY_M  (HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY_V << HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBOTG_PHY_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_usbotg_phy registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY_M  (HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY_V << HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBOTG_PHY_S  7
+/** HP_PERI1_PMS_HP_USBOTG_PHY_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_usbotg_phy peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_USBOTG_PHY_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_USBOTG_PHY_LOCK_M  (HP_PERI1_PMS_HP_USBOTG_PHY_LOCK_V << HP_PERI1_PMS_HP_USBOTG_PHY_LOCK_S)
+#define HP_PERI1_PMS_HP_USBOTG_PHY_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_USBOTG_PHY_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_MCPWM0_CTRL_REG register
+ *  hp_mcpwm0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_MCPWM0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x4)
+/** HP_PERI1_PMS_READ_TEE_HP_MCPWM0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mcpwm0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM0_M  (HP_PERI1_PMS_READ_TEE_HP_MCPWM0_V << HP_PERI1_PMS_READ_TEE_HP_MCPWM0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_MCPWM0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_mcpwm0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM0_M  (HP_PERI1_PMS_READ_REE0_HP_MCPWM0_V << HP_PERI1_PMS_READ_REE0_HP_MCPWM0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_MCPWM0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_mcpwm0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM0_M  (HP_PERI1_PMS_READ_REE1_HP_MCPWM0_V << HP_PERI1_PMS_READ_REE1_HP_MCPWM0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_MCPWM0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_mcpwm0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM0_M  (HP_PERI1_PMS_READ_REE2_HP_MCPWM0_V << HP_PERI1_PMS_READ_REE2_HP_MCPWM0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mcpwm0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0_M  (HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0_V << HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_mcpwm0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0_M  (HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0_V << HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_mcpwm0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0_M  (HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0_V << HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_mcpwm0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0_M  (HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0_V << HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM0_S  7
+/** HP_PERI1_PMS_HP_MCPWM0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mcpwm0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_MCPWM0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_MCPWM0_LOCK_M  (HP_PERI1_PMS_HP_MCPWM0_LOCK_V << HP_PERI1_PMS_HP_MCPWM0_LOCK_S)
+#define HP_PERI1_PMS_HP_MCPWM0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_MCPWM0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_MCPWM1_CTRL_REG register
+ *  hp_mcpwm1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_MCPWM1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x8)
+/** HP_PERI1_PMS_READ_TEE_HP_MCPWM1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mcpwm1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM1_M  (HP_PERI1_PMS_READ_TEE_HP_MCPWM1_V << HP_PERI1_PMS_READ_TEE_HP_MCPWM1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_MCPWM1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_mcpwm1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM1_M  (HP_PERI1_PMS_READ_REE0_HP_MCPWM1_V << HP_PERI1_PMS_READ_REE0_HP_MCPWM1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_MCPWM1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_mcpwm1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM1_M  (HP_PERI1_PMS_READ_REE1_HP_MCPWM1_V << HP_PERI1_PMS_READ_REE1_HP_MCPWM1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_MCPWM1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_mcpwm1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM1_M  (HP_PERI1_PMS_READ_REE2_HP_MCPWM1_V << HP_PERI1_PMS_READ_REE2_HP_MCPWM1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mcpwm1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1_M  (HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1_V << HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_mcpwm1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1_M  (HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1_V << HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_mcpwm1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1_M  (HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1_V << HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_mcpwm1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1_M  (HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1_V << HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM1_S  7
+/** HP_PERI1_PMS_HP_MCPWM1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mcpwm1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_MCPWM1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_MCPWM1_LOCK_M  (HP_PERI1_PMS_HP_MCPWM1_LOCK_V << HP_PERI1_PMS_HP_MCPWM1_LOCK_S)
+#define HP_PERI1_PMS_HP_MCPWM1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_MCPWM1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_MCPWM2_CTRL_REG register
+ *  hp_mcpwm2 read/write control register
+ */
+#define HP_PERI1_PMS_HP_MCPWM2_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0xc)
+/** HP_PERI1_PMS_READ_TEE_HP_MCPWM2 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mcpwm2 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM2    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM2_M  (HP_PERI1_PMS_READ_TEE_HP_MCPWM2_V << HP_PERI1_PMS_READ_TEE_HP_MCPWM2_S)
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM2_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_MCPWM2 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_mcpwm2 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM2    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM2_M  (HP_PERI1_PMS_READ_REE0_HP_MCPWM2_V << HP_PERI1_PMS_READ_REE0_HP_MCPWM2_S)
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM2_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_MCPWM2 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_mcpwm2 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM2    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM2_M  (HP_PERI1_PMS_READ_REE1_HP_MCPWM2_V << HP_PERI1_PMS_READ_REE1_HP_MCPWM2_S)
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM2_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_MCPWM2 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_mcpwm2 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM2    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM2_M  (HP_PERI1_PMS_READ_REE2_HP_MCPWM2_V << HP_PERI1_PMS_READ_REE2_HP_MCPWM2_S)
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM2_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mcpwm2 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2_M  (HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2_V << HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM2_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_mcpwm2 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2_M  (HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2_V << HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM2_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_mcpwm2 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2_M  (HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2_V << HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM2_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_mcpwm2 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2_M  (HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2_V << HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM2_S  7
+/** HP_PERI1_PMS_HP_MCPWM2_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mcpwm2 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_MCPWM2_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_MCPWM2_LOCK_M  (HP_PERI1_PMS_HP_MCPWM2_LOCK_V << HP_PERI1_PMS_HP_MCPWM2_LOCK_S)
+#define HP_PERI1_PMS_HP_MCPWM2_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_MCPWM2_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_MCPWM3_CTRL_REG register
+ *  hp_mcpwm3 read/write control register
+ */
+#define HP_PERI1_PMS_HP_MCPWM3_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x10)
+/** HP_PERI1_PMS_READ_TEE_HP_MCPWM3 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mcpwm3 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM3    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM3_M  (HP_PERI1_PMS_READ_TEE_HP_MCPWM3_V << HP_PERI1_PMS_READ_TEE_HP_MCPWM3_S)
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_MCPWM3_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_MCPWM3 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_mcpwm3 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM3    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM3_M  (HP_PERI1_PMS_READ_REE0_HP_MCPWM3_V << HP_PERI1_PMS_READ_REE0_HP_MCPWM3_S)
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_MCPWM3_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_MCPWM3 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_mcpwm3 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM3    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM3_M  (HP_PERI1_PMS_READ_REE1_HP_MCPWM3_V << HP_PERI1_PMS_READ_REE1_HP_MCPWM3_S)
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_MCPWM3_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_MCPWM3 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_mcpwm3 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM3    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM3_M  (HP_PERI1_PMS_READ_REE2_HP_MCPWM3_V << HP_PERI1_PMS_READ_REE2_HP_MCPWM3_S)
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_MCPWM3_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mcpwm3 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3_M  (HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3_V << HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_MCPWM3_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_mcpwm3 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3_M  (HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3_V << HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_MCPWM3_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_mcpwm3 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3_M  (HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3_V << HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_MCPWM3_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_mcpwm3 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3_M  (HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3_V << HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_MCPWM3_S  7
+/** HP_PERI1_PMS_HP_MCPWM3_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mcpwm3 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_MCPWM3_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_MCPWM3_LOCK_M  (HP_PERI1_PMS_HP_MCPWM3_LOCK_V << HP_PERI1_PMS_HP_MCPWM3_LOCK_S)
+#define HP_PERI1_PMS_HP_MCPWM3_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_MCPWM3_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_I2C0_CTRL_REG register
+ *  hp_i2c0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_I2C0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x14)
+/** HP_PERI1_PMS_READ_TEE_HP_I2C0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_i2c0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_I2C0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_I2C0_M  (HP_PERI1_PMS_READ_TEE_HP_I2C0_V << HP_PERI1_PMS_READ_TEE_HP_I2C0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_I2C0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_I2C0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_i2c0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_I2C0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_I2C0_M  (HP_PERI1_PMS_READ_REE0_HP_I2C0_V << HP_PERI1_PMS_READ_REE0_HP_I2C0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_I2C0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_I2C0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_i2c0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_I2C0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_I2C0_M  (HP_PERI1_PMS_READ_REE1_HP_I2C0_V << HP_PERI1_PMS_READ_REE1_HP_I2C0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_I2C0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_I2C0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_i2c0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_I2C0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_I2C0_M  (HP_PERI1_PMS_READ_REE2_HP_I2C0_V << HP_PERI1_PMS_READ_REE2_HP_I2C0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_I2C0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_I2C0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_i2c0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C0_M  (HP_PERI1_PMS_WRITE_TEE_HP_I2C0_V << HP_PERI1_PMS_WRITE_TEE_HP_I2C0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_I2C0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_i2c0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C0_M  (HP_PERI1_PMS_WRITE_REE0_HP_I2C0_V << HP_PERI1_PMS_WRITE_REE0_HP_I2C0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_I2C0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_i2c0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C0_M  (HP_PERI1_PMS_WRITE_REE1_HP_I2C0_V << HP_PERI1_PMS_WRITE_REE1_HP_I2C0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_I2C0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_i2c0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C0_M  (HP_PERI1_PMS_WRITE_REE2_HP_I2C0_V << HP_PERI1_PMS_WRITE_REE2_HP_I2C0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C0_S  7
+/** HP_PERI1_PMS_HP_I2C0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_i2c0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_I2C0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_I2C0_LOCK_M  (HP_PERI1_PMS_HP_I2C0_LOCK_V << HP_PERI1_PMS_HP_I2C0_LOCK_S)
+#define HP_PERI1_PMS_HP_I2C0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_I2C0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_I2C1_CTRL_REG register
+ *  hp_i2c1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_I2C1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x18)
+/** HP_PERI1_PMS_READ_TEE_HP_I2C1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_i2c1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_I2C1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_I2C1_M  (HP_PERI1_PMS_READ_TEE_HP_I2C1_V << HP_PERI1_PMS_READ_TEE_HP_I2C1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_I2C1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_I2C1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_i2c1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_I2C1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_I2C1_M  (HP_PERI1_PMS_READ_REE0_HP_I2C1_V << HP_PERI1_PMS_READ_REE0_HP_I2C1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_I2C1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_I2C1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_i2c1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_I2C1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_I2C1_M  (HP_PERI1_PMS_READ_REE1_HP_I2C1_V << HP_PERI1_PMS_READ_REE1_HP_I2C1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_I2C1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_I2C1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_i2c1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_I2C1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_I2C1_M  (HP_PERI1_PMS_READ_REE2_HP_I2C1_V << HP_PERI1_PMS_READ_REE2_HP_I2C1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_I2C1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_I2C1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_i2c1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C1_M  (HP_PERI1_PMS_WRITE_TEE_HP_I2C1_V << HP_PERI1_PMS_WRITE_TEE_HP_I2C1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2C1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_I2C1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_i2c1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C1_M  (HP_PERI1_PMS_WRITE_REE0_HP_I2C1_V << HP_PERI1_PMS_WRITE_REE0_HP_I2C1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2C1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_I2C1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_i2c1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C1_M  (HP_PERI1_PMS_WRITE_REE1_HP_I2C1_V << HP_PERI1_PMS_WRITE_REE1_HP_I2C1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2C1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_I2C1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_i2c1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C1_M  (HP_PERI1_PMS_WRITE_REE2_HP_I2C1_V << HP_PERI1_PMS_WRITE_REE2_HP_I2C1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2C1_S  7
+/** HP_PERI1_PMS_HP_I2C1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_i2c1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_I2C1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_I2C1_LOCK_M  (HP_PERI1_PMS_HP_I2C1_LOCK_V << HP_PERI1_PMS_HP_I2C1_LOCK_S)
+#define HP_PERI1_PMS_HP_I2C1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_I2C1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_I2S0_CTRL_REG register
+ *  hp_i2s0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_I2S0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x1c)
+/** HP_PERI1_PMS_READ_TEE_HP_I2S0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_i2s0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_I2S0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_I2S0_M  (HP_PERI1_PMS_READ_TEE_HP_I2S0_V << HP_PERI1_PMS_READ_TEE_HP_I2S0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_I2S0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_I2S0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_i2s0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_I2S0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_I2S0_M  (HP_PERI1_PMS_READ_REE0_HP_I2S0_V << HP_PERI1_PMS_READ_REE0_HP_I2S0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_I2S0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_I2S0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_i2s0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_I2S0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_I2S0_M  (HP_PERI1_PMS_READ_REE1_HP_I2S0_V << HP_PERI1_PMS_READ_REE1_HP_I2S0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_I2S0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_I2S0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_i2s0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_I2S0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_I2S0_M  (HP_PERI1_PMS_READ_REE2_HP_I2S0_V << HP_PERI1_PMS_READ_REE2_HP_I2S0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_I2S0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_I2S0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_i2s0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S0_M  (HP_PERI1_PMS_WRITE_TEE_HP_I2S0_V << HP_PERI1_PMS_WRITE_TEE_HP_I2S0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_I2S0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_i2s0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S0_M  (HP_PERI1_PMS_WRITE_REE0_HP_I2S0_V << HP_PERI1_PMS_WRITE_REE0_HP_I2S0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_I2S0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_i2s0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S0_M  (HP_PERI1_PMS_WRITE_REE1_HP_I2S0_V << HP_PERI1_PMS_WRITE_REE1_HP_I2S0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_I2S0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_i2s0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S0_M  (HP_PERI1_PMS_WRITE_REE2_HP_I2S0_V << HP_PERI1_PMS_WRITE_REE2_HP_I2S0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S0_S  7
+/** HP_PERI1_PMS_HP_I2S0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_i2s0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_I2S0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_I2S0_LOCK_M  (HP_PERI1_PMS_HP_I2S0_LOCK_V << HP_PERI1_PMS_HP_I2S0_LOCK_S)
+#define HP_PERI1_PMS_HP_I2S0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_I2S0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_I2S1_CTRL_REG register
+ *  hp_i2s1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_I2S1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x20)
+/** HP_PERI1_PMS_READ_TEE_HP_I2S1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_i2s1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_I2S1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_I2S1_M  (HP_PERI1_PMS_READ_TEE_HP_I2S1_V << HP_PERI1_PMS_READ_TEE_HP_I2S1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_I2S1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_I2S1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_i2s1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_I2S1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_I2S1_M  (HP_PERI1_PMS_READ_REE0_HP_I2S1_V << HP_PERI1_PMS_READ_REE0_HP_I2S1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_I2S1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_I2S1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_i2s1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_I2S1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_I2S1_M  (HP_PERI1_PMS_READ_REE1_HP_I2S1_V << HP_PERI1_PMS_READ_REE1_HP_I2S1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_I2S1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_I2S1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_i2s1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_I2S1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_I2S1_M  (HP_PERI1_PMS_READ_REE2_HP_I2S1_V << HP_PERI1_PMS_READ_REE2_HP_I2S1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_I2S1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_I2S1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_i2s1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S1_M  (HP_PERI1_PMS_WRITE_TEE_HP_I2S1_V << HP_PERI1_PMS_WRITE_TEE_HP_I2S1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_I2S1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_I2S1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_i2s1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S1_M  (HP_PERI1_PMS_WRITE_REE0_HP_I2S1_V << HP_PERI1_PMS_WRITE_REE0_HP_I2S1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_I2S1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_I2S1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_i2s1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S1_M  (HP_PERI1_PMS_WRITE_REE1_HP_I2S1_V << HP_PERI1_PMS_WRITE_REE1_HP_I2S1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_I2S1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_I2S1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_i2s1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S1_M  (HP_PERI1_PMS_WRITE_REE2_HP_I2S1_V << HP_PERI1_PMS_WRITE_REE2_HP_I2S1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_I2S1_S  7
+/** HP_PERI1_PMS_HP_I2S1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_i2s1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_I2S1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_I2S1_LOCK_M  (HP_PERI1_PMS_HP_I2S1_LOCK_V << HP_PERI1_PMS_HP_I2S1_LOCK_S)
+#define HP_PERI1_PMS_HP_I2S1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_I2S1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_PCNT0_CTRL_REG register
+ *  hp_pcnt0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_PCNT0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x24)
+/** HP_PERI1_PMS_READ_TEE_HP_PCNT0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_pcnt0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT0_M  (HP_PERI1_PMS_READ_TEE_HP_PCNT0_V << HP_PERI1_PMS_READ_TEE_HP_PCNT0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_PCNT0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_pcnt0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT0_M  (HP_PERI1_PMS_READ_REE0_HP_PCNT0_V << HP_PERI1_PMS_READ_REE0_HP_PCNT0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_PCNT0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_pcnt0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT0_M  (HP_PERI1_PMS_READ_REE1_HP_PCNT0_V << HP_PERI1_PMS_READ_REE1_HP_PCNT0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_PCNT0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_pcnt0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT0_M  (HP_PERI1_PMS_READ_REE2_HP_PCNT0_V << HP_PERI1_PMS_READ_REE2_HP_PCNT0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_PCNT0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_pcnt0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT0_M  (HP_PERI1_PMS_WRITE_TEE_HP_PCNT0_V << HP_PERI1_PMS_WRITE_TEE_HP_PCNT0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_PCNT0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_pcnt0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT0_M  (HP_PERI1_PMS_WRITE_REE0_HP_PCNT0_V << HP_PERI1_PMS_WRITE_REE0_HP_PCNT0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_PCNT0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_pcnt0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT0_M  (HP_PERI1_PMS_WRITE_REE1_HP_PCNT0_V << HP_PERI1_PMS_WRITE_REE1_HP_PCNT0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_PCNT0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_pcnt0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT0_M  (HP_PERI1_PMS_WRITE_REE2_HP_PCNT0_V << HP_PERI1_PMS_WRITE_REE2_HP_PCNT0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT0_S  7
+/** HP_PERI1_PMS_HP_PCNT0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_pcnt0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_PCNT0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_PCNT0_LOCK_M  (HP_PERI1_PMS_HP_PCNT0_LOCK_V << HP_PERI1_PMS_HP_PCNT0_LOCK_S)
+#define HP_PERI1_PMS_HP_PCNT0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_PCNT0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_UART0_CTRL_REG register
+ *  hp_uart0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_UART0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x28)
+/** HP_PERI1_PMS_READ_TEE_HP_UART0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_uart0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_UART0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_UART0_M  (HP_PERI1_PMS_READ_TEE_HP_UART0_V << HP_PERI1_PMS_READ_TEE_HP_UART0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_UART0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_UART0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_uart0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_UART0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_UART0_M  (HP_PERI1_PMS_READ_REE0_HP_UART0_V << HP_PERI1_PMS_READ_REE0_HP_UART0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_UART0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_UART0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_uart0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_UART0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_UART0_M  (HP_PERI1_PMS_READ_REE1_HP_UART0_V << HP_PERI1_PMS_READ_REE1_HP_UART0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_UART0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_UART0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_uart0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_UART0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_UART0_M  (HP_PERI1_PMS_READ_REE2_HP_UART0_V << HP_PERI1_PMS_READ_REE2_HP_UART0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_UART0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_UART0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_uart0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART0_M  (HP_PERI1_PMS_WRITE_TEE_HP_UART0_V << HP_PERI1_PMS_WRITE_TEE_HP_UART0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_UART0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_uart0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART0_M  (HP_PERI1_PMS_WRITE_REE0_HP_UART0_V << HP_PERI1_PMS_WRITE_REE0_HP_UART0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_UART0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_uart0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART0_M  (HP_PERI1_PMS_WRITE_REE1_HP_UART0_V << HP_PERI1_PMS_WRITE_REE1_HP_UART0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_UART0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_uart0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART0_M  (HP_PERI1_PMS_WRITE_REE2_HP_UART0_V << HP_PERI1_PMS_WRITE_REE2_HP_UART0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART0_S  7
+/** HP_PERI1_PMS_HP_UART0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_uart0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_UART0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_UART0_LOCK_M  (HP_PERI1_PMS_HP_UART0_LOCK_V << HP_PERI1_PMS_HP_UART0_LOCK_S)
+#define HP_PERI1_PMS_HP_UART0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_UART0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_UART1_CTRL_REG register
+ *  hp_uart1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_UART1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x2c)
+/** HP_PERI1_PMS_READ_TEE_HP_UART1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_uart1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_UART1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_UART1_M  (HP_PERI1_PMS_READ_TEE_HP_UART1_V << HP_PERI1_PMS_READ_TEE_HP_UART1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_UART1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_UART1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_uart1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_UART1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_UART1_M  (HP_PERI1_PMS_READ_REE0_HP_UART1_V << HP_PERI1_PMS_READ_REE0_HP_UART1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_UART1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_UART1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_uart1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_UART1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_UART1_M  (HP_PERI1_PMS_READ_REE1_HP_UART1_V << HP_PERI1_PMS_READ_REE1_HP_UART1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_UART1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_UART1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_uart1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_UART1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_UART1_M  (HP_PERI1_PMS_READ_REE2_HP_UART1_V << HP_PERI1_PMS_READ_REE2_HP_UART1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_UART1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_UART1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_uart1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART1_M  (HP_PERI1_PMS_WRITE_TEE_HP_UART1_V << HP_PERI1_PMS_WRITE_TEE_HP_UART1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_UART1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_uart1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART1_M  (HP_PERI1_PMS_WRITE_REE0_HP_UART1_V << HP_PERI1_PMS_WRITE_REE0_HP_UART1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_UART1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_uart1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART1_M  (HP_PERI1_PMS_WRITE_REE1_HP_UART1_V << HP_PERI1_PMS_WRITE_REE1_HP_UART1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_UART1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_uart1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART1_M  (HP_PERI1_PMS_WRITE_REE2_HP_UART1_V << HP_PERI1_PMS_WRITE_REE2_HP_UART1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART1_S  7
+/** HP_PERI1_PMS_HP_UART1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_uart1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_UART1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_UART1_LOCK_M  (HP_PERI1_PMS_HP_UART1_LOCK_V << HP_PERI1_PMS_HP_UART1_LOCK_S)
+#define HP_PERI1_PMS_HP_UART1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_UART1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_UART2_CTRL_REG register
+ *  hp_uart2 read/write control register
+ */
+#define HP_PERI1_PMS_HP_UART2_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x30)
+/** HP_PERI1_PMS_READ_TEE_HP_UART2 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_uart2 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_UART2    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_UART2_M  (HP_PERI1_PMS_READ_TEE_HP_UART2_V << HP_PERI1_PMS_READ_TEE_HP_UART2_S)
+#define HP_PERI1_PMS_READ_TEE_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_UART2_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_UART2 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_uart2 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_UART2    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_UART2_M  (HP_PERI1_PMS_READ_REE0_HP_UART2_V << HP_PERI1_PMS_READ_REE0_HP_UART2_S)
+#define HP_PERI1_PMS_READ_REE0_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_UART2_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_UART2 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_uart2 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_UART2    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_UART2_M  (HP_PERI1_PMS_READ_REE1_HP_UART2_V << HP_PERI1_PMS_READ_REE1_HP_UART2_S)
+#define HP_PERI1_PMS_READ_REE1_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_UART2_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_UART2 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_uart2 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_UART2    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_UART2_M  (HP_PERI1_PMS_READ_REE2_HP_UART2_V << HP_PERI1_PMS_READ_REE2_HP_UART2_S)
+#define HP_PERI1_PMS_READ_REE2_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_UART2_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_UART2 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_uart2 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART2    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART2_M  (HP_PERI1_PMS_WRITE_TEE_HP_UART2_V << HP_PERI1_PMS_WRITE_TEE_HP_UART2_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART2_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_UART2 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_uart2 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART2    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART2_M  (HP_PERI1_PMS_WRITE_REE0_HP_UART2_V << HP_PERI1_PMS_WRITE_REE0_HP_UART2_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART2_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_UART2 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_uart2 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART2    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART2_M  (HP_PERI1_PMS_WRITE_REE1_HP_UART2_V << HP_PERI1_PMS_WRITE_REE1_HP_UART2_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART2_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_UART2 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_uart2 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART2    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART2_M  (HP_PERI1_PMS_WRITE_REE2_HP_UART2_V << HP_PERI1_PMS_WRITE_REE2_HP_UART2_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART2_S  7
+/** HP_PERI1_PMS_HP_UART2_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_uart2 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_UART2_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_UART2_LOCK_M  (HP_PERI1_PMS_HP_UART2_LOCK_V << HP_PERI1_PMS_HP_UART2_LOCK_S)
+#define HP_PERI1_PMS_HP_UART2_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_UART2_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_UART3_CTRL_REG register
+ *  hp_uart3 read/write control register
+ */
+#define HP_PERI1_PMS_HP_UART3_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x34)
+/** HP_PERI1_PMS_READ_TEE_HP_UART3 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_uart3 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_UART3    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_UART3_M  (HP_PERI1_PMS_READ_TEE_HP_UART3_V << HP_PERI1_PMS_READ_TEE_HP_UART3_S)
+#define HP_PERI1_PMS_READ_TEE_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_UART3_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_UART3 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_uart3 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_UART3    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_UART3_M  (HP_PERI1_PMS_READ_REE0_HP_UART3_V << HP_PERI1_PMS_READ_REE0_HP_UART3_S)
+#define HP_PERI1_PMS_READ_REE0_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_UART3_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_UART3 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_uart3 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_UART3    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_UART3_M  (HP_PERI1_PMS_READ_REE1_HP_UART3_V << HP_PERI1_PMS_READ_REE1_HP_UART3_S)
+#define HP_PERI1_PMS_READ_REE1_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_UART3_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_UART3 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_uart3 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_UART3    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_UART3_M  (HP_PERI1_PMS_READ_REE2_HP_UART3_V << HP_PERI1_PMS_READ_REE2_HP_UART3_S)
+#define HP_PERI1_PMS_READ_REE2_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_UART3_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_UART3 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_uart3 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART3    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART3_M  (HP_PERI1_PMS_WRITE_TEE_HP_UART3_V << HP_PERI1_PMS_WRITE_TEE_HP_UART3_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_UART3_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_UART3 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_uart3 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART3    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART3_M  (HP_PERI1_PMS_WRITE_REE0_HP_UART3_V << HP_PERI1_PMS_WRITE_REE0_HP_UART3_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_UART3_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_UART3 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_uart3 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART3    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART3_M  (HP_PERI1_PMS_WRITE_REE1_HP_UART3_V << HP_PERI1_PMS_WRITE_REE1_HP_UART3_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_UART3_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_UART3 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_uart3 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART3    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART3_M  (HP_PERI1_PMS_WRITE_REE2_HP_UART3_V << HP_PERI1_PMS_WRITE_REE2_HP_UART3_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_UART3_S  7
+/** HP_PERI1_PMS_HP_UART3_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_uart3 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_UART3_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_UART3_LOCK_M  (HP_PERI1_PMS_HP_UART3_LOCK_V << HP_PERI1_PMS_HP_UART3_LOCK_S)
+#define HP_PERI1_PMS_HP_UART3_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_UART3_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_PARLIO_CTRL_REG register
+ *  hp_parlio read/write control register
+ */
+#define HP_PERI1_PMS_HP_PARLIO_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x38)
+/** HP_PERI1_PMS_READ_TEE_HP_PARLIO : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_parlio registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_PARLIO    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_PARLIO_M  (HP_PERI1_PMS_READ_TEE_HP_PARLIO_V << HP_PERI1_PMS_READ_TEE_HP_PARLIO_S)
+#define HP_PERI1_PMS_READ_TEE_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_PARLIO_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_PARLIO : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_parlio registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_PARLIO    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_PARLIO_M  (HP_PERI1_PMS_READ_REE0_HP_PARLIO_V << HP_PERI1_PMS_READ_REE0_HP_PARLIO_S)
+#define HP_PERI1_PMS_READ_REE0_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_PARLIO_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_PARLIO : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_parlio registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_PARLIO    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_PARLIO_M  (HP_PERI1_PMS_READ_REE1_HP_PARLIO_V << HP_PERI1_PMS_READ_REE1_HP_PARLIO_S)
+#define HP_PERI1_PMS_READ_REE1_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_PARLIO_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_PARLIO : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_parlio registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_PARLIO    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_PARLIO_M  (HP_PERI1_PMS_READ_REE2_HP_PARLIO_V << HP_PERI1_PMS_READ_REE2_HP_PARLIO_S)
+#define HP_PERI1_PMS_READ_REE2_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_PARLIO_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_PARLIO : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_parlio registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_PARLIO    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_PARLIO_M  (HP_PERI1_PMS_WRITE_TEE_HP_PARLIO_V << HP_PERI1_PMS_WRITE_TEE_HP_PARLIO_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_PARLIO_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_PARLIO : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_parlio registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_PARLIO    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_PARLIO_M  (HP_PERI1_PMS_WRITE_REE0_HP_PARLIO_V << HP_PERI1_PMS_WRITE_REE0_HP_PARLIO_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_PARLIO_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_PARLIO : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_parlio registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_PARLIO    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_PARLIO_M  (HP_PERI1_PMS_WRITE_REE1_HP_PARLIO_V << HP_PERI1_PMS_WRITE_REE1_HP_PARLIO_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_PARLIO_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_PARLIO : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_parlio registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_PARLIO    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_PARLIO_M  (HP_PERI1_PMS_WRITE_REE2_HP_PARLIO_V << HP_PERI1_PMS_WRITE_REE2_HP_PARLIO_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_PARLIO_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_PARLIO_S  7
+/** HP_PERI1_PMS_HP_PARLIO_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_parlio peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_PARLIO_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_PARLIO_LOCK_M  (HP_PERI1_PMS_HP_PARLIO_LOCK_V << HP_PERI1_PMS_HP_PARLIO_LOCK_S)
+#define HP_PERI1_PMS_HP_PARLIO_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_PARLIO_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_GPSPI2_CTRL_REG register
+ *  hp_gpspi2 read/write control register
+ */
+#define HP_PERI1_PMS_HP_GPSPI2_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x3c)
+/** HP_PERI1_PMS_READ_TEE_HP_GPSPI2 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_gpspi2 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI2    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI2_M  (HP_PERI1_PMS_READ_TEE_HP_GPSPI2_V << HP_PERI1_PMS_READ_TEE_HP_GPSPI2_S)
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI2_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_GPSPI2 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_gpspi2 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI2    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI2_M  (HP_PERI1_PMS_READ_REE0_HP_GPSPI2_V << HP_PERI1_PMS_READ_REE0_HP_GPSPI2_S)
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI2_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_GPSPI2 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_gpspi2 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI2    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI2_M  (HP_PERI1_PMS_READ_REE1_HP_GPSPI2_V << HP_PERI1_PMS_READ_REE1_HP_GPSPI2_S)
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI2_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_GPSPI2 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_gpspi2 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI2    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI2_M  (HP_PERI1_PMS_READ_REE2_HP_GPSPI2_V << HP_PERI1_PMS_READ_REE2_HP_GPSPI2_S)
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI2_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_gpspi2 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2_M  (HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2_V << HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI2_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_gpspi2 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2_M  (HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2_V << HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI2_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_gpspi2 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2_M  (HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2_V << HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI2_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_gpspi2 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2_M  (HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2_V << HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI2_S  7
+/** HP_PERI1_PMS_HP_GPSPI2_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_gpspi2 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_GPSPI2_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_GPSPI2_LOCK_M  (HP_PERI1_PMS_HP_GPSPI2_LOCK_V << HP_PERI1_PMS_HP_GPSPI2_LOCK_S)
+#define HP_PERI1_PMS_HP_GPSPI2_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_GPSPI2_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_GPSPI3_CTRL_REG register
+ *  hp_gpspi3 read/write control register
+ */
+#define HP_PERI1_PMS_HP_GPSPI3_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x40)
+/** HP_PERI1_PMS_READ_TEE_HP_GPSPI3 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_gpspi3 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI3    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI3_M  (HP_PERI1_PMS_READ_TEE_HP_GPSPI3_V << HP_PERI1_PMS_READ_TEE_HP_GPSPI3_S)
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_GPSPI3_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_GPSPI3 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_gpspi3 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI3    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI3_M  (HP_PERI1_PMS_READ_REE0_HP_GPSPI3_V << HP_PERI1_PMS_READ_REE0_HP_GPSPI3_S)
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_GPSPI3_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_GPSPI3 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_gpspi3 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI3    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI3_M  (HP_PERI1_PMS_READ_REE1_HP_GPSPI3_V << HP_PERI1_PMS_READ_REE1_HP_GPSPI3_S)
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_GPSPI3_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_GPSPI3 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_gpspi3 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI3    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI3_M  (HP_PERI1_PMS_READ_REE2_HP_GPSPI3_V << HP_PERI1_PMS_READ_REE2_HP_GPSPI3_S)
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_GPSPI3_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_gpspi3 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3_M  (HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3_V << HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_GPSPI3_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_gpspi3 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3_M  (HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3_V << HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_GPSPI3_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_gpspi3 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3_M  (HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3_V << HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_GPSPI3_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_gpspi3 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3_M  (HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3_V << HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_GPSPI3_S  7
+/** HP_PERI1_PMS_HP_GPSPI3_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_gpspi3 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_GPSPI3_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_GPSPI3_LOCK_M  (HP_PERI1_PMS_HP_GPSPI3_LOCK_V << HP_PERI1_PMS_HP_GPSPI3_LOCK_S)
+#define HP_PERI1_PMS_HP_GPSPI3_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_GPSPI3_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_USBDEVICE_CTRL_REG register
+ *  hp_usbdevice read/write control register
+ */
+#define HP_PERI1_PMS_HP_USBDEVICE_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x44)
+/** HP_PERI1_PMS_READ_TEE_HP_USBDEVICE : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_usbdevice registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_USBDEVICE    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_USBDEVICE_M  (HP_PERI1_PMS_READ_TEE_HP_USBDEVICE_V << HP_PERI1_PMS_READ_TEE_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_READ_TEE_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_USBDEVICE_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_USBDEVICE : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_usbdevice registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_USBDEVICE    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_USBDEVICE_M  (HP_PERI1_PMS_READ_REE0_HP_USBDEVICE_V << HP_PERI1_PMS_READ_REE0_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_READ_REE0_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_USBDEVICE_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_USBDEVICE : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_usbdevice registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_USBDEVICE    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_USBDEVICE_M  (HP_PERI1_PMS_READ_REE1_HP_USBDEVICE_V << HP_PERI1_PMS_READ_REE1_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_READ_REE1_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_USBDEVICE_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_USBDEVICE : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_usbdevice registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_USBDEVICE    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_USBDEVICE_M  (HP_PERI1_PMS_READ_REE2_HP_USBDEVICE_V << HP_PERI1_PMS_READ_REE2_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_READ_REE2_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_USBDEVICE_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_usbdevice registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE_M  (HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE_V << HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_USBDEVICE_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_usbdevice registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE_M  (HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE_V << HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_USBDEVICE_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_usbdevice registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE_M  (HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE_V << HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_USBDEVICE_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_usbdevice registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE_M  (HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE_V << HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_USBDEVICE_S  7
+/** HP_PERI1_PMS_HP_USBDEVICE_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_usbdevice peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_USBDEVICE_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_USBDEVICE_LOCK_M  (HP_PERI1_PMS_HP_USBDEVICE_LOCK_V << HP_PERI1_PMS_HP_USBDEVICE_LOCK_S)
+#define HP_PERI1_PMS_HP_USBDEVICE_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_USBDEVICE_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_LEDC0_CTRL_REG register
+ *  hp_ledc0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_LEDC0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x48)
+/** HP_PERI1_PMS_READ_TEE_HP_LEDC0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_ledc0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC0_M  (HP_PERI1_PMS_READ_TEE_HP_LEDC0_V << HP_PERI1_PMS_READ_TEE_HP_LEDC0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_LEDC0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_ledc0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC0_M  (HP_PERI1_PMS_READ_REE0_HP_LEDC0_V << HP_PERI1_PMS_READ_REE0_HP_LEDC0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_LEDC0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_ledc0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC0_M  (HP_PERI1_PMS_READ_REE1_HP_LEDC0_V << HP_PERI1_PMS_READ_REE1_HP_LEDC0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_LEDC0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_ledc0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC0_M  (HP_PERI1_PMS_READ_REE2_HP_LEDC0_V << HP_PERI1_PMS_READ_REE2_HP_LEDC0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_LEDC0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_ledc0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC0_M  (HP_PERI1_PMS_WRITE_TEE_HP_LEDC0_V << HP_PERI1_PMS_WRITE_TEE_HP_LEDC0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_LEDC0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_ledc0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC0_M  (HP_PERI1_PMS_WRITE_REE0_HP_LEDC0_V << HP_PERI1_PMS_WRITE_REE0_HP_LEDC0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_LEDC0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_ledc0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC0_M  (HP_PERI1_PMS_WRITE_REE1_HP_LEDC0_V << HP_PERI1_PMS_WRITE_REE1_HP_LEDC0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_LEDC0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_ledc0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC0_M  (HP_PERI1_PMS_WRITE_REE2_HP_LEDC0_V << HP_PERI1_PMS_WRITE_REE2_HP_LEDC0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC0_S  7
+/** HP_PERI1_PMS_HP_LEDC0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_ledc0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_LEDC0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_LEDC0_LOCK_M  (HP_PERI1_PMS_HP_LEDC0_LOCK_V << HP_PERI1_PMS_HP_LEDC0_LOCK_S)
+#define HP_PERI1_PMS_HP_LEDC0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_LEDC0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_ETM_CTRL_REG register
+ *  hp_etm read/write control register
+ */
+#define HP_PERI1_PMS_HP_ETM_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x4c)
+/** HP_PERI1_PMS_READ_TEE_HP_ETM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_etm registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_ETM    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_ETM_M  (HP_PERI1_PMS_READ_TEE_HP_ETM_V << HP_PERI1_PMS_READ_TEE_HP_ETM_S)
+#define HP_PERI1_PMS_READ_TEE_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_ETM_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_ETM : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_etm registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_ETM    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_ETM_M  (HP_PERI1_PMS_READ_REE0_HP_ETM_V << HP_PERI1_PMS_READ_REE0_HP_ETM_S)
+#define HP_PERI1_PMS_READ_REE0_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_ETM_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_ETM : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_etm registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_ETM    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_ETM_M  (HP_PERI1_PMS_READ_REE1_HP_ETM_V << HP_PERI1_PMS_READ_REE1_HP_ETM_S)
+#define HP_PERI1_PMS_READ_REE1_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_ETM_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_ETM : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_etm registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_ETM    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_ETM_M  (HP_PERI1_PMS_READ_REE2_HP_ETM_V << HP_PERI1_PMS_READ_REE2_HP_ETM_S)
+#define HP_PERI1_PMS_READ_REE2_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_ETM_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_ETM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_etm registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_ETM    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_ETM_M  (HP_PERI1_PMS_WRITE_TEE_HP_ETM_V << HP_PERI1_PMS_WRITE_TEE_HP_ETM_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_ETM_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_ETM : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_etm registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_ETM    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_ETM_M  (HP_PERI1_PMS_WRITE_REE0_HP_ETM_V << HP_PERI1_PMS_WRITE_REE0_HP_ETM_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_ETM_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_ETM : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_etm registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_ETM    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_ETM_M  (HP_PERI1_PMS_WRITE_REE1_HP_ETM_V << HP_PERI1_PMS_WRITE_REE1_HP_ETM_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_ETM_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_ETM : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_etm registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_ETM    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_ETM_M  (HP_PERI1_PMS_WRITE_REE2_HP_ETM_V << HP_PERI1_PMS_WRITE_REE2_HP_ETM_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_ETM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_ETM_S  7
+/** HP_PERI1_PMS_HP_ETM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_etm peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_ETM_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_ETM_LOCK_M  (HP_PERI1_PMS_HP_ETM_LOCK_V << HP_PERI1_PMS_HP_ETM_LOCK_S)
+#define HP_PERI1_PMS_HP_ETM_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_ETM_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_TWAI0_CTRL_REG register
+ *  hp_twai0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_TWAI0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x50)
+/** HP_PERI1_PMS_READ_TEE_HP_TWAI0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_twai0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI0_M  (HP_PERI1_PMS_READ_TEE_HP_TWAI0_V << HP_PERI1_PMS_READ_TEE_HP_TWAI0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_TWAI0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_twai0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI0_M  (HP_PERI1_PMS_READ_REE0_HP_TWAI0_V << HP_PERI1_PMS_READ_REE0_HP_TWAI0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_TWAI0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_twai0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI0_M  (HP_PERI1_PMS_READ_REE1_HP_TWAI0_V << HP_PERI1_PMS_READ_REE1_HP_TWAI0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_TWAI0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_twai0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI0_M  (HP_PERI1_PMS_READ_REE2_HP_TWAI0_V << HP_PERI1_PMS_READ_REE2_HP_TWAI0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_TWAI0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_twai0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI0_M  (HP_PERI1_PMS_WRITE_TEE_HP_TWAI0_V << HP_PERI1_PMS_WRITE_TEE_HP_TWAI0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_TWAI0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_twai0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI0_M  (HP_PERI1_PMS_WRITE_REE0_HP_TWAI0_V << HP_PERI1_PMS_WRITE_REE0_HP_TWAI0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_TWAI0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_twai0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI0_M  (HP_PERI1_PMS_WRITE_REE1_HP_TWAI0_V << HP_PERI1_PMS_WRITE_REE1_HP_TWAI0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_TWAI0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_twai0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI0_M  (HP_PERI1_PMS_WRITE_REE2_HP_TWAI0_V << HP_PERI1_PMS_WRITE_REE2_HP_TWAI0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI0_S  7
+/** HP_PERI1_PMS_HP_TWAI0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_twai0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_TWAI0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_TWAI0_LOCK_M  (HP_PERI1_PMS_HP_TWAI0_LOCK_V << HP_PERI1_PMS_HP_TWAI0_LOCK_S)
+#define HP_PERI1_PMS_HP_TWAI0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_TWAI0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_TWAI1_CTRL_REG register
+ *  hp_twai1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_TWAI1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x54)
+/** HP_PERI1_PMS_READ_TEE_HP_TWAI1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_twai1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI1_M  (HP_PERI1_PMS_READ_TEE_HP_TWAI1_V << HP_PERI1_PMS_READ_TEE_HP_TWAI1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_TWAI1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_TWAI1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_twai1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI1_M  (HP_PERI1_PMS_READ_REE0_HP_TWAI1_V << HP_PERI1_PMS_READ_REE0_HP_TWAI1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_TWAI1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_TWAI1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_twai1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI1_M  (HP_PERI1_PMS_READ_REE1_HP_TWAI1_V << HP_PERI1_PMS_READ_REE1_HP_TWAI1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_TWAI1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_TWAI1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_twai1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI1_M  (HP_PERI1_PMS_READ_REE2_HP_TWAI1_V << HP_PERI1_PMS_READ_REE2_HP_TWAI1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_TWAI1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_TWAI1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_twai1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI1_M  (HP_PERI1_PMS_WRITE_TEE_HP_TWAI1_V << HP_PERI1_PMS_WRITE_TEE_HP_TWAI1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_TWAI1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_TWAI1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_twai1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI1_M  (HP_PERI1_PMS_WRITE_REE0_HP_TWAI1_V << HP_PERI1_PMS_WRITE_REE0_HP_TWAI1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_TWAI1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_TWAI1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_twai1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI1_M  (HP_PERI1_PMS_WRITE_REE1_HP_TWAI1_V << HP_PERI1_PMS_WRITE_REE1_HP_TWAI1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_TWAI1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_TWAI1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_twai1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI1_M  (HP_PERI1_PMS_WRITE_REE2_HP_TWAI1_V << HP_PERI1_PMS_WRITE_REE2_HP_TWAI1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_TWAI1_S  7
+/** HP_PERI1_PMS_HP_TWAI1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_twai1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_TWAI1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_TWAI1_LOCK_M  (HP_PERI1_PMS_HP_TWAI1_LOCK_V << HP_PERI1_PMS_HP_TWAI1_LOCK_S)
+#define HP_PERI1_PMS_HP_TWAI1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_TWAI1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_LCDCAM_CTRL_REG register
+ *  hp_lcdcam read/write control register
+ */
+#define HP_PERI1_PMS_HP_LCDCAM_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x58)
+/** HP_PERI1_PMS_READ_TEE_HP_LCDCAM : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_lcdcam registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_LCDCAM    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_LCDCAM_M  (HP_PERI1_PMS_READ_TEE_HP_LCDCAM_V << HP_PERI1_PMS_READ_TEE_HP_LCDCAM_S)
+#define HP_PERI1_PMS_READ_TEE_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_LCDCAM_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_LCDCAM : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_lcdcam registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_LCDCAM    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_LCDCAM_M  (HP_PERI1_PMS_READ_REE0_HP_LCDCAM_V << HP_PERI1_PMS_READ_REE0_HP_LCDCAM_S)
+#define HP_PERI1_PMS_READ_REE0_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_LCDCAM_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_LCDCAM : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_lcdcam registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_LCDCAM    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_LCDCAM_M  (HP_PERI1_PMS_READ_REE1_HP_LCDCAM_V << HP_PERI1_PMS_READ_REE1_HP_LCDCAM_S)
+#define HP_PERI1_PMS_READ_REE1_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_LCDCAM_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_LCDCAM : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_lcdcam registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_LCDCAM    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_LCDCAM_M  (HP_PERI1_PMS_READ_REE2_HP_LCDCAM_V << HP_PERI1_PMS_READ_REE2_HP_LCDCAM_S)
+#define HP_PERI1_PMS_READ_REE2_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_LCDCAM_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_lcdcam registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM_M  (HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM_V << HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_LCDCAM_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_lcdcam registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM_M  (HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM_V << HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_LCDCAM_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_lcdcam registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM_M  (HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM_V << HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_LCDCAM_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_lcdcam registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM_M  (HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM_V << HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_LCDCAM_S  7
+/** HP_PERI1_PMS_HP_LCDCAM_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_lcdcam peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_LCDCAM_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_LCDCAM_LOCK_M  (HP_PERI1_PMS_HP_LCDCAM_LOCK_V << HP_PERI1_PMS_HP_LCDCAM_LOCK_S)
+#define HP_PERI1_PMS_HP_LCDCAM_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_LCDCAM_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_UHCI_CTRL_REG register
+ *  hp_uhci read/write control register
+ */
+#define HP_PERI1_PMS_HP_UHCI_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x5c)
+/** HP_PERI1_PMS_READ_TEE_HP_UHCI : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_uhci registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_UHCI    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_UHCI_M  (HP_PERI1_PMS_READ_TEE_HP_UHCI_V << HP_PERI1_PMS_READ_TEE_HP_UHCI_S)
+#define HP_PERI1_PMS_READ_TEE_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_UHCI_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_UHCI : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_uhci registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_UHCI    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_UHCI_M  (HP_PERI1_PMS_READ_REE0_HP_UHCI_V << HP_PERI1_PMS_READ_REE0_HP_UHCI_S)
+#define HP_PERI1_PMS_READ_REE0_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_UHCI_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_UHCI : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_uhci registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_UHCI    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_UHCI_M  (HP_PERI1_PMS_READ_REE1_HP_UHCI_V << HP_PERI1_PMS_READ_REE1_HP_UHCI_S)
+#define HP_PERI1_PMS_READ_REE1_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_UHCI_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_UHCI : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_uhci registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_UHCI    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_UHCI_M  (HP_PERI1_PMS_READ_REE2_HP_UHCI_V << HP_PERI1_PMS_READ_REE2_HP_UHCI_S)
+#define HP_PERI1_PMS_READ_REE2_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_UHCI_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_UHCI : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_uhci registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_UHCI    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_UHCI_M  (HP_PERI1_PMS_WRITE_TEE_HP_UHCI_V << HP_PERI1_PMS_WRITE_TEE_HP_UHCI_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_UHCI_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_UHCI : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_uhci registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_UHCI    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_UHCI_M  (HP_PERI1_PMS_WRITE_REE0_HP_UHCI_V << HP_PERI1_PMS_WRITE_REE0_HP_UHCI_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_UHCI_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_UHCI : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_uhci registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_UHCI    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_UHCI_M  (HP_PERI1_PMS_WRITE_REE1_HP_UHCI_V << HP_PERI1_PMS_WRITE_REE1_HP_UHCI_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_UHCI_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_UHCI : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_uhci registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_UHCI    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_UHCI_M  (HP_PERI1_PMS_WRITE_REE2_HP_UHCI_V << HP_PERI1_PMS_WRITE_REE2_HP_UHCI_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_UHCI_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_UHCI_S  7
+/** HP_PERI1_PMS_HP_UHCI_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_uhci peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_UHCI_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_UHCI_LOCK_M  (HP_PERI1_PMS_HP_UHCI_LOCK_V << HP_PERI1_PMS_HP_UHCI_LOCK_S)
+#define HP_PERI1_PMS_HP_UHCI_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_UHCI_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_SYSTIMER_CTRL_REG register
+ *  hp_systimer read/write control register
+ */
+#define HP_PERI1_PMS_HP_SYSTIMER_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x60)
+/** HP_PERI1_PMS_READ_TEE_HP_SYSTIMER : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_systimer registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_SYSTIMER    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_SYSTIMER_M  (HP_PERI1_PMS_READ_TEE_HP_SYSTIMER_V << HP_PERI1_PMS_READ_TEE_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_READ_TEE_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_SYSTIMER_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_SYSTIMER : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_systimer registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_SYSTIMER    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_SYSTIMER_M  (HP_PERI1_PMS_READ_REE0_HP_SYSTIMER_V << HP_PERI1_PMS_READ_REE0_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_READ_REE0_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_SYSTIMER_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_SYSTIMER : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_systimer registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_SYSTIMER    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_SYSTIMER_M  (HP_PERI1_PMS_READ_REE1_HP_SYSTIMER_V << HP_PERI1_PMS_READ_REE1_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_READ_REE1_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_SYSTIMER_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_SYSTIMER : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_systimer registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_SYSTIMER    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_SYSTIMER_M  (HP_PERI1_PMS_READ_REE2_HP_SYSTIMER_V << HP_PERI1_PMS_READ_REE2_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_READ_REE2_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_SYSTIMER_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_systimer registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER_M  (HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER_V << HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYSTIMER_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_systimer registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER_M  (HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER_V << HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYSTIMER_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_systimer registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER_M  (HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER_V << HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYSTIMER_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_systimer registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER_M  (HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER_V << HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYSTIMER_S  7
+/** HP_PERI1_PMS_HP_SYSTIMER_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_systimer peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_SYSTIMER_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_SYSTIMER_LOCK_M  (HP_PERI1_PMS_HP_SYSTIMER_LOCK_V << HP_PERI1_PMS_HP_SYSTIMER_LOCK_S)
+#define HP_PERI1_PMS_HP_SYSTIMER_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_SYSTIMER_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_ZERO_DET_CTRL_REG register
+ *  hp_zero_det read/write control register
+ */
+#define HP_PERI1_PMS_HP_ZERO_DET_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x64)
+/** HP_PERI1_PMS_READ_TEE_HP_ZERO_DET : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_zero_det registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_ZERO_DET    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_ZERO_DET_M  (HP_PERI1_PMS_READ_TEE_HP_ZERO_DET_V << HP_PERI1_PMS_READ_TEE_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_READ_TEE_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_ZERO_DET_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_ZERO_DET : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_zero_det registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_ZERO_DET    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_ZERO_DET_M  (HP_PERI1_PMS_READ_REE0_HP_ZERO_DET_V << HP_PERI1_PMS_READ_REE0_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_READ_REE0_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_ZERO_DET_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_ZERO_DET : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_zero_det registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_ZERO_DET    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_ZERO_DET_M  (HP_PERI1_PMS_READ_REE1_HP_ZERO_DET_V << HP_PERI1_PMS_READ_REE1_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_READ_REE1_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_ZERO_DET_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_ZERO_DET : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_zero_det registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_ZERO_DET    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_ZERO_DET_M  (HP_PERI1_PMS_READ_REE2_HP_ZERO_DET_V << HP_PERI1_PMS_READ_REE2_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_READ_REE2_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_ZERO_DET_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_zero_det registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET_M  (HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET_V << HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_ZERO_DET_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_zero_det registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET_M  (HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET_V << HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_ZERO_DET_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_zero_det registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET_M  (HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET_V << HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_ZERO_DET_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_zero_det registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET_M  (HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET_V << HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_ZERO_DET_S  7
+/** HP_PERI1_PMS_HP_ZERO_DET_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_zero_det peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_ZERO_DET_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_ZERO_DET_LOCK_M  (HP_PERI1_PMS_HP_ZERO_DET_LOCK_V << HP_PERI1_PMS_HP_ZERO_DET_LOCK_S)
+#define HP_PERI1_PMS_HP_ZERO_DET_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_ZERO_DET_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_CORDIC_CTRL_REG register
+ *  hp_cordic read/write control register
+ */
+#define HP_PERI1_PMS_HP_CORDIC_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x68)
+/** HP_PERI1_PMS_READ_TEE_HP_CORDIC : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_cordic registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_CORDIC    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_CORDIC_M  (HP_PERI1_PMS_READ_TEE_HP_CORDIC_V << HP_PERI1_PMS_READ_TEE_HP_CORDIC_S)
+#define HP_PERI1_PMS_READ_TEE_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_CORDIC_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_CORDIC : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_cordic registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_CORDIC    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_CORDIC_M  (HP_PERI1_PMS_READ_REE0_HP_CORDIC_V << HP_PERI1_PMS_READ_REE0_HP_CORDIC_S)
+#define HP_PERI1_PMS_READ_REE0_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_CORDIC_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_CORDIC : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_cordic registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_CORDIC    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_CORDIC_M  (HP_PERI1_PMS_READ_REE1_HP_CORDIC_V << HP_PERI1_PMS_READ_REE1_HP_CORDIC_S)
+#define HP_PERI1_PMS_READ_REE1_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_CORDIC_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_CORDIC : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_cordic registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_CORDIC    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_CORDIC_M  (HP_PERI1_PMS_READ_REE2_HP_CORDIC_V << HP_PERI1_PMS_READ_REE2_HP_CORDIC_S)
+#define HP_PERI1_PMS_READ_REE2_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_CORDIC_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_CORDIC : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_cordic registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_CORDIC    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_CORDIC_M  (HP_PERI1_PMS_WRITE_TEE_HP_CORDIC_V << HP_PERI1_PMS_WRITE_TEE_HP_CORDIC_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_CORDIC_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_CORDIC : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_cordic registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_CORDIC    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_CORDIC_M  (HP_PERI1_PMS_WRITE_REE0_HP_CORDIC_V << HP_PERI1_PMS_WRITE_REE0_HP_CORDIC_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_CORDIC_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_CORDIC : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_cordic registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_CORDIC    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_CORDIC_M  (HP_PERI1_PMS_WRITE_REE1_HP_CORDIC_V << HP_PERI1_PMS_WRITE_REE1_HP_CORDIC_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_CORDIC_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_CORDIC : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_cordic registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_CORDIC    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_CORDIC_M  (HP_PERI1_PMS_WRITE_REE2_HP_CORDIC_V << HP_PERI1_PMS_WRITE_REE2_HP_CORDIC_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_CORDIC_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_CORDIC_S  7
+/** HP_PERI1_PMS_HP_CORDIC_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_cordic peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_CORDIC_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_CORDIC_LOCK_M  (HP_PERI1_PMS_HP_CORDIC_LOCK_V << HP_PERI1_PMS_HP_CORDIC_LOCK_S)
+#define HP_PERI1_PMS_HP_CORDIC_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_CORDIC_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_LEDC1_CTRL_REG register
+ *  hp_ledc1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_LEDC1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x6c)
+/** HP_PERI1_PMS_READ_TEE_HP_LEDC1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_ledc1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC1_M  (HP_PERI1_PMS_READ_TEE_HP_LEDC1_V << HP_PERI1_PMS_READ_TEE_HP_LEDC1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_LEDC1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_LEDC1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_ledc1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC1_M  (HP_PERI1_PMS_READ_REE0_HP_LEDC1_V << HP_PERI1_PMS_READ_REE0_HP_LEDC1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_LEDC1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_LEDC1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_ledc1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC1_M  (HP_PERI1_PMS_READ_REE1_HP_LEDC1_V << HP_PERI1_PMS_READ_REE1_HP_LEDC1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_LEDC1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_LEDC1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_ledc1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC1_M  (HP_PERI1_PMS_READ_REE2_HP_LEDC1_V << HP_PERI1_PMS_READ_REE2_HP_LEDC1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_LEDC1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_LEDC1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_ledc1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC1_M  (HP_PERI1_PMS_WRITE_TEE_HP_LEDC1_V << HP_PERI1_PMS_WRITE_TEE_HP_LEDC1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_LEDC1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_LEDC1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_ledc1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC1_M  (HP_PERI1_PMS_WRITE_REE0_HP_LEDC1_V << HP_PERI1_PMS_WRITE_REE0_HP_LEDC1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_LEDC1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_LEDC1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_ledc1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC1_M  (HP_PERI1_PMS_WRITE_REE1_HP_LEDC1_V << HP_PERI1_PMS_WRITE_REE1_HP_LEDC1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_LEDC1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_LEDC1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_ledc1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC1_M  (HP_PERI1_PMS_WRITE_REE2_HP_LEDC1_V << HP_PERI1_PMS_WRITE_REE2_HP_LEDC1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_LEDC1_S  7
+/** HP_PERI1_PMS_HP_LEDC1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_ledc1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_LEDC1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_LEDC1_LOCK_M  (HP_PERI1_PMS_HP_LEDC1_LOCK_V << HP_PERI1_PMS_HP_LEDC1_LOCK_S)
+#define HP_PERI1_PMS_HP_LEDC1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_LEDC1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_PCNT1_CTRL_REG register
+ *  hp_pcnt1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_PCNT1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x70)
+/** HP_PERI1_PMS_READ_TEE_HP_PCNT1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_pcnt1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT1_M  (HP_PERI1_PMS_READ_TEE_HP_PCNT1_V << HP_PERI1_PMS_READ_TEE_HP_PCNT1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_PCNT1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_PCNT1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_pcnt1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT1_M  (HP_PERI1_PMS_READ_REE0_HP_PCNT1_V << HP_PERI1_PMS_READ_REE0_HP_PCNT1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_PCNT1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_PCNT1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_pcnt1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT1_M  (HP_PERI1_PMS_READ_REE1_HP_PCNT1_V << HP_PERI1_PMS_READ_REE1_HP_PCNT1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_PCNT1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_PCNT1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_pcnt1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT1_M  (HP_PERI1_PMS_READ_REE2_HP_PCNT1_V << HP_PERI1_PMS_READ_REE2_HP_PCNT1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_PCNT1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_PCNT1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_pcnt1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT1_M  (HP_PERI1_PMS_WRITE_TEE_HP_PCNT1_V << HP_PERI1_PMS_WRITE_TEE_HP_PCNT1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_PCNT1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_PCNT1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_pcnt1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT1_M  (HP_PERI1_PMS_WRITE_REE0_HP_PCNT1_V << HP_PERI1_PMS_WRITE_REE0_HP_PCNT1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_PCNT1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_PCNT1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_pcnt1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT1_M  (HP_PERI1_PMS_WRITE_REE1_HP_PCNT1_V << HP_PERI1_PMS_WRITE_REE1_HP_PCNT1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_PCNT1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_PCNT1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_pcnt1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT1_M  (HP_PERI1_PMS_WRITE_REE2_HP_PCNT1_V << HP_PERI1_PMS_WRITE_REE2_HP_PCNT1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_PCNT1_S  7
+/** HP_PERI1_PMS_HP_PCNT1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_pcnt1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_PCNT1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_PCNT1_LOCK_M  (HP_PERI1_PMS_HP_PCNT1_LOCK_V << HP_PERI1_PMS_HP_PCNT1_LOCK_S)
+#define HP_PERI1_PMS_HP_PCNT1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_PCNT1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_TIMER_GROUP0_CTRL_REG register
+ *  hp_timer_group0 read/write control register
+ */
+#define HP_PERI1_PMS_HP_TIMER_GROUP0_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x74)
+/** HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_timer_group0 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0_V << HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP0_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_timer_group0 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0_V << HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP0_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_timer_group0 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0_V << HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP0_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_timer_group0 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0_V << HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP0_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_timer_group0 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0_V << HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP0_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_timer_group0 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0_V << HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP0_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_timer_group0 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0_V << HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP0_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_timer_group0 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0_M  (HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0_V << HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP0_S  7
+/** HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_timer_group0 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK_M  (HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK_V << HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK_S)
+#define HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_TIMER_GROUP0_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_TIMER_GROUP1_CTRL_REG register
+ *  hp_timer_group1 read/write control register
+ */
+#define HP_PERI1_PMS_HP_TIMER_GROUP1_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x78)
+/** HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1 : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_timer_group1 registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1_V << HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_TIMER_GROUP1_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1 : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_timer_group1 registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1_V << HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_TIMER_GROUP1_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1 : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_timer_group1 registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1_V << HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_TIMER_GROUP1_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1 : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_timer_group1 registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1_V << HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_TIMER_GROUP1_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1 : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_timer_group1 registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1_V << HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_TIMER_GROUP1_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1 : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_timer_group1 registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1_V << HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_TIMER_GROUP1_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1 : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_timer_group1 registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1_V << HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_TIMER_GROUP1_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1 : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_timer_group1 registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1_M  (HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1_V << HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_TIMER_GROUP1_S  7
+/** HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_timer_group1 peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK_M  (HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK_V << HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK_S)
+#define HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_TIMER_GROUP1_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_IOMUX_CTRL_REG register
+ *  hp_iomux read/write control register
+ */
+#define HP_PERI1_PMS_HP_IOMUX_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x7c)
+/** HP_PERI1_PMS_READ_TEE_HP_IOMUX : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_iomux registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_IOMUX    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_IOMUX_M  (HP_PERI1_PMS_READ_TEE_HP_IOMUX_V << HP_PERI1_PMS_READ_TEE_HP_IOMUX_S)
+#define HP_PERI1_PMS_READ_TEE_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_IOMUX_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_IOMUX : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_iomux registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_IOMUX    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_IOMUX_M  (HP_PERI1_PMS_READ_REE0_HP_IOMUX_V << HP_PERI1_PMS_READ_REE0_HP_IOMUX_S)
+#define HP_PERI1_PMS_READ_REE0_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_IOMUX_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_IOMUX : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_iomux registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_IOMUX    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_IOMUX_M  (HP_PERI1_PMS_READ_REE1_HP_IOMUX_V << HP_PERI1_PMS_READ_REE1_HP_IOMUX_S)
+#define HP_PERI1_PMS_READ_REE1_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_IOMUX_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_IOMUX : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_iomux registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_IOMUX    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_IOMUX_M  (HP_PERI1_PMS_READ_REE2_HP_IOMUX_V << HP_PERI1_PMS_READ_REE2_HP_IOMUX_S)
+#define HP_PERI1_PMS_READ_REE2_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_IOMUX_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_IOMUX : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_iomux registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_IOMUX    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_IOMUX_M  (HP_PERI1_PMS_WRITE_TEE_HP_IOMUX_V << HP_PERI1_PMS_WRITE_TEE_HP_IOMUX_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_IOMUX_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_IOMUX : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_iomux registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_IOMUX    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_IOMUX_M  (HP_PERI1_PMS_WRITE_REE0_HP_IOMUX_V << HP_PERI1_PMS_WRITE_REE0_HP_IOMUX_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_IOMUX_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_IOMUX : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_iomux registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_IOMUX    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_IOMUX_M  (HP_PERI1_PMS_WRITE_REE1_HP_IOMUX_V << HP_PERI1_PMS_WRITE_REE1_HP_IOMUX_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_IOMUX_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_IOMUX : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_iomux registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_IOMUX    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_IOMUX_M  (HP_PERI1_PMS_WRITE_REE2_HP_IOMUX_V << HP_PERI1_PMS_WRITE_REE2_HP_IOMUX_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_IOMUX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_IOMUX_S  7
+/** HP_PERI1_PMS_HP_IOMUX_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_iomux peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_IOMUX_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_IOMUX_LOCK_M  (HP_PERI1_PMS_HP_IOMUX_LOCK_V << HP_PERI1_PMS_HP_IOMUX_LOCK_S)
+#define HP_PERI1_PMS_HP_IOMUX_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_IOMUX_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_MSPI_PADCTRL_CTRL_REG register
+ *  hp_mspi_padctrl read/write control register
+ */
+#define HP_PERI1_PMS_HP_MSPI_PADCTRL_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x80)
+/** HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_mspi_padctrl registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_MSPI_PADCTRL_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_mspi_padctrl registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_MSPI_PADCTRL_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_mspi_padctrl registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_MSPI_PADCTRL_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_mspi_padctrl registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_MSPI_PADCTRL_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_mspi_padctrl registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_MSPI_PADCTRL_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_mspi_padctrl registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_MSPI_PADCTRL_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_mspi_padctrl registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_MSPI_PADCTRL_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_mspi_padctrl registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL_M  (HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL_V << HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_MSPI_PADCTRL_S  7
+/** HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_mspi_padctrl peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK_M  (HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK_V << HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK_S)
+#define HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_MSPI_PADCTRL_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_INTRMTX_CTRL_REG register
+ *  hp_intrmtx read/write control register
+ */
+#define HP_PERI1_PMS_HP_INTRMTX_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x84)
+/** HP_PERI1_PMS_READ_TEE_HP_INTRMTX : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_intrmtx registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_INTRMTX    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_INTRMTX_M  (HP_PERI1_PMS_READ_TEE_HP_INTRMTX_V << HP_PERI1_PMS_READ_TEE_HP_INTRMTX_S)
+#define HP_PERI1_PMS_READ_TEE_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_INTRMTX_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_INTRMTX : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_intrmtx registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_INTRMTX    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_INTRMTX_M  (HP_PERI1_PMS_READ_REE0_HP_INTRMTX_V << HP_PERI1_PMS_READ_REE0_HP_INTRMTX_S)
+#define HP_PERI1_PMS_READ_REE0_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_INTRMTX_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_INTRMTX : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_intrmtx registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_INTRMTX    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_INTRMTX_M  (HP_PERI1_PMS_READ_REE1_HP_INTRMTX_V << HP_PERI1_PMS_READ_REE1_HP_INTRMTX_S)
+#define HP_PERI1_PMS_READ_REE1_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_INTRMTX_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_INTRMTX : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_intrmtx registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_INTRMTX    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_INTRMTX_M  (HP_PERI1_PMS_READ_REE2_HP_INTRMTX_V << HP_PERI1_PMS_READ_REE2_HP_INTRMTX_S)
+#define HP_PERI1_PMS_READ_REE2_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_INTRMTX_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_intrmtx registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX_M  (HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX_V << HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_INTRMTX_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_intrmtx registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX_M  (HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX_V << HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_INTRMTX_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_intrmtx registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX_M  (HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX_V << HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_INTRMTX_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_intrmtx registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX_M  (HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX_V << HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_INTRMTX_S  7
+/** HP_PERI1_PMS_HP_INTRMTX_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_intrmtx peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_INTRMTX_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_INTRMTX_LOCK_M  (HP_PERI1_PMS_HP_INTRMTX_LOCK_V << HP_PERI1_PMS_HP_INTRMTX_LOCK_S)
+#define HP_PERI1_PMS_HP_INTRMTX_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_INTRMTX_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_SYS_REG_CTRL_REG register
+ *  hp_sys_reg read/write control register
+ */
+#define HP_PERI1_PMS_HP_SYS_REG_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x88)
+/** HP_PERI1_PMS_READ_TEE_HP_SYS_REG : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_sys_reg registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_SYS_REG    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_SYS_REG_M  (HP_PERI1_PMS_READ_TEE_HP_SYS_REG_V << HP_PERI1_PMS_READ_TEE_HP_SYS_REG_S)
+#define HP_PERI1_PMS_READ_TEE_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_SYS_REG_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_SYS_REG : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_sys_reg registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_SYS_REG    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_SYS_REG_M  (HP_PERI1_PMS_READ_REE0_HP_SYS_REG_V << HP_PERI1_PMS_READ_REE0_HP_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE0_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_SYS_REG_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_SYS_REG : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_sys_reg registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_SYS_REG    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_SYS_REG_M  (HP_PERI1_PMS_READ_REE1_HP_SYS_REG_V << HP_PERI1_PMS_READ_REE1_HP_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE1_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_SYS_REG_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_SYS_REG : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_sys_reg registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_SYS_REG    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_SYS_REG_M  (HP_PERI1_PMS_READ_REE2_HP_SYS_REG_V << HP_PERI1_PMS_READ_REE2_HP_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE2_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_SYS_REG_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_sys_reg registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG_M  (HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG_V << HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_SYS_REG_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_sys_reg registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG_V << HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_SYS_REG_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_sys_reg registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG_V << HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_SYS_REG_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_sys_reg registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG_V << HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_SYS_REG_S  7
+/** HP_PERI1_PMS_HP_SYS_REG_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_sys_reg peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_SYS_REG_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_SYS_REG_LOCK_M  (HP_PERI1_PMS_HP_SYS_REG_LOCK_V << HP_PERI1_PMS_HP_SYS_REG_LOCK_S)
+#define HP_PERI1_PMS_HP_SYS_REG_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_SYS_REG_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_CLKRST_CTRL_REG register
+ *  hp_clkrst read/write control register
+ */
+#define HP_PERI1_PMS_HP_CLKRST_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x8c)
+/** HP_PERI1_PMS_READ_TEE_HP_CLKRST : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_clkrst registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_CLKRST    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_CLKRST_M  (HP_PERI1_PMS_READ_TEE_HP_CLKRST_V << HP_PERI1_PMS_READ_TEE_HP_CLKRST_S)
+#define HP_PERI1_PMS_READ_TEE_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_CLKRST_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_CLKRST : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_clkrst registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_CLKRST    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_CLKRST_M  (HP_PERI1_PMS_READ_REE0_HP_CLKRST_V << HP_PERI1_PMS_READ_REE0_HP_CLKRST_S)
+#define HP_PERI1_PMS_READ_REE0_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_CLKRST_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_CLKRST : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_clkrst registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_CLKRST    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_CLKRST_M  (HP_PERI1_PMS_READ_REE1_HP_CLKRST_V << HP_PERI1_PMS_READ_REE1_HP_CLKRST_S)
+#define HP_PERI1_PMS_READ_REE1_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_CLKRST_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_CLKRST : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_clkrst registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_CLKRST    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_CLKRST_M  (HP_PERI1_PMS_READ_REE2_HP_CLKRST_V << HP_PERI1_PMS_READ_REE2_HP_CLKRST_S)
+#define HP_PERI1_PMS_READ_REE2_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_CLKRST_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_CLKRST : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_clkrst registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_CLKRST    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_CLKRST_M  (HP_PERI1_PMS_WRITE_TEE_HP_CLKRST_V << HP_PERI1_PMS_WRITE_TEE_HP_CLKRST_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_CLKRST_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_CLKRST : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_clkrst registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_CLKRST    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_CLKRST_M  (HP_PERI1_PMS_WRITE_REE0_HP_CLKRST_V << HP_PERI1_PMS_WRITE_REE0_HP_CLKRST_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_CLKRST_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_CLKRST : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_clkrst registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_CLKRST    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_CLKRST_M  (HP_PERI1_PMS_WRITE_REE1_HP_CLKRST_V << HP_PERI1_PMS_WRITE_REE1_HP_CLKRST_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_CLKRST_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_CLKRST : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_clkrst registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_CLKRST    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_CLKRST_M  (HP_PERI1_PMS_WRITE_REE2_HP_CLKRST_V << HP_PERI1_PMS_WRITE_REE2_HP_CLKRST_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_CLKRST_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_CLKRST_S  7
+/** HP_PERI1_PMS_HP_CLKRST_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_clkrst peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_CLKRST_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_CLKRST_LOCK_M  (HP_PERI1_PMS_HP_CLKRST_LOCK_V << HP_PERI1_PMS_HP_CLKRST_LOCK_S)
+#define HP_PERI1_PMS_HP_CLKRST_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_CLKRST_LOCK_S  8
+
+/** HP_PERI1_PMS_CNNT_PAD_CTRL_CTRL_REG register
+ *  cnnt_pad_ctrl read/write control register
+ */
+#define HP_PERI1_PMS_CNNT_PAD_CTRL_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x90)
+/** HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL : R/W; bitpos: [0]; default: 1;
+ *  Configures cnnt_pad_ctrl registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL_V << HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_CNNT_PAD_CTRL_S  0
+/** HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL : R/W; bitpos: [1]; default: 0;
+ *  Configures cnnt_pad_ctrl registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL_V << HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_CNNT_PAD_CTRL_S  1
+/** HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL : R/W; bitpos: [2]; default: 0;
+ *  Configures cnnt_pad_ctrl registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL_V << HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_CNNT_PAD_CTRL_S  2
+/** HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Configures cnnt_pad_ctrl registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL_V << HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_CNNT_PAD_CTRL_S  3
+/** HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL : R/W; bitpos: [4]; default: 1;
+ *  Configures cnnt_pad_ctrl registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL_V << HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_CNNT_PAD_CTRL_S  4
+/** HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL : R/W; bitpos: [5]; default: 0;
+ *  Configures cnnt_pad_ctrl registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL_V << HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_CNNT_PAD_CTRL_S  5
+/** HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL : R/W; bitpos: [6]; default: 0;
+ *  Configures cnnt_pad_ctrl registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL_V << HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_CNNT_PAD_CTRL_S  6
+/** HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL : R/W; bitpos: [7]; default: 0;
+ *  Configures cnnt_pad_ctrl registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL_M  (HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL_V << HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL_S)
+#define HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_CNNT_PAD_CTRL_S  7
+/** HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock cnnt_pad_ctrl peri_apm configuration
+ */
+#define HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK    (BIT(8))
+#define HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK_M  (HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK_V << HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK_S)
+#define HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_CNNT_PAD_CTRL_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_ALIVE_SYS_REG_CTRL_REG register
+ *  hp_alive_sys_reg read/write control register
+ */
+#define HP_PERI1_PMS_HP_ALIVE_SYS_REG_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x94)
+/** HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_alive_sys_reg registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_ALIVE_SYS_REG_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG : R/W; bitpos: [1]; default: 0;
+ *  Configures hp_alive_sys_reg registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_ALIVE_SYS_REG_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG : R/W; bitpos: [2]; default: 0;
+ *  Configures hp_alive_sys_reg registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_ALIVE_SYS_REG_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG : R/W; bitpos: [3]; default: 0;
+ *  Configures hp_alive_sys_reg registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_ALIVE_SYS_REG_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_alive_sys_reg registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_ALIVE_SYS_REG_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG : R/W; bitpos: [5]; default: 0;
+ *  Configures hp_alive_sys_reg registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_ALIVE_SYS_REG_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG : R/W; bitpos: [6]; default: 0;
+ *  Configures hp_alive_sys_reg registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_ALIVE_SYS_REG_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG : R/W; bitpos: [7]; default: 0;
+ *  Configures hp_alive_sys_reg registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG_M  (HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG_V << HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_ALIVE_SYS_REG_S  7
+/** HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_alive_sys_reg peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK_M  (HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK_V << HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK_S)
+#define HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_ALIVE_SYS_REG_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_PERI1_PMS_CTRL_REG register
+ *  hp_peri1_pms read/write control register
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_CTRL_REG (DR_REG_HP_PERI1_PMS_BASE + 0x98)
+/** HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS : R/W; bitpos: [0]; default: 1;
+ *  Configures hp_peri1_pms registers read permission in tee mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS    (BIT(0))
+#define HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS_M  (HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS_V << HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_READ_TEE_HP_PERI1_PMS_S  0
+/** HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS : HRO; bitpos: [1]; default: 0;
+ *  Configures hp_peri1_pms registers read permission in ree0 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS    (BIT(1))
+#define HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS_M  (HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS_V << HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE0_HP_PERI1_PMS_S  1
+/** HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS : HRO; bitpos: [2]; default: 0;
+ *  Configures hp_peri1_pms registers read permission in ree1 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS    (BIT(2))
+#define HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS_M  (HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS_V << HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE1_HP_PERI1_PMS_S  2
+/** HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS : HRO; bitpos: [3]; default: 0;
+ *  Configures hp_peri1_pms registers read permission in ree2 mode.
+ *  0: can not be read
+ *  1: can be read
+ */
+#define HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS    (BIT(3))
+#define HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS_M  (HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS_V << HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_READ_REE2_HP_PERI1_PMS_S  3
+/** HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS : R/W; bitpos: [4]; default: 1;
+ *  Configures hp_peri1_pms registers write permission in tee mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS    (BIT(4))
+#define HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS_M  (HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS_V << HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_TEE_HP_PERI1_PMS_S  4
+/** HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS : HRO; bitpos: [5]; default: 0;
+ *  Configures hp_peri1_pms registers write permission in ree0 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS    (BIT(5))
+#define HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS_M  (HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS_V << HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE0_HP_PERI1_PMS_S  5
+/** HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS : HRO; bitpos: [6]; default: 0;
+ *  Configures hp_peri1_pms registers write permission in ree1 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS    (BIT(6))
+#define HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS_M  (HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS_V << HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE1_HP_PERI1_PMS_S  6
+/** HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS : HRO; bitpos: [7]; default: 0;
+ *  Configures hp_peri1_pms registers write permission in ree2 mode.
+ *  0: can not be write
+ *  1: can be write
+ */
+#define HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS    (BIT(7))
+#define HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS_M  (HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS_V << HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS_S)
+#define HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS_V  0x00000001U
+#define HP_PERI1_PMS_WRITE_REE2_HP_PERI1_PMS_S  7
+/** HP_PERI1_PMS_HP_PERI1_PMS_LOCK : R/W; bitpos: [8]; default: 0;
+ *  Set 1 to lock hp_peri1_pms peri_apm configuration
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_LOCK    (BIT(8))
+#define HP_PERI1_PMS_HP_PERI1_PMS_LOCK_M  (HP_PERI1_PMS_HP_PERI1_PMS_LOCK_V << HP_PERI1_PMS_HP_PERI1_PMS_LOCK_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_LOCK_V  0x00000001U
+#define HP_PERI1_PMS_HP_PERI1_PMS_LOCK_S  8
+
+/** HP_PERI1_PMS_HP_PERI1_0_REG register
+ *  HP_PERI1 PMS configuration & info register
+ */
+#define HP_PERI1_PMS_HP_PERI1_0_REG (DR_REG_HP_PERI1_PMS_BASE + 0x200)
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
+ *  Configures whether or not to clear hp_peri1 peri_pms_record_reg.
+ *  0: No clear
+ *  1: Clear peri_pms_record_reg
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR    (BIT(0))
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR_V  0x00000001U
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_CLR_S  0
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET : RO; bitpos: [1]; default: 0;
+ *  Represents whether the hp_peri1 pms has been triggered.
+ *  0: No triggered
+ *  1: Has been triggered
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET    (BIT(1))
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET_V  0x00000001U
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_DET_S  1
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID : RO; bitpos: [7:2]; default: 0;
+ *  Represents the master id when hp_peri1 pms has been triggered.
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID    0x0000003FU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID_V  0x0000003FU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ID_S  2
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE : RO; bitpos: [9:8]; default: 0;
+ *  Represents the security mode when hp_peri1 pms has been triggered.
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE    0x00000003U
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE_V  0x00000003U
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_MODE_S  8
+
+/** HP_PERI1_PMS_HP_PERI1_1_REG register
+ *  HP_PERI1 PMS exception addr record register
+ */
+#define HP_PERI1_PMS_HP_PERI1_1_REG (DR_REG_HP_PERI1_PMS_BASE + 0x204)
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR : RO; bitpos: [27:0]; default: 0;
+ *  Represents the access address (bit27~bit0) when hp_peri1 pms has been triggered.
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR    0x0FFFFFFFU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_V  0x0FFFFFFFU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_S  0
+/** HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST : HRO; bitpos: [31:28]; default: 2;
+ *  Represents the access address (bit31~bit28) when hp_peri1 pms has been triggered.
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST    0x0000000FU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST_M  (HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST_V << HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST_V  0x0000000FU
+#define HP_PERI1_PMS_HP_PERI1_PMS_EXCEPTION_ADDR_CONST_S  28
+
+/** HP_PERI1_PMS_INT_EN_REG register
+ *  APM interrupt enable register
+ */
+#define HP_PERI1_PMS_INT_EN_REG (DR_REG_HP_PERI1_PMS_BASE + 0x300)
+/** HP_PERI1_PMS_HP_PERI1_PMS_INT_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures to enable hp_peri1 pms interrupt.
+ *  0: disable
+ *  1: enable
+ */
+#define HP_PERI1_PMS_HP_PERI1_PMS_INT_EN    (BIT(0))
+#define HP_PERI1_PMS_HP_PERI1_PMS_INT_EN_M  (HP_PERI1_PMS_HP_PERI1_PMS_INT_EN_V << HP_PERI1_PMS_HP_PERI1_PMS_INT_EN_S)
+#define HP_PERI1_PMS_HP_PERI1_PMS_INT_EN_V  0x00000001U
+#define HP_PERI1_PMS_HP_PERI1_PMS_INT_EN_S  0
+
+/** HP_PERI1_PMS_BUS_ERR_CONF_REG register
+ *  Clock gating register
+ */
+#define HP_PERI1_PMS_BUS_ERR_CONF_REG (DR_REG_HP_PERI1_PMS_BASE + 0xff0)
+/** HP_PERI1_PMS_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0;
+ *  Configures whether return error response to cpu when access blocked
+ *  0: disable error response
+ *  1: enable error response
+ */
+#define HP_PERI1_PMS_BUS_ERR_RESP_EN    (BIT(0))
+#define HP_PERI1_PMS_BUS_ERR_RESP_EN_M  (HP_PERI1_PMS_BUS_ERR_RESP_EN_V << HP_PERI1_PMS_BUS_ERR_RESP_EN_S)
+#define HP_PERI1_PMS_BUS_ERR_RESP_EN_V  0x00000001U
+#define HP_PERI1_PMS_BUS_ERR_RESP_EN_S  0
+
+/** HP_PERI1_PMS_CLOCK_GATE_REG register
+ *  Clock gating register
+ */
+#define HP_PERI1_PMS_CLOCK_GATE_REG (DR_REG_HP_PERI1_PMS_BASE + 0xff8)
+/** HP_PERI1_PMS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Configures whether to keep the clock always on.
+ *  0: enable automatic clock gating
+ *  1: keep the clock always on
+ */
+#define HP_PERI1_PMS_CLK_EN    (BIT(0))
+#define HP_PERI1_PMS_CLK_EN_M  (HP_PERI1_PMS_CLK_EN_V << HP_PERI1_PMS_CLK_EN_S)
+#define HP_PERI1_PMS_CLK_EN_V  0x00000001U
+#define HP_PERI1_PMS_CLK_EN_S  0
+
+/** HP_PERI1_PMS_DATE_REG register
+ *  Version control register
+ */
+#define HP_PERI1_PMS_DATE_REG (DR_REG_HP_PERI1_PMS_BASE + 0xffc)
+/** HP_PERI1_PMS_DATE : R/W; bitpos: [27:0]; default: 38834720;
+ *  Version control register
+ */
+#define HP_PERI1_PMS_DATE    0x0FFFFFFFU
+#define HP_PERI1_PMS_DATE_M  (HP_PERI1_PMS_DATE_V << HP_PERI1_PMS_DATE_S)
+#define HP_PERI1_PMS_DATE_V  0x0FFFFFFFU
+#define HP_PERI1_PMS_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_peri1_pms_struct.h b/components/soc/esp32s31/register/soc/hp_peri1_pms_struct.h
new file mode 100644
index 00000000000..595651c9a23
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_peri1_pms_struct.h
@@ -0,0 +1,2609 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: read write control register */
+/** Type of hp_usbotg_phy_ctrl register
+ *  hp_usbotg_phy read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_usbotg_phy : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_usbotg_phy registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_usbotg_phy:1;
+        /** read_ree0_hp_usbotg_phy : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_usbotg_phy registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_usbotg_phy:1;
+        /** read_ree1_hp_usbotg_phy : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_usbotg_phy registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_usbotg_phy:1;
+        /** read_ree2_hp_usbotg_phy : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_usbotg_phy registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_usbotg_phy:1;
+        /** write_tee_hp_usbotg_phy : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_usbotg_phy registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_usbotg_phy:1;
+        /** write_ree0_hp_usbotg_phy : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_usbotg_phy registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_usbotg_phy:1;
+        /** write_ree1_hp_usbotg_phy : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_usbotg_phy registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_usbotg_phy:1;
+        /** write_ree2_hp_usbotg_phy : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_usbotg_phy registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_usbotg_phy:1;
+        /** hp_usbotg_phy_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_usbotg_phy peri_apm configuration
+         */
+        uint32_t hp_usbotg_phy_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_usbotg_phy_ctrl_reg_t;
+
+/** Type of hp_mcpwm0_ctrl register
+ *  hp_mcpwm0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mcpwm0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mcpwm0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mcpwm0:1;
+        /** read_ree0_hp_mcpwm0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_mcpwm0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mcpwm0:1;
+        /** read_ree1_hp_mcpwm0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_mcpwm0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mcpwm0:1;
+        /** read_ree2_hp_mcpwm0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_mcpwm0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mcpwm0:1;
+        /** write_tee_hp_mcpwm0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mcpwm0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mcpwm0:1;
+        /** write_ree0_hp_mcpwm0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_mcpwm0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mcpwm0:1;
+        /** write_ree1_hp_mcpwm0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_mcpwm0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mcpwm0:1;
+        /** write_ree2_hp_mcpwm0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_mcpwm0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mcpwm0:1;
+        /** hp_mcpwm0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mcpwm0 peri_apm configuration
+         */
+        uint32_t hp_mcpwm0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_mcpwm0_ctrl_reg_t;
+
+/** Type of hp_mcpwm1_ctrl register
+ *  hp_mcpwm1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mcpwm1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mcpwm1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mcpwm1:1;
+        /** read_ree0_hp_mcpwm1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_mcpwm1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mcpwm1:1;
+        /** read_ree1_hp_mcpwm1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_mcpwm1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mcpwm1:1;
+        /** read_ree2_hp_mcpwm1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_mcpwm1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mcpwm1:1;
+        /** write_tee_hp_mcpwm1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mcpwm1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mcpwm1:1;
+        /** write_ree0_hp_mcpwm1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_mcpwm1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mcpwm1:1;
+        /** write_ree1_hp_mcpwm1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_mcpwm1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mcpwm1:1;
+        /** write_ree2_hp_mcpwm1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_mcpwm1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mcpwm1:1;
+        /** hp_mcpwm1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mcpwm1 peri_apm configuration
+         */
+        uint32_t hp_mcpwm1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_mcpwm1_ctrl_reg_t;
+
+/** Type of hp_mcpwm2_ctrl register
+ *  hp_mcpwm2 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mcpwm2 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mcpwm2 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mcpwm2:1;
+        /** read_ree0_hp_mcpwm2 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_mcpwm2 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mcpwm2:1;
+        /** read_ree1_hp_mcpwm2 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_mcpwm2 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mcpwm2:1;
+        /** read_ree2_hp_mcpwm2 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_mcpwm2 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mcpwm2:1;
+        /** write_tee_hp_mcpwm2 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mcpwm2 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mcpwm2:1;
+        /** write_ree0_hp_mcpwm2 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_mcpwm2 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mcpwm2:1;
+        /** write_ree1_hp_mcpwm2 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_mcpwm2 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mcpwm2:1;
+        /** write_ree2_hp_mcpwm2 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_mcpwm2 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mcpwm2:1;
+        /** hp_mcpwm2_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mcpwm2 peri_apm configuration
+         */
+        uint32_t hp_mcpwm2_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_mcpwm2_ctrl_reg_t;
+
+/** Type of hp_mcpwm3_ctrl register
+ *  hp_mcpwm3 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mcpwm3 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mcpwm3 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mcpwm3:1;
+        /** read_ree0_hp_mcpwm3 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_mcpwm3 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mcpwm3:1;
+        /** read_ree1_hp_mcpwm3 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_mcpwm3 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mcpwm3:1;
+        /** read_ree2_hp_mcpwm3 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_mcpwm3 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mcpwm3:1;
+        /** write_tee_hp_mcpwm3 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mcpwm3 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mcpwm3:1;
+        /** write_ree0_hp_mcpwm3 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_mcpwm3 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mcpwm3:1;
+        /** write_ree1_hp_mcpwm3 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_mcpwm3 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mcpwm3:1;
+        /** write_ree2_hp_mcpwm3 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_mcpwm3 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mcpwm3:1;
+        /** hp_mcpwm3_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mcpwm3 peri_apm configuration
+         */
+        uint32_t hp_mcpwm3_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_mcpwm3_ctrl_reg_t;
+
+/** Type of hp_i2c0_ctrl register
+ *  hp_i2c0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_i2c0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_i2c0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_i2c0:1;
+        /** read_ree0_hp_i2c0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_i2c0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_i2c0:1;
+        /** read_ree1_hp_i2c0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_i2c0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_i2c0:1;
+        /** read_ree2_hp_i2c0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_i2c0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_i2c0:1;
+        /** write_tee_hp_i2c0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_i2c0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_i2c0:1;
+        /** write_ree0_hp_i2c0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_i2c0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_i2c0:1;
+        /** write_ree1_hp_i2c0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_i2c0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_i2c0:1;
+        /** write_ree2_hp_i2c0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_i2c0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_i2c0:1;
+        /** hp_i2c0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_i2c0 peri_apm configuration
+         */
+        uint32_t hp_i2c0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_i2c0_ctrl_reg_t;
+
+/** Type of hp_i2c1_ctrl register
+ *  hp_i2c1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_i2c1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_i2c1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_i2c1:1;
+        /** read_ree0_hp_i2c1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_i2c1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_i2c1:1;
+        /** read_ree1_hp_i2c1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_i2c1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_i2c1:1;
+        /** read_ree2_hp_i2c1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_i2c1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_i2c1:1;
+        /** write_tee_hp_i2c1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_i2c1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_i2c1:1;
+        /** write_ree0_hp_i2c1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_i2c1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_i2c1:1;
+        /** write_ree1_hp_i2c1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_i2c1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_i2c1:1;
+        /** write_ree2_hp_i2c1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_i2c1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_i2c1:1;
+        /** hp_i2c1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_i2c1 peri_apm configuration
+         */
+        uint32_t hp_i2c1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_i2c1_ctrl_reg_t;
+
+/** Type of hp_i2s0_ctrl register
+ *  hp_i2s0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_i2s0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_i2s0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_i2s0:1;
+        /** read_ree0_hp_i2s0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_i2s0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_i2s0:1;
+        /** read_ree1_hp_i2s0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_i2s0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_i2s0:1;
+        /** read_ree2_hp_i2s0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_i2s0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_i2s0:1;
+        /** write_tee_hp_i2s0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_i2s0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_i2s0:1;
+        /** write_ree0_hp_i2s0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_i2s0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_i2s0:1;
+        /** write_ree1_hp_i2s0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_i2s0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_i2s0:1;
+        /** write_ree2_hp_i2s0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_i2s0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_i2s0:1;
+        /** hp_i2s0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_i2s0 peri_apm configuration
+         */
+        uint32_t hp_i2s0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_i2s0_ctrl_reg_t;
+
+/** Type of hp_i2s1_ctrl register
+ *  hp_i2s1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_i2s1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_i2s1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_i2s1:1;
+        /** read_ree0_hp_i2s1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_i2s1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_i2s1:1;
+        /** read_ree1_hp_i2s1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_i2s1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_i2s1:1;
+        /** read_ree2_hp_i2s1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_i2s1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_i2s1:1;
+        /** write_tee_hp_i2s1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_i2s1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_i2s1:1;
+        /** write_ree0_hp_i2s1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_i2s1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_i2s1:1;
+        /** write_ree1_hp_i2s1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_i2s1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_i2s1:1;
+        /** write_ree2_hp_i2s1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_i2s1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_i2s1:1;
+        /** hp_i2s1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_i2s1 peri_apm configuration
+         */
+        uint32_t hp_i2s1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_i2s1_ctrl_reg_t;
+
+/** Type of hp_pcnt0_ctrl register
+ *  hp_pcnt0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_pcnt0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_pcnt0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_pcnt0:1;
+        /** read_ree0_hp_pcnt0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_pcnt0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_pcnt0:1;
+        /** read_ree1_hp_pcnt0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_pcnt0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_pcnt0:1;
+        /** read_ree2_hp_pcnt0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_pcnt0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_pcnt0:1;
+        /** write_tee_hp_pcnt0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_pcnt0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_pcnt0:1;
+        /** write_ree0_hp_pcnt0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_pcnt0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_pcnt0:1;
+        /** write_ree1_hp_pcnt0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_pcnt0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_pcnt0:1;
+        /** write_ree2_hp_pcnt0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_pcnt0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_pcnt0:1;
+        /** hp_pcnt0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_pcnt0 peri_apm configuration
+         */
+        uint32_t hp_pcnt0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_pcnt0_ctrl_reg_t;
+
+/** Type of hp_uart0_ctrl register
+ *  hp_uart0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_uart0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_uart0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_uart0:1;
+        /** read_ree0_hp_uart0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_uart0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_uart0:1;
+        /** read_ree1_hp_uart0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_uart0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_uart0:1;
+        /** read_ree2_hp_uart0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_uart0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_uart0:1;
+        /** write_tee_hp_uart0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_uart0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_uart0:1;
+        /** write_ree0_hp_uart0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_uart0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_uart0:1;
+        /** write_ree1_hp_uart0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_uart0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_uart0:1;
+        /** write_ree2_hp_uart0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_uart0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_uart0:1;
+        /** hp_uart0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_uart0 peri_apm configuration
+         */
+        uint32_t hp_uart0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_uart0_ctrl_reg_t;
+
+/** Type of hp_uart1_ctrl register
+ *  hp_uart1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_uart1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_uart1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_uart1:1;
+        /** read_ree0_hp_uart1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_uart1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_uart1:1;
+        /** read_ree1_hp_uart1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_uart1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_uart1:1;
+        /** read_ree2_hp_uart1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_uart1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_uart1:1;
+        /** write_tee_hp_uart1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_uart1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_uart1:1;
+        /** write_ree0_hp_uart1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_uart1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_uart1:1;
+        /** write_ree1_hp_uart1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_uart1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_uart1:1;
+        /** write_ree2_hp_uart1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_uart1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_uart1:1;
+        /** hp_uart1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_uart1 peri_apm configuration
+         */
+        uint32_t hp_uart1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_uart1_ctrl_reg_t;
+
+/** Type of hp_uart2_ctrl register
+ *  hp_uart2 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_uart2 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_uart2 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_uart2:1;
+        /** read_ree0_hp_uart2 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_uart2 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_uart2:1;
+        /** read_ree1_hp_uart2 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_uart2 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_uart2:1;
+        /** read_ree2_hp_uart2 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_uart2 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_uart2:1;
+        /** write_tee_hp_uart2 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_uart2 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_uart2:1;
+        /** write_ree0_hp_uart2 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_uart2 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_uart2:1;
+        /** write_ree1_hp_uart2 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_uart2 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_uart2:1;
+        /** write_ree2_hp_uart2 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_uart2 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_uart2:1;
+        /** hp_uart2_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_uart2 peri_apm configuration
+         */
+        uint32_t hp_uart2_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_uart2_ctrl_reg_t;
+
+/** Type of hp_uart3_ctrl register
+ *  hp_uart3 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_uart3 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_uart3 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_uart3:1;
+        /** read_ree0_hp_uart3 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_uart3 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_uart3:1;
+        /** read_ree1_hp_uart3 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_uart3 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_uart3:1;
+        /** read_ree2_hp_uart3 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_uart3 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_uart3:1;
+        /** write_tee_hp_uart3 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_uart3 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_uart3:1;
+        /** write_ree0_hp_uart3 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_uart3 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_uart3:1;
+        /** write_ree1_hp_uart3 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_uart3 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_uart3:1;
+        /** write_ree2_hp_uart3 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_uart3 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_uart3:1;
+        /** hp_uart3_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_uart3 peri_apm configuration
+         */
+        uint32_t hp_uart3_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_uart3_ctrl_reg_t;
+
+/** Type of hp_parlio_ctrl register
+ *  hp_parlio read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_parlio : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_parlio registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_parlio:1;
+        /** read_ree0_hp_parlio : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_parlio registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_parlio:1;
+        /** read_ree1_hp_parlio : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_parlio registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_parlio:1;
+        /** read_ree2_hp_parlio : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_parlio registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_parlio:1;
+        /** write_tee_hp_parlio : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_parlio registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_parlio:1;
+        /** write_ree0_hp_parlio : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_parlio registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_parlio:1;
+        /** write_ree1_hp_parlio : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_parlio registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_parlio:1;
+        /** write_ree2_hp_parlio : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_parlio registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_parlio:1;
+        /** hp_parlio_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_parlio peri_apm configuration
+         */
+        uint32_t hp_parlio_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_parlio_ctrl_reg_t;
+
+/** Type of hp_gpspi2_ctrl register
+ *  hp_gpspi2 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_gpspi2 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_gpspi2 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_gpspi2:1;
+        /** read_ree0_hp_gpspi2 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_gpspi2 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_gpspi2:1;
+        /** read_ree1_hp_gpspi2 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_gpspi2 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_gpspi2:1;
+        /** read_ree2_hp_gpspi2 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_gpspi2 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_gpspi2:1;
+        /** write_tee_hp_gpspi2 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_gpspi2 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_gpspi2:1;
+        /** write_ree0_hp_gpspi2 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_gpspi2 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_gpspi2:1;
+        /** write_ree1_hp_gpspi2 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_gpspi2 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_gpspi2:1;
+        /** write_ree2_hp_gpspi2 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_gpspi2 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_gpspi2:1;
+        /** hp_gpspi2_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_gpspi2 peri_apm configuration
+         */
+        uint32_t hp_gpspi2_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_gpspi2_ctrl_reg_t;
+
+/** Type of hp_gpspi3_ctrl register
+ *  hp_gpspi3 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_gpspi3 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_gpspi3 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_gpspi3:1;
+        /** read_ree0_hp_gpspi3 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_gpspi3 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_gpspi3:1;
+        /** read_ree1_hp_gpspi3 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_gpspi3 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_gpspi3:1;
+        /** read_ree2_hp_gpspi3 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_gpspi3 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_gpspi3:1;
+        /** write_tee_hp_gpspi3 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_gpspi3 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_gpspi3:1;
+        /** write_ree0_hp_gpspi3 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_gpspi3 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_gpspi3:1;
+        /** write_ree1_hp_gpspi3 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_gpspi3 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_gpspi3:1;
+        /** write_ree2_hp_gpspi3 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_gpspi3 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_gpspi3:1;
+        /** hp_gpspi3_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_gpspi3 peri_apm configuration
+         */
+        uint32_t hp_gpspi3_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_gpspi3_ctrl_reg_t;
+
+/** Type of hp_usbdevice_ctrl register
+ *  hp_usbdevice read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_usbdevice : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_usbdevice registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_usbdevice:1;
+        /** read_ree0_hp_usbdevice : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_usbdevice registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_usbdevice:1;
+        /** read_ree1_hp_usbdevice : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_usbdevice registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_usbdevice:1;
+        /** read_ree2_hp_usbdevice : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_usbdevice registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_usbdevice:1;
+        /** write_tee_hp_usbdevice : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_usbdevice registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_usbdevice:1;
+        /** write_ree0_hp_usbdevice : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_usbdevice registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_usbdevice:1;
+        /** write_ree1_hp_usbdevice : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_usbdevice registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_usbdevice:1;
+        /** write_ree2_hp_usbdevice : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_usbdevice registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_usbdevice:1;
+        /** hp_usbdevice_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_usbdevice peri_apm configuration
+         */
+        uint32_t hp_usbdevice_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_usbdevice_ctrl_reg_t;
+
+/** Type of hp_ledc0_ctrl register
+ *  hp_ledc0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_ledc0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_ledc0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_ledc0:1;
+        /** read_ree0_hp_ledc0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_ledc0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_ledc0:1;
+        /** read_ree1_hp_ledc0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_ledc0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_ledc0:1;
+        /** read_ree2_hp_ledc0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_ledc0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_ledc0:1;
+        /** write_tee_hp_ledc0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_ledc0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_ledc0:1;
+        /** write_ree0_hp_ledc0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_ledc0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_ledc0:1;
+        /** write_ree1_hp_ledc0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_ledc0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_ledc0:1;
+        /** write_ree2_hp_ledc0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_ledc0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_ledc0:1;
+        /** hp_ledc0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_ledc0 peri_apm configuration
+         */
+        uint32_t hp_ledc0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_ledc0_ctrl_reg_t;
+
+/** Type of hp_etm_ctrl register
+ *  hp_etm read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_etm : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_etm registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_etm:1;
+        /** read_ree0_hp_etm : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_etm registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_etm:1;
+        /** read_ree1_hp_etm : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_etm registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_etm:1;
+        /** read_ree2_hp_etm : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_etm registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_etm:1;
+        /** write_tee_hp_etm : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_etm registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_etm:1;
+        /** write_ree0_hp_etm : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_etm registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_etm:1;
+        /** write_ree1_hp_etm : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_etm registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_etm:1;
+        /** write_ree2_hp_etm : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_etm registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_etm:1;
+        /** hp_etm_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_etm peri_apm configuration
+         */
+        uint32_t hp_etm_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_etm_ctrl_reg_t;
+
+/** Type of hp_twai0_ctrl register
+ *  hp_twai0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_twai0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_twai0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_twai0:1;
+        /** read_ree0_hp_twai0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_twai0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_twai0:1;
+        /** read_ree1_hp_twai0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_twai0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_twai0:1;
+        /** read_ree2_hp_twai0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_twai0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_twai0:1;
+        /** write_tee_hp_twai0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_twai0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_twai0:1;
+        /** write_ree0_hp_twai0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_twai0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_twai0:1;
+        /** write_ree1_hp_twai0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_twai0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_twai0:1;
+        /** write_ree2_hp_twai0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_twai0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_twai0:1;
+        /** hp_twai0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_twai0 peri_apm configuration
+         */
+        uint32_t hp_twai0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_twai0_ctrl_reg_t;
+
+/** Type of hp_twai1_ctrl register
+ *  hp_twai1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_twai1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_twai1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_twai1:1;
+        /** read_ree0_hp_twai1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_twai1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_twai1:1;
+        /** read_ree1_hp_twai1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_twai1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_twai1:1;
+        /** read_ree2_hp_twai1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_twai1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_twai1:1;
+        /** write_tee_hp_twai1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_twai1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_twai1:1;
+        /** write_ree0_hp_twai1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_twai1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_twai1:1;
+        /** write_ree1_hp_twai1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_twai1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_twai1:1;
+        /** write_ree2_hp_twai1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_twai1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_twai1:1;
+        /** hp_twai1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_twai1 peri_apm configuration
+         */
+        uint32_t hp_twai1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_twai1_ctrl_reg_t;
+
+/** Type of hp_lcdcam_ctrl register
+ *  hp_lcdcam read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_lcdcam : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_lcdcam registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_lcdcam:1;
+        /** read_ree0_hp_lcdcam : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_lcdcam registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_lcdcam:1;
+        /** read_ree1_hp_lcdcam : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_lcdcam registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_lcdcam:1;
+        /** read_ree2_hp_lcdcam : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_lcdcam registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_lcdcam:1;
+        /** write_tee_hp_lcdcam : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_lcdcam registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_lcdcam:1;
+        /** write_ree0_hp_lcdcam : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_lcdcam registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_lcdcam:1;
+        /** write_ree1_hp_lcdcam : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_lcdcam registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_lcdcam:1;
+        /** write_ree2_hp_lcdcam : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_lcdcam registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_lcdcam:1;
+        /** hp_lcdcam_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_lcdcam peri_apm configuration
+         */
+        uint32_t hp_lcdcam_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_lcdcam_ctrl_reg_t;
+
+/** Type of hp_uhci_ctrl register
+ *  hp_uhci read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_uhci : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_uhci registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_uhci:1;
+        /** read_ree0_hp_uhci : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_uhci registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_uhci:1;
+        /** read_ree1_hp_uhci : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_uhci registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_uhci:1;
+        /** read_ree2_hp_uhci : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_uhci registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_uhci:1;
+        /** write_tee_hp_uhci : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_uhci registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_uhci:1;
+        /** write_ree0_hp_uhci : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_uhci registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_uhci:1;
+        /** write_ree1_hp_uhci : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_uhci registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_uhci:1;
+        /** write_ree2_hp_uhci : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_uhci registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_uhci:1;
+        /** hp_uhci_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_uhci peri_apm configuration
+         */
+        uint32_t hp_uhci_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_uhci_ctrl_reg_t;
+
+/** Type of hp_systimer_ctrl register
+ *  hp_systimer read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_systimer : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_systimer registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_systimer:1;
+        /** read_ree0_hp_systimer : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_systimer registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_systimer:1;
+        /** read_ree1_hp_systimer : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_systimer registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_systimer:1;
+        /** read_ree2_hp_systimer : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_systimer registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_systimer:1;
+        /** write_tee_hp_systimer : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_systimer registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_systimer:1;
+        /** write_ree0_hp_systimer : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_systimer registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_systimer:1;
+        /** write_ree1_hp_systimer : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_systimer registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_systimer:1;
+        /** write_ree2_hp_systimer : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_systimer registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_systimer:1;
+        /** hp_systimer_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_systimer peri_apm configuration
+         */
+        uint32_t hp_systimer_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_systimer_ctrl_reg_t;
+
+/** Type of hp_zero_det_ctrl register
+ *  hp_zero_det read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_zero_det : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_zero_det registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_zero_det:1;
+        /** read_ree0_hp_zero_det : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_zero_det registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_zero_det:1;
+        /** read_ree1_hp_zero_det : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_zero_det registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_zero_det:1;
+        /** read_ree2_hp_zero_det : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_zero_det registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_zero_det:1;
+        /** write_tee_hp_zero_det : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_zero_det registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_zero_det:1;
+        /** write_ree0_hp_zero_det : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_zero_det registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_zero_det:1;
+        /** write_ree1_hp_zero_det : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_zero_det registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_zero_det:1;
+        /** write_ree2_hp_zero_det : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_zero_det registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_zero_det:1;
+        /** hp_zero_det_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_zero_det peri_apm configuration
+         */
+        uint32_t hp_zero_det_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_zero_det_ctrl_reg_t;
+
+/** Type of hp_cordic_ctrl register
+ *  hp_cordic read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_cordic : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_cordic registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_cordic:1;
+        /** read_ree0_hp_cordic : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_cordic registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_cordic:1;
+        /** read_ree1_hp_cordic : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_cordic registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_cordic:1;
+        /** read_ree2_hp_cordic : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_cordic registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_cordic:1;
+        /** write_tee_hp_cordic : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_cordic registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_cordic:1;
+        /** write_ree0_hp_cordic : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_cordic registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_cordic:1;
+        /** write_ree1_hp_cordic : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_cordic registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_cordic:1;
+        /** write_ree2_hp_cordic : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_cordic registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_cordic:1;
+        /** hp_cordic_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_cordic peri_apm configuration
+         */
+        uint32_t hp_cordic_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_cordic_ctrl_reg_t;
+
+/** Type of hp_ledc1_ctrl register
+ *  hp_ledc1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_ledc1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_ledc1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_ledc1:1;
+        /** read_ree0_hp_ledc1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_ledc1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_ledc1:1;
+        /** read_ree1_hp_ledc1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_ledc1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_ledc1:1;
+        /** read_ree2_hp_ledc1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_ledc1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_ledc1:1;
+        /** write_tee_hp_ledc1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_ledc1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_ledc1:1;
+        /** write_ree0_hp_ledc1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_ledc1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_ledc1:1;
+        /** write_ree1_hp_ledc1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_ledc1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_ledc1:1;
+        /** write_ree2_hp_ledc1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_ledc1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_ledc1:1;
+        /** hp_ledc1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_ledc1 peri_apm configuration
+         */
+        uint32_t hp_ledc1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_ledc1_ctrl_reg_t;
+
+/** Type of hp_pcnt1_ctrl register
+ *  hp_pcnt1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_pcnt1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_pcnt1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_pcnt1:1;
+        /** read_ree0_hp_pcnt1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_pcnt1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_pcnt1:1;
+        /** read_ree1_hp_pcnt1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_pcnt1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_pcnt1:1;
+        /** read_ree2_hp_pcnt1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_pcnt1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_pcnt1:1;
+        /** write_tee_hp_pcnt1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_pcnt1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_pcnt1:1;
+        /** write_ree0_hp_pcnt1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_pcnt1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_pcnt1:1;
+        /** write_ree1_hp_pcnt1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_pcnt1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_pcnt1:1;
+        /** write_ree2_hp_pcnt1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_pcnt1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_pcnt1:1;
+        /** hp_pcnt1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_pcnt1 peri_apm configuration
+         */
+        uint32_t hp_pcnt1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_pcnt1_ctrl_reg_t;
+
+/** Type of hp_timer_group0_ctrl register
+ *  hp_timer_group0 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_timer_group0 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_timer_group0 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_timer_group0:1;
+        /** read_ree0_hp_timer_group0 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_timer_group0 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_timer_group0:1;
+        /** read_ree1_hp_timer_group0 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_timer_group0 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_timer_group0:1;
+        /** read_ree2_hp_timer_group0 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_timer_group0 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_timer_group0:1;
+        /** write_tee_hp_timer_group0 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_timer_group0 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_timer_group0:1;
+        /** write_ree0_hp_timer_group0 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_timer_group0 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_timer_group0:1;
+        /** write_ree1_hp_timer_group0 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_timer_group0 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_timer_group0:1;
+        /** write_ree2_hp_timer_group0 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_timer_group0 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_timer_group0:1;
+        /** hp_timer_group0_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_timer_group0 peri_apm configuration
+         */
+        uint32_t hp_timer_group0_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_timer_group0_ctrl_reg_t;
+
+/** Type of hp_timer_group1_ctrl register
+ *  hp_timer_group1 read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_timer_group1 : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_timer_group1 registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_timer_group1:1;
+        /** read_ree0_hp_timer_group1 : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_timer_group1 registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_timer_group1:1;
+        /** read_ree1_hp_timer_group1 : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_timer_group1 registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_timer_group1:1;
+        /** read_ree2_hp_timer_group1 : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_timer_group1 registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_timer_group1:1;
+        /** write_tee_hp_timer_group1 : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_timer_group1 registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_timer_group1:1;
+        /** write_ree0_hp_timer_group1 : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_timer_group1 registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_timer_group1:1;
+        /** write_ree1_hp_timer_group1 : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_timer_group1 registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_timer_group1:1;
+        /** write_ree2_hp_timer_group1 : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_timer_group1 registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_timer_group1:1;
+        /** hp_timer_group1_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_timer_group1 peri_apm configuration
+         */
+        uint32_t hp_timer_group1_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_timer_group1_ctrl_reg_t;
+
+/** Type of hp_iomux_ctrl register
+ *  hp_iomux read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_iomux : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_iomux registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_iomux:1;
+        /** read_ree0_hp_iomux : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_iomux registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_iomux:1;
+        /** read_ree1_hp_iomux : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_iomux registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_iomux:1;
+        /** read_ree2_hp_iomux : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_iomux registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_iomux:1;
+        /** write_tee_hp_iomux : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_iomux registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_iomux:1;
+        /** write_ree0_hp_iomux : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_iomux registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_iomux:1;
+        /** write_ree1_hp_iomux : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_iomux registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_iomux:1;
+        /** write_ree2_hp_iomux : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_iomux registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_iomux:1;
+        /** hp_iomux_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_iomux peri_apm configuration
+         */
+        uint32_t hp_iomux_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_iomux_ctrl_reg_t;
+
+/** Type of hp_mspi_padctrl_ctrl register
+ *  hp_mspi_padctrl read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_mspi_padctrl : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_mspi_padctrl registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_mspi_padctrl:1;
+        /** read_ree0_hp_mspi_padctrl : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_mspi_padctrl registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_mspi_padctrl:1;
+        /** read_ree1_hp_mspi_padctrl : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_mspi_padctrl registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_mspi_padctrl:1;
+        /** read_ree2_hp_mspi_padctrl : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_mspi_padctrl registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_mspi_padctrl:1;
+        /** write_tee_hp_mspi_padctrl : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_mspi_padctrl registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_mspi_padctrl:1;
+        /** write_ree0_hp_mspi_padctrl : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_mspi_padctrl registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_mspi_padctrl:1;
+        /** write_ree1_hp_mspi_padctrl : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_mspi_padctrl registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_mspi_padctrl:1;
+        /** write_ree2_hp_mspi_padctrl : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_mspi_padctrl registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_mspi_padctrl:1;
+        /** hp_mspi_padctrl_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_mspi_padctrl peri_apm configuration
+         */
+        uint32_t hp_mspi_padctrl_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_mspi_padctrl_ctrl_reg_t;
+
+/** Type of hp_intrmtx_ctrl register
+ *  hp_intrmtx read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_intrmtx : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_intrmtx registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_intrmtx:1;
+        /** read_ree0_hp_intrmtx : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_intrmtx registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_intrmtx:1;
+        /** read_ree1_hp_intrmtx : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_intrmtx registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_intrmtx:1;
+        /** read_ree2_hp_intrmtx : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_intrmtx registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_intrmtx:1;
+        /** write_tee_hp_intrmtx : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_intrmtx registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_intrmtx:1;
+        /** write_ree0_hp_intrmtx : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_intrmtx registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_intrmtx:1;
+        /** write_ree1_hp_intrmtx : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_intrmtx registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_intrmtx:1;
+        /** write_ree2_hp_intrmtx : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_intrmtx registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_intrmtx:1;
+        /** hp_intrmtx_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_intrmtx peri_apm configuration
+         */
+        uint32_t hp_intrmtx_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_intrmtx_ctrl_reg_t;
+
+/** Type of hp_sys_reg_ctrl register
+ *  hp_sys_reg read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_sys_reg : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_sys_reg registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_sys_reg:1;
+        /** read_ree0_hp_sys_reg : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_sys_reg registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_sys_reg:1;
+        /** read_ree1_hp_sys_reg : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_sys_reg registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_sys_reg:1;
+        /** read_ree2_hp_sys_reg : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_sys_reg registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_sys_reg:1;
+        /** write_tee_hp_sys_reg : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_sys_reg registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_sys_reg:1;
+        /** write_ree0_hp_sys_reg : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_sys_reg registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_sys_reg:1;
+        /** write_ree1_hp_sys_reg : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_sys_reg registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_sys_reg:1;
+        /** write_ree2_hp_sys_reg : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_sys_reg registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_sys_reg:1;
+        /** hp_sys_reg_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_sys_reg peri_apm configuration
+         */
+        uint32_t hp_sys_reg_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_sys_reg_ctrl_reg_t;
+
+/** Type of hp_clkrst_ctrl register
+ *  hp_clkrst read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_clkrst : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_clkrst registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_clkrst:1;
+        /** read_ree0_hp_clkrst : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_clkrst registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_clkrst:1;
+        /** read_ree1_hp_clkrst : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_clkrst registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_clkrst:1;
+        /** read_ree2_hp_clkrst : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_clkrst registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_clkrst:1;
+        /** write_tee_hp_clkrst : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_clkrst registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_clkrst:1;
+        /** write_ree0_hp_clkrst : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_clkrst registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_clkrst:1;
+        /** write_ree1_hp_clkrst : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_clkrst registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_clkrst:1;
+        /** write_ree2_hp_clkrst : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_clkrst registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_clkrst:1;
+        /** hp_clkrst_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_clkrst peri_apm configuration
+         */
+        uint32_t hp_clkrst_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_clkrst_ctrl_reg_t;
+
+/** Type of cnnt_pad_ctrl_ctrl register
+ *  cnnt_pad_ctrl read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_cnnt_pad_ctrl : R/W; bitpos: [0]; default: 1;
+         *  Configures cnnt_pad_ctrl registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_cnnt_pad_ctrl:1;
+        /** read_ree0_cnnt_pad_ctrl : R/W; bitpos: [1]; default: 0;
+         *  Configures cnnt_pad_ctrl registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_cnnt_pad_ctrl:1;
+        /** read_ree1_cnnt_pad_ctrl : R/W; bitpos: [2]; default: 0;
+         *  Configures cnnt_pad_ctrl registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_cnnt_pad_ctrl:1;
+        /** read_ree2_cnnt_pad_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Configures cnnt_pad_ctrl registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_cnnt_pad_ctrl:1;
+        /** write_tee_cnnt_pad_ctrl : R/W; bitpos: [4]; default: 1;
+         *  Configures cnnt_pad_ctrl registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_cnnt_pad_ctrl:1;
+        /** write_ree0_cnnt_pad_ctrl : R/W; bitpos: [5]; default: 0;
+         *  Configures cnnt_pad_ctrl registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_cnnt_pad_ctrl:1;
+        /** write_ree1_cnnt_pad_ctrl : R/W; bitpos: [6]; default: 0;
+         *  Configures cnnt_pad_ctrl registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_cnnt_pad_ctrl:1;
+        /** write_ree2_cnnt_pad_ctrl : R/W; bitpos: [7]; default: 0;
+         *  Configures cnnt_pad_ctrl registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_cnnt_pad_ctrl:1;
+        /** cnnt_pad_ctrl_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock cnnt_pad_ctrl peri_apm configuration
+         */
+        uint32_t cnnt_pad_ctrl_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_cnnt_pad_ctrl_ctrl_reg_t;
+
+/** Type of hp_alive_sys_reg_ctrl register
+ *  hp_alive_sys_reg read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_alive_sys_reg : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_alive_sys_reg registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_alive_sys_reg:1;
+        /** read_ree0_hp_alive_sys_reg : R/W; bitpos: [1]; default: 0;
+         *  Configures hp_alive_sys_reg registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_alive_sys_reg:1;
+        /** read_ree1_hp_alive_sys_reg : R/W; bitpos: [2]; default: 0;
+         *  Configures hp_alive_sys_reg registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_alive_sys_reg:1;
+        /** read_ree2_hp_alive_sys_reg : R/W; bitpos: [3]; default: 0;
+         *  Configures hp_alive_sys_reg registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_alive_sys_reg:1;
+        /** write_tee_hp_alive_sys_reg : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_alive_sys_reg registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_alive_sys_reg:1;
+        /** write_ree0_hp_alive_sys_reg : R/W; bitpos: [5]; default: 0;
+         *  Configures hp_alive_sys_reg registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_alive_sys_reg:1;
+        /** write_ree1_hp_alive_sys_reg : R/W; bitpos: [6]; default: 0;
+         *  Configures hp_alive_sys_reg registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_alive_sys_reg:1;
+        /** write_ree2_hp_alive_sys_reg : R/W; bitpos: [7]; default: 0;
+         *  Configures hp_alive_sys_reg registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_alive_sys_reg:1;
+        /** hp_alive_sys_reg_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_alive_sys_reg peri_apm configuration
+         */
+        uint32_t hp_alive_sys_reg_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_alive_sys_reg_ctrl_reg_t;
+
+/** Type of hp_peri1_pms_ctrl register
+ *  hp_peri1_pms read/write control register
+ */
+typedef union {
+    struct {
+        /** read_tee_hp_peri1_pms : R/W; bitpos: [0]; default: 1;
+         *  Configures hp_peri1_pms registers read permission in tee mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_tee_hp_peri1_pms:1;
+        /** read_ree0_hp_peri1_pms : HRO; bitpos: [1]; default: 0;
+         *  Configures hp_peri1_pms registers read permission in ree0 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree0_hp_peri1_pms:1;
+        /** read_ree1_hp_peri1_pms : HRO; bitpos: [2]; default: 0;
+         *  Configures hp_peri1_pms registers read permission in ree1 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree1_hp_peri1_pms:1;
+        /** read_ree2_hp_peri1_pms : HRO; bitpos: [3]; default: 0;
+         *  Configures hp_peri1_pms registers read permission in ree2 mode.
+         *  0: can not be read
+         *  1: can be read
+         */
+        uint32_t read_ree2_hp_peri1_pms:1;
+        /** write_tee_hp_peri1_pms : R/W; bitpos: [4]; default: 1;
+         *  Configures hp_peri1_pms registers write permission in tee mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_tee_hp_peri1_pms:1;
+        /** write_ree0_hp_peri1_pms : HRO; bitpos: [5]; default: 0;
+         *  Configures hp_peri1_pms registers write permission in ree0 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree0_hp_peri1_pms:1;
+        /** write_ree1_hp_peri1_pms : HRO; bitpos: [6]; default: 0;
+         *  Configures hp_peri1_pms registers write permission in ree1 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree1_hp_peri1_pms:1;
+        /** write_ree2_hp_peri1_pms : HRO; bitpos: [7]; default: 0;
+         *  Configures hp_peri1_pms registers write permission in ree2 mode.
+         *  0: can not be write
+         *  1: can be write
+         */
+        uint32_t write_ree2_hp_peri1_pms:1;
+        /** hp_peri1_pms_lock : R/W; bitpos: [8]; default: 0;
+         *  Set 1 to lock hp_peri1_pms peri_apm configuration
+         */
+        uint32_t hp_peri1_pms_lock:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_peri1_pms_ctrl_reg_t;
+
+
+/** Group: PMS Register */
+/** Type of hp_peri1_0 register
+ *  HP_PERI1 PMS configuration & info register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_pms_exception_clr : WT; bitpos: [0]; default: 0;
+         *  Configures whether or not to clear hp_peri1 peri_pms_record_reg.
+         *  0: No clear
+         *  1: Clear peri_pms_record_reg
+         */
+        uint32_t hp_peri1_pms_exception_clr:1;
+        /** hp_peri1_pms_exception_det : RO; bitpos: [1]; default: 0;
+         *  Represents whether the hp_peri1 pms has been triggered.
+         *  0: No triggered
+         *  1: Has been triggered
+         */
+        uint32_t hp_peri1_pms_exception_det:1;
+        /** hp_peri1_pms_exception_id : RO; bitpos: [7:2]; default: 0;
+         *  Represents the master id when hp_peri1 pms has been triggered.
+         */
+        uint32_t hp_peri1_pms_exception_id:6;
+        /** hp_peri1_pms_exception_mode : RO; bitpos: [9:8]; default: 0;
+         *  Represents the security mode when hp_peri1 pms has been triggered.
+         */
+        uint32_t hp_peri1_pms_exception_mode:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_peri1_0_reg_t;
+
+/** Type of hp_peri1_1 register
+ *  HP_PERI1 PMS exception addr record register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_pms_exception_addr : RO; bitpos: [27:0]; default: 0;
+         *  Represents the access address (bit27~bit0) when hp_peri1 pms has been triggered.
+         */
+        uint32_t hp_peri1_pms_exception_addr:28;
+        /** hp_peri1_pms_exception_addr_const : HRO; bitpos: [31:28]; default: 2;
+         *  Represents the access address (bit31~bit28) when hp_peri1 pms has been triggered.
+         */
+        uint32_t hp_peri1_pms_exception_addr_const:4;
+    };
+    uint32_t val;
+} hp_peri1_pms_hp_peri1_1_reg_t;
+
+/** Type of int_en register
+ *  APM interrupt enable register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_pms_int_en : R/W; bitpos: [0]; default: 0;
+         *  Configures to enable hp_peri1 pms interrupt.
+         *  0: disable
+         *  1: enable
+         */
+        uint32_t hp_peri1_pms_int_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri1_pms_int_en_reg_t;
+
+
+/** Group: config register */
+/** Type of bus_err_conf register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** bus_err_resp_en : R/W; bitpos: [0]; default: 0;
+         *  Configures whether return error response to cpu when access blocked
+         *  0: disable error response
+         *  1: enable error response
+         */
+        uint32_t bus_err_resp_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri1_pms_bus_err_conf_reg_t;
+
+
+/** Group: clock gating register */
+/** Type of clock_gate register
+ *  Clock gating register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Configures whether to keep the clock always on.
+         *  0: enable automatic clock gating
+         *  1: keep the clock always on
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_peri1_pms_clock_gate_reg_t;
+
+
+/** Group: Version control register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38834720;
+         *  Version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_peri1_pms_date_reg_t;
+
+
+typedef struct {
+    volatile hp_peri1_pms_hp_usbotg_phy_ctrl_reg_t hp_usbotg_phy_ctrl;
+    volatile hp_peri1_pms_hp_mcpwm0_ctrl_reg_t hp_mcpwm0_ctrl;
+    volatile hp_peri1_pms_hp_mcpwm1_ctrl_reg_t hp_mcpwm1_ctrl;
+    volatile hp_peri1_pms_hp_mcpwm2_ctrl_reg_t hp_mcpwm2_ctrl;
+    volatile hp_peri1_pms_hp_mcpwm3_ctrl_reg_t hp_mcpwm3_ctrl;
+    volatile hp_peri1_pms_hp_i2c0_ctrl_reg_t hp_i2c0_ctrl;
+    volatile hp_peri1_pms_hp_i2c1_ctrl_reg_t hp_i2c1_ctrl;
+    volatile hp_peri1_pms_hp_i2s0_ctrl_reg_t hp_i2s0_ctrl;
+    volatile hp_peri1_pms_hp_i2s1_ctrl_reg_t hp_i2s1_ctrl;
+    volatile hp_peri1_pms_hp_pcnt0_ctrl_reg_t hp_pcnt0_ctrl;
+    volatile hp_peri1_pms_hp_uart0_ctrl_reg_t hp_uart0_ctrl;
+    volatile hp_peri1_pms_hp_uart1_ctrl_reg_t hp_uart1_ctrl;
+    volatile hp_peri1_pms_hp_uart2_ctrl_reg_t hp_uart2_ctrl;
+    volatile hp_peri1_pms_hp_uart3_ctrl_reg_t hp_uart3_ctrl;
+    volatile hp_peri1_pms_hp_parlio_ctrl_reg_t hp_parlio_ctrl;
+    volatile hp_peri1_pms_hp_gpspi2_ctrl_reg_t hp_gpspi2_ctrl;
+    volatile hp_peri1_pms_hp_gpspi3_ctrl_reg_t hp_gpspi3_ctrl;
+    volatile hp_peri1_pms_hp_usbdevice_ctrl_reg_t hp_usbdevice_ctrl;
+    volatile hp_peri1_pms_hp_ledc0_ctrl_reg_t hp_ledc0_ctrl;
+    volatile hp_peri1_pms_hp_etm_ctrl_reg_t hp_etm_ctrl;
+    volatile hp_peri1_pms_hp_twai0_ctrl_reg_t hp_twai0_ctrl;
+    volatile hp_peri1_pms_hp_twai1_ctrl_reg_t hp_twai1_ctrl;
+    volatile hp_peri1_pms_hp_lcdcam_ctrl_reg_t hp_lcdcam_ctrl;
+    volatile hp_peri1_pms_hp_uhci_ctrl_reg_t hp_uhci_ctrl;
+    volatile hp_peri1_pms_hp_systimer_ctrl_reg_t hp_systimer_ctrl;
+    volatile hp_peri1_pms_hp_zero_det_ctrl_reg_t hp_zero_det_ctrl;
+    volatile hp_peri1_pms_hp_cordic_ctrl_reg_t hp_cordic_ctrl;
+    volatile hp_peri1_pms_hp_ledc1_ctrl_reg_t hp_ledc1_ctrl;
+    volatile hp_peri1_pms_hp_pcnt1_ctrl_reg_t hp_pcnt1_ctrl;
+    volatile hp_peri1_pms_hp_timer_group0_ctrl_reg_t hp_timer_group0_ctrl;
+    volatile hp_peri1_pms_hp_timer_group1_ctrl_reg_t hp_timer_group1_ctrl;
+    volatile hp_peri1_pms_hp_iomux_ctrl_reg_t hp_iomux_ctrl;
+    volatile hp_peri1_pms_hp_mspi_padctrl_ctrl_reg_t hp_mspi_padctrl_ctrl;
+    volatile hp_peri1_pms_hp_intrmtx_ctrl_reg_t hp_intrmtx_ctrl;
+    volatile hp_peri1_pms_hp_sys_reg_ctrl_reg_t hp_sys_reg_ctrl;
+    volatile hp_peri1_pms_hp_clkrst_ctrl_reg_t hp_clkrst_ctrl;
+    volatile hp_peri1_pms_cnnt_pad_ctrl_ctrl_reg_t cnnt_pad_ctrl_ctrl;
+    volatile hp_peri1_pms_hp_alive_sys_reg_ctrl_reg_t hp_alive_sys_reg_ctrl;
+    volatile hp_peri1_pms_hp_peri1_pms_ctrl_reg_t hp_peri1_pms_ctrl;
+    uint32_t reserved_09c[89];
+    volatile hp_peri1_pms_hp_peri1_0_reg_t hp_peri1_0;
+    volatile hp_peri1_pms_hp_peri1_1_reg_t hp_peri1_1;
+    uint32_t reserved_208[62];
+    volatile hp_peri1_pms_int_en_reg_t int_en;
+    uint32_t reserved_304[827];
+    volatile hp_peri1_pms_bus_err_conf_reg_t bus_err_conf;
+    uint32_t reserved_ff4;
+    volatile hp_peri1_pms_clock_gate_reg_t clock_gate;
+    volatile hp_peri1_pms_date_reg_t date;
+} hp_peri1_pms_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_peri1_pms_dev_t) == 0x1000, "Invalid size of hp_peri1_pms_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h b/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h
new file mode 100644
index 00000000000..f81628d907a
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_sys_clkrst_reg.h
@@ -0,0 +1,4465 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYS_CLKRST_SOC_CLK_SEL_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_SOC_CLK_SEL_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x0)
+/** HP_SYS_CLKRST_REG_SOC_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  Configures to select the clock source of HP_ROOT_CLK.
+ *  0 (default): XTAL_CLK
+ *  1: PLL_F300M_CLK
+ *  2: RC_FAST_CLK
+ */
+#define HP_SYS_CLKRST_REG_SOC_CLK_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SOC_CLK_SEL_M  (HP_SYS_CLKRST_REG_SOC_CLK_SEL_V << HP_SYS_CLKRST_REG_SOC_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_SOC_CLK_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SOC_CLK_SEL_S  0
+
+/** HP_SYS_CLKRST_CPU_FREQ_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CPU_FREQ_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4)
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR : R/W; bitpos: [10:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR : R/W; bitpos: [13:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_CLK_DIV_DENOMINATOR_S  11
+
+/** HP_SYS_CLKRST_MEM_FREQ_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MEM_FREQ_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8)
+/** HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM    (BIT(0))
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MEM_CLK_DIV_NUM_S  0
+
+/** HP_SYS_CLKRST_SYS_FREQ_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_SYS_FREQ_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc)
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR : R/W; bitpos: [10:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR : R/W; bitpos: [13:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_SYS_CLK_DIV_DENOMINATOR_S  11
+
+/** HP_SYS_CLKRST_APB_FREQ_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_APB_FREQ_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x10)
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR : R/W; bitpos: [10:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR : R/W; bitpos: [13:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR    0x00000007U
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_APB_CLK_DIV_DENOMINATOR_S  11
+
+/** HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ROOT_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x14)
+/** HP_SYS_CLKRST_REG_SOC_CLK_UPDATE : R/W/WTC; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SOC_CLK_UPDATE    (BIT(0))
+#define HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_M  (HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_V << HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SOC_CLK_UPDATE_S  0
+
+/** HP_SYS_CLKRST_CPU_WFI_DELAY_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CPU_WFI_DELAY_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x18)
+/** HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM : R/W; bitpos: [3:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM    0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_M  (HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V << HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S)
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_CPUICM_DELAY_NUM_S  0
+
+/** HP_SYS_CLKRST_HPCORE0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HPCORE0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1c)
+/** HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CLIC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_CPU_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN_M  (HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN_V << HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_GLOBAL_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_CORE0_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE0_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_CORE0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_CORE0_FORCE_NORST_V << HP_SYS_CLKRST_REG_CORE0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_CORE0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE0_FORCE_NORST_S  3
+
+/** HP_SYS_CLKRST_HPCORE1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HPCORE1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x20)
+/** HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CLIC_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN_M  (HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN_V << HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_GLOBAL_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_CORE1_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORE1_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_CORE1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_CORE1_FORCE_NORST_V << HP_SYS_CLKRST_REG_CORE1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_CORE1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORE1_FORCE_NORST_S  3
+
+/** HP_SYS_CLKRST_TRACE_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TRACE_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x24)
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON    (BIT(2))
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON_S  2
+/** HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON    (BIT(3))
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON_S  3
+/** HP_SYS_CLKRST_REG_TRACE0_RST_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE0_RST_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_TRACE0_RST_EN_M  (HP_SYS_CLKRST_REG_TRACE0_RST_EN_V << HP_SYS_CLKRST_REG_TRACE0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE0_RST_EN_S  4
+/** HP_SYS_CLKRST_REG_TRACE1_RST_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE1_RST_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TRACE1_RST_EN_M  (HP_SYS_CLKRST_REG_TRACE1_RST_EN_V << HP_SYS_CLKRST_REG_TRACE1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TRACE1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE1_RST_EN_S  5
+/** HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST    (BIT(6))
+#define HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST_V << HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE0_FORCE_NORST_S  6
+/** HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST    (BIT(7))
+#define HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST_V << HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TRACE1_FORCE_NORST_S  7
+
+/** HP_SYS_CLKRST_TCM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TCM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x28)
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_TCM_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCM_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_TCM_RST_EN_M  (HP_SYS_CLKRST_REG_TCM_RST_EN_V << HP_SYS_CLKRST_REG_TCM_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TCM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCM_RST_EN_S  2
+
+/** HP_SYS_CLKRST_TCMMON_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TCMMON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x2c)
+/** HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_SYS_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_TCMMON_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_TCMMON_RST_EN_M  (HP_SYS_CLKRST_REG_TCMMON_RST_EN_V << HP_SYS_CLKRST_REG_TCMMON_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TCMMON_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST_V << HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TCMMON_FORCE_NORST_S  3
+
+/** HP_SYS_CLKRST_PSRAMMON_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PSRAMMON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x30)
+/** HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_MON_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN_M  (HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN_V << HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_MON_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST_V << HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_MON_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_ROM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ROM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x34)
+/** HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_MEM_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_ROM_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ROM_RST_EN_M  (HP_SYS_CLKRST_REG_ROM_RST_EN_V << HP_SYS_CLKRST_REG_ROM_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ROM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_RST_EN_S  2
+
+/** HP_SYS_CLKRST_CACHE_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CACHE_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x38)
+/** HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN_M  (HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN_V << HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_ACACHE_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON    (BIT(4))
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON_S  4
+/** HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN_M  (HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN_V << HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ROM_ACACHE_RST_EN_S  5
+/** HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON    (BIT(7))
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON_S  7
+/** HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN_M  (HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN_V << HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_CACHE_RST_EN_S  8
+/** HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_EN_S  9
+/** HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON : R/W; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON    (BIT(10))
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON_S  10
+/** HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN_M  (HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN_V << HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CACHE_RST_EN_S  11
+/** HP_SYS_CLKRST_REG_DCACHE_CLK_EN : R/W; bitpos: [12]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DCACHE_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_DCACHE_CLK_EN_M  (HP_SYS_CLKRST_REG_DCACHE_CLK_EN_V << HP_SYS_CLKRST_REG_DCACHE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DCACHE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DCACHE_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_DCACHE_RST_EN : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DCACHE_RST_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_DCACHE_RST_EN_M  (HP_SYS_CLKRST_REG_DCACHE_RST_EN_V << HP_SYS_CLKRST_REG_DCACHE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_DCACHE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DCACHE_RST_EN_S  13
+/** HP_SYS_CLKRST_REG_ICACHE0_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICACHE0_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_ICACHE0_CLK_EN_M  (HP_SYS_CLKRST_REG_ICACHE0_CLK_EN_V << HP_SYS_CLKRST_REG_ICACHE0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICACHE0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICACHE0_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_ICACHE0_RST_EN : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICACHE0_RST_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_ICACHE0_RST_EN_M  (HP_SYS_CLKRST_REG_ICACHE0_RST_EN_V << HP_SYS_CLKRST_REG_ICACHE0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ICACHE0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICACHE0_RST_EN_S  15
+/** HP_SYS_CLKRST_REG_ICACHE1_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICACHE1_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_ICACHE1_CLK_EN_M  (HP_SYS_CLKRST_REG_ICACHE1_CLK_EN_V << HP_SYS_CLKRST_REG_ICACHE1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICACHE1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICACHE1_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_ICACHE1_RST_EN : R/W; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICACHE1_RST_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_ICACHE1_RST_EN_M  (HP_SYS_CLKRST_REG_ICACHE1_RST_EN_V << HP_SYS_CLKRST_REG_ICACHE1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ICACHE1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICACHE1_RST_EN_S  17
+
+/** HP_SYS_CLKRST_ICM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ICM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x3c)
+/** HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_MEM_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_SYS_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_ICM_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ICM_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON    (BIT(4))
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON_S  4
+
+/** HP_SYS_CLKRST_MODEM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MODEM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x40)
+/** HP_SYS_CLKRST_REG_MODEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MODEM_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MODEM_CLK_EN_M  (HP_SYS_CLKRST_REG_MODEM_CLK_EN_V << HP_SYS_CLKRST_REG_MODEM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MODEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MODEM_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_MISC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MISC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x44)
+/** HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MISC_SYS_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSREG_APB_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_CLKRST_APB_CLK_EN_S  3
+
+/** HP_SYS_CLKRST_BUSMON_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_BUSMON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x48)
+/** HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN_V << HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN_V << HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST_V << HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE0_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN_V << HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON    (BIT(5))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_CLK_FORCE_ON_S  5
+/** HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN_M  (HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN_V << HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_RST_EN_S  6
+/** HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST    (BIT(7))
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST_V << HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BUSMON_CORE1_FORCE_NORST_S  7
+
+/** HP_SYS_CLKRST_REMOVE_TMP0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REMOVE_TMP0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x4c)
+/** HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_CPU_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_CPU_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_VPU_SYS_CLK_EN_S  2
+
+/** HP_SYS_CLKRST_PVT0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PVT0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x50)
+/** HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_TOP_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PVT0_APB_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_APB_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_PVT0_APB_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_APB_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_APB_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PVT0_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_PVT0_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_PVT0_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_CLK_EN_S  11
+
+/** HP_SYS_CLKRST_PVT0_PERI_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PVT0_PERI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x54)
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_RST_EN_S  0
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  TOP power domain pvt clk en
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP1_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  TOP power domain pvt clk en
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP2_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  modem power domain pvt clk en
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP3_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  modem power domain pvt clk en
+ */
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN_M  (HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN_V << HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PVT0_PERI_GROUP4_CLK_EN_S  7
+
+/** HP_SYS_CLKRST_CRYPTO_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CRYPTO_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x58)
+/** HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CRYPTO_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CRYPTO_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SEC_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_AES_RST_EN_S  5
+/** HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_SHA_RST_EN_S  7
+/** HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN    (BIT(9))
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RSA_RST_EN_S  9
+/** HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_CLK_EN_S  10
+/** HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_DS_RST_EN_S  11
+/** HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN : R/W; bitpos: [12]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN    (BIT(12))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_CLK_EN_S  12
+/** HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN : R/W; bitpos: [13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN    (BIT(13))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECC_RST_EN_S  13
+/** HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN    (BIT(14))
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_CLK_EN_S  14
+/** HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN : R/W; bitpos: [15]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN    (BIT(15))
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_HMAC_RST_EN_S  15
+/** HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN_S  16
+/** HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN : R/W; bitpos: [17]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN    (BIT(17))
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_ECDSA_RST_EN_S  17
+/** HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL : R/W; bitpos: [21:20]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL_S  20
+/** HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_RMA_RST_EN_S  23
+
+/** HP_SYS_CLKRST_KEY_MANAGER_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_KEY_MANAGER_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x5c)
+/** HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN_V << HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_M  (HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V << HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN_S  2
+
+/** HP_SYS_CLKRST_DPA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DPA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x60)
+/** HP_SYS_CLKRST_REG_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V << HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SEC_DPA_LEVEL_S  0
+/** HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL    (BIT(2))
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_M  (HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V << HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S)
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SEC_DPA_CFG_SEL_S  2
+
+/** HP_SYS_CLKRST_FLASH_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_FLASH_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x64)
+/** HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN_M  (HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN_V << HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_AXI_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_FLASH_APB_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_APB_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_FLASH_APB_RST_EN_M  (HP_SYS_CLKRST_REG_FLASH_APB_RST_EN_V << HP_SYS_CLKRST_REG_FLASH_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_APB_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST_M  (HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST_V << HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_AXI_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST_M  (HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST_V << HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_APB_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_FLASH_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_PLL_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM : R/W; bitpos: [16:9]; default: 3;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_FLASH_CORE_CLK_DIV_NUM_S  9
+
+/** HP_SYS_CLKRST_PSRAM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PSRAM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x68)
+/** HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN_M  (HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN_V << HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN_M  (HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN_V << HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_APB_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST_V << HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_AXI_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST_V << HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_APB_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PSRAM_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_PLL_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM : R/W; bitpos: [16:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PSRAM_CORE_CLK_DIV_NUM_S  9
+
+/** HP_SYS_CLKRST_GPSPI2_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_GPSPI2_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x6c)
+/** HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_GPSPI2_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_GPSPI2_RST_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_RST_EN_V << HP_SYS_CLKRST_REG_GPSPI2_RST_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST_M  (HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST_V << HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL : R/W; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_GPSPI2_CLK_SRC_SEL_S  4
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM : R/W; bitpos: [14:7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_HS_CLK_DIV_NUM_S  7
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM : R/W; bitpos: [22:15]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_DIV_NUM_S  15
+/** HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI2_MST_CLK_EN_S  23
+
+/** HP_SYS_CLKRST_GPSPI3_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_GPSPI3_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x70)
+/** HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_GPSPI3_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_GPSPI3_RST_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_RST_EN_V << HP_SYS_CLKRST_REG_GPSPI3_RST_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST_M  (HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST_V << HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL : R/W; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_GPSPI3_CLK_SRC_SEL_S  4
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM : R/W; bitpos: [14:7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_HS_CLK_DIV_NUM_S  7
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM : R/W; bitpos: [22:15]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_DIV_NUM_S  15
+/** HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_M  (HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V << HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GPSPI3_MST_CLK_EN_S  23
+
+/** HP_SYS_CLKRST_GDMA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_GDMA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x74)
+/** HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_GDMA_SYS_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_AXI_PDMA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_AXI_PDMA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x78)
+/** HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PDMA_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN_M  (HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN_V << HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PDMA_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST_M  (HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST_V << HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PDMA_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_AHB_PDMA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_AHB_PDMA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x7c)
+/** HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_PDMA_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN_M  (HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN_V << HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_PDMA_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST_M  (HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST_V << HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_PDMA_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_REGDMA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REGDMA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x80)
+/** HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REGDMA_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_REGDMA_RST_EN_M  (HP_SYS_CLKRST_REG_REGDMA_RST_EN_V << HP_SYS_CLKRST_REG_REGDMA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_REGDMA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REGDMA_RST_EN_S  1
+
+/** HP_SYS_CLKRST_UHCI_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_UHCI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x84)
+/** HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_UHCI_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UHCI_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_UHCI_RST_EN_M  (HP_SYS_CLKRST_REG_UHCI_RST_EN_V << HP_SYS_CLKRST_REG_UHCI_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UHCI_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_UHCI_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UHCI_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_UHCI_FORCE_NORST_M  (HP_SYS_CLKRST_REG_UHCI_FORCE_NORST_V << HP_SYS_CLKRST_REG_UHCI_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_UHCI_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UHCI_FORCE_NORST_S  3
+
+/** HP_SYS_CLKRST_UART0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_UART0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x88)
+/** HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_UART0_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_UART0_CORE_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_CORE_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_UART0_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_UART0_CORE_RST_EN_V << HP_SYS_CLKRST_REG_UART0_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_CORE_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_UART0_APB_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_APB_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_UART0_APB_RST_EN_M  (HP_SYS_CLKRST_REG_UART0_APB_RST_EN_V << HP_SYS_CLKRST_REG_UART0_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_APB_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_UART0_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_UART0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_UART0_FORCE_NORST_V << HP_SYS_CLKRST_REG_UART0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_UART0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART0_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_UART0_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_M  (HP_SYS_CLKRST_REG_UART0_CLK_EN_V << HP_SYS_CLKRST_REG_UART0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART0_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUMERATOR_S  16
+/** HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART0_SCLK_DIV_DENOMINATOR_S  24
+
+/** HP_SYS_CLKRST_UART1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_UART1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x8c)
+/** HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_UART1_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_UART1_CORE_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_CORE_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_UART1_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_UART1_CORE_RST_EN_V << HP_SYS_CLKRST_REG_UART1_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_CORE_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_UART1_APB_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_APB_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_UART1_APB_RST_EN_M  (HP_SYS_CLKRST_REG_UART1_APB_RST_EN_V << HP_SYS_CLKRST_REG_UART1_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_APB_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_UART1_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_UART1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_UART1_FORCE_NORST_V << HP_SYS_CLKRST_REG_UART1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_UART1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART1_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_UART1_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_M  (HP_SYS_CLKRST_REG_UART1_CLK_EN_V << HP_SYS_CLKRST_REG_UART1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART1_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_NUMERATOR_S  16
+/** HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART1_SCLK_DIV_DENOMINATOR_S  24
+
+/** HP_SYS_CLKRST_UART2_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_UART2_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x90)
+/** HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_UART2_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_UART2_CORE_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_CORE_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_UART2_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_UART2_CORE_RST_EN_V << HP_SYS_CLKRST_REG_UART2_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_CORE_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_UART2_APB_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_APB_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_UART2_APB_RST_EN_M  (HP_SYS_CLKRST_REG_UART2_APB_RST_EN_V << HP_SYS_CLKRST_REG_UART2_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_APB_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_UART2_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_UART2_FORCE_NORST_M  (HP_SYS_CLKRST_REG_UART2_FORCE_NORST_V << HP_SYS_CLKRST_REG_UART2_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_UART2_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART2_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_UART2_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_M  (HP_SYS_CLKRST_REG_UART2_CLK_EN_V << HP_SYS_CLKRST_REG_UART2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART2_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_NUMERATOR_S  16
+/** HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART2_SCLK_DIV_DENOMINATOR_S  24
+
+/** HP_SYS_CLKRST_UART3_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_UART3_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x94)
+/** HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_UART3_APB_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_UART3_CORE_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_CORE_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_UART3_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_UART3_CORE_RST_EN_V << HP_SYS_CLKRST_REG_UART3_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_CORE_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_UART3_APB_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_APB_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_UART3_APB_RST_EN_M  (HP_SYS_CLKRST_REG_UART3_APB_RST_EN_V << HP_SYS_CLKRST_REG_UART3_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_APB_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_UART3_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_UART3_FORCE_NORST_M  (HP_SYS_CLKRST_REG_UART3_FORCE_NORST_V << HP_SYS_CLKRST_REG_UART3_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_UART3_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_UART3_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_UART3_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_M  (HP_SYS_CLKRST_REG_UART3_CLK_EN_V << HP_SYS_CLKRST_REG_UART3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_UART3_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_NUMERATOR_S  16
+/** HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR : R/W; bitpos: [31:24]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_UART3_SCLK_DIV_DENOMINATOR_S  24
+
+/** HP_SYS_CLKRST_PARLIO_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PARLIO_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x98)
+/** HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_PARLIO_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_PARLIO_RST_EN_M  (HP_SYS_CLKRST_REG_PARLIO_RST_EN_V << HP_SYS_CLKRST_REG_PARLIO_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST_V << HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_FORCE_NORST_S  3
+
+/** HP_SYS_CLKRST_PARLIO_RX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PARLIO_RX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x9c)
+/** HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN_M  (HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN_V << HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_RST_EN_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST    (BIT(1))
+#define HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST_V << HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_FORCE_NORST_S  1
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_SRC_SEL_S  2
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_RX_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_PARLIO_TX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PARLIO_TX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa0)
+/** HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN_M  (HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN_V << HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_RST_EN_S  0
+/** HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST    (BIT(1))
+#define HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST_V << HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_FORCE_NORST_S  1
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL : R/W; bitpos: [3:2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_SRC_SEL_S  2
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_PARLIO_TX_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_BITSRAMBLER_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_BITSRAMBLER_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa4)
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_SYS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_RST_EN_S  4
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST    (BIT(5))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_RX_FORCE_NORST_S  5
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_SYS_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_RST_EN_S  7
+/** HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST    (BIT(8))
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_V << HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BITSRAMBLER_TX_FORCE_NORST_S  8
+
+/** HP_SYS_CLKRST_ETM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ETM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xa8)
+/** HP_SYS_CLKRST_REG_ETM_APB_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_APB_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_ETM_RST_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ETM_RST_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ETM_RST_EN_M  (HP_SYS_CLKRST_REG_ETM_RST_EN_V << HP_SYS_CLKRST_REG_ETM_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ETM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_RST_EN_S  2
+/** HP_SYS_CLKRST_REG_ETM_FORCE_NORST : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ETM_FORCE_NORST    (BIT(3))
+#define HP_SYS_CLKRST_REG_ETM_FORCE_NORST_M  (HP_SYS_CLKRST_REG_ETM_FORCE_NORST_V << HP_SYS_CLKRST_REG_ETM_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_ETM_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ETM_FORCE_NORST_S  3
+/** HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL : R/W; bitpos: [5:4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL_M  (HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL_V << HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_SEL_S  4
+/** HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN_M  (HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN_V << HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SOC_ETM_CLK_EN_S  6
+
+/** HP_SYS_CLKRST_USB_OTGHS_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_USB_OTGHS_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xac)
+/** HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTGHS_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_OTGHS_SYS_CLK_EN_S  1
+
+/** HP_SYS_CLKRST_DMA2D_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DMA2D_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb0)
+/** HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DMA2D_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_DMA2D_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DMA2D_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_DMA2D_RST_EN_M  (HP_SYS_CLKRST_REG_DMA2D_RST_EN_V << HP_SYS_CLKRST_REG_DMA2D_RST_EN_S)
+#define HP_SYS_CLKRST_REG_DMA2D_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DMA2D_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST_M  (HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST_V << HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DMA2D_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_PPA_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PPA_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb4)
+/** HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PPA_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PPA_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PPA_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PPA_RST_EN_M  (HP_SYS_CLKRST_REG_PPA_RST_EN_V << HP_SYS_CLKRST_REG_PPA_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PPA_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PPA_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PPA_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PPA_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_PPA_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PPA_FORCE_NORST_V << HP_SYS_CLKRST_REG_PPA_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PPA_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PPA_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_JPEG_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_JPEG_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xb8)
+/** HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_JPEG_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_JPEG_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_JPEG_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_JPEG_RST_EN_M  (HP_SYS_CLKRST_REG_JPEG_RST_EN_V << HP_SYS_CLKRST_REG_JPEG_RST_EN_S)
+#define HP_SYS_CLKRST_REG_JPEG_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_JPEG_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_JPEG_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_JPEG_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_JPEG_FORCE_NORST_M  (HP_SYS_CLKRST_REG_JPEG_FORCE_NORST_V << HP_SYS_CLKRST_REG_JPEG_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_JPEG_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_JPEG_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_RMT_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_RMT_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xbc)
+/** HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_RMT_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_RMT_RST_EN_M  (HP_SYS_CLKRST_REG_RMT_RST_EN_V << HP_SYS_CLKRST_REG_RMT_RST_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_RMT_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_RMT_FORCE_NORST_M  (HP_SYS_CLKRST_REG_RMT_FORCE_NORST_V << HP_SYS_CLKRST_REG_RMT_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_RMT_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_RMT_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_RMT_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_M  (HP_SYS_CLKRST_REG_RMT_CLK_EN_V << HP_SYS_CLKRST_REG_RMT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_RMT_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUM_S  6
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR : R/W; bitpos: [21:14]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_NUMERATOR_S  14
+/** HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR : R/W; bitpos: [29:22]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_RMT_CLK_DIV_DENOMINATOR_S  22
+
+/** HP_SYS_CLKRST_SDIO_HOST_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_SDIO_HOST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc0)
+/** HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDMMC_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_SDIO_HS_MODE : R/W; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE    (BIT(1))
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_M  (HP_SYS_CLKRST_REG_SDIO_HS_MODE_V << HP_SYS_CLKRST_REG_SDIO_HS_MODE_S)
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_HS_MODE_S  1
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL : R/W; bitpos: [2]; default: 0;
+ *  reserved
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL    (BIT(2))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_SRC_SEL_S  2
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM : R/W; bitpos: [11:4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_DIV_NUM_S  4
+
+/** HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_SDIO_HOST_FUNC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc4)
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE : WT; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE    (BIT(0))
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_CFG_UPDATE_S  0
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L : R/W; bitpos: [4:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_L_S  1
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H : R/W; bitpos: [8:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_H_S  5
+/** HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N : R/W; bitpos: [12:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N    0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_M  (HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V << HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_SDIO_LS_CLK_EDGE_N_S  9
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL : R/W; bitpos: [15:13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EDGE_SEL_S  13
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL : R/W; bitpos: [18:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EDGE_SEL_S  16
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL : R/W; bitpos: [21:19]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL    0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_V  0x00000007U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EDGE_SEL_S  19
+/** HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN : R/W; bitpos: [22]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN    (BIT(22))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SLF_CLK_EN_S  22
+/** HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN : R/W; bitpos: [23]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN    (BIT(23))
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_DRV_CLK_EN_S  23
+/** HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN : R/W; bitpos: [24]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN    (BIT(24))
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_M  (HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V << HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_LS_SAM_CLK_EN_S  24
+
+/** HP_SYS_CLKRST_EMAC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_EMAC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xc8)
+/** HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_EMAC_SYS_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_DSI_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DSI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xcc)
+/** HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DSI_SYS_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_DSI_PHY_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DSI_PHY_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd0)
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_CFG_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPHY_PLL_REFCLK_EN_S  3
+
+/** HP_SYS_CLKRST_DSI_DPI_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DSI_DPI_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd4)
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_EN_S  2
+/** HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MIPI_DSI_DPICLK_DIV_NUM_S  3
+
+/** HP_SYS_CLKRST_MSPI_PAD_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MSPI_PAD_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xd8)
+/** HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN_M  (HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN_V << HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST_M  (HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST_V << HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_PAD_CTRL_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_I2C0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2C0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xdc)
+/** HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2C0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2C0_RST_EN_M  (HP_SYS_CLKRST_REG_I2C0_RST_EN_V << HP_SYS_CLKRST_REG_I2C0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_I2C0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_I2C0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_I2C0_FORCE_NORST_V << HP_SYS_CLKRST_REG_I2C0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_I2C0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL    (BIT(3))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_I2C0_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C0_CLK_EN_V << HP_SYS_CLKRST_REG_I2C0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C0_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C0_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_I2C1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2C1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe0)
+/** HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2C1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2C1_RST_EN_M  (HP_SYS_CLKRST_REG_I2C1_RST_EN_V << HP_SYS_CLKRST_REG_I2C1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_I2C1_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_I2C1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_I2C1_FORCE_NORST_V << HP_SYS_CLKRST_REG_I2C1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_I2C1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL    (BIT(3))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_I2C1_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_M  (HP_SYS_CLKRST_REG_I2C1_CLK_EN_V << HP_SYS_CLKRST_REG_I2C1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2C1_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUM_S  5
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR : R/W; bitpos: [20:13]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_NUMERATOR_S  13
+/** HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR : R/W; bitpos: [28:21]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2C1_CLK_DIV_DENOMINATOR_S  21
+
+/** HP_SYS_CLKRST_I2S0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe4)
+/** HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S0_APB_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_APB_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2S0_APB_RST_EN_M  (HP_SYS_CLKRST_REG_I2S0_APB_RST_EN_V << HP_SYS_CLKRST_REG_I2S0_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_APB_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_I2S0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_I2S0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_I2S0_FORCE_NORST_V << HP_SYS_CLKRST_REG_I2S0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_I2S0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_I2S0_RX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S0_RX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xe8)
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_RX_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_N : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_N_S  3
+/** HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL    (BIT(11))
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_MST_CLK_SEL_S  11
+
+/** HP_SYS_CLKRST_I2S0_RX_DIV_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S0_RX_DIV_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xec)
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_RX_DIV_YN1_S  27
+
+/** HP_SYS_CLKRST_I2S0_TX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S0_TX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf0)
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S0_TX_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_N : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_N_S  3
+
+/** HP_SYS_CLKRST_I2S0_TX_DIV_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S0_TX_DIV_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf4)
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S0_TX_DIV_YN1_S  27
+
+/** HP_SYS_CLKRST_I2S1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xf8)
+/** HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S1_APB_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_APB_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_I2S1_APB_RST_EN_M  (HP_SYS_CLKRST_REG_I2S1_APB_RST_EN_V << HP_SYS_CLKRST_REG_I2S1_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_APB_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_I2S1_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_I2S1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_I2S1_FORCE_NORST_V << HP_SYS_CLKRST_REG_I2S1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_I2S1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_I2S1_RX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S1_RX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0xfc)
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_RX_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_N : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_N_S  3
+/** HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL    (BIT(11))
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_M  (HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V << HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_MST_CLK_SEL_S  11
+
+/** HP_SYS_CLKRST_I2S1_RX_DIV_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S1_RX_DIV_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x100)
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_RX_DIV_YN1_S  27
+
+/** HP_SYS_CLKRST_I2S1_TX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S1_TX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x104)
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_I2S1_TX_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_N : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N    0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_N_S  3
+
+/** HP_SYS_CLKRST_I2S1_TX_DIV_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_I2S1_TX_DIV_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x108)
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_X : R/W; bitpos: [8:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_X_S  0
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y : R/W; bitpos: [17:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Y_S  9
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z : R/W; bitpos: [26:18]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z    0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_V  0x000001FFU
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_Z_S  18
+/** HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1 : R/W; bitpos: [27]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1    (BIT(27))
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_M  (HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V << HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S)
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_V  0x00000001U
+#define HP_SYS_CLKRST_REG_I2S1_TX_DIV_YN1_S  27
+
+/** HP_SYS_CLKRST_TWAI0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TWAI0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x10c)
+/** HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_TWAI0_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_TWAI0_RST_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_RST_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_TWAI0_RST_EN_M  (HP_SYS_CLKRST_REG_TWAI0_RST_EN_V << HP_SYS_CLKRST_REG_TWAI0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_RST_EN_S  4
+/** HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST    (BIT(5))
+#define HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST_V << HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI0_FORCE_NORST_S  5
+
+/** HP_SYS_CLKRST_TWAI1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TWAI1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x110)
+/** HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL : R/W; bitpos: [2:1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_TWAI1_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_M  (HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V << HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_TWAI1_RST_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_RST_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_TWAI1_RST_EN_M  (HP_SYS_CLKRST_REG_TWAI1_RST_EN_V << HP_SYS_CLKRST_REG_TWAI1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TWAI1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_RST_EN_S  4
+/** HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST    (BIT(5))
+#define HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST_V << HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TWAI1_FORCE_NORST_S  5
+
+/** HP_SYS_CLKRST_TIMERGRP0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TIMERGRP0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x114)
+/** HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST_V << HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T0_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_SRC_SEL_S  6
+/** HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_T1_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL : R/W; bitpos: [10:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_SRC_SEL_S  9
+/** HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN : R/W; bitpos: [11]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_WDT_CLK_EN_S  11
+
+/** HP_SYS_CLKRST_TIMERGRP0_TGRT_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TIMERGRP0_TGRT_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x118)
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL : R/W; bitpos: [4:1]; default: 8;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL    0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_V  0x0000000FU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_SRC_SEL_S  1
+/** HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM : R/W; bitpos: [20:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM    0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_V  0x0000FFFFU
+#define HP_SYS_CLKRST_REG_TIMERGRP0_TGRT_CLK_DIV_NUM_S  5
+
+/** HP_SYS_CLKRST_TIMERGRP1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TIMERGRP1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x11c)
+/** HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST_V << HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T0_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL : R/W; bitpos: [7:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_SRC_SEL_S  6
+/** HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_T1_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL : R/W; bitpos: [10:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_SRC_SEL_S  9
+/** HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN : R/W; bitpos: [11]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_M  (HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V << HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TIMERGRP1_WDT_CLK_EN_S  11
+
+/** HP_SYS_CLKRST_SYSTIMER_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_SYSTIMER_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x120)
+/** HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_SYSTIMER_RST_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_RST_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_RST_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST_M  (HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST_V << HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL    (BIT(3))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_M  (HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V << HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN_S  4
+
+/** HP_SYS_CLKRST_MCPWM0_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MCPWM0_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x124)
+/** HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MCPWM0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MCPWM0_RST_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_RST_EN_V << HP_SYS_CLKRST_REG_MCPWM0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST_V << HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM0_CLK_DIV_NUM_S  6
+
+/** HP_SYS_CLKRST_MCPWM1_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MCPWM1_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x128)
+/** HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MCPWM1_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MCPWM1_RST_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_RST_EN_V << HP_SYS_CLKRST_REG_MCPWM1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST_V << HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM1_CLK_DIV_NUM_S  6
+
+/** HP_SYS_CLKRST_MCPWM2_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MCPWM2_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x12c)
+/** HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM2_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MCPWM2_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MCPWM2_RST_EN_M  (HP_SYS_CLKRST_REG_MCPWM2_RST_EN_V << HP_SYS_CLKRST_REG_MCPWM2_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM2_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST_M  (HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST_V << HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM2_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_MCPWM2_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM2_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM2_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM2_CLK_DIV_NUM_S  6
+
+/** HP_SYS_CLKRST_MCPWM3_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_MCPWM3_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x130)
+/** HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM3_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_MCPWM3_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_MCPWM3_RST_EN_M  (HP_SYS_CLKRST_REG_MCPWM3_RST_EN_V << HP_SYS_CLKRST_REG_MCPWM3_RST_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM3_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST_M  (HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST_V << HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM3_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_MCPWM3_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_EN_M  (HP_SYS_CLKRST_REG_MCPWM3_CLK_EN_V << HP_SYS_CLKRST_REG_MCPWM3_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM : R/W; bitpos: [13:6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_MCPWM3_CLK_DIV_NUM_S  6
+
+/** HP_SYS_CLKRST_INTRMTX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_INTRMTX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x134)
+/** HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_INTRMTX_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_INTRMTX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_INTRMTX_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_INTRMTX_RST_EN_M  (HP_SYS_CLKRST_REG_INTRMTX_RST_EN_V << HP_SYS_CLKRST_REG_INTRMTX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_INTRMTX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_INTRMTX_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST_V << HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_INTRMTX_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_PCNT_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_PCNT_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x138)
+/** HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_PCNT0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT0_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_PCNT0_RST_EN_M  (HP_SYS_CLKRST_REG_PCNT0_RST_EN_V << HP_SYS_CLKRST_REG_PCNT0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT0_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST_V << HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT0_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT1_APB_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_PCNT1_RST_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT1_RST_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_PCNT1_RST_EN_M  (HP_SYS_CLKRST_REG_PCNT1_RST_EN_V << HP_SYS_CLKRST_REG_PCNT1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_PCNT1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT1_RST_EN_S  4
+/** HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST    (BIT(5))
+#define HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST_V << HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PCNT1_FORCE_NORST_S  5
+
+/** HP_SYS_CLKRST_USB_DEVICE_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_USB_DEVICE_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x144)
+/** HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V << HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_USB_DEVICE_APB_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_LEDC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LEDC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x148)
+/** HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC0_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_LEDC0_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC0_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_LEDC0_RST_EN_M  (HP_SYS_CLKRST_REG_LEDC0_RST_EN_V << HP_SYS_CLKRST_REG_LEDC0_RST_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC0_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC0_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST_M  (HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST_V << HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC0_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL : R/W; bitpos: [4:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_LEDC0_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC0_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC0_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC0_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC1_APB_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_LEDC1_RST_EN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC1_RST_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_LEDC1_RST_EN_M  (HP_SYS_CLKRST_REG_LEDC1_RST_EN_V << HP_SYS_CLKRST_REG_LEDC1_RST_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC1_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC1_RST_EN_S  7
+/** HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST    (BIT(8))
+#define HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST_M  (HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST_V << HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC1_FORCE_NORST_S  8
+/** HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL : R/W; bitpos: [10:9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_SRC_SEL_S  9
+/** HP_SYS_CLKRST_REG_LEDC1_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_EN    (BIT(11))
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_EN_M  (HP_SYS_CLKRST_REG_LEDC1_CLK_EN_V << HP_SYS_CLKRST_REG_LEDC1_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LEDC1_CLK_EN_S  11
+
+/** HP_SYS_CLKRST_LCDCAM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LCDCAM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x14c)
+/** HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V << HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN_V << HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_APB_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_SYS_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_LCDCAM_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_LCDCAM_RST_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_RST_EN_V << HP_SYS_CLKRST_REG_LCDCAM_RST_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST_M  (HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST_V << HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_FORCE_NORST_S  4
+
+/** HP_SYS_CLKRST_LCDCAM_LCD_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LCDCAM_LCD_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x150)
+/** HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LCD_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_LCD_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_M  (HP_SYS_CLKRST_REG_LCD_CLK_EN_V << HP_SYS_CLKRST_REG_LCD_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCD_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR : R/W; bitpos: [18:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_NUMERATOR_S  11
+/** HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR : R/W; bitpos: [26:19]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCD_CLK_DIV_DENOMINATOR_S  19
+
+/** HP_SYS_CLKRST_LCDCAM_LCDCAM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LCDCAM_LCDCAM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x154)
+/** HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_LCDCAM_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_EN_M  (HP_SYS_CLKRST_REG_LCDCAM_CLK_EN_V << HP_SYS_CLKRST_REG_LCDCAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR : R/W; bitpos: [18:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_NUMERATOR_S  11
+/** HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR : R/W; bitpos: [26:19]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_LCDCAM_CLK_DIV_DENOMINATOR_S  19
+
+/** HP_SYS_CLKRST_LCDCAM_CAM_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LCDCAM_CAM_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x158)
+/** HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL : R/W; bitpos: [1:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CAM_CLK_SRC_SEL_S  0
+/** HP_SYS_CLKRST_REG_CAM_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_M  (HP_SYS_CLKRST_REG_CAM_CLK_EN_V << HP_SYS_CLKRST_REG_CAM_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CAM_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUM_S  3
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR : R/W; bitpos: [18:11]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_NUMERATOR_S  11
+/** HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR : R/W; bitpos: [26:19]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_M  (HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V << HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S)
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CAM_CLK_DIV_DENOMINATOR_S  19
+
+/** HP_SYS_CLKRST_IOMUX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_IOMUX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x15c)
+/** HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_IOMUX_RST_EN_M  (HP_SYS_CLKRST_REG_IOMUX_RST_EN_V << HP_SYS_CLKRST_REG_IOMUX_RST_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST_M  (HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST_V << HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_FORCE_NORST_S  2
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL    (BIT(3))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_SRC_SEL_S  3
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_EN : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V << HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM : R/W; bitpos: [12:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_IOMUX_CLK_DIV_NUM_S  5
+
+/** HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE0_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x160)
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE0_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE0_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HPWDT_CORE1_RST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x164)
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_EN_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM : R/W; bitpos: [8:1]; default: 8;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_M  (HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V << HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_HPCORE1_STALL_WAIT_NUM_S  1
+/** HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN : R/W; bitpos: [16:9]; default: 8;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN    0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_M  (HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V << HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S)
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_WDT_HPCORE1_RST_LEN_S  9
+
+/** HP_SYS_CLKRST_CPU_SRC_FREQ0_REG register
+ *  CPU Source Frequency
+ */
+#define HP_SYS_CLKRST_CPU_SRC_FREQ0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x168)
+/** HP_SYS_CLKRST_REG_CPU_SRC_FREQ : RO; bitpos: [31:0]; default: 0;
+ *  cpu source clock frequency, step by 0.25MHz
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ    0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_M  (HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V << HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_V  0xFFFFFFFFU
+#define HP_SYS_CLKRST_REG_CPU_SRC_FREQ_S  0
+
+/** HP_SYS_CLKRST_CPU_CLK_STATUS0_REG register
+ *  CPU Clock Status
+ */
+#define HP_SYS_CLKRST_CPU_CLK_STATUS0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x16c)
+/** HP_SYS_CLKRST_REG_ASIC_OR_FPGA : RO; bitpos: [0]; default: 0;
+ *  0: ASIC mode, 1: FPGA mode
+ */
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA    (BIT(0))
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_M  (HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V << HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S)
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ASIC_OR_FPGA_S  0
+/** HP_SYS_CLKRST_REG_CPU_DIV_EFFECT : RO; bitpos: [1]; default: 0;
+ *  0: Divider bypass, 1: Divider takes effect
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT    (BIT(1))
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_M  (HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V << HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_DIV_EFFECT_S  1
+/** HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL : RO; bitpos: [2]; default: 0;
+ *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+ */
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_M  (HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V << HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S)
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_SRC_IS_CPLL_S  2
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR : RO; bitpos: [10:3]; default: 0;
+ *  cpu current div number
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUM_CUR_S  3
+/** HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR : RO; bitpos: [13:11]; default: 0;
+ *  cpu current div numerator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR    0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_DIV_NUMERATOR_CUR_S  11
+/** HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR : RO; bitpos: [16:14]; default: 0;
+ *  cpu current div denominator
+ */
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR    0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_M  (HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V << HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S)
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_V  0x00000007U
+#define HP_SYS_CLKRST_REG_CPU_DIV_DENOMINATOR_CUR_S  14
+
+/** HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HPCORE_WDT_RESET_SOURCE0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x170)
+/** HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL : R/W; bitpos: [0]; default: 0;
+ *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+ */
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE0_WDT_RESET_SOURCE_SEL_S  0
+/** HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL : R/W; bitpos: [1]; default: 1;
+ *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+ */
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL    (BIT(1))
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_M  (HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V << HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HPCORE1_WDT_RESET_SOURCE_SEL_S  1
+
+/** HP_SYS_CLKRST_ANA_PLL_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ANA_PLL_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x174)
+/** HP_SYS_CLKRST_REG_PLLA_CAL_END : RO; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END    (BIT(0))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_M  (HP_SYS_CLKRST_REG_PLLA_CAL_END_V << HP_SYS_CLKRST_REG_PLLA_CAL_END_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_END_S  0
+/** HP_SYS_CLKRST_REG_PLLA_CAL_STOP : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP    (BIT(1))
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_M  (HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V << HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLLA_CAL_STOP_S  1
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_END : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END    (BIT(2))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_END_S  2
+/** HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP    (BIT(3))
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP_S  3
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END : RO; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END    (BIT(4))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_END_S  4
+/** HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP    (BIT(5))
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V << HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_SDIO_PLL_CAL_STOP_S  5
+/** HP_SYS_CLKRST_REG_BBPLL_CAL_END : RO; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_END    (BIT(6))
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_END_M  (HP_SYS_CLKRST_REG_BBPLL_CAL_END_V << HP_SYS_CLKRST_REG_BBPLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_END_S  6
+/** HP_SYS_CLKRST_REG_BBPLL_CAL_STOP : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_STOP    (BIT(7))
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_M  (HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_V << HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_BBPLL_CAL_STOP_S  7
+/** HP_SYS_CLKRST_REG_MSPI_CAL_END : RO; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END    (BIT(8))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_M  (HP_SYS_CLKRST_REG_MSPI_CAL_END_V << HP_SYS_CLKRST_REG_MSPI_CAL_END_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_END_S  8
+/** HP_SYS_CLKRST_REG_MSPI_CAL_STOP : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP    (BIT(9))
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_M  (HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V << HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S)
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_V  0x00000001U
+#define HP_SYS_CLKRST_REG_MSPI_CAL_STOP_S  9
+/** HP_SYS_CLKRST_REG_PLL_CAL_END : RO; bitpos: [10]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_PLL_CAL_END    (BIT(10))
+#define HP_SYS_CLKRST_REG_PLL_CAL_END_M  (HP_SYS_CLKRST_REG_PLL_CAL_END_V << HP_SYS_CLKRST_REG_PLL_CAL_END_S)
+#define HP_SYS_CLKRST_REG_PLL_CAL_END_V  0x00000001U
+#define HP_SYS_CLKRST_REG_PLL_CAL_END_S  10
+
+/** HP_SYS_CLKRST_REF_500M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_500M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x178)
+/** HP_SYS_CLKRST_REG_REF_500M_SEL : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_500M_SEL    (BIT(0))
+#define HP_SYS_CLKRST_REG_REF_500M_SEL_M  (HP_SYS_CLKRST_REG_REF_500M_SEL_V << HP_SYS_CLKRST_REG_REF_500M_SEL_S)
+#define HP_SYS_CLKRST_REG_REF_500M_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_500M_SEL_S  0
+
+/** HP_SYS_CLKRST_REF_240M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_240M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x17c)
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_240M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_240M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_160M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_160M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x180)
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 2;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_160M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_160M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_120M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_120M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x184)
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 3;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_120M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_120M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_80M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_80M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x188)
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 5;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_80M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_80M_CLK_EN_S  8
+/** HP_SYS_CLKRST_REG_REF_80M_SEL : R/W; bitpos: [9]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_SEL    (BIT(9))
+#define HP_SYS_CLKRST_REG_REF_80M_SEL_M  (HP_SYS_CLKRST_REG_REF_80M_SEL_V << HP_SYS_CLKRST_REG_REF_80M_SEL_S)
+#define HP_SYS_CLKRST_REG_REF_80M_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_80M_SEL_S  9
+/** HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN    (BIT(10))
+#define HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN_V << HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_80M_MUX_CLK_EN_S  10
+
+/** HP_SYS_CLKRST_REF_60M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_60M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x18c)
+/** HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_60M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_60M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_60M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_60M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_20M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_20M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x190)
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 23;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_20M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_20M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_50M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_50M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x194)
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 5;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_50M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_50M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_REF_25M_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REF_25M_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x198)
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 11;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_REF_25M_CLK_EN : R/W; bitpos: [8]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_M  (HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V << HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_REF_25M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_TM_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_TM_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x19c)
+/** HP_SYS_CLKRST_REG_TM_480M_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_480M_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_TM_240M_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_240M_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_TM_160M_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_160M_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_TM_120M_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_120M_CLK_EN_S  3
+/** HP_SYS_CLKRST_REG_TM_80M_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_80M_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_TM_60M_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_60M_CLK_EN_S  5
+/** HP_SYS_CLKRST_REG_TM_48M_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN    (BIT(6))
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_48M_CLK_EN_S  6
+/** HP_SYS_CLKRST_REG_TM_20M_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN    (BIT(7))
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_20M_CLK_EN_S  7
+/** HP_SYS_CLKRST_REG_TM_250M_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_TM_250M_CLK_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_TM_250M_CLK_EN_M  (HP_SYS_CLKRST_REG_TM_250M_CLK_EN_V << HP_SYS_CLKRST_REG_TM_250M_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_TM_250M_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_TM_250M_CLK_EN_S  8
+
+/** HP_SYS_CLKRST_DBG0_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DBG0_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1a0)
+/** HP_SYS_CLKRST_REG_DBG_CH0_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH0_SEL_V << HP_SYS_CLKRST_REG_DBG_CH0_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_SEL_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH0_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH0_EN : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_M  (HP_SYS_CLKRST_REG_DBG_CH0_EN_V << HP_SYS_CLKRST_REG_DBG_CH0_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH0_EN_S  16
+
+/** HP_SYS_CLKRST_DBG1_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DBG1_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1a4)
+/** HP_SYS_CLKRST_REG_DBG_CH1_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH1_SEL_V << HP_SYS_CLKRST_REG_DBG_CH1_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_SEL_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH1_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH1_EN : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_M  (HP_SYS_CLKRST_REG_DBG_CH1_EN_V << HP_SYS_CLKRST_REG_DBG_CH1_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH1_EN_S  16
+
+/** HP_SYS_CLKRST_DBG2_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DBG2_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1a8)
+/** HP_SYS_CLKRST_REG_DBG_CH2_SEL : R/W; bitpos: [7:0]; default: 255;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_M  (HP_SYS_CLKRST_REG_DBG_CH2_SEL_V << HP_SYS_CLKRST_REG_DBG_CH2_SEL_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_SEL_S  0
+/** HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM : R/W; bitpos: [15:8]; default: 3;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_M  (HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V << HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_DBG_CH2_DIV_NUM_S  8
+/** HP_SYS_CLKRST_REG_DBG_CH2_EN : R/W; bitpos: [16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN    (BIT(16))
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_M  (HP_SYS_CLKRST_REG_DBG_CH2_EN_V << HP_SYS_CLKRST_REG_DBG_CH2_EN_S)
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_DBG_CH2_EN_S  16
+
+/** HP_SYS_CLKRST_LP_CLK_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_LP_CLK_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1ac)
+/** HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON    (BIT(0))
+#define HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LPAON_FOSC_CLK_FORCE_ON_S  0
+/** HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON    (BIT(1))
+#define HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LPAON_XTAL_CLK_FORCE_ON_S  1
+/** HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON    (BIT(2))
+#define HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON_M  (HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON_V << HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON_S)
+#define HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYS_CLKRST_REG_LPAON_PLL80M_CLK_FORCE_ON_S  2
+
+/** HP_SYS_CLKRST_AHB_ASRC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_AHB_ASRC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1b0)
+/** HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_ASRC_SYS_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN_M  (HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN_V << HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_ASRC_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST_M  (HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST_V << HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AHB_ASRC_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_CORDIC_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CORDIC_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1b4)
+/** HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN_V << HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN_M  (HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN_V << HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_APB_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN_M  (HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN_V << HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_SYS_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_CORDIC_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_EN_M  (HP_SYS_CLKRST_REG_CORDIC_CLK_EN_V << HP_SYS_CLKRST_REG_CORDIC_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_EN_S  4
+/** HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN : R/W; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN    (BIT(5))
+#define HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN_V << HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_CORE_RST_EN_S  5
+/** HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST : R/W; bitpos: [6]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST    (BIT(6))
+#define HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST_M  (HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST_V << HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CORDIC_FORCE_NORST_S  6
+/** HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL : R/W; bitpos: [8:7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_SRC_SEL_S  7
+
+/** HP_SYS_CLKRST_ZERO_DET_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_ZERO_DET_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1b8)
+/** HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN_V << HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN_M  (HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN_V << HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ZERO_DET_APB_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN_M  (HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN_V << HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_EN_S  2
+/** HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN    (BIT(3))
+#define HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN_M  (HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN_V << HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ZERO_DET_CORE_RST_EN_S  3
+/** HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST : R/W; bitpos: [4]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST    (BIT(4))
+#define HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST_M  (HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST_V << HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_ZERO_DET_FORCE_NORST_S  4
+/** HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL : R/W; bitpos: [6:5]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL    0x00000003U
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL_M  (HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL_V << HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL_V  0x00000003U
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_SRC_SEL_S  5
+/** HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM : R/W; bitpos: [14:7]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_ZERO_DET_CLK_DIV_NUM_S  7
+
+/** HP_SYS_CLKRST_CORDIC_CTRL1_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CORDIC_CTRL1_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1bc)
+/** HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM_M  (HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM_V << HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR_M  (HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR_V << HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_NUMERATOR_S  8
+/** HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR    0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR_M  (HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR_V << HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR_S)
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_CORDIC_CLK_DIV_DENONIMATOR_S  16
+
+/** HP_SYS_CLKRST_CLK_PWR_DECREASE_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CLK_PWR_DECREASE_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1c8)
+/** HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM    0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM_M  (HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM_V << HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM_S)
+#define HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM_V  0x000000FFU
+#define HP_SYS_CLKRST_REG_APB_HW_DECREASE_DIV_NUM_S  0
+/** HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN : R/W; bitpos: [8]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN    (BIT(8))
+#define HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN_M  (HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN_V << HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN_S)
+#define HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CPU_WFI_DECREASE_EN_S  8
+
+/** HP_SYS_CLKRST_CNNT_IOMUX_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CNNT_IOMUX_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1cc)
+/** HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  cnnt_iomux clk en
+ */
+#define HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN_V << HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CNNT_IOMUX_APB_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_HP_I2CMST_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HP_I2CMST_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1d0)
+/** HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN_V << HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_I2CMST_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN_M  (HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN_V << HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN_S)
+#define HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_I2CMST_RST_EN_S  1
+/** HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST_M  (HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST_V << HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_I2CMST_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_AXI_PERF_MON_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_AXI_PERF_MON_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1d4)
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN : R/W; bitpos: [0]; default: 0;
+ *  axi_perf_mon rst en
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_RST_EN_S  0
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  axi_perf_mon clk en
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN    (BIT(1))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_CLK_EN_S  1
+/** HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST : R/W; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST    (BIT(2))
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST_M  (HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST_V << HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST_S)
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST_V  0x00000001U
+#define HP_SYS_CLKRST_REG_AXI_PERF_MON_FORCE_NORST_S  2
+
+/** HP_SYS_CLKRST_CNNT_SYSREG_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CNNT_SYSREG_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1d8)
+/** HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  cnnt_sysreg clk en
+ */
+#define HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN_M  (HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN_V << HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CNNT_SYSREG_SYS_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_HP_ALIVE_SYSREG_CTRL0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_HP_ALIVE_SYSREG_CTRL0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1dc)
+/** HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  hp alive_sysreg clk en
+ */
+#define HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN_M  (HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN_V << HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_HP_ALIVE_SYSREG_APB_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_MODEM_CONF_REG register
+ *  MODEM_APB configuration register
+ */
+#define HP_SYS_CLKRST_MODEM_CONF_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1e0)
+/** HP_SYS_CLKRST_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
+ */
+#define HP_SYS_CLKRST_MODEM_APB_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_MODEM_APB_CLK_EN_M  (HP_SYS_CLKRST_MODEM_APB_CLK_EN_V << HP_SYS_CLKRST_MODEM_APB_CLK_EN_S)
+#define HP_SYS_CLKRST_MODEM_APB_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_APB_CLK_EN_S  0
+/** HP_SYS_CLKRST_MODEM_RST_EN : R/W; bitpos: [1]; default: 0;
+ *  Set this file as 1 to reset modem-subsystem.
+ */
+#define HP_SYS_CLKRST_MODEM_RST_EN    (BIT(1))
+#define HP_SYS_CLKRST_MODEM_RST_EN_M  (HP_SYS_CLKRST_MODEM_RST_EN_V << HP_SYS_CLKRST_MODEM_RST_EN_S)
+#define HP_SYS_CLKRST_MODEM_RST_EN_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_RST_EN_S  1
+/** HP_SYS_CLKRST_MODEM_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  This field indicates if modem source clock is enable. 0: disable, 1:
+ *  enable(default).
+ */
+#define HP_SYS_CLKRST_MODEM_CLK_EN    (BIT(2))
+#define HP_SYS_CLKRST_MODEM_CLK_EN_M  (HP_SYS_CLKRST_MODEM_CLK_EN_V << HP_SYS_CLKRST_MODEM_CLK_EN_S)
+#define HP_SYS_CLKRST_MODEM_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_CLK_EN_S  2
+/** HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL : R/W; bitpos: [3]; default: 0;
+ *  modem clk source sel
+ */
+#define HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL    (BIT(3))
+#define HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL_M  (HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL_V << HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL_S)
+#define HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_CLK_SOURCE_SEL_S  3
+/** HP_SYS_CLKRST_MODEM_PLL_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  modem clk source pll on
+ */
+#define HP_SYS_CLKRST_MODEM_PLL_CLK_EN    (BIT(4))
+#define HP_SYS_CLKRST_MODEM_PLL_CLK_EN_M  (HP_SYS_CLKRST_MODEM_PLL_CLK_EN_V << HP_SYS_CLKRST_MODEM_PLL_CLK_EN_S)
+#define HP_SYS_CLKRST_MODEM_PLL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_PLL_CLK_EN_S  4
+/** HP_SYS_CLKRST_MODEM_XTAL_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  modem clk source xtal on
+ */
+#define HP_SYS_CLKRST_MODEM_XTAL_CLK_EN    (BIT(5))
+#define HP_SYS_CLKRST_MODEM_XTAL_CLK_EN_M  (HP_SYS_CLKRST_MODEM_XTAL_CLK_EN_V << HP_SYS_CLKRST_MODEM_XTAL_CLK_EN_S)
+#define HP_SYS_CLKRST_MODEM_XTAL_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_MODEM_XTAL_CLK_EN_S  5
+
+/** HP_SYS_CLKRST_CLK_EN0_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_CLK_EN0_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1f8)
+/** HP_SYS_CLKRST_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  need_des
+ */
+#define HP_SYS_CLKRST_REG_CLK_EN    (BIT(0))
+#define HP_SYS_CLKRST_REG_CLK_EN_M  (HP_SYS_CLKRST_REG_CLK_EN_V << HP_SYS_CLKRST_REG_CLK_EN_S)
+#define HP_SYS_CLKRST_REG_CLK_EN_V  0x00000001U
+#define HP_SYS_CLKRST_REG_CLK_EN_S  0
+
+/** HP_SYS_CLKRST_DATE_REG register
+ *  need_des
+ */
+#define HP_SYS_CLKRST_DATE_REG (DR_REG_HP_SYS_CLKRST_BASE + 0x1fc)
+/** HP_SYS_CLKRST_REG_DATE : R/W; bitpos: [27:0]; default: 38834448;
+ *  Version control register
+ */
+#define HP_SYS_CLKRST_REG_DATE    0x0FFFFFFFU
+#define HP_SYS_CLKRST_REG_DATE_M  (HP_SYS_CLKRST_REG_DATE_V << HP_SYS_CLKRST_REG_DATE_S)
+#define HP_SYS_CLKRST_REG_DATE_V  0x0FFFFFFFU
+#define HP_SYS_CLKRST_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_sys_clkrst_struct.h b/components/soc/esp32s31/register/soc/hp_sys_clkrst_struct.h
new file mode 100644
index 00000000000..a15525e23bc
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_sys_clkrst_struct.h
@@ -0,0 +1,3773 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: root_clk_sel */
+/** Type of soc_clk_sel register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_soc_clk_sel : R/W; bitpos: [1:0]; default: 0;
+         *  Configures to select the clock source of HP_ROOT_CLK.
+         *  0 (default): XTAL_CLK
+         *  1: PLL_F300M_CLK
+         *  2: RC_FAST_CLK
+         */
+        uint32_t reg_soc_clk_sel:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_soc_clk_sel_reg_t;
+
+
+/** Group: cpu_freq_ctrl */
+/** Type of cpu_freq_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cpu_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_clk_div_num:8;
+        /** reg_cpu_clk_div_numerator : R/W; bitpos: [10:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_clk_div_numerator:3;
+        /** reg_cpu_clk_div_denominator : R/W; bitpos: [13:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_clk_div_denominator:3;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_freq_ctrl0_reg_t;
+
+
+/** Group: mem_freq_ctrl */
+/** Type of mem_freq_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mem_clk_div_num : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_mem_clk_div_num:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mem_freq_ctrl0_reg_t;
+
+
+/** Group: sys_freq_ctrl */
+/** Type of sys_freq_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_sys_clk_div_num : R/W; bitpos: [7:0]; default: 2;
+         *  need_des
+         */
+        uint32_t reg_sys_clk_div_num:8;
+        /** reg_sys_clk_div_numerator : R/W; bitpos: [10:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sys_clk_div_numerator:3;
+        /** reg_sys_clk_div_denominator : R/W; bitpos: [13:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sys_clk_div_denominator:3;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_sys_freq_ctrl0_reg_t;
+
+
+/** Group: apb_freq_ctrl */
+/** Type of apb_freq_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_apb_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_apb_clk_div_num:8;
+        /** reg_apb_clk_div_numerator : R/W; bitpos: [10:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_apb_clk_div_numerator:3;
+        /** reg_apb_clk_div_denominator : R/W; bitpos: [13:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_apb_clk_div_denominator:3;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_apb_freq_ctrl0_reg_t;
+
+
+/** Group: root_clk_ctrl */
+/** Type of root_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_soc_clk_update : R/W/WTC; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_soc_clk_update:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_root_clk_ctrl0_reg_t;
+
+
+/** Group: cpu_wfi_delay_ctrl */
+/** Type of cpu_wfi_delay_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cpuicm_delay_num : R/W; bitpos: [3:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpuicm_delay_num:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_wfi_delay_ctrl0_reg_t;
+
+
+/** Group: hpcore0_ctrl */
+/** Type of hpcore0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_core0_clic_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_core0_clic_clk_en:1;
+        /** reg_core0_cpu_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_core0_cpu_clk_en:1;
+        /** reg_core0_global_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_core0_global_rst_en:1;
+        /** reg_core0_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_core0_force_norst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpcore0_ctrl0_reg_t;
+
+
+/** Group: hpcore1_ctrl */
+/** Type of hpcore1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_core1_clic_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_core1_clic_clk_en:1;
+        /** reg_core1_cpu_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_core1_cpu_clk_en:1;
+        /** reg_core1_global_rst_en : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_core1_global_rst_en:1;
+        /** reg_core1_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_core1_force_norst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpcore1_ctrl0_reg_t;
+
+
+/** Group: trace_ctrl */
+/** Type of trace_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_trace_cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_trace_cpu_clk_en:1;
+        /** reg_trace_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_trace_sys_clk_en:1;
+        /** reg_trace_cpu_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace_cpu_clk_force_on:1;
+        /** reg_trace_sys_clk_force_on : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace_sys_clk_force_on:1;
+        /** reg_trace0_rst_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace0_rst_en:1;
+        /** reg_trace1_rst_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace1_rst_en:1;
+        /** reg_trace0_force_norst : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace0_force_norst:1;
+        /** reg_trace1_force_norst : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_trace1_force_norst:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_clkrst_trace_ctrl0_reg_t;
+
+
+/** Group: tcm_ctrl */
+/** Type of tcm_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_tcm_cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_tcm_cpu_clk_en:1;
+        /** reg_tcm_cpu_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_tcm_cpu_clk_force_on:1;
+        /** reg_tcm_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tcm_rst_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_tcm_ctrl0_reg_t;
+
+
+/** Group: tcmmon_ctrl */
+/** Type of tcmmon_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_tcmmon_cpu_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tcmmon_cpu_clk_en:1;
+        /** reg_tcmmon_sys_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tcmmon_sys_clk_en:1;
+        /** reg_tcmmon_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tcmmon_rst_en:1;
+        /** reg_tcmmon_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tcmmon_force_norst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_tcmmon_ctrl0_reg_t;
+
+
+/** Group: psrammon_ctrl */
+/** Type of psrammon_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_psram_mon_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_mon_sys_clk_en:1;
+        /** reg_psram_mon_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_mon_rst_en:1;
+        /** reg_psram_mon_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_mon_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_psrammon_ctrl0_reg_t;
+
+
+/** Group: rom_ctrl */
+/** Type of rom_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_rom_mem_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_rom_mem_clk_en:1;
+        /** reg_rom_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rom_mem_clk_force_on:1;
+        /** reg_rom_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rom_rst_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_rom_ctrl0_reg_t;
+
+
+/** Group: cache_ctrl */
+/** Type of cache_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cpu_acache_cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_cpu_acache_cpu_clk_en:1;
+        /** reg_cpu_acache_cpu_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_acache_cpu_clk_force_on:1;
+        /** reg_cpu_acache_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_acache_rst_en:1;
+        /** reg_rom_acache_mem_clk_en : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_rom_acache_mem_clk_en:1;
+        /** reg_rom_acache_mem_clk_force_on : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rom_acache_mem_clk_force_on:1;
+        /** reg_rom_acache_rst_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rom_acache_rst_en:1;
+        /** reg_cpu_cache_cpu_clk_en : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_cpu_cache_cpu_clk_en:1;
+        /** reg_cpu_cache_cpu_clk_force_on : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_cache_cpu_clk_force_on:1;
+        /** reg_cpu_cache_rst_en : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_cache_rst_en:1;
+        /** reg_mspi_cache_sys_clk_en : R/W; bitpos: [9]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_mspi_cache_sys_clk_en:1;
+        /** reg_mspi_cache_sys_clk_force_on : R/W; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_cache_sys_clk_force_on:1;
+        /** reg_mspi_cache_rst_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_cache_rst_en:1;
+        /** reg_dcache_clk_en : R/W; bitpos: [12]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_dcache_clk_en:1;
+        /** reg_dcache_rst_en : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dcache_rst_en:1;
+        /** reg_icache0_clk_en : R/W; bitpos: [14]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icache0_clk_en:1;
+        /** reg_icache0_rst_en : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_icache0_rst_en:1;
+        /** reg_icache1_clk_en : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icache1_clk_en:1;
+        /** reg_icache1_rst_en : R/W; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_icache1_rst_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cache_ctrl0_reg_t;
+
+
+/** Group: icm_ctrl */
+/** Type of icm_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_icm_cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icm_cpu_clk_en:1;
+        /** reg_icm_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icm_mem_clk_en:1;
+        /** reg_icm_sys_clk_en : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icm_sys_clk_en:1;
+        /** reg_icm_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_icm_apb_clk_en:1;
+        /** reg_cpuicm_gated_clk_force_on : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpuicm_gated_clk_force_on:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_clkrst_icm_ctrl0_reg_t;
+
+
+/** Group: modem_ctrl */
+/** Type of modem_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_modem_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_modem_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_modem_ctrl0_reg_t;
+
+
+/** Group: misc_ctrl */
+/** Type of misc_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_misc_cpu_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_misc_cpu_clk_en:1;
+        /** reg_misc_sys_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_misc_sys_clk_en:1;
+        /** reg_sysreg_apb_clk_en : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_sysreg_apb_clk_en:1;
+        /** reg_hp_clkrst_apb_clk_en : R/W; bitpos: [3]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_hp_clkrst_apb_clk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_misc_ctrl0_reg_t;
+
+
+/** Group: busmon_ctrl */
+/** Type of busmon_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_busmon_core0_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core0_clk_en:1;
+        /** reg_busmon_core0_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core0_clk_force_on:1;
+        /** reg_busmon_core0_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core0_rst_en:1;
+        /** reg_busmon_core0_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core0_force_norst:1;
+        /** reg_busmon_core1_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core1_clk_en:1;
+        /** reg_busmon_core1_clk_force_on : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core1_clk_force_on:1;
+        /** reg_busmon_core1_rst_en : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core1_rst_en:1;
+        /** reg_busmon_core1_force_norst : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_busmon_core1_force_norst:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_clkrst_busmon_ctrl0_reg_t;
+
+
+/** Group: remove_tmp */
+/** Type of remove_tmp0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_gdma_cpu_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gdma_cpu_clk_en:1;
+        /** reg_vpu_cpu_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_vpu_cpu_clk_en:1;
+        /** reg_vpu_sys_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_vpu_sys_clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_remove_tmp0_reg_t;
+
+
+/** Group: pvt0_ctrl */
+/** Type of pvt0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_pvt0_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_sys_clk_en:1;
+        /** reg_pvt0_top_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_top_rst_en:1;
+        /** reg_pvt0_apb_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_apb_rst_en:1;
+        /** reg_pvt0_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_clk_div_num:8;
+        /** reg_pvt0_clk_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_clk_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_pvt0_ctrl0_reg_t;
+
+
+/** Group: pvt0_peri_ctrl */
+/** Type of pvt0_peri_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_pvt0_peri_group1_rst_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_peri_group1_rst_en:1;
+        /** reg_pvt0_peri_group2_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_peri_group2_rst_en:1;
+        /** reg_pvt0_peri_group3_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_peri_group3_rst_en:1;
+        /** reg_pvt0_peri_group4_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pvt0_peri_group4_rst_en:1;
+        /** reg_pvt0_peri_group1_clk_en : R/W; bitpos: [4]; default: 0;
+         *  TOP power domain pvt clk en
+         */
+        uint32_t reg_pvt0_peri_group1_clk_en:1;
+        /** reg_pvt0_peri_group2_clk_en : R/W; bitpos: [5]; default: 0;
+         *  TOP power domain pvt clk en
+         */
+        uint32_t reg_pvt0_peri_group2_clk_en:1;
+        /** reg_pvt0_peri_group3_clk_en : R/W; bitpos: [6]; default: 0;
+         *  modem power domain pvt clk en
+         */
+        uint32_t reg_pvt0_peri_group3_clk_en:1;
+        /** reg_pvt0_peri_group4_clk_en : R/W; bitpos: [7]; default: 0;
+         *  modem power domain pvt clk en
+         */
+        uint32_t reg_pvt0_peri_group4_clk_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_sys_clkrst_pvt0_peri_ctrl0_reg_t;
+
+
+/** Group: crypto_ctrl */
+/** Type of crypto_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_crypto_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_sys_clk_en:1;
+        /** reg_crypto_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_rst_en:1;
+        /** reg_crypto_sec_clk_en : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_sec_clk_en:1;
+        /** reg_crypto_sec_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_sec_rst_en:1;
+        /** reg_crypto_aes_clk_en : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_aes_clk_en:1;
+        /** reg_crypto_aes_rst_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_aes_rst_en:1;
+        /** reg_crypto_sha_clk_en : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_sha_clk_en:1;
+        /** reg_crypto_sha_rst_en : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_sha_rst_en:1;
+        /** reg_crypto_rsa_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_rsa_clk_en:1;
+        /** reg_crypto_rsa_rst_en : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_rsa_rst_en:1;
+        /** reg_crypto_ds_clk_en : R/W; bitpos: [10]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_ds_clk_en:1;
+        /** reg_crypto_ds_rst_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_ds_rst_en:1;
+        /** reg_crypto_ecc_clk_en : R/W; bitpos: [12]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_ecc_clk_en:1;
+        /** reg_crypto_ecc_rst_en : R/W; bitpos: [13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_ecc_rst_en:1;
+        /** reg_crypto_hmac_clk_en : R/W; bitpos: [14]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_hmac_clk_en:1;
+        /** reg_crypto_hmac_rst_en : R/W; bitpos: [15]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_hmac_rst_en:1;
+        /** reg_crypto_ecdsa_clk_en : R/W; bitpos: [16]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_ecdsa_clk_en:1;
+        /** reg_crypto_ecdsa_rst_en : R/W; bitpos: [17]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_ecdsa_rst_en:1;
+        uint32_t reserved_18:2;
+        /** reg_crypto_clk_src_sel : R/W; bitpos: [21:20]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_clk_src_sel:2;
+        /** reg_crypto_rma_clk_en : R/W; bitpos: [22]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_rma_clk_en:1;
+        /** reg_crypto_rma_rst_en : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_rma_rst_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_crypto_ctrl0_reg_t;
+
+
+/** Group: key_manager_ctrl */
+/** Type of key_manager_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_key_manager_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_key_manager_sys_clk_en:1;
+        /** reg_crypto_km_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_crypto_km_rst_en:1;
+        /** reg_crypto_km_clk_en : R/W; bitpos: [2]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_crypto_km_clk_en:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_key_manager_ctrl0_reg_t;
+
+
+/** Group: dpa_ctrl */
+/** Type of dpa_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sec_dpa_level:2;
+        /** reg_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sec_dpa_cfg_sel:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dpa_ctrl0_reg_t;
+
+
+/** Group: flash_ctrl */
+/** Type of flash_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_flash_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_flash_sys_clk_en:1;
+        /** reg_flash_axi_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_flash_axi_rst_en:1;
+        /** reg_flash_apb_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_flash_apb_rst_en:1;
+        /** reg_flash_axi_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_flash_axi_force_norst:1;
+        /** reg_flash_apb_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_flash_apb_force_norst:1;
+        /** reg_flash_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_flash_clk_src_sel:2;
+        /** reg_flash_pll_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_flash_pll_clk_en:1;
+        /** reg_flash_core_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_flash_core_clk_en:1;
+        /** reg_flash_core_clk_div_num : R/W; bitpos: [16:9]; default: 3;
+         *  need_des
+         */
+        uint32_t reg_flash_core_clk_div_num:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_flash_ctrl0_reg_t;
+
+
+/** Group: psram_ctrl */
+/** Type of psram_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_psram_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_psram_sys_clk_en:1;
+        /** reg_psram_axi_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_axi_rst_en:1;
+        /** reg_psram_apb_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_apb_rst_en:1;
+        /** reg_psram_axi_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_axi_force_norst:1;
+        /** reg_psram_apb_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_apb_force_norst:1;
+        /** reg_psram_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_clk_src_sel:2;
+        /** reg_psram_pll_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_psram_pll_clk_en:1;
+        /** reg_psram_core_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_psram_core_clk_en:1;
+        /** reg_psram_core_clk_div_num : R/W; bitpos: [16:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_psram_core_clk_div_num:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_psram_ctrl0_reg_t;
+
+
+/** Group: gpspi2_ctrl */
+/** Type of gpspi2_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_gpspi2_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_sys_clk_en:1;
+        /** reg_gpspi2_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_apb_clk_en:1;
+        /** reg_gpspi2_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_rst_en:1;
+        /** reg_gpspi2_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_force_norst:1;
+        /** reg_gpspi2_clk_src_sel : R/W; bitpos: [5:4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_clk_src_sel:2;
+        /** reg_gpspi2_hs_clk_en : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_hs_clk_en:1;
+        /** reg_gpspi2_hs_clk_div_num : R/W; bitpos: [14:7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_hs_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_div_num : R/W; bitpos: [22:15]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_mst_clk_div_num:8;
+        /** reg_gpspi2_mst_clk_en : R/W; bitpos: [23]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi2_mst_clk_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_gpspi2_ctrl0_reg_t;
+
+
+/** Group: gpspi3_ctrl */
+/** Type of gpspi3_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_gpspi3_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_sys_clk_en:1;
+        /** reg_gpspi3_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_apb_clk_en:1;
+        /** reg_gpspi3_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_rst_en:1;
+        /** reg_gpspi3_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_force_norst:1;
+        /** reg_gpspi3_clk_src_sel : R/W; bitpos: [5:4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_clk_src_sel:2;
+        /** reg_gpspi3_hs_clk_en : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_hs_clk_en:1;
+        /** reg_gpspi3_hs_clk_div_num : R/W; bitpos: [14:7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_hs_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_div_num : R/W; bitpos: [22:15]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_mst_clk_div_num:8;
+        /** reg_gpspi3_mst_clk_en : R/W; bitpos: [23]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_gpspi3_mst_clk_en:1;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_gpspi3_ctrl0_reg_t;
+
+
+/** Group: gdma_ctrl */
+/** Type of gdma_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_gdma_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_gdma_sys_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_gdma_ctrl0_reg_t;
+
+
+/** Group: axi_pdma_ctrl */
+/** Type of axi_pdma_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_axi_pdma_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_axi_pdma_sys_clk_en:1;
+        /** reg_axi_pdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_axi_pdma_rst_en:1;
+        /** reg_axi_pdma_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_axi_pdma_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_axi_pdma_ctrl0_reg_t;
+
+
+/** Group: ahb_pdma_ctrl */
+/** Type of ahb_pdma_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ahb_pdma_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ahb_pdma_sys_clk_en:1;
+        /** reg_ahb_pdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ahb_pdma_rst_en:1;
+        /** reg_ahb_pdma_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ahb_pdma_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ahb_pdma_ctrl0_reg_t;
+
+
+/** Group: regdma_ctrl */
+/** Type of regdma_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_regdma_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_regdma_sys_clk_en:1;
+        /** reg_regdma_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_regdma_rst_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_regdma_ctrl0_reg_t;
+
+
+/** Group: uhci_ctrl */
+/** Type of uhci_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_uhci_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uhci_sys_clk_en:1;
+        /** reg_uhci_apb_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uhci_apb_clk_en:1;
+        /** reg_uhci_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uhci_rst_en:1;
+        /** reg_uhci_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uhci_force_norst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_uhci_ctrl0_reg_t;
+
+
+/** Group: uart0_ctrl */
+/** Type of uart0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_uart0_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart0_sys_clk_en:1;
+        /** reg_uart0_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart0_apb_clk_en:1;
+        /** reg_uart0_core_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_core_rst_en:1;
+        /** reg_uart0_apb_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_apb_rst_en:1;
+        /** reg_uart0_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_force_norst:1;
+        /** reg_uart0_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_clk_src_sel:2;
+        /** reg_uart0_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart0_clk_en:1;
+        /** reg_uart0_sclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_sclk_div_num:8;
+        /** reg_uart0_sclk_div_numerator : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_sclk_div_numerator:8;
+        /** reg_uart0_sclk_div_denominator : R/W; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart0_sclk_div_denominator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_uart0_ctrl0_reg_t;
+
+
+/** Group: uart1_ctrl */
+/** Type of uart1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_uart1_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart1_sys_clk_en:1;
+        /** reg_uart1_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart1_apb_clk_en:1;
+        /** reg_uart1_core_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_core_rst_en:1;
+        /** reg_uart1_apb_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_apb_rst_en:1;
+        /** reg_uart1_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_force_norst:1;
+        /** reg_uart1_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_clk_src_sel:2;
+        /** reg_uart1_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart1_clk_en:1;
+        /** reg_uart1_sclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_sclk_div_num:8;
+        /** reg_uart1_sclk_div_numerator : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_sclk_div_numerator:8;
+        /** reg_uart1_sclk_div_denominator : R/W; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart1_sclk_div_denominator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_uart1_ctrl0_reg_t;
+
+
+/** Group: uart2_ctrl */
+/** Type of uart2_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_uart2_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart2_sys_clk_en:1;
+        /** reg_uart2_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart2_apb_clk_en:1;
+        /** reg_uart2_core_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_core_rst_en:1;
+        /** reg_uart2_apb_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_apb_rst_en:1;
+        /** reg_uart2_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_force_norst:1;
+        /** reg_uart2_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_clk_src_sel:2;
+        /** reg_uart2_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart2_clk_en:1;
+        /** reg_uart2_sclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_sclk_div_num:8;
+        /** reg_uart2_sclk_div_numerator : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_sclk_div_numerator:8;
+        /** reg_uart2_sclk_div_denominator : R/W; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart2_sclk_div_denominator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_uart2_ctrl0_reg_t;
+
+
+/** Group: uart3_ctrl */
+/** Type of uart3_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_uart3_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart3_sys_clk_en:1;
+        /** reg_uart3_apb_clk_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart3_apb_clk_en:1;
+        /** reg_uart3_core_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_core_rst_en:1;
+        /** reg_uart3_apb_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_apb_rst_en:1;
+        /** reg_uart3_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_force_norst:1;
+        /** reg_uart3_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_clk_src_sel:2;
+        /** reg_uart3_clk_en : R/W; bitpos: [7]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_uart3_clk_en:1;
+        /** reg_uart3_sclk_div_num : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_sclk_div_num:8;
+        /** reg_uart3_sclk_div_numerator : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_sclk_div_numerator:8;
+        /** reg_uart3_sclk_div_denominator : R/W; bitpos: [31:24]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_uart3_sclk_div_denominator:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_uart3_ctrl0_reg_t;
+
+
+/** Group: parlio_ctrl */
+/** Type of parlio_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_parlio_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_sys_clk_en:1;
+        /** reg_parlio_apb_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_apb_clk_en:1;
+        /** reg_parlio_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rst_en:1;
+        /** reg_parlio_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_force_norst:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_parlio_ctrl0_reg_t;
+
+
+/** Group: parlio_rx_ctrl */
+/** Type of parlio_rx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_parlio_rx_rst_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_rst_en:1;
+        /** reg_parlio_rx_force_norst : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_force_norst:1;
+        /** reg_parlio_rx_clk_src_sel : R/W; bitpos: [3:2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_clk_src_sel:2;
+        /** reg_parlio_rx_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_clk_en:1;
+        /** reg_parlio_rx_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_clk_div_num:8;
+        /** reg_parlio_rx_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_clk_div_numerator:8;
+        /** reg_parlio_rx_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_rx_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_parlio_rx_ctrl0_reg_t;
+
+
+/** Group: parlio_tx_ctrl */
+/** Type of parlio_tx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_parlio_tx_rst_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_rst_en:1;
+        /** reg_parlio_tx_force_norst : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_force_norst:1;
+        /** reg_parlio_tx_clk_src_sel : R/W; bitpos: [3:2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_clk_src_sel:2;
+        /** reg_parlio_tx_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_clk_en:1;
+        /** reg_parlio_tx_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_clk_div_num:8;
+        /** reg_parlio_tx_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_clk_div_numerator:8;
+        /** reg_parlio_tx_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_parlio_tx_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_parlio_tx_ctrl0_reg_t;
+
+
+/** Group: bitsrambler_ctrl */
+/** Type of bitsrambler_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_bitsrambler_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_sys_clk_en:1;
+        /** reg_bitsrambler_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_rst_en:1;
+        /** reg_bitsrambler_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_force_norst:1;
+        /** reg_bitsrambler_rx_sys_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_rx_sys_clk_en:1;
+        /** reg_bitsrambler_rx_rst_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_rx_rst_en:1;
+        /** reg_bitsrambler_rx_force_norst : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_rx_force_norst:1;
+        /** reg_bitsrambler_tx_sys_clk_en : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_tx_sys_clk_en:1;
+        /** reg_bitsrambler_tx_rst_en : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_tx_rst_en:1;
+        /** reg_bitsrambler_tx_force_norst : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bitsrambler_tx_force_norst:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_bitsrambler_ctrl0_reg_t;
+
+
+/** Group: etm_ctrl */
+/** Type of etm_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** reg_etm_apb_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_etm_apb_clk_en:1;
+        /** reg_etm_rst_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_etm_rst_en:1;
+        /** reg_etm_force_norst : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_etm_force_norst:1;
+        /** reg_soc_etm_clk_sel : R/W; bitpos: [5:4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_soc_etm_clk_sel:2;
+        /** reg_soc_etm_clk_en : R/W; bitpos: [6]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_soc_etm_clk_en:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} hp_sys_clkrst_etm_ctrl0_reg_t;
+
+
+/** Group: usb_otghs_ctrl */
+/** Type of usb_otghs_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_usb_otghs_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_usb_otghs_apb_clk_en:1;
+        /** reg_usb_otghs_sys_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_usb_otghs_sys_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_usb_otghs_ctrl0_reg_t;
+
+
+/** Group: dma2d_ctrl */
+/** Type of dma2d_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_dma2d_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dma2d_sys_clk_en:1;
+        /** reg_dma2d_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dma2d_rst_en:1;
+        /** reg_dma2d_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dma2d_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dma2d_ctrl0_reg_t;
+
+
+/** Group: ppa_ctrl */
+/** Type of ppa_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ppa_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ppa_sys_clk_en:1;
+        /** reg_ppa_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ppa_rst_en:1;
+        /** reg_ppa_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ppa_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ppa_ctrl0_reg_t;
+
+
+/** Group: jpeg_ctrl */
+/** Type of jpeg_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_jpeg_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_jpeg_sys_clk_en:1;
+        /** reg_jpeg_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_jpeg_rst_en:1;
+        /** reg_jpeg_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_jpeg_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_jpeg_ctrl0_reg_t;
+
+
+/** Group: rmt_ctrl */
+/** Type of rmt_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_rmt_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_sys_clk_en:1;
+        /** reg_rmt_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_rst_en:1;
+        /** reg_rmt_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_force_norst:1;
+        /** reg_rmt_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_clk_src_sel:2;
+        /** reg_rmt_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_clk_en:1;
+        /** reg_rmt_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_clk_div_num:8;
+        /** reg_rmt_clk_div_numerator : R/W; bitpos: [21:14]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_clk_div_numerator:8;
+        /** reg_rmt_clk_div_denominator : R/W; bitpos: [29:22]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_rmt_clk_div_denominator:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} hp_sys_clkrst_rmt_ctrl0_reg_t;
+
+
+/** Group: sdio_host_ctrl */
+/** Type of sdio_host_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_sdmmc_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdmmc_sys_clk_en:1;
+        /** reg_sdio_hs_mode : R/W; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t reg_sdio_hs_mode:1;
+        /** reg_sdio_ls_clk_src_sel : R/W; bitpos: [2]; default: 0;
+         *  reserved
+         */
+        uint32_t reg_sdio_ls_clk_src_sel:1;
+        /** reg_sdio_ls_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_en:1;
+        /** reg_sdio_ls_clk_div_num : R/W; bitpos: [11:4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_div_num:8;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_sdio_host_ctrl0_reg_t;
+
+
+/** Group: sdio_host_func_ctrl */
+/** Type of sdio_host_func_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_sdio_ls_clk_edge_cfg_update : WT; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_edge_cfg_update:1;
+        /** reg_sdio_ls_clk_edge_l : R/W; bitpos: [4:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_edge_l:4;
+        /** reg_sdio_ls_clk_edge_h : R/W; bitpos: [8:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_edge_h:4;
+        /** reg_sdio_ls_clk_edge_n : R/W; bitpos: [12:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_clk_edge_n:4;
+        /** reg_sdio_ls_slf_clk_edge_sel : R/W; bitpos: [15:13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_slf_clk_edge_sel:3;
+        /** reg_sdio_ls_drv_clk_edge_sel : R/W; bitpos: [18:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_drv_clk_edge_sel:3;
+        /** reg_sdio_ls_sam_clk_edge_sel : R/W; bitpos: [21:19]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_sam_clk_edge_sel:3;
+        /** reg_sdio_ls_slf_clk_en : R/W; bitpos: [22]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_slf_clk_en:1;
+        /** reg_sdio_ls_drv_clk_en : R/W; bitpos: [23]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_drv_clk_en:1;
+        /** reg_sdio_ls_sam_clk_en : R/W; bitpos: [24]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_ls_sam_clk_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_sys_clkrst_sdio_host_func_ctrl0_reg_t;
+
+
+/** Group: emac_ctrl */
+/** Type of emac_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_emac_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_emac_sys_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_emac_ctrl0_reg_t;
+
+
+/** Group: dsi_ctrl */
+/** Type of dsi_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_dsi_sys_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dsi_sys_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dsi_ctrl0_reg_t;
+
+
+/** Group: dsi_phy_ctrl */
+/** Type of dsi_phy_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mipi_dsi_dphy_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dphy_clk_src_sel:2;
+        /** reg_mipi_dsi_dphy_cfg_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dphy_cfg_clk_en:1;
+        /** reg_mipi_dsi_dphy_pll_refclk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dphy_pll_refclk_en:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dsi_phy_ctrl0_reg_t;
+
+
+/** Group: dsi_dpi_ctrl */
+/** Type of dsi_dpi_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mipi_dsi_dpiclk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dpiclk_src_sel:2;
+        /** reg_mipi_dsi_dpiclk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dpiclk_en:1;
+        /** reg_mipi_dsi_dpiclk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mipi_dsi_dpiclk_div_num:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dsi_dpi_ctrl0_reg_t;
+
+
+/** Group: mspi_pad_ctrl */
+/** Type of mspi_pad_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mspi_pad_ctrl_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_mspi_pad_ctrl_apb_clk_en:1;
+        /** reg_mspi_pad_ctrl_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_pad_ctrl_rst_en:1;
+        /** reg_mspi_pad_ctrl_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_pad_ctrl_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mspi_pad_ctrl0_reg_t;
+
+
+/** Group: i2c0_ctrl */
+/** Type of i2c0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2c0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_apb_clk_en:1;
+        /** reg_i2c0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_rst_en:1;
+        /** reg_i2c0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_force_norst:1;
+        /** reg_i2c0_clk_src_sel : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_clk_src_sel:1;
+        /** reg_i2c0_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_clk_en:1;
+        /** reg_i2c0_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_clk_div_num:8;
+        /** reg_i2c0_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_clk_div_numerator:8;
+        /** reg_i2c0_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c0_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2c0_ctrl0_reg_t;
+
+
+/** Group: i2c1_ctrl */
+/** Type of i2c1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2c1_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_apb_clk_en:1;
+        /** reg_i2c1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_rst_en:1;
+        /** reg_i2c1_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_force_norst:1;
+        /** reg_i2c1_clk_src_sel : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_clk_src_sel:1;
+        /** reg_i2c1_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_clk_en:1;
+        /** reg_i2c1_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_clk_div_num:8;
+        /** reg_i2c1_clk_div_numerator : R/W; bitpos: [20:13]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_clk_div_numerator:8;
+        /** reg_i2c1_clk_div_denominator : R/W; bitpos: [28:21]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2c1_clk_div_denominator:8;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2c1_ctrl0_reg_t;
+
+
+/** Group: i2s0_ctrl */
+/** Type of i2s0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_apb_clk_en:1;
+        /** reg_i2s0_apb_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_apb_rst_en:1;
+        /** reg_i2s0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s0_ctrl0_reg_t;
+
+
+/** Group: i2s0_rx_ctrl */
+/** Type of i2s0_rx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_clk_en:1;
+        /** reg_i2s0_rx_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_clk_src_sel:2;
+        /** reg_i2s0_rx_div_n : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_div_n:8;
+        /** reg_i2s0_mst_clk_sel : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_mst_clk_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s0_rx_ctrl0_reg_t;
+
+
+/** Group: i2s0_rx_div_ctrl */
+/** Type of i2s0_rx_div_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_rx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_div_x:9;
+        /** reg_i2s0_rx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_div_y:9;
+        /** reg_i2s0_rx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_div_z:9;
+        /** reg_i2s0_rx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_rx_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s0_rx_div_ctrl0_reg_t;
+
+
+/** Group: i2s0_tx_ctrl */
+/** Type of i2s0_tx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_tx_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_clk_en:1;
+        /** reg_i2s0_tx_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_clk_src_sel:2;
+        /** reg_i2s0_tx_div_n : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_div_n:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s0_tx_ctrl0_reg_t;
+
+
+/** Group: i2s0_tx_div_ctrl */
+/** Type of i2s0_tx_div_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s0_tx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_div_x:9;
+        /** reg_i2s0_tx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_div_y:9;
+        /** reg_i2s0_tx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_div_z:9;
+        /** reg_i2s0_tx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s0_tx_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s0_tx_div_ctrl0_reg_t;
+
+
+/** Group: i2s1_ctrl */
+/** Type of i2s1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_apb_clk_en:1;
+        /** reg_i2s1_apb_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_apb_rst_en:1;
+        /** reg_i2s1_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s1_ctrl0_reg_t;
+
+
+/** Group: i2s1_rx_ctrl */
+/** Type of i2s1_rx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_rx_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_clk_en:1;
+        /** reg_i2s1_rx_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_clk_src_sel:2;
+        /** reg_i2s1_rx_div_n : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_div_n:8;
+        /** reg_i2s1_mst_clk_sel : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_mst_clk_sel:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s1_rx_ctrl0_reg_t;
+
+
+/** Group: i2s1_rx_div_ctrl */
+/** Type of i2s1_rx_div_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_rx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_div_x:9;
+        /** reg_i2s1_rx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_div_y:9;
+        /** reg_i2s1_rx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_div_z:9;
+        /** reg_i2s1_rx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_rx_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s1_rx_div_ctrl0_reg_t;
+
+
+/** Group: i2s1_tx_ctrl */
+/** Type of i2s1_tx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_clk_en:1;
+        /** reg_i2s1_tx_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_clk_src_sel:2;
+        /** reg_i2s1_tx_div_n : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_div_n:8;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s1_tx_ctrl0_reg_t;
+
+
+/** Group: i2s1_tx_div_ctrl */
+/** Type of i2s1_tx_div_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_i2s1_tx_div_x : R/W; bitpos: [8:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_div_x:9;
+        /** reg_i2s1_tx_div_y : R/W; bitpos: [17:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_div_y:9;
+        /** reg_i2s1_tx_div_z : R/W; bitpos: [26:18]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_div_z:9;
+        /** reg_i2s1_tx_div_yn1 : R/W; bitpos: [27]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_i2s1_tx_div_yn1:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_i2s1_tx_div_ctrl0_reg_t;
+
+
+/** Group: twai0_ctrl */
+/** Type of twai0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_twai0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai0_apb_clk_en:1;
+        /** reg_twai0_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai0_clk_src_sel:2;
+        /** reg_twai0_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai0_clk_en:1;
+        /** reg_twai0_rst_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai0_rst_en:1;
+        /** reg_twai0_force_norst : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai0_force_norst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_sys_clkrst_twai0_ctrl0_reg_t;
+
+
+/** Group: twai1_ctrl */
+/** Type of twai1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_twai1_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai1_apb_clk_en:1;
+        /** reg_twai1_clk_src_sel : R/W; bitpos: [2:1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai1_clk_src_sel:2;
+        /** reg_twai1_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai1_clk_en:1;
+        /** reg_twai1_rst_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai1_rst_en:1;
+        /** reg_twai1_force_norst : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_twai1_force_norst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_sys_clkrst_twai1_ctrl0_reg_t;
+
+
+/** Group: timergrp0_ctrl */
+/** Type of timergrp0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_timergrp0_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_apb_clk_en:1;
+        /** reg_timergrp0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_rst_en:1;
+        /** reg_timergrp0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_force_norst:1;
+        /** reg_timergrp0_t0_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_t0_src_sel:2;
+        /** reg_timergrp0_t0_clk_en : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_t0_clk_en:1;
+        /** reg_timergrp0_t1_src_sel : R/W; bitpos: [7:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_t1_src_sel:2;
+        /** reg_timergrp0_t1_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_t1_clk_en:1;
+        /** reg_timergrp0_wdt_src_sel : R/W; bitpos: [10:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_wdt_src_sel:2;
+        /** reg_timergrp0_wdt_clk_en : R/W; bitpos: [11]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_wdt_clk_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_timergrp0_ctrl0_reg_t;
+
+
+/** Group: timergrp0_tgrt_ctrl */
+/** Type of timergrp0_tgrt_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_timergrp0_tgrt_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_tgrt_clk_en:1;
+        /** reg_timergrp0_tgrt_clk_src_sel : R/W; bitpos: [4:1]; default: 8;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_tgrt_clk_src_sel:4;
+        /** reg_timergrp0_tgrt_clk_div_num : R/W; bitpos: [20:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp0_tgrt_clk_div_num:16;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} hp_sys_clkrst_timergrp0_tgrt_ctrl0_reg_t;
+
+
+/** Group: timergrp1_ctrl */
+/** Type of timergrp1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_timergrp1_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_apb_clk_en:1;
+        /** reg_timergrp1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_rst_en:1;
+        /** reg_timergrp1_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_force_norst:1;
+        /** reg_timergrp1_t0_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_t0_src_sel:2;
+        /** reg_timergrp1_t0_clk_en : R/W; bitpos: [5]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_t0_clk_en:1;
+        /** reg_timergrp1_t1_src_sel : R/W; bitpos: [7:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_t1_src_sel:2;
+        /** reg_timergrp1_t1_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_t1_clk_en:1;
+        /** reg_timergrp1_wdt_src_sel : R/W; bitpos: [10:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_wdt_src_sel:2;
+        /** reg_timergrp1_wdt_clk_en : R/W; bitpos: [11]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_timergrp1_wdt_clk_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_timergrp1_ctrl0_reg_t;
+
+
+/** Group: systimer_ctrl */
+/** Type of systimer_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_systimer_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_systimer_apb_clk_en:1;
+        /** reg_systimer_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_systimer_rst_en:1;
+        /** reg_systimer_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_systimer_force_norst:1;
+        /** reg_systimer_clk_src_sel : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_systimer_clk_src_sel:1;
+        /** reg_systimer_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_systimer_clk_en:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_clkrst_systimer_ctrl0_reg_t;
+
+
+/** Group: mcpwm0_ctrl */
+/** Type of mcpwm0_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_apb_clk_en:1;
+        /** reg_mcpwm0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_rst_en:1;
+        /** reg_mcpwm0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_force_norst:1;
+        /** reg_mcpwm0_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_clk_src_sel:2;
+        /** reg_mcpwm0_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_clk_en:1;
+        /** reg_mcpwm0_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm0_clk_div_num:8;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mcpwm0_ctrl0_reg_t;
+
+
+/** Group: mcpwm1_ctrl */
+/** Type of mcpwm1_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm1_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_apb_clk_en:1;
+        /** reg_mcpwm1_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_rst_en:1;
+        /** reg_mcpwm1_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_force_norst:1;
+        /** reg_mcpwm1_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_clk_src_sel:2;
+        /** reg_mcpwm1_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_clk_en:1;
+        /** reg_mcpwm1_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm1_clk_div_num:8;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mcpwm1_ctrl0_reg_t;
+
+
+/** Group: mcpwm2_ctrl */
+/** Type of mcpwm2_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm2_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_apb_clk_en:1;
+        /** reg_mcpwm2_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_rst_en:1;
+        /** reg_mcpwm2_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_force_norst:1;
+        /** reg_mcpwm2_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_clk_src_sel:2;
+        /** reg_mcpwm2_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_clk_en:1;
+        /** reg_mcpwm2_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm2_clk_div_num:8;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mcpwm2_ctrl0_reg_t;
+
+
+/** Group: mcpwm3_ctrl */
+/** Type of mcpwm3_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_mcpwm3_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_apb_clk_en:1;
+        /** reg_mcpwm3_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_rst_en:1;
+        /** reg_mcpwm3_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_force_norst:1;
+        /** reg_mcpwm3_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_clk_src_sel:2;
+        /** reg_mcpwm3_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_clk_en:1;
+        /** reg_mcpwm3_clk_div_num : R/W; bitpos: [13:6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mcpwm3_clk_div_num:8;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} hp_sys_clkrst_mcpwm3_ctrl0_reg_t;
+
+
+/** Group: intrmtx_ctrl */
+/** Type of intrmtx_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_intrmtx_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_intrmtx_apb_clk_en:1;
+        /** reg_intrmtx_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_intrmtx_rst_en:1;
+        /** reg_intrmtx_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_intrmtx_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_intrmtx_ctrl0_reg_t;
+
+
+/** Group: pcnt_ctrl */
+/** Type of pcnt_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_pcnt0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt0_apb_clk_en:1;
+        /** reg_pcnt0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt0_rst_en:1;
+        /** reg_pcnt0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt0_force_norst:1;
+        /** reg_pcnt1_apb_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt1_apb_clk_en:1;
+        /** reg_pcnt1_rst_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt1_rst_en:1;
+        /** reg_pcnt1_force_norst : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pcnt1_force_norst:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_sys_clkrst_pcnt_ctrl0_reg_t;
+
+
+/** Group: usb_device_ctrl */
+/** Type of usb_device_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_usb_device_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_usb_device_apb_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_usb_device_ctrl0_reg_t;
+
+
+/** Group: ledc_ctrl */
+/** Type of ledc_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ledc0_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc0_apb_clk_en:1;
+        /** reg_ledc0_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc0_rst_en:1;
+        /** reg_ledc0_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc0_force_norst:1;
+        /** reg_ledc0_clk_src_sel : R/W; bitpos: [4:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc0_clk_src_sel:2;
+        /** reg_ledc0_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc0_clk_en:1;
+        /** reg_ledc1_apb_clk_en : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc1_apb_clk_en:1;
+        /** reg_ledc1_rst_en : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc1_rst_en:1;
+        /** reg_ledc1_force_norst : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc1_force_norst:1;
+        /** reg_ledc1_clk_src_sel : R/W; bitpos: [10:9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc1_clk_src_sel:2;
+        /** reg_ledc1_clk_en : R/W; bitpos: [11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ledc1_clk_en:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ledc_ctrl0_reg_t;
+
+
+/** Group: lcdcam_ctrl */
+/** Type of lcdcam_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_lcdcam_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_apb_clk_en:1;
+        /** reg_lcdcam_apb_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_apb_rst_en:1;
+        /** reg_lcdcam_sys_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_sys_clk_en:1;
+        /** reg_lcdcam_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_rst_en:1;
+        /** reg_lcdcam_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_force_norst:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_sys_clkrst_lcdcam_ctrl0_reg_t;
+
+
+/** Group: lcdcam_lcd_ctrl */
+/** Type of lcdcam_lcd_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_lcd_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcd_clk_src_sel:2;
+        /** reg_lcd_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcd_clk_en:1;
+        /** reg_lcd_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcd_clk_div_num:8;
+        /** reg_lcd_clk_div_numerator : R/W; bitpos: [18:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcd_clk_div_numerator:8;
+        /** reg_lcd_clk_div_denominator : R/W; bitpos: [26:19]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcd_clk_div_denominator:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_lcdcam_lcd_ctrl0_reg_t;
+
+
+/** Group: lcdcam_lcdcam_ctrl */
+/** Type of lcdcam_lcdcam_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_lcdcam_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_clk_src_sel:2;
+        /** reg_lcdcam_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_clk_en:1;
+        /** reg_lcdcam_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_clk_div_num:8;
+        /** reg_lcdcam_clk_div_numerator : R/W; bitpos: [18:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_clk_div_numerator:8;
+        /** reg_lcdcam_clk_div_denominator : R/W; bitpos: [26:19]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lcdcam_clk_div_denominator:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_lcdcam_lcdcam_ctrl0_reg_t;
+
+
+/** Group: lcdcam_cam_ctrl */
+/** Type of lcdcam_cam_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cam_clk_src_sel : R/W; bitpos: [1:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cam_clk_src_sel:2;
+        /** reg_cam_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cam_clk_en:1;
+        /** reg_cam_clk_div_num : R/W; bitpos: [10:3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cam_clk_div_num:8;
+        /** reg_cam_clk_div_numerator : R/W; bitpos: [18:11]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cam_clk_div_numerator:8;
+        /** reg_cam_clk_div_denominator : R/W; bitpos: [26:19]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cam_clk_div_denominator:8;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} hp_sys_clkrst_lcdcam_cam_ctrl0_reg_t;
+
+
+/** Group: iomux_ctrl */
+/** Type of iomux_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_iomux_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_iomux_apb_clk_en:1;
+        /** reg_iomux_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_iomux_rst_en:1;
+        /** reg_iomux_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_iomux_force_norst:1;
+        /** reg_iomux_clk_src_sel : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_iomux_clk_src_sel:1;
+        /** reg_iomux_clk_en : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_iomux_clk_en:1;
+        /** reg_iomux_clk_div_num : R/W; bitpos: [12:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_iomux_clk_div_num:8;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} hp_sys_clkrst_iomux_ctrl0_reg_t;
+
+
+/** Group: hpwdt_core0_rst_ctrl */
+/** Type of hpwdt_core0_rst_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_stall_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_hpcore0_stall_en:1;
+        /** reg_hpcore0_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  need_des
+         */
+        uint32_t reg_hpcore0_stall_wait_num:8;
+        /** reg_wdt_hpcore0_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  need_des
+         */
+        uint32_t reg_wdt_hpcore0_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t;
+
+
+/** Group: hpwdt_core1_rst_ctrl */
+/** Type of hpwdt_core1_rst_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_hpcore1_stall_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_hpcore1_stall_en:1;
+        /** reg_hpcore1_stall_wait_num : R/W; bitpos: [8:1]; default: 8;
+         *  need_des
+         */
+        uint32_t reg_hpcore1_stall_wait_num:8;
+        /** reg_wdt_hpcore1_rst_len : R/W; bitpos: [16:9]; default: 8;
+         *  need_des
+         */
+        uint32_t reg_wdt_hpcore1_rst_len:8;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t;
+
+
+/** Group: cpu_src_freq */
+/** Type of cpu_src_freq0 register
+ *  CPU Source Frequency
+ */
+typedef union {
+    struct {
+        /** reg_cpu_src_freq : RO; bitpos: [31:0]; default: 0;
+         *  cpu source clock frequency, step by 0.25MHz
+         */
+        uint32_t reg_cpu_src_freq:32;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_src_freq0_reg_t;
+
+
+/** Group: cpu_clk_status */
+/** Type of cpu_clk_status0 register
+ *  CPU Clock Status
+ */
+typedef union {
+    struct {
+        /** reg_asic_or_fpga : RO; bitpos: [0]; default: 0;
+         *  0: ASIC mode, 1: FPGA mode
+         */
+        uint32_t reg_asic_or_fpga:1;
+        /** reg_cpu_div_effect : RO; bitpos: [1]; default: 0;
+         *  0: Divider bypass, 1: Divider takes effect
+         */
+        uint32_t reg_cpu_div_effect:1;
+        /** reg_cpu_src_is_cpll : RO; bitpos: [2]; default: 0;
+         *  0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m
+         */
+        uint32_t reg_cpu_src_is_cpll:1;
+        /** reg_cpu_div_num_cur : RO; bitpos: [10:3]; default: 0;
+         *  cpu current div number
+         */
+        uint32_t reg_cpu_div_num_cur:8;
+        /** reg_cpu_div_numerator_cur : RO; bitpos: [13:11]; default: 0;
+         *  cpu current div numerator
+         */
+        uint32_t reg_cpu_div_numerator_cur:3;
+        /** reg_cpu_div_denominator_cur : RO; bitpos: [16:14]; default: 0;
+         *  cpu current div denominator
+         */
+        uint32_t reg_cpu_div_denominator_cur:3;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cpu_clk_status0_reg_t;
+
+
+/** Group: hpcore_wdt_reset_source */
+/** Type of hpcore_wdt_reset_source0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_hpcore0_wdt_reset_source_sel : R/W; bitpos: [0]; default: 0;
+         *  1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0
+         */
+        uint32_t reg_hpcore0_wdt_reset_source_sel:1;
+        /** reg_hpcore1_wdt_reset_source_sel : R/W; bitpos: [1]; default: 1;
+         *  1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1
+         */
+        uint32_t reg_hpcore1_wdt_reset_source_sel:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t;
+
+
+/** Group: ana_pll_ctrl */
+/** Type of ana_pll_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_plla_cal_end : RO; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_plla_cal_end:1;
+        /** reg_plla_cal_stop : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_plla_cal_stop:1;
+        /** reg_cpu_pll_cal_end : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_pll_cal_end:1;
+        /** reg_cpu_pll_cal_stop : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_pll_cal_stop:1;
+        /** reg_sdio_pll_cal_end : RO; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_pll_cal_end:1;
+        /** reg_sdio_pll_cal_stop : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_sdio_pll_cal_stop:1;
+        /** reg_bbpll_cal_end : RO; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bbpll_cal_end:1;
+        /** reg_bbpll_cal_stop : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_bbpll_cal_stop:1;
+        /** reg_mspi_cal_end : RO; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_cal_end:1;
+        /** reg_mspi_cal_stop : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_mspi_cal_stop:1;
+        /** reg_pll_cal_end : RO; bitpos: [10]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_pll_cal_end:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ana_pll_ctrl0_reg_t;
+
+
+/** Group: ref_500m_ctrl */
+/** Type of ref_500m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_500m_sel : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ref_500m_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_500m_ctrl0_reg_t;
+
+
+/** Group: ref_240m_ctrl */
+/** Type of ref_240m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_240m_clk_div_num : R/W; bitpos: [7:0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_240m_clk_div_num:8;
+        /** reg_ref_240m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_240m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_240m_ctrl0_reg_t;
+
+
+/** Group: ref_160m_ctrl */
+/** Type of ref_160m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_160m_clk_div_num : R/W; bitpos: [7:0]; default: 2;
+         *  need_des
+         */
+        uint32_t reg_ref_160m_clk_div_num:8;
+        /** reg_ref_160m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_160m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_160m_ctrl0_reg_t;
+
+
+/** Group: ref_120m_ctrl */
+/** Type of ref_120m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_120m_clk_div_num : R/W; bitpos: [7:0]; default: 3;
+         *  need_des
+         */
+        uint32_t reg_ref_120m_clk_div_num:8;
+        /** reg_ref_120m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_120m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_120m_ctrl0_reg_t;
+
+
+/** Group: ref_80m_ctrl */
+/** Type of ref_80m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_80m_clk_div_num : R/W; bitpos: [7:0]; default: 5;
+         *  need_des
+         */
+        uint32_t reg_ref_80m_clk_div_num:8;
+        /** reg_ref_80m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_80m_clk_en:1;
+        /** reg_ref_80m_sel : R/W; bitpos: [9]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ref_80m_sel:1;
+        /** reg_ref_80m_mux_clk_en : R/W; bitpos: [10]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_80m_mux_clk_en:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_80m_ctrl0_reg_t;
+
+
+/** Group: ref_60m_ctrl */
+/** Type of ref_60m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_60m_clk_div_num : R/W; bitpos: [7:0]; default: 7;
+         *  need_des
+         */
+        uint32_t reg_ref_60m_clk_div_num:8;
+        /** reg_ref_60m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_60m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_60m_ctrl0_reg_t;
+
+
+/** Group: ref_20m_ctrl */
+/** Type of ref_20m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_20m_clk_div_num : R/W; bitpos: [7:0]; default: 23;
+         *  need_des
+         */
+        uint32_t reg_ref_20m_clk_div_num:8;
+        /** reg_ref_20m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_20m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_20m_ctrl0_reg_t;
+
+
+/** Group: ref_50m_ctrl */
+/** Type of ref_50m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_50m_clk_div_num : R/W; bitpos: [7:0]; default: 5;
+         *  need_des
+         */
+        uint32_t reg_ref_50m_clk_div_num:8;
+        /** reg_ref_50m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_50m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_50m_ctrl0_reg_t;
+
+
+/** Group: ref_25m_ctrl */
+/** Type of ref_25m_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ref_25m_clk_div_num : R/W; bitpos: [7:0]; default: 11;
+         *  need_des
+         */
+        uint32_t reg_ref_25m_clk_div_num:8;
+        /** reg_ref_25m_clk_en : R/W; bitpos: [8]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ref_25m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ref_25m_ctrl0_reg_t;
+
+
+/** Group: tm_clk_ctrl */
+/** Type of tm_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_tm_480m_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_480m_clk_en:1;
+        /** reg_tm_240m_clk_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_240m_clk_en:1;
+        /** reg_tm_160m_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_160m_clk_en:1;
+        /** reg_tm_120m_clk_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_120m_clk_en:1;
+        /** reg_tm_80m_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_80m_clk_en:1;
+        /** reg_tm_60m_clk_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_60m_clk_en:1;
+        /** reg_tm_48m_clk_en : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_48m_clk_en:1;
+        /** reg_tm_20m_clk_en : R/W; bitpos: [7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_20m_clk_en:1;
+        /** reg_tm_250m_clk_en : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_tm_250m_clk_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_tm_clk_ctrl0_reg_t;
+
+
+/** Group: dbg0_clk_ctrl */
+/** Type of dbg0_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch0_sel : R/W; bitpos: [7:0]; default: 255;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch0_sel:8;
+        /** reg_dbg_ch0_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch0_div_num:8;
+        /** reg_dbg_ch0_en : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch0_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg0_clk_ctrl0_reg_t;
+
+
+/** Group: dbg1_clk_ctrl */
+/** Type of dbg1_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch1_sel : R/W; bitpos: [7:0]; default: 255;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch1_sel:8;
+        /** reg_dbg_ch1_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch1_div_num:8;
+        /** reg_dbg_ch1_en : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch1_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg1_clk_ctrl0_reg_t;
+
+
+/** Group: dbg2_clk_ctrl */
+/** Type of dbg2_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_dbg_ch2_sel : R/W; bitpos: [7:0]; default: 255;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch2_sel:8;
+        /** reg_dbg_ch2_div_num : R/W; bitpos: [15:8]; default: 3;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch2_div_num:8;
+        /** reg_dbg_ch2_en : R/W; bitpos: [16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dbg_ch2_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_sys_clkrst_dbg2_clk_ctrl0_reg_t;
+
+
+/** Group: lp_clk_ctrl */
+/** Type of lp_clk_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_lpaon_fosc_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lpaon_fosc_clk_force_on:1;
+        /** reg_lpaon_xtal_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lpaon_xtal_clk_force_on:1;
+        /** reg_lpaon_pll80m_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_lpaon_pll80m_clk_force_on:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_lp_clk_ctrl0_reg_t;
+
+
+/** Group: ahb_asrc_ctrl */
+/** Type of ahb_asrc_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_ahb_asrc_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_ahb_asrc_sys_clk_en:1;
+        /** reg_ahb_asrc_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ahb_asrc_rst_en:1;
+        /** reg_ahb_asrc_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ahb_asrc_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_ahb_asrc_ctrl0_reg_t;
+
+
+/** Group: cordic_ctrl */
+/** Type of cordic_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cordic_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_apb_clk_en:1;
+        /** reg_cordic_apb_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_apb_rst_en:1;
+        /** reg_cordic_sys_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_sys_clk_en:1;
+        /** reg_cordic_sys_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_sys_rst_en:1;
+        /** reg_cordic_clk_en : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_clk_en:1;
+        /** reg_cordic_core_rst_en : R/W; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_core_rst_en:1;
+        /** reg_cordic_force_norst : R/W; bitpos: [6]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_force_norst:1;
+        /** reg_cordic_clk_src_sel : R/W; bitpos: [8:7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_clk_src_sel:2;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cordic_ctrl0_reg_t;
+
+/** Type of cordic_ctrl1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cordic_clk_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_clk_div_num:8;
+        /** reg_cordic_clk_div_numerator : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_clk_div_numerator:8;
+        /** reg_cordic_clk_div_denonimator : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cordic_clk_div_denonimator:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cordic_ctrl1_reg_t;
+
+
+/** Group: zero_det_ctrl */
+/** Type of zero_det_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_zero_det_apb_clk_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_apb_clk_en:1;
+        /** reg_zero_det_apb_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_apb_rst_en:1;
+        /** reg_zero_det_clk_en : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_clk_en:1;
+        /** reg_zero_det_core_rst_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_core_rst_en:1;
+        /** reg_zero_det_force_norst : R/W; bitpos: [4]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_force_norst:1;
+        /** reg_zero_det_clk_src_sel : R/W; bitpos: [6:5]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_clk_src_sel:2;
+        /** reg_zero_det_clk_div_num : R/W; bitpos: [14:7]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_zero_det_clk_div_num:8;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} hp_sys_clkrst_zero_det_ctrl0_reg_t;
+
+
+/** Group: power_ctrl */
+/** Type of clk_pwr_decrease register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_apb_hw_decrease_div_num : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_apb_hw_decrease_div_num:8;
+        /** reg_cpu_wfi_decrease_en : R/W; bitpos: [8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_cpu_wfi_decrease_en:1;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_pwr_decrease_reg_t;
+
+
+/** Group: cnnt_iomux_ctrl */
+/** Type of cnnt_iomux_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cnnt_iomux_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  cnnt_iomux clk en
+         */
+        uint32_t reg_cnnt_iomux_apb_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cnnt_iomux_ctrl0_reg_t;
+
+
+/** Group: hp_i2cmst_ctrl */
+/** Type of hp_i2cmst_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_hp_i2cmst_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_hp_i2cmst_apb_clk_en:1;
+        /** reg_hp_i2cmst_rst_en : R/W; bitpos: [1]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_hp_i2cmst_rst_en:1;
+        /** reg_hp_i2cmst_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_hp_i2cmst_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_i2cmst_ctrl0_reg_t;
+
+
+/** Group: axi_perf_mon_ctrl */
+/** Type of axi_perf_mon_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_axi_perf_mon_rst_en : R/W; bitpos: [0]; default: 0;
+         *  axi_perf_mon rst en
+         */
+        uint32_t reg_axi_perf_mon_rst_en:1;
+        /** reg_axi_perf_mon_clk_en : R/W; bitpos: [1]; default: 0;
+         *  axi_perf_mon clk en
+         */
+        uint32_t reg_axi_perf_mon_clk_en:1;
+        /** reg_axi_perf_mon_force_norst : R/W; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_axi_perf_mon_force_norst:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_sys_clkrst_axi_perf_mon_ctrl0_reg_t;
+
+
+/** Group: cnnt_sysreg_ctrl */
+/** Type of cnnt_sysreg_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_cnnt_sysreg_sys_clk_en : R/W; bitpos: [0]; default: 1;
+         *  cnnt_sysreg clk en
+         */
+        uint32_t reg_cnnt_sysreg_sys_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_cnnt_sysreg_ctrl0_reg_t;
+
+
+/** Group: hp alive_sysreg_ctrl */
+/** Type of hp_alive_sysreg_ctrl0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_hp_alive_sysreg_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  hp alive_sysreg clk en
+         */
+        uint32_t reg_hp_alive_sysreg_apb_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_hp_alive_sysreg_ctrl0_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of modem_conf register
+ *  MODEM_APB configuration register
+ */
+typedef union {
+    struct {
+        /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1;
+         *  This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default).
+         */
+        uint32_t modem_apb_clk_en:1;
+        /** modem_rst_en : R/W; bitpos: [1]; default: 0;
+         *  Set this file as 1 to reset modem-subsystem.
+         */
+        uint32_t modem_rst_en:1;
+        /** modem_clk_en : R/W; bitpos: [2]; default: 1;
+         *  This field indicates if modem source clock is enable. 0: disable, 1:
+         *  enable(default).
+         */
+        uint32_t modem_clk_en:1;
+        /** modem_clk_source_sel : R/W; bitpos: [3]; default: 0;
+         *  modem clk source sel
+         */
+        uint32_t modem_clk_source_sel:1;
+        /** modem_pll_clk_en : R/W; bitpos: [4]; default: 0;
+         *  modem clk source pll on
+         */
+        uint32_t modem_pll_clk_en:1;
+        /** modem_xtal_clk_en : R/W; bitpos: [5]; default: 1;
+         *  modem clk source xtal on
+         */
+        uint32_t modem_xtal_clk_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_sys_clkrst_modem_conf_reg_t;
+
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  need_des
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_sys_clkrst_clk_en0_reg_t;
+
+
+/** Group: date_reg */
+/** Type of date register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 38834448;
+         *  Version control register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} hp_sys_clkrst_date_reg_t;
+
+
+typedef struct {
+    volatile hp_sys_clkrst_soc_clk_sel_reg_t soc_clk_sel;
+    volatile hp_sys_clkrst_cpu_freq_ctrl0_reg_t cpu_freq_ctrl0;
+    volatile hp_sys_clkrst_mem_freq_ctrl0_reg_t mem_freq_ctrl0;
+    volatile hp_sys_clkrst_sys_freq_ctrl0_reg_t sys_freq_ctrl0;
+    volatile hp_sys_clkrst_apb_freq_ctrl0_reg_t apb_freq_ctrl0;
+    volatile hp_sys_clkrst_root_clk_ctrl0_reg_t root_clk_ctrl0;
+    volatile hp_sys_clkrst_cpu_wfi_delay_ctrl0_reg_t cpu_wfi_delay_ctrl0;
+    volatile hp_sys_clkrst_hpcore0_ctrl0_reg_t hpcore0_ctrl0;
+    volatile hp_sys_clkrst_hpcore1_ctrl0_reg_t hpcore1_ctrl0;
+    volatile hp_sys_clkrst_trace_ctrl0_reg_t trace_ctrl0;
+    volatile hp_sys_clkrst_tcm_ctrl0_reg_t tcm_ctrl0;
+    volatile hp_sys_clkrst_tcmmon_ctrl0_reg_t tcmmon_ctrl0;
+    volatile hp_sys_clkrst_psrammon_ctrl0_reg_t psrammon_ctrl0;
+    volatile hp_sys_clkrst_rom_ctrl0_reg_t rom_ctrl0;
+    volatile hp_sys_clkrst_cache_ctrl0_reg_t cache_ctrl0;
+    volatile hp_sys_clkrst_icm_ctrl0_reg_t icm_ctrl0;
+    volatile hp_sys_clkrst_modem_ctrl0_reg_t modem_ctrl0;
+    volatile hp_sys_clkrst_misc_ctrl0_reg_t misc_ctrl0;
+    volatile hp_sys_clkrst_busmon_ctrl0_reg_t busmon_ctrl0;
+    volatile hp_sys_clkrst_remove_tmp0_reg_t remove_tmp0;
+    volatile hp_sys_clkrst_pvt0_ctrl0_reg_t pvt0_ctrl0;
+    volatile hp_sys_clkrst_pvt0_peri_ctrl0_reg_t pvt0_peri_ctrl0;
+    volatile hp_sys_clkrst_crypto_ctrl0_reg_t crypto_ctrl0;
+    volatile hp_sys_clkrst_key_manager_ctrl0_reg_t key_manager_ctrl0;
+    volatile hp_sys_clkrst_dpa_ctrl0_reg_t dpa_ctrl0;
+    volatile hp_sys_clkrst_flash_ctrl0_reg_t flash_ctrl0;
+    volatile hp_sys_clkrst_psram_ctrl0_reg_t psram_ctrl0;
+    volatile hp_sys_clkrst_gpspi2_ctrl0_reg_t gpspi2_ctrl0;
+    volatile hp_sys_clkrst_gpspi3_ctrl0_reg_t gpspi3_ctrl0;
+    volatile hp_sys_clkrst_gdma_ctrl0_reg_t gdma_ctrl0;
+    volatile hp_sys_clkrst_axi_pdma_ctrl0_reg_t axi_pdma_ctrl0;
+    volatile hp_sys_clkrst_ahb_pdma_ctrl0_reg_t ahb_pdma_ctrl0;
+    volatile hp_sys_clkrst_regdma_ctrl0_reg_t regdma_ctrl0;
+    volatile hp_sys_clkrst_uhci_ctrl0_reg_t uhci_ctrl0;
+    volatile hp_sys_clkrst_uart0_ctrl0_reg_t uart0_ctrl0;
+    volatile hp_sys_clkrst_uart1_ctrl0_reg_t uart1_ctrl0;
+    volatile hp_sys_clkrst_uart2_ctrl0_reg_t uart2_ctrl0;
+    volatile hp_sys_clkrst_uart3_ctrl0_reg_t uart3_ctrl0;
+    volatile hp_sys_clkrst_parlio_ctrl0_reg_t parlio_ctrl0;
+    volatile hp_sys_clkrst_parlio_rx_ctrl0_reg_t parlio_rx_ctrl0;
+    volatile hp_sys_clkrst_parlio_tx_ctrl0_reg_t parlio_tx_ctrl0;
+    volatile hp_sys_clkrst_bitsrambler_ctrl0_reg_t bitsrambler_ctrl0;
+    volatile hp_sys_clkrst_etm_ctrl0_reg_t etm_ctrl0;
+    volatile hp_sys_clkrst_usb_otghs_ctrl0_reg_t usb_otghs_ctrl0;
+    volatile hp_sys_clkrst_dma2d_ctrl0_reg_t dma2d_ctrl0;
+    volatile hp_sys_clkrst_ppa_ctrl0_reg_t ppa_ctrl0;
+    volatile hp_sys_clkrst_jpeg_ctrl0_reg_t jpeg_ctrl0;
+    volatile hp_sys_clkrst_rmt_ctrl0_reg_t rmt_ctrl0;
+    volatile hp_sys_clkrst_sdio_host_ctrl0_reg_t sdio_host_ctrl0;
+    volatile hp_sys_clkrst_sdio_host_func_ctrl0_reg_t sdio_host_func_ctrl0;
+    volatile hp_sys_clkrst_emac_ctrl0_reg_t emac_ctrl0;
+    volatile hp_sys_clkrst_dsi_ctrl0_reg_t dsi_ctrl0;
+    volatile hp_sys_clkrst_dsi_phy_ctrl0_reg_t dsi_phy_ctrl0;
+    volatile hp_sys_clkrst_dsi_dpi_ctrl0_reg_t dsi_dpi_ctrl0;
+    volatile hp_sys_clkrst_mspi_pad_ctrl0_reg_t mspi_pad_ctrl0;
+    volatile hp_sys_clkrst_i2c0_ctrl0_reg_t i2c0_ctrl0;
+    volatile hp_sys_clkrst_i2c1_ctrl0_reg_t i2c1_ctrl0;
+    volatile hp_sys_clkrst_i2s0_ctrl0_reg_t i2s0_ctrl0;
+    volatile hp_sys_clkrst_i2s0_rx_ctrl0_reg_t i2s0_rx_ctrl0;
+    volatile hp_sys_clkrst_i2s0_rx_div_ctrl0_reg_t i2s0_rx_div_ctrl0;
+    volatile hp_sys_clkrst_i2s0_tx_ctrl0_reg_t i2s0_tx_ctrl0;
+    volatile hp_sys_clkrst_i2s0_tx_div_ctrl0_reg_t i2s0_tx_div_ctrl0;
+    volatile hp_sys_clkrst_i2s1_ctrl0_reg_t i2s1_ctrl0;
+    volatile hp_sys_clkrst_i2s1_rx_ctrl0_reg_t i2s1_rx_ctrl0;
+    volatile hp_sys_clkrst_i2s1_rx_div_ctrl0_reg_t i2s1_rx_div_ctrl0;
+    volatile hp_sys_clkrst_i2s1_tx_ctrl0_reg_t i2s1_tx_ctrl0;
+    volatile hp_sys_clkrst_i2s1_tx_div_ctrl0_reg_t i2s1_tx_div_ctrl0;
+    volatile hp_sys_clkrst_twai0_ctrl0_reg_t twai0_ctrl0;
+    volatile hp_sys_clkrst_twai1_ctrl0_reg_t twai1_ctrl0;
+    volatile hp_sys_clkrst_timergrp0_ctrl0_reg_t timergrp0_ctrl0;
+    volatile hp_sys_clkrst_timergrp0_tgrt_ctrl0_reg_t timergrp0_tgrt_ctrl0;
+    volatile hp_sys_clkrst_timergrp1_ctrl0_reg_t timergrp1_ctrl0;
+    volatile hp_sys_clkrst_systimer_ctrl0_reg_t systimer_ctrl0;
+    volatile hp_sys_clkrst_mcpwm0_ctrl0_reg_t mcpwm0_ctrl0;
+    volatile hp_sys_clkrst_mcpwm1_ctrl0_reg_t mcpwm1_ctrl0;
+    volatile hp_sys_clkrst_mcpwm2_ctrl0_reg_t mcpwm2_ctrl0;
+    volatile hp_sys_clkrst_mcpwm3_ctrl0_reg_t mcpwm3_ctrl0;
+    volatile hp_sys_clkrst_intrmtx_ctrl0_reg_t intrmtx_ctrl0;
+    volatile hp_sys_clkrst_pcnt_ctrl0_reg_t pcnt_ctrl0;
+    uint32_t reserved_13c[2];
+    volatile hp_sys_clkrst_usb_device_ctrl0_reg_t usb_device_ctrl0;
+    volatile hp_sys_clkrst_ledc_ctrl0_reg_t ledc_ctrl0;
+    volatile hp_sys_clkrst_lcdcam_ctrl0_reg_t lcdcam_ctrl0;
+    volatile hp_sys_clkrst_lcdcam_lcd_ctrl0_reg_t lcdcam_lcd_ctrl0;
+    volatile hp_sys_clkrst_lcdcam_lcdcam_ctrl0_reg_t lcdcam_lcdcam_ctrl0;
+    volatile hp_sys_clkrst_lcdcam_cam_ctrl0_reg_t lcdcam_cam_ctrl0;
+    volatile hp_sys_clkrst_iomux_ctrl0_reg_t iomux_ctrl0;
+    volatile hp_sys_clkrst_hpwdt_core0_rst_ctrl0_reg_t hpwdt_core0_rst_ctrl0;
+    volatile hp_sys_clkrst_hpwdt_core1_rst_ctrl0_reg_t hpwdt_core1_rst_ctrl0;
+    volatile hp_sys_clkrst_cpu_src_freq0_reg_t cpu_src_freq0;
+    volatile hp_sys_clkrst_cpu_clk_status0_reg_t cpu_clk_status0;
+    volatile hp_sys_clkrst_hpcore_wdt_reset_source0_reg_t hpcore_wdt_reset_source0;
+    volatile hp_sys_clkrst_ana_pll_ctrl0_reg_t ana_pll_ctrl0;
+    volatile hp_sys_clkrst_ref_500m_ctrl0_reg_t ref_500m_ctrl0;
+    volatile hp_sys_clkrst_ref_240m_ctrl0_reg_t ref_240m_ctrl0;
+    volatile hp_sys_clkrst_ref_160m_ctrl0_reg_t ref_160m_ctrl0;
+    volatile hp_sys_clkrst_ref_120m_ctrl0_reg_t ref_120m_ctrl0;
+    volatile hp_sys_clkrst_ref_80m_ctrl0_reg_t ref_80m_ctrl0;
+    volatile hp_sys_clkrst_ref_60m_ctrl0_reg_t ref_60m_ctrl0;
+    volatile hp_sys_clkrst_ref_20m_ctrl0_reg_t ref_20m_ctrl0;
+    volatile hp_sys_clkrst_ref_50m_ctrl0_reg_t ref_50m_ctrl0;
+    volatile hp_sys_clkrst_ref_25m_ctrl0_reg_t ref_25m_ctrl0;
+    volatile hp_sys_clkrst_tm_clk_ctrl0_reg_t tm_clk_ctrl0;
+    volatile hp_sys_clkrst_dbg0_clk_ctrl0_reg_t dbg0_clk_ctrl0;
+    volatile hp_sys_clkrst_dbg1_clk_ctrl0_reg_t dbg1_clk_ctrl0;
+    volatile hp_sys_clkrst_dbg2_clk_ctrl0_reg_t dbg2_clk_ctrl0;
+    volatile hp_sys_clkrst_lp_clk_ctrl0_reg_t lp_clk_ctrl0;
+    volatile hp_sys_clkrst_ahb_asrc_ctrl0_reg_t ahb_asrc_ctrl0;
+    volatile hp_sys_clkrst_cordic_ctrl0_reg_t cordic_ctrl0;
+    volatile hp_sys_clkrst_zero_det_ctrl0_reg_t zero_det_ctrl0;
+    volatile hp_sys_clkrst_cordic_ctrl1_reg_t cordic_ctrl1;
+    uint32_t reserved_1c0[2];
+    volatile hp_sys_clkrst_clk_pwr_decrease_reg_t clk_pwr_decrease;
+    volatile hp_sys_clkrst_cnnt_iomux_ctrl0_reg_t cnnt_iomux_ctrl0;
+    volatile hp_sys_clkrst_hp_i2cmst_ctrl0_reg_t hp_i2cmst_ctrl0;
+    volatile hp_sys_clkrst_axi_perf_mon_ctrl0_reg_t axi_perf_mon_ctrl0;
+    volatile hp_sys_clkrst_cnnt_sysreg_ctrl0_reg_t cnnt_sysreg_ctrl0;
+    volatile hp_sys_clkrst_hp_alive_sysreg_ctrl0_reg_t hp_alive_sysreg_ctrl0;
+    volatile hp_sys_clkrst_modem_conf_reg_t modem_conf;
+    uint32_t reserved_1e4[5];
+    volatile hp_sys_clkrst_clk_en0_reg_t clk_en0;
+    volatile hp_sys_clkrst_date_reg_t date;
+} hp_sys_clkrst_dev_t;
+
+extern hp_sys_clkrst_dev_t HP_SYS_CLKRST;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_sys_clkrst_dev_t) == 0x200, "Invalid size of hp_sys_clkrst_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_system_reg.h b/components/soc/esp32s31/register/soc/hp_system_reg.h
new file mode 100644
index 00000000000..f76f68f5359
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_system_reg.h
@@ -0,0 +1,2380 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+// #include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HP_SYSTEM_VER_DATE_REG register
+ *  NA
+ */
+#define HP_SYSTEM_VER_DATE_REG (DR_REG_HP_SYS_BASE + 0x0)
+/** HP_SYSTEM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296770;
+ *  NA
+ */
+#define HP_SYSTEM_REG_VER_DATE    0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_M  (HP_SYSTEM_REG_VER_DATE_V << HP_SYSTEM_REG_VER_DATE_S)
+#define HP_SYSTEM_REG_VER_DATE_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_VER_DATE_S  0
+
+/** HP_SYSTEM_CLK_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CLK_EN_REG (DR_REG_HP_SYS_BASE + 0x4)
+/** HP_SYSTEM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_CLK_EN    (BIT(0))
+#define HP_SYSTEM_REG_CLK_EN_M  (HP_SYSTEM_REG_CLK_EN_V << HP_SYSTEM_REG_CLK_EN_S)
+#define HP_SYSTEM_REG_CLK_EN_V  0x00000001U
+#define HP_SYSTEM_REG_CLK_EN_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_REG (DR_REG_HP_SYS_BASE + 0x10)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_M  (HP_SYSTEM_CPU_INT_FROM_CPU_0_V << HP_SYSTEM_CPU_INT_FROM_CPU_0_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_0_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_1_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_REG (DR_REG_HP_SYS_BASE + 0x14)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_M  (HP_SYSTEM_CPU_INT_FROM_CPU_1_V << HP_SYSTEM_CPU_INT_FROM_CPU_1_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_1_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_2_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_REG (DR_REG_HP_SYS_BASE + 0x18)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_M  (HP_SYSTEM_CPU_INT_FROM_CPU_2_V << HP_SYSTEM_CPU_INT_FROM_CPU_2_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_2_S  0
+
+/** HP_SYSTEM_CPU_INT_FROM_CPU_3_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_REG (DR_REG_HP_SYS_BASE + 0x1c)
+/** HP_SYSTEM_CPU_INT_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  set 1 will trigger a interrupt
+ */
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3    (BIT(0))
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_M  (HP_SYSTEM_CPU_INT_FROM_CPU_3_V << HP_SYSTEM_CPU_INT_FROM_CPU_3_S)
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_V  0x00000001U
+#define HP_SYSTEM_CPU_INT_FROM_CPU_3_S  0
+
+/** HP_SYSTEM_MODEM_DIAG_EN_REG register
+ *  NA
+ */
+#define HP_SYSTEM_MODEM_DIAG_EN_REG (DR_REG_HP_SYS_BASE + 0x28)
+/** HP_SYSTEM_REG_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
+ *  set reg_modem_diag_en[15:0] will let hp_probe_out[15:0] used as modem_diag[15:0],
+ *  set reg_modem_diag_en[31:16] will let lcd_data_out[15:0] used as modem_diag[31:16]
+ */
+#define HP_SYSTEM_REG_MODEM_DIAG_EN    0xFFFFFFFFU
+#define HP_SYSTEM_REG_MODEM_DIAG_EN_M  (HP_SYSTEM_REG_MODEM_DIAG_EN_V << HP_SYSTEM_REG_MODEM_DIAG_EN_S)
+#define HP_SYSTEM_REG_MODEM_DIAG_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_MODEM_DIAG_EN_S  0
+
+/** HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RAM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x3c)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  hp_tcm clk gatig force on
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_ROM_PWR_CTRL0_REG register
+ *  NA
+ */
+#define HP_SYSTEM_ROM_PWR_CTRL0_REG (DR_REG_HP_SYS_BASE + 0x40)
+/** HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  hp_rom clk gating force on
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_M  (HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_V << HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_ROM_CLK_FORCE_ON_S  0
+
+/** HP_SYSTEM_PROBEA_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x50)
+/** HP_SYSTEM_REG_PROBE_A_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_A_MOD_SEL_V << HP_SYSTEM_REG_PROBE_A_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_A_MOD_SEL_S  0
+/** HP_SYSTEM_REG_PROBE_A_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+ */
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_A_TOP_SEL_V << HP_SYSTEM_REG_PROBE_A_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_A_TOP_SEL_S  16
+/** HP_SYSTEM_REG_PROBE_L_SEL : R/W; bitpos: [25:24]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_L_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_M  (HP_SYSTEM_REG_PROBE_L_SEL_V << HP_SYSTEM_REG_PROBE_L_SEL_S)
+#define HP_SYSTEM_REG_PROBE_L_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_L_SEL_S  24
+/** HP_SYSTEM_REG_PROBE_H_SEL : R/W; bitpos: [27:26]; default: 0;
+ *  This field is used to selec probe_out[31:16]
+ */
+#define HP_SYSTEM_REG_PROBE_H_SEL    0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_M  (HP_SYSTEM_REG_PROBE_H_SEL_V << HP_SYSTEM_REG_PROBE_H_SEL_S)
+#define HP_SYSTEM_REG_PROBE_H_SEL_V  0x00000003U
+#define HP_SYSTEM_REG_PROBE_H_SEL_S  26
+/** HP_SYSTEM_REG_PROBE_GLOBAL_EN : R/W; bitpos: [28]; default: 0;
+ *  Set this bit to enable global debug probe in hp system.
+ */
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN    (BIT(28))
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_M  (HP_SYSTEM_REG_PROBE_GLOBAL_EN_V << HP_SYSTEM_REG_PROBE_GLOBAL_EN_S)
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_GLOBAL_EN_S  28
+
+/** HP_SYSTEM_PROBEB_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBEB_CTRL_REG (DR_REG_HP_SYS_BASE + 0x54)
+/** HP_SYSTEM_REG_PROBE_B_MOD_SEL : R/W; bitpos: [15:0]; default: 0;
+ *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+ *  module's probe_out[31:0] in b mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL    0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_M  (HP_SYSTEM_REG_PROBE_B_MOD_SEL_V << HP_SYSTEM_REG_PROBE_B_MOD_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_V  0x0000FFFFU
+#define HP_SYSTEM_REG_PROBE_B_MOD_SEL_S  0
+/** HP_SYSTEM_REG_PROBE_B_TOP_SEL : R/W; bitpos: [23:16]; default: 0;
+ *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+ */
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL    0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_M  (HP_SYSTEM_REG_PROBE_B_TOP_SEL_V << HP_SYSTEM_REG_PROBE_B_TOP_SEL_S)
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_V  0x000000FFU
+#define HP_SYSTEM_REG_PROBE_B_TOP_SEL_S  16
+/** HP_SYSTEM_REG_PROBE_B_EN : R/W; bitpos: [24]; default: 0;
+ *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+ */
+#define HP_SYSTEM_REG_PROBE_B_EN    (BIT(24))
+#define HP_SYSTEM_REG_PROBE_B_EN_M  (HP_SYSTEM_REG_PROBE_B_EN_V << HP_SYSTEM_REG_PROBE_B_EN_S)
+#define HP_SYSTEM_REG_PROBE_B_EN_V  0x00000001U
+#define HP_SYSTEM_REG_PROBE_B_EN_S  24
+
+/** HP_SYSTEM_PROBE_OUT_REG register
+ *  NA
+ */
+#define HP_SYSTEM_PROBE_OUT_REG (DR_REG_HP_SYS_BASE + 0x5c)
+/** HP_SYSTEM_REG_PROBE_TOP_OUT : RO; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_PROBE_TOP_OUT    0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_M  (HP_SYSTEM_REG_PROBE_TOP_OUT_V << HP_SYSTEM_REG_PROBE_TOP_OUT_S)
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_PROBE_TOP_OUT_S  0
+
+/** HP_SYSTEM_CPU_CORESTALLED_ST_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CPU_CORESTALLED_ST_REG (DR_REG_HP_SYS_BASE + 0x64)
+/** HP_SYSTEM_REG_CORE0_CORESTALLED_ST : RO; bitpos: [0]; default: 0;
+ *  hp core0 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST    (BIT(0))
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE0_CORESTALLED_ST_S  0
+/** HP_SYSTEM_REG_CORE1_CORESTALLED_ST : RO; bitpos: [1]; default: 0;
+ *  hp core1 corestalled status
+ */
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST    (BIT(1))
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_M  (HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V << HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S)
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_V  0x00000001U
+#define HP_SYSTEM_REG_CORE1_CORESTALLED_ST_S  1
+
+/** HP_SYSTEM_CRYPTO_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CRYPTO_CTRL_REG (DR_REG_HP_SYS_BASE + 0x70)
+/** HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** HP_SYSTEM_IOMUX_FPGA_DEBUG_REG register
+ *  NA
+ */
+#define HP_SYSTEM_IOMUX_FPGA_DEBUG_REG (DR_REG_HP_SYS_BASE + 0x7c)
+/** HP_SYSTEM_REG_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
+ *  iomux fpga debug
+ */
+#define HP_SYSTEM_REG_FPGA_DEBUG    (BIT(0))
+#define HP_SYSTEM_REG_FPGA_DEBUG_M  (HP_SYSTEM_REG_FPGA_DEBUG_V << HP_SYSTEM_REG_FPGA_DEBUG_S)
+#define HP_SYSTEM_REG_FPGA_DEBUG_V  0x00000001U
+#define HP_SYSTEM_REG_FPGA_DEBUG_S  0
+
+/** HP_SYSTEM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0x80)
+/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_EN_S  0
+/** HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_RDN_ECO_RESULT_S  1
+
+/** HP_SYSTEM_TCM_RDN_ECO_CS_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_CS_REG (DR_REG_HP_SYS_BASE + 0xe4)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN    (BIT(0))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_EN_S  0
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT    (BIT(1))
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_V  0x00000001U
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_RESULT_S  1
+
+/** HP_SYSTEM_TCM_RDN_ECO_LOW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_LOW_REG (DR_REG_HP_SYS_BASE + 0xe8)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW : R/W; bitpos: [31:0]; default: 0;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_LOW_S  0
+
+/** HP_SYSTEM_TCM_RDN_ECO_HIGH_REG register
+ *  NA
+ */
+#define HP_SYSTEM_TCM_RDN_ECO_HIGH_REG (DR_REG_HP_SYS_BASE + 0xec)
+/** HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH : R/W; bitpos: [31:0]; default: 4294967295;
+ *  NA
+ */
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH    0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_M  (HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V << HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S)
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_V  0xFFFFFFFFU
+#define HP_SYSTEM_REG_HP_SYSTEM_TCM_RDN_ECO_HIGH_S  0
+
+/** HP_SYSTEM_CACHE_PWR_CTRL_REG register
+ *  NA
+ */
+#define HP_SYSTEM_CACHE_PWR_CTRL_REG (DR_REG_HP_SYS_BASE + 0x110)
+/** HP_SYSTEM_REG_AC_MEM_FO : R/W; bitpos: [7:0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_AC_MEM_FO    0x000000FFU
+#define HP_SYSTEM_REG_AC_MEM_FO_M  (HP_SYSTEM_REG_AC_MEM_FO_V << HP_SYSTEM_REG_AC_MEM_FO_S)
+#define HP_SYSTEM_REG_AC_MEM_FO_V  0x000000FFU
+#define HP_SYSTEM_REG_AC_MEM_FO_S  0
+/** HP_SYSTEM_REG_IC_MEM_FO : R/W; bitpos: [15:8]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_IC_MEM_FO    0x000000FFU
+#define HP_SYSTEM_REG_IC_MEM_FO_M  (HP_SYSTEM_REG_IC_MEM_FO_V << HP_SYSTEM_REG_IC_MEM_FO_S)
+#define HP_SYSTEM_REG_IC_MEM_FO_V  0x000000FFU
+#define HP_SYSTEM_REG_IC_MEM_FO_S  8
+/** HP_SYSTEM_REG_DC_MEM_FO : R/W; bitpos: [23:16]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_REG_DC_MEM_FO    0x000000FFU
+#define HP_SYSTEM_REG_DC_MEM_FO_M  (HP_SYSTEM_REG_DC_MEM_FO_V << HP_SYSTEM_REG_DC_MEM_FO_S)
+#define HP_SYSTEM_REG_DC_MEM_FO_V  0x000000FFU
+#define HP_SYSTEM_REG_DC_MEM_FO_S  16
+
+/** HP_SYSTEM_TCM_DATA_DUMP_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_DATA_DUMP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x114)
+/** HP_SYSTEM_TCM_DATA_DUMP_EN : R/W; bitpos: [31:0]; default: 0;
+ *  hp tcm_data dump switch
+ */
+#define HP_SYSTEM_TCM_DATA_DUMP_EN    0xFFFFFFFFU
+#define HP_SYSTEM_TCM_DATA_DUMP_EN_M  (HP_SYSTEM_TCM_DATA_DUMP_EN_V << HP_SYSTEM_TCM_DATA_DUMP_EN_S)
+#define HP_SYSTEM_TCM_DATA_DUMP_EN_V  0xFFFFFFFFU
+#define HP_SYSTEM_TCM_DATA_DUMP_EN_S  0
+
+/** HP_SYSTEM_CPU_WAITI_CONF_REG register
+ *  CPU_WAITI configuration register
+ */
+#define HP_SYSTEM_CPU_WAITI_CONF_REG (DR_REG_HP_SYS_BASE + 0x118)
+/** HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ *  Set 1 to force cpu_waiti_clk enable.
+ */
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  0
+/** HP_SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [4:1]; default: 0;
+ *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+ *  will close
+ */
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_M  (HP_SYSTEM_CPU_WAITI_DELAY_NUM_V << HP_SYSTEM_CPU_WAITI_DELAY_NUM_S)
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define HP_SYSTEM_CPU_WAITI_DELAY_NUM_S  1
+
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
+ *  Core Debug runstall configure register
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYS_BASE + 0x11c)
+/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+ */
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE    (BIT(0))
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_M  (HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V << HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S)
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_V  0x00000001U
+#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_ENABLE_S  0
+
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_CONF_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x124)
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 ibus timeout handle
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_PROTECT_EN_S  0
+/** HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 ibus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_IBUS_TIMEOUT_THRES_S  1
+
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_CONF_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x128)
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN : R/W; bitpos: [0]; default: 1;
+ *  set this field to 1 to enable hp core0&1 dbus timeout handle
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN    (BIT(0))
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_PROTECT_EN_S  0
+/** HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES : R/W; bitpos: [16:1]; default: 65535;
+ *  This field used to set hp core0&1 dbus timeout  threshold
+ */
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_M  (HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V << HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CORE_DBUS_TIMEOUT_THRES_S  1
+
+/** HP_SYSTEM_ICM_H2X_CFG_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_ICM_H2X_CFG_REG (DR_REG_HP_SYS_BASE + 0x138)
+/** HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN : R/W; bitpos: [0]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN    (BIT(0))
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_POST_WR_EN_S  0
+/** HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [1]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN    (BIT(1))
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S)
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_CUT_THROUGH_EN_S  1
+/** HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [2]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY    (BIT(2))
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRIDGE_BUSY_S  2
+/** HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN : R/W; bitpos: [3]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN    (BIT(3))
+#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_M  (HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_V << HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_POST_WR_EN_S  3
+/** HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN : R/W; bitpos: [4]; default: 1;
+ *  need_des
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN    (BIT(4))
+#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_M  (HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_V << HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_CUT_THROUGH_EN_S  4
+/** HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY : RO; bitpos: [5]; default: 0;
+ *  need_des
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY    (BIT(5))
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_V << HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRIDGE_BUSY_S  5
+
+/** HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG register
+ *  Bitscrambler Peri Sel
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_SEL_REG (DR_REG_HP_SYS_BASE + 0x140)
+/** HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL : R/W; bitpos: [4:0]; default: 0;
+ *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler:
+ *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
+ *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
+ *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
+ *  5'h11, none: else.
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL    0x0000001FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_V  0x0000001FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_RX_SEL_S  0
+/** HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL : R/W; bitpos: [9:5]; default: 0;
+ *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler:
+ *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
+ *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
+ *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
+ *  5'h11, none: else.
+ */
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL    0x0000001FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_M  (HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V << HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S)
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_V  0x0000001FU
+#define HP_SYSTEM_BITSCRAMBLER_PERI_TX_SEL_S  5
+
+/** HP_SYSTEM_GDMA_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_GDMA_CTRL_REG (DR_REG_HP_SYS_BASE + 0x148)
+/** HP_SYSTEM_DEBUG_CH_NUM : R/W; bitpos: [1:0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_DEBUG_CH_NUM    0x00000003U
+#define HP_SYSTEM_DEBUG_CH_NUM_M  (HP_SYSTEM_DEBUG_CH_NUM_V << HP_SYSTEM_DEBUG_CH_NUM_S)
+#define HP_SYSTEM_DEBUG_CH_NUM_V  0x00000003U
+#define HP_SYSTEM_DEBUG_CH_NUM_S  0
+
+/** HP_SYSTEM_VPU_CTRL_REG register
+ *  N/A
+ */
+#define HP_SYSTEM_VPU_CTRL_REG (DR_REG_HP_SYS_BASE + 0x158)
+/** HP_SYSTEM_PPA_LSLP_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_PPA_LSLP_MEM_PD    (BIT(0))
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_M  (HP_SYSTEM_PPA_LSLP_MEM_PD_V << HP_SYSTEM_PPA_LSLP_MEM_PD_S)
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_PPA_LSLP_MEM_PD_S  0
+/** HP_SYSTEM_JPEG_SDSLP_MEM_PD : R/W; bitpos: [1]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD    (BIT(1))
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_M  (HP_SYSTEM_JPEG_SDSLP_MEM_PD_V << HP_SYSTEM_JPEG_SDSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_SDSLP_MEM_PD_S  1
+/** HP_SYSTEM_JPEG_LSLP_MEM_PD : R/W; bitpos: [2]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD    (BIT(2))
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_M  (HP_SYSTEM_JPEG_LSLP_MEM_PD_V << HP_SYSTEM_JPEG_LSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_LSLP_MEM_PD_S  2
+/** HP_SYSTEM_JPEG_DSLP_MEM_PD : R/W; bitpos: [3]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD    (BIT(3))
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_M  (HP_SYSTEM_JPEG_DSLP_MEM_PD_V << HP_SYSTEM_JPEG_DSLP_MEM_PD_S)
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_JPEG_DSLP_MEM_PD_S  3
+/** HP_SYSTEM_DMA2D_LSLP_MEM_PD : R/W; bitpos: [4]; default: 0;
+ *  N/A
+ */
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD    (BIT(4))
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_M  (HP_SYSTEM_DMA2D_LSLP_MEM_PD_V << HP_SYSTEM_DMA2D_LSLP_MEM_PD_S)
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_V  0x00000001U
+#define HP_SYSTEM_DMA2D_LSLP_MEM_PD_S  4
+
+/** HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION0_REG (DR_REG_HP_SYS_BASE + 0x170)
+/** HP_SYSTEM_DFV0 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV0    0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_M  (HP_SYSTEM_DFV0_V << HP_SYSTEM_DFV0_S)
+#define HP_SYSTEM_DFV0_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV0_S  0
+
+/** HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_DESIGN_FOR_VERIFICATION1_REG (DR_REG_HP_SYS_BASE + 0x174)
+/** HP_SYSTEM_DFV1 : R/W; bitpos: [31:0]; default: 0;
+ *  register for DV
+ */
+#define HP_SYSTEM_DFV1    0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_M  (HP_SYSTEM_DFV1_V << HP_SYSTEM_DFV1_S)
+#define HP_SYSTEM_DFV1_V  0xFFFFFFFFU
+#define HP_SYSTEM_DFV1_S  0
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG register
+ *  NA
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x188)
+/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
+ *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+ *  post write mode in ahb2axi.
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(30))
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_RAW_S  30
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
+ *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+ *  post write mode in ahb2axi.
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_RAW_S  31
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x18c)
+/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [30]; default: 0;
+ *  the masked interrupt status of  sdmmc_icm_h2x_bresp_err
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST    (BIT(30))
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ST_S  30
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST : RO; bitpos: [31]; default: 0;
+ *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ST_S  31
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x190)
+/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [30]; default: 0;
+ *  Write 1 to enable sdmmc_icm_h2x_bresp_err int
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(30))
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_ENA_S  30
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA : R/W; bitpos: [31]; default: 0;
+ *  Write 1 to enable cpu_icm_h2x_bresp_err int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_ENA_S  31
+
+/** HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_AHB2AXI_BRESP_ERR_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x194)
+/** HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [30]; default: 0;
+ *  Write 1 to clear sdmmc_icm_h2x_bresp_err  int
+ */
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(30))
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_S)
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_SDMMC_ICM_H2X_BRESP_ERR_INT_CLR_S  30
+/** HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR : WT; bitpos: [31]; default: 0;
+ *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+ */
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR    (BIT(31))
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_M  (HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V << HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S)
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_ICM_H2X_BRESP_ERR_INT_CLR_S  31
+
+/** HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_REG (DR_REG_HP_SYS_BASE + 0x1a0)
+/** HP_SYSTEM_CORE_DMACTIVE_LPCORE : RO; bitpos: [0]; default: 0;
+ *  hp core dmactive_lpcore value
+ */
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE    (BIT(0))
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_M  (HP_SYSTEM_CORE_DMACTIVE_LPCORE_V << HP_SYSTEM_CORE_DMACTIVE_LPCORE_S)
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_V  0x00000001U
+#define HP_SYSTEM_CORE_DMACTIVE_LPCORE_S  0
+
+/** HP_SYSTEM_CORE_ERR_RESP_DIS_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_REG (DR_REG_HP_SYS_BASE + 0x1a4)
+/** HP_SYSTEM_CORE_ERR_RESP_DIS : R/W; bitpos: [2:0]; default: 0;
+ *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+ *  disable ahb err resp.
+ */
+#define HP_SYSTEM_CORE_ERR_RESP_DIS    0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_M  (HP_SYSTEM_CORE_ERR_RESP_DIS_V << HP_SYSTEM_CORE_ERR_RESP_DIS_S)
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_V  0x00000007U
+#define HP_SYSTEM_CORE_ERR_RESP_DIS_S  0
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG register
+ *  Hp core bus timeout interrupt raw register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x1a8)
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  the raw interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_RAW_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
+ *  the raw interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_RAW_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  the raw interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_RAW_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  the raw interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_RAW_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x1ac)
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  the masked interrupt status of hp core0  ibus timeout
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ST_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  the masked interrupt status of hp core1  ibus timeout
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ST_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST : RO; bitpos: [4]; default: 0;
+ *  the masked interrupt status of hp core0  dbus timeout
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ST_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST : RO; bitpos: [5]; default: 0;
+ *  the masked interrupt status of hp core1  dbus timeout
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ST_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x1b0)
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_ENA_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_ENA_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_ENA_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_ENA_S  5
+
+/** HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_CORE_TIMEOUT_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x1b4)
+/** HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear hp_core0_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR    (BIT(2))
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_IBUS_TIMEOUT_INT_CLR_S  2
+/** HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear hp_core1_ibus_timeout int
+ */
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR    (BIT(3))
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_IBUS_TIMEOUT_INT_CLR_S  3
+/** HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear hp_core0_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR    (BIT(4))
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE0_DBUS_TIMEOUT_INT_CLR_S  4
+/** HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear hp_core1_dbus_timeout int
+ */
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR    (BIT(5))
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V << HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CORE1_DBUS_TIMEOUT_INT_CLR_S  5
+
+/** HP_SYSTEM_CORE_PAD_WAKEUP_EVENT_REG register
+ *  pad wakeup event register
+ */
+#define HP_SYSTEM_CORE_PAD_WAKEUP_EVENT_REG (DR_REG_HP_SYS_BASE + 0x1b8)
+/** HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT : R/W; bitpos: [0]; default: 0;
+ *  wakeup core0 register
+ */
+#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT    (BIT(0))
+#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_M  (HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_V << HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE0_PAD_WAKEUP_EVENT_S  0
+/** HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT : R/W; bitpos: [1]; default: 0;
+ *  wakeup core1 register
+ */
+#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT    (BIT(1))
+#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_M  (HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_V << HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_S)
+#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_V  0x00000001U
+#define HP_SYSTEM_CORE1_PAD_WAKEUP_EVENT_S  1
+
+/** HP_SYSTEM_TWAI0_TIMESTAMP_L_REG register
+ *  twai0 timestamp low bit reg
+ */
+#define HP_SYSTEM_TWAI0_TIMESTAMP_L_REG (DR_REG_HP_SYS_BASE + 0x1c0)
+/** HP_SYSTEM_TWAI0_TIMESTAMP_I : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This field used to set lower 32bits of timestamp hp twai0
+ */
+#define HP_SYSTEM_TWAI0_TIMESTAMP_I    0xFFFFFFFFU
+#define HP_SYSTEM_TWAI0_TIMESTAMP_I_M  (HP_SYSTEM_TWAI0_TIMESTAMP_I_V << HP_SYSTEM_TWAI0_TIMESTAMP_I_S)
+#define HP_SYSTEM_TWAI0_TIMESTAMP_I_V  0xFFFFFFFFU
+#define HP_SYSTEM_TWAI0_TIMESTAMP_I_S  0
+
+/** HP_SYSTEM_TWAI0_TIMESTAMP_H_REG register
+ *  twai0 timestamp high bit reg
+ */
+#define HP_SYSTEM_TWAI0_TIMESTAMP_H_REG (DR_REG_HP_SYS_BASE + 0x1c4)
+/** HP_SYSTEM_TWAI0_TIMESTAMP_H : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This field used to set upper 32bits of timestamp hp twai0
+ */
+#define HP_SYSTEM_TWAI0_TIMESTAMP_H    0xFFFFFFFFU
+#define HP_SYSTEM_TWAI0_TIMESTAMP_H_M  (HP_SYSTEM_TWAI0_TIMESTAMP_H_V << HP_SYSTEM_TWAI0_TIMESTAMP_H_S)
+#define HP_SYSTEM_TWAI0_TIMESTAMP_H_V  0xFFFFFFFFU
+#define HP_SYSTEM_TWAI0_TIMESTAMP_H_S  0
+
+/** HP_SYSTEM_TWAI1_TIMESTAMP_L_REG register
+ *  twai1 timestamp low bit reg
+ */
+#define HP_SYSTEM_TWAI1_TIMESTAMP_L_REG (DR_REG_HP_SYS_BASE + 0x1c8)
+/** HP_SYSTEM_TWAI1_TIMESTAMP_I : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This field used to set lower 32bits of timestamp hp twai1
+ */
+#define HP_SYSTEM_TWAI1_TIMESTAMP_I    0xFFFFFFFFU
+#define HP_SYSTEM_TWAI1_TIMESTAMP_I_M  (HP_SYSTEM_TWAI1_TIMESTAMP_I_V << HP_SYSTEM_TWAI1_TIMESTAMP_I_S)
+#define HP_SYSTEM_TWAI1_TIMESTAMP_I_V  0xFFFFFFFFU
+#define HP_SYSTEM_TWAI1_TIMESTAMP_I_S  0
+
+/** HP_SYSTEM_TWAI1_TIMESTAMP_H_REG register
+ *  twai1 timestamp high bit reg
+ */
+#define HP_SYSTEM_TWAI1_TIMESTAMP_H_REG (DR_REG_HP_SYS_BASE + 0x1cc)
+/** HP_SYSTEM_TWAI1_TIMESTAMP_H : R/W; bitpos: [31:0]; default: 4294967295;
+ *  This field used to set upper 32bits of timestamp hp twai1
+ */
+#define HP_SYSTEM_TWAI1_TIMESTAMP_H    0xFFFFFFFFU
+#define HP_SYSTEM_TWAI1_TIMESTAMP_H_M  (HP_SYSTEM_TWAI1_TIMESTAMP_H_V << HP_SYSTEM_TWAI1_TIMESTAMP_H_S)
+#define HP_SYSTEM_TWAI1_TIMESTAMP_H_V  0xFFFFFFFFU
+#define HP_SYSTEM_TWAI1_TIMESTAMP_H_S  0
+
+/** HP_SYSTEM_RNG_CFG_REG register
+ *  rng cfg register
+ */
+#define HP_SYSTEM_RNG_CFG_REG (DR_REG_HP_SYS_BASE + 0x1d8)
+/** HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM : R/W; bitpos: [23:16]; default: 0;
+ *  chain clk div num to pad for debug
+ */
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM    0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_M  (HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V << HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S)
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_V  0x000000FFU
+#define HP_SYSTEM_RNG_CHAIN_CLK_DIV_NUM_S  16
+
+/** HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG register
+ *  hp peri mem clk force on regpster
+ */
+#define HP_SYSTEM_PERI_MEM_CLK_FORCE_ON_REG (DR_REG_HP_SYS_BASE + 0x1e0)
+/** HP_SYSTEM_RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force on mem clk in rmt
+ */
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON    (BIT(0))
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V << HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_CLK_FORCE_ON_S  0
+/** HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to force on tx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON    (BIT(1))
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_TX_MEM_CLK_FORCE_ON_S  1
+/** HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force on rx mem clk in bitscrambler
+ */
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON    (BIT(2))
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V << HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_RX_MEM_CLK_FORCE_ON_S  2
+/** HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force on mem clk in gdma
+ */
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON    (BIT(3))
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_M  (HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V << HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S)
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_V  0x00000001U
+#define HP_SYSTEM_GDMA_MEM_CLK_FORCE_ON_S  3
+
+/** HP_SYSTEM_PRDYN_ST_REG register
+ *  hp system prdyn status register
+ */
+#define HP_SYSTEM_PRDYN_ST_REG (DR_REG_HP_SYS_BASE + 0x1e8)
+/** HP_SYSTEM_ROM_PRDYN : RO; bitpos: [1]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_ROM_PRDYN    (BIT(1))
+#define HP_SYSTEM_ROM_PRDYN_M  (HP_SYSTEM_ROM_PRDYN_V << HP_SYSTEM_ROM_PRDYN_S)
+#define HP_SYSTEM_ROM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_ROM_PRDYN_S  1
+/** HP_SYSTEM_CPU_MEM_PRDYN : RO; bitpos: [3]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_CPU_MEM_PRDYN    (BIT(3))
+#define HP_SYSTEM_CPU_MEM_PRDYN_M  (HP_SYSTEM_CPU_MEM_PRDYN_V << HP_SYSTEM_CPU_MEM_PRDYN_S)
+#define HP_SYSTEM_CPU_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_CPU_MEM_PRDYN_S  3
+/** HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN : RO; bitpos: [4]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN    (BIT(4))
+#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_M  (HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_V << HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_S)
+#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_BITSCRAMBLER_MEM_PRDYN_S  4
+/** HP_SYSTEM_USB_MEM_PRDYN : RO; bitpos: [6]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_USB_MEM_PRDYN    (BIT(6))
+#define HP_SYSTEM_USB_MEM_PRDYN_M  (HP_SYSTEM_USB_MEM_PRDYN_V << HP_SYSTEM_USB_MEM_PRDYN_S)
+#define HP_SYSTEM_USB_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_USB_MEM_PRDYN_S  6
+/** HP_SYSTEM_RMT_MEM_PRDYN : RO; bitpos: [7]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_RMT_MEM_PRDYN    (BIT(7))
+#define HP_SYSTEM_RMT_MEM_PRDYN_M  (HP_SYSTEM_RMT_MEM_PRDYN_V << HP_SYSTEM_RMT_MEM_PRDYN_S)
+#define HP_SYSTEM_RMT_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_PRDYN_S  7
+/** HP_SYSTEM_LEDC0_MEM_PRDYN : RO; bitpos: [8]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_LEDC0_MEM_PRDYN    (BIT(8))
+#define HP_SYSTEM_LEDC0_MEM_PRDYN_M  (HP_SYSTEM_LEDC0_MEM_PRDYN_V << HP_SYSTEM_LEDC0_MEM_PRDYN_S)
+#define HP_SYSTEM_LEDC0_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_LEDC0_MEM_PRDYN_S  8
+/** HP_SYSTEM_KEY_MANAGER_MEM_PRDYN : RO; bitpos: [9]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN    (BIT(9))
+#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_M  (HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_V << HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_S)
+#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_KEY_MANAGER_MEM_PRDYN_S  9
+/** HP_SYSTEM_VPU_MEM_PRDYN : RO; bitpos: [10]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_VPU_MEM_PRDYN    (BIT(10))
+#define HP_SYSTEM_VPU_MEM_PRDYN_M  (HP_SYSTEM_VPU_MEM_PRDYN_V << HP_SYSTEM_VPU_MEM_PRDYN_S)
+#define HP_SYSTEM_VPU_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_VPU_MEM_PRDYN_S  10
+/** HP_SYSTEM_GDMA_MEM_PRDYN : RO; bitpos: [12]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_GDMA_MEM_PRDYN    (BIT(12))
+#define HP_SYSTEM_GDMA_MEM_PRDYN_M  (HP_SYSTEM_GDMA_MEM_PRDYN_V << HP_SYSTEM_GDMA_MEM_PRDYN_S)
+#define HP_SYSTEM_GDMA_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_GDMA_MEM_PRDYN_S  12
+/** HP_SYSTEM_UART_MEM_PRDYN : RO; bitpos: [14]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_UART_MEM_PRDYN    (BIT(14))
+#define HP_SYSTEM_UART_MEM_PRDYN_M  (HP_SYSTEM_UART_MEM_PRDYN_V << HP_SYSTEM_UART_MEM_PRDYN_S)
+#define HP_SYSTEM_UART_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_UART_MEM_PRDYN_S  14
+/** HP_SYSTEM_CRYPTO_MEM_PRDYN : RO; bitpos: [15]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_CRYPTO_MEM_PRDYN    (BIT(15))
+#define HP_SYSTEM_CRYPTO_MEM_PRDYN_M  (HP_SYSTEM_CRYPTO_MEM_PRDYN_V << HP_SYSTEM_CRYPTO_MEM_PRDYN_S)
+#define HP_SYSTEM_CRYPTO_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_CRYPTO_MEM_PRDYN_S  15
+/** HP_SYSTEM_FLASH_MSPI_MEM_PRDYN : RO; bitpos: [16]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN    (BIT(16))
+#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_M  (HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_V << HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_S)
+#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_FLASH_MSPI_MEM_PRDYN_S  16
+/** HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN : RO; bitpos: [17]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN    (BIT(17))
+#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_M  (HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_V << HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_S)
+#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_PSRAM_MSPI_MEM_PRDYN_S  17
+/** HP_SYSTEM_MODEM_MEM_PRDYN : RO; bitpos: [18]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_MODEM_MEM_PRDYN    (BIT(18))
+#define HP_SYSTEM_MODEM_MEM_PRDYN_M  (HP_SYSTEM_MODEM_MEM_PRDYN_V << HP_SYSTEM_MODEM_MEM_PRDYN_S)
+#define HP_SYSTEM_MODEM_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_MODEM_MEM_PRDYN_S  18
+/** HP_SYSTEM_LEDC1_MEM_PRDYN : RO; bitpos: [19]; default: 1;
+ *  record memory power status
+ */
+#define HP_SYSTEM_LEDC1_MEM_PRDYN    (BIT(19))
+#define HP_SYSTEM_LEDC1_MEM_PRDYN_M  (HP_SYSTEM_LEDC1_MEM_PRDYN_V << HP_SYSTEM_LEDC1_MEM_PRDYN_S)
+#define HP_SYSTEM_LEDC1_MEM_PRDYN_V  0x00000001U
+#define HP_SYSTEM_LEDC1_MEM_PRDYN_S  19
+
+/** HP_SYSTEM_ICM_CFG_REG register
+ *  hp system axi icm ctrl register
+ */
+#define HP_SYSTEM_ICM_CFG_REG (DR_REG_HP_SYS_BASE + 0x1ec)
+/** HP_SYSTEM_ICM_DIS_RD : R/W; bitpos: [2:0]; default: 0;
+ *  0:mean master can access slave , 1:mean master can not rd slave ,will returen
+ *  decerro on axi bus
+ */
+#define HP_SYSTEM_ICM_DIS_RD    0x00000007U
+#define HP_SYSTEM_ICM_DIS_RD_M  (HP_SYSTEM_ICM_DIS_RD_V << HP_SYSTEM_ICM_DIS_RD_S)
+#define HP_SYSTEM_ICM_DIS_RD_V  0x00000007U
+#define HP_SYSTEM_ICM_DIS_RD_S  0
+/** HP_SYSTEM_ICM_DIS_WR : R/W; bitpos: [5:3]; default: 0;
+ *  0:mean master can access slave , 1:mean master can not wr slave ,will returen
+ *  decerro on axi bus
+ */
+#define HP_SYSTEM_ICM_DIS_WR    0x00000007U
+#define HP_SYSTEM_ICM_DIS_WR_M  (HP_SYSTEM_ICM_DIS_WR_V << HP_SYSTEM_ICM_DIS_WR_S)
+#define HP_SYSTEM_ICM_DIS_WR_V  0x00000007U
+#define HP_SYSTEM_ICM_DIS_WR_S  3
+/** HP_SYSTEM_ICM_CFG_SECURE : R/W; bitpos: [8:6]; default: 0;
+ *  axi_matrix slave ,0: non-secure, 1: secure , total 3 slave.
+ */
+#define HP_SYSTEM_ICM_CFG_SECURE    0x00000007U
+#define HP_SYSTEM_ICM_CFG_SECURE_M  (HP_SYSTEM_ICM_CFG_SECURE_V << HP_SYSTEM_ICM_CFG_SECURE_S)
+#define HP_SYSTEM_ICM_CFG_SECURE_V  0x00000007U
+#define HP_SYSTEM_ICM_CFG_SECURE_S  6
+
+/** HP_SYSTEM_UART3_MEM_LP_CTRL_REG register
+ *  uart memory power control register
+ */
+#define HP_SYSTEM_UART3_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x1f0)
+/** HP_SYSTEM_UART3_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures uart3 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_UART3_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_UART3_MEM_LP_MODE_M  (HP_SYSTEM_UART3_MEM_LP_MODE_V << HP_SYSTEM_UART3_MEM_LP_MODE_S)
+#define HP_SYSTEM_UART3_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_UART3_MEM_LP_MODE_S  0
+/** HP_SYSTEM_UART3_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down uart3 memory.
+ */
+#define HP_SYSTEM_UART3_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_UART3_MEM_LP_EN_M  (HP_SYSTEM_UART3_MEM_LP_EN_V << HP_SYSTEM_UART3_MEM_LP_EN_S)
+#define HP_SYSTEM_UART3_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_UART3_MEM_LP_EN_S  2
+/** HP_SYSTEM_UART3_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control uart3 memory, disable hardware control.
+ */
+#define HP_SYSTEM_UART3_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART3_MEM_FORCE_CTRL_V << HP_SYSTEM_UART3_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_UART3_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_RMT_MEM_LP_CTRL_REG register
+ *  rmt memory power control register
+ */
+#define HP_SYSTEM_RMT_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x204)
+/** HP_SYSTEM_RMT_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures rmt memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_RMT_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_RMT_MEM_LP_MODE_M  (HP_SYSTEM_RMT_MEM_LP_MODE_V << HP_SYSTEM_RMT_MEM_LP_MODE_S)
+#define HP_SYSTEM_RMT_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_RMT_MEM_LP_MODE_S  0
+/** HP_SYSTEM_RMT_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down rmt memory.
+ */
+#define HP_SYSTEM_RMT_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_RMT_MEM_LP_EN_M  (HP_SYSTEM_RMT_MEM_LP_EN_V << HP_SYSTEM_RMT_MEM_LP_EN_S)
+#define HP_SYSTEM_RMT_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_LP_EN_S  2
+/** HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control rmt memory, disable hardware control.
+ */
+#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_RMT_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_LEDC0_MEM_LP_CTRL_REG register
+ *  ledc0 memory power control register
+ */
+#define HP_SYSTEM_LEDC0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x208)
+/** HP_SYSTEM_LEDC0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures ledc0 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_LEDC0_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_LEDC0_MEM_LP_MODE_M  (HP_SYSTEM_LEDC0_MEM_LP_MODE_V << HP_SYSTEM_LEDC0_MEM_LP_MODE_S)
+#define HP_SYSTEM_LEDC0_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_LEDC0_MEM_LP_MODE_S  0
+/** HP_SYSTEM_LEDC0_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down ledc0 memory.
+ */
+#define HP_SYSTEM_LEDC0_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_LEDC0_MEM_LP_EN_M  (HP_SYSTEM_LEDC0_MEM_LP_EN_V << HP_SYSTEM_LEDC0_MEM_LP_EN_S)
+#define HP_SYSTEM_LEDC0_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_LEDC0_MEM_LP_EN_S  2
+/** HP_SYSTEM_LEDC0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control ledc0 memory, disable hardware control.
+ */
+#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_M  (HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_V << HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_LEDC0_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_KM_MEM_LP_CTRL_REG register
+ *  key manager memory power control register
+ */
+#define HP_SYSTEM_KM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x20c)
+/** HP_SYSTEM_KM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures km memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_KM_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_KM_MEM_LP_MODE_M  (HP_SYSTEM_KM_MEM_LP_MODE_V << HP_SYSTEM_KM_MEM_LP_MODE_S)
+#define HP_SYSTEM_KM_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_KM_MEM_LP_MODE_S  0
+/** HP_SYSTEM_KM_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down km memory.
+ */
+#define HP_SYSTEM_KM_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_KM_MEM_LP_EN_M  (HP_SYSTEM_KM_MEM_LP_EN_V << HP_SYSTEM_KM_MEM_LP_EN_S)
+#define HP_SYSTEM_KM_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_KM_MEM_LP_EN_S  2
+/** HP_SYSTEM_KM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control km memory, disable hardware control.
+ */
+#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_KM_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_DMA2D_MEM_LP_CTRL_REG register
+ *  vpu memory power control register
+ */
+#define HP_SYSTEM_DMA2D_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x210)
+/** HP_SYSTEM_2DDMA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures 2ddma memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_2DDMA_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_2DDMA_MEM_LP_MODE_M  (HP_SYSTEM_2DDMA_MEM_LP_MODE_V << HP_SYSTEM_2DDMA_MEM_LP_MODE_S)
+#define HP_SYSTEM_2DDMA_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_2DDMA_MEM_LP_MODE_S  0
+/** HP_SYSTEM_2DDMA_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down 2ddma memory.
+ */
+#define HP_SYSTEM_2DDMA_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_2DDMA_MEM_LP_EN_M  (HP_SYSTEM_2DDMA_MEM_LP_EN_V << HP_SYSTEM_2DDMA_MEM_LP_EN_S)
+#define HP_SYSTEM_2DDMA_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_2DDMA_MEM_LP_EN_S  2
+/** HP_SYSTEM_2DDMA_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control 2ddma memory, disable hardware control.
+ */
+#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_M  (HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_V << HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_2DDMA_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_AXI_PDMA_MEM_LP_CTRL_REG register
+ *  vpu memory power control register
+ */
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x214)
+/** HP_SYSTEM_AXI_PDMA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures axi_pdma memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_V << HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_S)
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_MODE_S  0
+/** HP_SYSTEM_AXI_PDMA_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down axi_pdma memory.
+ */
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_EN_V << HP_SYSTEM_AXI_PDMA_MEM_LP_EN_S)
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_EN_S  2
+/** HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control axi_pdma memory, disable hardware control.
+ */
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_AXI_PDMA_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_ECC_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_ECC_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x218)
+/** HP_SYSTEM_ECC_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures ecc memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_ECC_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_ECC_MEM_LP_MODE_M  (HP_SYSTEM_ECC_MEM_LP_MODE_V << HP_SYSTEM_ECC_MEM_LP_MODE_S)
+#define HP_SYSTEM_ECC_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_ECC_MEM_LP_MODE_S  0
+/** HP_SYSTEM_ECC_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down ecc memory.
+ */
+#define HP_SYSTEM_ECC_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_ECC_MEM_LP_EN_M  (HP_SYSTEM_ECC_MEM_LP_EN_V << HP_SYSTEM_ECC_MEM_LP_EN_S)
+#define HP_SYSTEM_ECC_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_LP_EN_S  2
+/** HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control ecc memory, disable hardware control.
+ */
+#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_RSA_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_RSA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x21c)
+/** HP_SYSTEM_RSA_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures rsa memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_RSA_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_RSA_MEM_LP_MODE_M  (HP_SYSTEM_RSA_MEM_LP_MODE_V << HP_SYSTEM_RSA_MEM_LP_MODE_S)
+#define HP_SYSTEM_RSA_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_RSA_MEM_LP_MODE_S  0
+/** HP_SYSTEM_RSA_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down rsa memory.
+ */
+#define HP_SYSTEM_RSA_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_RSA_MEM_LP_EN_M  (HP_SYSTEM_RSA_MEM_LP_EN_V << HP_SYSTEM_RSA_MEM_LP_EN_S)
+#define HP_SYSTEM_RSA_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_LP_EN_S  2
+/** HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control rsa memory, disable hardware control.
+ */
+#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_RSA_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_BITSCRAM_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_BITSCRAM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x220)
+/** HP_SYSTEM_BITSCRAM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures bitscram memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_M  (HP_SYSTEM_BITSCRAM_MEM_LP_MODE_V << HP_SYSTEM_BITSCRAM_MEM_LP_MODE_S)
+#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_BITSCRAM_MEM_LP_MODE_S  0
+/** HP_SYSTEM_BITSCRAM_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down bitscram memory.
+ */
+#define HP_SYSTEM_BITSCRAM_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_M  (HP_SYSTEM_BITSCRAM_MEM_LP_EN_V << HP_SYSTEM_BITSCRAM_MEM_LP_EN_S)
+#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_BITSCRAM_MEM_LP_EN_S  2
+/** HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control bitscram memory, disable hardware control.
+ */
+#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_BITSCRAM_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_CAN0_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_CAN0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x228)
+/** HP_SYSTEM_CAN0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures can0 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_CAN0_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_CAN0_MEM_LP_MODE_M  (HP_SYSTEM_CAN0_MEM_LP_MODE_V << HP_SYSTEM_CAN0_MEM_LP_MODE_S)
+#define HP_SYSTEM_CAN0_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_CAN0_MEM_LP_MODE_S  0
+/** HP_SYSTEM_CAN0_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down can0 memory.
+ */
+#define HP_SYSTEM_CAN0_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_CAN0_MEM_LP_EN_M  (HP_SYSTEM_CAN0_MEM_LP_EN_V << HP_SYSTEM_CAN0_MEM_LP_EN_S)
+#define HP_SYSTEM_CAN0_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_CAN0_MEM_LP_EN_S  2
+/** HP_SYSTEM_CAN0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control can0 memory, disable hardware control.
+ */
+#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_M  (HP_SYSTEM_CAN0_MEM_FORCE_CTRL_V << HP_SYSTEM_CAN0_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_CAN0_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_MSPI_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_MSPI_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x234)
+/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures psram_mspi memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_S)
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_MODE_S  0
+/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down psram_mspi memory.
+ */
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_S)
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_EN_S  2
+/** HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control psram_mspi memory, disable hardware control.
+ */
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_PSRAM_MSPI_MEM_LP_FORCE_CTRL_S  3
+/** HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 2;
+ *  Configures flash_mspi memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_S)
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_MODE_S  4
+/** HP_SYSTEM_FLASH_MSPI_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to power down flash_mspi memory.
+ */
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN    (BIT(6))
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_S)
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_EN_S  6
+/** HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
+ *  Set this bit to force software control flash_mspi memory, disable hardware control.
+ */
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL    (BIT(7))
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_FLASH_MSPI_MEM_LP_FORCE_CTRL_S  7
+
+/** HP_SYSTEM_HPCORE_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_HPCORE_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x24c)
+/** HP_SYSTEM_HPCORE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures hpcore memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_HPCORE_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_HPCORE_MEM_LP_MODE_M  (HP_SYSTEM_HPCORE_MEM_LP_MODE_V << HP_SYSTEM_HPCORE_MEM_LP_MODE_S)
+#define HP_SYSTEM_HPCORE_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_HPCORE_MEM_LP_MODE_S  0
+/** HP_SYSTEM_HPCORE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down hpcore memory.
+ */
+#define HP_SYSTEM_HPCORE_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_HPCORE_MEM_LP_EN_M  (HP_SYSTEM_HPCORE_MEM_LP_EN_V << HP_SYSTEM_HPCORE_MEM_LP_EN_S)
+#define HP_SYSTEM_HPCORE_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_HPCORE_MEM_LP_EN_S  2
+/** HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control hpcore memory, disable hardware control.
+ */
+#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_HPCORE_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_ROM_MEM_LP_CTRL_REG register
+ *  rom power control register
+ */
+#define HP_SYSTEM_ROM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x250)
+/** HP_SYSTEM_ROM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures rom low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_ROM_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_MODE_M  (HP_SYSTEM_ROM_MEM_LP_MODE_V << HP_SYSTEM_ROM_MEM_LP_MODE_S)
+#define HP_SYSTEM_ROM_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_MODE_S  0
+/** HP_SYSTEM_ROM_MEM_LP_EN : R/W; bitpos: [3:2]; default: 0;
+ *  Set this bit to power down rom.
+ */
+#define HP_SYSTEM_ROM_MEM_LP_EN    0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_EN_M  (HP_SYSTEM_ROM_MEM_LP_EN_V << HP_SYSTEM_ROM_MEM_LP_EN_S)
+#define HP_SYSTEM_ROM_MEM_LP_EN_V  0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_EN_S  2
+/** HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL : R/W; bitpos: [5:4]; default: 0;
+ *  Set this bit to force software control rom, disable hardware control.
+ */
+#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL    0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_V  0x00000003U
+#define HP_SYSTEM_ROM_MEM_LP_FORCE_CTRL_S  4
+
+/** HP_SYSTEM_L1_CACHE_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_L1_CACHE_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x25c)
+/** HP_SYSTEM_L1_CACHE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures l1_cache memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_M  (HP_SYSTEM_L1_CACHE_MEM_LP_MODE_V << HP_SYSTEM_L1_CACHE_MEM_LP_MODE_S)
+#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_L1_CACHE_MEM_LP_MODE_S  0
+/** HP_SYSTEM_L1_CACHE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down l1_cache memory.
+ */
+#define HP_SYSTEM_L1_CACHE_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_M  (HP_SYSTEM_L1_CACHE_MEM_LP_EN_V << HP_SYSTEM_L1_CACHE_MEM_LP_EN_S)
+#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_L1_CACHE_MEM_LP_EN_S  2
+/** HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control l1_cache memory, disable hardware control.
+ */
+#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_L1_CACHE_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_KYBER_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_KYBER_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x260)
+/** HP_SYSTEM_KYBER_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures kyber memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_KYBER_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_KYBER_MEM_LP_MODE_M  (HP_SYSTEM_KYBER_MEM_LP_MODE_V << HP_SYSTEM_KYBER_MEM_LP_MODE_S)
+#define HP_SYSTEM_KYBER_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_KYBER_MEM_LP_MODE_S  0
+/** HP_SYSTEM_KYBER_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down kyber memory.
+ */
+#define HP_SYSTEM_KYBER_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_KYBER_MEM_LP_EN_M  (HP_SYSTEM_KYBER_MEM_LP_EN_V << HP_SYSTEM_KYBER_MEM_LP_EN_S)
+#define HP_SYSTEM_KYBER_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_KYBER_MEM_LP_EN_S  2
+/** HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control kyber memory, disable hardware control.
+ */
+#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_KYBER_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_LCDCAM_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_LCDCAM_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x264)
+/** HP_SYSTEM_LCDCAM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures lcdcam memory low power mode in low power stage.
+ *  0: deep sleep
+ *  1: light sleep
+ *  2(default): shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_LCDCAM_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_M  (HP_SYSTEM_LCDCAM_MEM_LP_MODE_V << HP_SYSTEM_LCDCAM_MEM_LP_MODE_S)
+#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_LCDCAM_MEM_LP_MODE_S  0
+/** HP_SYSTEM_LCDCAM_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down lcdcam memory.
+ */
+#define HP_SYSTEM_LCDCAM_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_LCDCAM_MEM_LP_EN_M  (HP_SYSTEM_LCDCAM_MEM_LP_EN_V << HP_SYSTEM_LCDCAM_MEM_LP_EN_S)
+#define HP_SYSTEM_LCDCAM_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_LCDCAM_MEM_LP_EN_S  2
+/** HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control lcdcam memory, disable hardware control.
+ */
+#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_M  (HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_V << HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_S)
+#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_LCDCAM_MEM_LP_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_CONF_REG register
+ *  CPU_PERI0_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x268)
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Configures the timeout threshold for bus access for accessing CPU peripheral0
+ *  register in the number of clock cycles of the clock domain.
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear timeout interrupt.
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR    (BIT(16))
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_INT_CLR_S  16
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Configures whether or not to enable timeout protection for accessing CPU
+ *  peripheral0 registers.
+ *  0: Disable
+ *  1: Enable
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_REG register
+ *  CPU_PERI0_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x26c)
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address information of abnormal access.
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_REG register
+ *  CPU_PERI0_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x270)
+/** HP_SYSTEM_CPU_PERI0_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
+ *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+ *  register will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID    0x000000FFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_S)
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_V  0x000000FFU
+#define HP_SYSTEM_CPU_PERI0_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_CONF_REG register
+ *  HP_SYSTEM_PERI0_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x274)
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Configures the timeout threshold for bus access for accessing CPU peripheral
+ *  register in the number of clock cycles of the clock domain.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear timeout interrupt.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR    (BIT(16))
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_INT_CLR_S  16
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Configures whether or not to enable timeout protection for accessing CPU peripheral
+ *  registers.
+ *  0: Disable
+ *  1: Enable
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_REG register
+ *  HP_SYSTEM_PERI0_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x278)
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address information of abnormal access.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_REG register
+ *  HP_SYSTEM_PERI0_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x27c)
+/** HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
+ *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+ *  register will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID    0x000000FFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_M  (HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_V << HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_V  0x000000FFU
+#define HP_SYSTEM_HP_SYSTEM_PERI0_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_CONF_REG register
+ *  HP_SYSTEM_PERI1_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x280)
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Configures the timeout threshold for bus access for accessing CPU peripheral
+ *  register in the number of clock cycles of the clock domain.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear timeout interrupt.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR    (BIT(16))
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_INT_CLR_S  16
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Configures whether or not to enable timeout protection for accessing CPU peripheral
+ *  registers.
+ *  0: Disable
+ *  1: Enable
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_REG register
+ *  HP_SYSTEM_PERI1_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x284)
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address information of abnormal access.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_REG register
+ *  HP_SYSTEM_PERI1_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x288)
+/** HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
+ *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+ *  register will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID    0x000000FFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_M  (HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_V << HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_S)
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_V  0x000000FFU
+#define HP_SYSTEM_HP_SYSTEM_PERI1_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_UART0_MEM_LP_CTRL_REG register
+ *  uart memory power control register
+ */
+#define HP_SYSTEM_UART0_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x28c)
+/** HP_SYSTEM_UART0_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
+ *  Configures uart0 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_UART0_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_UART0_MEM_LP_MODE_M  (HP_SYSTEM_UART0_MEM_LP_MODE_V << HP_SYSTEM_UART0_MEM_LP_MODE_S)
+#define HP_SYSTEM_UART0_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_UART0_MEM_LP_MODE_S  0
+/** HP_SYSTEM_UART0_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to power down uart0 memory.
+ */
+#define HP_SYSTEM_UART0_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_UART0_MEM_LP_EN_M  (HP_SYSTEM_UART0_MEM_LP_EN_V << HP_SYSTEM_UART0_MEM_LP_EN_S)
+#define HP_SYSTEM_UART0_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_UART0_MEM_LP_EN_S  2
+/** HP_SYSTEM_UART0_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control uart0 memory, disable hardware control.
+ */
+#define HP_SYSTEM_UART0_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART0_MEM_FORCE_CTRL_V << HP_SYSTEM_UART0_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_UART0_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_UART1_MEM_LP_CTRL_REG register
+ *  uart memory power control register
+ */
+#define HP_SYSTEM_UART1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x290)
+/** HP_SYSTEM_UART1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures uart1 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_UART1_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_UART1_MEM_LP_MODE_M  (HP_SYSTEM_UART1_MEM_LP_MODE_V << HP_SYSTEM_UART1_MEM_LP_MODE_S)
+#define HP_SYSTEM_UART1_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_UART1_MEM_LP_MODE_S  0
+/** HP_SYSTEM_UART1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down uart1 memory.
+ */
+#define HP_SYSTEM_UART1_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_UART1_MEM_LP_EN_M  (HP_SYSTEM_UART1_MEM_LP_EN_V << HP_SYSTEM_UART1_MEM_LP_EN_S)
+#define HP_SYSTEM_UART1_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_UART1_MEM_LP_EN_S  2
+/** HP_SYSTEM_UART1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control uart1 memory, disable hardware control.
+ */
+#define HP_SYSTEM_UART1_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART1_MEM_FORCE_CTRL_V << HP_SYSTEM_UART1_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_UART1_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_UART2_MEM_LP_CTRL_REG register
+ *  uart memory power control register
+ */
+#define HP_SYSTEM_UART2_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x294)
+/** HP_SYSTEM_UART2_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures uart2 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_UART2_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_UART2_MEM_LP_MODE_M  (HP_SYSTEM_UART2_MEM_LP_MODE_V << HP_SYSTEM_UART2_MEM_LP_MODE_S)
+#define HP_SYSTEM_UART2_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_UART2_MEM_LP_MODE_S  0
+/** HP_SYSTEM_UART2_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down uart2 memory.
+ */
+#define HP_SYSTEM_UART2_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_UART2_MEM_LP_EN_M  (HP_SYSTEM_UART2_MEM_LP_EN_V << HP_SYSTEM_UART2_MEM_LP_EN_S)
+#define HP_SYSTEM_UART2_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_UART2_MEM_LP_EN_S  2
+/** HP_SYSTEM_UART2_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control uart2 memory, disable hardware control.
+ */
+#define HP_SYSTEM_UART2_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_M  (HP_SYSTEM_UART2_MEM_FORCE_CTRL_V << HP_SYSTEM_UART2_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_UART2_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_LEDC1_MEM_LP_CTRL_REG register
+ *  ledc1 memory power control register
+ */
+#define HP_SYSTEM_LEDC1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x298)
+/** HP_SYSTEM_LEDC1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures ledc1 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_LEDC1_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_LEDC1_MEM_LP_MODE_M  (HP_SYSTEM_LEDC1_MEM_LP_MODE_V << HP_SYSTEM_LEDC1_MEM_LP_MODE_S)
+#define HP_SYSTEM_LEDC1_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_LEDC1_MEM_LP_MODE_S  0
+/** HP_SYSTEM_LEDC1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down ledc1 memory.
+ */
+#define HP_SYSTEM_LEDC1_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_LEDC1_MEM_LP_EN_M  (HP_SYSTEM_LEDC1_MEM_LP_EN_V << HP_SYSTEM_LEDC1_MEM_LP_EN_S)
+#define HP_SYSTEM_LEDC1_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_LEDC1_MEM_LP_EN_S  2
+/** HP_SYSTEM_LEDC1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control ledc1 memory, disable hardware control.
+ */
+#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_M  (HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_V << HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_LEDC1_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_PPA_MEM_LP_CTRL_REG register
+ *  vpu memory power control register
+ */
+#define HP_SYSTEM_PPA_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x29c)
+/** HP_SYSTEM_PPA_SPRF_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures ppa_sprf memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_M  (HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_V << HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_S)
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_MODE_S  0
+/** HP_SYSTEM_PPA_SPRF_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down ppa_sprf memory.
+ */
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_M  (HP_SYSTEM_PPA_SPRF_MEM_LP_EN_V << HP_SYSTEM_PPA_SPRF_MEM_LP_EN_S)
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_PPA_SPRF_MEM_LP_EN_S  2
+/** HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control ppa_sprf memory, disable hardware control.
+ */
+#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_M  (HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_V << HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_PPA_SPRF_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_JPEG_MEM_LP_CTRL_REG register
+ *  vpu memory power control register
+ */
+#define HP_SYSTEM_JPEG_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2a0)
+/** HP_SYSTEM_JPEG_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures jpeg memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_JPEG_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_JPEG_MEM_LP_MODE_M  (HP_SYSTEM_JPEG_MEM_LP_MODE_V << HP_SYSTEM_JPEG_MEM_LP_MODE_S)
+#define HP_SYSTEM_JPEG_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_JPEG_MEM_LP_MODE_S  0
+/** HP_SYSTEM_JPEG_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down jpeg memory.
+ */
+#define HP_SYSTEM_JPEG_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_JPEG_MEM_LP_EN_M  (HP_SYSTEM_JPEG_MEM_LP_EN_V << HP_SYSTEM_JPEG_MEM_LP_EN_S)
+#define HP_SYSTEM_JPEG_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_JPEG_MEM_LP_EN_S  2
+/** HP_SYSTEM_JPEG_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control jpeg memory, disable hardware control.
+ */
+#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_M  (HP_SYSTEM_JPEG_MEM_FORCE_CTRL_V << HP_SYSTEM_JPEG_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_JPEG_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_CAN1_MEM_LP_CTRL_REG register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+#define HP_SYSTEM_CAN1_MEM_LP_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2a4)
+/** HP_SYSTEM_CAN1_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 2;
+ *  Configures can1 memory low power mode in low power stage.
+ *  0(default): deep sleep
+ *  1: light sleep
+ *  2: shut down
+ *  3: disable low power stage
+ */
+#define HP_SYSTEM_CAN1_MEM_LP_MODE    0x00000003U
+#define HP_SYSTEM_CAN1_MEM_LP_MODE_M  (HP_SYSTEM_CAN1_MEM_LP_MODE_V << HP_SYSTEM_CAN1_MEM_LP_MODE_S)
+#define HP_SYSTEM_CAN1_MEM_LP_MODE_V  0x00000003U
+#define HP_SYSTEM_CAN1_MEM_LP_MODE_S  0
+/** HP_SYSTEM_CAN1_MEM_LP_EN : R/W; bitpos: [2]; default: 1;
+ *  Set this bit to power down can1 memory.
+ */
+#define HP_SYSTEM_CAN1_MEM_LP_EN    (BIT(2))
+#define HP_SYSTEM_CAN1_MEM_LP_EN_M  (HP_SYSTEM_CAN1_MEM_LP_EN_V << HP_SYSTEM_CAN1_MEM_LP_EN_S)
+#define HP_SYSTEM_CAN1_MEM_LP_EN_V  0x00000001U
+#define HP_SYSTEM_CAN1_MEM_LP_EN_S  2
+/** HP_SYSTEM_CAN1_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to force software control can1 memory, disable hardware control.
+ */
+#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL    (BIT(3))
+#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_M  (HP_SYSTEM_CAN1_MEM_FORCE_CTRL_V << HP_SYSTEM_CAN1_MEM_FORCE_CTRL_S)
+#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_V  0x00000001U
+#define HP_SYSTEM_CAN1_MEM_FORCE_CTRL_S  3
+
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_CONF_REG register
+ *  CPU_PERI1_TIMEOUT configuration register
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_CONF_REG (DR_REG_HP_SYS_BASE + 0x2a8)
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
+ *  Configures the timeout threshold for bus access for accessing CPU peripheral
+ *  register in the number of clock cycles of the clock domain.
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES    0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_S)
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_V  0x0000FFFFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_THRES_S  0
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear timeout interrupt.
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR    (BIT(16))
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_S)
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_INT_CLR_S  16
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
+ *  Configures whether or not to enable timeout protection for accessing CPU
+ *  peripheral11 registers.
+ *  0: Disable
+ *  1: Enable
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN    (BIT(17))
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_S)
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_PROTECT_EN_S  17
+
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_REG register
+ *  CPU_PERI1_TIMEOUT_ADDR register
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_REG (DR_REG_HP_SYS_BASE + 0x2ac)
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Represents the address information of abnormal access.
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR    0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_S)
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_V  0xFFFFFFFFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_ADDR_S  0
+
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_REG register
+ *  CPU_PERI1_TIMEOUT_UID register
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_REG (DR_REG_HP_SYS_BASE + 0x2b0)
+/** HP_SYSTEM_CPU_PERI1_TIMEOUT_UID : RO; bitpos: [7:0]; default: 0;
+ *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+ *  register will be cleared after the interrupt is cleared.
+ */
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID    0x000000FFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_M  (HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_S)
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_V  0x000000FFU
+#define HP_SYSTEM_CPU_PERI1_TIMEOUT_UID_S  0
+
+/** HP_SYSTEM_CPU_ACS_CACHE_MEM_CONF_REG register
+ *  CPU access Cache data mem configuration register
+ */
+#define HP_SYSTEM_CPU_ACS_CACHE_MEM_CONF_REG (DR_REG_HP_SYS_BASE + 0x2b4)
+/** HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN : HRO; bitpos: [0]; default: 0;
+ *  Set this bit to enable CPU accessROMCache0 data mem path
+ */
+#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN    (BIT(0))
+#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_S)
+#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ACCESS_AC0_DATAMEM_EN_S  0
+/** HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN : HRO; bitpos: [1]; default: 0;
+ *  Set this bit to enable CPU access ROMCache1 data mem path
+ */
+#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN    (BIT(1))
+#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_S)
+#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ACCESS_AC1_DATAMEM_EN_S  1
+/** HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to enable CPU access ICache0 data mem path
+ */
+#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN    (BIT(2))
+#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_S)
+#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ACCESS_IC0_DATAMEM_EN_S  2
+/** HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable CPU access ICache1 data mem path
+ */
+#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN    (BIT(3))
+#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_S)
+#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ACCESS_IC1_DATAMEM_EN_S  3
+/** HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN : R/W; bitpos: [4]; default: 0;
+ *  Set this bit to enable CPU access DCache data mem path
+ */
+#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN    (BIT(4))
+#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_M  (HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_V << HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_S)
+#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_V  0x00000001U
+#define HP_SYSTEM_CPU_ACCESS_DC_DATAMEM_EN_S  4
+/** HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK : R/W; bitpos: [5]; default: 0;
+ *  Set 1 to lock cpu acs mem data mem path configuration
+ */
+#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK    (BIT(5))
+#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_M  (HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_V << HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_S)
+#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_V  0x00000001U
+#define HP_SYSTEM_CPU_ACS_CACHE_MEM_LOCK_S  5
+
+/** HP_SYSTEM_TCM_PERFORMACE_CTRL_REG register
+ *  need_des
+ */
+#define HP_SYSTEM_TCM_PERFORMACE_CTRL_REG (DR_REG_HP_SYS_BASE + 0x2e0)
+/** HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD : R/W; bitpos: [0]; default: 0;
+ *  Set 1 to keep TCM mem enable hold when mem access is busy.
+ */
+#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD    (BIT(0))
+#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_M  (HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_V << HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_S)
+#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_V  0x00000001U
+#define HP_SYSTEM_AHB_TO_TCM_MEM_EN_HOLD_S  0
+
+/** HP_SYSTEM_SDIO_PAD_BIST_CFG_REG register
+ *  sdio pad bist control register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x2e4)
+/** HP_SYSTEM_SDIO_PAD_BIST_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start sdio pad bist
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_START    (BIT(0))
+#define HP_SYSTEM_SDIO_PAD_BIST_START_M  (HP_SYSTEM_SDIO_PAD_BIST_START_V << HP_SYSTEM_SDIO_PAD_BIST_START_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_START_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_START_S  0
+
+/** HP_SYSTEM_SDIO_PAD_BIST_INT_RAW_REG register
+ *  sdio pad bist interrupt raw register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x2e8)
+/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when bist finish and status is bist ok
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW    (BIT(0))
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_RAW_S  0
+/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when bist finish and status is bist fail
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW    (BIT(1))
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_RAW_S  1
+
+/** HP_SYSTEM_SDIO_PAD_BIST_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x2ec)
+/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of sdio pad bist ok interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST    (BIT(0))
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ST_S  0
+/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of sdio pad bist fail interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST    (BIT(1))
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ST_S  1
+
+/** HP_SYSTEM_SDIO_PAD_BIST_INT_ENA_REG register
+ *  interrupt enable register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x2f0)
+/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable sdio pad bist ok interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA    (BIT(0))
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_ENA_S  0
+/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable sdio pad bist fail interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA    (BIT(1))
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_ENA_S  1
+
+/** HP_SYSTEM_SDIO_PAD_BIST_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x2f4)
+/** HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clr sdio pad bist ok interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR    (BIT(0))
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_OK_INT_CLR_S  0
+/** HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clr sdio pad bist fail interrupt
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR    (BIT(1))
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_SDIO_PAD_BIST_FAIL_INT_CLR_S  1
+
+/** HP_SYSTEM_SDIO_PAD_BIST_ST_REG register
+ *  sdio pad bist status register
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x2f8)
+/** HP_SYSTEM_SDIO_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
+ *  Indicate number of clock cycles received for pad bist debug
+ */
+#define HP_SYSTEM_SDIO_PAD_BIST_RCNT    0x0000003FU
+#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_M  (HP_SYSTEM_SDIO_PAD_BIST_RCNT_V << HP_SYSTEM_SDIO_PAD_BIST_RCNT_S)
+#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_V  0x0000003FU
+#define HP_SYSTEM_SDIO_PAD_BIST_RCNT_S  0
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_CFG_REG register
+ *  gmac0 pad bist control register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x2fc)
+/** HP_SYSTEM_GMAC0_PAD_BIST_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start gmac0 pad bist
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_START    (BIT(0))
+#define HP_SYSTEM_GMAC0_PAD_BIST_START_M  (HP_SYSTEM_GMAC0_PAD_BIST_START_V << HP_SYSTEM_GMAC0_PAD_BIST_START_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_START_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_START_S  0
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_INT_RAW_REG register
+ *  gmac0 pad bist interrupt raw register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x300)
+/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when bist finish and status is bist ok
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW    (BIT(0))
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_RAW_S  0
+/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when bist finish and status is bist fail
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW    (BIT(1))
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_RAW_S  1
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x304)
+/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of gmac0 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST    (BIT(0))
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ST_S  0
+/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of gmac0 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST    (BIT(1))
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ST_S  1
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_INT_ENA_REG register
+ *  interrupt enable register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x308)
+/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable gmac0 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA    (BIT(0))
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_ENA_S  0
+/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable gmac0 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA    (BIT(1))
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_ENA_S  1
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x30c)
+/** HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clr gmac0 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR    (BIT(0))
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_OK_INT_CLR_S  0
+/** HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clr gmac0 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR    (BIT(1))
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_GMAC0_PAD_BIST_FAIL_INT_CLR_S  1
+
+/** HP_SYSTEM_GMAC0_PAD_BIST_ST_REG register
+ *  gmac0 pad bist status register
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x310)
+/** HP_SYSTEM_GMAC0_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
+ *  Indicate number of clock cycles received for pad bist debug
+ */
+#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT    0x0000003FU
+#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_M  (HP_SYSTEM_GMAC0_PAD_BIST_RCNT_V << HP_SYSTEM_GMAC0_PAD_BIST_RCNT_S)
+#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_V  0x0000003FU
+#define HP_SYSTEM_GMAC0_PAD_BIST_RCNT_S  0
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_CFG_REG register
+ *  gmac1 pad bist control register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_CFG_REG (DR_REG_HP_SYS_BASE + 0x314)
+/** HP_SYSTEM_GMAC1_PAD_BIST_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to start gmac1 pad bist
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_START    (BIT(0))
+#define HP_SYSTEM_GMAC1_PAD_BIST_START_M  (HP_SYSTEM_GMAC1_PAD_BIST_START_V << HP_SYSTEM_GMAC1_PAD_BIST_START_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_START_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_START_S  0
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_INT_RAW_REG register
+ *  gmac1 pad bist interrupt raw register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_INT_RAW_REG (DR_REG_HP_SYS_BASE + 0x318)
+/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  intr triggered when bist finish and status is bist ok
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW    (BIT(0))
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_RAW_S  0
+/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  intr triggered when bist finish and status is bist fail
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW    (BIT(1))
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_RAW_S  1
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_INT_ST_REG register
+ *  masked interrupt register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_INT_ST_REG (DR_REG_HP_SYS_BASE + 0x31c)
+/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST : RO; bitpos: [0]; default: 0;
+ *  the masked interrupt status of gmac1 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST    (BIT(0))
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ST_S  0
+/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST : RO; bitpos: [1]; default: 0;
+ *  the masked interrupt status of gmac1 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST    (BIT(1))
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ST_S  1
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG register
+ *  interrupt enable register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_INT_ENA_REG (DR_REG_HP_SYS_BASE + 0x320)
+/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable gmac1 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA    (BIT(0))
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_ENA_S  0
+/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable gmac1 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA    (BIT(1))
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_ENA_S  1
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_INT_CLR_REG register
+ *  interrupt clear register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_INT_CLR_REG (DR_REG_HP_SYS_BASE + 0x324)
+/** HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clr gmac1 pad bist ok interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR    (BIT(0))
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_M  (HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_V << HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_OK_INT_CLR_S  0
+/** HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clr gmac1 pad bist fail interrupt
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR    (BIT(1))
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_M  (HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_V << HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_V  0x00000001U
+#define HP_SYSTEM_GMAC1_PAD_BIST_FAIL_INT_CLR_S  1
+
+/** HP_SYSTEM_GMAC1_PAD_BIST_ST_REG register
+ *  gmac1 pad bist status register
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_ST_REG (DR_REG_HP_SYS_BASE + 0x328)
+/** HP_SYSTEM_GMAC1_PAD_BIST_RCNT : RO; bitpos: [5:0]; default: 0;
+ *  Indicate number of clock cycles received for pad bist debug
+ */
+#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT    0x0000003FU
+#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_M  (HP_SYSTEM_GMAC1_PAD_BIST_RCNT_V << HP_SYSTEM_GMAC1_PAD_BIST_RCNT_S)
+#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_V  0x0000003FU
+#define HP_SYSTEM_GMAC1_PAD_BIST_RCNT_S  0
+
+/** HP_SYSTEM_CPU_PWAIT_MODE_REG register
+ *  Indicate status of core0 and core1 pwait
+ */
+#define HP_SYSTEM_CPU_PWAIT_MODE_REG (DR_REG_HP_SYS_BASE + 0x338)
+/** HP_SYSTEM_CPU_PWAIT_MODE : RO; bitpos: [1:0]; default: 0;
+ *  Indicate status of core0 and core1 pwait
+ */
+#define HP_SYSTEM_CPU_PWAIT_MODE    0x00000003U
+#define HP_SYSTEM_CPU_PWAIT_MODE_M  (HP_SYSTEM_CPU_PWAIT_MODE_V << HP_SYSTEM_CPU_PWAIT_MODE_S)
+#define HP_SYSTEM_CPU_PWAIT_MODE_V  0x00000003U
+#define HP_SYSTEM_CPU_PWAIT_MODE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/hp_system_struct.h b/components/soc/esp32s31/register/soc/hp_system_struct.h
new file mode 100644
index 00000000000..8a5f0a51799
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/hp_system_struct.h
@@ -0,0 +1,2382 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: HP SYS VER DATE REG */
+/** Type of sys_ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539296770;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} hp_system_ver_date_reg_t;
+
+
+/** Group: HP CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_clk_en_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 0 REG */
+/** Type of cpu_int_from_cpu_0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_0_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 1 REG */
+/** Type of cpu_int_from_cpu_1 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_1_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 2 REG */
+/** Type of cpu_int_from_cpu_2 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_2_reg_t;
+
+
+/** Group: HP CPU INT FROM CPU 3 REG */
+/** Type of cpu_int_from_cpu_3 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** cpu_int_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  set 1 will trigger a interrupt
+         */
+        uint32_t cpu_int_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_cpu_int_from_cpu_3_reg_t;
+
+
+/** Group: HP MODEM DIAG CONFIG REG */
+/** Type of modem_diag_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_modem_diag_en : R/W; bitpos: [31:0]; default: 0;
+         *  set reg_modem_diag_en[15:0] will let hp_system_probe_out[15:0] used as modem_diag[15:0],
+         *  set reg_modem_diag_en[31:16] will let lcd_data_out[15:0] used as modem_diag[31:16]
+         */
+        uint32_t reg_modem_diag_en:32;
+    };
+    uint32_t val;
+} hp_system_modem_diag_en_reg_t;
+
+
+/** Group: HP TCM RAM PWR CTRL0 REG */
+/** Type of tcm_ram_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  hp_system_tcm clk gatig force on
+         */
+        uint32_t reg_hp_system_tcm_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_ram_pwr_ctrl0_reg_t;
+
+
+/** Group: HP ROM PWR CTRL0 REG */
+/** Type of rom_pwr_ctrl0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_rom_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  hp_system_rom clk gating force on
+         */
+        uint32_t reg_hp_system_rom_clk_force_on:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_rom_pwr_ctrl0_reg_t;
+
+
+/** Group: HP PROBEA CTRL REG */
+/** Type of probea_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_a_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in a mode
+         */
+        uint32_t reg_probe_a_mod_sel:16;
+        /** reg_probe_a_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to selec module's probe_out[31:0] as probe out in a mode
+         */
+        uint32_t reg_probe_a_top_sel:8;
+        /** reg_probe_l_sel : R/W; bitpos: [25:24]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_l_sel:2;
+        /** reg_probe_h_sel : R/W; bitpos: [27:26]; default: 0;
+         *  This field is used to selec probe_out[31:16]
+         */
+        uint32_t reg_probe_h_sel:2;
+        /** reg_probe_global_en : R/W; bitpos: [28]; default: 0;
+         *  Set this bit to enable global debug probe in hp system.
+         */
+        uint32_t reg_probe_global_en:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} hp_system_probea_ctrl_reg_t;
+
+
+/** Group: HP PROBEB CTRL REG */
+/** Type of probeb_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_b_mod_sel : R/W; bitpos: [15:0]; default: 0;
+         *  This field is used to selec probe_group from probe_group0 to probe_group15 for
+         *  module's probe_out[31:0] in b mode.
+         */
+        uint32_t reg_probe_b_mod_sel:16;
+        /** reg_probe_b_top_sel : R/W; bitpos: [23:16]; default: 0;
+         *  This field is used to select module's probe_out[31:0]  as probe_out in b mode
+         */
+        uint32_t reg_probe_b_top_sel:8;
+        /** reg_probe_b_en : R/W; bitpos: [24]; default: 0;
+         *  Set this bit to enable b mode for debug probe. 1:  b mode, 0: a mode.
+         */
+        uint32_t reg_probe_b_en:1;
+        uint32_t reserved_25:7;
+    };
+    uint32_t val;
+} hp_system_probeb_ctrl_reg_t;
+
+
+/** Group: HP PROBE OUT REG */
+/** Type of probe_out register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_probe_top_out : RO; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_probe_top_out:32;
+    };
+    uint32_t val;
+} hp_system_probe_out_reg_t;
+
+
+/** Group: HP CPU CORESTALLED ST REG */
+/** Type of cpu_corestalled_st register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_core0_corestalled_st : RO; bitpos: [0]; default: 0;
+         *  hp core0 corestalled status
+         */
+        uint32_t reg_core0_corestalled_st:1;
+        /** reg_core1_corestalled_st : RO; bitpos: [1]; default: 0;
+         *  hp core1 corestalled status
+         */
+        uint32_t reg_core1_corestalled_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_cpu_corestalled_st_reg_t;
+
+
+/** Group: HP CRYPTO CTRL REG */
+/** Type of crypto_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_spi_manual_encrypt:1;
+        /** reg_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_db_encrypt:1;
+        /** reg_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_g0cb_decrypt:1;
+        /** reg_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  NA
+         */
+        uint32_t reg_enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_crypto_ctrl_reg_t;
+
+
+/** Group: HP IOMUX FPGA DEBUG REG */
+/** Type of iomux_fpga_debug register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_fpga_debug : R/W; bitpos: [0]; default: 1;
+         *  iomux fpga debug
+         */
+        uint32_t reg_fpga_debug:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_iomux_fpga_debug_reg_t;
+
+
+/** Group: HP SYS RDN ECO CS REG */
+/** Type of sys_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_rdn_eco_en:1;
+        /** reg_hp_system_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_rdn_eco_cs_reg_t;
+
+
+/** Group: HP TCM RDN ECO CS REG */
+/** Type of tcm_rdn_eco_cs register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_en:1;
+        /** reg_hp_system_tcm_rdn_eco_result : RO; bitpos: [1]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_cs_reg_t;
+
+
+/** Group: HP TCM RDN ECO LOW REG */
+/** Type of tcm_rdn_eco_low register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_low : R/W; bitpos: [31:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_low:32;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_low_reg_t;
+
+
+/** Group: HP TCM RDN ECO HIGH REG */
+/** Type of tcm_rdn_eco_high register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_hp_system_tcm_rdn_eco_high : R/W; bitpos: [31:0]; default: 4294967295;
+         *  NA
+         */
+        uint32_t reg_hp_system_tcm_rdn_eco_high:32;
+    };
+    uint32_t val;
+} hp_system_tcm_rdn_eco_high_reg_t;
+
+
+/** Group: HP CACHE PWR CTRL REG */
+/** Type of cache_pwr_ctrl register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ac_mem_fo : R/W; bitpos: [7:0]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ac_mem_fo:8;
+        /** reg_ic_mem_fo : R/W; bitpos: [15:8]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_ic_mem_fo:8;
+        /** reg_dc_mem_fo : R/W; bitpos: [23:16]; default: 0;
+         *  need_des
+         */
+        uint32_t reg_dc_mem_fo:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_system_cache_pwr_ctrl_reg_t;
+
+
+/** Group: HP_TCM_DATA_DUMP_CTRL_REG */
+/** Type of tcm_data_dump_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** tcm_data_dump_en : R/W; bitpos: [31:0]; default: 0;
+         *  hp tcm_data dump switch
+         */
+        uint32_t tcm_data_dump_en:32;
+    };
+    uint32_t val;
+} hp_system_tcm_data_dump_ctrl_reg_t;
+
+
+/** Group: Configuration Register */
+/** Type of cpu_waiti_conf register
+ *  CPU_WAITI configuration register
+ */
+typedef union {
+    struct {
+        /** cpu_wait_mode_force_on : R/W; bitpos: [0]; default: 1;
+         *  Set 1 to force cpu_waiti_clk enable.
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [4:1]; default: 0;
+         *  This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk
+         *  will close
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_system_cpu_waiti_conf_reg_t;
+
+/** Type of sys_core_debug_runstall_conf register
+ *  Core Debug runstall configure register
+ */
+typedef union {
+    struct {
+        /** sys_core_debug_runstall_enable : R/W; bitpos: [0]; default: 0;
+         *  Set this field to 1 to enable debug runstall feature between HP-core and LP-core.
+         */
+        uint32_t sys_core_debug_runstall_enable:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_core_debug_runstall_conf_reg_t;
+
+/** Type of core_pad_wakeup_event register
+ *  pad wakeup event register
+ */
+typedef union {
+    struct {
+        /** core0_pad_wakeup_event : R/W; bitpos: [0]; default: 0;
+         *  wakeup core0 register
+         */
+        uint32_t core0_pad_wakeup_event:1;
+        /** core1_pad_wakeup_event : R/W; bitpos: [1]; default: 0;
+         *  wakeup core1 register
+         */
+        uint32_t core1_pad_wakeup_event:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_core_pad_wakeup_event_reg_t;
+
+/** Type of twai0_timestamp_l register
+ *  twai0 timestamp low bit reg
+ */
+typedef union {
+    struct {
+        /** twai0_timestamp_i : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This field used to set lower 32bits of timestamp hp twai0
+         */
+        uint32_t twai0_timestamp_i:32;
+    };
+    uint32_t val;
+} hp_system_twai0_timestamp_l_reg_t;
+
+/** Type of twai0_timestamp_h register
+ *  twai0 timestamp high bit reg
+ */
+typedef union {
+    struct {
+        /** twai0_timestamp_h : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This field used to set upper 32bits of timestamp hp twai0
+         */
+        uint32_t twai0_timestamp_h:32;
+    };
+    uint32_t val;
+} hp_system_twai0_timestamp_h_reg_t;
+
+/** Type of twai1_timestamp_l register
+ *  twai1 timestamp low bit reg
+ */
+typedef union {
+    struct {
+        /** twai1_timestamp_i : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This field used to set lower 32bits of timestamp hp twai1
+         */
+        uint32_t twai1_timestamp_i:32;
+    };
+    uint32_t val;
+} hp_system_twai1_timestamp_l_reg_t;
+
+/** Type of twai1_timestamp_h register
+ *  twai1 timestamp high bit reg
+ */
+typedef union {
+    struct {
+        /** twai1_timestamp_h : R/W; bitpos: [31:0]; default: 4294967295;
+         *  This field used to set upper 32bits of timestamp hp twai1
+         */
+        uint32_t twai1_timestamp_h:32;
+    };
+    uint32_t val;
+} hp_system_twai1_timestamp_h_reg_t;
+
+/** Type of rng_cfg register
+ *  rng cfg register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** rng_chain_clk_div_num : R/W; bitpos: [23:16]; default: 0;
+         *  chain clk div num to pad for debug
+         */
+        uint32_t rng_chain_clk_div_num:8;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} hp_system_rng_cfg_reg_t;
+
+/** Type of peri_mem_clk_force_on register
+ *  hp peri mem clk force on regpster
+ */
+typedef union {
+    struct {
+        /** rmt_mem_clk_force_on : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force on mem clk in rmt
+         */
+        uint32_t rmt_mem_clk_force_on:1;
+        /** bitscrambler_tx_mem_clk_force_on : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to force on tx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_tx_mem_clk_force_on:1;
+        /** bitscrambler_rx_mem_clk_force_on : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force on rx mem clk in bitscrambler
+         */
+        uint32_t bitscrambler_rx_mem_clk_force_on:1;
+        /** gdma_mem_clk_force_on : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force on mem clk in gdma
+         */
+        uint32_t gdma_mem_clk_force_on:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_peri_mem_clk_force_on_reg_t;
+
+/** Type of sys_prdyn_st register
+ *  hp system prdyn status register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** rom_prdyn : RO; bitpos: [1]; default: 1;
+         *  record memory power status
+         */
+        uint32_t rom_prdyn:1;
+        uint32_t reserved_2:1;
+        /** cpu_mem_prdyn : RO; bitpos: [3]; default: 1;
+         *  record memory power status
+         */
+        uint32_t cpu_mem_prdyn:1;
+        /** bitscrambler_mem_prdyn : RO; bitpos: [4]; default: 1;
+         *  record memory power status
+         */
+        uint32_t bitscrambler_mem_prdyn:1;
+        uint32_t reserved_5:1;
+        /** usb_mem_prdyn : RO; bitpos: [6]; default: 1;
+         *  record memory power status
+         */
+        uint32_t usb_mem_prdyn:1;
+        /** rmt_mem_prdyn : RO; bitpos: [7]; default: 1;
+         *  record memory power status
+         */
+        uint32_t rmt_mem_prdyn:1;
+        /** ledc0_mem_prdyn : RO; bitpos: [8]; default: 1;
+         *  record memory power status
+         */
+        uint32_t ledc0_mem_prdyn:1;
+        /** key_manager_mem_prdyn : RO; bitpos: [9]; default: 1;
+         *  record memory power status
+         */
+        uint32_t key_manager_mem_prdyn:1;
+        /** vpu_mem_prdyn : RO; bitpos: [10]; default: 1;
+         *  record memory power status
+         */
+        uint32_t vpu_mem_prdyn:1;
+        uint32_t reserved_11:1;
+        /** gdma_mem_prdyn : RO; bitpos: [12]; default: 1;
+         *  record memory power status
+         */
+        uint32_t gdma_mem_prdyn:1;
+        uint32_t reserved_13:1;
+        /** uart_mem_prdyn : RO; bitpos: [14]; default: 1;
+         *  record memory power status
+         */
+        uint32_t uart_mem_prdyn:1;
+        /** crypto_mem_prdyn : RO; bitpos: [15]; default: 1;
+         *  record memory power status
+         */
+        uint32_t crypto_mem_prdyn:1;
+        /** flash_mspi_mem_prdyn : RO; bitpos: [16]; default: 1;
+         *  record memory power status
+         */
+        uint32_t flash_mspi_mem_prdyn:1;
+        /** psram_mspi_mem_prdyn : RO; bitpos: [17]; default: 1;
+         *  record memory power status
+         */
+        uint32_t psram_mspi_mem_prdyn:1;
+        /** modem_mem_prdyn : RO; bitpos: [18]; default: 1;
+         *  record memory power status
+         */
+        uint32_t modem_mem_prdyn:1;
+        /** ledc1_mem_prdyn : RO; bitpos: [19]; default: 1;
+         *  record memory power status
+         */
+        uint32_t ledc1_mem_prdyn:1;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} hp_system_prdyn_st_reg_t;
+
+/** Type of sys_icm_cfg register
+ *  hp system axi icm ctrl register
+ */
+typedef union {
+    struct {
+        /** sys_icm_dis_rd : R/W; bitpos: [2:0]; default: 0;
+         *  0:mean master can access slave , 1:mean master can not rd slave ,will returen
+         *  decerro on axi bus
+         */
+        uint32_t sys_icm_dis_rd:3;
+        /** sys_icm_dis_wr : R/W; bitpos: [5:3]; default: 0;
+         *  0:mean master can access slave , 1:mean master can not wr slave ,will returen
+         *  decerro on axi bus
+         */
+        uint32_t sys_icm_dis_wr:3;
+        /** sys_icm_cfg_secure : R/W; bitpos: [8:6]; default: 0;
+         *  axi_matrix slave ,0: non-secure, 1: secure , total 3 slave.
+         */
+        uint32_t sys_icm_cfg_secure:3;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} hp_system_icm_cfg_reg_t;
+
+/** Type of sys_uart3_mem_lp_ctrl register
+ *  uart memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_uart3_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures uart3 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_uart3_mem_lp_mode:2;
+        /** sys_uart3_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down uart3 memory.
+         */
+        uint32_t sys_uart3_mem_lp_en:1;
+        /** sys_uart3_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control uart3 memory, disable hardware control.
+         */
+        uint32_t sys_uart3_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_uart3_mem_lp_ctrl_reg_t;
+
+/** Type of sys_rmt_mem_lp_ctrl register
+ *  rmt memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_rmt_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures rmt memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_rmt_mem_lp_mode:2;
+        /** sys_rmt_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down rmt memory.
+         */
+        uint32_t sys_rmt_mem_lp_en:1;
+        /** sys_rmt_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control rmt memory, disable hardware control.
+         */
+        uint32_t sys_rmt_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_rmt_mem_lp_ctrl_reg_t;
+
+/** Type of sys_ledc0_mem_lp_ctrl register
+ *  ledc0 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_ledc0_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures ledc0 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_ledc0_mem_lp_mode:2;
+        /** sys_ledc0_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down ledc0 memory.
+         */
+        uint32_t sys_ledc0_mem_lp_en:1;
+        /** sys_ledc0_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control ledc0 memory, disable hardware control.
+         */
+        uint32_t sys_ledc0_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_ledc0_mem_lp_ctrl_reg_t;
+
+/** Type of sys_km_mem_lp_ctrl register
+ *  key manager memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_km_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures km memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_km_mem_lp_mode:2;
+        /** sys_km_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down km memory.
+         */
+        uint32_t sys_km_mem_lp_en:1;
+        /** sys_km_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control km memory, disable hardware control.
+         */
+        uint32_t sys_km_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_km_mem_lp_ctrl_reg_t;
+
+/** Type of sys_dma2d_mem_lp_ctrl register
+ *  vpu memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_2ddma_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures 2ddma memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_2ddma_mem_lp_mode:2;
+        /** sys_2ddma_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down 2ddma memory.
+         */
+        uint32_t sys_2ddma_mem_lp_en:1;
+        /** sys_2ddma_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control 2ddma memory, disable hardware control.
+         */
+        uint32_t sys_2ddma_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_dma2d_mem_lp_ctrl_reg_t;
+
+/** Type of sys_axi_pdma_mem_lp_ctrl register
+ *  vpu memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_axi_pdma_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures axi_pdma memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_axi_pdma_mem_lp_mode:2;
+        /** sys_axi_pdma_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down axi_pdma memory.
+         */
+        uint32_t sys_axi_pdma_mem_lp_en:1;
+        /** sys_axi_pdma_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control axi_pdma memory, disable hardware control.
+         */
+        uint32_t sys_axi_pdma_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_axi_pdma_mem_lp_ctrl_reg_t;
+
+/** Type of sys_ecc_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_ecc_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures ecc memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_ecc_mem_lp_mode:2;
+        /** sys_ecc_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down ecc memory.
+         */
+        uint32_t sys_ecc_mem_lp_en:1;
+        /** sys_ecc_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control ecc memory, disable hardware control.
+         */
+        uint32_t sys_ecc_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_ecc_mem_lp_ctrl_reg_t;
+
+/** Type of sys_rsa_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_rsa_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures rsa memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_rsa_mem_lp_mode:2;
+        /** sys_rsa_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down rsa memory.
+         */
+        uint32_t sys_rsa_mem_lp_en:1;
+        /** sys_rsa_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control rsa memory, disable hardware control.
+         */
+        uint32_t sys_rsa_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_rsa_mem_lp_ctrl_reg_t;
+
+/** Type of sys_bitscram_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_bitscram_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures bitscram memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_bitscram_mem_lp_mode:2;
+        /** sys_bitscram_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down bitscram memory.
+         */
+        uint32_t sys_bitscram_mem_lp_en:1;
+        /** sys_bitscram_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control bitscram memory, disable hardware control.
+         */
+        uint32_t sys_bitscram_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_bitscram_mem_lp_ctrl_reg_t;
+
+/** Type of sys_can0_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_can0_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures can0 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_can0_mem_lp_mode:2;
+        /** sys_can0_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down can0 memory.
+         */
+        uint32_t sys_can0_mem_lp_en:1;
+        /** sys_can0_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control can0 memory, disable hardware control.
+         */
+        uint32_t sys_can0_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_can0_mem_lp_ctrl_reg_t;
+
+/** Type of sys_mspi_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_psram_mspi_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures psram_mspi memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_psram_mspi_mem_lp_mode:2;
+        /** sys_psram_mspi_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down psram_mspi memory.
+         */
+        uint32_t sys_psram_mspi_mem_lp_en:1;
+        /** sys_psram_mspi_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control psram_mspi memory, disable hardware control.
+         */
+        uint32_t sys_psram_mspi_mem_lp_force_ctrl:1;
+        /** sys_flash_mspi_mem_lp_mode : R/W; bitpos: [5:4]; default: 2;
+         *  Configures flash_mspi memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_flash_mspi_mem_lp_mode:2;
+        /** sys_flash_mspi_mem_lp_en : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to power down flash_mspi memory.
+         */
+        uint32_t sys_flash_mspi_mem_lp_en:1;
+        /** sys_flash_mspi_mem_lp_force_ctrl : R/W; bitpos: [7]; default: 0;
+         *  Set this bit to force software control flash_mspi memory, disable hardware control.
+         */
+        uint32_t sys_flash_mspi_mem_lp_force_ctrl:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_mspi_mem_lp_ctrl_reg_t;
+
+/** Type of sys_hpcore_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_hpcore_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures hpcore memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_hpcore_mem_lp_mode:2;
+        /** sys_hpcore_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down hpcore memory.
+         */
+        uint32_t sys_hpcore_mem_lp_en:1;
+        /** sys_hpcore_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control hpcore memory, disable hardware control.
+         */
+        uint32_t sys_hpcore_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_hpcore_mem_lp_ctrl_reg_t;
+
+/** Type of sys_rom_mem_lp_ctrl register
+ *  rom power control register
+ */
+typedef union {
+    struct {
+        /** sys_rom_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures rom low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_rom_mem_lp_mode:2;
+        /** sys_rom_mem_lp_en : R/W; bitpos: [3:2]; default: 0;
+         *  Set this bit to power down rom.
+         */
+        uint32_t sys_rom_mem_lp_en:2;
+        /** sys_rom_mem_lp_force_ctrl : R/W; bitpos: [5:4]; default: 0;
+         *  Set this bit to force software control rom, disable hardware control.
+         */
+        uint32_t sys_rom_mem_lp_force_ctrl:2;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_rom_mem_lp_ctrl_reg_t;
+
+/** Type of sys_l1_cache_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_l1_cache_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures l1_cache memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_l1_cache_mem_lp_mode:2;
+        /** sys_l1_cache_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down l1_cache memory.
+         */
+        uint32_t sys_l1_cache_mem_lp_en:1;
+        /** sys_l1_cache_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control l1_cache memory, disable hardware control.
+         */
+        uint32_t sys_l1_cache_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_l1_cache_mem_lp_ctrl_reg_t;
+
+/** Type of sys_kyber_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_kyber_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures kyber memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_kyber_mem_lp_mode:2;
+        /** sys_kyber_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down kyber memory.
+         */
+        uint32_t sys_kyber_mem_lp_en:1;
+        /** sys_kyber_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control kyber memory, disable hardware control.
+         */
+        uint32_t sys_kyber_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_kyber_mem_lp_ctrl_reg_t;
+
+/** Type of sys_lcdcam_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_lcdcam_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures lcdcam memory low power mode in low power stage.
+         *  0: deep sleep
+         *  1: light sleep
+         *  2(default): shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_lcdcam_mem_lp_mode:2;
+        /** sys_lcdcam_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down lcdcam memory.
+         */
+        uint32_t sys_lcdcam_mem_lp_en:1;
+        /** sys_lcdcam_mem_lp_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control lcdcam memory, disable hardware control.
+         */
+        uint32_t sys_lcdcam_mem_lp_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_lcdcam_mem_lp_ctrl_reg_t;
+
+/** Type of sys_uart0_mem_lp_ctrl register
+ *  uart memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_uart0_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
+         *  Configures uart0 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_uart0_mem_lp_mode:2;
+        /** sys_uart0_mem_lp_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to power down uart0 memory.
+         */
+        uint32_t sys_uart0_mem_lp_en:1;
+        /** sys_uart0_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control uart0 memory, disable hardware control.
+         */
+        uint32_t sys_uart0_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_uart0_mem_lp_ctrl_reg_t;
+
+/** Type of sys_uart1_mem_lp_ctrl register
+ *  uart memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_uart1_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures uart1 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_uart1_mem_lp_mode:2;
+        /** sys_uart1_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down uart1 memory.
+         */
+        uint32_t sys_uart1_mem_lp_en:1;
+        /** sys_uart1_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control uart1 memory, disable hardware control.
+         */
+        uint32_t sys_uart1_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_uart1_mem_lp_ctrl_reg_t;
+
+/** Type of sys_uart2_mem_lp_ctrl register
+ *  uart memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_uart2_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures uart2 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_uart2_mem_lp_mode:2;
+        /** sys_uart2_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down uart2 memory.
+         */
+        uint32_t sys_uart2_mem_lp_en:1;
+        /** sys_uart2_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control uart2 memory, disable hardware control.
+         */
+        uint32_t sys_uart2_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_uart2_mem_lp_ctrl_reg_t;
+
+/** Type of sys_ledc1_mem_lp_ctrl register
+ *  ledc1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_ledc1_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures ledc1 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_ledc1_mem_lp_mode:2;
+        /** sys_ledc1_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down ledc1 memory.
+         */
+        uint32_t sys_ledc1_mem_lp_en:1;
+        /** sys_ledc1_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control ledc1 memory, disable hardware control.
+         */
+        uint32_t sys_ledc1_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_ledc1_mem_lp_ctrl_reg_t;
+
+/** Type of sys_ppa_mem_lp_ctrl register
+ *  vpu memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_ppa_sprf_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures ppa_sprf memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_ppa_sprf_mem_lp_mode:2;
+        /** sys_ppa_sprf_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down ppa_sprf memory.
+         */
+        uint32_t sys_ppa_sprf_mem_lp_en:1;
+        /** sys_ppa_sprf_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control ppa_sprf memory, disable hardware control.
+         */
+        uint32_t sys_ppa_sprf_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_ppa_mem_lp_ctrl_reg_t;
+
+/** Type of sys_jpeg_mem_lp_ctrl register
+ *  vpu memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_jpeg_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures jpeg memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_jpeg_mem_lp_mode:2;
+        /** sys_jpeg_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down jpeg memory.
+         */
+        uint32_t sys_jpeg_mem_lp_en:1;
+        /** sys_jpeg_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control jpeg memory, disable hardware control.
+         */
+        uint32_t sys_jpeg_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_jpeg_mem_lp_ctrl_reg_t;
+
+/** Type of sys_can1_mem_lp_ctrl register
+ *  HP CORE0 & HP CORE1 memory power control register
+ */
+typedef union {
+    struct {
+        /** sys_can1_mem_lp_mode : R/W; bitpos: [1:0]; default: 2;
+         *  Configures can1 memory low power mode in low power stage.
+         *  0(default): deep sleep
+         *  1: light sleep
+         *  2: shut down
+         *  3: disable low power stage
+         */
+        uint32_t sys_can1_mem_lp_mode:2;
+        /** sys_can1_mem_lp_en : R/W; bitpos: [2]; default: 1;
+         *  Set this bit to power down can1 memory.
+         */
+        uint32_t sys_can1_mem_lp_en:1;
+        /** sys_can1_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to force software control can1 memory, disable hardware control.
+         */
+        uint32_t sys_can1_mem_force_ctrl:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} hp_system_can1_mem_lp_ctrl_reg_t;
+
+/** Type of sys_cpu_acs_cache_mem_conf register
+ *  CPU access Cache data mem configuration register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_access_ac0_datamem_en : HRO; bitpos: [0]; default: 0;
+         *  Set this bit to enable CPU accessROMCache0 data mem path
+         */
+        uint32_t sys_cpu_access_ac0_datamem_en:1;
+        /** sys_cpu_access_ac1_datamem_en : HRO; bitpos: [1]; default: 0;
+         *  Set this bit to enable CPU access ROMCache1 data mem path
+         */
+        uint32_t sys_cpu_access_ac1_datamem_en:1;
+        /** sys_cpu_access_ic0_datamem_en : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to enable CPU access ICache0 data mem path
+         */
+        uint32_t sys_cpu_access_ic0_datamem_en:1;
+        /** sys_cpu_access_ic1_datamem_en : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable CPU access ICache1 data mem path
+         */
+        uint32_t sys_cpu_access_ic1_datamem_en:1;
+        /** sys_cpu_access_dc_datamem_en : R/W; bitpos: [4]; default: 0;
+         *  Set this bit to enable CPU access DCache data mem path
+         */
+        uint32_t sys_cpu_access_dc_datamem_en:1;
+        /** sys_cpu_acs_cache_mem_lock : R/W; bitpos: [5]; default: 0;
+         *  Set 1 to lock cpu acs mem data mem path configuration
+         */
+        uint32_t sys_cpu_acs_cache_mem_lock:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_cpu_acs_cache_mem_conf_reg_t;
+
+/** Type of sys_sdio_pad_bist_cfg register
+ *  sdio pad bist control register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start sdio pad bist
+         */
+        uint32_t sys_sdio_pad_bist_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_cfg_reg_t;
+
+/** Type of sys_gmac0_pad_bist_cfg register
+ *  gmac0 pad bist control register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start gmac0 pad bist
+         */
+        uint32_t sys_gmac0_pad_bist_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_cfg_reg_t;
+
+/** Type of sys_gmac1_pad_bist_cfg register
+ *  gmac1 pad bist control register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to start gmac1 pad bist
+         */
+        uint32_t sys_gmac1_pad_bist_start:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_cfg_reg_t;
+
+
+/** Group: configure_register */
+/** Type of core_ibus_timeout_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_ibus_timeout_protect_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 ibus timeout handle
+         */
+        uint32_t core_ibus_timeout_protect_en:1;
+        /** core_ibus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 ibus timeout  threshold
+         */
+        uint32_t core_ibus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_core_ibus_timeout_conf_reg_t;
+
+/** Type of core_dbus_timeout_conf register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dbus_timeout_protect_en : R/W; bitpos: [0]; default: 1;
+         *  set this field to 1 to enable hp core0&1 dbus timeout handle
+         */
+        uint32_t core_dbus_timeout_protect_en:1;
+        /** core_dbus_timeout_thres : R/W; bitpos: [16:1]; default: 65535;
+         *  This field used to set hp core0&1 dbus timeout  threshold
+         */
+        uint32_t core_dbus_timeout_thres:16;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} hp_system_core_dbus_timeout_conf_reg_t;
+
+/** Type of icm_h2x_cfg register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** cpu_icm_h2x_post_wr_en : R/W; bitpos: [0]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_post_wr_en:1;
+        /** cpu_icm_h2x_cut_through_en : R/W; bitpos: [1]; default: 1;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_cut_through_en:1;
+        /** cpu_icm_h2x_bridge_busy : RO; bitpos: [2]; default: 0;
+         *  need_des
+         */
+        uint32_t cpu_icm_h2x_bridge_busy:1;
+        /** sdmmc_icm_h2x_post_wr_en : R/W; bitpos: [3]; default: 0;
+         *  need_des
+         */
+        uint32_t sdmmc_icm_h2x_post_wr_en:1;
+        /** sdmmc_icm_h2x_cut_through_en : R/W; bitpos: [4]; default: 1;
+         *  need_des
+         */
+        uint32_t sdmmc_icm_h2x_cut_through_en:1;
+        /** sdmmc_icm_h2x_bridge_busy : RO; bitpos: [5]; default: 0;
+         *  need_des
+         */
+        uint32_t sdmmc_icm_h2x_bridge_busy:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_icm_h2x_cfg_reg_t;
+
+/** Type of bitscrambler_peri_sel register
+ *  Bitscrambler Peri Sel
+ */
+typedef union {
+    struct {
+        /** bitscrambler_peri_rx_sel : R/W; bitpos: [4:0]; default: 0;
+         *  Set  this field to sel peri with DMA RX interface to connect with bitscrambler:
+         *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
+         *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
+         *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
+         *  5'h11, none: else.
+         */
+        uint32_t bitscrambler_peri_rx_sel:5;
+        /** bitscrambler_peri_tx_sel : R/W; bitpos: [9:5]; default: 0;
+         *  Set  this field to sel peri with DMA TX interface to connect with bitscrambler:
+         *  lcd_cam: 5'h1, gpspi2: 5'h2: gpspi3: 5'h3, parl_io:5'h4, aes: 5'h5, sha: 5'h6, adc:
+         *  5'h7, i2s0_ch0: 5'h8, i2s0_ch1: 5'h9, i2s0_ch2: 5'ha, i2s0_ch3: 5'hb,
+         *  i2s1_ch0: 5'hc, i2s1_ch1: 5'hd, i2s1_ch2: 5'he, i2s1_ch3: 5'hf, uhci0: 5'h10, RMT:
+         *  5'h11, none: else.
+         */
+        uint32_t bitscrambler_peri_tx_sel:5;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} hp_system_bitscrambler_peri_sel_reg_t;
+
+
+/** Group: GDMA Ctonrol Register */
+/** Type of sys_gdma_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_debug_ch_num : R/W; bitpos: [1:0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_debug_ch_num:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gdma_ctrl_reg_t;
+
+
+/** Group: VPU Control Register */
+/** Type of sys_vpu_ctrl register
+ *  N/A
+ */
+typedef union {
+    struct {
+        /** sys_ppa_lslp_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_ppa_lslp_mem_pd:1;
+        /** sys_jpeg_sdslp_mem_pd : R/W; bitpos: [1]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_sdslp_mem_pd:1;
+        /** sys_jpeg_lslp_mem_pd : R/W; bitpos: [2]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_lslp_mem_pd:1;
+        /** sys_jpeg_dslp_mem_pd : R/W; bitpos: [3]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_jpeg_dslp_mem_pd:1;
+        /** sys_dma2d_lslp_mem_pd : R/W; bitpos: [4]; default: 0;
+         *  N/A
+         */
+        uint32_t sys_dma2d_lslp_mem_pd:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} hp_system_vpu_ctrl_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION0 */
+/** Type of design_for_verification0 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv0 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv0:32;
+    };
+    uint32_t val;
+} hp_system_design_for_verification0_reg_t;
+
+
+/** Group: HP_DESIGN_FOR_VERIFICATION1 */
+/** Type of design_for_verification1 register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** dfv1 : R/W; bitpos: [31:0]; default: 0;
+         *  register for DV
+         */
+        uint32_t dfv1:32;
+    };
+    uint32_t val;
+} hp_system_design_for_verification1_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of ahb2axi_bresp_err_int_raw register
+ *  NA
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sdmmc_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
+         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+         *  post write mode in ahb2axi.
+         */
+        uint32_t sdmmc_icm_h2x_bresp_err_int_raw:1;
+        /** cpu_icm_h2x_bresp_err_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
+         *  the raw interrupt status of bresp error,  triggered when if  bresp err occurs  in
+         *  post write mode in ahb2axi.
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_raw:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_raw_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_st register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sdmmc_icm_h2x_bresp_err_int_st : RO; bitpos: [30]; default: 0;
+         *  the masked interrupt status of  sdmmc_icm_h2x_bresp_err
+         */
+        uint32_t sdmmc_icm_h2x_bresp_err_int_st:1;
+        /** cpu_icm_h2x_bresp_err_int_st : RO; bitpos: [31]; default: 0;
+         *  the masked interrupt status of  cpu_icm_h2x_bresp_err
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_st:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_st_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_ena register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sdmmc_icm_h2x_bresp_err_int_ena : R/W; bitpos: [30]; default: 0;
+         *  Write 1 to enable sdmmc_icm_h2x_bresp_err int
+         */
+        uint32_t sdmmc_icm_h2x_bresp_err_int_ena:1;
+        /** cpu_icm_h2x_bresp_err_int_ena : R/W; bitpos: [31]; default: 0;
+         *  Write 1 to enable cpu_icm_h2x_bresp_err int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_ena:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_ena_reg_t;
+
+/** Type of ahb2axi_bresp_err_int_clr register
+ *  need_des
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** sdmmc_icm_h2x_bresp_err_int_clr : WT; bitpos: [30]; default: 0;
+         *  Write 1 to clear sdmmc_icm_h2x_bresp_err  int
+         */
+        uint32_t sdmmc_icm_h2x_bresp_err_int_clr:1;
+        /** cpu_icm_h2x_bresp_err_int_clr : WT; bitpos: [31]; default: 0;
+         *  Write 1 to clear cpu_icm_h2x_bresp_err  int
+         */
+        uint32_t cpu_icm_h2x_bresp_err_int_clr:1;
+    };
+    uint32_t val;
+} hp_system_ahb2axi_bresp_err_int_clr_reg_t;
+
+/** Type of core_timeout_int_raw register
+ *  Hp core bus timeout interrupt raw register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** core0_ibus_timeout_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  the raw interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_raw:1;
+        /** core1_ibus_timeout_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
+         *  the raw interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_raw:1;
+        /** core0_dbus_timeout_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  the raw interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_raw:1;
+        /** core1_dbus_timeout_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  the raw interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_raw:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_raw_reg_t;
+
+/** Type of core_timeout_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** core0_ibus_timeout_int_st : RO; bitpos: [2]; default: 0;
+         *  the masked interrupt status of hp core0  ibus timeout
+         */
+        uint32_t core0_ibus_timeout_int_st:1;
+        /** core1_ibus_timeout_int_st : RO; bitpos: [3]; default: 0;
+         *  the masked interrupt status of hp core1  ibus timeout
+         */
+        uint32_t core1_ibus_timeout_int_st:1;
+        /** core0_dbus_timeout_int_st : RO; bitpos: [4]; default: 0;
+         *  the masked interrupt status of hp core0  dbus timeout
+         */
+        uint32_t core0_dbus_timeout_int_st:1;
+        /** core1_dbus_timeout_int_st : RO; bitpos: [5]; default: 0;
+         *  the masked interrupt status of hp core1  dbus timeout
+         */
+        uint32_t core1_dbus_timeout_int_st:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_st_reg_t;
+
+/** Type of core_timeout_int_ena register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** core0_ibus_timeout_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable hp_system_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_ena:1;
+        /** core1_ibus_timeout_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable hp_system_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_ena:1;
+        /** core0_dbus_timeout_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable hp_system_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_ena:1;
+        /** core1_dbus_timeout_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable hp_system_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_ena:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_ena_reg_t;
+
+/** Type of core_timeout_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** core0_ibus_timeout_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear hp_system_core0_ibus_timeout int
+         */
+        uint32_t core0_ibus_timeout_int_clr:1;
+        /** core1_ibus_timeout_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear hp_system_core1_ibus_timeout int
+         */
+        uint32_t core1_ibus_timeout_int_clr:1;
+        /** core0_dbus_timeout_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear hp_system_core0_dbus_timeout int
+         */
+        uint32_t core0_dbus_timeout_int_clr:1;
+        /** core1_dbus_timeout_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear hp_system_core1_dbus_timeout int
+         */
+        uint32_t core1_dbus_timeout_int_clr:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_core_timeout_int_clr_reg_t;
+
+/** Type of sys_sdio_pad_bist_int_raw register
+ *  sdio pad bist interrupt raw register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_ok_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when bist finish and status is bist ok
+         */
+        uint32_t sys_sdio_pad_bist_ok_int_raw:1;
+        /** sys_sdio_pad_bist_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when bist finish and status is bist fail
+         */
+        uint32_t sys_sdio_pad_bist_fail_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_int_raw_reg_t;
+
+/** Type of sys_sdio_pad_bist_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_ok_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of sdio pad bist ok interrupt
+         */
+        uint32_t sys_sdio_pad_bist_ok_int_st:1;
+        /** sys_sdio_pad_bist_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of sdio pad bist fail interrupt
+         */
+        uint32_t sys_sdio_pad_bist_fail_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_int_st_reg_t;
+
+/** Type of sys_sdio_pad_bist_int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_ok_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable sdio pad bist ok interrupt
+         */
+        uint32_t sys_sdio_pad_bist_ok_int_ena:1;
+        /** sys_sdio_pad_bist_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable sdio pad bist fail interrupt
+         */
+        uint32_t sys_sdio_pad_bist_fail_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_int_ena_reg_t;
+
+/** Type of sys_sdio_pad_bist_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_ok_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clr sdio pad bist ok interrupt
+         */
+        uint32_t sys_sdio_pad_bist_ok_int_clr:1;
+        /** sys_sdio_pad_bist_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clr sdio pad bist fail interrupt
+         */
+        uint32_t sys_sdio_pad_bist_fail_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_int_clr_reg_t;
+
+/** Type of sys_gmac0_pad_bist_int_raw register
+ *  gmac0 pad bist interrupt raw register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_ok_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when bist finish and status is bist ok
+         */
+        uint32_t sys_gmac0_pad_bist_ok_int_raw:1;
+        /** sys_gmac0_pad_bist_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when bist finish and status is bist fail
+         */
+        uint32_t sys_gmac0_pad_bist_fail_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_int_raw_reg_t;
+
+/** Type of sys_gmac0_pad_bist_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_ok_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of gmac0 pad bist ok interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_ok_int_st:1;
+        /** sys_gmac0_pad_bist_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of gmac0 pad bist fail interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_fail_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_int_st_reg_t;
+
+/** Type of sys_gmac0_pad_bist_int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_ok_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable gmac0 pad bist ok interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_ok_int_ena:1;
+        /** sys_gmac0_pad_bist_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable gmac0 pad bist fail interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_fail_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_int_ena_reg_t;
+
+/** Type of sys_gmac0_pad_bist_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_ok_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clr gmac0 pad bist ok interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_ok_int_clr:1;
+        /** sys_gmac0_pad_bist_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clr gmac0 pad bist fail interrupt
+         */
+        uint32_t sys_gmac0_pad_bist_fail_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_int_clr_reg_t;
+
+/** Type of sys_gmac1_pad_bist_int_raw register
+ *  gmac1 pad bist interrupt raw register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_ok_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  intr triggered when bist finish and status is bist ok
+         */
+        uint32_t sys_gmac1_pad_bist_ok_int_raw:1;
+        /** sys_gmac1_pad_bist_fail_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  intr triggered when bist finish and status is bist fail
+         */
+        uint32_t sys_gmac1_pad_bist_fail_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_int_raw_reg_t;
+
+/** Type of sys_gmac1_pad_bist_int_st register
+ *  masked interrupt register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_ok_int_st : RO; bitpos: [0]; default: 0;
+         *  the masked interrupt status of gmac1 pad bist ok interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_ok_int_st:1;
+        /** sys_gmac1_pad_bist_fail_int_st : RO; bitpos: [1]; default: 0;
+         *  the masked interrupt status of gmac1 pad bist fail interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_fail_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_int_st_reg_t;
+
+/** Type of sys_gmac1_pad_bist_int_ena register
+ *  interrupt enable register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_ok_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable gmac1 pad bist ok interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_ok_int_ena:1;
+        /** sys_gmac1_pad_bist_fail_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable gmac1 pad bist fail interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_fail_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_int_ena_reg_t;
+
+/** Type of sys_gmac1_pad_bist_int_clr register
+ *  interrupt clear register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_ok_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clr gmac1 pad bist ok interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_ok_int_clr:1;
+        /** sys_gmac1_pad_bist_fail_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clr gmac1 pad bist fail interrupt
+         */
+        uint32_t sys_gmac1_pad_bist_fail_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_int_clr_reg_t;
+
+
+/** Group: HP_CORE_DMACTIVE_LPCORE_REG */
+/** Type of core_dmactive_lpcore register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_dmactive_lpcore : RO; bitpos: [0]; default: 0;
+         *  hp core dmactive_lpcore value
+         */
+        uint32_t core_dmactive_lpcore:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_core_dmactive_lpcore_reg_t;
+
+
+/** Group: control registers */
+/** Type of core_err_resp_dis register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** core_err_resp_dis : R/W; bitpos: [2:0]; default: 0;
+         *  Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp.  Set bit 2 to
+         *  disable ahb err resp.
+         */
+        uint32_t core_err_resp_dis:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} hp_system_core_err_resp_dis_reg_t;
+
+/** Type of sys_tcm_performace_ctrl register
+ *  need_des
+ */
+typedef union {
+    struct {
+        /** sys_ahb_to_tcm_mem_en_hold : R/W; bitpos: [0]; default: 0;
+         *  Set 1 to keep TCM mem enable hold when mem access is busy.
+         */
+        uint32_t sys_ahb_to_tcm_mem_en_hold:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} hp_system_tcm_performace_ctrl_reg_t;
+
+
+/** Group: Timeout Register */
+/** Type of sys_cpu_peri0_timeout_conf register
+ *  CPU_PERI0_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri0_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Configures the timeout threshold for bus access for accessing CPU peripheral0
+         *  register in the number of clock cycles of the clock domain.
+         */
+        uint32_t sys_cpu_peri0_timeout_thres:16;
+        /** sys_cpu_peri0_timeout_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear timeout interrupt.
+         */
+        uint32_t sys_cpu_peri0_timeout_int_clr:1;
+        /** sys_cpu_peri0_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Configures whether or not to enable timeout protection for accessing CPU
+         *  peripheral0 registers.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sys_cpu_peri0_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_cpu_peri0_timeout_conf_reg_t;
+
+/** Type of sys_cpu_peri0_timeout_addr register
+ *  CPU_PERI0_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri0_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address information of abnormal access.
+         */
+        uint32_t sys_cpu_peri0_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_cpu_peri0_timeout_addr_reg_t;
+
+/** Type of sys_cpu_peri0_timeout_uid register
+ *  CPU_PERI0_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri0_timeout_uid : RO; bitpos: [7:0]; default: 0;
+         *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+         *  register will be cleared after the interrupt is cleared.
+         */
+        uint32_t sys_cpu_peri0_timeout_uid:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_cpu_peri0_timeout_uid_reg_t;
+
+/** Type of sys_hp_system_peri0_timeout_conf register
+ *  HP_PERI0_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri0_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Configures the timeout threshold for bus access for accessing CPU peripheral
+         *  register in the number of clock cycles of the clock domain.
+         */
+        uint32_t sys_hp_system_peri0_timeout_thres:16;
+        /** sys_hp_system_peri0_timeout_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear timeout interrupt.
+         */
+        uint32_t sys_hp_system_peri0_timeout_int_clr:1;
+        /** sys_hp_system_peri0_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Configures whether or not to enable timeout protection for accessing CPU peripheral
+         *  registers.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sys_hp_system_peri0_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri0_timeout_conf_reg_t;
+
+/** Type of sys_hp_system_peri0_timeout_addr register
+ *  HP_PERI0_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri0_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address information of abnormal access.
+         */
+        uint32_t sys_hp_system_peri0_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri0_timeout_addr_reg_t;
+
+/** Type of sys_hp_system_peri0_timeout_uid register
+ *  HP_PERI0_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri0_timeout_uid : RO; bitpos: [7:0]; default: 0;
+         *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+         *  register will be cleared after the interrupt is cleared.
+         */
+        uint32_t sys_hp_system_peri0_timeout_uid:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri0_timeout_uid_reg_t;
+
+/** Type of sys_hp_system_peri1_timeout_conf register
+ *  HP_PERI1_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri1_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Configures the timeout threshold for bus access for accessing CPU peripheral
+         *  register in the number of clock cycles of the clock domain.
+         */
+        uint32_t sys_hp_system_peri1_timeout_thres:16;
+        /** sys_hp_system_peri1_timeout_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear timeout interrupt.
+         */
+        uint32_t sys_hp_system_peri1_timeout_int_clr:1;
+        /** sys_hp_system_peri1_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Configures whether or not to enable timeout protection for accessing CPU peripheral
+         *  registers.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sys_hp_system_peri1_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri1_timeout_conf_reg_t;
+
+/** Type of sys_hp_system_peri1_timeout_addr register
+ *  HP_PERI1_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri1_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address information of abnormal access.
+         */
+        uint32_t sys_hp_system_peri1_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri1_timeout_addr_reg_t;
+
+/** Type of sys_hp_system_peri1_timeout_uid register
+ *  HP_PERI1_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** sys_hp_system_peri1_timeout_uid : RO; bitpos: [7:0]; default: 0;
+         *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+         *  register will be cleared after the interrupt is cleared.
+         */
+        uint32_t sys_hp_system_peri1_timeout_uid:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_hp_system_peri1_timeout_uid_reg_t;
+
+/** Type of sys_cpu_peri1_timeout_conf register
+ *  CPU_PERI1_TIMEOUT configuration register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri1_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
+         *  Configures the timeout threshold for bus access for accessing CPU peripheral
+         *  register in the number of clock cycles of the clock domain.
+         */
+        uint32_t sys_cpu_peri1_timeout_thres:16;
+        /** sys_cpu_peri1_timeout_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear timeout interrupt.
+         */
+        uint32_t sys_cpu_peri1_timeout_int_clr:1;
+        /** sys_cpu_peri1_timeout_protect_en : R/W; bitpos: [17]; default: 1;
+         *  Configures whether or not to enable timeout protection for accessing CPU
+         *  peripheral11 registers.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t sys_cpu_peri1_timeout_protect_en:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} hp_system_cpu_peri1_timeout_conf_reg_t;
+
+/** Type of sys_cpu_peri1_timeout_addr register
+ *  CPU_PERI1_TIMEOUT_ADDR register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri1_timeout_addr : RO; bitpos: [31:0]; default: 0;
+         *  Represents the address information of abnormal access.
+         */
+        uint32_t sys_cpu_peri1_timeout_addr:32;
+    };
+    uint32_t val;
+} hp_system_cpu_peri1_timeout_addr_reg_t;
+
+/** Type of sys_cpu_peri1_timeout_uid register
+ *  CPU_PERI1_TIMEOUT_UID register
+ */
+typedef union {
+    struct {
+        /** sys_cpu_peri1_timeout_uid : RO; bitpos: [7:0]; default: 0;
+         *  Represents the master id[5:0] and master permission[6:5] when trigger timeout. This
+         *  register will be cleared after the interrupt is cleared.
+         */
+        uint32_t sys_cpu_peri1_timeout_uid:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} hp_system_cpu_peri1_timeout_uid_reg_t;
+
+
+/** Group: Status Register */
+/** Type of sys_sdio_pad_bist_st register
+ *  sdio pad bist status register
+ */
+typedef union {
+    struct {
+        /** sys_sdio_pad_bist_rcnt : RO; bitpos: [5:0]; default: 0;
+         *  Indicate number of clock cycles received for pad bist debug
+         */
+        uint32_t sys_sdio_pad_bist_rcnt:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_sdio_pad_bist_st_reg_t;
+
+/** Type of sys_gmac0_pad_bist_st register
+ *  gmac0 pad bist status register
+ */
+typedef union {
+    struct {
+        /** sys_gmac0_pad_bist_rcnt : RO; bitpos: [5:0]; default: 0;
+         *  Indicate number of clock cycles received for pad bist debug
+         */
+        uint32_t sys_gmac0_pad_bist_rcnt:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_gmac0_pad_bist_st_reg_t;
+
+/** Type of sys_gmac1_pad_bist_st register
+ *  gmac1 pad bist status register
+ */
+typedef union {
+    struct {
+        /** sys_gmac1_pad_bist_rcnt : RO; bitpos: [5:0]; default: 0;
+         *  Indicate number of clock cycles received for pad bist debug
+         */
+        uint32_t sys_gmac1_pad_bist_rcnt:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} hp_system_gmac1_pad_bist_st_reg_t;
+
+/** Type of sys_cpu_pwait_mode register
+ *  Indicate status of core0 and core1 pwait
+ */
+typedef union {
+    struct {
+        /** sys_cpu_pwait_mode : RO; bitpos: [1:0]; default: 0;
+         *  Indicate status of core0 and core1 pwait
+         */
+        uint32_t sys_cpu_pwait_mode:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} hp_system_cpu_pwait_mode_reg_t;
+
+
+typedef struct {
+    volatile hp_system_ver_date_reg_t sys_ver_date;
+    volatile hp_system_clk_en_reg_t clk_en;
+    uint32_t reserved_008[2];
+    volatile hp_system_cpu_int_from_cpu_0_reg_t cpu_int_from_cpu_0;
+    volatile hp_system_cpu_int_from_cpu_1_reg_t cpu_int_from_cpu_1;
+    volatile hp_system_cpu_int_from_cpu_2_reg_t cpu_int_from_cpu_2;
+    volatile hp_system_cpu_int_from_cpu_3_reg_t cpu_int_from_cpu_3;
+    uint32_t reserved_020[2];
+    volatile hp_system_modem_diag_en_reg_t modem_diag_en;
+    uint32_t reserved_02c[4];
+    volatile hp_system_tcm_ram_pwr_ctrl0_reg_t tcm_ram_pwr_ctrl0;
+    volatile hp_system_rom_pwr_ctrl0_reg_t rom_pwr_ctrl0;
+    uint32_t reserved_044[3];
+    volatile hp_system_probea_ctrl_reg_t probea_ctrl;
+    volatile hp_system_probeb_ctrl_reg_t probeb_ctrl;
+    uint32_t reserved_058;
+    volatile hp_system_probe_out_reg_t probe_out;
+    uint32_t reserved_060;
+    volatile hp_system_cpu_corestalled_st_reg_t cpu_corestalled_st;
+    uint32_t reserved_068[2];
+    volatile hp_system_crypto_ctrl_reg_t crypto_ctrl;
+    uint32_t reserved_074[2];
+    volatile hp_system_iomux_fpga_debug_reg_t iomux_fpga_debug;
+    volatile hp_system_rdn_eco_cs_reg_t sys_rdn_eco_cs;
+    uint32_t reserved_084[24];
+    volatile hp_system_tcm_rdn_eco_cs_reg_t tcm_rdn_eco_cs;
+    volatile hp_system_tcm_rdn_eco_low_reg_t tcm_rdn_eco_low;
+    volatile hp_system_tcm_rdn_eco_high_reg_t tcm_rdn_eco_high;
+    uint32_t reserved_0f0[8];
+    volatile hp_system_cache_pwr_ctrl_reg_t cache_pwr_ctrl;
+    volatile hp_system_tcm_data_dump_ctrl_reg_t tcm_data_dump_ctrl;
+    volatile hp_system_cpu_waiti_conf_reg_t cpu_waiti_conf;
+    volatile hp_system_core_debug_runstall_conf_reg_t sys_core_debug_runstall_conf;
+    uint32_t reserved_120;
+    volatile hp_system_core_ibus_timeout_conf_reg_t core_ibus_timeout_conf;
+    volatile hp_system_core_dbus_timeout_conf_reg_t core_dbus_timeout_conf;
+    uint32_t reserved_12c[3];
+    volatile hp_system_icm_h2x_cfg_reg_t icm_h2x_cfg;
+    uint32_t reserved_13c;
+    volatile hp_system_bitscrambler_peri_sel_reg_t bitscrambler_peri_sel;
+    uint32_t reserved_144;
+    volatile hp_system_gdma_ctrl_reg_t sys_gdma_ctrl;
+    uint32_t reserved_14c[3];
+    volatile hp_system_vpu_ctrl_reg_t sys_vpu_ctrl;
+    uint32_t reserved_15c[5];
+    volatile hp_system_design_for_verification0_reg_t design_for_verification0;
+    volatile hp_system_design_for_verification1_reg_t design_for_verification1;
+    uint32_t reserved_178[4];
+    volatile hp_system_ahb2axi_bresp_err_int_raw_reg_t ahb2axi_bresp_err_int_raw;
+    volatile hp_system_ahb2axi_bresp_err_int_st_reg_t ahb2axi_bresp_err_int_st;
+    volatile hp_system_ahb2axi_bresp_err_int_ena_reg_t ahb2axi_bresp_err_int_ena;
+    volatile hp_system_ahb2axi_bresp_err_int_clr_reg_t ahb2axi_bresp_err_int_clr;
+    uint32_t reserved_198[2];
+    volatile hp_system_core_dmactive_lpcore_reg_t core_dmactive_lpcore;
+    volatile hp_system_core_err_resp_dis_reg_t core_err_resp_dis;
+    volatile hp_system_core_timeout_int_raw_reg_t core_timeout_int_raw;
+    volatile hp_system_core_timeout_int_st_reg_t core_timeout_int_st;
+    volatile hp_system_core_timeout_int_ena_reg_t core_timeout_int_ena;
+    volatile hp_system_core_timeout_int_clr_reg_t core_timeout_int_clr;
+    volatile hp_system_core_pad_wakeup_event_reg_t core_pad_wakeup_event;
+    uint32_t reserved_1bc;
+    volatile hp_system_twai0_timestamp_l_reg_t twai0_timestamp_l;
+    volatile hp_system_twai0_timestamp_h_reg_t twai0_timestamp_h;
+    volatile hp_system_twai1_timestamp_l_reg_t twai1_timestamp_l;
+    volatile hp_system_twai1_timestamp_h_reg_t twai1_timestamp_h;
+    uint32_t reserved_1d0[2];
+    volatile hp_system_rng_cfg_reg_t rng_cfg;
+    uint32_t reserved_1dc;
+    volatile hp_system_peri_mem_clk_force_on_reg_t peri_mem_clk_force_on;
+    uint32_t reserved_1e4;
+    volatile hp_system_prdyn_st_reg_t sys_prdyn_st;
+    volatile hp_system_icm_cfg_reg_t sys_icm_cfg;
+    volatile hp_system_uart3_mem_lp_ctrl_reg_t sys_uart3_mem_lp_ctrl;
+    uint32_t reserved_1f4[4];
+    volatile hp_system_rmt_mem_lp_ctrl_reg_t sys_rmt_mem_lp_ctrl;
+    volatile hp_system_ledc0_mem_lp_ctrl_reg_t sys_ledc0_mem_lp_ctrl;
+    volatile hp_system_km_mem_lp_ctrl_reg_t sys_km_mem_lp_ctrl;
+    volatile hp_system_dma2d_mem_lp_ctrl_reg_t sys_dma2d_mem_lp_ctrl;
+    volatile hp_system_axi_pdma_mem_lp_ctrl_reg_t sys_axi_pdma_mem_lp_ctrl;
+    volatile hp_system_ecc_mem_lp_ctrl_reg_t sys_ecc_mem_lp_ctrl;
+    volatile hp_system_rsa_mem_lp_ctrl_reg_t sys_rsa_mem_lp_ctrl;
+    volatile hp_system_bitscram_mem_lp_ctrl_reg_t sys_bitscram_mem_lp_ctrl;
+    uint32_t reserved_224;
+    volatile hp_system_can0_mem_lp_ctrl_reg_t sys_can0_mem_lp_ctrl;
+    uint32_t reserved_22c[2];
+    volatile hp_system_mspi_mem_lp_ctrl_reg_t sys_mspi_mem_lp_ctrl;
+    uint32_t reserved_238[5];
+    volatile hp_system_hpcore_mem_lp_ctrl_reg_t sys_hpcore_mem_lp_ctrl;
+    volatile hp_system_rom_mem_lp_ctrl_reg_t sys_rom_mem_lp_ctrl;
+    uint32_t reserved_254[2];
+    volatile hp_system_l1_cache_mem_lp_ctrl_reg_t sys_l1_cache_mem_lp_ctrl;
+    volatile hp_system_kyber_mem_lp_ctrl_reg_t sys_kyber_mem_lp_ctrl;
+    volatile hp_system_lcdcam_mem_lp_ctrl_reg_t sys_lcdcam_mem_lp_ctrl;
+    volatile hp_system_cpu_peri0_timeout_conf_reg_t sys_cpu_peri0_timeout_conf;
+    volatile hp_system_cpu_peri0_timeout_addr_reg_t sys_cpu_peri0_timeout_addr;
+    volatile hp_system_cpu_peri0_timeout_uid_reg_t sys_cpu_peri0_timeout_uid;
+    volatile hp_system_hp_system_peri0_timeout_conf_reg_t sys_hp_system_peri0_timeout_conf;
+    volatile hp_system_hp_system_peri0_timeout_addr_reg_t sys_hp_system_peri0_timeout_addr;
+    volatile hp_system_hp_system_peri0_timeout_uid_reg_t sys_hp_system_peri0_timeout_uid;
+    volatile hp_system_hp_system_peri1_timeout_conf_reg_t sys_hp_system_peri1_timeout_conf;
+    volatile hp_system_hp_system_peri1_timeout_addr_reg_t sys_hp_system_peri1_timeout_addr;
+    volatile hp_system_hp_system_peri1_timeout_uid_reg_t sys_hp_system_peri1_timeout_uid;
+    volatile hp_system_uart0_mem_lp_ctrl_reg_t sys_uart0_mem_lp_ctrl;
+    volatile hp_system_uart1_mem_lp_ctrl_reg_t sys_uart1_mem_lp_ctrl;
+    volatile hp_system_uart2_mem_lp_ctrl_reg_t sys_uart2_mem_lp_ctrl;
+    volatile hp_system_ledc1_mem_lp_ctrl_reg_t sys_ledc1_mem_lp_ctrl;
+    volatile hp_system_ppa_mem_lp_ctrl_reg_t sys_ppa_mem_lp_ctrl;
+    volatile hp_system_jpeg_mem_lp_ctrl_reg_t sys_jpeg_mem_lp_ctrl;
+    volatile hp_system_can1_mem_lp_ctrl_reg_t sys_can1_mem_lp_ctrl;
+    volatile hp_system_cpu_peri1_timeout_conf_reg_t sys_cpu_peri1_timeout_conf;
+    volatile hp_system_cpu_peri1_timeout_addr_reg_t sys_cpu_peri1_timeout_addr;
+    volatile hp_system_cpu_peri1_timeout_uid_reg_t sys_cpu_peri1_timeout_uid;
+    volatile hp_system_cpu_acs_cache_mem_conf_reg_t sys_cpu_acs_cache_mem_conf;
+    uint32_t reserved_2b8[10];
+    volatile hp_system_tcm_performace_ctrl_reg_t sys_tcm_performace_ctrl;
+    volatile hp_system_sdio_pad_bist_cfg_reg_t sys_sdio_pad_bist_cfg;
+    volatile hp_system_sdio_pad_bist_int_raw_reg_t sys_sdio_pad_bist_int_raw;
+    volatile hp_system_sdio_pad_bist_int_st_reg_t sys_sdio_pad_bist_int_st;
+    volatile hp_system_sdio_pad_bist_int_ena_reg_t sys_sdio_pad_bist_int_ena;
+    volatile hp_system_sdio_pad_bist_int_clr_reg_t sys_sdio_pad_bist_int_clr;
+    volatile hp_system_sdio_pad_bist_st_reg_t sys_sdio_pad_bist_st;
+    volatile hp_system_gmac0_pad_bist_cfg_reg_t sys_gmac0_pad_bist_cfg;
+    volatile hp_system_gmac0_pad_bist_int_raw_reg_t sys_gmac0_pad_bist_int_raw;
+    volatile hp_system_gmac0_pad_bist_int_st_reg_t sys_gmac0_pad_bist_int_st;
+    volatile hp_system_gmac0_pad_bist_int_ena_reg_t sys_gmac0_pad_bist_int_ena;
+    volatile hp_system_gmac0_pad_bist_int_clr_reg_t sys_gmac0_pad_bist_int_clr;
+    volatile hp_system_gmac0_pad_bist_st_reg_t sys_gmac0_pad_bist_st;
+    volatile hp_system_gmac1_pad_bist_cfg_reg_t sys_gmac1_pad_bist_cfg;
+    volatile hp_system_gmac1_pad_bist_int_raw_reg_t sys_gmac1_pad_bist_int_raw;
+    volatile hp_system_gmac1_pad_bist_int_st_reg_t sys_gmac1_pad_bist_int_st;
+    volatile hp_system_gmac1_pad_bist_int_ena_reg_t sys_gmac1_pad_bist_int_ena;
+    volatile hp_system_gmac1_pad_bist_int_clr_reg_t sys_gmac1_pad_bist_int_clr;
+    volatile hp_system_gmac1_pad_bist_st_reg_t sys_gmac1_pad_bist_st;
+    uint32_t reserved_32c[3];
+    volatile hp_system_cpu_pwait_mode_reg_t sys_cpu_pwait_mode;
+} hp_system_dev_t;
+
+extern hp_system_dev_t HP_SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(hp_system_dev_t) == 0x33c, "Invalid size of hp_system_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/huk_reg.h b/components/soc/esp32s31/register/soc/huk_reg.h
new file mode 100644
index 00000000000..20c44c4d3dd
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/huk_reg.h
@@ -0,0 +1,230 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** HUK_CLK_REG register
+ *  HUK Generator clock gate control register
+ */
+#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
+/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Write 1 to force on register clock gate.
+ */
+#define HUK_CLK_EN    (BIT(0))
+#define HUK_CLK_EN_M  (HUK_CLK_EN_V << HUK_CLK_EN_S)
+#define HUK_CLK_EN_V  0x00000001U
+#define HUK_CLK_EN_S  0
+/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to force on memory clock gate.
+ */
+#define HUK_MEM_CG_FORCE_ON    (BIT(1))
+#define HUK_MEM_CG_FORCE_ON_M  (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
+#define HUK_MEM_CG_FORCE_ON_V  0x00000001U
+#define HUK_MEM_CG_FORCE_ON_S  1
+
+/** HUK_INT_RAW_REG register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
+/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_RAW    (BIT(0))
+#define HUK_PREP_DONE_INT_RAW_M  (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
+#define HUK_PREP_DONE_INT_RAW_V  0x00000001U
+#define HUK_PREP_DONE_INT_RAW_S  0
+/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_RAW    (BIT(1))
+#define HUK_PROC_DONE_INT_RAW_M  (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
+#define HUK_PROC_DONE_INT_RAW_V  0x00000001U
+#define HUK_PROC_DONE_INT_RAW_S  1
+/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_RAW    (BIT(2))
+#define HUK_POST_DONE_INT_RAW_M  (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
+#define HUK_POST_DONE_INT_RAW_V  0x00000001U
+#define HUK_POST_DONE_INT_RAW_S  2
+
+/** HUK_INT_ST_REG register
+ *  HUK Generator interrupt status register.
+ */
+#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
+/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ST    (BIT(0))
+#define HUK_PREP_DONE_INT_ST_M  (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
+#define HUK_PREP_DONE_INT_ST_V  0x00000001U
+#define HUK_PREP_DONE_INT_ST_S  0
+/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ST    (BIT(1))
+#define HUK_PROC_DONE_INT_ST_M  (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
+#define HUK_PROC_DONE_INT_ST_V  0x00000001U
+#define HUK_PROC_DONE_INT_ST_S  1
+/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ST    (BIT(2))
+#define HUK_POST_DONE_INT_ST_M  (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
+#define HUK_POST_DONE_INT_ST_V  0x00000001U
+#define HUK_POST_DONE_INT_ST_S  2
+
+/** HUK_INT_ENA_REG register
+ *  HUK Generator interrupt enable register.
+ */
+#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
+/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_ENA    (BIT(0))
+#define HUK_PREP_DONE_INT_ENA_M  (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
+#define HUK_PREP_DONE_INT_ENA_V  0x00000001U
+#define HUK_PREP_DONE_INT_ENA_S  0
+/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_ENA    (BIT(1))
+#define HUK_PROC_DONE_INT_ENA_M  (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
+#define HUK_PROC_DONE_INT_ENA_V  0x00000001U
+#define HUK_PROC_DONE_INT_ENA_S  1
+/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_ENA    (BIT(2))
+#define HUK_POST_DONE_INT_ENA_M  (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
+#define HUK_POST_DONE_INT_ENA_V  0x00000001U
+#define HUK_POST_DONE_INT_ENA_S  2
+
+/** HUK_INT_CLR_REG register
+ *  HUK Generator interrupt clear register.
+ */
+#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
+/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the huk_prep_done_int interrupt
+ */
+#define HUK_PREP_DONE_INT_CLR    (BIT(0))
+#define HUK_PREP_DONE_INT_CLR_M  (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
+#define HUK_PREP_DONE_INT_CLR_V  0x00000001U
+#define HUK_PREP_DONE_INT_CLR_S  0
+/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the huk_proc_done_int interrupt
+ */
+#define HUK_PROC_DONE_INT_CLR    (BIT(1))
+#define HUK_PROC_DONE_INT_CLR_M  (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
+#define HUK_PROC_DONE_INT_CLR_V  0x00000001U
+#define HUK_PROC_DONE_INT_CLR_S  1
+/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the huk_post_done_int interrupt
+ */
+#define HUK_POST_DONE_INT_CLR    (BIT(2))
+#define HUK_POST_DONE_INT_CLR_M  (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
+#define HUK_POST_DONE_INT_CLR_V  0x00000001U
+#define HUK_POST_DONE_INT_CLR_S  2
+
+/** HUK_CONF_REG register
+ *  HUK Generator configuration register
+ */
+#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
+/** HUK_MODE : R/W; bitpos: [0]; default: 0;
+ *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+ *  huk recovery mode.
+ */
+#define HUK_MODE    (BIT(0))
+#define HUK_MODE_M  (HUK_MODE_V << HUK_MODE_S)
+#define HUK_MODE_V  0x00000001U
+#define HUK_MODE_S  0
+
+/** HUK_START_REG register
+ *  HUK Generator control register
+ */
+#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
+/** HUK_START : WT; bitpos: [0]; default: 0;
+ *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+ */
+#define HUK_START    (BIT(0))
+#define HUK_START_M  (HUK_START_V << HUK_START_S)
+#define HUK_START_V  0x00000001U
+#define HUK_START_S  0
+/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
+ *  Write 1 to start HUK Generator at IDLE state.
+ */
+#define HUK_CONTINUE    (BIT(1))
+#define HUK_CONTINUE_M  (HUK_CONTINUE_V << HUK_CONTINUE_S)
+#define HUK_CONTINUE_V  0x00000001U
+#define HUK_CONTINUE_S  1
+
+/** HUK_STATE_REG register
+ *  HUK Generator state register
+ */
+#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
+/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
+ *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+ */
+#define HUK_STATE    0x00000003U
+#define HUK_STATE_M  (HUK_STATE_V << HUK_STATE_S)
+#define HUK_STATE_V  0x00000003U
+#define HUK_STATE_S  0
+
+/** HUK_STATUS_REG register
+ *  HUK Generator HUK status register
+ */
+#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
+/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
+ *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+ *  2: HUK is generated but invalid. 3: reserved.
+ */
+#define HUK_STATUS    0x00000003U
+#define HUK_STATUS_M  (HUK_STATUS_V << HUK_STATUS_S)
+#define HUK_STATUS_V  0x00000003U
+#define HUK_STATUS_S  0
+/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
+ *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+ *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+ */
+#define HUK_RISK_LEVEL    0x00000007U
+#define HUK_RISK_LEVEL_M  (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
+#define HUK_RISK_LEVEL_V  0x00000007U
+#define HUK_RISK_LEVEL_S  2
+/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
+ *  The update request of HUK info. 0: User can update HUK info according to the risk
+ *  level. 1: The HUK info is expired, and user need to update it.
+ */
+#define HUK_UPDATE_REQ    (BIT(5))
+#define HUK_UPDATE_REQ_M  (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
+#define HUK_UPDATE_REQ_V  0x00000001U
+#define HUK_UPDATE_REQ_S  5
+
+/** HUK_DATE_REG register
+ *  Version control register
+ */
+#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
+/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
+ *  HUK Generator version control register.
+ */
+#define HUK_DATE    0x0FFFFFFFU
+#define HUK_DATE_M  (HUK_DATE_V << HUK_DATE_S)
+#define HUK_DATE_V  0x0FFFFFFFU
+#define HUK_DATE_S  0
+
+/** HUK_INFO_MEM register
+ *  The memory that stores HUK info.
+ */
+#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
+#define HUK_INFO_MEM_SIZE_BYTES 384
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/huk_struct.h b/components/soc/esp32s31/register/soc/huk_struct.h
new file mode 100644
index 00000000000..493057a3131
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/huk_struct.h
@@ -0,0 +1,246 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Memory data */
+
+/** Group: Clock gate register */
+/** Type of clk register
+ *  HUK Generator clock gate control register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Write 1 to force on register clock gate.
+         */
+        uint32_t clk_en:1;
+        /** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to force on memory clock gate.
+         */
+        uint32_t mem_cg_force_on:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_clk_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  HUK Generator interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_raw:1;
+        /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_raw:1;
+        /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_raw:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_raw_reg_t;
+
+/** Type of int_st register
+ *  HUK Generator interrupt status register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_st:1;
+        /** proc_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_st:1;
+        /** post_done_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_st:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_st_reg_t;
+
+/** Type of int_ena register
+ *  HUK Generator interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_ena:1;
+        /** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_ena:1;
+        /** post_done_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_ena:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  HUK Generator interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** prep_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the huk_prep_done_int interrupt
+         */
+        uint32_t prep_done_int_clr:1;
+        /** proc_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the huk_proc_done_int interrupt
+         */
+        uint32_t proc_done_int_clr:1;
+        /** post_done_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the huk_post_done_int interrupt
+         */
+        uint32_t post_done_int_clr:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} huk_int_clr_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of conf register
+ *  HUK Generator configuration register
+ */
+typedef union {
+    struct {
+        /** mode : R/W; bitpos: [0]; default: 0;
+         *  Set this field to choose the huk process. 1: process huk generate mode. 0: process
+         *  huk recovery mode.
+         */
+        uint32_t mode:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} huk_conf_reg_t;
+
+
+/** Group: Control registers */
+/** Type of start register
+ *  HUK Generator control register
+ */
+typedef union {
+    struct {
+        /** start : WT; bitpos: [0]; default: 0;
+         *  Write 1 to continue HUK Generator operation at LOAD/GAIN state.
+         */
+        uint32_t start:1;
+        /** continue : WT; bitpos: [1]; default: 0;
+         *  Write 1 to start HUK Generator at IDLE state.
+         */
+        uint32_t continue:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_start_reg_t;
+
+
+/** Group: State registers */
+/** Type of state register
+ *  HUK Generator state register
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [1:0]; default: 0;
+         *  The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
+         */
+        uint32_t state:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} huk_state_reg_t;
+
+
+/** Group: Result registers */
+/** Type of status register
+ *  HUK Generator HUK status register
+ */
+typedef union {
+    struct {
+        /** status : RO; bitpos: [1:0]; default: 0;
+         *  The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
+         *  2: HUK is generated but invalid. 3: reserved.
+         */
+        uint32_t status:2;
+        /** risk_level : RO; bitpos: [4:2]; default: 0;
+         *  The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
+         *  are in the PUF SRAM. 7: Error Level, HUK is invalid.
+         */
+        uint32_t risk_level:3;
+        /** update_req : RO; bitpos: [5]; default: 0;
+         *  The update request of HUK info. 0: User can update HUK info according to the risk
+         *  level. 1: The HUK info is expired, and user need to update it.
+         */
+        uint32_t update_req:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} huk_status_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 37765232;
+         *  HUK Generator version control register.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} huk_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000;
+    volatile huk_clk_reg_t clk;
+    volatile huk_int_raw_reg_t int_raw;
+    volatile huk_int_st_reg_t int_st;
+    volatile huk_int_ena_reg_t int_ena;
+    volatile huk_int_clr_reg_t int_clr;
+    uint32_t reserved_018[2];
+    volatile huk_conf_reg_t conf;
+    volatile huk_start_reg_t start;
+    volatile huk_state_reg_t state;
+    uint32_t reserved_02c[2];
+    volatile huk_status_reg_t status;
+    uint32_t reserved_038[49];
+    volatile huk_date_reg_t date;
+    volatile uint32_t info[96];
+} huk_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/i2c_reg.h b/components/soc/esp32s31/register/soc/i2c_reg.h
new file mode 100644
index 00000000000..806dca7f442
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/i2c_reg.h
@@ -0,0 +1,1478 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2C_SCL_LOW_PERIOD_REG register
+ *  Configures the low level width of the SCL Clock
+ */
+#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0)
+/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the low level width of the SCL Clock in Master mode.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_LOW_PERIOD    0x000001FFU
+#define I2C_SCL_LOW_PERIOD_M  (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S)
+#define I2C_SCL_LOW_PERIOD_V  0x000001FFU
+#define I2C_SCL_LOW_PERIOD_S  0
+
+/** I2C_CTR_REG register
+ *  Transmission setting register
+ */
+#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4)
+/** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
+ *  Configures the SDA output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SDA_FORCE_OUT    (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S)
+#define I2C_SDA_FORCE_OUT_V  0x00000001U
+#define I2C_SDA_FORCE_OUT_S  0
+/** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
+ *  Configures the SCL output mode.
+ *  0: Open drain output
+ *  1: Direct output
+ */
+#define I2C_SCL_FORCE_OUT    (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S)
+#define I2C_SCL_FORCE_OUT_V  0x00000001U
+#define I2C_SCL_FORCE_OUT_S  1
+/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0;
+ *  Configures the sample mode for SDA.
+ *  0: Sample SDA data on the SCL high level
+ *  1: Sample SDA data on the SCL low level
+ */
+#define I2C_SAMPLE_SCL_LEVEL    (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S)
+#define I2C_SAMPLE_SCL_LEVEL_V  0x00000001U
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1;
+ *  Configures the ACK value that needs to be sent by master when rx_fifo_cnt has
+ *  reached the threshold.
+ */
+#define I2C_RX_FULL_ACK_LEVEL    (BIT(3))
+#define I2C_RX_FULL_ACK_LEVEL_M  (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S)
+#define I2C_RX_FULL_ACK_LEVEL_V  0x00000001U
+#define I2C_RX_FULL_ACK_LEVEL_S  3
+/** I2C_MS_MODE : R/W; bitpos: [4]; default: 0;
+ *  Configures the module as an I2C Master or Slave.
+ *  0: Slave
+ *  1: Master
+ */
+#define I2C_MS_MODE    (BIT(4))
+#define I2C_MS_MODE_M  (I2C_MS_MODE_V << I2C_MS_MODE_S)
+#define I2C_MS_MODE_V  0x00000001U
+#define I2C_MS_MODE_S  4
+/** I2C_TRANS_START : WT; bitpos: [5]; default: 0;
+ *  Configures whether the slave starts sending the data in TX FIFO.
+ *  0: No effect
+ *  1: Start
+ */
+#define I2C_TRANS_START    (BIT(5))
+#define I2C_TRANS_START_M  (I2C_TRANS_START_V << I2C_TRANS_START_S)
+#define I2C_TRANS_START_V  0x00000001U
+#define I2C_TRANS_START_S  5
+/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to control the sending order for data needing to be sent.
+ *  0: Send data from the most significant bit
+ *  1: Send data from the least significant bit
+ */
+#define I2C_TX_LSB_FIRST    (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S)
+#define I2C_TX_LSB_FIRST_V  0x00000001U
+#define I2C_TX_LSB_FIRST_S  6
+/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to control the storage order for received data.
+ *  0: Receive data from the most significant bit
+ *  1: Receive data from the least significant bit
+ */
+#define I2C_RX_LSB_FIRST    (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S)
+#define I2C_RX_LSB_FIRST_V  0x00000001U
+#define I2C_RX_LSB_FIRST_S  7
+/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Configures whether to gate clock signal for registers.
+ *  0: Support clock only when registers are read or written to by software
+ *  1: Force clock on for registers
+ */
+#define I2C_CLK_EN    (BIT(8))
+#define I2C_CLK_EN_M  (I2C_CLK_EN_V << I2C_CLK_EN_S)
+#define I2C_CLK_EN_V  0x00000001U
+#define I2C_CLK_EN_S  8
+/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures whether to enable I2C bus arbitration detection.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ARBITRATION_EN    (BIT(9))
+#define I2C_ARBITRATION_EN_M  (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S)
+#define I2C_ARBITRATION_EN_V  0x00000001U
+#define I2C_ARBITRATION_EN_S  9
+/** I2C_FSM_RST : WT; bitpos: [10]; default: 0;
+ *  Configures whether to reset the SCL_FSM.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_FSM_RST    (BIT(10))
+#define I2C_FSM_RST_M  (I2C_FSM_RST_V << I2C_FSM_RST_S)
+#define I2C_FSM_RST_V  0x00000001U
+#define I2C_FSM_RST_S  10
+/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0;
+ *  Configures the bit for synchronization.
+ *  0: No effect
+ *  1: Synchronize
+ */
+#define I2C_CONF_UPGATE    (BIT(11))
+#define I2C_CONF_UPGATE_M  (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S)
+#define I2C_CONF_UPGATE_V  0x00000001U
+#define I2C_CONF_UPGATE_S  11
+/** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable slave to send data automatically
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLV_TX_AUTO_START_EN    (BIT(12))
+#define I2C_SLV_TX_AUTO_START_EN_M  (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S)
+#define I2C_SLV_TX_AUTO_START_EN_V  0x00000001U
+#define I2C_SLV_TX_AUTO_START_EN_S  12
+/** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0;
+ *  Configures whether to check if the $R/\overline W$ bit of 10-bit addressing
+ *  consists with I2C protocol.
+ *  0: Not check
+ *  1: Check
+ */
+#define I2C_ADDR_10BIT_RW_CHECK_EN    (BIT(13))
+#define I2C_ADDR_10BIT_RW_CHECK_EN_M  (I2C_ADDR_10BIT_RW_CHECK_EN_V << I2C_ADDR_10BIT_RW_CHECK_EN_S)
+#define I2C_ADDR_10BIT_RW_CHECK_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_RW_CHECK_EN_S  13
+/** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0;
+ *  Configures whether to support the 7-bit general call function.
+ *  0: Not support
+ *  1: Support
+ */
+#define I2C_ADDR_BROADCASTING_EN    (BIT(14))
+#define I2C_ADDR_BROADCASTING_EN_M  (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S)
+#define I2C_ADDR_BROADCASTING_EN_V  0x00000001U
+#define I2C_ADDR_BROADCASTING_EN_S  14
+
+/** I2C_SR_REG register
+ *  I2C working status register
+ */
+#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8)
+/** I2C_RESP_REC : RO; bitpos: [0]; default: 0;
+ *  Represents the received ACK value in Master mode or Slave mode.
+ *  0: ACK
+ *  1: NACK
+ */
+#define I2C_RESP_REC    (BIT(0))
+#define I2C_RESP_REC_M  (I2C_RESP_REC_V << I2C_RESP_REC_S)
+#define I2C_RESP_REC_V  0x00000001U
+#define I2C_RESP_REC_S  0
+/** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
+ *  Represents the transfer direction in Slave mode.
+ *  0: Master writes to slave
+ *  1: Master reads from slave
+ */
+#define I2C_SLAVE_RW    (BIT(1))
+#define I2C_SLAVE_RW_M  (I2C_SLAVE_RW_V << I2C_SLAVE_RW_S)
+#define I2C_SLAVE_RW_V  0x00000001U
+#define I2C_SLAVE_RW_S  1
+/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0;
+ *  Represents whether the I2C controller loses control of SCL line.
+ *  0: No arbitration lost
+ *  1: Arbitration lost
+ */
+#define I2C_ARB_LOST    (BIT(3))
+#define I2C_ARB_LOST_M  (I2C_ARB_LOST_V << I2C_ARB_LOST_S)
+#define I2C_ARB_LOST_V  0x00000001U
+#define I2C_ARB_LOST_S  3
+/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0;
+ *  Represents the I2C bus state.
+ *  0: The I2C bus is in idle state
+ *  1: The I2C bus is busy transferring data
+ */
+#define I2C_BUS_BUSY    (BIT(4))
+#define I2C_BUS_BUSY_M  (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S)
+#define I2C_BUS_BUSY_V  0x00000001U
+#define I2C_BUS_BUSY_S  4
+/** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0;
+ *  Represents whether the address sent by the master is equal to the address of the
+ *  slave.
+ *  Valid only when the module is configured as an I2C Slave.
+ *  0: Not equal
+ *  1: Equal
+ */
+#define I2C_SLAVE_ADDRESSED    (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S)
+#define I2C_SLAVE_ADDRESSED_V  0x00000001U
+#define I2C_SLAVE_ADDRESSED_S  5
+/** I2C_RXFIFO_CNT : RO; bitpos: [13:8]; default: 0;
+ *  Represents the number of data bytes received in RAM.
+ */
+#define I2C_RXFIFO_CNT    0x0000003FU
+#define I2C_RXFIFO_CNT_M  (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S)
+#define I2C_RXFIFO_CNT_V  0x0000003FU
+#define I2C_RXFIFO_CNT_S  8
+/** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3;
+ *  Represents the cause of SCL clocking stretching in Slave mode.
+ *  0: Stretching SCL low when the master starts to read data.
+ *  1: Stretching SCL low when I2C TX FIFO is empty in Slave mode.
+ *  2: Stretching SCL low when I2C RX FIFO is full in Slave mode.
+ */
+#define I2C_STRETCH_CAUSE    0x00000003U
+#define I2C_STRETCH_CAUSE_M  (I2C_STRETCH_CAUSE_V << I2C_STRETCH_CAUSE_S)
+#define I2C_STRETCH_CAUSE_V  0x00000003U
+#define I2C_STRETCH_CAUSE_S  14
+/** I2C_TXFIFO_CNT : RO; bitpos: [23:18]; default: 0;
+ *  Represents the number of data bytes to be sent.
+ */
+#define I2C_TXFIFO_CNT    0x0000003FU
+#define I2C_TXFIFO_CNT_M  (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S)
+#define I2C_TXFIFO_CNT_V  0x0000003FU
+#define I2C_TXFIFO_CNT_S  18
+/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
+ *  Represents the states of the I2C module state machine.
+ *  0: Idle
+ *  1: Address shift
+ *  2: ACK address
+ *  3: Rx data
+ *  4: Tx data
+ *  5: Send ACK
+ *  6: Wait ACK
+ */
+#define I2C_SCL_MAIN_STATE_LAST    0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_M  (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S)
+#define I2C_SCL_MAIN_STATE_LAST_V  0x00000007U
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
+ *  Represents the states of the state machine used to produce SCL.
+ *  0: Idle
+ *  1: Start
+ *  2: Negative edge
+ *  3: Low
+ *  4: Positive edge
+ *  5: High
+ *  6: Stop
+ */
+#define I2C_SCL_STATE_LAST    0x00000007U
+#define I2C_SCL_STATE_LAST_M  (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S)
+#define I2C_SCL_STATE_LAST_V  0x00000007U
+#define I2C_SCL_STATE_LAST_S  28
+
+/** I2C_TO_REG register
+ *  Timeout control register for receiving data
+ */
+#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc)
+/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the timeout threshold period for SCL stucking at high or low level. The
+ *  actual period is 2\^{}(reg_time_out_value).
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_TIME_OUT_VALUE    0x0000001FU
+#define I2C_TIME_OUT_VALUE_M  (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S)
+#define I2C_TIME_OUT_VALUE_V  0x0000001FU
+#define I2C_TIME_OUT_VALUE_S  0
+/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0;
+ *  Configures whether to enable timeout control.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_TIME_OUT_EN    (BIT(5))
+#define I2C_TIME_OUT_EN_M  (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S)
+#define I2C_TIME_OUT_EN_V  0x00000001U
+#define I2C_TIME_OUT_EN_S  5
+
+/** I2C_SLAVE_ADDR_REG register
+ *  Local slave address setting register
+ */
+#define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10)
+/** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
+ *  Configures the slave address of the I2C slave.
+ */
+#define I2C_SLAVE_ADDR    0x00007FFFU
+#define I2C_SLAVE_ADDR_M  (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S)
+#define I2C_SLAVE_ADDR_V  0x00007FFFU
+#define I2C_SLAVE_ADDR_S  0
+/** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
+ *  Configures whether to enable the slave 10-bit addressing mode in Master mode.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_ADDR_10BIT_EN    (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S)
+#define I2C_ADDR_10BIT_EN_V  0x00000001U
+#define I2C_ADDR_10BIT_EN_S  31
+
+/** I2C_FIFO_ST_REG register
+ *  FIFO status register
+ */
+#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14)
+/** I2C_RXFIFO_RADDR : RO; bitpos: [4:0]; default: 0;
+ *  Represents the offset address of the APB reading from RX FIFO.
+ */
+#define I2C_RXFIFO_RADDR    0x0000001FU
+#define I2C_RXFIFO_RADDR_M  (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S)
+#define I2C_RXFIFO_RADDR_V  0x0000001FU
+#define I2C_RXFIFO_RADDR_S  0
+/** I2C_RXFIFO_WADDR : RO; bitpos: [9:5]; default: 0;
+ *  Represents the offset address of i2c module receiving data and writing to RX FIFO.
+ */
+#define I2C_RXFIFO_WADDR    0x0000001FU
+#define I2C_RXFIFO_WADDR_M  (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S)
+#define I2C_RXFIFO_WADDR_V  0x0000001FU
+#define I2C_RXFIFO_WADDR_S  5
+/** I2C_TXFIFO_RADDR : RO; bitpos: [14:10]; default: 0;
+ *  Represents the offset address of I2C module reading from TX FIFO.
+ */
+#define I2C_TXFIFO_RADDR    0x0000001FU
+#define I2C_TXFIFO_RADDR_M  (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S)
+#define I2C_TXFIFO_RADDR_V  0x0000001FU
+#define I2C_TXFIFO_RADDR_S  10
+/** I2C_TXFIFO_WADDR : RO; bitpos: [19:15]; default: 0;
+ *  Represents the offset address of APB bus writing to TX FIFO.
+ */
+#define I2C_TXFIFO_WADDR    0x0000001FU
+#define I2C_TXFIFO_WADDR_M  (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S)
+#define I2C_TXFIFO_WADDR_V  0x0000001FU
+#define I2C_TXFIFO_WADDR_S  15
+/** I2C_SLAVE_RW_POINT : RO; bitpos: [29:22]; default: 0;
+ *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+ *  I2C Slave mode.
+ */
+#define I2C_SLAVE_RW_POINT    0x000000FFU
+#define I2C_SLAVE_RW_POINT_M  (I2C_SLAVE_RW_POINT_V << I2C_SLAVE_RW_POINT_S)
+#define I2C_SLAVE_RW_POINT_V  0x000000FFU
+#define I2C_SLAVE_RW_POINT_S  22
+
+/** I2C_FIFO_CONF_REG register
+ *  FIFO configuration register
+ */
+#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18)
+/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [4:0]; default: 11;
+ *  Configures the watermark threshold of RX FIFO in non-FIFO access mode. When
+ *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+ *  the I2C_RXFIFO_WM_INT_RAW bit will be valid.
+ */
+#define I2C_RXFIFO_WM_THRHD    0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_M  (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S)
+#define I2C_RXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_RXFIFO_WM_THRHD_S  0
+/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [9:5]; default: 4;
+ *  Configures the watermark threshold of TX FIFO in non-FIFO access mode.  When
+ *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+ *  the I2C_TXFIFO_WM_INT_RAW bit will be valid.
+ */
+#define I2C_TXFIFO_WM_THRHD    0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_M  (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S)
+#define I2C_TXFIFO_WM_THRHD_V  0x0000001FU
+#define I2C_TXFIFO_WM_THRHD_S  5
+/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether to enable APB non-FIFO access.
+ */
+#define I2C_NONFIFO_EN    (BIT(10))
+#define I2C_NONFIFO_EN_M  (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S)
+#define I2C_NONFIFO_EN_V  0x00000001U
+#define I2C_NONFIFO_EN_S  10
+/** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0;
+ *  Configures the slave to enable dual address mode. When this mode is enabled, the
+ *  byte received after the I2C address byte represents the offset address in the I2C
+ *  Slave RAM.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_FIFO_ADDR_CFG_EN    (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S)
+#define I2C_FIFO_ADDR_CFG_EN_V  0x00000001U
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0;
+ *  Configures whether or not to reset RX FIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_RX_FIFO_RST    (BIT(12))
+#define I2C_RX_FIFO_RST_M  (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S)
+#define I2C_RX_FIFO_RST_V  0x00000001U
+#define I2C_RX_FIFO_RST_S  12
+/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0;
+ *  Configures whether or not to reset TX FIFO.
+ *  0: No effect
+ *  1: Reset
+ */
+#define I2C_TX_FIFO_RST    (BIT(13))
+#define I2C_TX_FIFO_RST_M  (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S)
+#define I2C_TX_FIFO_RST_V  0x00000001U
+#define I2C_TX_FIFO_RST_S  13
+/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1;
+ *  Configures whether to enable FIFO pointer in non-FIFO access mode. This bit
+ *  controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty
+ *  interrupts.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_FIFO_PRT_EN    (BIT(14))
+#define I2C_FIFO_PRT_EN_M  (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S)
+#define I2C_FIFO_PRT_EN_V  0x00000001U
+#define I2C_FIFO_PRT_EN_S  14
+
+/** I2C_DATA_REG register
+ *  Rx FIFO read data
+ */
+#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c)
+/** I2C_FIFO_RDATA : HRO; bitpos: [7:0]; default: 0;
+ *  Represents the value of RXFIFO read data.
+ */
+#define I2C_FIFO_RDATA    0x000000FFU
+#define I2C_FIFO_RDATA_M  (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S)
+#define I2C_FIFO_RDATA_V  0x000000FFU
+#define I2C_FIFO_RDATA_S  0
+
+/** I2C_INT_RAW_REG register
+ *  Raw interrupt status register
+ */
+#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20)
+/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_WM_INT.
+ */
+#define I2C_RXFIFO_WM_INT_RAW    (BIT(0))
+#define I2C_RXFIFO_WM_INT_RAW_M  (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S)
+#define I2C_RXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_RAW_S  0
+/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1;
+ *  The raw interrupt status of I2C_TXFIFO_WM_INT.
+ */
+#define I2C_TXFIFO_WM_INT_RAW    (BIT(1))
+#define I2C_TXFIFO_WM_INT_RAW_M  (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S)
+#define I2C_TXFIFO_WM_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_RAW_S  1
+/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_OVF_INT.
+ */
+#define I2C_RXFIFO_OVF_INT_RAW    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S)
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0;
+ *  The raw interrupt status of I2C_END_DETECT_INT.
+ */
+#define I2C_END_DETECT_INT_RAW    (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S)
+#define I2C_END_DETECT_INT_RAW_V  0x00000001U
+#define I2C_END_DETECT_INT_RAW_S  3
+/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0;
+ *  The raw interrupt status of I2C_BYTE_TRANS_DONE_INT.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_RAW    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_RAW_M  (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S)
+#define I2C_BYTE_TRANS_DONE_INT_RAW_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_RAW_S  4
+/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0;
+ *  The raw interrupt status of I2C_ARBITRATION_LOST_INT.
+ */
+#define I2C_ARBITRATION_LOST_INT_RAW    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S)
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0;
+ *  The raw interrupt status of I2C_MST_TXFIFO_UDF_INT.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_RAW    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_RAW_M  (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S)
+#define I2C_MST_TXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_RAW_S  6
+/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0;
+ *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT.
+ */
+#define I2C_TRANS_COMPLETE_INT_RAW    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S)
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0;
+ *  The raw interrupt status of I2C_TIME_OUT_INT.
+ */
+#define I2C_TIME_OUT_INT_RAW    (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S)
+#define I2C_TIME_OUT_INT_RAW_V  0x00000001U
+#define I2C_TIME_OUT_INT_RAW_S  8
+/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0;
+ *  The raw interrupt status of I2C_TRANS_START_INT.
+ */
+#define I2C_TRANS_START_INT_RAW    (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S)
+#define I2C_TRANS_START_INT_RAW_V  0x00000001U
+#define I2C_TRANS_START_INT_RAW_S  9
+/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0;
+ *  The raw interrupt status of I2C_NACK_INT.
+ */
+#define I2C_NACK_INT_RAW    (BIT(10))
+#define I2C_NACK_INT_RAW_M  (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S)
+#define I2C_NACK_INT_RAW_V  0x00000001U
+#define I2C_NACK_INT_RAW_S  10
+/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0;
+ *  The raw interrupt status of I2C_TXFIFO_OVF_INT.
+ */
+#define I2C_TXFIFO_OVF_INT_RAW    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_RAW_M  (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S)
+#define I2C_TXFIFO_OVF_INT_RAW_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_RAW_S  11
+/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0;
+ *  The raw interrupt status of I2C_RXFIFO_UDF_INT.
+ */
+#define I2C_RXFIFO_UDF_INT_RAW    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_RAW_M  (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S)
+#define I2C_RXFIFO_UDF_INT_RAW_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_RAW_S  12
+/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0;
+ *  The raw interrupt status of I2C_SCL_ST_TO_INT.
+ */
+#define I2C_SCL_ST_TO_INT_RAW    (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S)
+#define I2C_SCL_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0;
+ *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S)
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0;
+ *  The raw interrupt status of I2C_DET_START_INT.
+ */
+#define I2C_DET_START_INT_RAW    (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S)
+#define I2C_DET_START_INT_RAW_V  0x00000001U
+#define I2C_DET_START_INT_RAW_S  15
+/** I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC; bitpos: [16]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_STRETCH_INT.
+ */
+#define I2C_SLAVE_STRETCH_INT_RAW    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_RAW_M  (I2C_SLAVE_STRETCH_INT_RAW_V << I2C_SLAVE_STRETCH_INT_RAW_S)
+#define I2C_SLAVE_STRETCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_RAW_S  16
+/** I2C_GENERAL_CALL_INT_RAW : R/SS/WTC; bitpos: [17]; default: 0;
+ *  The raw interrupt status of I2C_GENERAL_CALL_INT.
+ */
+#define I2C_GENERAL_CALL_INT_RAW    (BIT(17))
+#define I2C_GENERAL_CALL_INT_RAW_M  (I2C_GENERAL_CALL_INT_RAW_V << I2C_GENERAL_CALL_INT_RAW_S)
+#define I2C_GENERAL_CALL_INT_RAW_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_RAW_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_RAW : R/SS/WTC; bitpos: [18]; default: 0;
+ *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_M  (I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V << I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_RAW_S  18
+
+/** I2C_INT_CLR_REG register
+ *  Interrupt clear register
+ */
+#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24)
+/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_WM_INT.
+ */
+#define I2C_RXFIFO_WM_INT_CLR    (BIT(0))
+#define I2C_RXFIFO_WM_INT_CLR_M  (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S)
+#define I2C_RXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_CLR_S  0
+/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_WM_INT.
+ */
+#define I2C_TXFIFO_WM_INT_CLR    (BIT(1))
+#define I2C_TXFIFO_WM_INT_CLR_M  (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S)
+#define I2C_TXFIFO_WM_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_CLR_S  1
+/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_OVF_INT.
+ */
+#define I2C_RXFIFO_OVF_INT_CLR    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S)
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Write 1 to clear I2C_END_DETECT_INT.
+ */
+#define I2C_END_DETECT_INT_CLR    (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S)
+#define I2C_END_DETECT_INT_CLR_V  0x00000001U
+#define I2C_END_DETECT_INT_CLR_S  3
+/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Write 1 to clear I2C_BYTE_TRANS_DONE_INT.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_CLR    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_CLR_M  (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S)
+#define I2C_BYTE_TRANS_DONE_INT_CLR_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_CLR_S  4
+/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Write 1 to clear I2C_ARBITRATION_LOST_INT.
+ */
+#define I2C_ARBITRATION_LOST_INT_CLR    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S)
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Write 1 to clear I2C_MST_TXFIFO_UDF_INT.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_CLR    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_CLR_M  (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S)
+#define I2C_MST_TXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_CLR_S  6
+/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Write 1 to clear I2C_TRANS_COMPLETE_INT.
+ */
+#define I2C_TRANS_COMPLETE_INT_CLR    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S)
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Write 1 to clear I2C_TIME_OUT_INT.
+ */
+#define I2C_TIME_OUT_INT_CLR    (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S)
+#define I2C_TIME_OUT_INT_CLR_V  0x00000001U
+#define I2C_TIME_OUT_INT_CLR_S  8
+/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Write 1 to clear I2C_TRANS_START_INT.
+ */
+#define I2C_TRANS_START_INT_CLR    (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S)
+#define I2C_TRANS_START_INT_CLR_V  0x00000001U
+#define I2C_TRANS_START_INT_CLR_S  9
+/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Write 1 to clear I2C_NACK_INT.
+ */
+#define I2C_NACK_INT_CLR    (BIT(10))
+#define I2C_NACK_INT_CLR_M  (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S)
+#define I2C_NACK_INT_CLR_V  0x00000001U
+#define I2C_NACK_INT_CLR_S  10
+/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Write 1 to clear I2C_TXFIFO_OVF_INT.
+ */
+#define I2C_TXFIFO_OVF_INT_CLR    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_CLR_M  (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S)
+#define I2C_TXFIFO_OVF_INT_CLR_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_CLR_S  11
+/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0;
+ *  Write 1 to clear I2C_RXFIFO_UDF_INT.
+ */
+#define I2C_RXFIFO_UDF_INT_CLR    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_CLR_M  (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S)
+#define I2C_RXFIFO_UDF_INT_CLR_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_CLR_S  12
+/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0;
+ *  Write 1 to clear I2C_SCL_ST_TO_INT.
+ */
+#define I2C_SCL_ST_TO_INT_CLR    (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S)
+#define I2C_SCL_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0;
+ *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S)
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0;
+ *  Write 1 to clear I2C_DET_START_INT.
+ */
+#define I2C_DET_START_INT_CLR    (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S)
+#define I2C_DET_START_INT_CLR_V  0x00000001U
+#define I2C_DET_START_INT_CLR_S  15
+/** I2C_SLAVE_STRETCH_INT_CLR : WT; bitpos: [16]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_STRETCH_INT.
+ */
+#define I2C_SLAVE_STRETCH_INT_CLR    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_CLR_M  (I2C_SLAVE_STRETCH_INT_CLR_V << I2C_SLAVE_STRETCH_INT_CLR_S)
+#define I2C_SLAVE_STRETCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_CLR_S  16
+/** I2C_GENERAL_CALL_INT_CLR : WT; bitpos: [17]; default: 0;
+ *  Write 1 to clear I2C_GENERAL_CALL_INT.
+ */
+#define I2C_GENERAL_CALL_INT_CLR    (BIT(17))
+#define I2C_GENERAL_CALL_INT_CLR_M  (I2C_GENERAL_CALL_INT_CLR_V << I2C_GENERAL_CALL_INT_CLR_S)
+#define I2C_GENERAL_CALL_INT_CLR_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_CLR_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_CLR : WT; bitpos: [18]; default: 0;
+ *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_M  (I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V << I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_CLR_S  18
+
+/** I2C_INT_ENA_REG register
+ *  Interrupt enable register
+ */
+#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28)
+/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_WM_INT.
+ */
+#define I2C_RXFIFO_WM_INT_ENA    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ENA_M  (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S)
+#define I2C_RXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ENA_S  0
+/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_WM_INT.
+ */
+#define I2C_TXFIFO_WM_INT_ENA    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ENA_M  (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S)
+#define I2C_TXFIFO_WM_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ENA_S  1
+/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_OVF_INT.
+ */
+#define I2C_RXFIFO_OVF_INT_ENA    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S)
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  Write 1 to enable I2C_END_DETECT_INT.
+ */
+#define I2C_END_DETECT_INT_ENA    (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S)
+#define I2C_END_DETECT_INT_ENA_V  0x00000001U
+#define I2C_END_DETECT_INT_ENA_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  Write 1 to enable I2C_BYTE_TRANS_DONE_INT.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ENA    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ENA_M  (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S)
+#define I2C_BYTE_TRANS_DONE_INT_ENA_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ENA_S  4
+/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  Write 1 to enable I2C_ARBITRATION_LOST_INT.
+ */
+#define I2C_ARBITRATION_LOST_INT_ENA    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S)
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  Write 1 to enable I2C_MST_TXFIFO_UDF_INT.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ENA    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ENA_M  (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S)
+#define I2C_MST_TXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ENA_S  6
+/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  Write 1 to enable I2C_TRANS_COMPLETE_INT.
+ */
+#define I2C_TRANS_COMPLETE_INT_ENA    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S)
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to enable I2C_TIME_OUT_INT.
+ */
+#define I2C_TIME_OUT_INT_ENA    (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S)
+#define I2C_TIME_OUT_INT_ENA_V  0x00000001U
+#define I2C_TIME_OUT_INT_ENA_S  8
+/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to enable I2C_TRANS_START_INT.
+ */
+#define I2C_TRANS_START_INT_ENA    (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S)
+#define I2C_TRANS_START_INT_ENA_V  0x00000001U
+#define I2C_TRANS_START_INT_ENA_S  9
+/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  Write 1 to enable I2C_NACK_INT.
+ */
+#define I2C_NACK_INT_ENA    (BIT(10))
+#define I2C_NACK_INT_ENA_M  (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S)
+#define I2C_NACK_INT_ENA_V  0x00000001U
+#define I2C_NACK_INT_ENA_S  10
+/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  Write 1 to enable I2C_TXFIFO_OVF_INT.
+ */
+#define I2C_TXFIFO_OVF_INT_ENA    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ENA_M  (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S)
+#define I2C_TXFIFO_OVF_INT_ENA_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ENA_S  11
+/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0;
+ *  Write 1 to enable I2C_RXFIFO_UDF_INT.
+ */
+#define I2C_RXFIFO_UDF_INT_ENA    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ENA_M  (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S)
+#define I2C_RXFIFO_UDF_INT_ENA_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ENA_S  12
+/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0;
+ *  Write 1 to enable I2C_SCL_ST_TO_INT.
+ */
+#define I2C_SCL_ST_TO_INT_ENA    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S)
+#define I2C_SCL_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0;
+ *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0;
+ *  Write 1 to enable I2C_DET_START_INT.
+ */
+#define I2C_DET_START_INT_ENA    (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S)
+#define I2C_DET_START_INT_ENA_V  0x00000001U
+#define I2C_DET_START_INT_ENA_S  15
+/** I2C_SLAVE_STRETCH_INT_ENA : R/W; bitpos: [16]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_STRETCH_INT.
+ */
+#define I2C_SLAVE_STRETCH_INT_ENA    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ENA_M  (I2C_SLAVE_STRETCH_INT_ENA_V << I2C_SLAVE_STRETCH_INT_ENA_S)
+#define I2C_SLAVE_STRETCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ENA_S  16
+/** I2C_GENERAL_CALL_INT_ENA : R/W; bitpos: [17]; default: 0;
+ *  Write 1 to enable I2C_GENERAL_CALL_INT.
+ */
+#define I2C_GENERAL_CALL_INT_ENA    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ENA_M  (I2C_GENERAL_CALL_INT_ENA_V << I2C_GENERAL_CALL_INT_ENA_S)
+#define I2C_GENERAL_CALL_INT_ENA_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ENA_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ENA : R/W; bitpos: [18]; default: 0;
+ *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V << I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ENA_S  18
+
+/** I2C_INT_STATUS_REG register
+ *  Status register of captured I2C communication events
+ */
+#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c)
+/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status of I2C_RXFIFO_WM_INT.
+ */
+#define I2C_RXFIFO_WM_INT_ST    (BIT(0))
+#define I2C_RXFIFO_WM_INT_ST_M  (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S)
+#define I2C_RXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_WM_INT_ST_S  0
+/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status of I2C_TXFIFO_WM_INT.
+ */
+#define I2C_TXFIFO_WM_INT_ST    (BIT(1))
+#define I2C_TXFIFO_WM_INT_ST_M  (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S)
+#define I2C_TXFIFO_WM_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_WM_INT_ST_S  1
+/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status of I2C_RXFIFO_OVF_INT.
+ */
+#define I2C_RXFIFO_OVF_INT_ST    (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S)
+#define I2C_RXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status of I2C_END_DETECT_INT.
+ */
+#define I2C_END_DETECT_INT_ST    (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S)
+#define I2C_END_DETECT_INT_ST_V  0x00000001U
+#define I2C_END_DETECT_INT_ST_S  3
+/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status of I2C_BYTE_TRANS_DONE_INT.
+ */
+#define I2C_BYTE_TRANS_DONE_INT_ST    (BIT(4))
+#define I2C_BYTE_TRANS_DONE_INT_ST_M  (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S)
+#define I2C_BYTE_TRANS_DONE_INT_ST_V  0x00000001U
+#define I2C_BYTE_TRANS_DONE_INT_ST_S  4
+/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The masked interrupt status of I2C_ARBITRATION_LOST_INT.
+ */
+#define I2C_ARBITRATION_LOST_INT_ST    (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S)
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x00000001U
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The masked interrupt status of I2C_MST_TXFIFO_UDF_INT.
+ */
+#define I2C_MST_TXFIFO_UDF_INT_ST    (BIT(6))
+#define I2C_MST_TXFIFO_UDF_INT_ST_M  (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S)
+#define I2C_MST_TXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_MST_TXFIFO_UDF_INT_ST_S  6
+/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The masked interrupt status of I2C_TRANS_COMPLETE_INT.
+ */
+#define I2C_TRANS_COMPLETE_INT_ST    (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S)
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x00000001U
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The masked interrupt status of I2C_TIME_OUT_INT.
+ */
+#define I2C_TIME_OUT_INT_ST    (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S)
+#define I2C_TIME_OUT_INT_ST_V  0x00000001U
+#define I2C_TIME_OUT_INT_ST_S  8
+/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The masked interrupt status of I2C_TRANS_START_INT.
+ */
+#define I2C_TRANS_START_INT_ST    (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S)
+#define I2C_TRANS_START_INT_ST_V  0x00000001U
+#define I2C_TRANS_START_INT_ST_S  9
+/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The masked interrupt status of I2C_NACK_INT.
+ */
+#define I2C_NACK_INT_ST    (BIT(10))
+#define I2C_NACK_INT_ST_M  (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S)
+#define I2C_NACK_INT_ST_V  0x00000001U
+#define I2C_NACK_INT_ST_S  10
+/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The masked interrupt status of I2C_TXFIFO_OVF_INT.
+ */
+#define I2C_TXFIFO_OVF_INT_ST    (BIT(11))
+#define I2C_TXFIFO_OVF_INT_ST_M  (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S)
+#define I2C_TXFIFO_OVF_INT_ST_V  0x00000001U
+#define I2C_TXFIFO_OVF_INT_ST_S  11
+/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0;
+ *  The masked interrupt status of I2C_RXFIFO_UDF_INT.
+ */
+#define I2C_RXFIFO_UDF_INT_ST    (BIT(12))
+#define I2C_RXFIFO_UDF_INT_ST_M  (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S)
+#define I2C_RXFIFO_UDF_INT_ST_V  0x00000001U
+#define I2C_RXFIFO_UDF_INT_ST_S  12
+/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0;
+ *  The masked interrupt status of I2C_SCL_ST_TO_INT.
+ */
+#define I2C_SCL_ST_TO_INT_ST    (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S)
+#define I2C_SCL_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0;
+ *  The masked interrupt status of I2C_SCL_MAIN_ST_TO_INT.
+ */
+#define I2C_SCL_MAIN_ST_TO_INT_ST    (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S)
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x00000001U
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0;
+ *  The masked interrupt status of I2C_DET_START_INT.
+ */
+#define I2C_DET_START_INT_ST    (BIT(15))
+#define I2C_DET_START_INT_ST_M  (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S)
+#define I2C_DET_START_INT_ST_V  0x00000001U
+#define I2C_DET_START_INT_ST_S  15
+/** I2C_SLAVE_STRETCH_INT_ST : RO; bitpos: [16]; default: 0;
+ *  The masked interrupt status of I2C_SLAVE_STRETCH_INT.
+ */
+#define I2C_SLAVE_STRETCH_INT_ST    (BIT(16))
+#define I2C_SLAVE_STRETCH_INT_ST_M  (I2C_SLAVE_STRETCH_INT_ST_V << I2C_SLAVE_STRETCH_INT_ST_S)
+#define I2C_SLAVE_STRETCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_STRETCH_INT_ST_S  16
+/** I2C_GENERAL_CALL_INT_ST : RO; bitpos: [17]; default: 0;
+ *  The masked interrupt status of I2C_GENERAL_CALL_INT.
+ */
+#define I2C_GENERAL_CALL_INT_ST    (BIT(17))
+#define I2C_GENERAL_CALL_INT_ST_M  (I2C_GENERAL_CALL_INT_ST_V << I2C_GENERAL_CALL_INT_ST_S)
+#define I2C_GENERAL_CALL_INT_ST_V  0x00000001U
+#define I2C_GENERAL_CALL_INT_ST_S  17
+/** I2C_SLAVE_ADDR_UNMATCH_INT_ST : RO; bitpos: [18]; default: 0;
+ *  The masked interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT.
+ */
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST    (BIT(18))
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_M  (I2C_SLAVE_ADDR_UNMATCH_INT_ST_V << I2C_SLAVE_ADDR_UNMATCH_INT_ST_S)
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_V  0x00000001U
+#define I2C_SLAVE_ADDR_UNMATCH_INT_ST_S  18
+
+/** I2C_SDA_HOLD_REG register
+ *  Configures the hold time after a negative SCL edge
+ */
+#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30)
+/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time to hold the data after the falling edge of SCL.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SDA_HOLD_TIME    0x000001FFU
+#define I2C_SDA_HOLD_TIME_M  (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S)
+#define I2C_SDA_HOLD_TIME_V  0x000001FFU
+#define I2C_SDA_HOLD_TIME_S  0
+
+/** I2C_SDA_SAMPLE_REG register
+ *  Configures the sample time after a positive SCL edge
+ */
+#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34)
+/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0;
+ *  Configures the time for sampling SDA.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SDA_SAMPLE_TIME    0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_M  (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S)
+#define I2C_SDA_SAMPLE_TIME_V  0x000001FFU
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+/** I2C_SCL_HIGH_PERIOD_REG register
+ *  Configures the high level width of SCL
+ */
+#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38)
+/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0;
+ *  Configures for how long SCL remains high in Master mode.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_HIGH_PERIOD    0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_M  (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S)
+#define I2C_SCL_HIGH_PERIOD_V  0x000001FFU
+#define I2C_SCL_HIGH_PERIOD_S  0
+/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0;
+ *  Configures the SCL_FSM's waiting period for SCL high level in Master mode.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_WAIT_HIGH_PERIOD    0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_M  (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S)
+#define I2C_SCL_WAIT_HIGH_PERIOD_V  0x0000007FU
+#define I2C_SCL_WAIT_HIGH_PERIOD_S  9
+
+/** I2C_SCL_START_HOLD_REG register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40)
+/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+ *  a START condition.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_START_HOLD_TIME    0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_M  (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S)
+#define I2C_SCL_START_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+/** I2C_SCL_RSTART_SETUP_REG register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44)
+/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the positive edge of SCL and the negative edge of SDA
+ *  for a RESTART condition.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_RSTART_SETUP_TIME    0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_M  (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S)
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+/** I2C_SCL_STOP_HOLD_REG register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48)
+/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the delay after the STOP condition.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_STOP_HOLD_TIME    0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_M  (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S)
+#define I2C_SCL_STOP_HOLD_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+/** I2C_SCL_STOP_SETUP_REG register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c)
+/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8;
+ *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_STOP_SETUP_TIME    0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_M  (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S)
+#define I2C_SCL_STOP_SETUP_TIME_V  0x000001FFU
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+/** I2C_FILTER_CFG_REG register
+ *  SCL and SDA filter configuration register
+ */
+#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50)
+/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_FILTER_THRES    0x0000000FU
+#define I2C_SCL_FILTER_THRES_M  (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S)
+#define I2C_SCL_FILTER_THRES_V  0x0000000FU
+#define I2C_SCL_FILTER_THRES_S  0
+/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0;
+ *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+ *  input has smaller width than this register value, the I2C controller will ignore
+ *  that pulse.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SDA_FILTER_THRES    0x0000000FU
+#define I2C_SDA_FILTER_THRES_M  (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S)
+#define I2C_SDA_FILTER_THRES_V  0x0000000FU
+#define I2C_SDA_FILTER_THRES_S  4
+/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1;
+ *  Configures whether to enable the filter function for SCL.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SCL_FILTER_EN    (BIT(8))
+#define I2C_SCL_FILTER_EN_M  (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S)
+#define I2C_SCL_FILTER_EN_V  0x00000001U
+#define I2C_SCL_FILTER_EN_S  8
+/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1;
+ *  Configures whether to enable the filter function for SDA.
+ *  0: No effect
+ *  1: Enable
+ */
+#define I2C_SDA_FILTER_EN    (BIT(9))
+#define I2C_SDA_FILTER_EN_M  (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S)
+#define I2C_SDA_FILTER_EN_V  0x00000001U
+#define I2C_SDA_FILTER_EN_S  9
+
+/** I2C_COMD0_REG register
+ *  I2C command register 0
+ */
+#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58)
+/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 0.
+ *  It consists of three parts:
+ *  op_code is the command
+ *  0: RSTART
+ *  1: WRITE
+ *  2: READ
+ *  3: STOP
+ *  4: END.
+ *  Byte_num represents the number of bytes that need to be sent or received.
+ *  ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd
+ *  structure  for more information.
+ *  "
+ */
+#define I2C_COMMAND0    0x00003FFFU
+#define I2C_COMMAND0_M  (I2C_COMMAND0_V << I2C_COMMAND0_S)
+#define I2C_COMMAND0_V  0x00003FFFU
+#define I2C_COMMAND0_S  0
+/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 0 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND0_DONE    (BIT(31))
+#define I2C_COMMAND0_DONE_M  (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S)
+#define I2C_COMMAND0_DONE_V  0x00000001U
+#define I2C_COMMAND0_DONE_S  31
+
+/** I2C_COMD1_REG register
+ *  I2C command register 1
+ */
+#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c)
+/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 1. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND1    0x00003FFFU
+#define I2C_COMMAND1_M  (I2C_COMMAND1_V << I2C_COMMAND1_S)
+#define I2C_COMMAND1_V  0x00003FFFU
+#define I2C_COMMAND1_S  0
+/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 1 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND1_DONE    (BIT(31))
+#define I2C_COMMAND1_DONE_M  (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S)
+#define I2C_COMMAND1_DONE_V  0x00000001U
+#define I2C_COMMAND1_DONE_S  31
+
+/** I2C_COMD2_REG register
+ *  I2C command register 2
+ */
+#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60)
+/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 2. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND2    0x00003FFFU
+#define I2C_COMMAND2_M  (I2C_COMMAND2_V << I2C_COMMAND2_S)
+#define I2C_COMMAND2_V  0x00003FFFU
+#define I2C_COMMAND2_S  0
+/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 2 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND2_DONE    (BIT(31))
+#define I2C_COMMAND2_DONE_M  (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S)
+#define I2C_COMMAND2_DONE_V  0x00000001U
+#define I2C_COMMAND2_DONE_S  31
+
+/** I2C_COMD3_REG register
+ *  I2C command register 3
+ */
+#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64)
+/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 3. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND3    0x00003FFFU
+#define I2C_COMMAND3_M  (I2C_COMMAND3_V << I2C_COMMAND3_S)
+#define I2C_COMMAND3_V  0x00003FFFU
+#define I2C_COMMAND3_S  0
+/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 3 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND3_DONE    (BIT(31))
+#define I2C_COMMAND3_DONE_M  (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S)
+#define I2C_COMMAND3_DONE_V  0x00000001U
+#define I2C_COMMAND3_DONE_S  31
+
+/** I2C_COMD4_REG register
+ *  I2C command register 4
+ */
+#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68)
+/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 4. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND4    0x00003FFFU
+#define I2C_COMMAND4_M  (I2C_COMMAND4_V << I2C_COMMAND4_S)
+#define I2C_COMMAND4_V  0x00003FFFU
+#define I2C_COMMAND4_S  0
+/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 4 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND4_DONE    (BIT(31))
+#define I2C_COMMAND4_DONE_M  (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S)
+#define I2C_COMMAND4_DONE_V  0x00000001U
+#define I2C_COMMAND4_DONE_S  31
+
+/** I2C_COMD5_REG register
+ *  I2C command register 5
+ */
+#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c)
+/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 5. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND5    0x00003FFFU
+#define I2C_COMMAND5_M  (I2C_COMMAND5_V << I2C_COMMAND5_S)
+#define I2C_COMMAND5_V  0x00003FFFU
+#define I2C_COMMAND5_S  0
+/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 5 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND5_DONE    (BIT(31))
+#define I2C_COMMAND5_DONE_M  (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S)
+#define I2C_COMMAND5_DONE_V  0x00000001U
+#define I2C_COMMAND5_DONE_S  31
+
+/** I2C_COMD6_REG register
+ *  I2C command register 6
+ */
+#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70)
+/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 6. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND6    0x00003FFFU
+#define I2C_COMMAND6_M  (I2C_COMMAND6_V << I2C_COMMAND6_S)
+#define I2C_COMMAND6_V  0x00003FFFU
+#define I2C_COMMAND6_S  0
+/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 6 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND6_DONE    (BIT(31))
+#define I2C_COMMAND6_DONE_M  (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S)
+#define I2C_COMMAND6_DONE_V  0x00000001U
+#define I2C_COMMAND6_DONE_S  31
+
+/** I2C_COMD7_REG register
+ *  I2C command register 7
+ */
+#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74)
+/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0;
+ *  Configures command 7. See details in I2C_COMD0_REG [13:0].
+ */
+#define I2C_COMMAND7    0x00003FFFU
+#define I2C_COMMAND7_M  (I2C_COMMAND7_V << I2C_COMMAND7_S)
+#define I2C_COMMAND7_V  0x00003FFFU
+#define I2C_COMMAND7_S  0
+/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0;
+ *  Represents whether command 7 is done in I2C Master mode.
+ *  0: Not done
+ *  1: Done
+ */
+#define I2C_COMMAND7_DONE    (BIT(31))
+#define I2C_COMMAND7_DONE_M  (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S)
+#define I2C_COMMAND7_DONE_V  0x00000001U
+#define I2C_COMMAND7_DONE_S  31
+
+/** I2C_SCL_ST_TIME_OUT_REG register
+ *  SCL status timeout register
+ */
+#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78)
+/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+ *  more than 23, more than 1.
+ *  \[
+ *  \text{Threshold} = 2^{\text{I2C_SCL_ST_TO_I2C} - 1}
+ *  \]
+ *
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_ST_TO_I2C_M  (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S)
+#define I2C_SCL_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_ST_TO_I2C_S  0
+
+/** I2C_SCL_MAIN_ST_TIME_OUT_REG register
+ *  SCL main status timeout register
+ */
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c)
+/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16;
+ *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+ *  no more than 23.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_MAIN_ST_TO_I2C    0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_M  (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S)
+#define I2C_SCL_MAIN_ST_TO_I2C_V  0x0000001FU
+#define I2C_SCL_MAIN_ST_TO_I2C_S  0
+
+/** I2C_SCL_SP_CONF_REG register
+ *  Power configuration register
+ */
+#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80)
+/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0;
+ *  Configures whether or not to send out SCL pulses when I2C master is IDLE. The
+ *  number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0].
+ */
+#define I2C_SCL_RST_SLV_EN    (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S)
+#define I2C_SCL_RST_SLV_EN_V  0x00000001U
+#define I2C_SCL_RST_SLV_EN_S  0
+/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0;
+ *  Configure the pulses of SCL generated in I2C Master mode.
+ *  Valid when I2C_SCL_RST_SLV_EN is 1.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_SCL_RST_SLV_NUM    0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_M  (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S)
+#define I2C_SCL_RST_SLV_NUM_V  0x0000001FU
+#define I2C_SCL_RST_SLV_NUM_S  1
+/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0;
+ *  Configures whether or not to power down the I2C output SCL line.
+ *  0: Not power down
+ *  1: Power down
+ *  Valid only when I2C_SCL_FORCE_OUT is 1.
+ */
+#define I2C_SCL_PD_EN    (BIT(6))
+#define I2C_SCL_PD_EN_M  (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S)
+#define I2C_SCL_PD_EN_V  0x00000001U
+#define I2C_SCL_PD_EN_S  6
+/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0;
+ *  Configures whether or not to power down the I2C output SDA line.
+ *  0: Not power down
+ *  1: Power down
+ *  Valid only when I2C_SDA_FORCE_OUT is 1.
+ */
+#define I2C_SDA_PD_EN    (BIT(7))
+#define I2C_SDA_PD_EN_M  (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S)
+#define I2C_SDA_PD_EN_V  0x00000001U
+#define I2C_SDA_PD_EN_S  7
+
+/** I2C_SCL_STRETCH_CONF_REG register
+ *  SCL stretch setting register of I2C slave
+ */
+#define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84)
+/** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0;
+ *  Configures the time period to release the SCL line from stretching to avoid timing
+ *  violation. Usually it should be larger than the SDA setup time.
+ *  Measurement unit: I2C_SCLK
+ */
+#define I2C_STRETCH_PROTECT_NUM    0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_M  (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S)
+#define I2C_STRETCH_PROTECT_NUM_V  0x000003FFU
+#define I2C_STRETCH_PROTECT_NUM_S  0
+/** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0;
+ *  Configures whether to enable slave SCL stretch function. The SCL output line will
+ *  be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+ *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_SCL_STRETCH_EN    (BIT(10))
+#define I2C_SLAVE_SCL_STRETCH_EN_M  (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S)
+#define I2C_SLAVE_SCL_STRETCH_EN_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_EN_S  10
+/** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0;
+ *  Configures whether or not to clear the I2C slave SCL stretch function.
+ *  0: No effect
+ *  1: Clear
+ */
+#define I2C_SLAVE_SCL_STRETCH_CLR    (BIT(11))
+#define I2C_SLAVE_SCL_STRETCH_CLR_M  (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S)
+#define I2C_SLAVE_SCL_STRETCH_CLR_V  0x00000001U
+#define I2C_SLAVE_SCL_STRETCH_CLR_S  11
+/** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0;
+ *  Configures whether to enable the function for slave to control ACK level.
+ *  0: Disable
+ *  1: Enable
+ */
+#define I2C_SLAVE_BYTE_ACK_CTL_EN    (BIT(12))
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_M  (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S)
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_CTL_EN_S  12
+/** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0;
+ *  Configures the ACK level when slave controlling ACK level function enables.
+ *  0: Low level
+ *  1: High level
+ */
+#define I2C_SLAVE_BYTE_ACK_LVL    (BIT(13))
+#define I2C_SLAVE_BYTE_ACK_LVL_M  (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S)
+#define I2C_SLAVE_BYTE_ACK_LVL_V  0x00000001U
+#define I2C_SLAVE_BYTE_ACK_LVL_S  13
+
+/** I2C_DATE_REG register
+ *  Version control register
+ */
+#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8)
+/** I2C_DATE : R/W; bitpos: [31:0]; default: 38817888;
+ *  Version control register.
+ */
+#define I2C_DATE    0xFFFFFFFFU
+#define I2C_DATE_M  (I2C_DATE_V << I2C_DATE_S)
+#define I2C_DATE_V  0xFFFFFFFFU
+#define I2C_DATE_S  0
+
+/** I2C_TXFIFO_START_ADDR_REG register
+ *  I2C TXFIFO base address register
+ */
+#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100)
+/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C TX FIFO first address.
+ */
+#define I2C_TXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_M  (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S)
+#define I2C_TXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_TXFIFO_START_ADDR_S  0
+
+/** I2C_RXFIFO_START_ADDR_REG register
+ *  I2C RXFIFO base address register
+ */
+#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180)
+/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0;
+ *  Represents the I2C RX FIFO first address.
+ */
+#define I2C_RXFIFO_START_ADDR    0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_M  (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S)
+#define I2C_RXFIFO_START_ADDR_V  0xFFFFFFFFU
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/i2c_struct.h b/components/soc/esp32s31/register/soc/i2c_struct.h
new file mode 100644
index 00000000000..9f7de8eb0ce
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/i2c_struct.h
@@ -0,0 +1,1233 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Timing registers */
+/** Type of scl_low_period register
+ *  Configures the low level width of the SCL Clock
+ */
+typedef union {
+    struct {
+        /** scl_low_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the low level width of the SCL Clock in Master mode.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_low_period:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_low_period_reg_t;
+
+/** Type of sda_hold register
+ *  Configures the hold time after a negative SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time to hold the data after the falling edge of SCL.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t sda_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_hold_reg_t;
+
+/** Type of sda_sample register
+ *  Configures the sample time after a positive SCL edge
+ */
+typedef union {
+    struct {
+        /** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
+         *  Configures the time for sampling SDA.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t sda_sample_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_sda_sample_reg_t;
+
+/** Type of scl_high_period register
+ *  Configures the high level width of SCL
+ */
+typedef union {
+    struct {
+        /** scl_high_period : R/W; bitpos: [8:0]; default: 0;
+         *  Configures for how long SCL remains high in Master mode.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_high_period:9;
+        /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
+         *  Configures the SCL_FSM's waiting period for SCL high level in Master mode.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_wait_high_period:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2c_scl_high_period_reg_t;
+
+/** Type of scl_start_hold register
+ *  Configures the delay between the SDA and SCL negative edge for a start condition
+ */
+typedef union {
+    struct {
+        /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the falling edge of SDA and the falling edge of SCL for
+         *  a START condition.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_start_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_start_hold_reg_t;
+
+/** Type of scl_rstart_setup register
+ *  Configures the delay between the positive edge of SCL and the negative edge of SDA
+ */
+typedef union {
+    struct {
+        /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the positive edge of SCL and the negative edge of SDA
+         *  for a RESTART condition.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_rstart_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_rstart_setup_reg_t;
+
+/** Type of scl_stop_hold register
+ *  Configures the delay after the SCL clock edge for a stop condition
+ */
+typedef union {
+    struct {
+        /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the delay after the STOP condition.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_stop_hold_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_hold_reg_t;
+
+/** Type of scl_stop_setup register
+ *  Configures the delay between the SDA and SCL rising edge for a stop condition.
+ *  Measurement unit: I2C_SCLK
+ */
+typedef union {
+    struct {
+        /** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
+         *  Configures the time between the rising edge of SCL and the rising edge of SDA.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_stop_setup_time:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} i2c_scl_stop_setup_reg_t;
+
+/** Type of scl_st_time_out register
+ *  SCL status timeout register
+ */
+typedef union {
+    struct {
+        /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_FSM state unchanged period. It should be no
+         *  more than 23, more than 1.
+         *  \[
+         *  \text{Threshold} = 2^{\text{I2C_SCL_ST_TO_I2C} - 1}
+         *  \]
+         *
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_st_time_out_reg_t;
+
+/** Type of scl_main_st_time_out register
+ *  SCL main status timeout register
+ */
+typedef union {
+    struct {
+        /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be
+         *  no more than 23.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_main_st_to_i2c:5;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2c_scl_main_st_time_out_reg_t;
+
+
+/** Group: Configuration registers */
+/** Type of ctr register
+ *  Transmission setting register
+ */
+typedef union {
+    struct {
+        /** sda_force_out : R/W; bitpos: [0]; default: 0;
+         *  Configures the SDA output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t sda_force_out:1;
+        /** scl_force_out : R/W; bitpos: [1]; default: 0;
+         *  Configures the SCL output mode.
+         *  0: Open drain output
+         *  1: Direct output
+         */
+        uint32_t scl_force_out:1;
+        /** sample_scl_level : R/W; bitpos: [2]; default: 0;
+         *  Configures the sample mode for SDA.
+         *  0: Sample SDA data on the SCL high level
+         *  1: Sample SDA data on the SCL low level
+         */
+        uint32_t sample_scl_level:1;
+        /** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
+         *  Configures the ACK value that needs to be sent by master when rx_fifo_cnt has
+         *  reached the threshold.
+         */
+        uint32_t rx_full_ack_level:1;
+        /** ms_mode : R/W; bitpos: [4]; default: 0;
+         *  Configures the module as an I2C Master or Slave.
+         *  0: Slave
+         *  1: Master
+         */
+        uint32_t ms_mode:1;
+        /** trans_start : WT; bitpos: [5]; default: 0;
+         *  Configures whether the slave starts sending the data in TX FIFO.
+         *  0: No effect
+         *  1: Start
+         */
+        uint32_t trans_start:1;
+        /** tx_lsb_first : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to control the sending order for data needing to be sent.
+         *  0: Send data from the most significant bit
+         *  1: Send data from the least significant bit
+         */
+        uint32_t tx_lsb_first:1;
+        /** rx_lsb_first : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to control the storage order for received data.
+         *  0: Receive data from the most significant bit
+         *  1: Receive data from the least significant bit
+         */
+        uint32_t rx_lsb_first:1;
+        /** clk_en : R/W; bitpos: [8]; default: 0;
+         *  Configures whether to gate clock signal for registers.
+         *  0: Support clock only when registers are read or written to by software
+         *  1: Force clock on for registers
+         */
+        uint32_t clk_en:1;
+        /** arbitration_en : R/W; bitpos: [9]; default: 1;
+         *  Configures whether to enable I2C bus arbitration detection.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t arbitration_en:1;
+        /** fsm_rst : WT; bitpos: [10]; default: 0;
+         *  Configures whether to reset the SCL_FSM.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t fsm_rst:1;
+        /** conf_upgate : WT; bitpos: [11]; default: 0;
+         *  Configures the bit for synchronization.
+         *  0: No effect
+         *  1: Synchronize
+         */
+        uint32_t conf_upgate:1;
+        /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable slave to send data automatically
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slv_tx_auto_start_en:1;
+        /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
+         *  Configures whether to check if the $R/\overline W$ bit of 10-bit addressing
+         *  consists with I2C protocol.
+         *  0: Not check
+         *  1: Check
+         */
+        uint32_t addr_10bit_rw_check_en:1;
+        /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
+         *  Configures whether to support the 7-bit general call function.
+         *  0: Not support
+         *  1: Support
+         */
+        uint32_t addr_broadcasting_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_ctr_reg_t;
+
+/** Type of to register
+ *  Timeout control register for receiving data
+ */
+typedef union {
+    struct {
+        /** time_out_value : R/W; bitpos: [4:0]; default: 16;
+         *  Configures the timeout threshold period for SCL stucking at high or low level. The
+         *  actual period is 2\^{}(reg_time_out_value).
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t time_out_value:5;
+        /** time_out_en : R/W; bitpos: [5]; default: 0;
+         *  Configures whether to enable timeout control.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t time_out_en:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} i2c_to_reg_t;
+
+/** Type of slave_addr register
+ *  Local slave address setting register
+ */
+typedef union {
+    struct {
+        /** slave_addr : R/W; bitpos: [14:0]; default: 0;
+         *  Configures the slave address of the I2C slave.
+         */
+        uint32_t slave_addr:15;
+        uint32_t reserved_15:16;
+        /** addr_10bit_en : R/W; bitpos: [31]; default: 0;
+         *  Configures whether to enable the slave 10-bit addressing mode in Master mode.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t addr_10bit_en:1;
+    };
+    uint32_t val;
+} i2c_slave_addr_reg_t;
+
+/** Type of fifo_conf register
+ *  FIFO configuration register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
+         *  Configures the watermark threshold of RX FIFO in non-FIFO access mode. When
+         *  I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0],
+         *  the I2C_RXFIFO_WM_INT_RAW bit will be valid.
+         */
+        uint32_t rxfifo_wm_thrhd:5;
+        /** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
+         *  Configures the watermark threshold of TX FIFO in non-FIFO access mode.  When
+         *  I2C_FIFO_PRT_EN is 1 and TC FIFO counter is bigger than I2C_TXFIFO_WM_THRHD[4:0],
+         *  the I2C_TXFIFO_WM_INT_RAW bit will be valid.
+         */
+        uint32_t txfifo_wm_thrhd:5;
+        /** nonfifo_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether to enable APB non-FIFO access.
+         */
+        uint32_t nonfifo_en:1;
+        /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
+         *  Configures the slave to enable dual address mode. When this mode is enabled, the
+         *  byte received after the I2C address byte represents the offset address in the I2C
+         *  Slave RAM.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t fifo_addr_cfg_en:1;
+        /** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
+         *  Configures whether or not to reset RX FIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t rx_fifo_rst:1;
+        /** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
+         *  Configures whether or not to reset TX FIFO.
+         *  0: No effect
+         *  1: Reset
+         */
+        uint32_t tx_fifo_rst:1;
+        /** fifo_prt_en : R/W; bitpos: [14]; default: 1;
+         *  Configures whether to enable FIFO pointer in non-FIFO access mode. This bit
+         *  controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty
+         *  interrupts.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t fifo_prt_en:1;
+        uint32_t reserved_15:17;
+    };
+    uint32_t val;
+} i2c_fifo_conf_reg_t;
+
+/** Type of filter_cfg register
+ *  SCL and SDA filter configuration register
+ */
+typedef union {
+    struct {
+        /** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_filter_thres:4;
+        /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
+         *  Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA
+         *  input has smaller width than this register value, the I2C controller will ignore
+         *  that pulse.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t sda_filter_thres:4;
+        /** scl_filter_en : R/W; bitpos: [8]; default: 1;
+         *  Configures whether to enable the filter function for SCL.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t scl_filter_en:1;
+        /** sda_filter_en : R/W; bitpos: [9]; default: 1;
+         *  Configures whether to enable the filter function for SDA.
+         *  0: No effect
+         *  1: Enable
+         */
+        uint32_t sda_filter_en:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} i2c_filter_cfg_reg_t;
+
+/** Type of scl_sp_conf register
+ *  Power configuration register
+ */
+typedef union {
+    struct {
+        /** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
+         *  Configures whether or not to send out SCL pulses when I2C master is IDLE. The
+         *  number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0].
+         */
+        uint32_t scl_rst_slv_en:1;
+        /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
+         *  Configure the pulses of SCL generated in I2C Master mode.
+         *  Valid when I2C_SCL_RST_SLV_EN is 1.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t scl_rst_slv_num:5;
+        /** scl_pd_en : R/W; bitpos: [6]; default: 0;
+         *  Configures whether or not to power down the I2C output SCL line.
+         *  0: Not power down
+         *  1: Power down
+         *  Valid only when I2C_SCL_FORCE_OUT is 1.
+         */
+        uint32_t scl_pd_en:1;
+        /** sda_pd_en : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to power down the I2C output SDA line.
+         *  0: Not power down
+         *  1: Power down
+         *  Valid only when I2C_SDA_FORCE_OUT is 1.
+         */
+        uint32_t sda_pd_en:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_scl_sp_conf_reg_t;
+
+/** Type of scl_stretch_conf register
+ *  SCL stretch setting register of I2C slave
+ */
+typedef union {
+    struct {
+        /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
+         *  Configures the time period to release the SCL line from stretching to avoid timing
+         *  violation. Usually it should be larger than the SDA setup time.
+         *  Measurement unit: I2C_SCLK
+         */
+        uint32_t stretch_protect_num:10;
+        /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
+         *  Configures whether to enable slave SCL stretch function. The SCL output line will
+         *  be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The
+         *  stretch cause can be seen in I2C_STRETCH_CAUSE.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_scl_stretch_en:1;
+        /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
+         *  Configures whether or not to clear the I2C slave SCL stretch function.
+         *  0: No effect
+         *  1: Clear
+         */
+        uint32_t slave_scl_stretch_clr:1;
+        /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
+         *  Configures whether to enable the function for slave to control ACK level.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t slave_byte_ack_ctl_en:1;
+        /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
+         *  Configures the ACK level when slave controlling ACK level function enables.
+         *  0: Low level
+         *  1: High level
+         */
+        uint32_t slave_byte_ack_lvl:1;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} i2c_scl_stretch_conf_reg_t;
+
+
+/** Group: Status registers */
+/** Type of sr register
+ *  I2C working status register
+ */
+typedef union {
+    struct {
+        /** resp_rec : RO; bitpos: [0]; default: 0;
+         *  Represents the received ACK value in Master mode or Slave mode.
+         *  0: ACK
+         *  1: NACK
+         */
+        uint32_t resp_rec:1;
+        /** slave_rw : RO; bitpos: [1]; default: 0;
+         *  Represents the transfer direction in Slave mode.
+         *  0: Master writes to slave
+         *  1: Master reads from slave
+         */
+        uint32_t slave_rw:1;
+        uint32_t reserved_2:1;
+        /** arb_lost : RO; bitpos: [3]; default: 0;
+         *  Represents whether the I2C controller loses control of SCL line.
+         *  0: No arbitration lost
+         *  1: Arbitration lost
+         */
+        uint32_t arb_lost:1;
+        /** bus_busy : RO; bitpos: [4]; default: 0;
+         *  Represents the I2C bus state.
+         *  0: The I2C bus is in idle state
+         *  1: The I2C bus is busy transferring data
+         */
+        uint32_t bus_busy:1;
+        /** slave_addressed : RO; bitpos: [5]; default: 0;
+         *  Represents whether the address sent by the master is equal to the address of the
+         *  slave.
+         *  Valid only when the module is configured as an I2C Slave.
+         *  0: Not equal
+         *  1: Equal
+         */
+        uint32_t slave_addressed:1;
+        uint32_t reserved_6:2;
+        /** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
+         *  Represents the number of data bytes received in RAM.
+         */
+        uint32_t rxfifo_cnt:6;
+        /** stretch_cause : RO; bitpos: [15:14]; default: 3;
+         *  Represents the cause of SCL clocking stretching in Slave mode.
+         *  0: Stretching SCL low when the master starts to read data.
+         *  1: Stretching SCL low when I2C TX FIFO is empty in Slave mode.
+         *  2: Stretching SCL low when I2C RX FIFO is full in Slave mode.
+         */
+        uint32_t stretch_cause:2;
+        uint32_t reserved_16:2;
+        /** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
+         *  Represents the number of data bytes to be sent.
+         */
+        uint32_t txfifo_cnt:6;
+        /** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
+         *  Represents the states of the I2C module state machine.
+         *  0: Idle
+         *  1: Address shift
+         *  2: ACK address
+         *  3: Rx data
+         *  4: Tx data
+         *  5: Send ACK
+         *  6: Wait ACK
+         */
+        uint32_t scl_main_state_last:3;
+        uint32_t reserved_27:1;
+        /** scl_state_last : RO; bitpos: [30:28]; default: 0;
+         *  Represents the states of the state machine used to produce SCL.
+         *  0: Idle
+         *  1: Start
+         *  2: Negative edge
+         *  3: Low
+         *  4: Positive edge
+         *  5: High
+         *  6: Stop
+         */
+        uint32_t scl_state_last:3;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2c_sr_reg_t;
+
+/** Type of fifo_st register
+ *  FIFO status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
+         *  Represents the offset address of the APB reading from RX FIFO.
+         */
+        uint32_t rxfifo_raddr:5;
+        /** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
+         *  Represents the offset address of i2c module receiving data and writing to RX FIFO.
+         */
+        uint32_t rxfifo_waddr:5;
+        /** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
+         *  Represents the offset address of I2C module reading from TX FIFO.
+         */
+        uint32_t txfifo_raddr:5;
+        /** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
+         *  Represents the offset address of APB bus writing to TX FIFO.
+         */
+        uint32_t txfifo_waddr:5;
+        uint32_t reserved_20:2;
+        /** slave_rw_point : RO; bitpos: [29:22]; default: 0;
+         *  Represents the offset address in the I2C Slave RAM addressed by I2C Master when in
+         *  I2C Slave mode.
+         */
+        uint32_t slave_rw_point:8;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2c_fifo_st_reg_t;
+
+/** Type of data register
+ *  Rx FIFO read data
+ */
+typedef union {
+    struct {
+        /** fifo_rdata : HRO; bitpos: [7:0]; default: 0;
+         *  Represents the value of RXFIFO read data.
+         */
+        uint32_t fifo_rdata:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} i2c_data_reg_t;
+
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Raw interrupt status register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_WM_INT.
+         */
+        uint32_t rxfifo_wm_int_raw:1;
+        /** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
+         *  The raw interrupt status of I2C_TXFIFO_WM_INT.
+         */
+        uint32_t txfifo_wm_int_raw:1;
+        /** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_raw:1;
+        /** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
+         *  The raw interrupt status of I2C_END_DETECT_INT.
+         */
+        uint32_t end_detect_int_raw:1;
+        /** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
+         *  The raw interrupt status of I2C_BYTE_TRANS_DONE_INT.
+         */
+        uint32_t byte_trans_done_int_raw:1;
+        /** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
+         *  The raw interrupt status of I2C_ARBITRATION_LOST_INT.
+         */
+        uint32_t arbitration_lost_int_raw:1;
+        /** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
+         *  The raw interrupt status of I2C_MST_TXFIFO_UDF_INT.
+         */
+        uint32_t mst_txfifo_udf_int_raw:1;
+        /** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
+         *  The raw interrupt status of the I2C_TRANS_COMPLETE_INT.
+         */
+        uint32_t trans_complete_int_raw:1;
+        /** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
+         *  The raw interrupt status of I2C_TIME_OUT_INT.
+         */
+        uint32_t time_out_int_raw:1;
+        /** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
+         *  The raw interrupt status of I2C_TRANS_START_INT.
+         */
+        uint32_t trans_start_int_raw:1;
+        /** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
+         *  The raw interrupt status of I2C_NACK_INT.
+         */
+        uint32_t nack_int_raw:1;
+        /** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
+         *  The raw interrupt status of I2C_TXFIFO_OVF_INT.
+         */
+        uint32_t txfifo_ovf_int_raw:1;
+        /** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
+         *  The raw interrupt status of I2C_RXFIFO_UDF_INT.
+         */
+        uint32_t rxfifo_udf_int_raw:1;
+        /** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
+         *  The raw interrupt status of I2C_SCL_ST_TO_INT.
+         */
+        uint32_t scl_st_to_int_raw:1;
+        /** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
+         *  The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT.
+         */
+        uint32_t scl_main_st_to_int_raw:1;
+        /** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
+         *  The raw interrupt status of I2C_DET_START_INT.
+         */
+        uint32_t det_start_int_raw:1;
+        /** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_STRETCH_INT.
+         */
+        uint32_t slave_stretch_int_raw:1;
+        /** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
+         *  The raw interrupt status of I2C_GENERAL_CALL_INT.
+         */
+        uint32_t general_call_int_raw:1;
+        /** slave_addr_unmatch_int_raw : R/SS/WTC; bitpos: [18]; default: 0;
+         *  The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT.
+         */
+        uint32_t slave_addr_unmatch_int_raw:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_raw_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_WM_INT.
+         */
+        uint32_t rxfifo_wm_int_clr:1;
+        /** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_WM_INT.
+         */
+        uint32_t txfifo_wm_int_clr:1;
+        /** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_clr:1;
+        /** end_detect_int_clr : WT; bitpos: [3]; default: 0;
+         *  Write 1 to clear I2C_END_DETECT_INT.
+         */
+        uint32_t end_detect_int_clr:1;
+        /** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
+         *  Write 1 to clear I2C_BYTE_TRANS_DONE_INT.
+         */
+        uint32_t byte_trans_done_int_clr:1;
+        /** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
+         *  Write 1 to clear I2C_ARBITRATION_LOST_INT.
+         */
+        uint32_t arbitration_lost_int_clr:1;
+        /** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
+         *  Write 1 to clear I2C_MST_TXFIFO_UDF_INT.
+         */
+        uint32_t mst_txfifo_udf_int_clr:1;
+        /** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
+         *  Write 1 to clear I2C_TRANS_COMPLETE_INT.
+         */
+        uint32_t trans_complete_int_clr:1;
+        /** time_out_int_clr : WT; bitpos: [8]; default: 0;
+         *  Write 1 to clear I2C_TIME_OUT_INT.
+         */
+        uint32_t time_out_int_clr:1;
+        /** trans_start_int_clr : WT; bitpos: [9]; default: 0;
+         *  Write 1 to clear I2C_TRANS_START_INT.
+         */
+        uint32_t trans_start_int_clr:1;
+        /** nack_int_clr : WT; bitpos: [10]; default: 0;
+         *  Write 1 to clear I2C_NACK_INT.
+         */
+        uint32_t nack_int_clr:1;
+        /** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
+         *  Write 1 to clear I2C_TXFIFO_OVF_INT.
+         */
+        uint32_t txfifo_ovf_int_clr:1;
+        /** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
+         *  Write 1 to clear I2C_RXFIFO_UDF_INT.
+         */
+        uint32_t rxfifo_udf_int_clr:1;
+        /** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
+         *  Write 1 to clear I2C_SCL_ST_TO_INT.
+         */
+        uint32_t scl_st_to_int_clr:1;
+        /** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
+         *  Write 1 to clear I2C_SCL_MAIN_ST_TO_INT.
+         */
+        uint32_t scl_main_st_to_int_clr:1;
+        /** det_start_int_clr : WT; bitpos: [15]; default: 0;
+         *  Write 1 to clear I2C_DET_START_INT.
+         */
+        uint32_t det_start_int_clr:1;
+        /** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_STRETCH_INT.
+         */
+        uint32_t slave_stretch_int_clr:1;
+        /** general_call_int_clr : WT; bitpos: [17]; default: 0;
+         *  Write 1 to clear I2C_GENERAL_CALL_INT.
+         */
+        uint32_t general_call_int_clr:1;
+        /** slave_addr_unmatch_int_clr : WT; bitpos: [18]; default: 0;
+         *  Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT.
+         */
+        uint32_t slave_addr_unmatch_int_clr:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_clr_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable register
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_WM_INT.
+         */
+        uint32_t rxfifo_wm_int_ena:1;
+        /** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_WM_INT.
+         */
+        uint32_t txfifo_wm_int_ena:1;
+        /** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_ena:1;
+        /** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
+         *  Write 1 to enable I2C_END_DETECT_INT.
+         */
+        uint32_t end_detect_int_ena:1;
+        /** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
+         *  Write 1 to enable I2C_BYTE_TRANS_DONE_INT.
+         */
+        uint32_t byte_trans_done_int_ena:1;
+        /** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
+         *  Write 1 to enable I2C_ARBITRATION_LOST_INT.
+         */
+        uint32_t arbitration_lost_int_ena:1;
+        /** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
+         *  Write 1 to enable I2C_MST_TXFIFO_UDF_INT.
+         */
+        uint32_t mst_txfifo_udf_int_ena:1;
+        /** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
+         *  Write 1 to enable I2C_TRANS_COMPLETE_INT.
+         */
+        uint32_t trans_complete_int_ena:1;
+        /** time_out_int_ena : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to enable I2C_TIME_OUT_INT.
+         */
+        uint32_t time_out_int_ena:1;
+        /** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to enable I2C_TRANS_START_INT.
+         */
+        uint32_t trans_start_int_ena:1;
+        /** nack_int_ena : R/W; bitpos: [10]; default: 0;
+         *  Write 1 to enable I2C_NACK_INT.
+         */
+        uint32_t nack_int_ena:1;
+        /** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
+         *  Write 1 to enable I2C_TXFIFO_OVF_INT.
+         */
+        uint32_t txfifo_ovf_int_ena:1;
+        /** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
+         *  Write 1 to enable I2C_RXFIFO_UDF_INT.
+         */
+        uint32_t rxfifo_udf_int_ena:1;
+        /** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
+         *  Write 1 to enable I2C_SCL_ST_TO_INT.
+         */
+        uint32_t scl_st_to_int_ena:1;
+        /** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
+         *  Write 1 to enable I2C_SCL_MAIN_ST_TO_INT.
+         */
+        uint32_t scl_main_st_to_int_ena:1;
+        /** det_start_int_ena : R/W; bitpos: [15]; default: 0;
+         *  Write 1 to enable I2C_DET_START_INT.
+         */
+        uint32_t det_start_int_ena:1;
+        /** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_STRETCH_INT.
+         */
+        uint32_t slave_stretch_int_ena:1;
+        /** general_call_int_ena : R/W; bitpos: [17]; default: 0;
+         *  Write 1 to enable I2C_GENERAL_CALL_INT.
+         */
+        uint32_t general_call_int_ena:1;
+        /** slave_addr_unmatch_int_ena : R/W; bitpos: [18]; default: 0;
+         *  Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT.
+         */
+        uint32_t slave_addr_unmatch_int_ena:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_ena_reg_t;
+
+/** Type of int_status register
+ *  Status register of captured I2C communication events
+ */
+typedef union {
+    struct {
+        /** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status of I2C_RXFIFO_WM_INT.
+         */
+        uint32_t rxfifo_wm_int_st:1;
+        /** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status of I2C_TXFIFO_WM_INT.
+         */
+        uint32_t txfifo_wm_int_st:1;
+        /** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status of I2C_RXFIFO_OVF_INT.
+         */
+        uint32_t rxfifo_ovf_int_st:1;
+        /** end_detect_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status of I2C_END_DETECT_INT.
+         */
+        uint32_t end_detect_int_st:1;
+        /** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status of I2C_BYTE_TRANS_DONE_INT.
+         */
+        uint32_t byte_trans_done_int_st:1;
+        /** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
+         *  The masked interrupt status of I2C_ARBITRATION_LOST_INT.
+         */
+        uint32_t arbitration_lost_int_st:1;
+        /** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
+         *  The masked interrupt status of I2C_MST_TXFIFO_UDF_INT.
+         */
+        uint32_t mst_txfifo_udf_int_st:1;
+        /** trans_complete_int_st : RO; bitpos: [7]; default: 0;
+         *  The masked interrupt status of I2C_TRANS_COMPLETE_INT.
+         */
+        uint32_t trans_complete_int_st:1;
+        /** time_out_int_st : RO; bitpos: [8]; default: 0;
+         *  The masked interrupt status of I2C_TIME_OUT_INT.
+         */
+        uint32_t time_out_int_st:1;
+        /** trans_start_int_st : RO; bitpos: [9]; default: 0;
+         *  The masked interrupt status of I2C_TRANS_START_INT.
+         */
+        uint32_t trans_start_int_st:1;
+        /** nack_int_st : RO; bitpos: [10]; default: 0;
+         *  The masked interrupt status of I2C_NACK_INT.
+         */
+        uint32_t nack_int_st:1;
+        /** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
+         *  The masked interrupt status of I2C_TXFIFO_OVF_INT.
+         */
+        uint32_t txfifo_ovf_int_st:1;
+        /** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
+         *  The masked interrupt status of I2C_RXFIFO_UDF_INT.
+         */
+        uint32_t rxfifo_udf_int_st:1;
+        /** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
+         *  The masked interrupt status of I2C_SCL_ST_TO_INT.
+         */
+        uint32_t scl_st_to_int_st:1;
+        /** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
+         *  The masked interrupt status of I2C_SCL_MAIN_ST_TO_INT.
+         */
+        uint32_t scl_main_st_to_int_st:1;
+        /** det_start_int_st : RO; bitpos: [15]; default: 0;
+         *  The masked interrupt status of I2C_DET_START_INT.
+         */
+        uint32_t det_start_int_st:1;
+        /** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
+         *  The masked interrupt status of I2C_SLAVE_STRETCH_INT.
+         */
+        uint32_t slave_stretch_int_st:1;
+        /** general_call_int_st : RO; bitpos: [17]; default: 0;
+         *  The masked interrupt status of I2C_GENERAL_CALL_INT.
+         */
+        uint32_t general_call_int_st:1;
+        /** slave_addr_unmatch_int_st : RO; bitpos: [18]; default: 0;
+         *  The masked interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT.
+         */
+        uint32_t slave_addr_unmatch_int_st:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} i2c_int_status_reg_t;
+
+
+/** Group: Command registers */
+/** Type of comd0 register
+ *  I2C command register 0
+ */
+typedef union {
+    struct {
+        /** command0 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 0.
+         *  It consists of three parts:
+         *  op_code is the command
+         *  0: RSTART
+         *  1: WRITE
+         *  2: READ
+         *  3: STOP
+         *  4: END.
+         *  Byte_num represents the number of bytes that need to be sent or received.
+         *  ack_check_en, ack_exp, and ack are used to control the ACK bit. See I2C cmd
+         *  structure  for more information.
+         *  "
+         */
+        uint32_t command0:14;
+        uint32_t reserved_14:17;
+        /** command0_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 0 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command0_done:1;
+    };
+    uint32_t val;
+} i2c_comd0_reg_t;
+
+/** Type of comd1 register
+ *  I2C command register 1
+ */
+typedef union {
+    struct {
+        /** command1 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 1. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command1:14;
+        uint32_t reserved_14:17;
+        /** command1_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 1 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command1_done:1;
+    };
+    uint32_t val;
+} i2c_comd1_reg_t;
+
+/** Type of comd2 register
+ *  I2C command register 2
+ */
+typedef union {
+    struct {
+        /** command2 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 2. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command2:14;
+        uint32_t reserved_14:17;
+        /** command2_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 2 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command2_done:1;
+    };
+    uint32_t val;
+} i2c_comd2_reg_t;
+
+/** Type of comd3 register
+ *  I2C command register 3
+ */
+typedef union {
+    struct {
+        /** command3 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 3. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command3:14;
+        uint32_t reserved_14:17;
+        /** command3_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 3 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command3_done:1;
+    };
+    uint32_t val;
+} i2c_comd3_reg_t;
+
+/** Type of comd4 register
+ *  I2C command register 4
+ */
+typedef union {
+    struct {
+        /** command4 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 4. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command4:14;
+        uint32_t reserved_14:17;
+        /** command4_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 4 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command4_done:1;
+    };
+    uint32_t val;
+} i2c_comd4_reg_t;
+
+/** Type of comd5 register
+ *  I2C command register 5
+ */
+typedef union {
+    struct {
+        /** command5 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 5. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command5:14;
+        uint32_t reserved_14:17;
+        /** command5_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 5 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command5_done:1;
+    };
+    uint32_t val;
+} i2c_comd5_reg_t;
+
+/** Type of comd6 register
+ *  I2C command register 6
+ */
+typedef union {
+    struct {
+        /** command6 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 6. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command6:14;
+        uint32_t reserved_14:17;
+        /** command6_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 6 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command6_done:1;
+    };
+    uint32_t val;
+} i2c_comd6_reg_t;
+
+/** Type of comd7 register
+ *  I2C command register 7
+ */
+typedef union {
+    struct {
+        /** command7 : R/W; bitpos: [13:0]; default: 0;
+         *  Configures command 7. See details in I2C_COMD0_REG [13:0].
+         */
+        uint32_t command7:14;
+        uint32_t reserved_14:17;
+        /** command7_done : R/W/SS; bitpos: [31]; default: 0;
+         *  Represents whether command 7 is done in I2C Master mode.
+         *  0: Not done
+         *  1: Done
+         */
+        uint32_t command7_done:1;
+    };
+    uint32_t val;
+} i2c_comd7_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 38817888;
+         *  Version control register.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} i2c_date_reg_t;
+
+
+/** Group: Address register */
+/** Type of txfifo_start_addr register
+ *  I2C TXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C TX FIFO first address.
+         */
+        uint32_t txfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_txfifo_start_addr_reg_t;
+
+/** Type of rxfifo_start_addr register
+ *  I2C RXFIFO base address register
+ */
+typedef union {
+    struct {
+        /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0;
+         *  Represents the I2C RX FIFO first address.
+         */
+        uint32_t rxfifo_start_addr:32;
+    };
+    uint32_t val;
+} i2c_rxfifo_start_addr_reg_t;
+
+
+typedef struct {
+    volatile i2c_scl_low_period_reg_t scl_low_period;
+    volatile i2c_ctr_reg_t ctr;
+    volatile i2c_sr_reg_t sr;
+    volatile i2c_to_reg_t to;
+    volatile i2c_slave_addr_reg_t slave_addr;
+    volatile i2c_fifo_st_reg_t fifo_st;
+    volatile i2c_fifo_conf_reg_t fifo_conf;
+    volatile i2c_data_reg_t data;
+    volatile i2c_int_raw_reg_t int_raw;
+    volatile i2c_int_clr_reg_t int_clr;
+    volatile i2c_int_ena_reg_t int_ena;
+    volatile i2c_int_status_reg_t int_status;
+    volatile i2c_sda_hold_reg_t sda_hold;
+    volatile i2c_sda_sample_reg_t sda_sample;
+    volatile i2c_scl_high_period_reg_t scl_high_period;
+    uint32_t reserved_03c;
+    volatile i2c_scl_start_hold_reg_t scl_start_hold;
+    volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
+    volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
+    volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
+    volatile i2c_filter_cfg_reg_t filter_cfg;
+    uint32_t reserved_054;
+    volatile i2c_comd0_reg_t comd0;
+    volatile i2c_comd1_reg_t comd1;
+    volatile i2c_comd2_reg_t comd2;
+    volatile i2c_comd3_reg_t comd3;
+    volatile i2c_comd4_reg_t comd4;
+    volatile i2c_comd5_reg_t comd5;
+    volatile i2c_comd6_reg_t comd6;
+    volatile i2c_comd7_reg_t comd7;
+    volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
+    volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
+    volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
+    volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
+    uint32_t reserved_088[28];
+    volatile i2c_date_reg_t date;
+    uint32_t reserved_0fc;
+    volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
+    uint32_t reserved_104[31];
+    volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
+} i2c_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/i2s_reg.h b/components/soc/esp32s31/register/soc/i2s_reg.h
new file mode 100644
index 00000000000..dd7163fc1e6
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/i2s_reg.h
@@ -0,0 +1,1594 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** I2S_INT_RAW_REG register
+ *  I2S interrupt raw register, valid in level.
+ */
+#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc)
+/** I2S_RX_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_RAW    (BIT(0))
+#define I2S_RX_DONE_INT_RAW_M  (I2S_RX_DONE_INT_RAW_V << I2S_RX_DONE_INT_RAW_S)
+#define I2S_RX_DONE_INT_RAW_V  0x00000001U
+#define I2S_RX_DONE_INT_RAW_S  0
+/** I2S_TX_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_RAW    (BIT(1))
+#define I2S_TX_DONE_INT_RAW_M  (I2S_TX_DONE_INT_RAW_V << I2S_TX_DONE_INT_RAW_S)
+#define I2S_TX_DONE_INT_RAW_V  0x00000001U
+#define I2S_TX_DONE_INT_RAW_S  1
+/** I2S_RX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_RAW    (BIT(2))
+#define I2S_RX_HUNG_INT_RAW_M  (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S)
+#define I2S_RX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_RX_HUNG_INT_RAW_S  2
+/** I2S_TX_HUNG_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_RAW    (BIT(3))
+#define I2S_TX_HUNG_INT_RAW_M  (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S)
+#define I2S_TX_HUNG_INT_RAW_V  0x00000001U
+#define I2S_TX_HUNG_INT_RAW_S  3
+/** I2S_TX_SYNC_INT_RAW : RO/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit  for the i2s_tx_sync_int interrupt
+ */
+#define I2S_TX_SYNC_INT_RAW    (BIT(4))
+#define I2S_TX_SYNC_INT_RAW_M  (I2S_TX_SYNC_INT_RAW_V << I2S_TX_SYNC_INT_RAW_S)
+#define I2S_TX_SYNC_INT_RAW_V  0x00000001U
+#define I2S_TX_SYNC_INT_RAW_S  4
+
+/** I2S_INT_ST_REG register
+ *  I2S interrupt status register.
+ */
+#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10)
+/** I2S_RX_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ST    (BIT(0))
+#define I2S_RX_DONE_INT_ST_M  (I2S_RX_DONE_INT_ST_V << I2S_RX_DONE_INT_ST_S)
+#define I2S_RX_DONE_INT_ST_V  0x00000001U
+#define I2S_RX_DONE_INT_ST_S  0
+/** I2S_TX_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ST    (BIT(1))
+#define I2S_TX_DONE_INT_ST_M  (I2S_TX_DONE_INT_ST_V << I2S_TX_DONE_INT_ST_S)
+#define I2S_TX_DONE_INT_ST_V  0x00000001U
+#define I2S_TX_DONE_INT_ST_S  1
+/** I2S_RX_HUNG_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ST    (BIT(2))
+#define I2S_RX_HUNG_INT_ST_M  (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S)
+#define I2S_RX_HUNG_INT_ST_V  0x00000001U
+#define I2S_RX_HUNG_INT_ST_S  2
+/** I2S_TX_HUNG_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ST    (BIT(3))
+#define I2S_TX_HUNG_INT_ST_M  (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S)
+#define I2S_TX_HUNG_INT_ST_V  0x00000001U
+#define I2S_TX_HUNG_INT_ST_S  3
+/** I2S_TX_SYNC_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The masked interrupt status bit  for the i2s_tx_sync_int interrupt
+ */
+#define I2S_TX_SYNC_INT_ST    (BIT(4))
+#define I2S_TX_SYNC_INT_ST_M  (I2S_TX_SYNC_INT_ST_V << I2S_TX_SYNC_INT_ST_S)
+#define I2S_TX_SYNC_INT_ST_V  0x00000001U
+#define I2S_TX_SYNC_INT_ST_S  4
+
+/** I2S_INT_ENA_REG register
+ *  I2S interrupt enable register.
+ */
+#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14)
+/** I2S_RX_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_ENA    (BIT(0))
+#define I2S_RX_DONE_INT_ENA_M  (I2S_RX_DONE_INT_ENA_V << I2S_RX_DONE_INT_ENA_S)
+#define I2S_RX_DONE_INT_ENA_V  0x00000001U
+#define I2S_RX_DONE_INT_ENA_S  0
+/** I2S_TX_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_ENA    (BIT(1))
+#define I2S_TX_DONE_INT_ENA_M  (I2S_TX_DONE_INT_ENA_V << I2S_TX_DONE_INT_ENA_S)
+#define I2S_TX_DONE_INT_ENA_V  0x00000001U
+#define I2S_TX_DONE_INT_ENA_S  1
+/** I2S_RX_HUNG_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_ENA    (BIT(2))
+#define I2S_RX_HUNG_INT_ENA_M  (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S)
+#define I2S_RX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_RX_HUNG_INT_ENA_S  2
+/** I2S_TX_HUNG_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_ENA    (BIT(3))
+#define I2S_TX_HUNG_INT_ENA_M  (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S)
+#define I2S_TX_HUNG_INT_ENA_V  0x00000001U
+#define I2S_TX_HUNG_INT_ENA_S  3
+/** I2S_TX_SYNC_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit  for the i2s_tx_sync_int interrupt
+ */
+#define I2S_TX_SYNC_INT_ENA    (BIT(4))
+#define I2S_TX_SYNC_INT_ENA_M  (I2S_TX_SYNC_INT_ENA_V << I2S_TX_SYNC_INT_ENA_S)
+#define I2S_TX_SYNC_INT_ENA_V  0x00000001U
+#define I2S_TX_SYNC_INT_ENA_S  4
+
+/** I2S_INT_CLR_REG register
+ *  I2S interrupt clear register.
+ */
+#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18)
+/** I2S_RX_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the i2s_rx_done_int interrupt
+ */
+#define I2S_RX_DONE_INT_CLR    (BIT(0))
+#define I2S_RX_DONE_INT_CLR_M  (I2S_RX_DONE_INT_CLR_V << I2S_RX_DONE_INT_CLR_S)
+#define I2S_RX_DONE_INT_CLR_V  0x00000001U
+#define I2S_RX_DONE_INT_CLR_S  0
+/** I2S_TX_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the i2s_tx_done_int interrupt
+ */
+#define I2S_TX_DONE_INT_CLR    (BIT(1))
+#define I2S_TX_DONE_INT_CLR_M  (I2S_TX_DONE_INT_CLR_V << I2S_TX_DONE_INT_CLR_S)
+#define I2S_TX_DONE_INT_CLR_V  0x00000001U
+#define I2S_TX_DONE_INT_CLR_S  1
+/** I2S_RX_HUNG_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the i2s_rx_hung_int interrupt
+ */
+#define I2S_RX_HUNG_INT_CLR    (BIT(2))
+#define I2S_RX_HUNG_INT_CLR_M  (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S)
+#define I2S_RX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_RX_HUNG_INT_CLR_S  2
+/** I2S_TX_HUNG_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the i2s_tx_hung_int interrupt
+ */
+#define I2S_TX_HUNG_INT_CLR    (BIT(3))
+#define I2S_TX_HUNG_INT_CLR_M  (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S)
+#define I2S_TX_HUNG_INT_CLR_V  0x00000001U
+#define I2S_TX_HUNG_INT_CLR_S  3
+/** I2S_TX_SYNC_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the i2s_tx_sync_int interrupt
+ */
+#define I2S_TX_SYNC_INT_CLR    (BIT(4))
+#define I2S_TX_SYNC_INT_CLR_M  (I2S_TX_SYNC_INT_CLR_V << I2S_TX_SYNC_INT_CLR_S)
+#define I2S_TX_SYNC_INT_CLR_V  0x00000001U
+#define I2S_TX_SYNC_INT_CLR_S  4
+
+/** I2S_RX_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_CONF_REG (DR_REG_I2S_BASE + 0x20)
+/** I2S_RX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset receiver
+ */
+#define I2S_RX_RESET    (BIT(0))
+#define I2S_RX_RESET_M  (I2S_RX_RESET_V << I2S_RX_RESET_S)
+#define I2S_RX_RESET_V  0x00000001U
+#define I2S_RX_RESET_S  0
+/** I2S_RX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Rx AFIFO
+ */
+#define I2S_RX_FIFO_RESET    (BIT(1))
+#define I2S_RX_FIFO_RESET_M  (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S)
+#define I2S_RX_FIFO_RESET_V  0x00000001U
+#define I2S_RX_FIFO_RESET_S  1
+/** I2S_RX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start receiving data
+ */
+#define I2S_RX_START    (BIT(2))
+#define I2S_RX_START_M  (I2S_RX_START_V << I2S_RX_START_S)
+#define I2S_RX_START_V  0x00000001U
+#define I2S_RX_START_S  2
+/** I2S_RX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave receiver mode
+ */
+#define I2S_RX_SLAVE_MOD    (BIT(3))
+#define I2S_RX_SLAVE_MOD_M  (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S)
+#define I2S_RX_SLAVE_MOD_V  0x00000001U
+#define I2S_RX_SLAVE_MOD_S  3
+/** I2S_RX_STOP_MODE : R/W; bitpos: [5:4]; default: 0;
+ *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+ *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+ */
+#define I2S_RX_STOP_MODE    0x00000003U
+#define I2S_RX_STOP_MODE_M  (I2S_RX_STOP_MODE_V << I2S_RX_STOP_MODE_S)
+#define I2S_RX_STOP_MODE_V  0x00000003U
+#define I2S_RX_STOP_MODE_S  4
+/** I2S_RX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable receiver  in mono mode
+ */
+#define I2S_RX_MONO    (BIT(6))
+#define I2S_RX_MONO_M  (I2S_RX_MONO_V << I2S_RX_MONO_S)
+#define I2S_RX_MONO_V  0x00000001U
+#define I2S_RX_MONO_S  6
+/** I2S_RX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+ */
+#define I2S_RX_BIG_ENDIAN    (BIT(7))
+#define I2S_RX_BIG_ENDIAN_M  (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S)
+#define I2S_RX_BIG_ENDIAN_V  0x00000001U
+#define I2S_RX_BIG_ENDIAN_S  7
+/** I2S_RX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_RX_UPDATE    (BIT(8))
+#define I2S_RX_UPDATE_M  (I2S_RX_UPDATE_V << I2S_RX_UPDATE_S)
+#define I2S_RX_UPDATE_V  0x00000001U
+#define I2S_RX_UPDATE_S  8
+/** I2S_RX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+ *  channel data value is valid in I2S RX mono mode.
+ */
+#define I2S_RX_MONO_FST_VLD    (BIT(9))
+#define I2S_RX_MONO_FST_VLD_M  (I2S_RX_MONO_FST_VLD_V << I2S_RX_MONO_FST_VLD_S)
+#define I2S_RX_MONO_FST_VLD_V  0x00000001U
+#define I2S_RX_MONO_FST_VLD_S  9
+/** I2S_RX_PCM_CONF : R/W; bitpos: [11:10]; default: 1;
+ *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_RX_PCM_CONF    0x00000003U
+#define I2S_RX_PCM_CONF_M  (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S)
+#define I2S_RX_PCM_CONF_V  0x00000003U
+#define I2S_RX_PCM_CONF_S  10
+/** I2S_RX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass Compress/Decompress module for received data.
+ */
+#define I2S_RX_PCM_BYPASS    (BIT(12))
+#define I2S_RX_PCM_BYPASS_M  (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S)
+#define I2S_RX_PCM_BYPASS_V  0x00000001U
+#define I2S_RX_PCM_BYPASS_S  12
+/** I2S_RX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable receiver in Phillips standard mode
+ */
+#define I2S_RX_MSB_SHIFT    (BIT(13))
+#define I2S_RX_MSB_SHIFT_M  (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S)
+#define I2S_RX_MSB_SHIFT_V  0x00000001U
+#define I2S_RX_MSB_SHIFT_S  13
+/** I2S_RX_DONE_MODE : R/W; bitpos: [14]; default: 0;
+ *  1: I2S trigger rx_done when in_suc_eof is 1. 0: I2S trigger rx_done when RX FIFO is
+ *  full.
+ */
+#define I2S_RX_DONE_MODE    (BIT(14))
+#define I2S_RX_DONE_MODE_M  (I2S_RX_DONE_MODE_V << I2S_RX_DONE_MODE_S)
+#define I2S_RX_DONE_MODE_V  0x00000001U
+#define I2S_RX_DONE_MODE_S  14
+/** I2S_RX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+ */
+#define I2S_RX_LEFT_ALIGN    (BIT(15))
+#define I2S_RX_LEFT_ALIGN_M  (I2S_RX_LEFT_ALIGN_V << I2S_RX_LEFT_ALIGN_S)
+#define I2S_RX_LEFT_ALIGN_V  0x00000001U
+#define I2S_RX_LEFT_ALIGN_S  15
+/** I2S_RX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+ */
+#define I2S_RX_24_FILL_EN    (BIT(16))
+#define I2S_RX_24_FILL_EN_M  (I2S_RX_24_FILL_EN_V << I2S_RX_24_FILL_EN_S)
+#define I2S_RX_24_FILL_EN_V  0x00000001U
+#define I2S_RX_24_FILL_EN_S  16
+/** I2S_RX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+ *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+ */
+#define I2S_RX_WS_IDLE_POL    (BIT(17))
+#define I2S_RX_WS_IDLE_POL_M  (I2S_RX_WS_IDLE_POL_V << I2S_RX_WS_IDLE_POL_S)
+#define I2S_RX_WS_IDLE_POL_V  0x00000001U
+#define I2S_RX_WS_IDLE_POL_S  17
+/** I2S_RX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+ *  is received first.
+ */
+#define I2S_RX_BIT_ORDER    (BIT(18))
+#define I2S_RX_BIT_ORDER_M  (I2S_RX_BIT_ORDER_V << I2S_RX_BIT_ORDER_S)
+#define I2S_RX_BIT_ORDER_V  0x00000001U
+#define I2S_RX_BIT_ORDER_S  18
+/** I2S_RX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_TDM_EN    (BIT(19))
+#define I2S_RX_TDM_EN_M  (I2S_RX_TDM_EN_V << I2S_RX_TDM_EN_S)
+#define I2S_RX_TDM_EN_V  0x00000001U
+#define I2S_RX_TDM_EN_S  19
+/** I2S_RX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Rx mode . 0: Disable.
+ */
+#define I2S_RX_PDM_EN    (BIT(20))
+#define I2S_RX_PDM_EN_M  (I2S_RX_PDM_EN_V << I2S_RX_PDM_EN_S)
+#define I2S_RX_PDM_EN_V  0x00000001U
+#define I2S_RX_PDM_EN_S  20
+/** I2S_RX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in receiver mode.
+ */
+#define I2S_RX_BCK_DIV_NUM    0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_M  (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S)
+#define I2S_RX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_RX_BCK_DIV_NUM_S  21
+
+/** I2S_TX_CONF_REG register
+ *  I2S TX configure register
+ */
+#define I2S_TX_CONF_REG (DR_REG_I2S_BASE + 0x24)
+/** I2S_TX_RESET : WT; bitpos: [0]; default: 0;
+ *  Set this bit to reset transmitter
+ */
+#define I2S_TX_RESET    (BIT(0))
+#define I2S_TX_RESET_M  (I2S_TX_RESET_V << I2S_TX_RESET_S)
+#define I2S_TX_RESET_V  0x00000001U
+#define I2S_TX_RESET_S  0
+/** I2S_TX_FIFO_RESET : WT; bitpos: [1]; default: 0;
+ *  Set this bit to reset Tx AFIFO
+ */
+#define I2S_TX_FIFO_RESET    (BIT(1))
+#define I2S_TX_FIFO_RESET_M  (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S)
+#define I2S_TX_FIFO_RESET_V  0x00000001U
+#define I2S_TX_FIFO_RESET_S  1
+/** I2S_TX_START : R/W/SC; bitpos: [2]; default: 0;
+ *  Set this bit to start transmitting data
+ */
+#define I2S_TX_START    (BIT(2))
+#define I2S_TX_START_M  (I2S_TX_START_V << I2S_TX_START_S)
+#define I2S_TX_START_V  0x00000001U
+#define I2S_TX_START_S  2
+/** I2S_TX_SLAVE_MOD : R/W; bitpos: [3]; default: 0;
+ *  Set this bit to enable slave transmitter mode
+ */
+#define I2S_TX_SLAVE_MOD    (BIT(3))
+#define I2S_TX_SLAVE_MOD_M  (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S)
+#define I2S_TX_SLAVE_MOD_V  0x00000001U
+#define I2S_TX_SLAVE_MOD_S  3
+/** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+ */
+#define I2S_TX_STOP_EN    (BIT(4))
+#define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)
+#define I2S_TX_STOP_EN_V  0x00000001U
+#define I2S_TX_STOP_EN_S  4
+/** I2S_TX_CHAN_EQUAL : R/W; bitpos: [5]; default: 0;
+ *  1: The value of Left channel data is equal to the value of right channel data in
+ *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+ *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+ */
+#define I2S_TX_CHAN_EQUAL    (BIT(5))
+#define I2S_TX_CHAN_EQUAL_M  (I2S_TX_CHAN_EQUAL_V << I2S_TX_CHAN_EQUAL_S)
+#define I2S_TX_CHAN_EQUAL_V  0x00000001U
+#define I2S_TX_CHAN_EQUAL_S  5
+/** I2S_TX_MONO : R/W; bitpos: [6]; default: 0;
+ *  Set this bit to enable transmitter in mono mode
+ */
+#define I2S_TX_MONO    (BIT(6))
+#define I2S_TX_MONO_M  (I2S_TX_MONO_V << I2S_TX_MONO_S)
+#define I2S_TX_MONO_V  0x00000001U
+#define I2S_TX_MONO_S  6
+/** I2S_TX_BIG_ENDIAN : R/W; bitpos: [7]; default: 0;
+ *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+ *  value.
+ */
+#define I2S_TX_BIG_ENDIAN    (BIT(7))
+#define I2S_TX_BIG_ENDIAN_M  (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S)
+#define I2S_TX_BIG_ENDIAN_V  0x00000001U
+#define I2S_TX_BIG_ENDIAN_S  7
+/** I2S_TX_UPDATE : R/W/SC; bitpos: [8]; default: 0;
+ *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+ *  bit will be cleared by hardware after update register done.
+ */
+#define I2S_TX_UPDATE    (BIT(8))
+#define I2S_TX_UPDATE_M  (I2S_TX_UPDATE_V << I2S_TX_UPDATE_S)
+#define I2S_TX_UPDATE_V  0x00000001U
+#define I2S_TX_UPDATE_S  8
+/** I2S_TX_MONO_FST_VLD : R/W; bitpos: [9]; default: 1;
+ *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+ *  channel data value is valid in I2S TX mono mode.
+ */
+#define I2S_TX_MONO_FST_VLD    (BIT(9))
+#define I2S_TX_MONO_FST_VLD_M  (I2S_TX_MONO_FST_VLD_V << I2S_TX_MONO_FST_VLD_S)
+#define I2S_TX_MONO_FST_VLD_V  0x00000001U
+#define I2S_TX_MONO_FST_VLD_S  9
+/** I2S_TX_PCM_CONF : R/W; bitpos: [11:10]; default: 0;
+ *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+ *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+ */
+#define I2S_TX_PCM_CONF    0x00000003U
+#define I2S_TX_PCM_CONF_M  (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S)
+#define I2S_TX_PCM_CONF_V  0x00000003U
+#define I2S_TX_PCM_CONF_S  10
+/** I2S_TX_PCM_BYPASS : R/W; bitpos: [12]; default: 1;
+ *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+ */
+#define I2S_TX_PCM_BYPASS    (BIT(12))
+#define I2S_TX_PCM_BYPASS_M  (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S)
+#define I2S_TX_PCM_BYPASS_V  0x00000001U
+#define I2S_TX_PCM_BYPASS_S  12
+/** I2S_TX_MSB_SHIFT : R/W; bitpos: [13]; default: 1;
+ *  Set this bit to enable transmitter in Phillips standard mode
+ */
+#define I2S_TX_MSB_SHIFT    (BIT(13))
+#define I2S_TX_MSB_SHIFT_M  (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S)
+#define I2S_TX_MSB_SHIFT_V  0x00000001U
+#define I2S_TX_MSB_SHIFT_S  13
+/** I2S_TX_BCK_NO_DLY : R/W; bitpos: [14]; default: 1;
+ *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+ *  generate pos/neg edge in master mode.
+ */
+#define I2S_TX_BCK_NO_DLY    (BIT(14))
+#define I2S_TX_BCK_NO_DLY_M  (I2S_TX_BCK_NO_DLY_V << I2S_TX_BCK_NO_DLY_S)
+#define I2S_TX_BCK_NO_DLY_V  0x00000001U
+#define I2S_TX_BCK_NO_DLY_S  14
+/** I2S_TX_LEFT_ALIGN : R/W; bitpos: [15]; default: 1;
+ *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+ */
+#define I2S_TX_LEFT_ALIGN    (BIT(15))
+#define I2S_TX_LEFT_ALIGN_M  (I2S_TX_LEFT_ALIGN_V << I2S_TX_LEFT_ALIGN_S)
+#define I2S_TX_LEFT_ALIGN_V  0x00000001U
+#define I2S_TX_LEFT_ALIGN_S  15
+/** I2S_TX_24_FILL_EN : R/W; bitpos: [16]; default: 0;
+ *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+ */
+#define I2S_TX_24_FILL_EN    (BIT(16))
+#define I2S_TX_24_FILL_EN_M  (I2S_TX_24_FILL_EN_V << I2S_TX_24_FILL_EN_S)
+#define I2S_TX_24_FILL_EN_V  0x00000001U
+#define I2S_TX_24_FILL_EN_S  16
+/** I2S_TX_WS_IDLE_POL : R/W; bitpos: [17]; default: 0;
+ *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+ *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+ */
+#define I2S_TX_WS_IDLE_POL    (BIT(17))
+#define I2S_TX_WS_IDLE_POL_M  (I2S_TX_WS_IDLE_POL_V << I2S_TX_WS_IDLE_POL_S)
+#define I2S_TX_WS_IDLE_POL_V  0x00000001U
+#define I2S_TX_WS_IDLE_POL_S  17
+/** I2S_TX_BIT_ORDER : R/W; bitpos: [18]; default: 0;
+ *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+ *  sent first.
+ */
+#define I2S_TX_BIT_ORDER    (BIT(18))
+#define I2S_TX_BIT_ORDER_M  (I2S_TX_BIT_ORDER_V << I2S_TX_BIT_ORDER_S)
+#define I2S_TX_BIT_ORDER_V  0x00000001U
+#define I2S_TX_BIT_ORDER_S  18
+/** I2S_TX_TDM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable I2S TDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_TDM_EN    (BIT(19))
+#define I2S_TX_TDM_EN_M  (I2S_TX_TDM_EN_V << I2S_TX_TDM_EN_S)
+#define I2S_TX_TDM_EN_V  0x00000001U
+#define I2S_TX_TDM_EN_S  19
+/** I2S_TX_PDM_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Enable I2S PDM Tx mode . 0: Disable.
+ */
+#define I2S_TX_PDM_EN    (BIT(20))
+#define I2S_TX_PDM_EN_M  (I2S_TX_PDM_EN_V << I2S_TX_PDM_EN_S)
+#define I2S_TX_PDM_EN_V  0x00000001U
+#define I2S_TX_PDM_EN_S  20
+/** I2S_TX_BCK_DIV_NUM : R/W; bitpos: [26:21]; default: 6;
+ *  Bit clock configuration bits in transmitter mode.
+ */
+#define I2S_TX_BCK_DIV_NUM    0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_M  (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S)
+#define I2S_TX_BCK_DIV_NUM_V  0x0000003FU
+#define I2S_TX_BCK_DIV_NUM_S  21
+/** I2S_TX_CHAN_MOD : R/W; bitpos: [29:27]; default: 0;
+ *  I2S transmitter channel mode configuration bits.
+ */
+#define I2S_TX_CHAN_MOD    0x00000007U
+#define I2S_TX_CHAN_MOD_M  (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S)
+#define I2S_TX_CHAN_MOD_V  0x00000007U
+#define I2S_TX_CHAN_MOD_S  27
+/** I2S_SIG_LOOPBACK : R/W; bitpos: [30]; default: 0;
+ *  Enable signal loop back mode with transmitter module and receiver module sharing
+ *  the same WS and BCK signals.
+ */
+#define I2S_SIG_LOOPBACK    (BIT(30))
+#define I2S_SIG_LOOPBACK_M  (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S)
+#define I2S_SIG_LOOPBACK_V  0x00000001U
+#define I2S_SIG_LOOPBACK_S  30
+
+/** I2S_RX_CONF1_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_CONF1_REG (DR_REG_I2S_BASE + 0x28)
+/** I2S_RX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_RX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_M  (I2S_RX_TDM_WS_WIDTH_V << I2S_RX_TDM_WS_WIDTH_S)
+#define I2S_RX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_RX_TDM_WS_WIDTH_S  0
+/** I2S_RX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+ *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_RX_BITS_MOD    0x0000001FU
+#define I2S_RX_BITS_MOD_M  (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S)
+#define I2S_RX_BITS_MOD_V  0x0000001FU
+#define I2S_RX_BITS_MOD_S  14
+/** I2S_RX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Rx half sample bits -1.
+ */
+#define I2S_RX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_M  (I2S_RX_HALF_SAMPLE_BITS_V << I2S_RX_HALF_SAMPLE_BITS_S)
+#define I2S_RX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_RX_HALF_SAMPLE_BITS_S  19
+/** I2S_RX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Rx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_RX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_M  (I2S_RX_TDM_CHAN_BITS_V << I2S_RX_TDM_CHAN_BITS_S)
+#define I2S_RX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_RX_TDM_CHAN_BITS_S  27
+
+/** I2S_TX_CONF1_REG register
+ *  I2S TX configure register 1
+ */
+#define I2S_TX_CONF1_REG (DR_REG_I2S_BASE + 0x2c)
+/** I2S_TX_TDM_WS_WIDTH : R/W; bitpos: [8:0]; default: 0;
+ *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+ *  T_bck
+ */
+#define I2S_TX_TDM_WS_WIDTH    0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_M  (I2S_TX_TDM_WS_WIDTH_V << I2S_TX_TDM_WS_WIDTH_S)
+#define I2S_TX_TDM_WS_WIDTH_V  0x000001FFU
+#define I2S_TX_TDM_WS_WIDTH_S  0
+/** I2S_TX_BITS_MOD : R/W; bitpos: [18:14]; default: 15;
+ *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+ *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+ *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+ *  channel data is in 32-bit-mode.
+ */
+#define I2S_TX_BITS_MOD    0x0000001FU
+#define I2S_TX_BITS_MOD_M  (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S)
+#define I2S_TX_BITS_MOD_V  0x0000001FU
+#define I2S_TX_BITS_MOD_S  14
+/** I2S_TX_HALF_SAMPLE_BITS : R/W; bitpos: [26:19]; default: 15;
+ *  I2S Tx half sample bits -1.
+ */
+#define I2S_TX_HALF_SAMPLE_BITS    0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_M  (I2S_TX_HALF_SAMPLE_BITS_V << I2S_TX_HALF_SAMPLE_BITS_S)
+#define I2S_TX_HALF_SAMPLE_BITS_V  0x000000FFU
+#define I2S_TX_HALF_SAMPLE_BITS_S  19
+/** I2S_TX_TDM_CHAN_BITS : R/W; bitpos: [31:27]; default: 15;
+ *  The Tx bit number for each channel minus 1in TDM mode.
+ */
+#define I2S_TX_TDM_CHAN_BITS    0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_M  (I2S_TX_TDM_CHAN_BITS_V << I2S_TX_TDM_CHAN_BITS_S)
+#define I2S_TX_TDM_CHAN_BITS_V  0x0000001FU
+#define I2S_TX_TDM_CHAN_BITS_S  27
+
+/** I2S_RX_RECOMB_CTRL_REG register
+ *  I2S RX configure register 1
+ */
+#define I2S_RX_RECOMB_CTRL_REG (DR_REG_I2S_BASE + 0x30)
+/** I2S_RX_RECOMB_EN : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable i2s rx data recombination.
+ */
+#define I2S_RX_RECOMB_EN    (BIT(0))
+#define I2S_RX_RECOMB_EN_M  (I2S_RX_RECOMB_EN_V << I2S_RX_RECOMB_EN_S)
+#define I2S_RX_RECOMB_EN_V  0x00000001U
+#define I2S_RX_RECOMB_EN_S  0
+/** I2S_RX_RECOMB_EXT_CH_NUM : R/W; bitpos: [2:1]; default: 0;
+ *  The channel number that i2s will extract the data into.
+ */
+#define I2S_RX_RECOMB_EXT_CH_NUM    0x00000003U
+#define I2S_RX_RECOMB_EXT_CH_NUM_M  (I2S_RX_RECOMB_EXT_CH_NUM_V << I2S_RX_RECOMB_EXT_CH_NUM_S)
+#define I2S_RX_RECOMB_EXT_CH_NUM_V  0x00000003U
+#define I2S_RX_RECOMB_EXT_CH_NUM_S  1
+/** I2S_RX_RECOMB_UPDATE : WT; bitpos: [31]; default: 0;
+ *  Set this bit to update i2s data recombination configuration, must be performed
+ *  after changing the config of any recombined-dma-channel.
+ */
+#define I2S_RX_RECOMB_UPDATE    (BIT(31))
+#define I2S_RX_RECOMB_UPDATE_M  (I2S_RX_RECOMB_UPDATE_V << I2S_RX_RECOMB_UPDATE_S)
+#define I2S_RX_RECOMB_UPDATE_V  0x00000001U
+#define I2S_RX_RECOMB_UPDATE_S  31
+
+/** I2S_RX_RECOMB_DMA_CH0_REG register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+#define I2S_RX_RECOMB_DMA_CH0_REG (DR_REG_I2S_BASE + 0x34)
+/** I2S_RX_RECOMB_DMA_CH0_VALID : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the adc-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH0_VALID    (BIT(0))
+#define I2S_RX_RECOMB_DMA_CH0_VALID_M  (I2S_RX_RECOMB_DMA_CH0_VALID_V << I2S_RX_RECOMB_DMA_CH0_VALID_S)
+#define I2S_RX_RECOMB_DMA_CH0_VALID_V  0x00000001U
+#define I2S_RX_RECOMB_DMA_CH0_VALID_S  0
+/** I2S_RX_RECOMB_DMA_CH0_STYLE : R/W; bitpos: [4:1]; default: 0;
+ *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+ *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+ */
+#define I2S_RX_RECOMB_DMA_CH0_STYLE    0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH0_STYLE_M  (I2S_RX_RECOMB_DMA_CH0_STYLE_V << I2S_RX_RECOMB_DMA_CH0_STYLE_S)
+#define I2S_RX_RECOMB_DMA_CH0_STYLE_V  0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH0_STYLE_S  1
+/** I2S_RX_RECOMB_DMA_CH0_ORDER : R/W; bitpos: [12:5]; default: 0;
+ *  Set this field to set the recombined-dma-channel order. If choose to use the order
+ *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+ */
+#define I2S_RX_RECOMB_DMA_CH0_ORDER    0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH0_ORDER_M  (I2S_RX_RECOMB_DMA_CH0_ORDER_V << I2S_RX_RECOMB_DMA_CH0_ORDER_S)
+#define I2S_RX_RECOMB_DMA_CH0_ORDER_V  0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH0_ORDER_S  5
+/** I2S_RX_RECOMB_DMA_CH0_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
+ *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM    0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_M  (I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S)
+#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V  0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S  13
+
+/** I2S_RX_RECOMB_DMA_CH1_REG register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+#define I2S_RX_RECOMB_DMA_CH1_REG (DR_REG_I2S_BASE + 0x38)
+/** I2S_RX_RECOMB_DMA_CH1_VALID : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the adc-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH1_VALID    (BIT(0))
+#define I2S_RX_RECOMB_DMA_CH1_VALID_M  (I2S_RX_RECOMB_DMA_CH1_VALID_V << I2S_RX_RECOMB_DMA_CH1_VALID_S)
+#define I2S_RX_RECOMB_DMA_CH1_VALID_V  0x00000001U
+#define I2S_RX_RECOMB_DMA_CH1_VALID_S  0
+/** I2S_RX_RECOMB_DMA_CH1_STYLE : R/W; bitpos: [4:1]; default: 0;
+ *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+ *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+ */
+#define I2S_RX_RECOMB_DMA_CH1_STYLE    0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH1_STYLE_M  (I2S_RX_RECOMB_DMA_CH1_STYLE_V << I2S_RX_RECOMB_DMA_CH1_STYLE_S)
+#define I2S_RX_RECOMB_DMA_CH1_STYLE_V  0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH1_STYLE_S  1
+/** I2S_RX_RECOMB_DMA_CH1_ORDER : R/W; bitpos: [12:5]; default: 0;
+ *  Set this field to set the recombined-dma-channel order. If choose to use the order
+ *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+ */
+#define I2S_RX_RECOMB_DMA_CH1_ORDER    0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH1_ORDER_M  (I2S_RX_RECOMB_DMA_CH1_ORDER_V << I2S_RX_RECOMB_DMA_CH1_ORDER_S)
+#define I2S_RX_RECOMB_DMA_CH1_ORDER_V  0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH1_ORDER_S  5
+/** I2S_RX_RECOMB_DMA_CH1_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
+ *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM    0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_M  (I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S)
+#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V  0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S  13
+
+/** I2S_RX_RECOMB_DMA_CH2_REG register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+#define I2S_RX_RECOMB_DMA_CH2_REG (DR_REG_I2S_BASE + 0x3c)
+/** I2S_RX_RECOMB_DMA_CH2_VALID : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the adc-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH2_VALID    (BIT(0))
+#define I2S_RX_RECOMB_DMA_CH2_VALID_M  (I2S_RX_RECOMB_DMA_CH2_VALID_V << I2S_RX_RECOMB_DMA_CH2_VALID_S)
+#define I2S_RX_RECOMB_DMA_CH2_VALID_V  0x00000001U
+#define I2S_RX_RECOMB_DMA_CH2_VALID_S  0
+/** I2S_RX_RECOMB_DMA_CH2_STYLE : R/W; bitpos: [4:1]; default: 0;
+ *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+ *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+ */
+#define I2S_RX_RECOMB_DMA_CH2_STYLE    0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH2_STYLE_M  (I2S_RX_RECOMB_DMA_CH2_STYLE_V << I2S_RX_RECOMB_DMA_CH2_STYLE_S)
+#define I2S_RX_RECOMB_DMA_CH2_STYLE_V  0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH2_STYLE_S  1
+/** I2S_RX_RECOMB_DMA_CH2_ORDER : R/W; bitpos: [12:5]; default: 0;
+ *  Set this field to set the recombined-dma-channel order. If choose to use the order
+ *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+ */
+#define I2S_RX_RECOMB_DMA_CH2_ORDER    0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH2_ORDER_M  (I2S_RX_RECOMB_DMA_CH2_ORDER_V << I2S_RX_RECOMB_DMA_CH2_ORDER_S)
+#define I2S_RX_RECOMB_DMA_CH2_ORDER_V  0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH2_ORDER_S  5
+/** I2S_RX_RECOMB_DMA_CH2_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
+ *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM    0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_M  (I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S)
+#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V  0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S  13
+
+/** I2S_RX_RECOMB_DMA_CH3_REG register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+#define I2S_RX_RECOMB_DMA_CH3_REG (DR_REG_I2S_BASE + 0x40)
+/** I2S_RX_RECOMB_DMA_CH3_VALID : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to enable the adc-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH3_VALID    (BIT(0))
+#define I2S_RX_RECOMB_DMA_CH3_VALID_M  (I2S_RX_RECOMB_DMA_CH3_VALID_V << I2S_RX_RECOMB_DMA_CH3_VALID_S)
+#define I2S_RX_RECOMB_DMA_CH3_VALID_V  0x00000001U
+#define I2S_RX_RECOMB_DMA_CH3_VALID_S  0
+/** I2S_RX_RECOMB_DMA_CH3_STYLE : R/W; bitpos: [4:1]; default: 0;
+ *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+ *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+ */
+#define I2S_RX_RECOMB_DMA_CH3_STYLE    0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH3_STYLE_M  (I2S_RX_RECOMB_DMA_CH3_STYLE_V << I2S_RX_RECOMB_DMA_CH3_STYLE_S)
+#define I2S_RX_RECOMB_DMA_CH3_STYLE_V  0x0000000FU
+#define I2S_RX_RECOMB_DMA_CH3_STYLE_S  1
+/** I2S_RX_RECOMB_DMA_CH3_ORDER : R/W; bitpos: [12:5]; default: 0;
+ *  Set this field to set the recombined-dma-channel order. If choose to use the order
+ *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+ */
+#define I2S_RX_RECOMB_DMA_CH3_ORDER    0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH3_ORDER_M  (I2S_RX_RECOMB_DMA_CH3_ORDER_V << I2S_RX_RECOMB_DMA_CH3_ORDER_S)
+#define I2S_RX_RECOMB_DMA_CH3_ORDER_V  0x000000FFU
+#define I2S_RX_RECOMB_DMA_CH3_ORDER_S  5
+/** I2S_RX_RECOMB_DMA_CH3_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
+ *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+ */
+#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM    0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_M  (I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S)
+#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V  0x0000FFFFU
+#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S  13
+
+/** I2S_TX_PCM2PDM_CONF_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF_REG (DR_REG_I2S_BASE + 0x44)
+/** I2S_TX_PDM_SINC_OSR2 : R/W; bitpos: [4:1]; default: 2;
+ *  I2S TX PDM OSR2 value
+ */
+#define I2S_TX_PDM_SINC_OSR2    0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_M  (I2S_TX_PDM_SINC_OSR2_V << I2S_TX_PDM_SINC_OSR2_S)
+#define I2S_TX_PDM_SINC_OSR2_V  0x0000000FU
+#define I2S_TX_PDM_SINC_OSR2_S  1
+/** I2S_TX_PDM_PRESCALE : R/W; bitpos: [12:5]; default: 0;
+ *  I2S TX PDM prescale for sigmadelta
+ */
+#define I2S_TX_PDM_PRESCALE    0x000000FFU
+#define I2S_TX_PDM_PRESCALE_M  (I2S_TX_PDM_PRESCALE_V << I2S_TX_PDM_PRESCALE_S)
+#define I2S_TX_PDM_PRESCALE_V  0x000000FFU
+#define I2S_TX_PDM_PRESCALE_S  5
+/** I2S_TX_PDM_HP_IN_SHIFT : R/W; bitpos: [14:13]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_HP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_M  (I2S_TX_PDM_HP_IN_SHIFT_V << I2S_TX_PDM_HP_IN_SHIFT_S)
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_HP_IN_SHIFT_S  13
+/** I2S_TX_PDM_LP_IN_SHIFT : R/W; bitpos: [16:15]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_LP_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_M  (I2S_TX_PDM_LP_IN_SHIFT_V << I2S_TX_PDM_LP_IN_SHIFT_S)
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_LP_IN_SHIFT_S  15
+/** I2S_TX_PDM_SINC_IN_SHIFT : R/W; bitpos: [18:17]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SINC_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  (I2S_TX_PDM_SINC_IN_SHIFT_V << I2S_TX_PDM_SINC_IN_SHIFT_S)
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  17
+/** I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W; bitpos: [20:19]; default: 1;
+ *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+ */
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT    0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  (I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V << I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x00000003U
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  19
+/** I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W; bitpos: [21]; default: 0;
+ *  I2S TX PDM sigmadelta dither2 value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER2    (BIT(21))
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_M  (I2S_TX_PDM_SIGMADELTA_DITHER2_V << I2S_TX_PDM_SIGMADELTA_DITHER2_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER2_S  21
+/** I2S_TX_PDM_SIGMADELTA_DITHER : R/W; bitpos: [22]; default: 1;
+ *  I2S TX PDM sigmadelta dither value
+ */
+#define I2S_TX_PDM_SIGMADELTA_DITHER    (BIT(22))
+#define I2S_TX_PDM_SIGMADELTA_DITHER_M  (I2S_TX_PDM_SIGMADELTA_DITHER_V << I2S_TX_PDM_SIGMADELTA_DITHER_S)
+#define I2S_TX_PDM_SIGMADELTA_DITHER_V  0x00000001U
+#define I2S_TX_PDM_SIGMADELTA_DITHER_S  22
+/** I2S_TX_PDM_DAC_2OUT_EN : R/W; bitpos: [23]; default: 0;
+ *  I2S TX PDM dac mode enable
+ */
+#define I2S_TX_PDM_DAC_2OUT_EN    (BIT(23))
+#define I2S_TX_PDM_DAC_2OUT_EN_M  (I2S_TX_PDM_DAC_2OUT_EN_V << I2S_TX_PDM_DAC_2OUT_EN_S)
+#define I2S_TX_PDM_DAC_2OUT_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_2OUT_EN_S  23
+/** I2S_TX_PDM_DAC_MODE_EN : R/W; bitpos: [24]; default: 0;
+ *  I2S TX PDM dac 2channel enable
+ */
+#define I2S_TX_PDM_DAC_MODE_EN    (BIT(24))
+#define I2S_TX_PDM_DAC_MODE_EN_M  (I2S_TX_PDM_DAC_MODE_EN_V << I2S_TX_PDM_DAC_MODE_EN_S)
+#define I2S_TX_PDM_DAC_MODE_EN_V  0x00000001U
+#define I2S_TX_PDM_DAC_MODE_EN_S  24
+/** I2S_PCM2PDM_CONV_EN : R/W; bitpos: [25]; default: 0;
+ *  I2S TX PDM Converter enable
+ */
+#define I2S_PCM2PDM_CONV_EN    (BIT(25))
+#define I2S_PCM2PDM_CONV_EN_M  (I2S_PCM2PDM_CONV_EN_V << I2S_PCM2PDM_CONV_EN_S)
+#define I2S_PCM2PDM_CONV_EN_V  0x00000001U
+#define I2S_PCM2PDM_CONV_EN_S  25
+
+/** I2S_TX_PCM2PDM_CONF1_REG register
+ *  I2S TX PCM2PDM configuration register
+ */
+#define I2S_TX_PCM2PDM_CONF1_REG (DR_REG_I2S_BASE + 0x48)
+/** I2S_TX_PDM_FP : R/W; bitpos: [9:0]; default: 960;
+ *  I2S TX PDM Fp
+ */
+#define I2S_TX_PDM_FP    0x000003FFU
+#define I2S_TX_PDM_FP_M  (I2S_TX_PDM_FP_V << I2S_TX_PDM_FP_S)
+#define I2S_TX_PDM_FP_V  0x000003FFU
+#define I2S_TX_PDM_FP_S  0
+/** I2S_TX_PDM_FS : R/W; bitpos: [19:10]; default: 480;
+ *  I2S TX PDM Fs
+ */
+#define I2S_TX_PDM_FS    0x000003FFU
+#define I2S_TX_PDM_FS_M  (I2S_TX_PDM_FS_V << I2S_TX_PDM_FS_S)
+#define I2S_TX_PDM_FS_V  0x000003FFU
+#define I2S_TX_PDM_FS_S  10
+/** I2S_TX_IIR_HP_MULT12_5 : R/W; bitpos: [22:20]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_M  (I2S_TX_IIR_HP_MULT12_5_V << I2S_TX_IIR_HP_MULT12_5_S)
+#define I2S_TX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_5_S  20
+/** I2S_TX_IIR_HP_MULT12_0 : R/W; bitpos: [25:23]; default: 7;
+ *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+ *  I2S_TX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_TX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_M  (I2S_TX_IIR_HP_MULT12_0_V << I2S_TX_IIR_HP_MULT12_0_S)
+#define I2S_TX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_TX_IIR_HP_MULT12_0_S  23
+
+/** I2S_RX_PDM2PCM_CONF_REG register
+ *  I2S RX configure register
+ */
+#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x4c)
+/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
+ *  1: Enable PDM2PCM RX mode. 0: DIsable.
+ */
+#define I2S_RX_PDM2PCM_EN    (BIT(19))
+#define I2S_RX_PDM2PCM_EN_M  (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
+#define I2S_RX_PDM2PCM_EN_V  0x00000001U
+#define I2S_RX_PDM2PCM_EN_S  19
+/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
+ *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+ *  sampling rate is 128. 0: down sampling rate is 64.
+ */
+#define I2S_RX_PDM_SINC_DSR_16_EN    (BIT(20))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x00000001U
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  20
+/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
+ *  Configure PDM RX amplify number.
+ */
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM    0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M  (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V  0x0000000FU
+#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S  21
+/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
+ *  I2S PDM RX bypass hp filter or not.
+ */
+#define I2S_RX_PDM_HP_BYPASS    (BIT(25))
+#define I2S_RX_PDM_HP_BYPASS_M  (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
+#define I2S_RX_PDM_HP_BYPASS_V  0x00000001U
+#define I2S_RX_PDM_HP_BYPASS_S  25
+/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_5    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_M  (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
+#define I2S_RX_IIR_HP_MULT12_5_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_5_S  26
+/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
+ *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+ *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+ */
+#define I2S_RX_IIR_HP_MULT12_0    0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_M  (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
+#define I2S_RX_IIR_HP_MULT12_0_V  0x00000007U
+#define I2S_RX_IIR_HP_MULT12_0_S  29
+
+/** I2S_RX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_RX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x50)
+/** I2S_RX_TDM_PDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN0_EN    (BIT(0))
+#define I2S_RX_TDM_PDM_CHAN0_EN_M  (I2S_RX_TDM_PDM_CHAN0_EN_V << I2S_RX_TDM_PDM_CHAN0_EN_S)
+#define I2S_RX_TDM_PDM_CHAN0_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN0_EN_S  0
+/** I2S_RX_TDM_PDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN1_EN    (BIT(1))
+#define I2S_RX_TDM_PDM_CHAN1_EN_M  (I2S_RX_TDM_PDM_CHAN1_EN_V << I2S_RX_TDM_PDM_CHAN1_EN_S)
+#define I2S_RX_TDM_PDM_CHAN1_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN1_EN_S  1
+/** I2S_RX_TDM_PDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN2_EN    (BIT(2))
+#define I2S_RX_TDM_PDM_CHAN2_EN_M  (I2S_RX_TDM_PDM_CHAN2_EN_V << I2S_RX_TDM_PDM_CHAN2_EN_S)
+#define I2S_RX_TDM_PDM_CHAN2_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN2_EN_S  2
+/** I2S_RX_TDM_PDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN3_EN    (BIT(3))
+#define I2S_RX_TDM_PDM_CHAN3_EN_M  (I2S_RX_TDM_PDM_CHAN3_EN_V << I2S_RX_TDM_PDM_CHAN3_EN_S)
+#define I2S_RX_TDM_PDM_CHAN3_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN3_EN_S  3
+/** I2S_RX_TDM_PDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN4_EN    (BIT(4))
+#define I2S_RX_TDM_PDM_CHAN4_EN_M  (I2S_RX_TDM_PDM_CHAN4_EN_V << I2S_RX_TDM_PDM_CHAN4_EN_S)
+#define I2S_RX_TDM_PDM_CHAN4_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN4_EN_S  4
+/** I2S_RX_TDM_PDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN5_EN    (BIT(5))
+#define I2S_RX_TDM_PDM_CHAN5_EN_M  (I2S_RX_TDM_PDM_CHAN5_EN_V << I2S_RX_TDM_PDM_CHAN5_EN_S)
+#define I2S_RX_TDM_PDM_CHAN5_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN5_EN_S  5
+/** I2S_RX_TDM_PDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN6_EN    (BIT(6))
+#define I2S_RX_TDM_PDM_CHAN6_EN_M  (I2S_RX_TDM_PDM_CHAN6_EN_V << I2S_RX_TDM_PDM_CHAN6_EN_S)
+#define I2S_RX_TDM_PDM_CHAN6_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN6_EN_S  6
+/** I2S_RX_TDM_PDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+ *  input 0 in this channel.
+ */
+#define I2S_RX_TDM_PDM_CHAN7_EN    (BIT(7))
+#define I2S_RX_TDM_PDM_CHAN7_EN_M  (I2S_RX_TDM_PDM_CHAN7_EN_V << I2S_RX_TDM_PDM_CHAN7_EN_S)
+#define I2S_RX_TDM_PDM_CHAN7_EN_V  0x00000001U
+#define I2S_RX_TDM_PDM_CHAN7_EN_S  7
+/** I2S_RX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_RX_TDM_CHAN8_EN_M  (I2S_RX_TDM_CHAN8_EN_V << I2S_RX_TDM_CHAN8_EN_S)
+#define I2S_RX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN8_EN_S  8
+/** I2S_RX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_RX_TDM_CHAN9_EN_M  (I2S_RX_TDM_CHAN9_EN_V << I2S_RX_TDM_CHAN9_EN_S)
+#define I2S_RX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN9_EN_S  9
+/** I2S_RX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_RX_TDM_CHAN10_EN_M  (I2S_RX_TDM_CHAN10_EN_V << I2S_RX_TDM_CHAN10_EN_S)
+#define I2S_RX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN10_EN_S  10
+/** I2S_RX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_RX_TDM_CHAN11_EN_M  (I2S_RX_TDM_CHAN11_EN_V << I2S_RX_TDM_CHAN11_EN_S)
+#define I2S_RX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN11_EN_S  11
+/** I2S_RX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_RX_TDM_CHAN12_EN_M  (I2S_RX_TDM_CHAN12_EN_V << I2S_RX_TDM_CHAN12_EN_S)
+#define I2S_RX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN12_EN_S  12
+/** I2S_RX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_RX_TDM_CHAN13_EN_M  (I2S_RX_TDM_CHAN13_EN_V << I2S_RX_TDM_CHAN13_EN_S)
+#define I2S_RX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN13_EN_S  13
+/** I2S_RX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_RX_TDM_CHAN14_EN_M  (I2S_RX_TDM_CHAN14_EN_V << I2S_RX_TDM_CHAN14_EN_S)
+#define I2S_RX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN14_EN_S  14
+/** I2S_RX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+ *  in this channel.
+ */
+#define I2S_RX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_RX_TDM_CHAN15_EN_M  (I2S_RX_TDM_CHAN15_EN_V << I2S_RX_TDM_CHAN15_EN_S)
+#define I2S_RX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_RX_TDM_CHAN15_EN_S  15
+/** I2S_RX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_RX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_M  (I2S_RX_TDM_TOT_CHAN_NUM_V << I2S_RX_TDM_TOT_CHAN_NUM_S)
+#define I2S_RX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_RX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_RX_TDM_BITS_MODE_DET_EN : R/W; bitpos: [20]; default: 0;
+ *  1: Auto detect bit mode in tdm slave mode. 0: Disable.
+ */
+#define I2S_RX_TDM_BITS_MODE_DET_EN    (BIT(20))
+#define I2S_RX_TDM_BITS_MODE_DET_EN_M  (I2S_RX_TDM_BITS_MODE_DET_EN_V << I2S_RX_TDM_BITS_MODE_DET_EN_S)
+#define I2S_RX_TDM_BITS_MODE_DET_EN_V  0x00000001U
+#define I2S_RX_TDM_BITS_MODE_DET_EN_S  20
+
+/** I2S_TX_TDM_CTRL_REG register
+ *  I2S TX TDM mode control register
+ */
+#define I2S_TX_TDM_CTRL_REG (DR_REG_I2S_BASE + 0x54)
+/** I2S_TX_TDM_CHAN0_EN : R/W; bitpos: [0]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN0_EN    (BIT(0))
+#define I2S_TX_TDM_CHAN0_EN_M  (I2S_TX_TDM_CHAN0_EN_V << I2S_TX_TDM_CHAN0_EN_S)
+#define I2S_TX_TDM_CHAN0_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN0_EN_S  0
+/** I2S_TX_TDM_CHAN1_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN1_EN    (BIT(1))
+#define I2S_TX_TDM_CHAN1_EN_M  (I2S_TX_TDM_CHAN1_EN_V << I2S_TX_TDM_CHAN1_EN_S)
+#define I2S_TX_TDM_CHAN1_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN1_EN_S  1
+/** I2S_TX_TDM_CHAN2_EN : R/W; bitpos: [2]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN2_EN    (BIT(2))
+#define I2S_TX_TDM_CHAN2_EN_M  (I2S_TX_TDM_CHAN2_EN_V << I2S_TX_TDM_CHAN2_EN_S)
+#define I2S_TX_TDM_CHAN2_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN2_EN_S  2
+/** I2S_TX_TDM_CHAN3_EN : R/W; bitpos: [3]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN3_EN    (BIT(3))
+#define I2S_TX_TDM_CHAN3_EN_M  (I2S_TX_TDM_CHAN3_EN_V << I2S_TX_TDM_CHAN3_EN_S)
+#define I2S_TX_TDM_CHAN3_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN3_EN_S  3
+/** I2S_TX_TDM_CHAN4_EN : R/W; bitpos: [4]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN4_EN    (BIT(4))
+#define I2S_TX_TDM_CHAN4_EN_M  (I2S_TX_TDM_CHAN4_EN_V << I2S_TX_TDM_CHAN4_EN_S)
+#define I2S_TX_TDM_CHAN4_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN4_EN_S  4
+/** I2S_TX_TDM_CHAN5_EN : R/W; bitpos: [5]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN5_EN    (BIT(5))
+#define I2S_TX_TDM_CHAN5_EN_M  (I2S_TX_TDM_CHAN5_EN_V << I2S_TX_TDM_CHAN5_EN_S)
+#define I2S_TX_TDM_CHAN5_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN5_EN_S  5
+/** I2S_TX_TDM_CHAN6_EN : R/W; bitpos: [6]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN6_EN    (BIT(6))
+#define I2S_TX_TDM_CHAN6_EN_M  (I2S_TX_TDM_CHAN6_EN_V << I2S_TX_TDM_CHAN6_EN_S)
+#define I2S_TX_TDM_CHAN6_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN6_EN_S  6
+/** I2S_TX_TDM_CHAN7_EN : R/W; bitpos: [7]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN7_EN    (BIT(7))
+#define I2S_TX_TDM_CHAN7_EN_M  (I2S_TX_TDM_CHAN7_EN_V << I2S_TX_TDM_CHAN7_EN_S)
+#define I2S_TX_TDM_CHAN7_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN7_EN_S  7
+/** I2S_TX_TDM_CHAN8_EN : R/W; bitpos: [8]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN8_EN    (BIT(8))
+#define I2S_TX_TDM_CHAN8_EN_M  (I2S_TX_TDM_CHAN8_EN_V << I2S_TX_TDM_CHAN8_EN_S)
+#define I2S_TX_TDM_CHAN8_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN8_EN_S  8
+/** I2S_TX_TDM_CHAN9_EN : R/W; bitpos: [9]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN9_EN    (BIT(9))
+#define I2S_TX_TDM_CHAN9_EN_M  (I2S_TX_TDM_CHAN9_EN_V << I2S_TX_TDM_CHAN9_EN_S)
+#define I2S_TX_TDM_CHAN9_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN9_EN_S  9
+/** I2S_TX_TDM_CHAN10_EN : R/W; bitpos: [10]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN10_EN    (BIT(10))
+#define I2S_TX_TDM_CHAN10_EN_M  (I2S_TX_TDM_CHAN10_EN_V << I2S_TX_TDM_CHAN10_EN_S)
+#define I2S_TX_TDM_CHAN10_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN10_EN_S  10
+/** I2S_TX_TDM_CHAN11_EN : R/W; bitpos: [11]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN11_EN    (BIT(11))
+#define I2S_TX_TDM_CHAN11_EN_M  (I2S_TX_TDM_CHAN11_EN_V << I2S_TX_TDM_CHAN11_EN_S)
+#define I2S_TX_TDM_CHAN11_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN11_EN_S  11
+/** I2S_TX_TDM_CHAN12_EN : R/W; bitpos: [12]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN12_EN    (BIT(12))
+#define I2S_TX_TDM_CHAN12_EN_M  (I2S_TX_TDM_CHAN12_EN_V << I2S_TX_TDM_CHAN12_EN_S)
+#define I2S_TX_TDM_CHAN12_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN12_EN_S  12
+/** I2S_TX_TDM_CHAN13_EN : R/W; bitpos: [13]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN13_EN    (BIT(13))
+#define I2S_TX_TDM_CHAN13_EN_M  (I2S_TX_TDM_CHAN13_EN_V << I2S_TX_TDM_CHAN13_EN_S)
+#define I2S_TX_TDM_CHAN13_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN13_EN_S  13
+/** I2S_TX_TDM_CHAN14_EN : R/W; bitpos: [14]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN14_EN    (BIT(14))
+#define I2S_TX_TDM_CHAN14_EN_M  (I2S_TX_TDM_CHAN14_EN_V << I2S_TX_TDM_CHAN14_EN_S)
+#define I2S_TX_TDM_CHAN14_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN14_EN_S  14
+/** I2S_TX_TDM_CHAN15_EN : R/W; bitpos: [15]; default: 1;
+ *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+ *  0 in this channel.
+ */
+#define I2S_TX_TDM_CHAN15_EN    (BIT(15))
+#define I2S_TX_TDM_CHAN15_EN_M  (I2S_TX_TDM_CHAN15_EN_V << I2S_TX_TDM_CHAN15_EN_S)
+#define I2S_TX_TDM_CHAN15_EN_V  0x00000001U
+#define I2S_TX_TDM_CHAN15_EN_S  15
+/** I2S_TX_TDM_TOT_CHAN_NUM : R/W; bitpos: [19:16]; default: 0;
+ *  The total channel number of I2S TX TDM mode.
+ */
+#define I2S_TX_TDM_TOT_CHAN_NUM    0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_M  (I2S_TX_TDM_TOT_CHAN_NUM_V << I2S_TX_TDM_TOT_CHAN_NUM_S)
+#define I2S_TX_TDM_TOT_CHAN_NUM_V  0x0000000FU
+#define I2S_TX_TDM_TOT_CHAN_NUM_S  16
+/** I2S_TX_TDM_SKIP_MSK_EN : R/W; bitpos: [20]; default: 0;
+ *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+ *  only the data of the enabled channels is sent, then this bit should be set. Clear
+ *  it when all the data stored in DMA TX buffer is for enabled channels.
+ */
+#define I2S_TX_TDM_SKIP_MSK_EN    (BIT(20))
+#define I2S_TX_TDM_SKIP_MSK_EN_M  (I2S_TX_TDM_SKIP_MSK_EN_V << I2S_TX_TDM_SKIP_MSK_EN_S)
+#define I2S_TX_TDM_SKIP_MSK_EN_V  0x00000001U
+#define I2S_TX_TDM_SKIP_MSK_EN_S  20
+/** I2S_TX_TDM_BITS_MODE_DET_EN : R/W; bitpos: [21]; default: 0;
+ *  1: Auto detect bit mode in tdm slave mode. 0: Disable.
+ */
+#define I2S_TX_TDM_BITS_MODE_DET_EN    (BIT(21))
+#define I2S_TX_TDM_BITS_MODE_DET_EN_M  (I2S_TX_TDM_BITS_MODE_DET_EN_V << I2S_TX_TDM_BITS_MODE_DET_EN_S)
+#define I2S_TX_TDM_BITS_MODE_DET_EN_V  0x00000001U
+#define I2S_TX_TDM_BITS_MODE_DET_EN_S  21
+
+/** I2S_RX_TIMING_REG register
+ *  I2S RX timing control register
+ */
+#define I2S_RX_TIMING_REG (DR_REG_I2S_BASE + 0x58)
+/** I2S_RX_SD_IN_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD_IN_DM    0x00000003U
+#define I2S_RX_SD_IN_DM_M  (I2S_RX_SD_IN_DM_V << I2S_RX_SD_IN_DM_S)
+#define I2S_RX_SD_IN_DM_V  0x00000003U
+#define I2S_RX_SD_IN_DM_S  0
+/** I2S_RX_SD1_IN_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD1_IN_DM    0x00000003U
+#define I2S_RX_SD1_IN_DM_M  (I2S_RX_SD1_IN_DM_V << I2S_RX_SD1_IN_DM_S)
+#define I2S_RX_SD1_IN_DM_V  0x00000003U
+#define I2S_RX_SD1_IN_DM_S  4
+/** I2S_RX_SD2_IN_DM : R/W; bitpos: [9:8]; default: 0;
+ *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD2_IN_DM    0x00000003U
+#define I2S_RX_SD2_IN_DM_M  (I2S_RX_SD2_IN_DM_V << I2S_RX_SD2_IN_DM_S)
+#define I2S_RX_SD2_IN_DM_V  0x00000003U
+#define I2S_RX_SD2_IN_DM_S  8
+/** I2S_RX_SD3_IN_DM : R/W; bitpos: [13:12]; default: 0;
+ *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_SD3_IN_DM    0x00000003U
+#define I2S_RX_SD3_IN_DM_M  (I2S_RX_SD3_IN_DM_V << I2S_RX_SD3_IN_DM_S)
+#define I2S_RX_SD3_IN_DM_V  0x00000003U
+#define I2S_RX_SD3_IN_DM_S  12
+/** I2S_RX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_OUT_DM    0x00000003U
+#define I2S_RX_WS_OUT_DM_M  (I2S_RX_WS_OUT_DM_V << I2S_RX_WS_OUT_DM_S)
+#define I2S_RX_WS_OUT_DM_V  0x00000003U
+#define I2S_RX_WS_OUT_DM_S  16
+/** I2S_RX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_OUT_DM    0x00000003U
+#define I2S_RX_BCK_OUT_DM_M  (I2S_RX_BCK_OUT_DM_V << I2S_RX_BCK_OUT_DM_S)
+#define I2S_RX_BCK_OUT_DM_V  0x00000003U
+#define I2S_RX_BCK_OUT_DM_S  20
+/** I2S_RX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_WS_IN_DM    0x00000003U
+#define I2S_RX_WS_IN_DM_M  (I2S_RX_WS_IN_DM_V << I2S_RX_WS_IN_DM_S)
+#define I2S_RX_WS_IN_DM_V  0x00000003U
+#define I2S_RX_WS_IN_DM_S  24
+/** I2S_RX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_RX_BCK_IN_DM    0x00000003U
+#define I2S_RX_BCK_IN_DM_M  (I2S_RX_BCK_IN_DM_V << I2S_RX_BCK_IN_DM_S)
+#define I2S_RX_BCK_IN_DM_V  0x00000003U
+#define I2S_RX_BCK_IN_DM_S  28
+
+/** I2S_TX_TIMING_REG register
+ *  I2S TX timing control register
+ */
+#define I2S_TX_TIMING_REG (DR_REG_I2S_BASE + 0x5c)
+/** I2S_TX_SD_OUT_DM : R/W; bitpos: [1:0]; default: 0;
+ *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD_OUT_DM    0x00000003U
+#define I2S_TX_SD_OUT_DM_M  (I2S_TX_SD_OUT_DM_V << I2S_TX_SD_OUT_DM_S)
+#define I2S_TX_SD_OUT_DM_V  0x00000003U
+#define I2S_TX_SD_OUT_DM_S  0
+/** I2S_TX_SD1_OUT_DM : R/W; bitpos: [5:4]; default: 0;
+ *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_SD1_OUT_DM    0x00000003U
+#define I2S_TX_SD1_OUT_DM_M  (I2S_TX_SD1_OUT_DM_V << I2S_TX_SD1_OUT_DM_S)
+#define I2S_TX_SD1_OUT_DM_V  0x00000003U
+#define I2S_TX_SD1_OUT_DM_S  4
+/** I2S_TX_WS_OUT_DM : R/W; bitpos: [17:16]; default: 0;
+ *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_OUT_DM    0x00000003U
+#define I2S_TX_WS_OUT_DM_M  (I2S_TX_WS_OUT_DM_V << I2S_TX_WS_OUT_DM_S)
+#define I2S_TX_WS_OUT_DM_V  0x00000003U
+#define I2S_TX_WS_OUT_DM_S  16
+/** I2S_TX_BCK_OUT_DM : R/W; bitpos: [21:20]; default: 0;
+ *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_OUT_DM    0x00000003U
+#define I2S_TX_BCK_OUT_DM_M  (I2S_TX_BCK_OUT_DM_V << I2S_TX_BCK_OUT_DM_S)
+#define I2S_TX_BCK_OUT_DM_V  0x00000003U
+#define I2S_TX_BCK_OUT_DM_S  20
+/** I2S_TX_WS_IN_DM : R/W; bitpos: [25:24]; default: 0;
+ *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_WS_IN_DM    0x00000003U
+#define I2S_TX_WS_IN_DM_M  (I2S_TX_WS_IN_DM_V << I2S_TX_WS_IN_DM_S)
+#define I2S_TX_WS_IN_DM_V  0x00000003U
+#define I2S_TX_WS_IN_DM_S  24
+/** I2S_TX_BCK_IN_DM : R/W; bitpos: [29:28]; default: 0;
+ *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+ *  delay by neg edge. 3: not used.
+ */
+#define I2S_TX_BCK_IN_DM    0x00000003U
+#define I2S_TX_BCK_IN_DM_M  (I2S_TX_BCK_IN_DM_V << I2S_TX_BCK_IN_DM_S)
+#define I2S_TX_BCK_IN_DM_V  0x00000003U
+#define I2S_TX_BCK_IN_DM_S  28
+
+/** I2S_LC_HUNG_CONF_REG register
+ *  I2S HUNG configure register.
+ */
+#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x60)
+/** I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16;
+ *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+ *  when fifo hung counter is equal to this value
+ */
+#define I2S_LC_FIFO_TIMEOUT    0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_M  (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S)
+#define I2S_LC_FIFO_TIMEOUT_V  0x000000FFU
+#define I2S_LC_FIFO_TIMEOUT_S  0
+/** I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0;
+ *  The bits are used to scale tick counter threshold. The tick counter is reset when
+ *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+ */
+#define I2S_LC_FIFO_TIMEOUT_SHIFT    0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S)
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x00000007U
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/** I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1;
+ *  The enable bit for FIFO timeout
+ */
+#define I2S_LC_FIFO_TIMEOUT_ENA    (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S)
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x00000001U
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+
+/** I2S_RXEOF_NUM_REG register
+ *  I2S RX data number control register.
+ */
+#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x64)
+/** I2S_RX_EOF_NUM : R/W; bitpos: [15:0]; default: 64;
+ *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0])
+ *  . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+ */
+#define I2S_RX_EOF_NUM    0x0000FFFFU
+#define I2S_RX_EOF_NUM_M  (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S)
+#define I2S_RX_EOF_NUM_V  0x0000FFFFU
+#define I2S_RX_EOF_NUM_S  0
+
+/** I2S_CONF_SIGLE_DATA_REG register
+ *  I2S signal data register
+ */
+#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x68)
+/** I2S_SINGLE_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  The configured constant channel data to be sent out.
+ */
+#define I2S_SINGLE_DATA    0xFFFFFFFFU
+#define I2S_SINGLE_DATA_M  (I2S_SINGLE_DATA_V << I2S_SINGLE_DATA_S)
+#define I2S_SINGLE_DATA_V  0xFFFFFFFFU
+#define I2S_SINGLE_DATA_S  0
+
+/** I2S_STATE_REG register
+ *  I2S TX status register
+ */
+#define I2S_STATE_REG (DR_REG_I2S_BASE + 0x6c)
+/** I2S_TX_IDLE : RO; bitpos: [0]; default: 1;
+ *  1: i2s_tx is idle state. 0: i2s_tx is working.
+ */
+#define I2S_TX_IDLE    (BIT(0))
+#define I2S_TX_IDLE_M  (I2S_TX_IDLE_V << I2S_TX_IDLE_S)
+#define I2S_TX_IDLE_V  0x00000001U
+#define I2S_TX_IDLE_S  0
+
+/** I2S_ETM_CONF_REG register
+ *  I2S ETM configure register
+ */
+#define I2S_ETM_CONF_REG (DR_REG_I2S_BASE + 0x70)
+/** I2S_ETM_TX_SEND_WORD_NUM : R/W; bitpos: [13:0]; default: 64;
+ *  I2S ETM send x words event. When sending word number of
+ *  reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_TX_SEND_WORD_NUM    0x00003FFFU
+#define I2S_ETM_TX_SEND_WORD_NUM_M  (I2S_ETM_TX_SEND_WORD_NUM_V << I2S_ETM_TX_SEND_WORD_NUM_S)
+#define I2S_ETM_TX_SEND_WORD_NUM_V  0x00003FFFU
+#define I2S_ETM_TX_SEND_WORD_NUM_S  0
+/** I2S_ETM_RX_RECEIVE_WORD_NUM : R/W; bitpos: [27:14]; default: 64;
+ *  I2S ETM receive x words event. When receiving word number of
+ *  reg_etm_rx_receive_word_num[13:0], i2s will trigger an etm event.
+ */
+#define I2S_ETM_RX_RECEIVE_WORD_NUM    0x00003FFFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_M  (I2S_ETM_RX_RECEIVE_WORD_NUM_V << I2S_ETM_RX_RECEIVE_WORD_NUM_S)
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_V  0x00003FFFU
+#define I2S_ETM_RX_RECEIVE_WORD_NUM_S  14
+
+/** I2S_IDEAL_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_IDEAL_CNT_REG (DR_REG_I2S_BASE + 0x74)
+/** I2S_TX_IDEAL_CNT : R/W; bitpos: [30:0]; default: 0;
+ *  tx fifo counter ideal value.
+ */
+#define I2S_TX_IDEAL_CNT    0x7FFFFFFFU
+#define I2S_TX_IDEAL_CNT_M  (I2S_TX_IDEAL_CNT_V << I2S_TX_IDEAL_CNT_S)
+#define I2S_TX_IDEAL_CNT_V  0x7FFFFFFFU
+#define I2S_TX_IDEAL_CNT_S  0
+
+/** I2S_FIFO_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_FIFO_CNT_REG (DR_REG_I2S_BASE + 0x78)
+/** I2S_TX_FIFO_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx fifo counter value.
+ */
+#define I2S_TX_FIFO_CNT    0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_M  (I2S_TX_FIFO_CNT_V << I2S_TX_FIFO_CNT_S)
+#define I2S_TX_FIFO_CNT_V  0x7FFFFFFFU
+#define I2S_TX_FIFO_CNT_S  0
+/** I2S_TX_FIFO_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx fifo counter.
+ */
+#define I2S_TX_FIFO_CNT_RST    (BIT(31))
+#define I2S_TX_FIFO_CNT_RST_M  (I2S_TX_FIFO_CNT_RST_V << I2S_TX_FIFO_CNT_RST_S)
+#define I2S_TX_FIFO_CNT_RST_V  0x00000001U
+#define I2S_TX_FIFO_CNT_RST_S  31
+
+/** I2S_BCK_CNT_REG register
+ *  I2S sync counter register
+ */
+#define I2S_BCK_CNT_REG (DR_REG_I2S_BASE + 0x7c)
+/** I2S_TX_BCK_CNT : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_BCK_CNT    0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_M  (I2S_TX_BCK_CNT_V << I2S_TX_BCK_CNT_S)
+#define I2S_TX_BCK_CNT_V  0x7FFFFFFFU
+#define I2S_TX_BCK_CNT_S  0
+/** I2S_TX_BCK_CNT_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset tx bck counter.
+ */
+#define I2S_TX_BCK_CNT_RST    (BIT(31))
+#define I2S_TX_BCK_CNT_RST_M  (I2S_TX_BCK_CNT_RST_V << I2S_TX_BCK_CNT_RST_S)
+#define I2S_TX_BCK_CNT_RST_V  0x00000001U
+#define I2S_TX_BCK_CNT_RST_S  31
+
+/** I2S_CNT_DIFF_REG register
+ *  I2S sync counter register
+ */
+#define I2S_CNT_DIFF_REG (DR_REG_I2S_BASE + 0x80)
+/** I2S_TX_CNT_DIFF : RO; bitpos: [30:0]; default: 0;
+ *  tx bck counter value.
+ */
+#define I2S_TX_CNT_DIFF    0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_M  (I2S_TX_CNT_DIFF_V << I2S_TX_CNT_DIFF_S)
+#define I2S_TX_CNT_DIFF_V  0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_S  0
+/** I2S_TX_CNT_DIFF_RST : WT; bitpos: [31]; default: 0;
+ *  Set this bit to reset fifo counter difference.
+ */
+#define I2S_TX_CNT_DIFF_RST    (BIT(31))
+#define I2S_TX_CNT_DIFF_RST_M  (I2S_TX_CNT_DIFF_RST_V << I2S_TX_CNT_DIFF_RST_S)
+#define I2S_TX_CNT_DIFF_RST_V  0x00000001U
+#define I2S_TX_CNT_DIFF_RST_S  31
+
+/** I2S_SYNC_SW_THRES_REG register
+ *  I2S sync counter register
+ */
+#define I2S_SYNC_SW_THRES_REG (DR_REG_I2S_BASE + 0x84)
+/** I2S_TX_CNT_DIFF_SW_THRES : R/W; bitpos: [30:0]; default: 0;
+ *  tx fifo counter difference software threshold value, when difference larger than
+ *  this threshold, interrupt will occur and hardware sync will not be executed.
+ */
+#define I2S_TX_CNT_DIFF_SW_THRES    0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_SW_THRES_M  (I2S_TX_CNT_DIFF_SW_THRES_V << I2S_TX_CNT_DIFF_SW_THRES_S)
+#define I2S_TX_CNT_DIFF_SW_THRES_V  0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_SW_THRES_S  0
+
+/** I2S_SYNC_HW_THRES_REG register
+ *  I2S sync counter register
+ */
+#define I2S_SYNC_HW_THRES_REG (DR_REG_I2S_BASE + 0x88)
+/** I2S_TX_CNT_DIFF_HW_THRES : R/W; bitpos: [30:0]; default: 0;
+ *  tx fifo counter difference hardware threshold value, which means that only when
+ *  difference larger than this threshold will hardware start hardware sync.
+ */
+#define I2S_TX_CNT_DIFF_HW_THRES    0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_HW_THRES_M  (I2S_TX_CNT_DIFF_HW_THRES_V << I2S_TX_CNT_DIFF_HW_THRES_S)
+#define I2S_TX_CNT_DIFF_HW_THRES_V  0x7FFFFFFFU
+#define I2S_TX_CNT_DIFF_HW_THRES_S  0
+
+/** I2S_HW_SYNC_CONF_REG register
+ *  I2S TX hardware sync function configuration register
+ */
+#define I2S_HW_SYNC_CONF_REG (DR_REG_I2S_BASE + 0x8c)
+/** I2S_TX_HW_SYNC_EN : R/W; bitpos: [0]; default: 0;
+ *  Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable
+ */
+#define I2S_TX_HW_SYNC_EN    (BIT(0))
+#define I2S_TX_HW_SYNC_EN_M  (I2S_TX_HW_SYNC_EN_V << I2S_TX_HW_SYNC_EN_S)
+#define I2S_TX_HW_SYNC_EN_V  0x00000001U
+#define I2S_TX_HW_SYNC_EN_S  0
+/** I2S_TX_HW_SYNC_SUPPL_MODE : R/W; bitpos: [1]; default: 0;
+ *  Configure the i2s tx hardware sync supplementation mode. 1: Supplement the data
+ *  configured in I2S_TX_HW_SYNC_SUPPL_DATA[31:0]. 0: Supplement the last data.
+ */
+#define I2S_TX_HW_SYNC_SUPPL_MODE    (BIT(1))
+#define I2S_TX_HW_SYNC_SUPPL_MODE_M  (I2S_TX_HW_SYNC_SUPPL_MODE_V << I2S_TX_HW_SYNC_SUPPL_MODE_S)
+#define I2S_TX_HW_SYNC_SUPPL_MODE_V  0x00000001U
+#define I2S_TX_HW_SYNC_SUPPL_MODE_S  1
+
+/** I2S_HW_SYNC_DATA_REG register
+ *  I2S TX hardware sync function configuration register
+ */
+#define I2S_HW_SYNC_DATA_REG (DR_REG_I2S_BASE + 0x90)
+/** I2S_TX_HW_SYNC_SUPPL_DATA : R/W; bitpos: [31:0]; default: 0;
+ *  Configure the i2s tx hardware sync supplementation data when
+ *  I2S_TX_HW_SYNC_SUPPL_MODE is 1.
+ */
+#define I2S_TX_HW_SYNC_SUPPL_DATA    0xFFFFFFFFU
+#define I2S_TX_HW_SYNC_SUPPL_DATA_M  (I2S_TX_HW_SYNC_SUPPL_DATA_V << I2S_TX_HW_SYNC_SUPPL_DATA_S)
+#define I2S_TX_HW_SYNC_SUPPL_DATA_V  0xFFFFFFFFU
+#define I2S_TX_HW_SYNC_SUPPL_DATA_S  0
+
+/** I2S_DESTINATION_REG register
+ *  I2S TX status register
+ */
+#define I2S_DESTINATION_REG (DR_REG_I2S_BASE + 0xf4)
+/** I2S_RX_DESTINATION : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to configure the data destination of i2s rx. 1: ble. 0: gdma.
+ */
+#define I2S_RX_DESTINATION    (BIT(0))
+#define I2S_RX_DESTINATION_M  (I2S_RX_DESTINATION_V << I2S_RX_DESTINATION_S)
+#define I2S_RX_DESTINATION_V  0x00000001U
+#define I2S_RX_DESTINATION_S  0
+/** I2S_TX_DESTINATION : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to configure the data destination of i2s tx. 1: ble. 0: gdma.
+ */
+#define I2S_TX_DESTINATION    (BIT(1))
+#define I2S_TX_DESTINATION_M  (I2S_TX_DESTINATION_V << I2S_TX_DESTINATION_S)
+#define I2S_TX_DESTINATION_V  0x00000001U
+#define I2S_TX_DESTINATION_S  1
+
+/** I2S_CLK_GATE_REG register
+ *  Clock gate register
+ */
+#define I2S_CLK_GATE_REG (DR_REG_I2S_BASE + 0xf8)
+/** I2S_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  set this bit to enable clock gate
+ */
+#define I2S_CLK_EN    (BIT(0))
+#define I2S_CLK_EN_M  (I2S_CLK_EN_V << I2S_CLK_EN_S)
+#define I2S_CLK_EN_V  0x00000001U
+#define I2S_CLK_EN_S  0
+
+/** I2S_DATE_REG register
+ *  Version control register
+ */
+#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc)
+/** I2S_DATE : R/W; bitpos: [27:0]; default: 38813744;
+ *  I2S version control register
+ */
+#define I2S_DATE    0x0FFFFFFFU
+#define I2S_DATE_M  (I2S_DATE_V << I2S_DATE_S)
+#define I2S_DATE_V  0x0FFFFFFFU
+#define I2S_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/i2s_struct.h b/components/soc/esp32s31/register/soc/i2s_struct.h
new file mode 100644
index 00000000000..f866bb75ff8
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/i2s_struct.h
@@ -0,0 +1,1292 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  I2S interrupt raw register, valid in level.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_raw:1;
+        /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_raw:1;
+        /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_raw:1;
+        /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_raw:1;
+        /** tx_sync_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit  for the i2s_tx_sync_int interrupt
+         */
+        uint32_t tx_sync_int_raw:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2s_int_raw_reg_t;
+
+/** Type of int_st register
+ *  I2S interrupt status register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_st:1;
+        /** tx_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_st:1;
+        /** rx_hung_int_st : RO; bitpos: [2]; default: 0;
+         *  The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_st:1;
+        /** tx_hung_int_st : RO; bitpos: [3]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_st:1;
+        /** tx_sync_int_st : RO; bitpos: [4]; default: 0;
+         *  The masked interrupt status bit  for the i2s_tx_sync_int interrupt
+         */
+        uint32_t tx_sync_int_st:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2s_int_st_reg_t;
+
+/** Type of int_ena register
+ *  I2S interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_ena:1;
+        /** tx_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_ena:1;
+        /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit  for the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_ena:1;
+        /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_ena:1;
+        /** tx_sync_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit  for the i2s_tx_sync_int interrupt
+         */
+        uint32_t tx_sync_int_ena:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2s_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  I2S interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** rx_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the i2s_rx_done_int interrupt
+         */
+        uint32_t rx_done_int_clr:1;
+        /** tx_done_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the i2s_tx_done_int interrupt
+         */
+        uint32_t tx_done_int_clr:1;
+        /** rx_hung_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the i2s_rx_hung_int interrupt
+         */
+        uint32_t rx_hung_int_clr:1;
+        /** tx_hung_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the i2s_tx_hung_int interrupt
+         */
+        uint32_t tx_hung_int_clr:1;
+        /** tx_sync_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the i2s_tx_sync_int interrupt
+         */
+        uint32_t tx_sync_int_clr:1;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} i2s_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of rx_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        /** rx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset receiver
+         */
+        uint32_t rx_reset:1;
+        /** rx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Rx AFIFO
+         */
+        uint32_t rx_fifo_reset:1;
+        /** rx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start receiving data
+         */
+        uint32_t rx_start:1;
+        /** rx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave receiver mode
+         */
+        uint32_t rx_slave_mod:1;
+        /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0;
+         *  0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is
+         *  0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+         */
+        uint32_t rx_stop_mode:2;
+        /** rx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable receiver  in mono mode
+         */
+        uint32_t rx_mono:1;
+        /** rx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+         */
+        uint32_t rx_big_endian:1;
+        /** rx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t rx_update:1;
+        /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S RX mono mode.   0: The second
+         *  channel data value is valid in I2S RX mono mode.
+         */
+        uint32_t rx_mono_fst_vld:1;
+        /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1;
+         *  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t rx_pcm_conf:2;
+        /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass Compress/Decompress module for received data.
+         */
+        uint32_t rx_pcm_bypass:1;
+        /** rx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable receiver in Phillips standard mode
+         */
+        uint32_t rx_msb_shift:1;
+        /** rx_done_mode : R/W; bitpos: [14]; default: 0;
+         *  1: I2S trigger rx_done when in_suc_eof is 1. 0: I2S trigger rx_done when RX FIFO is
+         *  full.
+         */
+        uint32_t rx_done_mode:1;
+        /** rx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+         */
+        uint32_t rx_left_align:1;
+        /** rx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+         */
+        uint32_t rx_24_fill_en:1;
+        /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+         *  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+         */
+        uint32_t rx_ws_idle_pol:1;
+        /** rx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
+         *  is received first.
+         */
+        uint32_t rx_bit_order:1;
+        /** rx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_tdm_en:1;
+        /** rx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Rx mode . 0: Disable.
+         */
+        uint32_t rx_pdm_en:1;
+        /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in receiver mode.
+         */
+        uint32_t rx_bck_div_num:6;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} i2s_rx_conf_reg_t;
+
+/** Type of rx_conf1 register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t rx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
+         *  the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t rx_bits_mod:5;
+        /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Rx half sample bits -1.
+         */
+        uint32_t rx_half_sample_bits:8;
+        /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Rx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t rx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_rx_conf1_reg_t;
+
+/** Type of rx_recomb_ctrl register
+ *  I2S RX configure register 1
+ */
+typedef union {
+    struct {
+        /** rx_recomb_en : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable i2s rx data recombination.
+         */
+        uint32_t rx_recomb_en:1;
+        /** rx_recomb_ext_ch_num : R/W; bitpos: [2:1]; default: 0;
+         *  The channel number that i2s will extract the data into.
+         */
+        uint32_t rx_recomb_ext_ch_num:2;
+        uint32_t reserved_3:28;
+        /** rx_recomb_update : WT; bitpos: [31]; default: 0;
+         *  Set this bit to update i2s data recombination configuration, must be performed
+         *  after changing the config of any recombined-dma-channel.
+         */
+        uint32_t rx_recomb_update:1;
+    };
+    uint32_t val;
+} i2s_rx_recomb_ctrl_reg_t;
+
+/** Type of rx_recomb_dma_ch0 register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+typedef union {
+    struct {
+        /** rx_recomb_dma_ch0_valid : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the adc-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch0_valid:1;
+        /** rx_recomb_dma_ch0_style : R/W; bitpos: [4:1]; default: 0;
+         *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+         *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+         */
+        uint32_t rx_recomb_dma_ch0_style:4;
+        /** rx_recomb_dma_ch0_order : R/W; bitpos: [12:5]; default: 0;
+         *  Set this field to set the recombined-dma-channel order. If choose to use the order
+         *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+         */
+        uint32_t rx_recomb_dma_ch0_order:8;
+        /** rx_recomb_dma_ch0_eof_num : R/W; bitpos: [28:13]; default: 0;
+         *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch0_eof_num:16;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2s_rx_recomb_dma_ch0_reg_t;
+
+/** Type of rx_recomb_dma_ch1 register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+typedef union {
+    struct {
+        /** rx_recomb_dma_ch1_valid : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the adc-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch1_valid:1;
+        /** rx_recomb_dma_ch1_style : R/W; bitpos: [4:1]; default: 0;
+         *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+         *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+         */
+        uint32_t rx_recomb_dma_ch1_style:4;
+        /** rx_recomb_dma_ch1_order : R/W; bitpos: [12:5]; default: 0;
+         *  Set this field to set the recombined-dma-channel order. If choose to use the order
+         *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+         */
+        uint32_t rx_recomb_dma_ch1_order:8;
+        /** rx_recomb_dma_ch1_eof_num : R/W; bitpos: [28:13]; default: 0;
+         *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch1_eof_num:16;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2s_rx_recomb_dma_ch1_reg_t;
+
+/** Type of rx_recomb_dma_ch2 register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+typedef union {
+    struct {
+        /** rx_recomb_dma_ch2_valid : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the adc-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch2_valid:1;
+        /** rx_recomb_dma_ch2_style : R/W; bitpos: [4:1]; default: 0;
+         *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+         *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+         */
+        uint32_t rx_recomb_dma_ch2_style:4;
+        /** rx_recomb_dma_ch2_order : R/W; bitpos: [12:5]; default: 0;
+         *  Set this field to set the recombined-dma-channel order. If choose to use the order
+         *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+         */
+        uint32_t rx_recomb_dma_ch2_order:8;
+        /** rx_recomb_dma_ch2_eof_num : R/W; bitpos: [28:13]; default: 0;
+         *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch2_eof_num:16;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2s_rx_recomb_dma_ch2_reg_t;
+
+/** Type of rx_recomb_dma_ch3 register
+ *  I2S RX recombined-dma-channel configuration register
+ */
+typedef union {
+    struct {
+        /** rx_recomb_dma_ch3_valid : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to enable the adc-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch3_valid:1;
+        /** rx_recomb_dma_ch3_style : R/W; bitpos: [4:1]; default: 0;
+         *  Set this field to set the recombined-dma-channel style. If choose to use i2s
+         *  extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
+         */
+        uint32_t rx_recomb_dma_ch3_style:4;
+        /** rx_recomb_dma_ch3_order : R/W; bitpos: [12:5]; default: 0;
+         *  Set this field to set the recombined-dma-channel order. If choose to use the order
+         *  ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
+         */
+        uint32_t rx_recomb_dma_ch3_order:8;
+        /** rx_recomb_dma_ch3_eof_num : R/W; bitpos: [28:13]; default: 0;
+         *  Set this field to set the receive eof byte length of the recombined-dma-channel.
+         */
+        uint32_t rx_recomb_dma_ch3_eof_num:16;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} i2s_rx_recomb_dma_ch3_reg_t;
+
+/** Type of rx_pdm2pcm_conf register
+ *  I2S RX configure register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable PDM2PCM RX mode. 0: DIsable.
+         */
+        uint32_t rx_pdm2pcm_en:1;
+        /** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
+         *  Configure the down sampling rate of PDM RX filter group1 module. 1: The  down
+         *  sampling rate is 128. 0: down sampling rate is 64.
+         */
+        uint32_t rx_pdm_sinc_dsr_16_en:1;
+        /** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
+         *  Configure PDM RX amplify number.
+         */
+        uint32_t rx_pdm2pcm_amplify_num:4;
+        /** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
+         *  I2S PDM RX bypass hp filter or not.
+         */
+        uint32_t rx_pdm_hp_bypass:1;
+        /** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_5:3;
+        /** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
+         *  The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
+         *  LP_I2S_RX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t rx_iir_hp_mult12_0:3;
+    };
+    uint32_t val;
+} i2s_rx_pdm2pcm_conf_reg_t;
+
+/** Type of rx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan0_en:1;
+        /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan1_en:1;
+        /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan2_en:1;
+        /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan3_en:1;
+        /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan4_en:1;
+        /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan5_en:1;
+        /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan6_en:1;
+        /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0:  Disable, just
+         *  input 0 in this channel.
+         */
+        uint32_t rx_tdm_pdm_chan7_en:1;
+        /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan8_en:1;
+        /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan9_en:1;
+        /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan10_en:1;
+        /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan11_en:1;
+        /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan12_en:1;
+        /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan13_en:1;
+        /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan14_en:1;
+        /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data input of I2S RX TDM channel $n. 0:  Disable, just input 0
+         *  in this channel.
+         */
+        uint32_t rx_tdm_chan15_en:1;
+        /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t rx_tdm_tot_chan_num:4;
+        /** rx_tdm_bits_mode_det_en : R/W; bitpos: [20]; default: 0;
+         *  1: Auto detect bit mode in tdm slave mode. 0: Disable.
+         */
+        uint32_t rx_tdm_bits_mode_det_en:1;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} i2s_rx_tdm_ctrl_reg_t;
+
+/** Type of rxeof_num register
+ *  I2S RX data number control register.
+ */
+typedef union {
+    struct {
+        /** rx_eof_num : R/W; bitpos: [15:0]; default: 64;
+         *  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[15:0])
+         *  . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+         */
+        uint32_t rx_eof_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} i2s_rxeof_num_reg_t;
+
+
+/** Group: TX Control and configuration registers */
+/** Type of tx_conf register
+ *  I2S TX configure register
+ */
+typedef union {
+    struct {
+        /** tx_reset : WT; bitpos: [0]; default: 0;
+         *  Set this bit to reset transmitter
+         */
+        uint32_t tx_reset:1;
+        /** tx_fifo_reset : WT; bitpos: [1]; default: 0;
+         *  Set this bit to reset Tx AFIFO
+         */
+        uint32_t tx_fifo_reset:1;
+        /** tx_start : R/W/SC; bitpos: [2]; default: 0;
+         *  Set this bit to start transmitting data
+         */
+        uint32_t tx_start:1;
+        /** tx_slave_mod : R/W; bitpos: [3]; default: 0;
+         *  Set this bit to enable slave transmitter mode
+         */
+        uint32_t tx_slave_mod:1;
+        /** tx_stop_en : R/W; bitpos: [4]; default: 1;
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
+         */
+        uint32_t tx_stop_en:1;
+        /** tx_chan_equal : R/W; bitpos: [5]; default: 0;
+         *  1: The value of Left channel data is equal to the value of right channel data in
+         *  I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+         *  reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+         */
+        uint32_t tx_chan_equal:1;
+        /** tx_mono : R/W; bitpos: [6]; default: 0;
+         *  Set this bit to enable transmitter in mono mode
+         */
+        uint32_t tx_mono:1;
+        /** tx_big_endian : R/W; bitpos: [7]; default: 0;
+         *  I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr
+         *  value.
+         */
+        uint32_t tx_big_endian:1;
+        /** tx_update : R/W/SC; bitpos: [8]; default: 0;
+         *  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
+         *  bit will be cleared by hardware after update register done.
+         */
+        uint32_t tx_update:1;
+        /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1;
+         *  1: The first channel data value is valid in I2S TX mono mode.   0: The second
+         *  channel data value is valid in I2S TX mono mode.
+         */
+        uint32_t tx_mono_fst_vld:1;
+        /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0;
+         *  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+         *  (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+         */
+        uint32_t tx_pcm_conf:2;
+        /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1;
+         *  Set this bit to bypass  Compress/Decompress module for transmitted data.
+         */
+        uint32_t tx_pcm_bypass:1;
+        /** tx_msb_shift : R/W; bitpos: [13]; default: 1;
+         *  Set this bit to enable transmitter in Phillips standard mode
+         */
+        uint32_t tx_msb_shift:1;
+        /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1;
+         *  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to
+         *  generate pos/neg edge in master mode.
+         */
+        uint32_t tx_bck_no_dly:1;
+        /** tx_left_align : R/W; bitpos: [15]; default: 1;
+         *  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+         */
+        uint32_t tx_left_align:1;
+        /** tx_24_fill_en : R/W; bitpos: [16]; default: 0;
+         *  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+         */
+        uint32_t tx_24_fill_en:1;
+        /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0;
+         *  0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1:
+         *  WS should be 1 when sending left channel data, and WS is 0in right channel.
+         */
+        uint32_t tx_ws_idle_pol:1;
+        /** tx_bit_order : R/W; bitpos: [18]; default: 0;
+         *  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
+         *  sent first.
+         */
+        uint32_t tx_bit_order:1;
+        /** tx_tdm_en : R/W; bitpos: [19]; default: 0;
+         *  1: Enable I2S TDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_tdm_en:1;
+        /** tx_pdm_en : R/W; bitpos: [20]; default: 0;
+         *  1: Enable I2S PDM Tx mode . 0: Disable.
+         */
+        uint32_t tx_pdm_en:1;
+        /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6;
+         *  Bit clock configuration bits in transmitter mode.
+         */
+        uint32_t tx_bck_div_num:6;
+        /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0;
+         *  I2S transmitter channel mode configuration bits.
+         */
+        uint32_t tx_chan_mod:3;
+        /** sig_loopback : R/W; bitpos: [30]; default: 0;
+         *  Enable signal loop back mode with transmitter module and receiver module sharing
+         *  the same WS and BCK signals.
+         */
+        uint32_t sig_loopback:1;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_tx_conf_reg_t;
+
+/** Type of tx_conf1 register
+ *  I2S TX configure register 1
+ */
+typedef union {
+    struct {
+        /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0;
+         *  The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) *
+         *  T_bck
+         */
+        uint32_t tx_tdm_ws_width:9;
+        uint32_t reserved_9:5;
+        /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15;
+         *  Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
+         *  all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in
+         *  16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid
+         *  channel data is in 32-bit-mode.
+         */
+        uint32_t tx_bits_mod:5;
+        /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15;
+         *  I2S Tx half sample bits -1.
+         */
+        uint32_t tx_half_sample_bits:8;
+        /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15;
+         *  The Tx bit number for each channel minus 1in TDM mode.
+         */
+        uint32_t tx_tdm_chan_bits:5;
+    };
+    uint32_t val;
+} i2s_tx_conf1_reg_t;
+
+/** Type of tx_pcm2pdm_conf register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2;
+         *  I2S TX PDM OSR2 value
+         */
+        uint32_t tx_pdm_sinc_osr2:4;
+        /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0;
+         *  I2S TX PDM prescale for sigmadelta
+         */
+        uint32_t tx_pdm_prescale:8;
+        /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_hp_in_shift:2;
+        /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_lp_in_shift:2;
+        /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sinc_in_shift:2;
+        /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1;
+         *  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+         */
+        uint32_t tx_pdm_sigmadelta_in_shift:2;
+        /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0;
+         *  I2S TX PDM sigmadelta dither2 value
+         */
+        uint32_t tx_pdm_sigmadelta_dither2:1;
+        /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1;
+         *  I2S TX PDM sigmadelta dither value
+         */
+        uint32_t tx_pdm_sigmadelta_dither:1;
+        /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0;
+         *  I2S TX PDM dac mode enable
+         */
+        uint32_t tx_pdm_dac_2out_en:1;
+        /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0;
+         *  I2S TX PDM dac 2channel enable
+         */
+        uint32_t tx_pdm_dac_mode_en:1;
+        /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0;
+         *  I2S TX PDM Converter enable
+         */
+        uint32_t pcm2pdm_conv_en:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf_reg_t;
+
+/** Type of tx_pcm2pdm_conf1 register
+ *  I2S TX PCM2PDM configuration register
+ */
+typedef union {
+    struct {
+        /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960;
+         *  I2S TX PDM Fp
+         */
+        uint32_t tx_pdm_fp:10;
+        /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480;
+         *  I2S TX PDM Fs
+         */
+        uint32_t tx_pdm_fs:10;
+        /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_5[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_5:3;
+        /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7;
+         *  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+         *  I2S_TX_IIR_HP_MULT12_0[2:0])
+         */
+        uint32_t tx_iir_hp_mult12_0:3;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} i2s_tx_pcm2pdm_conf1_reg_t;
+
+/** Type of tx_tdm_ctrl register
+ *  I2S TX TDM mode control register
+ */
+typedef union {
+    struct {
+        /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan0_en:1;
+        /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan1_en:1;
+        /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan2_en:1;
+        /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan3_en:1;
+        /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan4_en:1;
+        /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan5_en:1;
+        /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan6_en:1;
+        /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan7_en:1;
+        /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan8_en:1;
+        /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan9_en:1;
+        /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan10_en:1;
+        /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan11_en:1;
+        /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan12_en:1;
+        /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan13_en:1;
+        /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan14_en:1;
+        /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1;
+         *  1: Enable the valid data output of I2S TX TDM channel $n. 0:  Disable, just output
+         *  0 in this channel.
+         */
+        uint32_t tx_tdm_chan15_en:1;
+        /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0;
+         *  The total channel number of I2S TX TDM mode.
+         */
+        uint32_t tx_tdm_tot_chan_num:4;
+        /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0;
+         *  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and
+         *  only the data of the enabled channels is sent, then this bit should be set. Clear
+         *  it when all the data stored in DMA TX buffer is for enabled channels.
+         */
+        uint32_t tx_tdm_skip_msk_en:1;
+        /** tx_tdm_bits_mode_det_en : R/W; bitpos: [21]; default: 0;
+         *  1: Auto detect bit mode in tdm slave mode. 0: Disable.
+         */
+        uint32_t tx_tdm_bits_mode_det_en:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} i2s_tx_tdm_ctrl_reg_t;
+
+
+/** Group: RX clock and timing registers */
+/** Type of rx_timing register
+ *  I2S RX timing control register
+ */
+typedef union {
+    struct {
+        /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd_in_dm:2;
+        uint32_t reserved_2:2;
+        /** rx_sd1_in_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd1_in_dm:2;
+        uint32_t reserved_6:2;
+        /** rx_sd2_in_dm : R/W; bitpos: [9:8]; default: 0;
+         *  The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd2_in_dm:2;
+        uint32_t reserved_10:2;
+        /** rx_sd3_in_dm : R/W; bitpos: [13:12]; default: 0;
+         *  The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_sd3_in_dm:2;
+        uint32_t reserved_14:2;
+        /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t rx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_rx_timing_reg_t;
+
+
+/** Group: TX clock and timing registers */
+/** Type of tx_timing register
+ *  I2S TX timing control register
+ */
+typedef union {
+    struct {
+        /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0;
+         *  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd_out_dm:2;
+        uint32_t reserved_2:2;
+        /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0;
+         *  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_sd1_out_dm:2;
+        uint32_t reserved_6:10;
+        /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0;
+         *  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_out_dm:2;
+        uint32_t reserved_18:2;
+        /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0;
+         *  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_out_dm:2;
+        uint32_t reserved_22:2;
+        /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0;
+         *  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_ws_in_dm:2;
+        uint32_t reserved_26:2;
+        /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0;
+         *  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2:
+         *  delay by neg edge. 3: not used.
+         */
+        uint32_t tx_bck_in_dm:2;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} i2s_tx_timing_reg_t;
+
+
+/** Group: Control and configuration registers */
+/** Type of lc_hung_conf register
+ *  I2S HUNG configure register.
+ */
+typedef union {
+    struct {
+        /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16;
+         *  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+         *  when fifo hung counter is equal to this value
+         */
+        uint32_t lc_fifo_timeout:8;
+        /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0;
+         *  The bits are used to scale tick counter threshold. The tick counter is reset when
+         *  counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+         */
+        uint32_t lc_fifo_timeout_shift:3;
+        /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1;
+         *  The enable bit for FIFO timeout
+         */
+        uint32_t lc_fifo_timeout_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} i2s_lc_hung_conf_reg_t;
+
+/** Type of conf_sigle_data register
+ *  I2S signal data register
+ */
+typedef union {
+    struct {
+        /** single_data : R/W; bitpos: [31:0]; default: 0;
+         *  The configured constant channel data to be sent out.
+         */
+        uint32_t single_data:32;
+    };
+    uint32_t val;
+} i2s_conf_sigle_data_reg_t;
+
+/** Type of destination register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** rx_destination : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to configure the data destination of i2s rx. 1: ble. 0: gdma.
+         */
+        uint32_t rx_destination:1;
+        /** tx_destination : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to configure the data destination of i2s tx. 1: ble. 0: gdma.
+         */
+        uint32_t tx_destination:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} i2s_destination_reg_t;
+
+
+/** Group: TX status registers */
+/** Type of state register
+ *  I2S TX status register
+ */
+typedef union {
+    struct {
+        /** tx_idle : RO; bitpos: [0]; default: 1;
+         *  1: i2s_tx is idle state. 0: i2s_tx is working.
+         */
+        uint32_t tx_idle:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_state_reg_t;
+
+
+/** Group: ETM registers */
+/** Type of etm_conf register
+ *  I2S ETM configure register
+ */
+typedef union {
+    struct {
+        /** etm_tx_send_word_num : R/W; bitpos: [13:0]; default: 64;
+         *  I2S ETM send x words event. When sending word number of
+         *  reg_etm_tx_send_word_num[13:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_tx_send_word_num:14;
+        /** etm_rx_receive_word_num : R/W; bitpos: [27:14]; default: 64;
+         *  I2S ETM receive x words event. When receiving word number of
+         *  reg_etm_rx_receive_word_num[13:0], i2s will trigger an etm event.
+         */
+        uint32_t etm_rx_receive_word_num:14;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_etm_conf_reg_t;
+
+
+/** Group: TX sync function registers */
+/** Type of ideal_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_ideal_cnt : R/W; bitpos: [30:0]; default: 0;
+         *  tx fifo counter ideal value.
+         */
+        uint32_t tx_ideal_cnt:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_ideal_cnt_reg_t;
+
+/** Type of fifo_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_fifo_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx fifo counter value.
+         */
+        uint32_t tx_fifo_cnt:31;
+        /** tx_fifo_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx fifo counter.
+         */
+        uint32_t tx_fifo_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_fifo_cnt_reg_t;
+
+/** Type of bck_cnt register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_bck_cnt : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_bck_cnt:31;
+        /** tx_bck_cnt_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset tx bck counter.
+         */
+        uint32_t tx_bck_cnt_rst:1;
+    };
+    uint32_t val;
+} i2s_bck_cnt_reg_t;
+
+/** Type of cnt_diff register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_cnt_diff : RO; bitpos: [30:0]; default: 0;
+         *  tx bck counter value.
+         */
+        uint32_t tx_cnt_diff:31;
+        /** tx_cnt_diff_rst : WT; bitpos: [31]; default: 0;
+         *  Set this bit to reset fifo counter difference.
+         */
+        uint32_t tx_cnt_diff_rst:1;
+    };
+    uint32_t val;
+} i2s_cnt_diff_reg_t;
+
+/** Type of sync_sw_thres register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_cnt_diff_sw_thres : R/W; bitpos: [30:0]; default: 0;
+         *  tx fifo counter difference software threshold value, when difference larger than
+         *  this threshold, interrupt will occur and hardware sync will not be executed.
+         */
+        uint32_t tx_cnt_diff_sw_thres:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_sync_sw_thres_reg_t;
+
+/** Type of sync_hw_thres register
+ *  I2S sync counter register
+ */
+typedef union {
+    struct {
+        /** tx_cnt_diff_hw_thres : R/W; bitpos: [30:0]; default: 0;
+         *  tx fifo counter difference hardware threshold value, which means that only when
+         *  difference larger than this threshold will hardware start hardware sync.
+         */
+        uint32_t tx_cnt_diff_hw_thres:31;
+        uint32_t reserved_31:1;
+    };
+    uint32_t val;
+} i2s_sync_hw_thres_reg_t;
+
+/** Type of hw_sync_conf register
+ *  I2S TX hardware sync function configuration register
+ */
+typedef union {
+    struct {
+        /** tx_hw_sync_en : R/W; bitpos: [0]; default: 0;
+         *  Configure whether enable i2s tx hardware sync function. 1: Enable. 0: Disable
+         */
+        uint32_t tx_hw_sync_en:1;
+        /** tx_hw_sync_suppl_mode : R/W; bitpos: [1]; default: 0;
+         *  Configure the i2s tx hardware sync supplementation mode. 1: Supplement the data
+         *  configured in I2S_TX_HW_SYNC_SUPPL_DATA[31:0]. 0: Supplement the last data.
+         */
+        uint32_t tx_hw_sync_suppl_mode:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} i2s_hw_sync_conf_reg_t;
+
+/** Type of hw_sync_data register
+ *  I2S TX hardware sync function configuration register
+ */
+typedef union {
+    struct {
+        /** tx_hw_sync_suppl_data : R/W; bitpos: [31:0]; default: 0;
+         *  Configure the i2s tx hardware sync supplementation data when
+         *  I2S_TX_HW_SYNC_SUPPL_MODE is 1.
+         */
+        uint32_t tx_hw_sync_suppl_data:32;
+    };
+    uint32_t val;
+} i2s_hw_sync_data_reg_t;
+
+
+/** Group: Clock registers */
+/** Type of clk_gate register
+ *  Clock gate register
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  set this bit to enable clock gate
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} i2s_clk_gate_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 38813744;
+         *  I2S version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} i2s_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile i2s_int_raw_reg_t int_raw;
+    volatile i2s_int_st_reg_t int_st;
+    volatile i2s_int_ena_reg_t int_ena;
+    volatile i2s_int_clr_reg_t int_clr;
+    uint32_t reserved_01c;
+    volatile i2s_rx_conf_reg_t rx_conf;
+    volatile i2s_tx_conf_reg_t tx_conf;
+    volatile i2s_rx_conf1_reg_t rx_conf1;
+    volatile i2s_tx_conf1_reg_t tx_conf1;
+    volatile i2s_rx_recomb_ctrl_reg_t rx_recomb_ctrl;
+    volatile i2s_rx_recomb_dma_ch0_reg_t rx_recomb_dma_ch0;
+    volatile i2s_rx_recomb_dma_ch1_reg_t rx_recomb_dma_ch1;
+    volatile i2s_rx_recomb_dma_ch2_reg_t rx_recomb_dma_ch2;
+    volatile i2s_rx_recomb_dma_ch3_reg_t rx_recomb_dma_ch3;
+    volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
+    volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
+    volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
+    volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
+    volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
+    volatile i2s_rx_timing_reg_t rx_timing;
+    volatile i2s_tx_timing_reg_t tx_timing;
+    volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
+    volatile i2s_rxeof_num_reg_t rxeof_num;
+    volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
+    volatile i2s_state_reg_t state;
+    volatile i2s_etm_conf_reg_t etm_conf;
+    volatile i2s_ideal_cnt_reg_t ideal_cnt;
+    volatile i2s_fifo_cnt_reg_t fifo_cnt;
+    volatile i2s_bck_cnt_reg_t bck_cnt;
+    volatile i2s_cnt_diff_reg_t cnt_diff;
+    volatile i2s_sync_sw_thres_reg_t sync_sw_thres;
+    volatile i2s_sync_hw_thres_reg_t sync_hw_thres;
+    volatile i2s_hw_sync_conf_reg_t hw_sync_conf;
+    volatile i2s_hw_sync_data_reg_t hw_sync_data;
+    uint32_t reserved_094[24];
+    volatile i2s_destination_reg_t destination;
+    volatile i2s_clk_gate_reg_t clk_gate;
+    volatile i2s_date_reg_t date;
+} i2s_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(i2s_dev_t) == 0x100, "Invalid size of i2s_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/icm_sys_axi_ic_reg.h b/components/soc/esp32s31/register/soc/icm_sys_axi_ic_reg.h
new file mode 100644
index 00000000000..c5deb9dfbc0
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/icm_sys_axi_ic_reg.h
@@ -0,0 +1,2790 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** AXI_IC_DATE_REG register
+ *  Version Control Register
+ */
+#define AXI_IC_DATE_REG (DR_REG_AXI_IC_BASE + 0x0)
+/** AXI_IC_REG_DATE : R/W; bitpos: [31:0]; default: 23050900;
+ *  Version Control Register
+ */
+#define AXI_IC_REG_DATE    0xFFFFFFFFU
+#define AXI_IC_REG_DATE_M  (AXI_IC_REG_DATE_V << AXI_IC_REG_DATE_S)
+#define AXI_IC_REG_DATE_V  0xFFFFFFFFU
+#define AXI_IC_REG_DATE_S  0
+
+/** AXI_IC_CLK_EN_REG register
+ *  AXI IC reg clk enable config register
+ */
+#define AXI_IC_CLK_EN_REG (DR_REG_AXI_IC_BASE + 0x4)
+/** AXI_IC_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  value 1 enable clk, value 0 disable clk, default 1
+ */
+#define AXI_IC_REG_CLK_EN    (BIT(0))
+#define AXI_IC_REG_CLK_EN_M  (AXI_IC_REG_CLK_EN_V << AXI_IC_REG_CLK_EN_S)
+#define AXI_IC_REG_CLK_EN_V  0x00000001U
+#define AXI_IC_REG_CLK_EN_S  0
+
+/** AXI_IC_INTERRUPT_RAW_REG register
+ *  Interrupt raw of AXI IC  Interrupt register.
+ */
+#define AXI_IC_INTERRUPT_RAW_REG (DR_REG_AXI_IC_BASE + 0x8)
+/** AXI_IC_REG_DEC_FAILURE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
+ *  Interrupt raw of reg_dec_failure_int_raw
+ */
+#define AXI_IC_REG_DEC_FAILURE_INT_RAW    (BIT(0))
+#define AXI_IC_REG_DEC_FAILURE_INT_RAW_M  (AXI_IC_REG_DEC_FAILURE_INT_RAW_V << AXI_IC_REG_DEC_FAILURE_INT_RAW_S)
+#define AXI_IC_REG_DEC_FAILURE_INT_RAW_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_INT_RAW_S  0
+/** AXI_IC_REG_TIMEOUT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
+ *  Interrupt raw of reg_timeout_int_raw
+ */
+#define AXI_IC_REG_TIMEOUT_INT_RAW    (BIT(1))
+#define AXI_IC_REG_TIMEOUT_INT_RAW_M  (AXI_IC_REG_TIMEOUT_INT_RAW_V << AXI_IC_REG_TIMEOUT_INT_RAW_S)
+#define AXI_IC_REG_TIMEOUT_INT_RAW_V  0x00000001U
+#define AXI_IC_REG_TIMEOUT_INT_RAW_S  1
+
+/** AXI_IC_INTERRUPT_CLR_REG register
+ *  Interrupt clear of AXI IC  Interrupt register.
+ */
+#define AXI_IC_INTERRUPT_CLR_REG (DR_REG_AXI_IC_BASE + 0xc)
+/** AXI_IC_REG_DEC_FAILURE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Interrupt clr of reg_dec_failure_int_clr
+ */
+#define AXI_IC_REG_DEC_FAILURE_INT_CLR    (BIT(0))
+#define AXI_IC_REG_DEC_FAILURE_INT_CLR_M  (AXI_IC_REG_DEC_FAILURE_INT_CLR_V << AXI_IC_REG_DEC_FAILURE_INT_CLR_S)
+#define AXI_IC_REG_DEC_FAILURE_INT_CLR_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_INT_CLR_S  0
+/** AXI_IC_REG_TIMEOUT_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Interrupt clr of reg_timeout_int_clr
+ */
+#define AXI_IC_REG_TIMEOUT_INT_CLR    (BIT(1))
+#define AXI_IC_REG_TIMEOUT_INT_CLR_M  (AXI_IC_REG_TIMEOUT_INT_CLR_V << AXI_IC_REG_TIMEOUT_INT_CLR_S)
+#define AXI_IC_REG_TIMEOUT_INT_CLR_V  0x00000001U
+#define AXI_IC_REG_TIMEOUT_INT_CLR_S  1
+
+/** AXI_IC_INTERRUPT_ENA_REG register
+ *  Interrupt enable of AXI IC  Interrupt register.
+ */
+#define AXI_IC_INTERRUPT_ENA_REG (DR_REG_AXI_IC_BASE + 0x10)
+/** AXI_IC_REG_DEC_FAILURE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Interrupt ena of reg_dec_failure_int_ena
+ */
+#define AXI_IC_REG_DEC_FAILURE_INT_ENA    (BIT(0))
+#define AXI_IC_REG_DEC_FAILURE_INT_ENA_M  (AXI_IC_REG_DEC_FAILURE_INT_ENA_V << AXI_IC_REG_DEC_FAILURE_INT_ENA_S)
+#define AXI_IC_REG_DEC_FAILURE_INT_ENA_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_INT_ENA_S  0
+/** AXI_IC_REG_TIMEOUT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Interrupt ena of reg_timeout_int_ena
+ */
+#define AXI_IC_REG_TIMEOUT_INT_ENA    (BIT(1))
+#define AXI_IC_REG_TIMEOUT_INT_ENA_M  (AXI_IC_REG_TIMEOUT_INT_ENA_V << AXI_IC_REG_TIMEOUT_INT_ENA_S)
+#define AXI_IC_REG_TIMEOUT_INT_ENA_V  0x00000001U
+#define AXI_IC_REG_TIMEOUT_INT_ENA_S  1
+
+/** AXI_IC_INTERRUPT_ST_REG register
+ *  AXI IC  Interrupt register.
+ */
+#define AXI_IC_INTERRUPT_ST_REG (DR_REG_AXI_IC_BASE + 0x14)
+/** AXI_IC_REG_DEC_FAILURE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Interrupt st of reg_dec_failure_int_st
+ */
+#define AXI_IC_REG_DEC_FAILURE_INT_ST    (BIT(0))
+#define AXI_IC_REG_DEC_FAILURE_INT_ST_M  (AXI_IC_REG_DEC_FAILURE_INT_ST_V << AXI_IC_REG_DEC_FAILURE_INT_ST_S)
+#define AXI_IC_REG_DEC_FAILURE_INT_ST_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_INT_ST_S  0
+/** AXI_IC_REG_TIMEOUT_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Interrupt st of reg_timeout_int_st
+ */
+#define AXI_IC_REG_TIMEOUT_INT_ST    (BIT(1))
+#define AXI_IC_REG_TIMEOUT_INT_ST_M  (AXI_IC_REG_TIMEOUT_INT_ST_V << AXI_IC_REG_TIMEOUT_INT_ST_S)
+#define AXI_IC_REG_TIMEOUT_INT_ST_V  0x00000001U
+#define AXI_IC_REG_TIMEOUT_INT_ST_S  1
+
+/** AXI_IC_TIMEOUT_MAX_CNT_REG register
+ *  AXI IC core AW or AR channel timeout counter maximum value.
+ */
+#define AXI_IC_TIMEOUT_MAX_CNT_REG (DR_REG_AXI_IC_BASE + 0x18)
+/** AXI_IC_REG_TIMEOUT_MAX_CNT : R/W; bitpos: [31:0]; default: 4294967295;
+ *  AXI IC core AW or AR channel timeout counter maximum value.
+ */
+#define AXI_IC_REG_TIMEOUT_MAX_CNT    0xFFFFFFFFU
+#define AXI_IC_REG_TIMEOUT_MAX_CNT_M  (AXI_IC_REG_TIMEOUT_MAX_CNT_V << AXI_IC_REG_TIMEOUT_MAX_CNT_S)
+#define AXI_IC_REG_TIMEOUT_MAX_CNT_V  0xFFFFFFFFU
+#define AXI_IC_REG_TIMEOUT_MAX_CNT_S  0
+
+/** AXI_IC_TIMEOUT_INFO_REG register
+ *  AXI IC core AW or AR channel timeout information.
+ */
+#define AXI_IC_TIMEOUT_INFO_REG (DR_REG_AXI_IC_BASE + 0x1c)
+/** AXI_IC_REG_TIMEOUT_SLAVE : RO; bitpos: [2:0]; default: 0;
+ *  bit[i] is 1 means slave[i] occurs timeout.
+ */
+#define AXI_IC_REG_TIMEOUT_SLAVE    0x00000007U
+#define AXI_IC_REG_TIMEOUT_SLAVE_M  (AXI_IC_REG_TIMEOUT_SLAVE_V << AXI_IC_REG_TIMEOUT_SLAVE_S)
+#define AXI_IC_REG_TIMEOUT_SLAVE_V  0x00000007U
+#define AXI_IC_REG_TIMEOUT_SLAVE_S  0
+/** AXI_IC_REG_TIMEOUT_ID : RO; bitpos: [9:3]; default: 0;
+ *  (master id, awid)
+ */
+#define AXI_IC_REG_TIMEOUT_ID    0x0000007FU
+#define AXI_IC_REG_TIMEOUT_ID_M  (AXI_IC_REG_TIMEOUT_ID_V << AXI_IC_REG_TIMEOUT_ID_S)
+#define AXI_IC_REG_TIMEOUT_ID_V  0x0000007FU
+#define AXI_IC_REG_TIMEOUT_ID_S  3
+/** AXI_IC_REG_TIMEOUT_WR : RO; bitpos: [10]; default: 0;
+ *  1 indicates write operation, 0 indicates read operation.
+ */
+#define AXI_IC_REG_TIMEOUT_WR    (BIT(10))
+#define AXI_IC_REG_TIMEOUT_WR_M  (AXI_IC_REG_TIMEOUT_WR_V << AXI_IC_REG_TIMEOUT_WR_S)
+#define AXI_IC_REG_TIMEOUT_WR_V  0x00000001U
+#define AXI_IC_REG_TIMEOUT_WR_S  10
+
+/** AXI_IC_DEC_FAILURE_INFO_REG register
+ *  Default slave information get control and status.
+ */
+#define AXI_IC_DEC_FAILURE_INFO_REG (DR_REG_AXI_IC_BASE + 0x20)
+/** AXI_IC_REG_DEC_FAILURE_READ_FIRST : R/W; bitpos: [0]; default: 0;
+ *  Decoder failure recorded control. 1 means record read failure first, else write
+ *  failure first.
+ */
+#define AXI_IC_REG_DEC_FAILURE_READ_FIRST    (BIT(0))
+#define AXI_IC_REG_DEC_FAILURE_READ_FIRST_M  (AXI_IC_REG_DEC_FAILURE_READ_FIRST_V << AXI_IC_REG_DEC_FAILURE_READ_FIRST_S)
+#define AXI_IC_REG_DEC_FAILURE_READ_FIRST_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_READ_FIRST_S  0
+/** AXI_IC_REG_DEC_FAILURE_VALID : RO; bitpos: [1]; default: 0;
+ *  Decoder failure valid control.
+ */
+#define AXI_IC_REG_DEC_FAILURE_VALID    (BIT(1))
+#define AXI_IC_REG_DEC_FAILURE_VALID_M  (AXI_IC_REG_DEC_FAILURE_VALID_V << AXI_IC_REG_DEC_FAILURE_VALID_S)
+#define AXI_IC_REG_DEC_FAILURE_VALID_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_VALID_S  1
+/** AXI_IC_REG_DEC_FAILURE_TYPE : RO; bitpos: [2]; default: 0;
+ *  Decoder failure type control. 0 means ar failure, 1 means aw failure.
+ */
+#define AXI_IC_REG_DEC_FAILURE_TYPE    (BIT(2))
+#define AXI_IC_REG_DEC_FAILURE_TYPE_M  (AXI_IC_REG_DEC_FAILURE_TYPE_V << AXI_IC_REG_DEC_FAILURE_TYPE_S)
+#define AXI_IC_REG_DEC_FAILURE_TYPE_V  0x00000001U
+#define AXI_IC_REG_DEC_FAILURE_TYPE_S  2
+/** AXI_IC_REG_DEC_FAILURE_CAUSE : RO; bitpos: [5:3]; default: 0;
+ *  bit[0] is 0 means to access the mapped slave address, and is 1 means to access the
+ *  unmapped slave address. bit[1] is 0 means to access the visible slave, and is 1
+ *  means to access the invisible slave. bit[2] is 0 means to access the secure slave,
+ *  and is 1 means to access the non-secure slave.
+ */
+#define AXI_IC_REG_DEC_FAILURE_CAUSE    0x00000007U
+#define AXI_IC_REG_DEC_FAILURE_CAUSE_M  (AXI_IC_REG_DEC_FAILURE_CAUSE_V << AXI_IC_REG_DEC_FAILURE_CAUSE_S)
+#define AXI_IC_REG_DEC_FAILURE_CAUSE_V  0x00000007U
+#define AXI_IC_REG_DEC_FAILURE_CAUSE_S  3
+/** AXI_IC_REG_DEC_FAILURE_MST_ID : RO; bitpos: [12:6]; default: 0;
+ *  (master id, awid/arid)
+ */
+#define AXI_IC_REG_DEC_FAILURE_MST_ID    0x0000007FU
+#define AXI_IC_REG_DEC_FAILURE_MST_ID_M  (AXI_IC_REG_DEC_FAILURE_MST_ID_V << AXI_IC_REG_DEC_FAILURE_MST_ID_S)
+#define AXI_IC_REG_DEC_FAILURE_MST_ID_V  0x0000007FU
+#define AXI_IC_REG_DEC_FAILURE_MST_ID_S  6
+
+/** AXI_IC_QOS_DEBUG_MST_SEL_REG register
+ *  Config the select for debug master.
+ */
+#define AXI_IC_QOS_DEBUG_MST_SEL_REG (DR_REG_AXI_IC_BASE + 0x24)
+/** AXI_IC_REG_QOS_DEBUG_MST_SEL : R/W; bitpos: [3:0]; default: 0;
+ *  select which master will be debug.
+ */
+#define AXI_IC_REG_QOS_DEBUG_MST_SEL    0x0000000FU
+#define AXI_IC_REG_QOS_DEBUG_MST_SEL_M  (AXI_IC_REG_QOS_DEBUG_MST_SEL_V << AXI_IC_REG_QOS_DEBUG_MST_SEL_S)
+#define AXI_IC_REG_QOS_DEBUG_MST_SEL_V  0x0000000FU
+#define AXI_IC_REG_QOS_DEBUG_MST_SEL_S  0
+
+/** AXI_IC_DEC_FAILURE_ADDR_REG register
+ *  Record the address for AXI Master access Default slave.
+ */
+#define AXI_IC_DEC_FAILURE_ADDR_REG (DR_REG_AXI_IC_BASE + 0x80)
+/** AXI_IC_REG_DEC_FAILURE_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  AXI IC core AW or AR channel decoder failure address.
+ */
+#define AXI_IC_REG_DEC_FAILURE_ADDR    0xFFFFFFFFU
+#define AXI_IC_REG_DEC_FAILURE_ADDR_M  (AXI_IC_REG_DEC_FAILURE_ADDR_V << AXI_IC_REG_DEC_FAILURE_ADDR_S)
+#define AXI_IC_REG_DEC_FAILURE_ADDR_V  0xFFFFFFFFU
+#define AXI_IC_REG_DEC_FAILURE_ADDR_S  0
+
+/** AXI_IC_REG_SLAVE_IS_SECURE_REG register
+ *  AXI IC core slave security control.
+ */
+#define AXI_IC_REG_SLAVE_IS_SECURE_REG (DR_REG_AXI_IC_BASE + 0x84)
+/** AXI_IC_REG_SLAVE_IS_SECURE_0 : R/W; bitpos: [0]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_SLAVE_IS_SECURE_0    (BIT(0))
+#define AXI_IC_REG_SLAVE_IS_SECURE_0_M  (AXI_IC_REG_SLAVE_IS_SECURE_0_V << AXI_IC_REG_SLAVE_IS_SECURE_0_S)
+#define AXI_IC_REG_SLAVE_IS_SECURE_0_V  0x00000001U
+#define AXI_IC_REG_SLAVE_IS_SECURE_0_S  0
+/** AXI_IC_REG_SLAVE_IS_SECURE_1 : R/W; bitpos: [1]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_SLAVE_IS_SECURE_1    (BIT(1))
+#define AXI_IC_REG_SLAVE_IS_SECURE_1_M  (AXI_IC_REG_SLAVE_IS_SECURE_1_V << AXI_IC_REG_SLAVE_IS_SECURE_1_S)
+#define AXI_IC_REG_SLAVE_IS_SECURE_1_V  0x00000001U
+#define AXI_IC_REG_SLAVE_IS_SECURE_1_S  1
+/** AXI_IC_REG_SLAVE_IS_SECURE_2 : R/W; bitpos: [2]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_SLAVE_IS_SECURE_2    (BIT(2))
+#define AXI_IC_REG_SLAVE_IS_SECURE_2_M  (AXI_IC_REG_SLAVE_IS_SECURE_2_V << AXI_IC_REG_SLAVE_IS_SECURE_2_S)
+#define AXI_IC_REG_SLAVE_IS_SECURE_2_V  0x00000001U
+#define AXI_IC_REG_SLAVE_IS_SECURE_2_S  2
+
+/** AXI_IC_SLAVE_SECURITY_OVERRIDE_REG register
+ *  The control signal whether slave security is overridden by software.
+ */
+#define AXI_IC_SLAVE_SECURITY_OVERRIDE_REG (DR_REG_AXI_IC_BASE + 0x88)
+/** AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0 : R/W; bitpos: [0]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0    (BIT(0))
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0_M  (AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0_V << AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0_S)
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0_V  0x00000001U
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_0_S  0
+/** AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1 : R/W; bitpos: [1]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1    (BIT(1))
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1_M  (AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1_V << AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1_S)
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1_V  0x00000001U
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_1_S  1
+/** AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2 : R/W; bitpos: [2]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2    (BIT(2))
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2_M  (AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2_V << AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2_S)
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2_V  0x00000001U
+#define AXI_IC_REG_SLAVE_SECURITY_OVERRIDE_2_S  2
+
+/** AXI_IC_MASTER_IS_SECURE_REG register
+ *  AXI IC core master security control.
+ */
+#define AXI_IC_MASTER_IS_SECURE_REG (DR_REG_AXI_IC_BASE + 0x8c)
+/** AXI_IC_REG_MASTER_IS_SECURE_0 : R/W; bitpos: [0]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_0    (BIT(0))
+#define AXI_IC_REG_MASTER_IS_SECURE_0_M  (AXI_IC_REG_MASTER_IS_SECURE_0_V << AXI_IC_REG_MASTER_IS_SECURE_0_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_0_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_0_S  0
+/** AXI_IC_REG_MASTER_IS_SECURE_1 : R/W; bitpos: [1]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_1    (BIT(1))
+#define AXI_IC_REG_MASTER_IS_SECURE_1_M  (AXI_IC_REG_MASTER_IS_SECURE_1_V << AXI_IC_REG_MASTER_IS_SECURE_1_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_1_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_1_S  1
+/** AXI_IC_REG_MASTER_IS_SECURE_2 : R/W; bitpos: [2]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_2    (BIT(2))
+#define AXI_IC_REG_MASTER_IS_SECURE_2_M  (AXI_IC_REG_MASTER_IS_SECURE_2_V << AXI_IC_REG_MASTER_IS_SECURE_2_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_2_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_2_S  2
+/** AXI_IC_REG_MASTER_IS_SECURE_3 : R/W; bitpos: [3]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_3    (BIT(3))
+#define AXI_IC_REG_MASTER_IS_SECURE_3_M  (AXI_IC_REG_MASTER_IS_SECURE_3_V << AXI_IC_REG_MASTER_IS_SECURE_3_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_3_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_3_S  3
+/** AXI_IC_REG_MASTER_IS_SECURE_4 : R/W; bitpos: [4]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_4    (BIT(4))
+#define AXI_IC_REG_MASTER_IS_SECURE_4_M  (AXI_IC_REG_MASTER_IS_SECURE_4_V << AXI_IC_REG_MASTER_IS_SECURE_4_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_4_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_4_S  4
+/** AXI_IC_REG_MASTER_IS_SECURE_5 : R/W; bitpos: [5]; default: 0;
+ *  1 means safe and 0 means not safe.
+ */
+#define AXI_IC_REG_MASTER_IS_SECURE_5    (BIT(5))
+#define AXI_IC_REG_MASTER_IS_SECURE_5_M  (AXI_IC_REG_MASTER_IS_SECURE_5_V << AXI_IC_REG_MASTER_IS_SECURE_5_S)
+#define AXI_IC_REG_MASTER_IS_SECURE_5_V  0x00000001U
+#define AXI_IC_REG_MASTER_IS_SECURE_5_S  5
+
+/** AXI_IC_MASTER_SECURITY_OVERRIDE_REG register
+ *  The control signal whether master security is overridden by software.
+ */
+#define AXI_IC_MASTER_SECURITY_OVERRIDE_REG (DR_REG_AXI_IC_BASE + 0x90)
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0 : R/W; bitpos: [0]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0    (BIT(0))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_0_S  0
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1 : R/W; bitpos: [1]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1    (BIT(1))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_1_S  1
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2 : R/W; bitpos: [2]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2    (BIT(2))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_2_S  2
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3 : R/W; bitpos: [3]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3    (BIT(3))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_3_S  3
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4 : R/W; bitpos: [4]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4    (BIT(4))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_4_S  4
+/** AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5 : R/W; bitpos: [5]; default: 0;
+ *  0 means not overridden, and 1 means overridden.
+ */
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5    (BIT(5))
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5_M  (AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5_V << AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5_S)
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5_V  0x00000001U
+#define AXI_IC_REG_MASTER_SECURITY_OVERRIDE_5_S  5
+
+/** AXI_IC_AW_QOS_VALUE_0_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_0_REG (DR_REG_AXI_IC_BASE + 0x94)
+/** AXI_IC_REG_AW_QOS_VALUE_0 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_0    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_0_M  (AXI_IC_REG_AW_QOS_VALUE_0_V << AXI_IC_REG_AW_QOS_VALUE_0_S)
+#define AXI_IC_REG_AW_QOS_VALUE_0_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_0_S  0
+
+/** AXI_IC_AW_QOS_VALUE_1_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_1_REG (DR_REG_AXI_IC_BASE + 0x98)
+/** AXI_IC_REG_AW_QOS_VALUE_1 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_1    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_1_M  (AXI_IC_REG_AW_QOS_VALUE_1_V << AXI_IC_REG_AW_QOS_VALUE_1_S)
+#define AXI_IC_REG_AW_QOS_VALUE_1_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_1_S  0
+
+/** AXI_IC_AW_QOS_VALUE_2_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_2_REG (DR_REG_AXI_IC_BASE + 0x9c)
+/** AXI_IC_REG_AW_QOS_VALUE_2 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_2    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_2_M  (AXI_IC_REG_AW_QOS_VALUE_2_V << AXI_IC_REG_AW_QOS_VALUE_2_S)
+#define AXI_IC_REG_AW_QOS_VALUE_2_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_2_S  0
+
+/** AXI_IC_AW_QOS_VALUE_3_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_3_REG (DR_REG_AXI_IC_BASE + 0xa0)
+/** AXI_IC_REG_AW_QOS_VALUE_3 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_3    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_3_M  (AXI_IC_REG_AW_QOS_VALUE_3_V << AXI_IC_REG_AW_QOS_VALUE_3_S)
+#define AXI_IC_REG_AW_QOS_VALUE_3_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_3_S  0
+
+/** AXI_IC_AW_QOS_VALUE_4_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_4_REG (DR_REG_AXI_IC_BASE + 0xa4)
+/** AXI_IC_REG_AW_QOS_VALUE_4 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_4    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_4_M  (AXI_IC_REG_AW_QOS_VALUE_4_V << AXI_IC_REG_AW_QOS_VALUE_4_S)
+#define AXI_IC_REG_AW_QOS_VALUE_4_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_4_S  0
+
+/** AXI_IC_AW_QOS_VALUE_5_REG register
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_AW_QOS_VALUE_5_REG (DR_REG_AXI_IC_BASE + 0xa8)
+/** AXI_IC_REG_AW_QOS_VALUE_5 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AW QOS value specified by software.
+ */
+#define AXI_IC_REG_AW_QOS_VALUE_5    0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_5_M  (AXI_IC_REG_AW_QOS_VALUE_5_V << AXI_IC_REG_AW_QOS_VALUE_5_S)
+#define AXI_IC_REG_AW_QOS_VALUE_5_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_VALUE_5_S  0
+
+/** AXI_IC_AR_QOS_VALUE_0_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_0_REG (DR_REG_AXI_IC_BASE + 0xac)
+/** AXI_IC_REG_AR_QOS_VALUE_0 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_0    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_0_M  (AXI_IC_REG_AR_QOS_VALUE_0_V << AXI_IC_REG_AR_QOS_VALUE_0_S)
+#define AXI_IC_REG_AR_QOS_VALUE_0_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_0_S  0
+
+/** AXI_IC_AR_QOS_VALUE_1_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_1_REG (DR_REG_AXI_IC_BASE + 0xb0)
+/** AXI_IC_REG_AR_QOS_VALUE_1 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_1    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_1_M  (AXI_IC_REG_AR_QOS_VALUE_1_V << AXI_IC_REG_AR_QOS_VALUE_1_S)
+#define AXI_IC_REG_AR_QOS_VALUE_1_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_1_S  0
+
+/** AXI_IC_AR_QOS_VALUE_2_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_2_REG (DR_REG_AXI_IC_BASE + 0xb4)
+/** AXI_IC_REG_AR_QOS_VALUE_2 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_2    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_2_M  (AXI_IC_REG_AR_QOS_VALUE_2_V << AXI_IC_REG_AR_QOS_VALUE_2_S)
+#define AXI_IC_REG_AR_QOS_VALUE_2_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_2_S  0
+
+/** AXI_IC_AR_QOS_VALUE_3_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_3_REG (DR_REG_AXI_IC_BASE + 0xb8)
+/** AXI_IC_REG_AR_QOS_VALUE_3 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_3    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_3_M  (AXI_IC_REG_AR_QOS_VALUE_3_V << AXI_IC_REG_AR_QOS_VALUE_3_S)
+#define AXI_IC_REG_AR_QOS_VALUE_3_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_3_S  0
+
+/** AXI_IC_AR_QOS_VALUE_4_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_4_REG (DR_REG_AXI_IC_BASE + 0xbc)
+/** AXI_IC_REG_AR_QOS_VALUE_4 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_4    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_4_M  (AXI_IC_REG_AR_QOS_VALUE_4_V << AXI_IC_REG_AR_QOS_VALUE_4_S)
+#define AXI_IC_REG_AR_QOS_VALUE_4_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_4_S  0
+
+/** AXI_IC_AR_QOS_VALUE_5_REG register
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_AR_QOS_VALUE_5_REG (DR_REG_AXI_IC_BASE + 0xc0)
+/** AXI_IC_REG_AR_QOS_VALUE_5 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core AR QOS value specified by software.
+ */
+#define AXI_IC_REG_AR_QOS_VALUE_5    0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_5_M  (AXI_IC_REG_AR_QOS_VALUE_5_V << AXI_IC_REG_AR_QOS_VALUE_5_S)
+#define AXI_IC_REG_AR_QOS_VALUE_5_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_VALUE_5_S  0
+
+/** AXI_IC_B_PRIOR_VALUE_0_REG register
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_B_PRIOR_VALUE_0_REG (DR_REG_AXI_IC_BASE + 0xc4)
+/** AXI_IC_REG_B_PRIOR_VALUE_0 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_REG_B_PRIOR_VALUE_0    0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_0_M  (AXI_IC_REG_B_PRIOR_VALUE_0_V << AXI_IC_REG_B_PRIOR_VALUE_0_S)
+#define AXI_IC_REG_B_PRIOR_VALUE_0_V  0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_0_S  0
+
+/** AXI_IC_B_PRIOR_VALUE_1_REG register
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_B_PRIOR_VALUE_1_REG (DR_REG_AXI_IC_BASE + 0xc8)
+/** AXI_IC_REG_B_PRIOR_VALUE_1 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_REG_B_PRIOR_VALUE_1    0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_1_M  (AXI_IC_REG_B_PRIOR_VALUE_1_V << AXI_IC_REG_B_PRIOR_VALUE_1_S)
+#define AXI_IC_REG_B_PRIOR_VALUE_1_V  0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_1_S  0
+
+/** AXI_IC_B_PRIOR_VALUE_2_REG register
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_B_PRIOR_VALUE_2_REG (DR_REG_AXI_IC_BASE + 0xcc)
+/** AXI_IC_REG_B_PRIOR_VALUE_2 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core B priority value specified by software.
+ */
+#define AXI_IC_REG_B_PRIOR_VALUE_2    0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_2_M  (AXI_IC_REG_B_PRIOR_VALUE_2_V << AXI_IC_REG_B_PRIOR_VALUE_2_S)
+#define AXI_IC_REG_B_PRIOR_VALUE_2_V  0x0000000FU
+#define AXI_IC_REG_B_PRIOR_VALUE_2_S  0
+
+/** AXI_IC_R_PRIOR_VALUE_0_REG register
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_R_PRIOR_VALUE_0_REG (DR_REG_AXI_IC_BASE + 0xd0)
+/** AXI_IC_REG_R_PRIOR_VALUE_0 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_REG_R_PRIOR_VALUE_0    0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_0_M  (AXI_IC_REG_R_PRIOR_VALUE_0_V << AXI_IC_REG_R_PRIOR_VALUE_0_S)
+#define AXI_IC_REG_R_PRIOR_VALUE_0_V  0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_0_S  0
+
+/** AXI_IC_R_PRIOR_VALUE_1_REG register
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_R_PRIOR_VALUE_1_REG (DR_REG_AXI_IC_BASE + 0xd4)
+/** AXI_IC_REG_R_PRIOR_VALUE_1 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_REG_R_PRIOR_VALUE_1    0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_1_M  (AXI_IC_REG_R_PRIOR_VALUE_1_V << AXI_IC_REG_R_PRIOR_VALUE_1_S)
+#define AXI_IC_REG_R_PRIOR_VALUE_1_V  0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_1_S  0
+
+/** AXI_IC_R_PRIOR_VALUE_2_REG register
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_R_PRIOR_VALUE_2_REG (DR_REG_AXI_IC_BASE + 0xd8)
+/** AXI_IC_REG_R_PRIOR_VALUE_2 : R/W; bitpos: [3:0]; default: 0;
+ *  AXI IC core R priority value specified by software.
+ */
+#define AXI_IC_REG_R_PRIOR_VALUE_2    0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_2_M  (AXI_IC_REG_R_PRIOR_VALUE_2_V << AXI_IC_REG_R_PRIOR_VALUE_2_S)
+#define AXI_IC_REG_R_PRIOR_VALUE_2_V  0x0000000FU
+#define AXI_IC_REG_R_PRIOR_VALUE_2_S  0
+
+/** AXI_IC_AW_QOS_SEL_0_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_0_REG (DR_REG_AXI_IC_BASE + 0xdc)
+/** AXI_IC_REG_AW_QOS_SEL_0 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_0    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_0_M  (AXI_IC_REG_AW_QOS_SEL_0_V << AXI_IC_REG_AW_QOS_SEL_0_S)
+#define AXI_IC_REG_AW_QOS_SEL_0_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_0_S  0
+
+/** AXI_IC_AW_QOS_SEL_1_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_1_REG (DR_REG_AXI_IC_BASE + 0xe0)
+/** AXI_IC_REG_AW_QOS_SEL_1 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_1    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_1_M  (AXI_IC_REG_AW_QOS_SEL_1_V << AXI_IC_REG_AW_QOS_SEL_1_S)
+#define AXI_IC_REG_AW_QOS_SEL_1_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_1_S  0
+
+/** AXI_IC_AW_QOS_SEL_2_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_2_REG (DR_REG_AXI_IC_BASE + 0xe4)
+/** AXI_IC_REG_AW_QOS_SEL_2 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_2    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_2_M  (AXI_IC_REG_AW_QOS_SEL_2_V << AXI_IC_REG_AW_QOS_SEL_2_S)
+#define AXI_IC_REG_AW_QOS_SEL_2_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_2_S  0
+
+/** AXI_IC_AW_QOS_SEL_3_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_3_REG (DR_REG_AXI_IC_BASE + 0xe8)
+/** AXI_IC_REG_AW_QOS_SEL_3 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_3    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_3_M  (AXI_IC_REG_AW_QOS_SEL_3_V << AXI_IC_REG_AW_QOS_SEL_3_S)
+#define AXI_IC_REG_AW_QOS_SEL_3_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_3_S  0
+
+/** AXI_IC_AW_QOS_SEL_4_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_4_REG (DR_REG_AXI_IC_BASE + 0xec)
+/** AXI_IC_REG_AW_QOS_SEL_4 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_4    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_4_M  (AXI_IC_REG_AW_QOS_SEL_4_V << AXI_IC_REG_AW_QOS_SEL_4_S)
+#define AXI_IC_REG_AW_QOS_SEL_4_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_4_S  0
+
+/** AXI_IC_AW_QOS_SEL_5_REG register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+#define AXI_IC_AW_QOS_SEL_5_REG (DR_REG_AXI_IC_BASE + 0xf0)
+/** AXI_IC_REG_AW_QOS_SEL_5 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AW_QOS_SEL_5    0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_5_M  (AXI_IC_REG_AW_QOS_SEL_5_V << AXI_IC_REG_AW_QOS_SEL_5_S)
+#define AXI_IC_REG_AW_QOS_SEL_5_V  0x00000003U
+#define AXI_IC_REG_AW_QOS_SEL_5_S  0
+
+/** AXI_IC_AR_QOS_SEL_0_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_0_REG (DR_REG_AXI_IC_BASE + 0xf4)
+/** AXI_IC_REG_AR_QOS_SEL_0 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_0    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_0_M  (AXI_IC_REG_AR_QOS_SEL_0_V << AXI_IC_REG_AR_QOS_SEL_0_S)
+#define AXI_IC_REG_AR_QOS_SEL_0_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_0_S  0
+
+/** AXI_IC_AR_QOS_SEL_1_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_1_REG (DR_REG_AXI_IC_BASE + 0xf8)
+/** AXI_IC_REG_AR_QOS_SEL_1 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_1    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_1_M  (AXI_IC_REG_AR_QOS_SEL_1_V << AXI_IC_REG_AR_QOS_SEL_1_S)
+#define AXI_IC_REG_AR_QOS_SEL_1_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_1_S  0
+
+/** AXI_IC_AR_QOS_SEL_2_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_2_REG (DR_REG_AXI_IC_BASE + 0xfc)
+/** AXI_IC_REG_AR_QOS_SEL_2 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_2    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_2_M  (AXI_IC_REG_AR_QOS_SEL_2_V << AXI_IC_REG_AR_QOS_SEL_2_S)
+#define AXI_IC_REG_AR_QOS_SEL_2_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_2_S  0
+
+/** AXI_IC_AR_QOS_SEL_3_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_3_REG (DR_REG_AXI_IC_BASE + 0x100)
+/** AXI_IC_REG_AR_QOS_SEL_3 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_3    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_3_M  (AXI_IC_REG_AR_QOS_SEL_3_V << AXI_IC_REG_AR_QOS_SEL_3_S)
+#define AXI_IC_REG_AR_QOS_SEL_3_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_3_S  0
+
+/** AXI_IC_AR_QOS_SEL_4_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_4_REG (DR_REG_AXI_IC_BASE + 0x104)
+/** AXI_IC_REG_AR_QOS_SEL_4 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_4    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_4_M  (AXI_IC_REG_AR_QOS_SEL_4_V << AXI_IC_REG_AR_QOS_SEL_4_S)
+#define AXI_IC_REG_AR_QOS_SEL_4_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_4_S  0
+
+/** AXI_IC_AR_QOS_SEL_5_REG register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+#define AXI_IC_AR_QOS_SEL_5_REG (DR_REG_AXI_IC_BASE + 0x108)
+/** AXI_IC_REG_AR_QOS_SEL_5 : R/W; bitpos: [1:0]; default: 0;
+ *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+ *  software, 2'b10 selects the QOS value set by the QOS regulator.
+ */
+#define AXI_IC_REG_AR_QOS_SEL_5    0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_5_M  (AXI_IC_REG_AR_QOS_SEL_5_V << AXI_IC_REG_AR_QOS_SEL_5_S)
+#define AXI_IC_REG_AR_QOS_SEL_5_V  0x00000003U
+#define AXI_IC_REG_AR_QOS_SEL_5_S  0
+
+/** AXI_IC_AW_QOS_RECOVERY_REG register
+ *  AXI IC core AW QOS recovery signal specified by software.
+ */
+#define AXI_IC_AW_QOS_RECOVERY_REG (DR_REG_AXI_IC_BASE + 0x10c)
+/** AXI_IC_REG_AW_QOS_RECOVERY_0 : R/W; bitpos: [0]; default: 0;
+ *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AW_QOS_RECOVERY_0    (BIT(0))
+#define AXI_IC_REG_AW_QOS_RECOVERY_0_M  (AXI_IC_REG_AW_QOS_RECOVERY_0_V << AXI_IC_REG_AW_QOS_RECOVERY_0_S)
+#define AXI_IC_REG_AW_QOS_RECOVERY_0_V  0x00000001U
+#define AXI_IC_REG_AW_QOS_RECOVERY_0_S  0
+/** AXI_IC_REG_AW_QOS_RECOVERY_1 : R/W; bitpos: [1]; default: 0;
+ *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AW_QOS_RECOVERY_1    (BIT(1))
+#define AXI_IC_REG_AW_QOS_RECOVERY_1_M  (AXI_IC_REG_AW_QOS_RECOVERY_1_V << AXI_IC_REG_AW_QOS_RECOVERY_1_S)
+#define AXI_IC_REG_AW_QOS_RECOVERY_1_V  0x00000001U
+#define AXI_IC_REG_AW_QOS_RECOVERY_1_S  1
+/** AXI_IC_REG_AW_QOS_RECOVERY_2 : R/W; bitpos: [2]; default: 0;
+ *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AW_QOS_RECOVERY_2    (BIT(2))
+#define AXI_IC_REG_AW_QOS_RECOVERY_2_M  (AXI_IC_REG_AW_QOS_RECOVERY_2_V << AXI_IC_REG_AW_QOS_RECOVERY_2_S)
+#define AXI_IC_REG_AW_QOS_RECOVERY_2_V  0x00000001U
+#define AXI_IC_REG_AW_QOS_RECOVERY_2_S  2
+
+/** AXI_IC_AR_QOS_RECOVERY_REG register
+ *  AXI IC core AR QOS recovery signal specified by software.
+ */
+#define AXI_IC_AR_QOS_RECOVERY_REG (DR_REG_AXI_IC_BASE + 0x110)
+/** AXI_IC_REG_AR_QOS_RECOVERY_0 : R/W; bitpos: [0]; default: 0;
+ *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AR_QOS_RECOVERY_0    (BIT(0))
+#define AXI_IC_REG_AR_QOS_RECOVERY_0_M  (AXI_IC_REG_AR_QOS_RECOVERY_0_V << AXI_IC_REG_AR_QOS_RECOVERY_0_S)
+#define AXI_IC_REG_AR_QOS_RECOVERY_0_V  0x00000001U
+#define AXI_IC_REG_AR_QOS_RECOVERY_0_S  0
+/** AXI_IC_REG_AR_QOS_RECOVERY_1 : R/W; bitpos: [1]; default: 0;
+ *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AR_QOS_RECOVERY_1    (BIT(1))
+#define AXI_IC_REG_AR_QOS_RECOVERY_1_M  (AXI_IC_REG_AR_QOS_RECOVERY_1_V << AXI_IC_REG_AR_QOS_RECOVERY_1_S)
+#define AXI_IC_REG_AR_QOS_RECOVERY_1_V  0x00000001U
+#define AXI_IC_REG_AR_QOS_RECOVERY_1_S  1
+/** AXI_IC_REG_AR_QOS_RECOVERY_2 : R/W; bitpos: [2]; default: 0;
+ *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+ *  QOS regulator or software).
+ */
+#define AXI_IC_REG_AR_QOS_RECOVERY_2    (BIT(2))
+#define AXI_IC_REG_AR_QOS_RECOVERY_2_M  (AXI_IC_REG_AR_QOS_RECOVERY_2_V << AXI_IC_REG_AR_QOS_RECOVERY_2_S)
+#define AXI_IC_REG_AR_QOS_RECOVERY_2_V  0x00000001U
+#define AXI_IC_REG_AR_QOS_RECOVERY_2_S  2
+
+/** AXI_IC_AW_QOS_ID_MASK_0_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_0_REG (DR_REG_AXI_IC_BASE + 0x114)
+/** AXI_IC_REG_AW_QOS_ID_MASK_0 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_0    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_0_M  (AXI_IC_REG_AW_QOS_ID_MASK_0_V << AXI_IC_REG_AW_QOS_ID_MASK_0_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_0_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_0_S  0
+
+/** AXI_IC_AW_QOS_ID_MASK_1_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_1_REG (DR_REG_AXI_IC_BASE + 0x118)
+/** AXI_IC_REG_AW_QOS_ID_MASK_1 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_1    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_1_M  (AXI_IC_REG_AW_QOS_ID_MASK_1_V << AXI_IC_REG_AW_QOS_ID_MASK_1_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_1_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_1_S  0
+
+/** AXI_IC_AW_QOS_ID_MASK_2_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_2_REG (DR_REG_AXI_IC_BASE + 0x11c)
+/** AXI_IC_REG_AW_QOS_ID_MASK_2 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_2    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_2_M  (AXI_IC_REG_AW_QOS_ID_MASK_2_V << AXI_IC_REG_AW_QOS_ID_MASK_2_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_2_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_2_S  0
+
+/** AXI_IC_AW_QOS_ID_MASK_3_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_3_REG (DR_REG_AXI_IC_BASE + 0x120)
+/** AXI_IC_REG_AW_QOS_ID_MASK_3 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_3    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_3_M  (AXI_IC_REG_AW_QOS_ID_MASK_3_V << AXI_IC_REG_AW_QOS_ID_MASK_3_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_3_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_3_S  0
+
+/** AXI_IC_AW_QOS_ID_MASK_4_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_4_REG (DR_REG_AXI_IC_BASE + 0x124)
+/** AXI_IC_REG_AW_QOS_ID_MASK_4 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_4    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_4_M  (AXI_IC_REG_AW_QOS_ID_MASK_4_V << AXI_IC_REG_AW_QOS_ID_MASK_4_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_4_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_4_S  0
+
+/** AXI_IC_AW_QOS_ID_MASK_5_REG register
+ *  Config the aw channel id mask for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_MASK_5_REG (DR_REG_AXI_IC_BASE + 0x128)
+/** AXI_IC_REG_AW_QOS_ID_MASK_5 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_MASK_5    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_5_M  (AXI_IC_REG_AW_QOS_ID_MASK_5_V << AXI_IC_REG_AW_QOS_ID_MASK_5_S)
+#define AXI_IC_REG_AW_QOS_ID_MASK_5_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_MASK_5_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_0_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_0_REG (DR_REG_AXI_IC_BASE + 0x12c)
+/** AXI_IC_REG_AR_QOS_ID_MASK_0 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_0    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_0_M  (AXI_IC_REG_AR_QOS_ID_MASK_0_V << AXI_IC_REG_AR_QOS_ID_MASK_0_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_0_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_0_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_1_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_1_REG (DR_REG_AXI_IC_BASE + 0x130)
+/** AXI_IC_REG_AR_QOS_ID_MASK_1 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_1    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_1_M  (AXI_IC_REG_AR_QOS_ID_MASK_1_V << AXI_IC_REG_AR_QOS_ID_MASK_1_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_1_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_1_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_2_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_2_REG (DR_REG_AXI_IC_BASE + 0x134)
+/** AXI_IC_REG_AR_QOS_ID_MASK_2 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_2    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_2_M  (AXI_IC_REG_AR_QOS_ID_MASK_2_V << AXI_IC_REG_AR_QOS_ID_MASK_2_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_2_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_2_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_3_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_3_REG (DR_REG_AXI_IC_BASE + 0x138)
+/** AXI_IC_REG_AR_QOS_ID_MASK_3 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_3    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_3_M  (AXI_IC_REG_AR_QOS_ID_MASK_3_V << AXI_IC_REG_AR_QOS_ID_MASK_3_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_3_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_3_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_4_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_4_REG (DR_REG_AXI_IC_BASE + 0x13c)
+/** AXI_IC_REG_AR_QOS_ID_MASK_4 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_4    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_4_M  (AXI_IC_REG_AR_QOS_ID_MASK_4_V << AXI_IC_REG_AR_QOS_ID_MASK_4_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_4_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_4_S  0
+
+/** AXI_IC_AR_QOS_ID_MASK_5_REG register
+ *  Config the ar channel id mask for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_MASK_5_REG (DR_REG_AXI_IC_BASE + 0x140)
+/** AXI_IC_REG_AR_QOS_ID_MASK_5 : R/W; bitpos: [3:0]; default: 15;
+ *  mask for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_MASK_5    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_5_M  (AXI_IC_REG_AR_QOS_ID_MASK_5_V << AXI_IC_REG_AR_QOS_ID_MASK_5_S)
+#define AXI_IC_REG_AR_QOS_ID_MASK_5_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_MASK_5_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_0_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_0_REG (DR_REG_AXI_IC_BASE + 0x144)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_0 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_0    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_0_M  (AXI_IC_REG_AW_QOS_ID_FILTER_0_V << AXI_IC_REG_AW_QOS_ID_FILTER_0_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_0_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_0_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_1_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_1_REG (DR_REG_AXI_IC_BASE + 0x148)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_1 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_1    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_1_M  (AXI_IC_REG_AW_QOS_ID_FILTER_1_V << AXI_IC_REG_AW_QOS_ID_FILTER_1_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_1_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_1_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_2_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_2_REG (DR_REG_AXI_IC_BASE + 0x14c)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_2 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_2    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_2_M  (AXI_IC_REG_AW_QOS_ID_FILTER_2_V << AXI_IC_REG_AW_QOS_ID_FILTER_2_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_2_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_2_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_3_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_3_REG (DR_REG_AXI_IC_BASE + 0x150)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_3 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_3    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_3_M  (AXI_IC_REG_AW_QOS_ID_FILTER_3_V << AXI_IC_REG_AW_QOS_ID_FILTER_3_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_3_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_3_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_4_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_4_REG (DR_REG_AXI_IC_BASE + 0x154)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_4 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_4    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_4_M  (AXI_IC_REG_AW_QOS_ID_FILTER_4_V << AXI_IC_REG_AW_QOS_ID_FILTER_4_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_4_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_4_S  0
+
+/** AXI_IC_AW_QOS_ID_FILTER_5_REG register
+ *  Config the aw channel id filter for id filter function.
+ */
+#define AXI_IC_AW_QOS_ID_FILTER_5_REG (DR_REG_AXI_IC_BASE + 0x158)
+/** AXI_IC_REG_AW_QOS_ID_FILTER_5 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of aw channel id.
+ */
+#define AXI_IC_REG_AW_QOS_ID_FILTER_5    0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_5_M  (AXI_IC_REG_AW_QOS_ID_FILTER_5_V << AXI_IC_REG_AW_QOS_ID_FILTER_5_S)
+#define AXI_IC_REG_AW_QOS_ID_FILTER_5_V  0x0000000FU
+#define AXI_IC_REG_AW_QOS_ID_FILTER_5_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_0_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_0_REG (DR_REG_AXI_IC_BASE + 0x15c)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_0 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_0    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_0_M  (AXI_IC_REG_AR_QOS_ID_FILTER_0_V << AXI_IC_REG_AR_QOS_ID_FILTER_0_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_0_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_0_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_1_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_1_REG (DR_REG_AXI_IC_BASE + 0x160)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_1 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_1    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_1_M  (AXI_IC_REG_AR_QOS_ID_FILTER_1_V << AXI_IC_REG_AR_QOS_ID_FILTER_1_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_1_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_1_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_2_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_2_REG (DR_REG_AXI_IC_BASE + 0x164)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_2 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_2    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_2_M  (AXI_IC_REG_AR_QOS_ID_FILTER_2_V << AXI_IC_REG_AR_QOS_ID_FILTER_2_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_2_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_2_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_3_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_3_REG (DR_REG_AXI_IC_BASE + 0x168)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_3 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_3    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_3_M  (AXI_IC_REG_AR_QOS_ID_FILTER_3_V << AXI_IC_REG_AR_QOS_ID_FILTER_3_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_3_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_3_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_4_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_4_REG (DR_REG_AXI_IC_BASE + 0x16c)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_4 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_4    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_4_M  (AXI_IC_REG_AR_QOS_ID_FILTER_4_V << AXI_IC_REG_AR_QOS_ID_FILTER_4_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_4_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_4_S  0
+
+/** AXI_IC_AR_QOS_ID_FILTER_5_REG register
+ *  Config the ar channel id filter for id filter function.
+ */
+#define AXI_IC_AR_QOS_ID_FILTER_5_REG (DR_REG_AXI_IC_BASE + 0x170)
+/** AXI_IC_REG_AR_QOS_ID_FILTER_5 : R/W; bitpos: [3:0]; default: 15;
+ *  filter for enable qos of ar channel id.
+ */
+#define AXI_IC_REG_AR_QOS_ID_FILTER_5    0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_5_M  (AXI_IC_REG_AR_QOS_ID_FILTER_5_V << AXI_IC_REG_AR_QOS_ID_FILTER_5_S)
+#define AXI_IC_REG_AR_QOS_ID_FILTER_5_V  0x0000000FU
+#define AXI_IC_REG_AR_QOS_ID_FILTER_5_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_0_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_0_REG (DR_REG_AXI_IC_BASE + 0x174)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_0 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_0    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_0_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_0_V << AXI_IC_REG_AW_QOS_CTRL_CFG_0_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_0_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_0_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_1_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_1_REG (DR_REG_AXI_IC_BASE + 0x178)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_1 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_1    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_1_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_1_V << AXI_IC_REG_AW_QOS_CTRL_CFG_1_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_1_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_1_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_2_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_2_REG (DR_REG_AXI_IC_BASE + 0x17c)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_2 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_2    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_2_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_2_V << AXI_IC_REG_AW_QOS_CTRL_CFG_2_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_2_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_2_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_3_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_3_REG (DR_REG_AXI_IC_BASE + 0x180)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_3 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_3    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_3_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_3_V << AXI_IC_REG_AW_QOS_CTRL_CFG_3_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_3_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_3_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_4_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_4_REG (DR_REG_AXI_IC_BASE + 0x184)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_4 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_4    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_4_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_4_V << AXI_IC_REG_AW_QOS_CTRL_CFG_4_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_4_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_4_S  0
+
+/** AXI_IC_AW_QOS_CTRL_CFG_5_REG register
+ *  Config the QOS Regulator aw module control.
+ */
+#define AXI_IC_AW_QOS_CTRL_CFG_5_REG (DR_REG_AXI_IC_BASE + 0x188)
+/** AXI_IC_REG_AW_QOS_CTRL_CFG_5 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_5    0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_5_M  (AXI_IC_REG_AW_QOS_CTRL_CFG_5_V << AXI_IC_REG_AW_QOS_CTRL_CFG_5_S)
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_5_V  0xFFFFFFFFU
+#define AXI_IC_REG_AW_QOS_CTRL_CFG_5_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_0_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_0_REG (DR_REG_AXI_IC_BASE + 0x18c)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_0 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_0    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_0_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_0_V << AXI_IC_REG_AR_QOS_CTRL_CFG_0_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_0_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_0_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_1_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_1_REG (DR_REG_AXI_IC_BASE + 0x190)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_1 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_1    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_1_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_1_V << AXI_IC_REG_AR_QOS_CTRL_CFG_1_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_1_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_1_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_2_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_2_REG (DR_REG_AXI_IC_BASE + 0x194)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_2 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_2    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_2_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_2_V << AXI_IC_REG_AR_QOS_CTRL_CFG_2_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_2_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_2_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_3_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_3_REG (DR_REG_AXI_IC_BASE + 0x198)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_3 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_3    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_3_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_3_V << AXI_IC_REG_AR_QOS_CTRL_CFG_3_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_3_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_3_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_4_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_4_REG (DR_REG_AXI_IC_BASE + 0x19c)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_4 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_4    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_4_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_4_V << AXI_IC_REG_AR_QOS_CTRL_CFG_4_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_4_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_4_S  0
+
+/** AXI_IC_AR_QOS_CTRL_CFG_5_REG register
+ *  Config the QOS Regulator ar module control.
+ */
+#define AXI_IC_AR_QOS_CTRL_CFG_5_REG (DR_REG_AXI_IC_BASE + 0x1a0)
+/** AXI_IC_REG_AR_QOS_CTRL_CFG_5 : R/W; bitpos: [31:0]; default: 8208;
+ *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+ *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+ */
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_5    0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_5_M  (AXI_IC_REG_AR_QOS_CTRL_CFG_5_V << AXI_IC_REG_AR_QOS_CTRL_CFG_5_S)
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_5_V  0xFFFFFFFFU
+#define AXI_IC_REG_AR_QOS_CTRL_CFG_5_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_0_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_0_REG (DR_REG_AXI_IC_BASE + 0x1a4)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_0 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_0    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_0_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_0_V << AXI_IC_REG_AW_QOS_TRANS_RATE_0_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_0_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_0_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_1_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_1_REG (DR_REG_AXI_IC_BASE + 0x1a8)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_1 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_1    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_1_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_1_V << AXI_IC_REG_AW_QOS_TRANS_RATE_1_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_1_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_1_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_2_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_2_REG (DR_REG_AXI_IC_BASE + 0x1ac)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_2 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_2    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_2_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_2_V << AXI_IC_REG_AW_QOS_TRANS_RATE_2_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_2_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_2_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_3_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_3_REG (DR_REG_AXI_IC_BASE + 0x1b0)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_3 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_3    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_3_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_3_V << AXI_IC_REG_AW_QOS_TRANS_RATE_3_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_3_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_3_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_4_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_4_REG (DR_REG_AXI_IC_BASE + 0x1b4)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_4 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_4    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_4_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_4_V << AXI_IC_REG_AW_QOS_TRANS_RATE_4_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_4_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_4_S  0
+
+/** AXI_IC_AW_QOS_TRANS_RATE_5_REG register
+ *  Config the Current Master Write bandwidth.
+ */
+#define AXI_IC_AW_QOS_TRANS_RATE_5_REG (DR_REG_AXI_IC_BASE + 0x1b8)
+/** AXI_IC_REG_AW_QOS_TRANS_RATE_5 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_5    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_5_M  (AXI_IC_REG_AW_QOS_TRANS_RATE_5_V << AXI_IC_REG_AW_QOS_TRANS_RATE_5_S)
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_5_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_TRANS_RATE_5_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_0_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_0_REG (DR_REG_AXI_IC_BASE + 0x1bc)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_0 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_0    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_0_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_0_V << AXI_IC_REG_AR_QOS_TRANS_RATE_0_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_0_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_0_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_1_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_1_REG (DR_REG_AXI_IC_BASE + 0x1c0)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_1 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_1    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_1_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_1_V << AXI_IC_REG_AR_QOS_TRANS_RATE_1_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_1_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_1_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_2_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_2_REG (DR_REG_AXI_IC_BASE + 0x1c4)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_2 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_2    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_2_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_2_V << AXI_IC_REG_AR_QOS_TRANS_RATE_2_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_2_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_2_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_3_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_3_REG (DR_REG_AXI_IC_BASE + 0x1c8)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_3 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_3    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_3_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_3_V << AXI_IC_REG_AR_QOS_TRANS_RATE_3_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_3_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_3_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_4_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_4_REG (DR_REG_AXI_IC_BASE + 0x1cc)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_4 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_4    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_4_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_4_V << AXI_IC_REG_AR_QOS_TRANS_RATE_4_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_4_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_4_S  0
+
+/** AXI_IC_AR_QOS_TRANS_RATE_5_REG register
+ *  Config the Current Master Read bandwidth.
+ */
+#define AXI_IC_AR_QOS_TRANS_RATE_5_REG (DR_REG_AXI_IC_BASE + 0x1d0)
+/** AXI_IC_REG_AR_QOS_TRANS_RATE_5 : R/W; bitpos: [15:0]; default: 12296;
+ *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_5    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_5_M  (AXI_IC_REG_AR_QOS_TRANS_RATE_5_V << AXI_IC_REG_AR_QOS_TRANS_RATE_5_S)
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_5_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_TRANS_RATE_5_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_0_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_0_REG (DR_REG_AXI_IC_BASE + 0x1d4)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_0 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_0    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_0_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_0_V << AXI_IC_REG_AW_QOS_PEAK_RATE_0_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_0_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_0_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_1_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_1_REG (DR_REG_AXI_IC_BASE + 0x1d8)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_1 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_1    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_1_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_1_V << AXI_IC_REG_AW_QOS_PEAK_RATE_1_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_1_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_1_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_2_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_2_REG (DR_REG_AXI_IC_BASE + 0x1dc)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_2 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_2    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_2_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_2_V << AXI_IC_REG_AW_QOS_PEAK_RATE_2_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_2_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_2_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_3_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_3_REG (DR_REG_AXI_IC_BASE + 0x1e0)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_3 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_3    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_3_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_3_V << AXI_IC_REG_AW_QOS_PEAK_RATE_3_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_3_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_3_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_4_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_4_REG (DR_REG_AXI_IC_BASE + 0x1e4)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_4 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_4    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_4_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_4_V << AXI_IC_REG_AW_QOS_PEAK_RATE_4_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_4_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_4_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_5_REG register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_5_REG (DR_REG_AXI_IC_BASE + 0x1e8)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_5 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the aw channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_5    0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_5_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_5_V << AXI_IC_REG_AW_QOS_PEAK_RATE_5_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_5_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_5_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_0_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_0_REG (DR_REG_AXI_IC_BASE + 0x1ec)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_0 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_0    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_0_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_0_V << AXI_IC_REG_AR_QOS_PEAK_RATE_0_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_0_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_0_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_1_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_1_REG (DR_REG_AXI_IC_BASE + 0x1f0)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_1 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_1    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_1_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_1_V << AXI_IC_REG_AR_QOS_PEAK_RATE_1_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_1_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_1_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_2_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_2_REG (DR_REG_AXI_IC_BASE + 0x1f4)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_2 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_2    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_2_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_2_V << AXI_IC_REG_AR_QOS_PEAK_RATE_2_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_2_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_2_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_3_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_3_REG (DR_REG_AXI_IC_BASE + 0x1f8)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_3 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_3    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_3_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_3_V << AXI_IC_REG_AR_QOS_PEAK_RATE_3_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_3_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_3_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_4_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_4_REG (DR_REG_AXI_IC_BASE + 0x1fc)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_4 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_4    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_4_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_4_V << AXI_IC_REG_AR_QOS_PEAK_RATE_4_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_4_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_4_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_5_REG register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_5_REG (DR_REG_AXI_IC_BASE + 0x200)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_5 : R/W; bitpos: [7:0]; default: 0;
+ *  peak rate, to control the ar channel request issue rate, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_5    0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_5_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_5_V << AXI_IC_REG_AR_QOS_PEAK_RATE_5_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_5_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_5_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_0_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_0_REG (DR_REG_AXI_IC_BASE + 0x204)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_0 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_0    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_0_M  (AXI_IC_REG_AW_QOS_BURSTINESS_0_V << AXI_IC_REG_AW_QOS_BURSTINESS_0_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_0_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_0_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_1_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_1_REG (DR_REG_AXI_IC_BASE + 0x208)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_1 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_1    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_1_M  (AXI_IC_REG_AW_QOS_BURSTINESS_1_V << AXI_IC_REG_AW_QOS_BURSTINESS_1_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_1_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_1_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_2_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_2_REG (DR_REG_AXI_IC_BASE + 0x20c)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_2 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_2    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_2_M  (AXI_IC_REG_AW_QOS_BURSTINESS_2_V << AXI_IC_REG_AW_QOS_BURSTINESS_2_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_2_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_2_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_3_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_3_REG (DR_REG_AXI_IC_BASE + 0x210)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_3 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_3    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_3_M  (AXI_IC_REG_AW_QOS_BURSTINESS_3_V << AXI_IC_REG_AW_QOS_BURSTINESS_3_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_3_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_3_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_4_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_4_REG (DR_REG_AXI_IC_BASE + 0x214)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_4 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_4    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_4_M  (AXI_IC_REG_AW_QOS_BURSTINESS_4_V << AXI_IC_REG_AW_QOS_BURSTINESS_4_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_4_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_4_S  0
+
+/** AXI_IC_AW_QOS_BURSTINESS_5_REG register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AW_QOS_BURSTINESS_5_REG (DR_REG_AXI_IC_BASE + 0x218)
+/** AXI_IC_REG_AW_QOS_BURSTINESS_5 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the aw channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AW_QOS_BURSTINESS_5    0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_5_M  (AXI_IC_REG_AW_QOS_BURSTINESS_5_V << AXI_IC_REG_AW_QOS_BURSTINESS_5_S)
+#define AXI_IC_REG_AW_QOS_BURSTINESS_5_V  0x00000FFFU
+#define AXI_IC_REG_AW_QOS_BURSTINESS_5_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_0_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_0_REG (DR_REG_AXI_IC_BASE + 0x21c)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_0 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_0    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_0_M  (AXI_IC_REG_AR_QOS_BURSTINESS_0_V << AXI_IC_REG_AR_QOS_BURSTINESS_0_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_0_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_0_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_1_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_1_REG (DR_REG_AXI_IC_BASE + 0x220)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_1 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_1    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_1_M  (AXI_IC_REG_AR_QOS_BURSTINESS_1_V << AXI_IC_REG_AR_QOS_BURSTINESS_1_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_1_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_1_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_2_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_2_REG (DR_REG_AXI_IC_BASE + 0x224)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_2 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_2    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_2_M  (AXI_IC_REG_AR_QOS_BURSTINESS_2_V << AXI_IC_REG_AR_QOS_BURSTINESS_2_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_2_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_2_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_3_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_3_REG (DR_REG_AXI_IC_BASE + 0x228)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_3 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_3    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_3_M  (AXI_IC_REG_AR_QOS_BURSTINESS_3_V << AXI_IC_REG_AR_QOS_BURSTINESS_3_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_3_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_3_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_4_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_4_REG (DR_REG_AXI_IC_BASE + 0x22c)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_4 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_4    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_4_M  (AXI_IC_REG_AR_QOS_BURSTINESS_4_V << AXI_IC_REG_AR_QOS_BURSTINESS_4_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_4_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_4_S  0
+
+/** AXI_IC_AR_QOS_BURSTINESS_5_REG register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+#define AXI_IC_AR_QOS_BURSTINESS_5_REG (DR_REG_AXI_IC_BASE + 0x230)
+/** AXI_IC_REG_AR_QOS_BURSTINESS_5 : R/W; bitpos: [11:0]; default: 128;
+ *  the maximum numbers of the ar channel token, default 128 tokens.
+ */
+#define AXI_IC_REG_AR_QOS_BURSTINESS_5    0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_5_M  (AXI_IC_REG_AR_QOS_BURSTINESS_5_V << AXI_IC_REG_AR_QOS_BURSTINESS_5_S)
+#define AXI_IC_REG_AR_QOS_BURSTINESS_5_V  0x00000FFFU
+#define AXI_IC_REG_AR_QOS_BURSTINESS_5_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_0_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_0_REG (DR_REG_AXI_IC_BASE + 0x234)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_0 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_0    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_0_M  (AXI_IC_REG_AW_QOS_CFG_VLU_0_V << AXI_IC_REG_AW_QOS_CFG_VLU_0_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_0_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_0_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_1_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_1_REG (DR_REG_AXI_IC_BASE + 0x238)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_1 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_1    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_1_M  (AXI_IC_REG_AW_QOS_CFG_VLU_1_V << AXI_IC_REG_AW_QOS_CFG_VLU_1_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_1_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_1_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_2_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_2_REG (DR_REG_AXI_IC_BASE + 0x23c)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_2 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_2    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_2_M  (AXI_IC_REG_AW_QOS_CFG_VLU_2_V << AXI_IC_REG_AW_QOS_CFG_VLU_2_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_2_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_2_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_3_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_3_REG (DR_REG_AXI_IC_BASE + 0x240)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_3 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_3    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_3_M  (AXI_IC_REG_AW_QOS_CFG_VLU_3_V << AXI_IC_REG_AW_QOS_CFG_VLU_3_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_3_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_3_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_4_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_4_REG (DR_REG_AXI_IC_BASE + 0x244)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_4 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_4    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_4_M  (AXI_IC_REG_AW_QOS_CFG_VLU_4_V << AXI_IC_REG_AW_QOS_CFG_VLU_4_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_4_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_4_S  0
+
+/** AXI_IC_AW_QOS_CFG_VLU_5_REG register
+ *  Config the QOS Priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_CFG_VLU_5_REG (DR_REG_AXI_IC_BASE + 0x248)
+/** AXI_IC_REG_AW_QOS_CFG_VLU_5 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the aw channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AW_QOS_CFG_VLU_5    0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_5_M  (AXI_IC_REG_AW_QOS_CFG_VLU_5_V << AXI_IC_REG_AW_QOS_CFG_VLU_5_S)
+#define AXI_IC_REG_AW_QOS_CFG_VLU_5_V  0x0000FFFFU
+#define AXI_IC_REG_AW_QOS_CFG_VLU_5_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_0_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_0_REG (DR_REG_AXI_IC_BASE + 0x24c)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_0 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_0    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_0_M  (AXI_IC_REG_AR_QOS_CFG_VLU_0_V << AXI_IC_REG_AR_QOS_CFG_VLU_0_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_0_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_0_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_1_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_1_REG (DR_REG_AXI_IC_BASE + 0x250)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_1 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_1    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_1_M  (AXI_IC_REG_AR_QOS_CFG_VLU_1_V << AXI_IC_REG_AR_QOS_CFG_VLU_1_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_1_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_1_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_2_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_2_REG (DR_REG_AXI_IC_BASE + 0x254)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_2 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_2    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_2_M  (AXI_IC_REG_AR_QOS_CFG_VLU_2_V << AXI_IC_REG_AR_QOS_CFG_VLU_2_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_2_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_2_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_3_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_3_REG (DR_REG_AXI_IC_BASE + 0x258)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_3 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_3    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_3_M  (AXI_IC_REG_AR_QOS_CFG_VLU_3_V << AXI_IC_REG_AR_QOS_CFG_VLU_3_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_3_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_3_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_4_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_4_REG (DR_REG_AXI_IC_BASE + 0x25c)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_4 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_4    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_4_M  (AXI_IC_REG_AR_QOS_CFG_VLU_4_V << AXI_IC_REG_AR_QOS_CFG_VLU_4_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_4_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_4_S  0
+
+/** AXI_IC_AR_QOS_CFG_VLU_5_REG register
+ *  Config the QOS Priority in AR channel.
+ */
+#define AXI_IC_AR_QOS_CFG_VLU_5_REG (DR_REG_AXI_IC_BASE + 0x260)
+/** AXI_IC_REG_AR_QOS_CFG_VLU_5 : R/W; bitpos: [15:0]; default: 55906;
+ *  the four level of the ar channel qos priority, default is 2,6,10,13
+ */
+#define AXI_IC_REG_AR_QOS_CFG_VLU_5    0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_5_M  (AXI_IC_REG_AR_QOS_CFG_VLU_5_V << AXI_IC_REG_AR_QOS_CFG_VLU_5_S)
+#define AXI_IC_REG_AR_QOS_CFG_VLU_5_V  0x0000FFFFU
+#define AXI_IC_REG_AR_QOS_CFG_VLU_5_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_0_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_0_REG (DR_REG_AXI_IC_BASE + 0x264)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_0 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_0    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_0_M  (AXI_IC_REG_AW_QOS_DLY_THR0_0_V << AXI_IC_REG_AW_QOS_DLY_THR0_0_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_0_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_0_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_1_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_1_REG (DR_REG_AXI_IC_BASE + 0x268)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_1 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_1    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_1_M  (AXI_IC_REG_AW_QOS_DLY_THR0_1_V << AXI_IC_REG_AW_QOS_DLY_THR0_1_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_1_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_1_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_2_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_2_REG (DR_REG_AXI_IC_BASE + 0x26c)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_2 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_2    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_2_M  (AXI_IC_REG_AW_QOS_DLY_THR0_2_V << AXI_IC_REG_AW_QOS_DLY_THR0_2_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_2_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_2_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_3_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_3_REG (DR_REG_AXI_IC_BASE + 0x270)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_3 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_3    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_3_M  (AXI_IC_REG_AW_QOS_DLY_THR0_3_V << AXI_IC_REG_AW_QOS_DLY_THR0_3_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_3_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_3_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_4_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_4_REG (DR_REG_AXI_IC_BASE + 0x274)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_4 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_4    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_4_M  (AXI_IC_REG_AW_QOS_DLY_THR0_4_V << AXI_IC_REG_AW_QOS_DLY_THR0_4_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_4_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_4_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR0_5_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR0_5_REG (DR_REG_AXI_IC_BASE + 0x278)
+/** AXI_IC_REG_AW_QOS_DLY_THR0_5 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the aw channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR0_5    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_5_M  (AXI_IC_REG_AW_QOS_DLY_THR0_5_V << AXI_IC_REG_AW_QOS_DLY_THR0_5_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR0_5_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR0_5_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_0_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_0_REG (DR_REG_AXI_IC_BASE + 0x27c)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_0 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_0    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_0_M  (AXI_IC_REG_AW_QOS_DLY_THR1_0_V << AXI_IC_REG_AW_QOS_DLY_THR1_0_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_0_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_0_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_1_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_1_REG (DR_REG_AXI_IC_BASE + 0x280)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_1 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_1    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_1_M  (AXI_IC_REG_AW_QOS_DLY_THR1_1_V << AXI_IC_REG_AW_QOS_DLY_THR1_1_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_1_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_1_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_2_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_2_REG (DR_REG_AXI_IC_BASE + 0x284)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_2 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_2    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_2_M  (AXI_IC_REG_AW_QOS_DLY_THR1_2_V << AXI_IC_REG_AW_QOS_DLY_THR1_2_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_2_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_2_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_3_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_3_REG (DR_REG_AXI_IC_BASE + 0x288)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_3 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_3    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_3_M  (AXI_IC_REG_AW_QOS_DLY_THR1_3_V << AXI_IC_REG_AW_QOS_DLY_THR1_3_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_3_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_3_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_4_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_4_REG (DR_REG_AXI_IC_BASE + 0x28c)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_4 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_4    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_4_M  (AXI_IC_REG_AW_QOS_DLY_THR1_4_V << AXI_IC_REG_AW_QOS_DLY_THR1_4_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_4_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_4_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR1_5_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR1_5_REG (DR_REG_AXI_IC_BASE + 0x290)
+/** AXI_IC_REG_AW_QOS_DLY_THR1_5 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the aw channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR1_5    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_5_M  (AXI_IC_REG_AW_QOS_DLY_THR1_5_V << AXI_IC_REG_AW_QOS_DLY_THR1_5_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR1_5_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR1_5_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_0_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_0_REG (DR_REG_AXI_IC_BASE + 0x294)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_0 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_0    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_0_M  (AXI_IC_REG_AW_QOS_DLY_THR2_0_V << AXI_IC_REG_AW_QOS_DLY_THR2_0_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_0_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_0_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_1_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_1_REG (DR_REG_AXI_IC_BASE + 0x298)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_1 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_1    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_1_M  (AXI_IC_REG_AW_QOS_DLY_THR2_1_V << AXI_IC_REG_AW_QOS_DLY_THR2_1_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_1_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_1_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_2_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_2_REG (DR_REG_AXI_IC_BASE + 0x29c)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_2 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_2    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_2_M  (AXI_IC_REG_AW_QOS_DLY_THR2_2_V << AXI_IC_REG_AW_QOS_DLY_THR2_2_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_2_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_2_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_3_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_3_REG (DR_REG_AXI_IC_BASE + 0x2a0)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_3 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_3    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_3_M  (AXI_IC_REG_AW_QOS_DLY_THR2_3_V << AXI_IC_REG_AW_QOS_DLY_THR2_3_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_3_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_3_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_4_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_4_REG (DR_REG_AXI_IC_BASE + 0x2a4)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_4 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_4    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_4_M  (AXI_IC_REG_AW_QOS_DLY_THR2_4_V << AXI_IC_REG_AW_QOS_DLY_THR2_4_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_4_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_4_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR2_5_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR2_5_REG (DR_REG_AXI_IC_BASE + 0x2a8)
+/** AXI_IC_REG_AW_QOS_DLY_THR2_5 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the aw channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR2_5    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_5_M  (AXI_IC_REG_AW_QOS_DLY_THR2_5_V << AXI_IC_REG_AW_QOS_DLY_THR2_5_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR2_5_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR2_5_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_0_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_0_REG (DR_REG_AXI_IC_BASE + 0x2ac)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_0 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_0    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_0_M  (AXI_IC_REG_AW_QOS_DLY_THR3_0_V << AXI_IC_REG_AW_QOS_DLY_THR3_0_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_0_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_0_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_1_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_1_REG (DR_REG_AXI_IC_BASE + 0x2b0)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_1 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_1    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_1_M  (AXI_IC_REG_AW_QOS_DLY_THR3_1_V << AXI_IC_REG_AW_QOS_DLY_THR3_1_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_1_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_1_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_2_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_2_REG (DR_REG_AXI_IC_BASE + 0x2b4)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_2 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_2    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_2_M  (AXI_IC_REG_AW_QOS_DLY_THR3_2_V << AXI_IC_REG_AW_QOS_DLY_THR3_2_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_2_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_2_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_3_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_3_REG (DR_REG_AXI_IC_BASE + 0x2b8)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_3 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_3    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_3_M  (AXI_IC_REG_AW_QOS_DLY_THR3_3_V << AXI_IC_REG_AW_QOS_DLY_THR3_3_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_3_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_3_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_4_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_4_REG (DR_REG_AXI_IC_BASE + 0x2bc)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_4 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_4    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_4_M  (AXI_IC_REG_AW_QOS_DLY_THR3_4_V << AXI_IC_REG_AW_QOS_DLY_THR3_4_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_4_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_4_S  0
+
+/** AXI_IC_AW_QOS_DLY_THR3_5_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AW_QOS_DLY_THR3_5_REG (DR_REG_AXI_IC_BASE + 0x2c0)
+/** AXI_IC_REG_AW_QOS_DLY_THR3_5 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the aw channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AW_QOS_DLY_THR3_5    0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_5_M  (AXI_IC_REG_AW_QOS_DLY_THR3_5_V << AXI_IC_REG_AW_QOS_DLY_THR3_5_S)
+#define AXI_IC_REG_AW_QOS_DLY_THR3_5_V  0x00001FFFU
+#define AXI_IC_REG_AW_QOS_DLY_THR3_5_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_0_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_0_REG (DR_REG_AXI_IC_BASE + 0x2c4)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_0 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_0    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_0_M  (AXI_IC_REG_AR_QOS_DLY_THR0_0_V << AXI_IC_REG_AR_QOS_DLY_THR0_0_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_0_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_0_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_1_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_1_REG (DR_REG_AXI_IC_BASE + 0x2c8)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_1 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_1    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_1_M  (AXI_IC_REG_AR_QOS_DLY_THR0_1_V << AXI_IC_REG_AR_QOS_DLY_THR0_1_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_1_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_1_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_2_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_2_REG (DR_REG_AXI_IC_BASE + 0x2cc)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_2 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_2    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_2_M  (AXI_IC_REG_AR_QOS_DLY_THR0_2_V << AXI_IC_REG_AR_QOS_DLY_THR0_2_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_2_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_2_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_3_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_3_REG (DR_REG_AXI_IC_BASE + 0x2d0)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_3 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_3    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_3_M  (AXI_IC_REG_AR_QOS_DLY_THR0_3_V << AXI_IC_REG_AR_QOS_DLY_THR0_3_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_3_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_3_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_4_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_4_REG (DR_REG_AXI_IC_BASE + 0x2d4)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_4 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_4    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_4_M  (AXI_IC_REG_AR_QOS_DLY_THR0_4_V << AXI_IC_REG_AR_QOS_DLY_THR0_4_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_4_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_4_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR0_5_REG register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR0_5_REG (DR_REG_AXI_IC_BASE + 0x2d8)
+/** AXI_IC_REG_AR_QOS_DLY_THR0_5 : R/W; bitpos: [12:0]; default: 32;
+ *  the first level of the ar channel delay threshold, default is 32.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR0_5    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_5_M  (AXI_IC_REG_AR_QOS_DLY_THR0_5_V << AXI_IC_REG_AR_QOS_DLY_THR0_5_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR0_5_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR0_5_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_0_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_0_REG (DR_REG_AXI_IC_BASE + 0x2dc)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_0 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_0    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_0_M  (AXI_IC_REG_AR_QOS_DLY_THR1_0_V << AXI_IC_REG_AR_QOS_DLY_THR1_0_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_0_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_0_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_1_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_1_REG (DR_REG_AXI_IC_BASE + 0x2e0)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_1 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_1    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_1_M  (AXI_IC_REG_AR_QOS_DLY_THR1_1_V << AXI_IC_REG_AR_QOS_DLY_THR1_1_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_1_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_1_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_2_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_2_REG (DR_REG_AXI_IC_BASE + 0x2e4)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_2 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_2    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_2_M  (AXI_IC_REG_AR_QOS_DLY_THR1_2_V << AXI_IC_REG_AR_QOS_DLY_THR1_2_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_2_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_2_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_3_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_3_REG (DR_REG_AXI_IC_BASE + 0x2e8)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_3 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_3    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_3_M  (AXI_IC_REG_AR_QOS_DLY_THR1_3_V << AXI_IC_REG_AR_QOS_DLY_THR1_3_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_3_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_3_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_4_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_4_REG (DR_REG_AXI_IC_BASE + 0x2ec)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_4 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_4    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_4_M  (AXI_IC_REG_AR_QOS_DLY_THR1_4_V << AXI_IC_REG_AR_QOS_DLY_THR1_4_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_4_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_4_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR1_5_REG register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR1_5_REG (DR_REG_AXI_IC_BASE + 0x2f0)
+/** AXI_IC_REG_AR_QOS_DLY_THR1_5 : R/W; bitpos: [12:0]; default: 160;
+ *  the second level of the ar channel delay threshold, default is 160.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR1_5    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_5_M  (AXI_IC_REG_AR_QOS_DLY_THR1_5_V << AXI_IC_REG_AR_QOS_DLY_THR1_5_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR1_5_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR1_5_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_0_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_0_REG (DR_REG_AXI_IC_BASE + 0x2f4)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_0 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_0    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_0_M  (AXI_IC_REG_AR_QOS_DLY_THR2_0_V << AXI_IC_REG_AR_QOS_DLY_THR2_0_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_0_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_0_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_1_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_1_REG (DR_REG_AXI_IC_BASE + 0x2f8)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_1 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_1    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_1_M  (AXI_IC_REG_AR_QOS_DLY_THR2_1_V << AXI_IC_REG_AR_QOS_DLY_THR2_1_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_1_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_1_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_2_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_2_REG (DR_REG_AXI_IC_BASE + 0x2fc)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_2 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_2    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_2_M  (AXI_IC_REG_AR_QOS_DLY_THR2_2_V << AXI_IC_REG_AR_QOS_DLY_THR2_2_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_2_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_2_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_3_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_3_REG (DR_REG_AXI_IC_BASE + 0x300)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_3 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_3    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_3_M  (AXI_IC_REG_AR_QOS_DLY_THR2_3_V << AXI_IC_REG_AR_QOS_DLY_THR2_3_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_3_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_3_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_4_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_4_REG (DR_REG_AXI_IC_BASE + 0x304)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_4 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_4    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_4_M  (AXI_IC_REG_AR_QOS_DLY_THR2_4_V << AXI_IC_REG_AR_QOS_DLY_THR2_4_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_4_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_4_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR2_5_REG register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR2_5_REG (DR_REG_AXI_IC_BASE + 0x308)
+/** AXI_IC_REG_AR_QOS_DLY_THR2_5 : R/W; bitpos: [12:0]; default: 416;
+ *  the third level of the ar channel delay threshold, default is 416.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR2_5    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_5_M  (AXI_IC_REG_AR_QOS_DLY_THR2_5_V << AXI_IC_REG_AR_QOS_DLY_THR2_5_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR2_5_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR2_5_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_0_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_0_REG (DR_REG_AXI_IC_BASE + 0x30c)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_0 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_0    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_0_M  (AXI_IC_REG_AR_QOS_DLY_THR3_0_V << AXI_IC_REG_AR_QOS_DLY_THR3_0_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_0_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_0_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_1_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_1_REG (DR_REG_AXI_IC_BASE + 0x310)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_1 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_1    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_1_M  (AXI_IC_REG_AR_QOS_DLY_THR3_1_V << AXI_IC_REG_AR_QOS_DLY_THR3_1_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_1_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_1_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_2_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_2_REG (DR_REG_AXI_IC_BASE + 0x314)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_2 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_2    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_2_M  (AXI_IC_REG_AR_QOS_DLY_THR3_2_V << AXI_IC_REG_AR_QOS_DLY_THR3_2_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_2_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_2_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_3_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_3_REG (DR_REG_AXI_IC_BASE + 0x318)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_3 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_3    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_3_M  (AXI_IC_REG_AR_QOS_DLY_THR3_3_V << AXI_IC_REG_AR_QOS_DLY_THR3_3_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_3_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_3_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_4_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_4_REG (DR_REG_AXI_IC_BASE + 0x31c)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_4 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_4    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_4_M  (AXI_IC_REG_AR_QOS_DLY_THR3_4_V << AXI_IC_REG_AR_QOS_DLY_THR3_4_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_4_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_4_S  0
+
+/** AXI_IC_AR_QOS_DLY_THR3_5_REG register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+#define AXI_IC_AR_QOS_DLY_THR3_5_REG (DR_REG_AXI_IC_BASE + 0x320)
+/** AXI_IC_REG_AR_QOS_DLY_THR3_5 : R/W; bitpos: [12:0]; default: 928;
+ *  the forth level of the ar channel delay threshold, default is 928.
+ */
+#define AXI_IC_REG_AR_QOS_DLY_THR3_5    0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_5_M  (AXI_IC_REG_AR_QOS_DLY_THR3_5_V << AXI_IC_REG_AR_QOS_DLY_THR3_5_S)
+#define AXI_IC_REG_AR_QOS_DLY_THR3_5_V  0x00001FFFU
+#define AXI_IC_REG_AR_QOS_DLY_THR3_5_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_0_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_0_REG (DR_REG_AXI_IC_BASE + 0x324)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_0 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_0    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_0_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_0_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_0_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_0_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_0_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_1_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_1_REG (DR_REG_AXI_IC_BASE + 0x328)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_1 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_1    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_1_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_1_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_1_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_1_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_1_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_2_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_2_REG (DR_REG_AXI_IC_BASE + 0x32c)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_2 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_2    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_2_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_2_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_2_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_2_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_2_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_3_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_3_REG (DR_REG_AXI_IC_BASE + 0x330)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_3 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_3    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_3_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_3_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_3_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_3_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_3_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_4_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_4_REG (DR_REG_AXI_IC_BASE + 0x334)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_4 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_4    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_4_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_4_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_4_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_4_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_4_S  0
+
+/** AXI_IC_AW_QOS_BUR_LEN_THR_5_REG register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+#define AXI_IC_AW_QOS_BUR_LEN_THR_5_REG (DR_REG_AXI_IC_BASE + 0x338)
+/** AXI_IC_REG_AW_QOS_BUR_LEN_THR_5 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of aw channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_5    0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_5_M  (AXI_IC_REG_AW_QOS_BUR_LEN_THR_5_V << AXI_IC_REG_AW_QOS_BUR_LEN_THR_5_S)
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_5_V  0x000003FFU
+#define AXI_IC_REG_AW_QOS_BUR_LEN_THR_5_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_0_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_0_REG (DR_REG_AXI_IC_BASE + 0x33c)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_0 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_0    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_0_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_0_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_0_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_0_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_0_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_1_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_1_REG (DR_REG_AXI_IC_BASE + 0x340)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_1 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_1    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_1_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_1_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_1_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_1_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_1_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_2_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_2_REG (DR_REG_AXI_IC_BASE + 0x344)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_2 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_2    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_2_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_2_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_2_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_2_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_2_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_3_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_3_REG (DR_REG_AXI_IC_BASE + 0x348)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_3 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_3    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_3_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_3_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_3_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_3_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_3_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_4_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_4_REG (DR_REG_AXI_IC_BASE + 0x34c)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_4 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_4    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_4_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_4_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_4_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_4_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_4_S  0
+
+/** AXI_IC_AR_QOS_BUR_LEN_THR_5_REG register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+#define AXI_IC_AR_QOS_BUR_LEN_THR_5_REG (DR_REG_AXI_IC_BASE + 0x350)
+/** AXI_IC_REG_AR_QOS_BUR_LEN_THR_5 : R/W; bitpos: [9:0]; default: 64;
+ *  limit the starting token value of ar channel to turn on transmission, default value
+ *  is 64, 0 means no limit.
+ */
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_5    0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_5_M  (AXI_IC_REG_AR_QOS_BUR_LEN_THR_5_V << AXI_IC_REG_AR_QOS_BUR_LEN_THR_5_S)
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_5_V  0x000003FFU
+#define AXI_IC_REG_AR_QOS_BUR_LEN_THR_5_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_0_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_0_REG (DR_REG_AXI_IC_BASE + 0x354)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_0 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_0    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_0_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_0_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_0_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_0_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_0_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_1_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_1_REG (DR_REG_AXI_IC_BASE + 0x358)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_1 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_1    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_1_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_1_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_1_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_1_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_1_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_2_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_2_REG (DR_REG_AXI_IC_BASE + 0x35c)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_2 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_2    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_2_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_2_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_2_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_2_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_2_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_3_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_3_REG (DR_REG_AXI_IC_BASE + 0x360)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_3 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_3    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_3_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_3_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_3_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_3_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_3_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_4_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_4_REG (DR_REG_AXI_IC_BASE + 0x364)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_4 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_4    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_4_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_4_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_4_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_4_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_4_S  0
+
+/** AXI_IC_AW_QOS_DBG_TK_THR_5_REG register
+ *  Config the debug smple interval in aw channel.
+ */
+#define AXI_IC_AW_QOS_DBG_TK_THR_5_REG (DR_REG_AXI_IC_BASE + 0x368)
+/** AXI_IC_REG_AW_QOS_DBG_TK_THR_5 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_5    0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_5_M  (AXI_IC_REG_AW_QOS_DBG_TK_THR_5_V << AXI_IC_REG_AW_QOS_DBG_TK_THR_5_S)
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_5_V  0x000000FFU
+#define AXI_IC_REG_AW_QOS_DBG_TK_THR_5_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_0_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_0_REG (DR_REG_AXI_IC_BASE + 0x36c)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_0 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_0    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_0_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_0_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_0_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_0_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_0_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_1_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_1_REG (DR_REG_AXI_IC_BASE + 0x370)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_1 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_1    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_1_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_1_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_1_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_1_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_1_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_2_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_2_REG (DR_REG_AXI_IC_BASE + 0x374)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_2 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_2    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_2_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_2_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_2_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_2_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_2_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_3_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_3_REG (DR_REG_AXI_IC_BASE + 0x378)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_3 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_3    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_3_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_3_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_3_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_3_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_3_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_4_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_4_REG (DR_REG_AXI_IC_BASE + 0x37c)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_4 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_4    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_4_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_4_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_4_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_4_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_4_S  0
+
+/** AXI_IC_AR_QOS_DBG_TK_THR_5_REG register
+ *  Config the debug smple interval in ar channel.
+ */
+#define AXI_IC_AR_QOS_DBG_TK_THR_5_REG (DR_REG_AXI_IC_BASE + 0x380)
+/** AXI_IC_REG_AR_QOS_DBG_TK_THR_5 : R/W; bitpos: [7:0]; default: 16;
+ *  limit the debug sample interval, default value is 16
+ */
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_5    0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_5_M  (AXI_IC_REG_AR_QOS_DBG_TK_THR_5_V << AXI_IC_REG_AR_QOS_DBG_TK_THR_5_S)
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_5_V  0x000000FFU
+#define AXI_IC_REG_AR_QOS_DBG_TK_THR_5_S  0
+
+/** AXI_IC_MAX_OST_AW_S_0_REG register
+ *  Config the max outstanding num in current slave write port.
+ */
+#define AXI_IC_MAX_OST_AW_S_0_REG (DR_REG_AXI_IC_BASE + 0x384)
+/** AXI_IC_REG_MAX_OST_AW_S_0 : R/W; bitpos: [5:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15, max is 32.
+ */
+#define AXI_IC_REG_MAX_OST_AW_S_0    0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_0_M  (AXI_IC_REG_MAX_OST_AW_S_0_V << AXI_IC_REG_MAX_OST_AW_S_0_S)
+#define AXI_IC_REG_MAX_OST_AW_S_0_V  0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_0_S  0
+
+/** AXI_IC_MAX_OST_AW_S_1_REG register
+ *  Config the max outstanding num in current slave write port.
+ */
+#define AXI_IC_MAX_OST_AW_S_1_REG (DR_REG_AXI_IC_BASE + 0x388)
+/** AXI_IC_REG_MAX_OST_AW_S_1 : R/W; bitpos: [5:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15, max is 32.
+ */
+#define AXI_IC_REG_MAX_OST_AW_S_1    0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_1_M  (AXI_IC_REG_MAX_OST_AW_S_1_V << AXI_IC_REG_MAX_OST_AW_S_1_S)
+#define AXI_IC_REG_MAX_OST_AW_S_1_V  0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_1_S  0
+
+/** AXI_IC_MAX_OST_AW_S_2_REG register
+ *  Config the max outstanding num in current slave write port.
+ */
+#define AXI_IC_MAX_OST_AW_S_2_REG (DR_REG_AXI_IC_BASE + 0x38c)
+/** AXI_IC_REG_MAX_OST_AW_S_2 : R/W; bitpos: [5:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15, max is 32.
+ */
+#define AXI_IC_REG_MAX_OST_AW_S_2    0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_2_M  (AXI_IC_REG_MAX_OST_AW_S_2_V << AXI_IC_REG_MAX_OST_AW_S_2_S)
+#define AXI_IC_REG_MAX_OST_AW_S_2_V  0x0000003FU
+#define AXI_IC_REG_MAX_OST_AW_S_2_S  0
+
+/** AXI_IC_MAX_OST_AR_S_0_REG register
+ *  Config the max outstanding num in current slave read port.
+ */
+#define AXI_IC_MAX_OST_AR_S_0_REG (DR_REG_AXI_IC_BASE + 0x390)
+/** AXI_IC_REG_MAX_OST_AR_S_0 : R/W; bitpos: [7:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15
+ */
+#define AXI_IC_REG_MAX_OST_AR_S_0    0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_0_M  (AXI_IC_REG_MAX_OST_AR_S_0_V << AXI_IC_REG_MAX_OST_AR_S_0_S)
+#define AXI_IC_REG_MAX_OST_AR_S_0_V  0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_0_S  0
+
+/** AXI_IC_MAX_OST_AR_S_1_REG register
+ *  Config the max outstanding num in current slave read port.
+ */
+#define AXI_IC_MAX_OST_AR_S_1_REG (DR_REG_AXI_IC_BASE + 0x394)
+/** AXI_IC_REG_MAX_OST_AR_S_1 : R/W; bitpos: [7:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15
+ */
+#define AXI_IC_REG_MAX_OST_AR_S_1    0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_1_M  (AXI_IC_REG_MAX_OST_AR_S_1_V << AXI_IC_REG_MAX_OST_AR_S_1_S)
+#define AXI_IC_REG_MAX_OST_AR_S_1_V  0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_1_S  0
+
+/** AXI_IC_MAX_OST_AR_S_2_REG register
+ *  Config the max outstanding num in current slave read port.
+ */
+#define AXI_IC_MAX_OST_AR_S_2_REG (DR_REG_AXI_IC_BASE + 0x398)
+/** AXI_IC_REG_MAX_OST_AR_S_2 : R/W; bitpos: [7:0]; default: 15;
+ *  limit the number of outstanding for slave port, default value is 15
+ */
+#define AXI_IC_REG_MAX_OST_AR_S_2    0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_2_M  (AXI_IC_REG_MAX_OST_AR_S_2_V << AXI_IC_REG_MAX_OST_AR_S_2_S)
+#define AXI_IC_REG_MAX_OST_AR_S_2_V  0x000000FFU
+#define AXI_IC_REG_MAX_OST_AR_S_2_S  0
+
+/** AXI_IC_AW_QOS_PEAK_RATE_MODE_REG register
+ *  Config the aw channel token store mode in peak rate enable.
+ */
+#define AXI_IC_AW_QOS_PEAK_RATE_MODE_REG (DR_REG_AXI_IC_BASE + 0x39c)
+/** AXI_IC_REG_AW_QOS_PEAK_RATE_MODE : R/W; bitpos: [5:0]; default: 0;
+ *  peak rate, to control the aw channel request token num more than 1, default 0.
+ */
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_MODE    0x0000003FU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_MODE_M  (AXI_IC_REG_AW_QOS_PEAK_RATE_MODE_V << AXI_IC_REG_AW_QOS_PEAK_RATE_MODE_S)
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_MODE_V  0x0000003FU
+#define AXI_IC_REG_AW_QOS_PEAK_RATE_MODE_S  0
+
+/** AXI_IC_AR_QOS_PEAK_RATE_MODE_REG register
+ *  Config the ar channel token store mode in peak rate enable.
+ */
+#define AXI_IC_AR_QOS_PEAK_RATE_MODE_REG (DR_REG_AXI_IC_BASE + 0x3a0)
+/** AXI_IC_REG_AR_QOS_PEAK_RATE_MODE : R/W; bitpos: [5:0]; default: 0;
+ *  peak rate, to control the ar channel request token num  more than 1, default 0.
+ */
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_MODE    0x0000003FU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_MODE_M  (AXI_IC_REG_AR_QOS_PEAK_RATE_MODE_V << AXI_IC_REG_AR_QOS_PEAK_RATE_MODE_S)
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_MODE_V  0x0000003FU
+#define AXI_IC_REG_AR_QOS_PEAK_RATE_MODE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/icm_sys_axi_ic_struct.h b/components/soc/esp32s31/register/soc/icm_sys_axi_ic_struct.h
new file mode 100644
index 00000000000..d2af77cacb9
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/icm_sys_axi_ic_struct.h
@@ -0,0 +1,3432 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: date */
+/** Type of date register
+ *  Version Control Register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [31:0]; default: 23050900;
+         *  Version Control Register
+         */
+        uint32_t reg_date:32;
+    };
+    uint32_t val;
+} axi_ic_date_reg_t;
+
+
+/** Group: clk_en */
+/** Type of clk_en register
+ *  AXI IC reg clk enable config register
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  value 1 enable clk, value 0 disable clk, default 1
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} axi_ic_clk_en_reg_t;
+
+
+/** Group: interrupt */
+/** Type of interrupt_raw register
+ *  Interrupt raw of AXI IC  Interrupt register.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
+         *  Interrupt raw of reg_dec_failure_int_raw
+         */
+        uint32_t reg_dec_failure_int_raw:1;
+        /** reg_timeout_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
+         *  Interrupt raw of reg_timeout_int_raw
+         */
+        uint32_t reg_timeout_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_interrupt_raw_reg_t;
+
+/** Type of interrupt_clr register
+ *  Interrupt clear of AXI IC  Interrupt register.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_int_clr : WT; bitpos: [0]; default: 0;
+         *  Interrupt clr of reg_dec_failure_int_clr
+         */
+        uint32_t reg_dec_failure_int_clr:1;
+        /** reg_timeout_int_clr : WT; bitpos: [1]; default: 0;
+         *  Interrupt clr of reg_timeout_int_clr
+         */
+        uint32_t reg_timeout_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_interrupt_clr_reg_t;
+
+/** Type of interrupt_ena register
+ *  Interrupt enable of AXI IC  Interrupt register.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Interrupt ena of reg_dec_failure_int_ena
+         */
+        uint32_t reg_dec_failure_int_ena:1;
+        /** reg_timeout_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Interrupt ena of reg_timeout_int_ena
+         */
+        uint32_t reg_timeout_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_interrupt_ena_reg_t;
+
+/** Type of interrupt_st register
+ *  AXI IC  Interrupt register.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_int_st : RO; bitpos: [0]; default: 0;
+         *  Interrupt st of reg_dec_failure_int_st
+         */
+        uint32_t reg_dec_failure_int_st:1;
+        /** reg_timeout_int_st : RO; bitpos: [1]; default: 0;
+         *  Interrupt st of reg_timeout_int_st
+         */
+        uint32_t reg_timeout_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_interrupt_st_reg_t;
+
+
+/** Group: timeout_max_cnt */
+/** Type of timeout_max_cnt register
+ *  AXI IC core AW or AR channel timeout counter maximum value.
+ */
+typedef union {
+    struct {
+        /** reg_timeout_max_cnt : R/W; bitpos: [31:0]; default: 4294967295;
+         *  AXI IC core AW or AR channel timeout counter maximum value.
+         */
+        uint32_t reg_timeout_max_cnt:32;
+    };
+    uint32_t val;
+} axi_ic_timeout_max_cnt_reg_t;
+
+
+/** Group: timeout_info */
+/** Type of timeout_info register
+ *  AXI IC core AW or AR channel timeout information.
+ */
+typedef union {
+    struct {
+        /** reg_timeout_slave : RO; bitpos: [2:0]; default: 0;
+         *  bit[i] is 1 means slave[i] occurs timeout.
+         */
+        uint32_t reg_timeout_slave:3;
+        /** reg_timeout_id : RO; bitpos: [9:3]; default: 0;
+         *  (master id, awid)
+         */
+        uint32_t reg_timeout_id:7;
+        /** reg_timeout_wr : RO; bitpos: [10]; default: 0;
+         *  1 indicates write operation, 0 indicates read operation.
+         */
+        uint32_t reg_timeout_wr:1;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} axi_ic_timeout_info_reg_t;
+
+
+/** Group: dec_failure_info */
+/** Type of dec_failure_info register
+ *  Default slave information get control and status.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_read_first : R/W; bitpos: [0]; default: 0;
+         *  Decoder failure recorded control. 1 means record read failure first, else write
+         *  failure first.
+         */
+        uint32_t reg_dec_failure_read_first:1;
+        /** reg_dec_failure_valid : RO; bitpos: [1]; default: 0;
+         *  Decoder failure valid control.
+         */
+        uint32_t reg_dec_failure_valid:1;
+        /** reg_dec_failure_type : RO; bitpos: [2]; default: 0;
+         *  Decoder failure type control. 0 means ar failure, 1 means aw failure.
+         */
+        uint32_t reg_dec_failure_type:1;
+        /** reg_dec_failure_cause : RO; bitpos: [5:3]; default: 0;
+         *  bit[0] is 0 means to access the mapped slave address, and is 1 means to access the
+         *  unmapped slave address. bit[1] is 0 means to access the visible slave, and is 1
+         *  means to access the invisible slave. bit[2] is 0 means to access the secure slave,
+         *  and is 1 means to access the non-secure slave.
+         */
+        uint32_t reg_dec_failure_cause:3;
+        /** reg_dec_failure_mst_id : RO; bitpos: [12:6]; default: 0;
+         *  (master id, awid/arid)
+         */
+        uint32_t reg_dec_failure_mst_id:7;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_dec_failure_info_reg_t;
+
+
+/** Group: qos_debug_mst_sel */
+/** Type of qos_debug_mst_sel register
+ *  Config the select for debug master.
+ */
+typedef union {
+    struct {
+        /** reg_qos_debug_mst_sel : R/W; bitpos: [3:0]; default: 0;
+         *  select which master will be debug.
+         */
+        uint32_t reg_qos_debug_mst_sel:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_qos_debug_mst_sel_reg_t;
+
+
+/** Group: dec_failure_addr */
+/** Type of dec_failure_addr register
+ *  Record the address for AXI Master access Default slave.
+ */
+typedef union {
+    struct {
+        /** reg_dec_failure_addr : RO; bitpos: [31:0]; default: 0;
+         *  AXI IC core AW or AR channel decoder failure address.
+         */
+        uint32_t reg_dec_failure_addr:32;
+    };
+    uint32_t val;
+} axi_ic_dec_failure_addr_reg_t;
+
+
+/** Group: reg_slave_is_secure */
+/** Type of reg_slave_is_secure register
+ *  AXI IC core slave security control.
+ */
+typedef union {
+    struct {
+        /** reg_slave_is_secure_0 : R/W; bitpos: [0]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_slave_is_secure_0:1;
+        /** reg_slave_is_secure_1 : R/W; bitpos: [1]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_slave_is_secure_1:1;
+        /** reg_slave_is_secure_2 : R/W; bitpos: [2]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_slave_is_secure_2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_ic_reg_slave_is_secure_reg_t;
+
+
+/** Group: slave_security_override */
+/** Type of slave_security_override register
+ *  The control signal whether slave security is overridden by software.
+ */
+typedef union {
+    struct {
+        /** reg_slave_security_override_0 : R/W; bitpos: [0]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_slave_security_override_0:1;
+        /** reg_slave_security_override_1 : R/W; bitpos: [1]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_slave_security_override_1:1;
+        /** reg_slave_security_override_2 : R/W; bitpos: [2]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_slave_security_override_2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_ic_slave_security_override_reg_t;
+
+
+/** Group: master_is_secure */
+/** Type of master_is_secure register
+ *  AXI IC core master security control.
+ */
+typedef union {
+    struct {
+        /** reg_master_is_secure_0 : R/W; bitpos: [0]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_0:1;
+        /** reg_master_is_secure_1 : R/W; bitpos: [1]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_1:1;
+        /** reg_master_is_secure_2 : R/W; bitpos: [2]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_2:1;
+        /** reg_master_is_secure_3 : R/W; bitpos: [3]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_3:1;
+        /** reg_master_is_secure_4 : R/W; bitpos: [4]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_4:1;
+        /** reg_master_is_secure_5 : R/W; bitpos: [5]; default: 0;
+         *  1 means safe and 0 means not safe.
+         */
+        uint32_t reg_master_is_secure_5:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_master_is_secure_reg_t;
+
+
+/** Group: master_security_override */
+/** Type of master_security_override register
+ *  The control signal whether master security is overridden by software.
+ */
+typedef union {
+    struct {
+        /** reg_master_security_override_0 : R/W; bitpos: [0]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_0:1;
+        /** reg_master_security_override_1 : R/W; bitpos: [1]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_1:1;
+        /** reg_master_security_override_2 : R/W; bitpos: [2]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_2:1;
+        /** reg_master_security_override_3 : R/W; bitpos: [3]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_3:1;
+        /** reg_master_security_override_4 : R/W; bitpos: [4]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_4:1;
+        /** reg_master_security_override_5 : R/W; bitpos: [5]; default: 0;
+         *  0 means not overridden, and 1 means overridden.
+         */
+        uint32_t reg_master_security_override_5:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_master_security_override_reg_t;
+
+
+/** Group: aw_qos_value */
+/** Type of aw_qos_value_0 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_0 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_0_reg_t;
+
+/** Type of aw_qos_value_1 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_1 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_1_reg_t;
+
+/** Type of aw_qos_value_2 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_2 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_2_reg_t;
+
+/** Type of aw_qos_value_3 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_3 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_3_reg_t;
+
+/** Type of aw_qos_value_4 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_4 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_4_reg_t;
+
+/** Type of aw_qos_value_5 register
+ *  AXI IC core AW QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_value_5 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AW QOS value specified by software.
+         */
+        uint32_t reg_aw_qos_value_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_value_5_reg_t;
+
+
+/** Group: ar_qos_value */
+/** Type of ar_qos_value_0 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_0 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_0_reg_t;
+
+/** Type of ar_qos_value_1 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_1 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_1_reg_t;
+
+/** Type of ar_qos_value_2 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_2 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_2_reg_t;
+
+/** Type of ar_qos_value_3 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_3 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_3_reg_t;
+
+/** Type of ar_qos_value_4 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_4 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_4_reg_t;
+
+/** Type of ar_qos_value_5 register
+ *  AXI IC core AR QOS value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_value_5 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core AR QOS value specified by software.
+         */
+        uint32_t reg_ar_qos_value_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_value_5_reg_t;
+
+
+/** Group: b_prior_value */
+/** Type of b_prior_value_0 register
+ *  AXI IC core B priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_b_prior_value_0 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core B priority value specified by software.
+         */
+        uint32_t reg_b_prior_value_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_b_prior_value_0_reg_t;
+
+/** Type of b_prior_value_1 register
+ *  AXI IC core B priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_b_prior_value_1 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core B priority value specified by software.
+         */
+        uint32_t reg_b_prior_value_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_b_prior_value_1_reg_t;
+
+/** Type of b_prior_value_2 register
+ *  AXI IC core B priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_b_prior_value_2 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core B priority value specified by software.
+         */
+        uint32_t reg_b_prior_value_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_b_prior_value_2_reg_t;
+
+
+/** Group: r_prior_value */
+/** Type of r_prior_value_0 register
+ *  AXI IC core R priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_r_prior_value_0 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core R priority value specified by software.
+         */
+        uint32_t reg_r_prior_value_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_r_prior_value_0_reg_t;
+
+/** Type of r_prior_value_1 register
+ *  AXI IC core R priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_r_prior_value_1 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core R priority value specified by software.
+         */
+        uint32_t reg_r_prior_value_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_r_prior_value_1_reg_t;
+
+/** Type of r_prior_value_2 register
+ *  AXI IC core R priority value specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_r_prior_value_2 : R/W; bitpos: [3:0]; default: 0;
+         *  AXI IC core R priority value specified by software.
+         */
+        uint32_t reg_r_prior_value_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_r_prior_value_2_reg_t;
+
+
+/** Group: aw_qos_sel */
+/** Type of aw_qos_sel_0 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_0 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_0:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_0_reg_t;
+
+/** Type of aw_qos_sel_1 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_1 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_1:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_1_reg_t;
+
+/** Type of aw_qos_sel_2 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_2 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_2:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_2_reg_t;
+
+/** Type of aw_qos_sel_3 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_3 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_3:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_3_reg_t;
+
+/** Type of aw_qos_sel_4 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_4 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_4:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_4_reg_t;
+
+/** Type of aw_qos_sel_5 register
+ *  AXI IC core AW QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_sel_5 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_aw_qos_sel_5:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_sel_5_reg_t;
+
+
+/** Group: ar_qos_sel */
+/** Type of ar_qos_sel_0 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_0 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_0:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_0_reg_t;
+
+/** Type of ar_qos_sel_1 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_1 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_1:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_1_reg_t;
+
+/** Type of ar_qos_sel_2 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_2 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_2:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_2_reg_t;
+
+/** Type of ar_qos_sel_3 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_3 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_3:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_3_reg_t;
+
+/** Type of ar_qos_sel_4 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_4 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_4:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_4_reg_t;
+
+/** Type of ar_qos_sel_5 register
+ *  AXI IC core AR QOS select signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_sel_5 : R/W; bitpos: [1:0]; default: 0;
+         *  2'b00 selects the original QOS value, 2'b01 selects the QOS value set by the
+         *  software, 2'b10 selects the QOS value set by the QOS regulator.
+         */
+        uint32_t reg_ar_qos_sel_5:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_sel_5_reg_t;
+
+
+/** Group: aw_qos_recovery */
+/** Type of aw_qos_recovery register
+ *  AXI IC core AW QOS recovery signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_recovery_0 : R/W; bitpos: [0]; default: 0;
+         *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_aw_qos_recovery_0:1;
+        /** reg_aw_qos_recovery_1 : R/W; bitpos: [1]; default: 0;
+         *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_aw_qos_recovery_1:1;
+        /** reg_aw_qos_recovery_2 : R/W; bitpos: [2]; default: 0;
+         *  Use QOS_COPY in SI_IF AW payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_aw_qos_recovery_2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_recovery_reg_t;
+
+
+/** Group: ar_qos_recovery */
+/** Type of ar_qos_recovery register
+ *  AXI IC core AR QOS recovery signal specified by software.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_recovery_0 : R/W; bitpos: [0]; default: 0;
+         *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_ar_qos_recovery_0:1;
+        /** reg_ar_qos_recovery_1 : R/W; bitpos: [1]; default: 0;
+         *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_ar_qos_recovery_1:1;
+        /** reg_ar_qos_recovery_2 : R/W; bitpos: [2]; default: 0;
+         *  Use QOS_COPY in SI_IF AR payload when it is asserted, otherwise use QOS_NEW (from
+         *  QOS regulator or software).
+         */
+        uint32_t reg_ar_qos_recovery_2:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_recovery_reg_t;
+
+
+/** Group: aw_qos_id_mask */
+/** Type of aw_qos_id_mask_0 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_0 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_0_reg_t;
+
+/** Type of aw_qos_id_mask_1 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_1 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_1_reg_t;
+
+/** Type of aw_qos_id_mask_2 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_2 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_2_reg_t;
+
+/** Type of aw_qos_id_mask_3 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_3 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_3_reg_t;
+
+/** Type of aw_qos_id_mask_4 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_4 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_4_reg_t;
+
+/** Type of aw_qos_id_mask_5 register
+ *  Config the aw channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_mask_5 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_mask_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_mask_5_reg_t;
+
+
+/** Group: ar_qos_id_mask */
+/** Type of ar_qos_id_mask_0 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_0 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_0_reg_t;
+
+/** Type of ar_qos_id_mask_1 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_1 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_1_reg_t;
+
+/** Type of ar_qos_id_mask_2 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_2 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_2_reg_t;
+
+/** Type of ar_qos_id_mask_3 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_3 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_3_reg_t;
+
+/** Type of ar_qos_id_mask_4 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_4 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_4_reg_t;
+
+/** Type of ar_qos_id_mask_5 register
+ *  Config the ar channel id mask for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_mask_5 : R/W; bitpos: [3:0]; default: 15;
+         *  mask for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_mask_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_mask_5_reg_t;
+
+
+/** Group: aw_qos_id_filter */
+/** Type of aw_qos_id_filter_0 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_0 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_0_reg_t;
+
+/** Type of aw_qos_id_filter_1 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_1 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_1_reg_t;
+
+/** Type of aw_qos_id_filter_2 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_2 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_2_reg_t;
+
+/** Type of aw_qos_id_filter_3 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_3 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_3_reg_t;
+
+/** Type of aw_qos_id_filter_4 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_4 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_4_reg_t;
+
+/** Type of aw_qos_id_filter_5 register
+ *  Config the aw channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_id_filter_5 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of aw channel id.
+         */
+        uint32_t reg_aw_qos_id_filter_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_id_filter_5_reg_t;
+
+
+/** Group: ar_qos_id_filter */
+/** Type of ar_qos_id_filter_0 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_0 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_0:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_0_reg_t;
+
+/** Type of ar_qos_id_filter_1 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_1 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_1:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_1_reg_t;
+
+/** Type of ar_qos_id_filter_2 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_2 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_2:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_2_reg_t;
+
+/** Type of ar_qos_id_filter_3 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_3 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_3:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_3_reg_t;
+
+/** Type of ar_qos_id_filter_4 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_4 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_4:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_4_reg_t;
+
+/** Type of ar_qos_id_filter_5 register
+ *  Config the ar channel id filter for id filter function.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_id_filter_5 : R/W; bitpos: [3:0]; default: 15;
+         *  filter for enable qos of ar channel id.
+         */
+        uint32_t reg_ar_qos_id_filter_5:4;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_id_filter_5_reg_t;
+
+
+/** Group: aw_qos_ctrl_cfg */
+/** Type of aw_qos_ctrl_cfg_0 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_0 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_0:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_0_reg_t;
+
+/** Type of aw_qos_ctrl_cfg_1 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_1 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_1:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_1_reg_t;
+
+/** Type of aw_qos_ctrl_cfg_2 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_2 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_2:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_2_reg_t;
+
+/** Type of aw_qos_ctrl_cfg_3 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_3 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_3:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_3_reg_t;
+
+/** Type of aw_qos_ctrl_cfg_4 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_4 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_4:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_4_reg_t;
+
+/** Type of aw_qos_ctrl_cfg_5 register
+ *  Config the QOS Regulator aw module control.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_ctrl_cfg_5 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_aw_qos_ctrl_cfg_5:32;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_ctrl_cfg_5_reg_t;
+
+
+/** Group: ar_qos_ctrl_cfg */
+/** Type of ar_qos_ctrl_cfg_0 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_0 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_0:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_0_reg_t;
+
+/** Type of ar_qos_ctrl_cfg_1 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_1 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_1:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_1_reg_t;
+
+/** Type of ar_qos_ctrl_cfg_2 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_2 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_2:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_2_reg_t;
+
+/** Type of ar_qos_ctrl_cfg_3 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_3 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_3:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_3_reg_t;
+
+/** Type of ar_qos_ctrl_cfg_4 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_4 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_4:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_4_reg_t;
+
+/** Type of ar_qos_ctrl_cfg_5 register
+ *  Config the QOS Regulator ar module control.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_ctrl_cfg_5 : R/W; bitpos: [31:0]; default: 8208;
+         *  bit[0] enable channel qos, bit[1] enable debug, bit[7:4] mode of vlu regulate,
+         *  bit[15:8] step of dly thr, bit[16] dly cnt rst.
+         */
+        uint32_t reg_ar_qos_ctrl_cfg_5:32;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_ctrl_cfg_5_reg_t;
+
+
+/** Group: aw_qos_trans_rate */
+/** Type of aw_qos_trans_rate_0 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_0 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_0_reg_t;
+
+/** Type of aw_qos_trans_rate_1 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_1 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_1_reg_t;
+
+/** Type of aw_qos_trans_rate_2 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_2 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_2_reg_t;
+
+/** Type of aw_qos_trans_rate_3 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_3 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_3_reg_t;
+
+/** Type of aw_qos_trans_rate_4 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_4 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_4:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_4_reg_t;
+
+/** Type of aw_qos_trans_rate_5 register
+ *  Config the Current Master Write bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_trans_rate_5 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the aw channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_aw_qos_trans_rate_5:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_trans_rate_5_reg_t;
+
+
+/** Group: ar_qos_trans_rate */
+/** Type of ar_qos_trans_rate_0 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_0 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_0_reg_t;
+
+/** Type of ar_qos_trans_rate_1 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_1 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_1_reg_t;
+
+/** Type of ar_qos_trans_rate_2 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_2 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_2_reg_t;
+
+/** Type of ar_qos_trans_rate_3 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_3 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_3_reg_t;
+
+/** Type of ar_qos_trans_rate_4 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_4 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_4:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_4_reg_t;
+
+/** Type of ar_qos_trans_rate_5 register
+ *  Config the Current Master Read bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_trans_rate_5 : R/W; bitpos: [15:0]; default: 12296;
+         *  transaction rate, to control the ar channel bandwidth, default 8 cycles 3 tokens.
+         */
+        uint32_t reg_ar_qos_trans_rate_5:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_trans_rate_5_reg_t;
+
+
+/** Group: aw_qos_peak_rate */
+/** Type of aw_qos_peak_rate_0 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_0 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_0_reg_t;
+
+/** Type of aw_qos_peak_rate_1 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_1 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_1_reg_t;
+
+/** Type of aw_qos_peak_rate_2 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_2 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_2_reg_t;
+
+/** Type of aw_qos_peak_rate_3 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_3 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_3_reg_t;
+
+/** Type of aw_qos_peak_rate_4 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_4 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_4_reg_t;
+
+/** Type of aw_qos_peak_rate_5 register
+ *  Config the Current Master Write Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_5 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the aw channel request issue rate, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_5_reg_t;
+
+
+/** Group: ar_qos_peak_rate */
+/** Type of ar_qos_peak_rate_0 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_0 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_0_reg_t;
+
+/** Type of ar_qos_peak_rate_1 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_1 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_1_reg_t;
+
+/** Type of ar_qos_peak_rate_2 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_2 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_2_reg_t;
+
+/** Type of ar_qos_peak_rate_3 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_3 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_3_reg_t;
+
+/** Type of ar_qos_peak_rate_4 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_4 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_4_reg_t;
+
+/** Type of ar_qos_peak_rate_5 register
+ *  Config the Current Master Read Peak bandwidth.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_5 : R/W; bitpos: [7:0]; default: 0;
+         *  peak rate, to control the ar channel request issue rate, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_5_reg_t;
+
+
+/** Group: aw_qos_burstiness */
+/** Type of aw_qos_burstiness_0 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_0 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_0:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_0_reg_t;
+
+/** Type of aw_qos_burstiness_1 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_1 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_1:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_1_reg_t;
+
+/** Type of aw_qos_burstiness_2 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_2 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_2:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_2_reg_t;
+
+/** Type of aw_qos_burstiness_3 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_3 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_3:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_3_reg_t;
+
+/** Type of aw_qos_burstiness_4 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_4 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_4:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_4_reg_t;
+
+/** Type of aw_qos_burstiness_5 register
+ *  The Depth for AW channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_burstiness_5 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the aw channel token, default 128 tokens.
+         */
+        uint32_t reg_aw_qos_burstiness_5:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_burstiness_5_reg_t;
+
+
+/** Group: ar_qos_burstiness */
+/** Type of ar_qos_burstiness_0 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_0 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_0:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_0_reg_t;
+
+/** Type of ar_qos_burstiness_1 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_1 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_1:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_1_reg_t;
+
+/** Type of ar_qos_burstiness_2 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_2 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_2:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_2_reg_t;
+
+/** Type of ar_qos_burstiness_3 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_3 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_3:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_3_reg_t;
+
+/** Type of ar_qos_burstiness_4 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_4 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_4:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_4_reg_t;
+
+/** Type of ar_qos_burstiness_5 register
+ *  The Depth for AR channel TOKEN Busrtiness.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_burstiness_5 : R/W; bitpos: [11:0]; default: 128;
+         *  the maximum numbers of the ar channel token, default 128 tokens.
+         */
+        uint32_t reg_ar_qos_burstiness_5:12;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_burstiness_5_reg_t;
+
+
+/** Group: aw_qos_cfg_vlu */
+/** Type of aw_qos_cfg_vlu_0 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_0 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_0_reg_t;
+
+/** Type of aw_qos_cfg_vlu_1 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_1 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_1_reg_t;
+
+/** Type of aw_qos_cfg_vlu_2 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_2 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_2_reg_t;
+
+/** Type of aw_qos_cfg_vlu_3 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_3 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_3_reg_t;
+
+/** Type of aw_qos_cfg_vlu_4 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_4 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_4:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_4_reg_t;
+
+/** Type of aw_qos_cfg_vlu_5 register
+ *  Config the QOS Priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_cfg_vlu_5 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the aw channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_aw_qos_cfg_vlu_5:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_cfg_vlu_5_reg_t;
+
+
+/** Group: ar_qos_cfg_vlu */
+/** Type of ar_qos_cfg_vlu_0 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_0 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_0:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_0_reg_t;
+
+/** Type of ar_qos_cfg_vlu_1 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_1 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_1:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_1_reg_t;
+
+/** Type of ar_qos_cfg_vlu_2 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_2 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_2:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_2_reg_t;
+
+/** Type of ar_qos_cfg_vlu_3 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_3 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_3:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_3_reg_t;
+
+/** Type of ar_qos_cfg_vlu_4 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_4 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_4:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_4_reg_t;
+
+/** Type of ar_qos_cfg_vlu_5 register
+ *  Config the QOS Priority in AR channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_cfg_vlu_5 : R/W; bitpos: [15:0]; default: 55906;
+         *  the four level of the ar channel qos priority, default is 2,6,10,13
+         */
+        uint32_t reg_ar_qos_cfg_vlu_5:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_cfg_vlu_5_reg_t;
+
+
+/** Group: aw_qos_dly_thr0 */
+/** Type of aw_qos_dly_thr0_0 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_0 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_0_reg_t;
+
+/** Type of aw_qos_dly_thr0_1 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_1 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_1_reg_t;
+
+/** Type of aw_qos_dly_thr0_2 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_2 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_2_reg_t;
+
+/** Type of aw_qos_dly_thr0_3 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_3 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_3_reg_t;
+
+/** Type of aw_qos_dly_thr0_4 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_4 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_4_reg_t;
+
+/** Type of aw_qos_dly_thr0_5 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr0_5 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the aw channel delay threshold, default is 32.
+         */
+        uint32_t reg_aw_qos_dly_thr0_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr0_5_reg_t;
+
+
+/** Group: aw_qos_dly_thr1 */
+/** Type of aw_qos_dly_thr1_0 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_0 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_0_reg_t;
+
+/** Type of aw_qos_dly_thr1_1 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_1 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_1_reg_t;
+
+/** Type of aw_qos_dly_thr1_2 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_2 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_2_reg_t;
+
+/** Type of aw_qos_dly_thr1_3 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_3 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_3_reg_t;
+
+/** Type of aw_qos_dly_thr1_4 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_4 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_4_reg_t;
+
+/** Type of aw_qos_dly_thr1_5 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr1_5 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the aw channel delay threshold, default is 160.
+         */
+        uint32_t reg_aw_qos_dly_thr1_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr1_5_reg_t;
+
+
+/** Group: aw_qos_dly_thr2 */
+/** Type of aw_qos_dly_thr2_0 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_0 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_0_reg_t;
+
+/** Type of aw_qos_dly_thr2_1 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_1 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_1_reg_t;
+
+/** Type of aw_qos_dly_thr2_2 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_2 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_2_reg_t;
+
+/** Type of aw_qos_dly_thr2_3 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_3 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_3_reg_t;
+
+/** Type of aw_qos_dly_thr2_4 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_4 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_4_reg_t;
+
+/** Type of aw_qos_dly_thr2_5 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr2_5 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the aw channel delay threshold, default is 416.
+         */
+        uint32_t reg_aw_qos_dly_thr2_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr2_5_reg_t;
+
+
+/** Group: aw_qos_dly_thr3 */
+/** Type of aw_qos_dly_thr3_0 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_0 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_0_reg_t;
+
+/** Type of aw_qos_dly_thr3_1 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_1 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_1_reg_t;
+
+/** Type of aw_qos_dly_thr3_2 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_2 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_2_reg_t;
+
+/** Type of aw_qos_dly_thr3_3 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_3 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_3_reg_t;
+
+/** Type of aw_qos_dly_thr3_4 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_4 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_4_reg_t;
+
+/** Type of aw_qos_dly_thr3_5 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dly_thr3_5 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the aw channel delay threshold, default is 928.
+         */
+        uint32_t reg_aw_qos_dly_thr3_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dly_thr3_5_reg_t;
+
+
+/** Group: ar_qos_dly_thr0 */
+/** Type of ar_qos_dly_thr0_0 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_0 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_0_reg_t;
+
+/** Type of ar_qos_dly_thr0_1 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_1 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_1_reg_t;
+
+/** Type of ar_qos_dly_thr0_2 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_2 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_2_reg_t;
+
+/** Type of ar_qos_dly_thr0_3 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_3 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_3_reg_t;
+
+/** Type of ar_qos_dly_thr0_4 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_4 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_4_reg_t;
+
+/** Type of ar_qos_dly_thr0_5 register
+ *  Config the first level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr0_5 : R/W; bitpos: [12:0]; default: 32;
+         *  the first level of the ar channel delay threshold, default is 32.
+         */
+        uint32_t reg_ar_qos_dly_thr0_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr0_5_reg_t;
+
+
+/** Group: ar_qos_dly_thr1 */
+/** Type of ar_qos_dly_thr1_0 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_0 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_0_reg_t;
+
+/** Type of ar_qos_dly_thr1_1 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_1 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_1_reg_t;
+
+/** Type of ar_qos_dly_thr1_2 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_2 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_2_reg_t;
+
+/** Type of ar_qos_dly_thr1_3 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_3 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_3_reg_t;
+
+/** Type of ar_qos_dly_thr1_4 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_4 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_4_reg_t;
+
+/** Type of ar_qos_dly_thr1_5 register
+ *  Config the second level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr1_5 : R/W; bitpos: [12:0]; default: 160;
+         *  the second level of the ar channel delay threshold, default is 160.
+         */
+        uint32_t reg_ar_qos_dly_thr1_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr1_5_reg_t;
+
+
+/** Group: ar_qos_dly_thr2 */
+/** Type of ar_qos_dly_thr2_0 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_0 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_0_reg_t;
+
+/** Type of ar_qos_dly_thr2_1 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_1 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_1_reg_t;
+
+/** Type of ar_qos_dly_thr2_2 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_2 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_2_reg_t;
+
+/** Type of ar_qos_dly_thr2_3 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_3 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_3_reg_t;
+
+/** Type of ar_qos_dly_thr2_4 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_4 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_4_reg_t;
+
+/** Type of ar_qos_dly_thr2_5 register
+ *  Config the third level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr2_5 : R/W; bitpos: [12:0]; default: 416;
+         *  the third level of the ar channel delay threshold, default is 416.
+         */
+        uint32_t reg_ar_qos_dly_thr2_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr2_5_reg_t;
+
+
+/** Group: ar_qos_dly_thr3 */
+/** Type of ar_qos_dly_thr3_0 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_0 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_0:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_0_reg_t;
+
+/** Type of ar_qos_dly_thr3_1 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_1 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_1:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_1_reg_t;
+
+/** Type of ar_qos_dly_thr3_2 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_2 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_2:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_2_reg_t;
+
+/** Type of ar_qos_dly_thr3_3 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_3 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_3:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_3_reg_t;
+
+/** Type of ar_qos_dly_thr3_4 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_4 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_4:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_4_reg_t;
+
+/** Type of ar_qos_dly_thr3_5 register
+ *  Config the forth level delay threshold for first priority in AW channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dly_thr3_5 : R/W; bitpos: [12:0]; default: 928;
+         *  the forth level of the ar channel delay threshold, default is 928.
+         */
+        uint32_t reg_ar_qos_dly_thr3_5:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dly_thr3_5_reg_t;
+
+
+/** Group: aw_qos_bur_len_thr */
+/** Type of aw_qos_bur_len_thr_0 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_0 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_0_reg_t;
+
+/** Type of aw_qos_bur_len_thr_1 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_1 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_1_reg_t;
+
+/** Type of aw_qos_bur_len_thr_2 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_2 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_2_reg_t;
+
+/** Type of aw_qos_bur_len_thr_3 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_3 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_3_reg_t;
+
+/** Type of aw_qos_bur_len_thr_4 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_4 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_4_reg_t;
+
+/** Type of aw_qos_bur_len_thr_5 register
+ *  Config the min value of token which can enable axi write transaction.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_bur_len_thr_5 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of aw channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_aw_qos_bur_len_thr_5:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_bur_len_thr_5_reg_t;
+
+
+/** Group: ar_qos_bur_len_thr */
+/** Type of ar_qos_bur_len_thr_0 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_0 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_0:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_0_reg_t;
+
+/** Type of ar_qos_bur_len_thr_1 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_1 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_1:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_1_reg_t;
+
+/** Type of ar_qos_bur_len_thr_2 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_2 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_2:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_2_reg_t;
+
+/** Type of ar_qos_bur_len_thr_3 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_3 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_3:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_3_reg_t;
+
+/** Type of ar_qos_bur_len_thr_4 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_4 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_4:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_4_reg_t;
+
+/** Type of ar_qos_bur_len_thr_5 register
+ *  Config the min value of token which can enable axi read transaction.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_bur_len_thr_5 : R/W; bitpos: [9:0]; default: 64;
+         *  limit the starting token value of ar channel to turn on transmission, default value
+         *  is 64, 0 means no limit.
+         */
+        uint32_t reg_ar_qos_bur_len_thr_5:10;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_bur_len_thr_5_reg_t;
+
+
+/** Group: aw_qos_dbg_tk_thr */
+/** Type of aw_qos_dbg_tk_thr_0 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_0 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_0_reg_t;
+
+/** Type of aw_qos_dbg_tk_thr_1 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_1 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_1_reg_t;
+
+/** Type of aw_qos_dbg_tk_thr_2 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_2 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_2_reg_t;
+
+/** Type of aw_qos_dbg_tk_thr_3 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_3 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_3_reg_t;
+
+/** Type of aw_qos_dbg_tk_thr_4 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_4 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_4_reg_t;
+
+/** Type of aw_qos_dbg_tk_thr_5 register
+ *  Config the debug smple interval in aw channel.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_dbg_tk_thr_5 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_aw_qos_dbg_tk_thr_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_dbg_tk_thr_5_reg_t;
+
+
+/** Group: ar_qos_dbg_tk_thr */
+/** Type of ar_qos_dbg_tk_thr_0 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_0 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_0_reg_t;
+
+/** Type of ar_qos_dbg_tk_thr_1 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_1 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_1_reg_t;
+
+/** Type of ar_qos_dbg_tk_thr_2 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_2 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_2_reg_t;
+
+/** Type of ar_qos_dbg_tk_thr_3 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_3 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_3:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_3_reg_t;
+
+/** Type of ar_qos_dbg_tk_thr_4 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_4 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_4:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_4_reg_t;
+
+/** Type of ar_qos_dbg_tk_thr_5 register
+ *  Config the debug smple interval in ar channel.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_dbg_tk_thr_5 : R/W; bitpos: [7:0]; default: 16;
+         *  limit the debug sample interval, default value is 16
+         */
+        uint32_t reg_ar_qos_dbg_tk_thr_5:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_dbg_tk_thr_5_reg_t;
+
+
+/** Group: max_ost_aw_s */
+/** Type of max_ost_aw_s_0 register
+ *  Config the max outstanding num in current slave write port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_aw_s_0 : R/W; bitpos: [5:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15, max is 32.
+         */
+        uint32_t reg_max_ost_aw_s_0:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_max_ost_aw_s_0_reg_t;
+
+/** Type of max_ost_aw_s_1 register
+ *  Config the max outstanding num in current slave write port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_aw_s_1 : R/W; bitpos: [5:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15, max is 32.
+         */
+        uint32_t reg_max_ost_aw_s_1:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_max_ost_aw_s_1_reg_t;
+
+/** Type of max_ost_aw_s_2 register
+ *  Config the max outstanding num in current slave write port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_aw_s_2 : R/W; bitpos: [5:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15, max is 32.
+         */
+        uint32_t reg_max_ost_aw_s_2:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_max_ost_aw_s_2_reg_t;
+
+
+/** Group: max_ost_ar_s */
+/** Type of max_ost_ar_s_0 register
+ *  Config the max outstanding num in current slave read port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_ar_s_0 : R/W; bitpos: [7:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15
+         */
+        uint32_t reg_max_ost_ar_s_0:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_max_ost_ar_s_0_reg_t;
+
+/** Type of max_ost_ar_s_1 register
+ *  Config the max outstanding num in current slave read port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_ar_s_1 : R/W; bitpos: [7:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15
+         */
+        uint32_t reg_max_ost_ar_s_1:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_max_ost_ar_s_1_reg_t;
+
+/** Type of max_ost_ar_s_2 register
+ *  Config the max outstanding num in current slave read port.
+ */
+typedef union {
+    struct {
+        /** reg_max_ost_ar_s_2 : R/W; bitpos: [7:0]; default: 15;
+         *  limit the number of outstanding for slave port, default value is 15
+         */
+        uint32_t reg_max_ost_ar_s_2:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} axi_ic_max_ost_ar_s_2_reg_t;
+
+
+/** Group: aw_qos_peak_rate_mode */
+/** Type of aw_qos_peak_rate_mode register
+ *  Config the aw channel token store mode in peak rate enable.
+ */
+typedef union {
+    struct {
+        /** reg_aw_qos_peak_rate_mode : R/W; bitpos: [5:0]; default: 0;
+         *  peak rate, to control the aw channel request token num more than 1, default 0.
+         */
+        uint32_t reg_aw_qos_peak_rate_mode:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_aw_qos_peak_rate_mode_reg_t;
+
+
+/** Group: ar_qos_peak_rate_mode */
+/** Type of ar_qos_peak_rate_mode register
+ *  Config the ar channel token store mode in peak rate enable.
+ */
+typedef union {
+    struct {
+        /** reg_ar_qos_peak_rate_mode : R/W; bitpos: [5:0]; default: 0;
+         *  peak rate, to control the ar channel request token num  more than 1, default 0.
+         */
+        uint32_t reg_ar_qos_peak_rate_mode:6;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} axi_ic_ar_qos_peak_rate_mode_reg_t;
+
+
+typedef struct {
+    volatile axi_ic_date_reg_t date;
+    volatile axi_ic_clk_en_reg_t clk_en;
+    volatile axi_ic_interrupt_raw_reg_t interrupt_raw;
+    volatile axi_ic_interrupt_clr_reg_t interrupt_clr;
+    volatile axi_ic_interrupt_ena_reg_t interrupt_ena;
+    volatile axi_ic_interrupt_st_reg_t interrupt_st;
+    volatile axi_ic_timeout_max_cnt_reg_t timeout_max_cnt;
+    volatile axi_ic_timeout_info_reg_t timeout_info;
+    volatile axi_ic_dec_failure_info_reg_t dec_failure_info;
+    volatile axi_ic_qos_debug_mst_sel_reg_t qos_debug_mst_sel;
+    uint32_t reserved_028[22];
+    volatile axi_ic_dec_failure_addr_reg_t dec_failure_addr;
+    volatile axi_ic_reg_slave_is_secure_reg_t reg_slave_is_secure;
+    volatile axi_ic_slave_security_override_reg_t slave_security_override;
+    volatile axi_ic_master_is_secure_reg_t master_is_secure;
+    volatile axi_ic_master_security_override_reg_t master_security_override;
+    volatile axi_ic_aw_qos_value_0_reg_t aw_qos_value_0;
+    volatile axi_ic_aw_qos_value_1_reg_t aw_qos_value_1;
+    volatile axi_ic_aw_qos_value_2_reg_t aw_qos_value_2;
+    volatile axi_ic_aw_qos_value_3_reg_t aw_qos_value_3;
+    volatile axi_ic_aw_qos_value_4_reg_t aw_qos_value_4;
+    volatile axi_ic_aw_qos_value_5_reg_t aw_qos_value_5;
+    volatile axi_ic_ar_qos_value_0_reg_t ar_qos_value_0;
+    volatile axi_ic_ar_qos_value_1_reg_t ar_qos_value_1;
+    volatile axi_ic_ar_qos_value_2_reg_t ar_qos_value_2;
+    volatile axi_ic_ar_qos_value_3_reg_t ar_qos_value_3;
+    volatile axi_ic_ar_qos_value_4_reg_t ar_qos_value_4;
+    volatile axi_ic_ar_qos_value_5_reg_t ar_qos_value_5;
+    volatile axi_ic_b_prior_value_0_reg_t b_prior_value_0;
+    volatile axi_ic_b_prior_value_1_reg_t b_prior_value_1;
+    volatile axi_ic_b_prior_value_2_reg_t b_prior_value_2;
+    volatile axi_ic_r_prior_value_0_reg_t r_prior_value_0;
+    volatile axi_ic_r_prior_value_1_reg_t r_prior_value_1;
+    volatile axi_ic_r_prior_value_2_reg_t r_prior_value_2;
+    volatile axi_ic_aw_qos_sel_0_reg_t aw_qos_sel_0;
+    volatile axi_ic_aw_qos_sel_1_reg_t aw_qos_sel_1;
+    volatile axi_ic_aw_qos_sel_2_reg_t aw_qos_sel_2;
+    volatile axi_ic_aw_qos_sel_3_reg_t aw_qos_sel_3;
+    volatile axi_ic_aw_qos_sel_4_reg_t aw_qos_sel_4;
+    volatile axi_ic_aw_qos_sel_5_reg_t aw_qos_sel_5;
+    volatile axi_ic_ar_qos_sel_0_reg_t ar_qos_sel_0;
+    volatile axi_ic_ar_qos_sel_1_reg_t ar_qos_sel_1;
+    volatile axi_ic_ar_qos_sel_2_reg_t ar_qos_sel_2;
+    volatile axi_ic_ar_qos_sel_3_reg_t ar_qos_sel_3;
+    volatile axi_ic_ar_qos_sel_4_reg_t ar_qos_sel_4;
+    volatile axi_ic_ar_qos_sel_5_reg_t ar_qos_sel_5;
+    volatile axi_ic_aw_qos_recovery_reg_t aw_qos_recovery;
+    volatile axi_ic_ar_qos_recovery_reg_t ar_qos_recovery;
+    volatile axi_ic_aw_qos_id_mask_0_reg_t aw_qos_id_mask_0;
+    volatile axi_ic_aw_qos_id_mask_1_reg_t aw_qos_id_mask_1;
+    volatile axi_ic_aw_qos_id_mask_2_reg_t aw_qos_id_mask_2;
+    volatile axi_ic_aw_qos_id_mask_3_reg_t aw_qos_id_mask_3;
+    volatile axi_ic_aw_qos_id_mask_4_reg_t aw_qos_id_mask_4;
+    volatile axi_ic_aw_qos_id_mask_5_reg_t aw_qos_id_mask_5;
+    volatile axi_ic_ar_qos_id_mask_0_reg_t ar_qos_id_mask_0;
+    volatile axi_ic_ar_qos_id_mask_1_reg_t ar_qos_id_mask_1;
+    volatile axi_ic_ar_qos_id_mask_2_reg_t ar_qos_id_mask_2;
+    volatile axi_ic_ar_qos_id_mask_3_reg_t ar_qos_id_mask_3;
+    volatile axi_ic_ar_qos_id_mask_4_reg_t ar_qos_id_mask_4;
+    volatile axi_ic_ar_qos_id_mask_5_reg_t ar_qos_id_mask_5;
+    volatile axi_ic_aw_qos_id_filter_0_reg_t aw_qos_id_filter_0;
+    volatile axi_ic_aw_qos_id_filter_1_reg_t aw_qos_id_filter_1;
+    volatile axi_ic_aw_qos_id_filter_2_reg_t aw_qos_id_filter_2;
+    volatile axi_ic_aw_qos_id_filter_3_reg_t aw_qos_id_filter_3;
+    volatile axi_ic_aw_qos_id_filter_4_reg_t aw_qos_id_filter_4;
+    volatile axi_ic_aw_qos_id_filter_5_reg_t aw_qos_id_filter_5;
+    volatile axi_ic_ar_qos_id_filter_0_reg_t ar_qos_id_filter_0;
+    volatile axi_ic_ar_qos_id_filter_1_reg_t ar_qos_id_filter_1;
+    volatile axi_ic_ar_qos_id_filter_2_reg_t ar_qos_id_filter_2;
+    volatile axi_ic_ar_qos_id_filter_3_reg_t ar_qos_id_filter_3;
+    volatile axi_ic_ar_qos_id_filter_4_reg_t ar_qos_id_filter_4;
+    volatile axi_ic_ar_qos_id_filter_5_reg_t ar_qos_id_filter_5;
+    volatile axi_ic_aw_qos_ctrl_cfg_0_reg_t aw_qos_ctrl_cfg_0;
+    volatile axi_ic_aw_qos_ctrl_cfg_1_reg_t aw_qos_ctrl_cfg_1;
+    volatile axi_ic_aw_qos_ctrl_cfg_2_reg_t aw_qos_ctrl_cfg_2;
+    volatile axi_ic_aw_qos_ctrl_cfg_3_reg_t aw_qos_ctrl_cfg_3;
+    volatile axi_ic_aw_qos_ctrl_cfg_4_reg_t aw_qos_ctrl_cfg_4;
+    volatile axi_ic_aw_qos_ctrl_cfg_5_reg_t aw_qos_ctrl_cfg_5;
+    volatile axi_ic_ar_qos_ctrl_cfg_0_reg_t ar_qos_ctrl_cfg_0;
+    volatile axi_ic_ar_qos_ctrl_cfg_1_reg_t ar_qos_ctrl_cfg_1;
+    volatile axi_ic_ar_qos_ctrl_cfg_2_reg_t ar_qos_ctrl_cfg_2;
+    volatile axi_ic_ar_qos_ctrl_cfg_3_reg_t ar_qos_ctrl_cfg_3;
+    volatile axi_ic_ar_qos_ctrl_cfg_4_reg_t ar_qos_ctrl_cfg_4;
+    volatile axi_ic_ar_qos_ctrl_cfg_5_reg_t ar_qos_ctrl_cfg_5;
+    volatile axi_ic_aw_qos_trans_rate_0_reg_t aw_qos_trans_rate_0;
+    volatile axi_ic_aw_qos_trans_rate_1_reg_t aw_qos_trans_rate_1;
+    volatile axi_ic_aw_qos_trans_rate_2_reg_t aw_qos_trans_rate_2;
+    volatile axi_ic_aw_qos_trans_rate_3_reg_t aw_qos_trans_rate_3;
+    volatile axi_ic_aw_qos_trans_rate_4_reg_t aw_qos_trans_rate_4;
+    volatile axi_ic_aw_qos_trans_rate_5_reg_t aw_qos_trans_rate_5;
+    volatile axi_ic_ar_qos_trans_rate_0_reg_t ar_qos_trans_rate_0;
+    volatile axi_ic_ar_qos_trans_rate_1_reg_t ar_qos_trans_rate_1;
+    volatile axi_ic_ar_qos_trans_rate_2_reg_t ar_qos_trans_rate_2;
+    volatile axi_ic_ar_qos_trans_rate_3_reg_t ar_qos_trans_rate_3;
+    volatile axi_ic_ar_qos_trans_rate_4_reg_t ar_qos_trans_rate_4;
+    volatile axi_ic_ar_qos_trans_rate_5_reg_t ar_qos_trans_rate_5;
+    volatile axi_ic_aw_qos_peak_rate_0_reg_t aw_qos_peak_rate_0;
+    volatile axi_ic_aw_qos_peak_rate_1_reg_t aw_qos_peak_rate_1;
+    volatile axi_ic_aw_qos_peak_rate_2_reg_t aw_qos_peak_rate_2;
+    volatile axi_ic_aw_qos_peak_rate_3_reg_t aw_qos_peak_rate_3;
+    volatile axi_ic_aw_qos_peak_rate_4_reg_t aw_qos_peak_rate_4;
+    volatile axi_ic_aw_qos_peak_rate_5_reg_t aw_qos_peak_rate_5;
+    volatile axi_ic_ar_qos_peak_rate_0_reg_t ar_qos_peak_rate_0;
+    volatile axi_ic_ar_qos_peak_rate_1_reg_t ar_qos_peak_rate_1;
+    volatile axi_ic_ar_qos_peak_rate_2_reg_t ar_qos_peak_rate_2;
+    volatile axi_ic_ar_qos_peak_rate_3_reg_t ar_qos_peak_rate_3;
+    volatile axi_ic_ar_qos_peak_rate_4_reg_t ar_qos_peak_rate_4;
+    volatile axi_ic_ar_qos_peak_rate_5_reg_t ar_qos_peak_rate_5;
+    volatile axi_ic_aw_qos_burstiness_0_reg_t aw_qos_burstiness_0;
+    volatile axi_ic_aw_qos_burstiness_1_reg_t aw_qos_burstiness_1;
+    volatile axi_ic_aw_qos_burstiness_2_reg_t aw_qos_burstiness_2;
+    volatile axi_ic_aw_qos_burstiness_3_reg_t aw_qos_burstiness_3;
+    volatile axi_ic_aw_qos_burstiness_4_reg_t aw_qos_burstiness_4;
+    volatile axi_ic_aw_qos_burstiness_5_reg_t aw_qos_burstiness_5;
+    volatile axi_ic_ar_qos_burstiness_0_reg_t ar_qos_burstiness_0;
+    volatile axi_ic_ar_qos_burstiness_1_reg_t ar_qos_burstiness_1;
+    volatile axi_ic_ar_qos_burstiness_2_reg_t ar_qos_burstiness_2;
+    volatile axi_ic_ar_qos_burstiness_3_reg_t ar_qos_burstiness_3;
+    volatile axi_ic_ar_qos_burstiness_4_reg_t ar_qos_burstiness_4;
+    volatile axi_ic_ar_qos_burstiness_5_reg_t ar_qos_burstiness_5;
+    volatile axi_ic_aw_qos_cfg_vlu_0_reg_t aw_qos_cfg_vlu_0;
+    volatile axi_ic_aw_qos_cfg_vlu_1_reg_t aw_qos_cfg_vlu_1;
+    volatile axi_ic_aw_qos_cfg_vlu_2_reg_t aw_qos_cfg_vlu_2;
+    volatile axi_ic_aw_qos_cfg_vlu_3_reg_t aw_qos_cfg_vlu_3;
+    volatile axi_ic_aw_qos_cfg_vlu_4_reg_t aw_qos_cfg_vlu_4;
+    volatile axi_ic_aw_qos_cfg_vlu_5_reg_t aw_qos_cfg_vlu_5;
+    volatile axi_ic_ar_qos_cfg_vlu_0_reg_t ar_qos_cfg_vlu_0;
+    volatile axi_ic_ar_qos_cfg_vlu_1_reg_t ar_qos_cfg_vlu_1;
+    volatile axi_ic_ar_qos_cfg_vlu_2_reg_t ar_qos_cfg_vlu_2;
+    volatile axi_ic_ar_qos_cfg_vlu_3_reg_t ar_qos_cfg_vlu_3;
+    volatile axi_ic_ar_qos_cfg_vlu_4_reg_t ar_qos_cfg_vlu_4;
+    volatile axi_ic_ar_qos_cfg_vlu_5_reg_t ar_qos_cfg_vlu_5;
+    volatile axi_ic_aw_qos_dly_thr0_0_reg_t aw_qos_dly_thr0_0;
+    volatile axi_ic_aw_qos_dly_thr0_1_reg_t aw_qos_dly_thr0_1;
+    volatile axi_ic_aw_qos_dly_thr0_2_reg_t aw_qos_dly_thr0_2;
+    volatile axi_ic_aw_qos_dly_thr0_3_reg_t aw_qos_dly_thr0_3;
+    volatile axi_ic_aw_qos_dly_thr0_4_reg_t aw_qos_dly_thr0_4;
+    volatile axi_ic_aw_qos_dly_thr0_5_reg_t aw_qos_dly_thr0_5;
+    volatile axi_ic_aw_qos_dly_thr1_0_reg_t aw_qos_dly_thr1_0;
+    volatile axi_ic_aw_qos_dly_thr1_1_reg_t aw_qos_dly_thr1_1;
+    volatile axi_ic_aw_qos_dly_thr1_2_reg_t aw_qos_dly_thr1_2;
+    volatile axi_ic_aw_qos_dly_thr1_3_reg_t aw_qos_dly_thr1_3;
+    volatile axi_ic_aw_qos_dly_thr1_4_reg_t aw_qos_dly_thr1_4;
+    volatile axi_ic_aw_qos_dly_thr1_5_reg_t aw_qos_dly_thr1_5;
+    volatile axi_ic_aw_qos_dly_thr2_0_reg_t aw_qos_dly_thr2_0;
+    volatile axi_ic_aw_qos_dly_thr2_1_reg_t aw_qos_dly_thr2_1;
+    volatile axi_ic_aw_qos_dly_thr2_2_reg_t aw_qos_dly_thr2_2;
+    volatile axi_ic_aw_qos_dly_thr2_3_reg_t aw_qos_dly_thr2_3;
+    volatile axi_ic_aw_qos_dly_thr2_4_reg_t aw_qos_dly_thr2_4;
+    volatile axi_ic_aw_qos_dly_thr2_5_reg_t aw_qos_dly_thr2_5;
+    volatile axi_ic_aw_qos_dly_thr3_0_reg_t aw_qos_dly_thr3_0;
+    volatile axi_ic_aw_qos_dly_thr3_1_reg_t aw_qos_dly_thr3_1;
+    volatile axi_ic_aw_qos_dly_thr3_2_reg_t aw_qos_dly_thr3_2;
+    volatile axi_ic_aw_qos_dly_thr3_3_reg_t aw_qos_dly_thr3_3;
+    volatile axi_ic_aw_qos_dly_thr3_4_reg_t aw_qos_dly_thr3_4;
+    volatile axi_ic_aw_qos_dly_thr3_5_reg_t aw_qos_dly_thr3_5;
+    volatile axi_ic_ar_qos_dly_thr0_0_reg_t ar_qos_dly_thr0_0;
+    volatile axi_ic_ar_qos_dly_thr0_1_reg_t ar_qos_dly_thr0_1;
+    volatile axi_ic_ar_qos_dly_thr0_2_reg_t ar_qos_dly_thr0_2;
+    volatile axi_ic_ar_qos_dly_thr0_3_reg_t ar_qos_dly_thr0_3;
+    volatile axi_ic_ar_qos_dly_thr0_4_reg_t ar_qos_dly_thr0_4;
+    volatile axi_ic_ar_qos_dly_thr0_5_reg_t ar_qos_dly_thr0_5;
+    volatile axi_ic_ar_qos_dly_thr1_0_reg_t ar_qos_dly_thr1_0;
+    volatile axi_ic_ar_qos_dly_thr1_1_reg_t ar_qos_dly_thr1_1;
+    volatile axi_ic_ar_qos_dly_thr1_2_reg_t ar_qos_dly_thr1_2;
+    volatile axi_ic_ar_qos_dly_thr1_3_reg_t ar_qos_dly_thr1_3;
+    volatile axi_ic_ar_qos_dly_thr1_4_reg_t ar_qos_dly_thr1_4;
+    volatile axi_ic_ar_qos_dly_thr1_5_reg_t ar_qos_dly_thr1_5;
+    volatile axi_ic_ar_qos_dly_thr2_0_reg_t ar_qos_dly_thr2_0;
+    volatile axi_ic_ar_qos_dly_thr2_1_reg_t ar_qos_dly_thr2_1;
+    volatile axi_ic_ar_qos_dly_thr2_2_reg_t ar_qos_dly_thr2_2;
+    volatile axi_ic_ar_qos_dly_thr2_3_reg_t ar_qos_dly_thr2_3;
+    volatile axi_ic_ar_qos_dly_thr2_4_reg_t ar_qos_dly_thr2_4;
+    volatile axi_ic_ar_qos_dly_thr2_5_reg_t ar_qos_dly_thr2_5;
+    volatile axi_ic_ar_qos_dly_thr3_0_reg_t ar_qos_dly_thr3_0;
+    volatile axi_ic_ar_qos_dly_thr3_1_reg_t ar_qos_dly_thr3_1;
+    volatile axi_ic_ar_qos_dly_thr3_2_reg_t ar_qos_dly_thr3_2;
+    volatile axi_ic_ar_qos_dly_thr3_3_reg_t ar_qos_dly_thr3_3;
+    volatile axi_ic_ar_qos_dly_thr3_4_reg_t ar_qos_dly_thr3_4;
+    volatile axi_ic_ar_qos_dly_thr3_5_reg_t ar_qos_dly_thr3_5;
+    volatile axi_ic_aw_qos_bur_len_thr_0_reg_t aw_qos_bur_len_thr_0;
+    volatile axi_ic_aw_qos_bur_len_thr_1_reg_t aw_qos_bur_len_thr_1;
+    volatile axi_ic_aw_qos_bur_len_thr_2_reg_t aw_qos_bur_len_thr_2;
+    volatile axi_ic_aw_qos_bur_len_thr_3_reg_t aw_qos_bur_len_thr_3;
+    volatile axi_ic_aw_qos_bur_len_thr_4_reg_t aw_qos_bur_len_thr_4;
+    volatile axi_ic_aw_qos_bur_len_thr_5_reg_t aw_qos_bur_len_thr_5;
+    volatile axi_ic_ar_qos_bur_len_thr_0_reg_t ar_qos_bur_len_thr_0;
+    volatile axi_ic_ar_qos_bur_len_thr_1_reg_t ar_qos_bur_len_thr_1;
+    volatile axi_ic_ar_qos_bur_len_thr_2_reg_t ar_qos_bur_len_thr_2;
+    volatile axi_ic_ar_qos_bur_len_thr_3_reg_t ar_qos_bur_len_thr_3;
+    volatile axi_ic_ar_qos_bur_len_thr_4_reg_t ar_qos_bur_len_thr_4;
+    volatile axi_ic_ar_qos_bur_len_thr_5_reg_t ar_qos_bur_len_thr_5;
+    volatile axi_ic_aw_qos_dbg_tk_thr_0_reg_t aw_qos_dbg_tk_thr_0;
+    volatile axi_ic_aw_qos_dbg_tk_thr_1_reg_t aw_qos_dbg_tk_thr_1;
+    volatile axi_ic_aw_qos_dbg_tk_thr_2_reg_t aw_qos_dbg_tk_thr_2;
+    volatile axi_ic_aw_qos_dbg_tk_thr_3_reg_t aw_qos_dbg_tk_thr_3;
+    volatile axi_ic_aw_qos_dbg_tk_thr_4_reg_t aw_qos_dbg_tk_thr_4;
+    volatile axi_ic_aw_qos_dbg_tk_thr_5_reg_t aw_qos_dbg_tk_thr_5;
+    volatile axi_ic_ar_qos_dbg_tk_thr_0_reg_t ar_qos_dbg_tk_thr_0;
+    volatile axi_ic_ar_qos_dbg_tk_thr_1_reg_t ar_qos_dbg_tk_thr_1;
+    volatile axi_ic_ar_qos_dbg_tk_thr_2_reg_t ar_qos_dbg_tk_thr_2;
+    volatile axi_ic_ar_qos_dbg_tk_thr_3_reg_t ar_qos_dbg_tk_thr_3;
+    volatile axi_ic_ar_qos_dbg_tk_thr_4_reg_t ar_qos_dbg_tk_thr_4;
+    volatile axi_ic_ar_qos_dbg_tk_thr_5_reg_t ar_qos_dbg_tk_thr_5;
+    volatile axi_ic_max_ost_aw_s_0_reg_t max_ost_aw_s_0;
+    volatile axi_ic_max_ost_aw_s_1_reg_t max_ost_aw_s_1;
+    volatile axi_ic_max_ost_aw_s_2_reg_t max_ost_aw_s_2;
+    volatile axi_ic_max_ost_ar_s_0_reg_t max_ost_ar_s_0;
+    volatile axi_ic_max_ost_ar_s_1_reg_t max_ost_ar_s_1;
+    volatile axi_ic_max_ost_ar_s_2_reg_t max_ost_ar_s_2;
+    volatile axi_ic_aw_qos_peak_rate_mode_reg_t aw_qos_peak_rate_mode;
+    volatile axi_ic_ar_qos_peak_rate_mode_reg_t ar_qos_peak_rate_mode;
+} axi_ic_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(axi_ic_dev_t) == 0x3a4, "Invalid size of axi_ic_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/icm_sys_reg.h b/components/soc/esp32s31/register/soc/icm_sys_reg.h
new file mode 100644
index 00000000000..7fd2abef623
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/icm_sys_reg.h
@@ -0,0 +1,134 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ICM_VER_DATE_REG register
+ *  NA
+ */
+#define ICM_VER_DATE_REG (DR_REG_ICM_BASE + 0x0)
+/** ICM_REG_VER_DATE : R/W; bitpos: [31:0]; default: 539296517;
+ *  NA
+ */
+#define ICM_REG_VER_DATE    0xFFFFFFFFU
+#define ICM_REG_VER_DATE_M  (ICM_REG_VER_DATE_V << ICM_REG_VER_DATE_S)
+#define ICM_REG_VER_DATE_V  0xFFFFFFFFU
+#define ICM_REG_VER_DATE_S  0
+
+/** ICM_CLK_EN_REG register
+ *  NA
+ */
+#define ICM_CLK_EN_REG (DR_REG_ICM_BASE + 0x4)
+/** ICM_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CLK_EN    (BIT(0))
+#define ICM_REG_CLK_EN_M  (ICM_REG_CLK_EN_V << ICM_REG_CLK_EN_S)
+#define ICM_REG_CLK_EN_V  0x00000001U
+#define ICM_REG_CLK_EN_S  0
+
+/** ICM_MST_ARQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_ARQOS_REG0_REG (DR_REG_ICM_BASE + 0x28)
+/** ICM_REG_CPU_ARQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_ARQOS    0x0000000FU
+#define ICM_REG_CPU_ARQOS_M  (ICM_REG_CPU_ARQOS_V << ICM_REG_CPU_ARQOS_S)
+#define ICM_REG_CPU_ARQOS_V  0x0000000FU
+#define ICM_REG_CPU_ARQOS_S  0
+/** ICM_REG_CACHE_ARQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_ARQOS    0x0000000FU
+#define ICM_REG_CACHE_ARQOS_M  (ICM_REG_CACHE_ARQOS_V << ICM_REG_CACHE_ARQOS_S)
+#define ICM_REG_CACHE_ARQOS_V  0x0000000FU
+#define ICM_REG_CACHE_ARQOS_S  4
+/** ICM_REG_DMA2D_ARQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_ARQOS    0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_M  (ICM_REG_DMA2D_ARQOS_V << ICM_REG_DMA2D_ARQOS_S)
+#define ICM_REG_DMA2D_ARQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_ARQOS_S  8
+/** ICM_REG_AXI_PDMA_INT_ARQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_AXI_PDMA_INT_ARQOS    0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_M  (ICM_REG_AXI_PDMA_INT_ARQOS_V << ICM_REG_AXI_PDMA_INT_ARQOS_S)
+#define ICM_REG_AXI_PDMA_INT_ARQOS_V  0x0000000FU
+#define ICM_REG_AXI_PDMA_INT_ARQOS_S  12
+/** ICM_REG_GMAC_ARQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GMAC_ARQOS    0x0000000FU
+#define ICM_REG_GMAC_ARQOS_M  (ICM_REG_GMAC_ARQOS_V << ICM_REG_GMAC_ARQOS_S)
+#define ICM_REG_GMAC_ARQOS_V  0x0000000FU
+#define ICM_REG_GMAC_ARQOS_S  16
+/** ICM_REG_AXI_SDMMC_INT_ARQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_AXI_SDMMC_INT_ARQOS    0x0000000FU
+#define ICM_REG_AXI_SDMMC_INT_ARQOS_M  (ICM_REG_AXI_SDMMC_INT_ARQOS_V << ICM_REG_AXI_SDMMC_INT_ARQOS_S)
+#define ICM_REG_AXI_SDMMC_INT_ARQOS_V  0x0000000FU
+#define ICM_REG_AXI_SDMMC_INT_ARQOS_S  20
+
+/** ICM_MST_AWQOS_REG0_REG register
+ *  NA
+ */
+#define ICM_MST_AWQOS_REG0_REG (DR_REG_ICM_BASE + 0x30)
+/** ICM_REG_CPU_AWQOS : R/W; bitpos: [3:0]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CPU_AWQOS    0x0000000FU
+#define ICM_REG_CPU_AWQOS_M  (ICM_REG_CPU_AWQOS_V << ICM_REG_CPU_AWQOS_S)
+#define ICM_REG_CPU_AWQOS_V  0x0000000FU
+#define ICM_REG_CPU_AWQOS_S  0
+/** ICM_REG_CACHE_AWQOS : R/W; bitpos: [7:4]; default: 0;
+ *  NA
+ */
+#define ICM_REG_CACHE_AWQOS    0x0000000FU
+#define ICM_REG_CACHE_AWQOS_M  (ICM_REG_CACHE_AWQOS_V << ICM_REG_CACHE_AWQOS_S)
+#define ICM_REG_CACHE_AWQOS_V  0x0000000FU
+#define ICM_REG_CACHE_AWQOS_S  4
+/** ICM_REG_DMA2D_AWQOS : R/W; bitpos: [11:8]; default: 0;
+ *  NA
+ */
+#define ICM_REG_DMA2D_AWQOS    0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_M  (ICM_REG_DMA2D_AWQOS_V << ICM_REG_DMA2D_AWQOS_S)
+#define ICM_REG_DMA2D_AWQOS_V  0x0000000FU
+#define ICM_REG_DMA2D_AWQOS_S  8
+/** ICM_REG_PDMA_INT_AWQOS : R/W; bitpos: [15:12]; default: 0;
+ *  NA
+ */
+#define ICM_REG_PDMA_INT_AWQOS    0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_M  (ICM_REG_PDMA_INT_AWQOS_V << ICM_REG_PDMA_INT_AWQOS_S)
+#define ICM_REG_PDMA_INT_AWQOS_V  0x0000000FU
+#define ICM_REG_PDMA_INT_AWQOS_S  12
+/** ICM_REG_GMAC_AWQOS : R/W; bitpos: [19:16]; default: 0;
+ *  NA
+ */
+#define ICM_REG_GMAC_AWQOS    0x0000000FU
+#define ICM_REG_GMAC_AWQOS_M  (ICM_REG_GMAC_AWQOS_V << ICM_REG_GMAC_AWQOS_S)
+#define ICM_REG_GMAC_AWQOS_V  0x0000000FU
+#define ICM_REG_GMAC_AWQOS_S  16
+/** ICM_REG_AXI_SDMMC_INT_AWQOS : R/W; bitpos: [23:20]; default: 0;
+ *  NA
+ */
+#define ICM_REG_AXI_SDMMC_INT_AWQOS    0x0000000FU
+#define ICM_REG_AXI_SDMMC_INT_AWQOS_M  (ICM_REG_AXI_SDMMC_INT_AWQOS_V << ICM_REG_AXI_SDMMC_INT_AWQOS_S)
+#define ICM_REG_AXI_SDMMC_INT_AWQOS_V  0x0000000FU
+#define ICM_REG_AXI_SDMMC_INT_AWQOS_S  20
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/icm_sys_struct.h b/components/soc/esp32s31/register/soc/icm_sys_struct.h
new file mode 100644
index 00000000000..9695def957d
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/icm_sys_struct.h
@@ -0,0 +1,132 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: ICM VER DATE REG */
+/** Type of ver_date register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_ver_date : R/W; bitpos: [31:0]; default: 539296517;
+         *  NA
+         */
+        uint32_t reg_ver_date:32;
+    };
+    uint32_t val;
+} icm_ver_date_reg_t;
+
+
+/** Group: ICM CLK EN REG */
+/** Type of clk_en register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} icm_clk_en_reg_t;
+
+
+/** Group: ICM MST ARQOS REG0 REG */
+/** Type of mst_arqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_arqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_arqos:4;
+        /** reg_cache_arqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_arqos:4;
+        /** reg_dma2d_arqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_arqos:4;
+        /** reg_axi_pdma_int_arqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_pdma_int_arqos:4;
+        /** reg_gmac_arqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gmac_arqos:4;
+        /** reg_axi_sdmmc_int_arqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_sdmmc_int_arqos:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} icm_mst_arqos_reg0_reg_t;
+
+
+/** Group: ICM MST AWQOS REG0 REG */
+/** Type of mst_awqos_reg0 register
+ *  NA
+ */
+typedef union {
+    struct {
+        /** reg_cpu_awqos : R/W; bitpos: [3:0]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cpu_awqos:4;
+        /** reg_cache_awqos : R/W; bitpos: [7:4]; default: 0;
+         *  NA
+         */
+        uint32_t reg_cache_awqos:4;
+        /** reg_dma2d_awqos : R/W; bitpos: [11:8]; default: 0;
+         *  NA
+         */
+        uint32_t reg_dma2d_awqos:4;
+        /** reg_pdma_int_awqos : R/W; bitpos: [15:12]; default: 0;
+         *  NA
+         */
+        uint32_t reg_pdma_int_awqos:4;
+        /** reg_gmac_awqos : R/W; bitpos: [19:16]; default: 0;
+         *  NA
+         */
+        uint32_t reg_gmac_awqos:4;
+        /** reg_axi_sdmmc_int_awqos : R/W; bitpos: [23:20]; default: 0;
+         *  NA
+         */
+        uint32_t reg_axi_sdmmc_int_awqos:4;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} icm_mst_awqos_reg0_reg_t;
+
+
+typedef struct {
+    volatile icm_ver_date_reg_t ver_date;
+    volatile icm_clk_en_reg_t clk_en;
+    uint32_t reserved_008[8];
+    volatile icm_mst_arqos_reg0_reg_t mst_arqos_reg0;
+    uint32_t reserved_02c;
+    volatile icm_mst_awqos_reg0_reg_t mst_awqos_reg0;
+} icm_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(icm_dev_t) == 0x34, "Invalid size of icm_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/interrupt_core0_reg.h b/components/soc/esp32s31/register/soc/interrupt_core0_reg.h
new file mode 100644
index 00000000000..cb27c5cc8d6
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/interrupt_core0_reg.h
@@ -0,0 +1,3925 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTERRUPT_CORE0_SYS_ICM_INTR_MAP_REG register
+ *  SYS_ICM_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
+/** INTERRUPT_CORE0_SYS_ICM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_M  (INTERRUPT_CORE0_SYS_ICM_INTR_MAP_V << INTERRUPT_CORE0_SYS_ICM_INTR_MAP_S)
+#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SYS_ICM_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SYS_ICM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_REG register
+ *  AXI_PERF_MON_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
+/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_V << INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PERF_MON_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_REG register
+ *  USB_DEVICE_INTR mapping register
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
+/** INTERRUPT_CORE0_USB_DEVICE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_M  (INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_V << INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_S)
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_MAP_S  0
+/** INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_USB_DEVICE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_REG register
+ *  SDIO_HOST_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
+/** INTERRUPT_CORE0_SDIO_HOST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_M  (INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_V << INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_S)
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SDIO_HOST_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SPI2_INTR_MAP_REG register
+ *  SPI2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
+/** INTERRUPT_CORE0_SPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SPI2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SPI2_INTR_MAP_M  (INTERRUPT_CORE0_SPI2_INTR_MAP_V << INTERRUPT_CORE0_SPI2_INTR_MAP_S)
+#define INTERRUPT_CORE0_SPI2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SPI2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SPI2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SPI3_INTR_MAP_REG register
+ *  SPI3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
+/** INTERRUPT_CORE0_SPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SPI3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SPI3_INTR_MAP_M  (INTERRUPT_CORE0_SPI3_INTR_MAP_V << INTERRUPT_CORE0_SPI3_INTR_MAP_S)
+#define INTERRUPT_CORE0_SPI3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SPI3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SPI3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_I2S0_INTR_MAP_REG register
+ *  I2S0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_I2S0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
+/** INTERRUPT_CORE0_I2S0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_I2S0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2S0_INTR_MAP_M  (INTERRUPT_CORE0_I2S0_INTR_MAP_V << INTERRUPT_CORE0_I2S0_INTR_MAP_S)
+#define INTERRUPT_CORE0_I2S0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_I2S0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_I2S0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register
+ *  I2S1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
+/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_I2S1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2S1_INTR_MAP_M  (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S)
+#define INTERRUPT_CORE0_I2S1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_I2S1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_I2S1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
+ *  UHCI0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
+/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_UHCI0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
+ *  UART0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
+/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_UART0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART0_INTR_MAP_M  (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_UART0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_UART0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
+ *  UART1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
+/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_UART1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_UART2_INTR_MAP_REG register
+ *  UART2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
+/** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_UART2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART2_INTR_MAP_M  (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_UART2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_UART2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_UART3_INTR_MAP_REG register
+ *  UART3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_UART3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
+/** INTERRUPT_CORE0_UART3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_UART3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_UART3_INTR_MAP_M  (INTERRUPT_CORE0_UART3_INTR_MAP_V << INTERRUPT_CORE0_UART3_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_UART3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_UART3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LCD_CAM_INTR_MAP_REG register
+ *  LCD_CAM_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
+/** INTERRUPT_CORE0_LCD_CAM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_M  (INTERRUPT_CORE0_LCD_CAM_INTR_MAP_V << INTERRUPT_CORE0_LCD_CAM_INTR_MAP_S)
+#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LCD_CAM_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LCD_CAM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PWM0_INTR_MAP_REG register
+ *  PWM0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
+/** INTERRUPT_CORE0_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PWM0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_M  (INTERRUPT_CORE0_PWM0_INTR_MAP_V << INTERRUPT_CORE0_PWM0_INTR_MAP_S)
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PWM0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PWM0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PWM1_INTR_MAP_REG register
+ *  PWM1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
+/** INTERRUPT_CORE0_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PWM1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_M  (INTERRUPT_CORE0_PWM1_INTR_MAP_V << INTERRUPT_CORE0_PWM1_INTR_MAP_S)
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PWM1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PWM1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PWM2_INTR_MAP_REG register
+ *  PWM2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
+/** INTERRUPT_CORE0_PWM2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PWM2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_M  (INTERRUPT_CORE0_PWM2_INTR_MAP_V << INTERRUPT_CORE0_PWM2_INTR_MAP_S)
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PWM2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PWM2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PWM3_INTR_MAP_REG register
+ *  PWM3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
+/** INTERRUPT_CORE0_PWM3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PWM3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_M  (INTERRUPT_CORE0_PWM3_INTR_MAP_V << INTERRUPT_CORE0_PWM3_INTR_MAP_S)
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PWM3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PWM3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
+ *  CAN0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
+/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CAN0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN0_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S)
+#define INTERRUPT_CORE0_CAN0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CAN0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CAN0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG register
+ *  CAN0_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
+/** INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CAN0_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register
+ *  CAN1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
+/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CAN1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN1_INTR_MAP_M  (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S)
+#define INTERRUPT_CORE0_CAN1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CAN1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CAN1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_REG register
+ *  CAN1_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
+/** INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CAN1_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
+ *  RMT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
+/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_RMT_INTR_MAP_M  (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
+#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_RMT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_I2C0_INTR_MAP_REG register
+ *  I2C0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_I2C0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
+/** INTERRUPT_CORE0_I2C0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_I2C0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2C0_INTR_MAP_M  (INTERRUPT_CORE0_I2C0_INTR_MAP_V << INTERRUPT_CORE0_I2C0_INTR_MAP_S)
+#define INTERRUPT_CORE0_I2C0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_I2C0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_I2C0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_I2C1_INTR_MAP_REG register
+ *  I2C1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_I2C1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
+/** INTERRUPT_CORE0_I2C1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_I2C1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_I2C1_INTR_MAP_M  (INTERRUPT_CORE0_I2C1_INTR_MAP_V << INTERRUPT_CORE0_I2C1_INTR_MAP_S)
+#define INTERRUPT_CORE0_I2C1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_I2C1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_I2C1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_REG register
+ *  TIMERGRP0_T0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
+/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_T0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_REG register
+ *  TIMERGRP0_T1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
+/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_T1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_REG register
+ *  TIMERGRP0_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
+/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP0_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_REG register
+ *  TIMERGRP1_T0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
+/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_T0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_REG register
+ *  TIMERGRP1_T1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
+/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_T1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_REG register
+ *  TIMERGRP1_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
+/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_M  (INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_TIMERGRP1_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LEDC0_INTR_MAP_REG register
+ *  LEDC0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LEDC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
+/** INTERRUPT_CORE0_LEDC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LEDC0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LEDC0_INTR_MAP_M  (INTERRUPT_CORE0_LEDC0_INTR_MAP_V << INTERRUPT_CORE0_LEDC0_INTR_MAP_S)
+#define INTERRUPT_CORE0_LEDC0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LEDC0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LEDC0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LEDC1_INTR_MAP_REG register
+ *  LEDC1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LEDC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
+/** INTERRUPT_CORE0_LEDC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LEDC1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LEDC1_INTR_MAP_M  (INTERRUPT_CORE0_LEDC1_INTR_MAP_V << INTERRUPT_CORE0_LEDC1_INTR_MAP_S)
+#define INTERRUPT_CORE0_LEDC1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LEDC1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LEDC1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
+ *  SYSTIMER_TARGET0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
+ *  SYSTIMER_TARGET1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
+ *  SYSTIMER_TARGET2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH4_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH4_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG register
+ *  ASRC_CHNL0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
+/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S)
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_ASRC_CHNL0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG register
+ *  ASRC_CHNL1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
+/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S)
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_ASRC_CHNL1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
+ *  RSA_INTR mapping register
+ */
+#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
+/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_RSA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_RSA_INTR_MAP_M  (INTERRUPT_CORE0_RSA_INTR_MAP_V << INTERRUPT_CORE0_RSA_INTR_MAP_S)
+#define INTERRUPT_CORE0_RSA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_RSA_INTR_MAP_S  0
+/** INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_RSA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
+ *  AES_INTR mapping register
+ */
+#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
+/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_AES_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_AES_INTR_MAP_M  (INTERRUPT_CORE0_AES_INTR_MAP_V << INTERRUPT_CORE0_AES_INTR_MAP_S)
+#define INTERRUPT_CORE0_AES_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_AES_INTR_MAP_S  0
+/** INTERRUPT_CORE0_AES_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_AES_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
+ *  SHA_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
+/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SHA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SHA_INTR_MAP_M  (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
+#define INTERRUPT_CORE0_SHA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SHA_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SHA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
+ *  ECC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
+/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_ECC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ECC_INTR_MAP_M  (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
+#define INTERRUPT_CORE0_ECC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_ECC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_ECC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
+ *  ECDSA_INTR mapping register
+ */
+#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
+/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_ECDSA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M  (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
+#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S  0
+/** INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_ECDSA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
+ *  KM_INTR mapping register
+ */
+#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
+/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_KM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_KM_INTR_MAP_M  (INTERRUPT_CORE0_KM_INTR_MAP_V << INTERRUPT_CORE0_KM_INTR_MAP_S)
+#define INTERRUPT_CORE0_KM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_KM_INTR_MAP_S  0
+/** INTERRUPT_CORE0_KM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_KM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_RMA_INTR_MAP_REG register
+ *  RMA_INTR mapping register
+ */
+#define INTERRUPT_CORE0_RMA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
+/** INTERRUPT_CORE0_RMA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_RMA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_RMA_INTR_MAP_M  (INTERRUPT_CORE0_RMA_INTR_MAP_V << INTERRUPT_CORE0_RMA_INTR_MAP_S)
+#define INTERRUPT_CORE0_RMA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_RMA_INTR_MAP_S  0
+/** INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_RMA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_GPIO_INTR0_MAP_REG register
+ *  GPIO_INTR0 mapping register
+ */
+#define INTERRUPT_CORE0_GPIO_INTR0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
+/** INTERRUPT_CORE0_GPIO_INTR0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR0_MAP_M  (INTERRUPT_CORE0_GPIO_INTR0_MAP_V << INTERRUPT_CORE0_GPIO_INTR0_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTR0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR0_MAP_S  0
+/** INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR0_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_GPIO_INTR1_MAP_REG register
+ *  GPIO_INTR1 mapping register
+ */
+#define INTERRUPT_CORE0_GPIO_INTR1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
+/** INTERRUPT_CORE0_GPIO_INTR1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR1_MAP_M  (INTERRUPT_CORE0_GPIO_INTR1_MAP_V << INTERRUPT_CORE0_GPIO_INTR1_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTR1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR1_MAP_S  0
+/** INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR1_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_GPIO_INTR2_MAP_REG register
+ *  GPIO_INTR2 mapping register
+ */
+#define INTERRUPT_CORE0_GPIO_INTR2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
+/** INTERRUPT_CORE0_GPIO_INTR2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR2_MAP_M  (INTERRUPT_CORE0_GPIO_INTR2_MAP_V << INTERRUPT_CORE0_GPIO_INTR2_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTR2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR2_MAP_S  0
+/** INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR2_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_GPIO_INTR3_MAP_REG register
+ *  GPIO_INTR3 mapping register
+ */
+#define INTERRUPT_CORE0_GPIO_INTR3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
+/** INTERRUPT_CORE0_GPIO_INTR3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR3_MAP_M  (INTERRUPT_CORE0_GPIO_INTR3_MAP_V << INTERRUPT_CORE0_GPIO_INTR3_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTR3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_GPIO_INTR3_MAP_S  0
+/** INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_M  (INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_V << INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_GPIO_INTR3_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  CPU_INTR_FROM_CPU_0 mapping register
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  CPU_INTR_FROM_CPU_1 mapping register
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  CPU_INTR_FROM_CPU_2 mapping register
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  CPU_INTR_FROM_CPU_3 mapping register
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
+ *  CACHE_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
+/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CACHE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CACHE_INTR_MAP_M  (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CACHE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CACHE_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CACHE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register
+ *  CPU_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
+/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register
+ *  CPU_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
+/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG register
+ *  CPU_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
+/** INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG register
+ *  CPU_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
+/** INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG register
+ *  HP_MEM_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
+/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG register
+ *  HP_MEM_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
+/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG register
+ *  HP_MEM_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
+/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG register
+ *  HP_MEM_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
+/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_REG register
+ *  HP_MEM_APM_M4_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
+/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_REG register
+ *  HP_MEM_APM_M5_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
+/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_M  (INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_V << INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_MEM_APM_M5_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_REG register
+ *  CPU_PERI0_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
+/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_REG register
+ *  CPU_PERI1_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
+/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_REG register
+ *  HP_PERI0_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
+/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_REG register
+ *  HP_PERI1_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
+/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
+ *  HP_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
+/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
+ *  HP_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
+/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
+ *  HP_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
+/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
+ *  HP_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
+/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
+ *  HP_APM_M4_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
+/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_REG register
+ *  HP_APM_M5_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
+/** INTERRUPT_CORE0_HP_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M5_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_REG register
+ *  HP_APM_M6_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
+/** INTERRUPT_CORE0_HP_APM_M6_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_M  (INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_APM_M6_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_REG register
+ *  HP_PERI0_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16c)
+/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PERI0_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_REG register
+ *  HP_PERI1_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
+/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PERI1_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_REG register
+ *  CPU0_PERI_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
+/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU0_PERI_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_REG register
+ *  CPU1_PERI_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
+/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CPU1_PERI_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_REG register
+ *  FLASH_MSPI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17c)
+/** INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_V << INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_S)
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_FLASH_MSPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LPI_INTR_MAP_REG register
+ *  LPI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
+/** INTERRUPT_CORE0_LPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LPI_INTR_MAP_M  (INTERRUPT_CORE0_LPI_INTR_MAP_V << INTERRUPT_CORE0_LPI_INTR_MAP_S)
+#define INTERRUPT_CORE0_LPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LPI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PMT_INTR_MAP_REG register
+ *  PMT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
+/** INTERRUPT_CORE0_PMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PMT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMT_INTR_MAP_M  (INTERRUPT_CORE0_PMT_INTR_MAP_V << INTERRUPT_CORE0_PMT_INTR_MAP_S)
+#define INTERRUPT_CORE0_PMT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PMT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PMT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SBD_INTR_MAP_REG register
+ *  SBD_INTR mapping register
+ */
+#define INTERRUPT_CORE0_SBD_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
+/** INTERRUPT_CORE0_SBD_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_SBD_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_SBD_INTR_MAP_M  (INTERRUPT_CORE0_SBD_INTR_MAP_V << INTERRUPT_CORE0_SBD_INTR_MAP_S)
+#define INTERRUPT_CORE0_SBD_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_SBD_INTR_MAP_S  0
+/** INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_SBD_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_REG register
+ *  USB_OTGHS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18c)
+/** INTERRUPT_CORE0_USB_OTGHS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_M  (INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_V << INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_S)
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_USB_OTGHS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG register
+ *  USB_OTGHS_ENDP_MULTI_PROC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
+/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_M  (INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S)
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL : R/W; bitpos: [9:8];
+ *  default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_JPEG_INTR_MAP_REG register
+ *  JPEG_INTR mapping register
+ */
+#define INTERRUPT_CORE0_JPEG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
+/** INTERRUPT_CORE0_JPEG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_JPEG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_JPEG_INTR_MAP_M  (INTERRUPT_CORE0_JPEG_INTR_MAP_V << INTERRUPT_CORE0_JPEG_INTR_MAP_S)
+#define INTERRUPT_CORE0_JPEG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_JPEG_INTR_MAP_S  0
+/** INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_JPEG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PPA_INTR_MAP_REG register
+ *  PPA_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PPA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
+/** INTERRUPT_CORE0_PPA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PPA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PPA_INTR_MAP_M  (INTERRUPT_CORE0_PPA_INTR_MAP_V << INTERRUPT_CORE0_PPA_INTR_MAP_S)
+#define INTERRUPT_CORE0_PPA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PPA_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PPA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG register
+ *  CORE0_TRACE_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
+/** INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CORE0_TRACE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG register
+ *  CORE1_TRACE_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a0)
+/** INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CORE1_TRACE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_REG register
+ *  DMA2D_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a4)
+/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_REG register
+ *  DMA2D_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1a8)
+/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_REG register
+ *  DMA2D_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ac)
+/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_REG register
+ *  DMA2D_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b0)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_REG register
+ *  DMA2D_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b4)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_REG register
+ *  DMA2D_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1b8)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_REG register
+ *  DMA2D_OUT_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1bc)
+/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_REG register
+ *  PSRAM_MSPI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c0)
+/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_M  (INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_V << INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_S)
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PSRAM_MSPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_REG register
+ *  HP_SYSREG_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c4)
+/** INTERRUPT_CORE0_HP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_V << INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_SYSREG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PCNT0_INTR_MAP_REG register
+ *  PCNT0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PCNT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c8)
+/** INTERRUPT_CORE0_PCNT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PCNT0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PCNT0_INTR_MAP_M  (INTERRUPT_CORE0_PCNT0_INTR_MAP_V << INTERRUPT_CORE0_PCNT0_INTR_MAP_S)
+#define INTERRUPT_CORE0_PCNT0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PCNT0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PCNT0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PCNT1_INTR_MAP_REG register
+ *  PCNT1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PCNT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1cc)
+/** INTERRUPT_CORE0_PCNT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PCNT1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PCNT1_INTR_MAP_M  (INTERRUPT_CORE0_PCNT1_INTR_MAP_V << INTERRUPT_CORE0_PCNT1_INTR_MAP_S)
+#define INTERRUPT_CORE0_PCNT1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PCNT1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PCNT1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PAU_INTR_MAP_REG register
+ *  HP_PAU_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d0)
+/** INTERRUPT_CORE0_HP_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PAU_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_M  (INTERRUPT_CORE0_HP_PAU_INTR_MAP_V << INTERRUPT_CORE0_HP_PAU_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PAU_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PAU_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_REG register
+ *  HP_PARLIO_RX_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d4)
+/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_M  (INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_V << INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PARLIO_RX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_REG register
+ *  HP_PARLIO_TX_INTR mapping register
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1d8)
+/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_M  (INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_V << INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_S)
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_MAP_S  0
+/** INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_HP_PARLIO_TX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register
+ *  BUS_MONITOR_INTR mapping register
+ */
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1dc)
+/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S)
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S  0
+/** INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_BUS_MONITOR_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_REG register
+ *  MODEM_WIFI_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e0)
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_REG register
+ *  MODEM_WIFI_MAC_NMI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e4)
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_REG register
+ *  MODEM_WIFI_PWR_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1e8)
+/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_REG register
+ *  MODEM_WIFI_BB_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1ec)
+/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_WIFI_BB_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_REG register
+ *  MODEM_BT_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f0)
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_REG register
+ *  MODEM_BT_BB_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f4)
+/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_BB_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_REG register
+ *  MODEM_BT_BB_NMI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1f8)
+/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_REG register
+ *  MODEM_LP_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1fc)
+/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_LP_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_REG register
+ *  MODEM_COEX_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x200)
+/** INTERRUPT_CORE0_MODEM_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_V << INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_COEX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_REG register
+ *  MODEM_BLE_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x204)
+/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_REG register
+ *  MODEM_BLE_SEC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x208)
+/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BLE_SEC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_REG register
+ *  MODEM_I2C_MST_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20c)
+/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_I2C_MST_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_REG register
+ *  MODEM_ZB_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x210)
+/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_ZB_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_REG register
+ *  MODEM_BT_MAC_INT1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x214)
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_V << INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_S)
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_CORDIC_INTR_MAP_REG register
+ *  CORDIC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_CORDIC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x218)
+/** INTERRUPT_CORE0_CORDIC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_CORDIC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_CORDIC_INTR_MAP_M  (INTERRUPT_CORE0_CORDIC_INTR_MAP_V << INTERRUPT_CORE0_CORDIC_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORDIC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_CORDIC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_CORDIC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG register
+ *  ZERO_DET_INTR mapping register
+ */
+#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x21c)
+/** INTERRUPT_CORE0_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_M  (INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V << INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S)
+#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_ZERO_DET_INTR_MAP_S  0
+/** INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_ZERO_DET_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
+ *  LP_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x220)
+/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M  (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_REG register
+ *  LP_TIMER_REG_0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x224)
+/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_TIMER_REG_0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_REG register
+ *  LP_TIMER_REG_1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x228)
+/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_M  (INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_TIMER_REG_1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MB_HP_INTR_MAP_REG register
+ *  MB_HP_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MB_HP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x22c)
+/** INTERRUPT_CORE0_MB_HP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MB_HP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MB_HP_INTR_MAP_M  (INTERRUPT_CORE0_MB_HP_INTR_MAP_V << INTERRUPT_CORE0_MB_HP_INTR_MAP_S)
+#define INTERRUPT_CORE0_MB_HP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MB_HP_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MB_HP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_MB_LP_INTR_MAP_REG register
+ *  MB_LP_INTR mapping register
+ */
+#define INTERRUPT_CORE0_MB_LP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x230)
+/** INTERRUPT_CORE0_MB_LP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_MB_LP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_MB_LP_INTR_MAP_M  (INTERRUPT_CORE0_MB_LP_INTR_MAP_V << INTERRUPT_CORE0_MB_LP_INTR_MAP_S)
+#define INTERRUPT_CORE0_MB_LP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_MB_LP_INTR_MAP_S  0
+/** INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_MB_LP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_REG register
+ *  PMU_REG_0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x234)
+/** INTERRUPT_CORE0_PMU_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_M  (INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_V << INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_S)
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PMU_REG_0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_REG register
+ *  PMU_REG_1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x238)
+/** INTERRUPT_CORE0_PMU_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_M  (INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_V << INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_S)
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_PMU_REG_1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_REG register
+ *  LP_ANAPERI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x23c)
+/** INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_M  (INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_V << INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_ANAPERI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_ADC_INTR_MAP_REG register
+ *  LP_ADC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x240)
+/** INTERRUPT_CORE0_LP_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_ADC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_M  (INTERRUPT_CORE0_LP_ADC_INTR_MAP_V << INTERRUPT_CORE0_LP_ADC_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_ADC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_ADC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_DAC_INTR_MAP_REG register
+ *  LP_DAC_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x244)
+/** INTERRUPT_CORE0_LP_DAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_DAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_M  (INTERRUPT_CORE0_LP_DAC_INTR_MAP_V << INTERRUPT_CORE0_LP_DAC_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_DAC_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_DAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_GPIO_INTR_MAP_REG register
+ *  LP_GPIO_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x248)
+/** INTERRUPT_CORE0_LP_GPIO_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_M  (INTERRUPT_CORE0_LP_GPIO_INTR_MAP_V << INTERRUPT_CORE0_LP_GPIO_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_GPIO_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_GPIO_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG register
+ *  LP_I2C_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24c)
+/** INTERRUPT_CORE0_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_I2C_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_M  (INTERRUPT_CORE0_LP_I2C_INTR_MAP_V << INTERRUPT_CORE0_LP_I2C_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_I2C_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_I2C_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_SPI_INTR_MAP_REG register
+ *  LP_SPI_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x250)
+/** INTERRUPT_CORE0_LP_SPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_SPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_M  (INTERRUPT_CORE0_LP_SPI_INTR_MAP_V << INTERRUPT_CORE0_LP_SPI_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_SPI_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_SPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_REG register
+ *  LP_TOUCH_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x254)
+/** INTERRUPT_CORE0_LP_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_M  (INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_V << INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_TOUCH_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_TSENS_INTR_MAP_REG register
+ *  LP_TSENS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x258)
+/** INTERRUPT_CORE0_LP_TSENS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_M  (INTERRUPT_CORE0_LP_TSENS_INTR_MAP_V << INTERRUPT_CORE0_LP_TSENS_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_TSENS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_TSENS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_UART_INTR_MAP_REG register
+ *  LP_UART_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x25c)
+/** INTERRUPT_CORE0_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_UART_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_UART_INTR_MAP_M  (INTERRUPT_CORE0_LP_UART_INTR_MAP_V << INTERRUPT_CORE0_LP_UART_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_UART_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_UART_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_UART_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_REG register
+ *  LP_EFUSE_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x260)
+/** INTERRUPT_CORE0_LP_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_M  (INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_EFUSE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_SW_INTR_MAP_REG register
+ *  LP_SW_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_SW_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x264)
+/** INTERRUPT_CORE0_LP_SW_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_SW_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SW_INTR_MAP_M  (INTERRUPT_CORE0_LP_SW_INTR_MAP_V << INTERRUPT_CORE0_LP_SW_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_SW_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_SW_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_SW_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_TRNG_INTR_MAP_REG register
+ *  LP_TRNG_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x268)
+/** INTERRUPT_CORE0_LP_TRNG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_M  (INTERRUPT_CORE0_LP_TRNG_INTR_MAP_V << INTERRUPT_CORE0_LP_TRNG_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_TRNG_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_TRNG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_REG register
+ *  LP_SYSREG_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x26c)
+/** INTERRUPT_CORE0_LP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_V << INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_SYSREG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register
+ *  LP_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x270)
+/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG register
+ *  LP_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x274)
+/** INTERRUPT_CORE0_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_REG register
+ *  LP_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x278)
+/** INTERRUPT_CORE0_LP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_REG register
+ *  LP_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x27c)
+/** INTERRUPT_CORE0_LP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_REG register
+ *  LP_PERI0_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x280)
+/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_PERI0_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_REG register
+ *  LP_PERI1_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x284)
+/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_PERI1_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_HUK_INTR_MAP_REG register
+ *  LP_HUK_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x288)
+/** INTERRUPT_CORE0_LP_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_HUK_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_M  (INTERRUPT_CORE0_LP_HUK_INTR_MAP_V << INTERRUPT_CORE0_LP_HUK_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_HUK_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_HUK_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  LP_PERI_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28c)
+/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG register
+ *  LP_AHB_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x290)
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG register
+ *  LP_AHB_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x294)
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  LP_AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x298)
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  LP_AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x29c)
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_REG register
+ *  LP_SW_INVALID_SLEEP_INTR mapping register
+ */
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a0)
+/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_M  (INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_V << INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_S)
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_MAP_S  0
+/** INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V << INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE0_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a4)
+/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S : R/W; bitpos: [5:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S    0x0000003FU
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_M  (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_S)
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_V  0x0000003FU
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_S_S  0
+/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M : R/W; bitpos: [11:6]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M    0x0000003FU
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_M  (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_S)
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_V  0x0000003FU
+#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_M_S  6
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
+ *  Status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2a8)
+/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
+ *  Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_0_M  (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
+#define INTERRUPT_CORE0_INT_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_0_S  0
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
+ *  Status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2ac)
+/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
+ *  63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_1_M  (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
+#define INTERRUPT_CORE0_INT_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_1_S  0
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
+ *  Status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b0)
+/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
+ *  95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_2_M  (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S)
+#define INTERRUPT_CORE0_INT_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_2_S  0
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_3_REG register
+ *  Status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b4)
+/** INTERRUPT_CORE0_INT_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 96 ~
+ *  127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_3_M  (INTERRUPT_CORE0_INT_STATUS_3_V << INTERRUPT_CORE0_INT_STATUS_3_S)
+#define INTERRUPT_CORE0_INT_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_3_S  0
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_4_REG register
+ *  Status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2b8)
+/** INTERRUPT_CORE0_INT_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 128 ~
+ *  159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_4_M  (INTERRUPT_CORE0_INT_STATUS_4_V << INTERRUPT_CORE0_INT_STATUS_4_S)
+#define INTERRUPT_CORE0_INT_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_STATUS_4_S  0
+
+/** INTERRUPT_CORE0_INT_STATUS_REG_5_REG register
+ *  Status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE0_INT_STATUS_REG_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2bc)
+/** INTERRUPT_CORE0_INT_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 160 ~
+ *  168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE0_INT_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE0_INT_STATUS_5_M  (INTERRUPT_CORE0_INT_STATUS_5_V << INTERRUPT_CORE0_INT_STATUS_5_S)
+#define INTERRUPT_CORE0_INT_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE0_INT_STATUS_5_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_0_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c0)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_0_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_1_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c4)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_1_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_2_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c8)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_2_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_3_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2cc)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_3_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_4_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d0)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_4_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_5_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_S_STATUS_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d4)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources with
+ *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_S_STATUS_5_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_0_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2d8)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_0_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_1_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2dc)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_1_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_2_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e0)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_2_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_3_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e4)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_3_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_4_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2e8)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_4_S  0
+
+/** INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_5_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE0_SRC_PASS_IN_M_STATUS_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2ec)
+/** INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources with
+ *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_M  (INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_S)
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE0_INT_SRC_PASS_IN_M_STATUS_5_S  0
+
+/** INTERRUPT_CORE0_CONFIG_STATE_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE0_CONFIG_STATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f0)
+/** INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR    (BIT(0))
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_M  (INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_V << INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_S)
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_V  0x00000001U
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_S_ERR_S  0
+/** INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR    (BIT(1))
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_M  (INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_V << INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_S)
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_V  0x00000001U
+#define INTERRUPT_CORE0_SIG_IDX_ASSERT_M_ERR_S  1
+
+/** INTERRUPT_CORE0_S_STATUS_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE0_S_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f4)
+/** INTERRUPT_CORE0_INT_S_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_INT_S_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_S_STATUS_M  (INTERRUPT_CORE0_INT_S_STATUS_V << INTERRUPT_CORE0_INT_S_STATUS_S)
+#define INTERRUPT_CORE0_INT_S_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_S_STATUS_S  0
+
+/** INTERRUPT_CORE0_M_STATUS_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE0_M_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2f8)
+/** INTERRUPT_CORE0_INT_M_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE0_INT_M_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_M_STATUS_M  (INTERRUPT_CORE0_INT_M_STATUS_V << INTERRUPT_CORE0_INT_M_STATUS_S)
+#define INTERRUPT_CORE0_INT_M_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE0_INT_M_STATUS_S  0
+
+/** INTERRUPT_CORE0_CLOCK_GATE_REG register
+ *  Interrupt clock gating configure register
+ */
+#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2fc)
+/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Interrupt clock gating configure register
+ */
+#define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE0_REG_CLK_EN_M  (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
+#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
+#define INTERRUPT_CORE0_REG_CLK_EN_S  0
+
+/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
+ *  Version control register
+ */
+#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
+/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38834448;
+ *  Version control register
+ */
+#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE0_INTERRUPT_DATE_M  (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
+#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/interrupt_core0_struct.h b/components/soc/esp32s31/register/soc/interrupt_core0_struct.h
new file mode 100644
index 00000000000..33a84aef60d
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/interrupt_core0_struct.h
@@ -0,0 +1,4153 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of sys_icm_intr_map register
+ *  SYS_ICM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sys_icm_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sys_icm_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sys_icm_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sys_icm_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_sys_icm_intr_map_reg_t;
+
+/** Type of axi_perf_mon_intr_map register
+ *  AXI_PERF_MON_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_perf_mon_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_perf_mon_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_perf_mon_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_perf_mon_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_perf_mon_intr_map_reg_t;
+
+/** Type of usb_device_intr_map register
+ *  USB_DEVICE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_device_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_device_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_device_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_device_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_usb_device_intr_map_reg_t;
+
+/** Type of sdio_host_intr_map register
+ *  SDIO_HOST_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sdio_host_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sdio_host_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sdio_host_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sdio_host_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_sdio_host_intr_map_reg_t;
+
+/** Type of spi2_intr_map register
+ *  SPI2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** spi2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t spi2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** spi2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t spi2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_spi2_intr_map_reg_t;
+
+/** Type of spi3_intr_map register
+ *  SPI3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** spi3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t spi3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** spi3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t spi3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_spi3_intr_map_reg_t;
+
+/** Type of i2s0_intr_map register
+ *  I2S0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2s0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2s0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2s0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2s0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_i2s0_intr_map_reg_t;
+
+/** Type of i2s1_intr_map register
+ *  I2S1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2s1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2s1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2s1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_i2s1_intr_map_reg_t;
+
+/** Type of uhci0_intr_map register
+ *  UHCI0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uhci0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uhci0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uhci0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_uhci0_intr_map_reg_t;
+
+/** Type of uart0_intr_map register
+ *  UART0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_uart0_intr_map_reg_t;
+
+/** Type of uart1_intr_map register
+ *  UART1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_uart1_intr_map_reg_t;
+
+/** Type of uart2_intr_map register
+ *  UART2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_uart2_intr_map_reg_t;
+
+/** Type of uart3_intr_map register
+ *  UART3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_uart3_intr_map_reg_t;
+
+/** Type of lcd_cam_intr_map register
+ *  LCD_CAM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lcd_cam_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lcd_cam_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lcd_cam_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lcd_cam_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lcd_cam_intr_map_reg_t;
+
+/** Type of pwm0_intr_map register
+ *  PWM0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pwm0_intr_map_reg_t;
+
+/** Type of pwm1_intr_map register
+ *  PWM1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pwm1_intr_map_reg_t;
+
+/** Type of pwm2_intr_map register
+ *  PWM2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pwm2_intr_map_reg_t;
+
+/** Type of pwm3_intr_map register
+ *  PWM3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pwm3_intr_map_reg_t;
+
+/** Type of can0_intr_map register
+ *  CAN0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_can0_intr_map_reg_t;
+
+/** Type of can0_timer_intr_map register
+ *  CAN0_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can0_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can0_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can0_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can0_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_can0_timer_intr_map_reg_t;
+
+/** Type of can1_intr_map register
+ *  CAN1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_can1_intr_map_reg_t;
+
+/** Type of can1_timer_intr_map register
+ *  CAN1_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can1_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can1_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can1_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can1_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_can1_timer_intr_map_reg_t;
+
+/** Type of rmt_intr_map register
+ *  RMT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rmt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rmt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rmt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_rmt_intr_map_reg_t;
+
+/** Type of i2c0_intr_map register
+ *  I2C0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2c0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2c0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2c0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2c0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_i2c0_intr_map_reg_t;
+
+/** Type of i2c1_intr_map register
+ *  I2C1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2c1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2c1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2c1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2c1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_i2c1_intr_map_reg_t;
+
+/** Type of timergrp0_t0_intr_map register
+ *  TIMERGRP0_T0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_t0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_t0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_t0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_t0_intr_map_reg_t;
+
+/** Type of timergrp0_t1_intr_map register
+ *  TIMERGRP0_T1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_t1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_t1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_t1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_t1_intr_map_reg_t;
+
+/** Type of timergrp0_wdt_intr_map register
+ *  TIMERGRP0_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp0_wdt_intr_map_reg_t;
+
+/** Type of timergrp1_t0_intr_map register
+ *  TIMERGRP1_T0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_t0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_t0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_t0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_t0_intr_map_reg_t;
+
+/** Type of timergrp1_t1_intr_map register
+ *  TIMERGRP1_T1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_t1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_t1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_t1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_t1_intr_map_reg_t;
+
+/** Type of timergrp1_wdt_intr_map register
+ *  TIMERGRP1_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_timergrp1_wdt_intr_map_reg_t;
+
+/** Type of ledc0_intr_map register
+ *  LEDC0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ledc0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ledc0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ledc0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ledc0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ledc0_intr_map_reg_t;
+
+/** Type of ledc1_intr_map register
+ *  LEDC1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ledc1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ledc1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ledc1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ledc1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ledc1_intr_map_reg_t;
+
+/** Type of systimer_target0_intr_map register
+ *  SYSTIMER_TARGET0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target0_intr_map_reg_t;
+
+/** Type of systimer_target1_intr_map register
+ *  SYSTIMER_TARGET1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target1_intr_map_reg_t;
+
+/** Type of systimer_target2_intr_map register
+ *  SYSTIMER_TARGET2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_systimer_target2_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch0_intr_map register
+ *  AHB_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch1_intr_map register
+ *  AHB_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch2_intr_map register
+ *  AHB_PDMA_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch2_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch3_intr_map register
+ *  AHB_PDMA_IN_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch3_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch4_intr_map register
+ *  AHB_PDMA_IN_CH4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_in_ch4_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch0_intr_map register
+ *  AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch1_intr_map register
+ *  AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch2_intr_map register
+ *  AHB_PDMA_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch2_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch3_intr_map register
+ *  AHB_PDMA_OUT_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch3_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch4_intr_map register
+ *  AHB_PDMA_OUT_CH4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ahb_pdma_out_ch4_intr_map_reg_t;
+
+/** Type of asrc_chnl0_intr_map register
+ *  ASRC_CHNL0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** asrc_chnl0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t asrc_chnl0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** asrc_chnl0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t asrc_chnl0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_asrc_chnl0_intr_map_reg_t;
+
+/** Type of asrc_chnl1_intr_map register
+ *  ASRC_CHNL1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** asrc_chnl1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t asrc_chnl1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** asrc_chnl1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t asrc_chnl1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_asrc_chnl1_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch0_intr_map register
+ *  AXI_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch1_intr_map register
+ *  AXI_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch2_intr_map register
+ *  AXI_PDMA_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_in_ch2_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch0_intr_map register
+ *  AXI_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch1_intr_map register
+ *  AXI_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch2_intr_map register
+ *  AXI_PDMA_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_axi_pdma_out_ch2_intr_map_reg_t;
+
+/** Type of rsa_intr_map register
+ *  RSA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rsa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rsa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rsa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rsa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_rsa_intr_map_reg_t;
+
+/** Type of aes_intr_map register
+ *  AES_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** aes_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t aes_intr_map:6;
+        uint32_t reserved_6:2;
+        /** aes_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t aes_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_aes_intr_map_reg_t;
+
+/** Type of sha_intr_map register
+ *  SHA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sha_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sha_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sha_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sha_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_sha_intr_map_reg_t;
+
+/** Type of ecc_intr_map register
+ *  ECC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ecc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ecc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ecc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ecc_intr_map_reg_t;
+
+/** Type of ecdsa_intr_map register
+ *  ECDSA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ecdsa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ecdsa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ecdsa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ecdsa_intr_map_reg_t;
+
+/** Type of km_intr_map register
+ *  KM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** km_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t km_intr_map:6;
+        uint32_t reserved_6:2;
+        /** km_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t km_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_km_intr_map_reg_t;
+
+/** Type of rma_intr_map register
+ *  RMA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rma_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rma_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rma_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rma_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_rma_intr_map_reg_t;
+
+/** Type of gpio_intr0_map register
+ *  GPIO_INTR0 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr0_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr0_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr0_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_intr0_map_reg_t;
+
+/** Type of gpio_intr1_map register
+ *  GPIO_INTR1 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr1_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr1_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr1_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_intr1_map_reg_t;
+
+/** Type of gpio_intr2_map register
+ *  GPIO_INTR2 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr2_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr2_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr2_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_intr2_map_reg_t;
+
+/** Type of gpio_intr3_map register
+ *  GPIO_INTR3 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr3_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr3_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr3_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_gpio_intr3_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_0_map register
+ *  CPU_INTR_FROM_CPU_0 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_0_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_0_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_0_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_1_map register
+ *  CPU_INTR_FROM_CPU_1 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_1_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_1_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_1_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_2_map register
+ *  CPU_INTR_FROM_CPU_2 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_2_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_2_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_2_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_3_map register
+ *  CPU_INTR_FROM_CPU_3 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_3_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_3_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_3_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t;
+
+/** Type of cache_intr_map register
+ *  CACHE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cache_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cache_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cache_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cache_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cache_intr_map_reg_t;
+
+/** Type of cpu_apm_m0_intr_map register
+ *  CPU_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_apm_m0_intr_map_reg_t;
+
+/** Type of cpu_apm_m1_intr_map register
+ *  CPU_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_apm_m1_intr_map_reg_t;
+
+/** Type of cpu_apm_m2_intr_map register
+ *  CPU_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_apm_m2_intr_map_reg_t;
+
+/** Type of cpu_apm_m3_intr_map register
+ *  CPU_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_apm_m3_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m0_intr_map register
+ *  HP_MEM_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m0_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m1_intr_map register
+ *  HP_MEM_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m1_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m2_intr_map register
+ *  HP_MEM_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m2_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m3_intr_map register
+ *  HP_MEM_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m3_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m4_intr_map register
+ *  HP_MEM_APM_M4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m4_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m5_intr_map register
+ *  HP_MEM_APM_M5_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m5_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m5_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m5_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m5_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_mem_apm_m5_intr_map_reg_t;
+
+/** Type of cpu_peri0_timeout_intr_map register
+ *  CPU_PERI0_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_peri0_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_peri0_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_peri0_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_peri0_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_peri0_timeout_intr_map_reg_t;
+
+/** Type of cpu_peri1_timeout_intr_map register
+ *  CPU_PERI1_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_peri1_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_peri1_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_peri1_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_peri1_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu_peri1_timeout_intr_map_reg_t;
+
+/** Type of hp_peri0_timeout_intr_map register
+ *  HP_PERI0_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri0_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri0_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri0_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_peri0_timeout_intr_map_reg_t;
+
+/** Type of hp_peri1_timeout_intr_map register
+ *  HP_PERI1_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri1_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri1_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri1_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_peri1_timeout_intr_map_reg_t;
+
+/** Type of hp_apm_m0_intr_map register
+ *  HP_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m0_intr_map_reg_t;
+
+/** Type of hp_apm_m1_intr_map register
+ *  HP_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m1_intr_map_reg_t;
+
+/** Type of hp_apm_m2_intr_map register
+ *  HP_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m2_intr_map_reg_t;
+
+/** Type of hp_apm_m3_intr_map register
+ *  HP_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m3_intr_map_reg_t;
+
+/** Type of hp_apm_m4_intr_map register
+ *  HP_APM_M4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m4_intr_map_reg_t;
+
+/** Type of hp_apm_m5_intr_map register
+ *  HP_APM_M5_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m5_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m5_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m5_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m5_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m5_intr_map_reg_t;
+
+/** Type of hp_apm_m6_intr_map register
+ *  HP_APM_M6_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m6_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m6_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m6_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m6_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_apm_m6_intr_map_reg_t;
+
+/** Type of hp_peri0_pms_intr_map register
+ *  HP_PERI0_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri0_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri0_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri0_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_peri0_pms_intr_map_reg_t;
+
+/** Type of hp_peri1_pms_intr_map register
+ *  HP_PERI1_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri1_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri1_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri1_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_peri1_pms_intr_map_reg_t;
+
+/** Type of cpu0_peri_pms_intr_map register
+ *  CPU0_PERI_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu0_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu0_peri_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu0_peri_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu0_peri_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu0_peri_pms_intr_map_reg_t;
+
+/** Type of cpu1_peri_pms_intr_map register
+ *  CPU1_PERI_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu1_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu1_peri_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu1_peri_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu1_peri_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cpu1_peri_pms_intr_map_reg_t;
+
+/** Type of flash_mspi_intr_map register
+ *  FLASH_MSPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** flash_mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t flash_mspi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** flash_mspi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t flash_mspi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_flash_mspi_intr_map_reg_t;
+
+/** Type of lpi_intr_map register
+ *  LPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lpi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lpi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lpi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lpi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lpi_intr_map_reg_t;
+
+/** Type of pmt_intr_map register
+ *  PMT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pmt_intr_map_reg_t;
+
+/** Type of sbd_intr_map register
+ *  SBD_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sbd_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sbd_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sbd_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sbd_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_sbd_intr_map_reg_t;
+
+/** Type of usb_otghs_intr_map register
+ *  USB_OTGHS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_otghs_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_otghs_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_otghs_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_otghs_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_usb_otghs_intr_map_reg_t;
+
+/** Type of usb_otghs_endp_multi_proc_intr_map register
+ *  USB_OTGHS_ENDP_MULTI_PROC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_otghs_endp_multi_proc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_otghs_endp_multi_proc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_otghs_endp_multi_proc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_otghs_endp_multi_proc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_usb_otghs_endp_multi_proc_intr_map_reg_t;
+
+/** Type of jpeg_intr_map register
+ *  JPEG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** jpeg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t jpeg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** jpeg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t jpeg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_jpeg_intr_map_reg_t;
+
+/** Type of ppa_intr_map register
+ *  PPA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ppa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ppa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ppa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ppa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_ppa_intr_map_reg_t;
+
+/** Type of core0_trace_intr_map register
+ *  CORE0_TRACE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_trace_intr_map:6;
+        uint32_t reserved_6:2;
+        /** core0_trace_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t core0_trace_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_core0_trace_intr_map_reg_t;
+
+/** Type of core1_trace_intr_map register
+ *  CORE1_TRACE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** core1_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_trace_intr_map:6;
+        uint32_t reserved_6:2;
+        /** core1_trace_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t core1_trace_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_core1_trace_intr_map_reg_t;
+
+/** Type of dma2d_in_ch0_intr_map register
+ *  DMA2D_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_in_ch0_intr_map_reg_t;
+
+/** Type of dma2d_in_ch1_intr_map register
+ *  DMA2D_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_in_ch1_intr_map_reg_t;
+
+/** Type of dma2d_in_ch2_intr_map register
+ *  DMA2D_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_in_ch2_intr_map_reg_t;
+
+/** Type of dma2d_out_ch0_intr_map register
+ *  DMA2D_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch0_intr_map_reg_t;
+
+/** Type of dma2d_out_ch1_intr_map register
+ *  DMA2D_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch1_intr_map_reg_t;
+
+/** Type of dma2d_out_ch2_intr_map register
+ *  DMA2D_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch2_intr_map_reg_t;
+
+/** Type of dma2d_out_ch3_intr_map register
+ *  DMA2D_OUT_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_dma2d_out_ch3_intr_map_reg_t;
+
+/** Type of psram_mspi_intr_map register
+ *  PSRAM_MSPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** psram_mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t psram_mspi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** psram_mspi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t psram_mspi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_psram_mspi_intr_map_reg_t;
+
+/** Type of hp_sysreg_intr_map register
+ *  HP_SYSREG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_sysreg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_sysreg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_sysreg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_sysreg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_sysreg_intr_map_reg_t;
+
+/** Type of pcnt0_intr_map register
+ *  PCNT0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pcnt0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pcnt0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pcnt0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pcnt0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pcnt0_intr_map_reg_t;
+
+/** Type of pcnt1_intr_map register
+ *  PCNT1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pcnt1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pcnt1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pcnt1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pcnt1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pcnt1_intr_map_reg_t;
+
+/** Type of hp_pau_intr_map register
+ *  HP_PAU_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_pau_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_pau_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_pau_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_pau_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_pau_intr_map_reg_t;
+
+/** Type of hp_parlio_rx_intr_map register
+ *  HP_PARLIO_RX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_parlio_rx_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_parlio_rx_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_parlio_rx_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_parlio_rx_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_parlio_rx_intr_map_reg_t;
+
+/** Type of hp_parlio_tx_intr_map register
+ *  HP_PARLIO_TX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_parlio_tx_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_parlio_tx_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_parlio_tx_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_parlio_tx_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_hp_parlio_tx_intr_map_reg_t;
+
+/** Type of bus_monitor_intr_map register
+ *  BUS_MONITOR_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** bus_monitor_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t bus_monitor_intr_map:6;
+        uint32_t reserved_6:2;
+        /** bus_monitor_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t bus_monitor_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_bus_monitor_intr_map_reg_t;
+
+/** Type of modem_wifi_mac_intr_map register
+ *  MODEM_WIFI_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_wifi_mac_intr_map_reg_t;
+
+/** Type of modem_wifi_mac_nmi_intr_map register
+ *  MODEM_WIFI_MAC_NMI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_mac_nmi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_mac_nmi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_mac_nmi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_mac_nmi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_wifi_mac_nmi_intr_map_reg_t;
+
+/** Type of modem_wifi_pwr_intr_map register
+ *  MODEM_WIFI_PWR_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_pwr_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_pwr_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_pwr_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_wifi_pwr_intr_map_reg_t;
+
+/** Type of modem_wifi_bb_intr_map register
+ *  MODEM_WIFI_BB_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_bb_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_bb_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_bb_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_wifi_bb_intr_map_reg_t;
+
+/** Type of modem_bt_mac_intr_map register
+ *  MODEM_BT_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_bt_mac_intr_map_reg_t;
+
+/** Type of modem_bt_bb_intr_map register
+ *  MODEM_BT_BB_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_bb_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_bb_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_bb_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_bt_bb_intr_map_reg_t;
+
+/** Type of modem_bt_bb_nmi_intr_map register
+ *  MODEM_BT_BB_NMI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_bb_nmi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_bb_nmi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_bb_nmi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_bb_nmi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_bt_bb_nmi_intr_map_reg_t;
+
+/** Type of modem_lp_timer_intr_map register
+ *  MODEM_LP_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_lp_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_lp_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_lp_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_lp_timer_intr_map_reg_t;
+
+/** Type of modem_coex_intr_map register
+ *  MODEM_COEX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_coex_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_coex_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_coex_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_coex_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_coex_intr_map_reg_t;
+
+/** Type of modem_ble_timer_intr_map register
+ *  MODEM_BLE_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_ble_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_ble_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_ble_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_ble_timer_intr_map_reg_t;
+
+/** Type of modem_ble_sec_intr_map register
+ *  MODEM_BLE_SEC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_ble_sec_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_ble_sec_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_ble_sec_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_ble_sec_intr_map_reg_t;
+
+/** Type of modem_i2c_mst_intr_map register
+ *  MODEM_I2C_MST_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_i2c_mst_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_i2c_mst_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_i2c_mst_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_i2c_mst_intr_map_reg_t;
+
+/** Type of modem_zb_mac_intr_map register
+ *  MODEM_ZB_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_zb_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_zb_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_zb_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_zb_mac_intr_map_reg_t;
+
+/** Type of modem_bt_mac_int1_intr_map register
+ *  MODEM_BT_MAC_INT1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_mac_int1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_mac_int1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_mac_int1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_mac_int1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_modem_bt_mac_int1_intr_map_reg_t;
+
+/** Type of cordic_intr_map register
+ *  CORDIC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cordic_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cordic_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cordic_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cordic_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_cordic_intr_map_reg_t;
+
+/** Type of zero_det_intr_map register
+ *  ZERO_DET_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** zero_det_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t zero_det_intr_map:6;
+        uint32_t reserved_6:2;
+        /** zero_det_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t zero_det_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_zero_det_intr_map_reg_t;
+
+/** Type of lp_wdt_intr_map register
+ *  LP_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_wdt_intr_map_reg_t;
+
+/** Type of lp_timer_reg_0_intr_map register
+ *  LP_TIMER_REG_0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_timer_reg_0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_timer_reg_0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_timer_reg_0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_timer_reg_0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_timer_reg_0_intr_map_reg_t;
+
+/** Type of lp_timer_reg_1_intr_map register
+ *  LP_TIMER_REG_1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_timer_reg_1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_timer_reg_1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_timer_reg_1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_timer_reg_1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_timer_reg_1_intr_map_reg_t;
+
+/** Type of mb_hp_intr_map register
+ *  MB_HP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** mb_hp_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t mb_hp_intr_map:6;
+        uint32_t reserved_6:2;
+        /** mb_hp_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t mb_hp_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_mb_hp_intr_map_reg_t;
+
+/** Type of mb_lp_intr_map register
+ *  MB_LP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** mb_lp_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t mb_lp_intr_map:6;
+        uint32_t reserved_6:2;
+        /** mb_lp_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t mb_lp_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_mb_lp_intr_map_reg_t;
+
+/** Type of pmu_reg_0_intr_map register
+ *  PMU_REG_0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmu_reg_0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmu_reg_0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmu_reg_0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmu_reg_0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pmu_reg_0_intr_map_reg_t;
+
+/** Type of pmu_reg_1_intr_map register
+ *  PMU_REG_1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmu_reg_1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmu_reg_1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmu_reg_1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmu_reg_1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_pmu_reg_1_intr_map_reg_t;
+
+/** Type of lp_anaperi_intr_map register
+ *  LP_ANAPERI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_anaperi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_anaperi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_anaperi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_anaperi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_anaperi_intr_map_reg_t;
+
+/** Type of lp_adc_intr_map register
+ *  LP_ADC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_adc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_adc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_adc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_adc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_adc_intr_map_reg_t;
+
+/** Type of lp_dac_intr_map register
+ *  LP_DAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_dac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_dac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_dac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_dac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_dac_intr_map_reg_t;
+
+/** Type of lp_gpio_intr_map register
+ *  LP_GPIO_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_gpio_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_gpio_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_gpio_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_gpio_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_gpio_intr_map_reg_t;
+
+/** Type of lp_i2c_intr_map register
+ *  LP_I2C_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_i2c_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_i2c_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_i2c_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_i2c_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_i2c_intr_map_reg_t;
+
+/** Type of lp_spi_intr_map register
+ *  LP_SPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_spi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_spi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_spi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_spi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_spi_intr_map_reg_t;
+
+/** Type of lp_touch_intr_map register
+ *  LP_TOUCH_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_touch_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_touch_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_touch_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_touch_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_touch_intr_map_reg_t;
+
+/** Type of lp_tsens_intr_map register
+ *  LP_TSENS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_tsens_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_tsens_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_tsens_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_tsens_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_tsens_intr_map_reg_t;
+
+/** Type of lp_uart_intr_map register
+ *  LP_UART_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_uart_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_uart_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_uart_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_uart_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_uart_intr_map_reg_t;
+
+/** Type of lp_efuse_intr_map register
+ *  LP_EFUSE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_efuse_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_efuse_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_efuse_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_efuse_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_efuse_intr_map_reg_t;
+
+/** Type of lp_sw_intr_map register
+ *  LP_SW_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sw_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sw_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sw_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sw_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_sw_intr_map_reg_t;
+
+/** Type of lp_trng_intr_map register
+ *  LP_TRNG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_trng_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_trng_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_trng_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_trng_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_trng_intr_map_reg_t;
+
+/** Type of lp_sysreg_intr_map register
+ *  LP_SYSREG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sysreg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sysreg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sysreg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sysreg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_sysreg_intr_map_reg_t;
+
+/** Type of lp_apm_m0_intr_map register
+ *  LP_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_apm_m0_intr_map_reg_t;
+
+/** Type of lp_apm_m1_intr_map register
+ *  LP_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_apm_m1_intr_map_reg_t;
+
+/** Type of lp_apm_m2_intr_map register
+ *  LP_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_apm_m2_intr_map_reg_t;
+
+/** Type of lp_apm_m3_intr_map register
+ *  LP_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_apm_m3_intr_map_reg_t;
+
+/** Type of lp_peri0_pms_intr_map register
+ *  LP_PERI0_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri0_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri0_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri0_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri0_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_peri0_pms_intr_map_reg_t;
+
+/** Type of lp_peri1_pms_intr_map register
+ *  LP_PERI1_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri1_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri1_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri1_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri1_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_peri1_pms_intr_map_reg_t;
+
+/** Type of lp_huk_intr_map register
+ *  LP_HUK_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_huk_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_huk_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_huk_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_huk_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_huk_intr_map_reg_t;
+
+/** Type of lp_peri_timeout_intr_map register
+ *  LP_PERI_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_peri_timeout_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_in_ch0_intr_map register
+ *  LP_AHB_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_ahb_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_in_ch1_intr_map register
+ *  LP_AHB_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_ahb_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_out_ch0_intr_map register
+ *  LP_AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_ahb_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_out_ch1_intr_map register
+ *  LP_AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_ahb_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of lp_sw_invalid_sleep_intr_map register
+ *  LP_SW_INVALID_SLEEP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sw_invalid_sleep_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sw_invalid_sleep_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sw_invalid_sleep_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sw_invalid_sleep_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core0_lp_sw_invalid_sleep_intr_map_reg_t;
+
+/** Type of sig_idx_assert_in_sec register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_sig_idx_assert_in_s : R/W; bitpos: [5:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_sig_idx_assert_in_s:6;
+        /** int_sig_idx_assert_in_m : R/W; bitpos: [11:6]; default: 0;
+         *  reserved
+         */
+        uint32_t int_sig_idx_assert_in_m:6;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} interrupt_core0_sig_idx_assert_in_sec_reg_t;
+
+/** Type of clock_gate register
+ *  Interrupt clock gating configure register
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Interrupt clock gating configure register
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_core0_clock_gate_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of int_status_reg_0 register
+ *  Status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
+         *  Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_0_reg_t;
+
+/** Type of int_status_reg_1 register
+ *  Status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
+         *  63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_1_reg_t;
+
+/** Type of int_status_reg_2 register
+ *  Status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
+         *  95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_2_reg_t;
+
+/** Type of int_status_reg_3 register
+ *  Status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 96 ~
+         *  127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_3_reg_t;
+
+/** Type of int_status_reg_4 register
+ *  Status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 128 ~
+         *  159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_4_reg_t;
+
+/** Type of int_status_reg_5 register
+ *  Status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 160 ~
+         *  168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core0_int_status_reg_5_reg_t;
+
+/** Type of src_pass_in_s_status_0 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_0_reg_t;
+
+/** Type of src_pass_in_s_status_1 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_1_reg_t;
+
+/** Type of src_pass_in_s_status_2 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_2_reg_t;
+
+/** Type of src_pass_in_s_status_3 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_3_reg_t;
+
+/** Type of src_pass_in_s_status_4 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_4_reg_t;
+
+/** Type of src_pass_in_s_status_5 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources with
+         *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_s_status_5_reg_t;
+
+/** Type of src_pass_in_m_status_0 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_0_reg_t;
+
+/** Type of src_pass_in_m_status_1 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_1_reg_t;
+
+/** Type of src_pass_in_m_status_2 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_2_reg_t;
+
+/** Type of src_pass_in_m_status_3 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_3_reg_t;
+
+/** Type of src_pass_in_m_status_4 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_4_reg_t;
+
+/** Type of src_pass_in_m_status_5 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources with
+         *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core0_src_pass_in_m_status_5_reg_t;
+
+/** Type of config_state register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sig_idx_assert_s_err : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sig_idx_assert_s_err:1;
+        /** sig_idx_assert_m_err : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t sig_idx_assert_m_err:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} interrupt_core0_config_state_reg_t;
+
+/** Type of s_status register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_s_status : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_s_status:32;
+    };
+    uint32_t val;
+} interrupt_core0_s_status_reg_t;
+
+/** Type of m_status register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_m_status : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_m_status:32;
+    };
+    uint32_t val;
+} interrupt_core0_m_status_reg_t;
+
+
+/** Group: Version Register */
+/** Type of interrupt_date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** interrupt_date : R/W; bitpos: [27:0]; default: 38834448;
+         *  Version control register
+         */
+        uint32_t interrupt_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_core0_interrupt_date_reg_t;
+
+
+typedef struct {
+    volatile interrupt_core0_sys_icm_intr_map_reg_t sys_icm_intr_map;
+    volatile interrupt_core0_axi_perf_mon_intr_map_reg_t axi_perf_mon_intr_map;
+    volatile interrupt_core0_usb_device_intr_map_reg_t usb_device_intr_map;
+    volatile interrupt_core0_sdio_host_intr_map_reg_t sdio_host_intr_map;
+    volatile interrupt_core0_spi2_intr_map_reg_t spi2_intr_map;
+    volatile interrupt_core0_spi3_intr_map_reg_t spi3_intr_map;
+    volatile interrupt_core0_i2s0_intr_map_reg_t i2s0_intr_map;
+    volatile interrupt_core0_i2s1_intr_map_reg_t i2s1_intr_map;
+    volatile interrupt_core0_uhci0_intr_map_reg_t uhci0_intr_map;
+    volatile interrupt_core0_uart0_intr_map_reg_t uart0_intr_map;
+    volatile interrupt_core0_uart1_intr_map_reg_t uart1_intr_map;
+    volatile interrupt_core0_uart2_intr_map_reg_t uart2_intr_map;
+    volatile interrupt_core0_uart3_intr_map_reg_t uart3_intr_map;
+    volatile interrupt_core0_lcd_cam_intr_map_reg_t lcd_cam_intr_map;
+    volatile interrupt_core0_pwm0_intr_map_reg_t pwm0_intr_map;
+    volatile interrupt_core0_pwm1_intr_map_reg_t pwm1_intr_map;
+    volatile interrupt_core0_pwm2_intr_map_reg_t pwm2_intr_map;
+    volatile interrupt_core0_pwm3_intr_map_reg_t pwm3_intr_map;
+    volatile interrupt_core0_can0_intr_map_reg_t can0_intr_map;
+    volatile interrupt_core0_can0_timer_intr_map_reg_t can0_timer_intr_map;
+    volatile interrupt_core0_can1_intr_map_reg_t can1_intr_map;
+    volatile interrupt_core0_can1_timer_intr_map_reg_t can1_timer_intr_map;
+    volatile interrupt_core0_rmt_intr_map_reg_t rmt_intr_map;
+    volatile interrupt_core0_i2c0_intr_map_reg_t i2c0_intr_map;
+    volatile interrupt_core0_i2c1_intr_map_reg_t i2c1_intr_map;
+    volatile interrupt_core0_timergrp0_t0_intr_map_reg_t timergrp0_t0_intr_map;
+    volatile interrupt_core0_timergrp0_t1_intr_map_reg_t timergrp0_t1_intr_map;
+    volatile interrupt_core0_timergrp0_wdt_intr_map_reg_t timergrp0_wdt_intr_map;
+    volatile interrupt_core0_timergrp1_t0_intr_map_reg_t timergrp1_t0_intr_map;
+    volatile interrupt_core0_timergrp1_t1_intr_map_reg_t timergrp1_t1_intr_map;
+    volatile interrupt_core0_timergrp1_wdt_intr_map_reg_t timergrp1_wdt_intr_map;
+    volatile interrupt_core0_ledc0_intr_map_reg_t ledc0_intr_map;
+    volatile interrupt_core0_ledc1_intr_map_reg_t ledc1_intr_map;
+    volatile interrupt_core0_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
+    volatile interrupt_core0_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
+    volatile interrupt_core0_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
+    volatile interrupt_core0_ahb_pdma_in_ch0_intr_map_reg_t ahb_pdma_in_ch0_intr_map;
+    volatile interrupt_core0_ahb_pdma_in_ch1_intr_map_reg_t ahb_pdma_in_ch1_intr_map;
+    volatile interrupt_core0_ahb_pdma_in_ch2_intr_map_reg_t ahb_pdma_in_ch2_intr_map;
+    volatile interrupt_core0_ahb_pdma_in_ch3_intr_map_reg_t ahb_pdma_in_ch3_intr_map;
+    volatile interrupt_core0_ahb_pdma_in_ch4_intr_map_reg_t ahb_pdma_in_ch4_intr_map;
+    volatile interrupt_core0_ahb_pdma_out_ch0_intr_map_reg_t ahb_pdma_out_ch0_intr_map;
+    volatile interrupt_core0_ahb_pdma_out_ch1_intr_map_reg_t ahb_pdma_out_ch1_intr_map;
+    volatile interrupt_core0_ahb_pdma_out_ch2_intr_map_reg_t ahb_pdma_out_ch2_intr_map;
+    volatile interrupt_core0_ahb_pdma_out_ch3_intr_map_reg_t ahb_pdma_out_ch3_intr_map;
+    volatile interrupt_core0_ahb_pdma_out_ch4_intr_map_reg_t ahb_pdma_out_ch4_intr_map;
+    volatile interrupt_core0_asrc_chnl0_intr_map_reg_t asrc_chnl0_intr_map;
+    volatile interrupt_core0_asrc_chnl1_intr_map_reg_t asrc_chnl1_intr_map;
+    volatile interrupt_core0_axi_pdma_in_ch0_intr_map_reg_t axi_pdma_in_ch0_intr_map;
+    volatile interrupt_core0_axi_pdma_in_ch1_intr_map_reg_t axi_pdma_in_ch1_intr_map;
+    volatile interrupt_core0_axi_pdma_in_ch2_intr_map_reg_t axi_pdma_in_ch2_intr_map;
+    volatile interrupt_core0_axi_pdma_out_ch0_intr_map_reg_t axi_pdma_out_ch0_intr_map;
+    volatile interrupt_core0_axi_pdma_out_ch1_intr_map_reg_t axi_pdma_out_ch1_intr_map;
+    volatile interrupt_core0_axi_pdma_out_ch2_intr_map_reg_t axi_pdma_out_ch2_intr_map;
+    volatile interrupt_core0_rsa_intr_map_reg_t rsa_intr_map;
+    volatile interrupt_core0_aes_intr_map_reg_t aes_intr_map;
+    volatile interrupt_core0_sha_intr_map_reg_t sha_intr_map;
+    volatile interrupt_core0_ecc_intr_map_reg_t ecc_intr_map;
+    volatile interrupt_core0_ecdsa_intr_map_reg_t ecdsa_intr_map;
+    volatile interrupt_core0_km_intr_map_reg_t km_intr_map;
+    volatile interrupt_core0_rma_intr_map_reg_t rma_intr_map;
+    volatile interrupt_core0_gpio_intr0_map_reg_t gpio_intr0_map;
+    volatile interrupt_core0_gpio_intr1_map_reg_t gpio_intr1_map;
+    volatile interrupt_core0_gpio_intr2_map_reg_t gpio_intr2_map;
+    volatile interrupt_core0_gpio_intr3_map_reg_t gpio_intr3_map;
+    volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
+    volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
+    volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
+    volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
+    volatile interrupt_core0_cache_intr_map_reg_t cache_intr_map;
+    volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t cpu_apm_m0_intr_map;
+    volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t cpu_apm_m1_intr_map;
+    volatile interrupt_core0_cpu_apm_m2_intr_map_reg_t cpu_apm_m2_intr_map;
+    volatile interrupt_core0_cpu_apm_m3_intr_map_reg_t cpu_apm_m3_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m0_intr_map_reg_t hp_mem_apm_m0_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m1_intr_map_reg_t hp_mem_apm_m1_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m2_intr_map_reg_t hp_mem_apm_m2_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m3_intr_map_reg_t hp_mem_apm_m3_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m4_intr_map_reg_t hp_mem_apm_m4_intr_map;
+    volatile interrupt_core0_hp_mem_apm_m5_intr_map_reg_t hp_mem_apm_m5_intr_map;
+    volatile interrupt_core0_cpu_peri0_timeout_intr_map_reg_t cpu_peri0_timeout_intr_map;
+    volatile interrupt_core0_cpu_peri1_timeout_intr_map_reg_t cpu_peri1_timeout_intr_map;
+    volatile interrupt_core0_hp_peri0_timeout_intr_map_reg_t hp_peri0_timeout_intr_map;
+    volatile interrupt_core0_hp_peri1_timeout_intr_map_reg_t hp_peri1_timeout_intr_map;
+    volatile interrupt_core0_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
+    volatile interrupt_core0_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
+    volatile interrupt_core0_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
+    volatile interrupt_core0_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
+    volatile interrupt_core0_hp_apm_m4_intr_map_reg_t hp_apm_m4_intr_map;
+    volatile interrupt_core0_hp_apm_m5_intr_map_reg_t hp_apm_m5_intr_map;
+    volatile interrupt_core0_hp_apm_m6_intr_map_reg_t hp_apm_m6_intr_map;
+    volatile interrupt_core0_hp_peri0_pms_intr_map_reg_t hp_peri0_pms_intr_map;
+    volatile interrupt_core0_hp_peri1_pms_intr_map_reg_t hp_peri1_pms_intr_map;
+    volatile interrupt_core0_cpu0_peri_pms_intr_map_reg_t cpu0_peri_pms_intr_map;
+    volatile interrupt_core0_cpu1_peri_pms_intr_map_reg_t cpu1_peri_pms_intr_map;
+    volatile interrupt_core0_flash_mspi_intr_map_reg_t flash_mspi_intr_map;
+    volatile interrupt_core0_lpi_intr_map_reg_t lpi_intr_map;
+    volatile interrupt_core0_pmt_intr_map_reg_t pmt_intr_map;
+    volatile interrupt_core0_sbd_intr_map_reg_t sbd_intr_map;
+    volatile interrupt_core0_usb_otghs_intr_map_reg_t usb_otghs_intr_map;
+    volatile interrupt_core0_usb_otghs_endp_multi_proc_intr_map_reg_t usb_otghs_endp_multi_proc_intr_map;
+    volatile interrupt_core0_jpeg_intr_map_reg_t jpeg_intr_map;
+    volatile interrupt_core0_ppa_intr_map_reg_t ppa_intr_map;
+    volatile interrupt_core0_core0_trace_intr_map_reg_t core0_trace_intr_map;
+    volatile interrupt_core0_core1_trace_intr_map_reg_t core1_trace_intr_map;
+    volatile interrupt_core0_dma2d_in_ch0_intr_map_reg_t dma2d_in_ch0_intr_map;
+    volatile interrupt_core0_dma2d_in_ch1_intr_map_reg_t dma2d_in_ch1_intr_map;
+    volatile interrupt_core0_dma2d_in_ch2_intr_map_reg_t dma2d_in_ch2_intr_map;
+    volatile interrupt_core0_dma2d_out_ch0_intr_map_reg_t dma2d_out_ch0_intr_map;
+    volatile interrupt_core0_dma2d_out_ch1_intr_map_reg_t dma2d_out_ch1_intr_map;
+    volatile interrupt_core0_dma2d_out_ch2_intr_map_reg_t dma2d_out_ch2_intr_map;
+    volatile interrupt_core0_dma2d_out_ch3_intr_map_reg_t dma2d_out_ch3_intr_map;
+    volatile interrupt_core0_psram_mspi_intr_map_reg_t psram_mspi_intr_map;
+    volatile interrupt_core0_hp_sysreg_intr_map_reg_t hp_sysreg_intr_map;
+    volatile interrupt_core0_pcnt0_intr_map_reg_t pcnt0_intr_map;
+    volatile interrupt_core0_pcnt1_intr_map_reg_t pcnt1_intr_map;
+    volatile interrupt_core0_hp_pau_intr_map_reg_t hp_pau_intr_map;
+    volatile interrupt_core0_hp_parlio_rx_intr_map_reg_t hp_parlio_rx_intr_map;
+    volatile interrupt_core0_hp_parlio_tx_intr_map_reg_t hp_parlio_tx_intr_map;
+    volatile interrupt_core0_bus_monitor_intr_map_reg_t bus_monitor_intr_map;
+    volatile interrupt_core0_modem_wifi_mac_intr_map_reg_t modem_wifi_mac_intr_map;
+    volatile interrupt_core0_modem_wifi_mac_nmi_intr_map_reg_t modem_wifi_mac_nmi_intr_map;
+    volatile interrupt_core0_modem_wifi_pwr_intr_map_reg_t modem_wifi_pwr_intr_map;
+    volatile interrupt_core0_modem_wifi_bb_intr_map_reg_t modem_wifi_bb_intr_map;
+    volatile interrupt_core0_modem_bt_mac_intr_map_reg_t modem_bt_mac_intr_map;
+    volatile interrupt_core0_modem_bt_bb_intr_map_reg_t modem_bt_bb_intr_map;
+    volatile interrupt_core0_modem_bt_bb_nmi_intr_map_reg_t modem_bt_bb_nmi_intr_map;
+    volatile interrupt_core0_modem_lp_timer_intr_map_reg_t modem_lp_timer_intr_map;
+    volatile interrupt_core0_modem_coex_intr_map_reg_t modem_coex_intr_map;
+    volatile interrupt_core0_modem_ble_timer_intr_map_reg_t modem_ble_timer_intr_map;
+    volatile interrupt_core0_modem_ble_sec_intr_map_reg_t modem_ble_sec_intr_map;
+    volatile interrupt_core0_modem_i2c_mst_intr_map_reg_t modem_i2c_mst_intr_map;
+    volatile interrupt_core0_modem_zb_mac_intr_map_reg_t modem_zb_mac_intr_map;
+    volatile interrupt_core0_modem_bt_mac_int1_intr_map_reg_t modem_bt_mac_int1_intr_map;
+    volatile interrupt_core0_cordic_intr_map_reg_t cordic_intr_map;
+    volatile interrupt_core0_zero_det_intr_map_reg_t zero_det_intr_map;
+    volatile interrupt_core0_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
+    volatile interrupt_core0_lp_timer_reg_0_intr_map_reg_t lp_timer_reg_0_intr_map;
+    volatile interrupt_core0_lp_timer_reg_1_intr_map_reg_t lp_timer_reg_1_intr_map;
+    volatile interrupt_core0_mb_hp_intr_map_reg_t mb_hp_intr_map;
+    volatile interrupt_core0_mb_lp_intr_map_reg_t mb_lp_intr_map;
+    volatile interrupt_core0_pmu_reg_0_intr_map_reg_t pmu_reg_0_intr_map;
+    volatile interrupt_core0_pmu_reg_1_intr_map_reg_t pmu_reg_1_intr_map;
+    volatile interrupt_core0_lp_anaperi_intr_map_reg_t lp_anaperi_intr_map;
+    volatile interrupt_core0_lp_adc_intr_map_reg_t lp_adc_intr_map;
+    volatile interrupt_core0_lp_dac_intr_map_reg_t lp_dac_intr_map;
+    volatile interrupt_core0_lp_gpio_intr_map_reg_t lp_gpio_intr_map;
+    volatile interrupt_core0_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
+    volatile interrupt_core0_lp_spi_intr_map_reg_t lp_spi_intr_map;
+    volatile interrupt_core0_lp_touch_intr_map_reg_t lp_touch_intr_map;
+    volatile interrupt_core0_lp_tsens_intr_map_reg_t lp_tsens_intr_map;
+    volatile interrupt_core0_lp_uart_intr_map_reg_t lp_uart_intr_map;
+    volatile interrupt_core0_lp_efuse_intr_map_reg_t lp_efuse_intr_map;
+    volatile interrupt_core0_lp_sw_intr_map_reg_t lp_sw_intr_map;
+    volatile interrupt_core0_lp_trng_intr_map_reg_t lp_trng_intr_map;
+    volatile interrupt_core0_lp_sysreg_intr_map_reg_t lp_sysreg_intr_map;
+    volatile interrupt_core0_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
+    volatile interrupt_core0_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
+    volatile interrupt_core0_lp_apm_m2_intr_map_reg_t lp_apm_m2_intr_map;
+    volatile interrupt_core0_lp_apm_m3_intr_map_reg_t lp_apm_m3_intr_map;
+    volatile interrupt_core0_lp_peri0_pms_intr_map_reg_t lp_peri0_pms_intr_map;
+    volatile interrupt_core0_lp_peri1_pms_intr_map_reg_t lp_peri1_pms_intr_map;
+    volatile interrupt_core0_lp_huk_intr_map_reg_t lp_huk_intr_map;
+    volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
+    volatile interrupt_core0_lp_ahb_pdma_in_ch0_intr_map_reg_t lp_ahb_pdma_in_ch0_intr_map;
+    volatile interrupt_core0_lp_ahb_pdma_in_ch1_intr_map_reg_t lp_ahb_pdma_in_ch1_intr_map;
+    volatile interrupt_core0_lp_ahb_pdma_out_ch0_intr_map_reg_t lp_ahb_pdma_out_ch0_intr_map;
+    volatile interrupt_core0_lp_ahb_pdma_out_ch1_intr_map_reg_t lp_ahb_pdma_out_ch1_intr_map;
+    volatile interrupt_core0_lp_sw_invalid_sleep_intr_map_reg_t lp_sw_invalid_sleep_intr_map;
+    volatile interrupt_core0_sig_idx_assert_in_sec_reg_t sig_idx_assert_in_sec;
+    volatile interrupt_core0_int_status_reg_0_reg_t int_status_reg_0;
+    volatile interrupt_core0_int_status_reg_1_reg_t int_status_reg_1;
+    volatile interrupt_core0_int_status_reg_2_reg_t int_status_reg_2;
+    volatile interrupt_core0_int_status_reg_3_reg_t int_status_reg_3;
+    volatile interrupt_core0_int_status_reg_4_reg_t int_status_reg_4;
+    volatile interrupt_core0_int_status_reg_5_reg_t int_status_reg_5;
+    volatile interrupt_core0_src_pass_in_s_status_0_reg_t src_pass_in_s_status_0;
+    volatile interrupt_core0_src_pass_in_s_status_1_reg_t src_pass_in_s_status_1;
+    volatile interrupt_core0_src_pass_in_s_status_2_reg_t src_pass_in_s_status_2;
+    volatile interrupt_core0_src_pass_in_s_status_3_reg_t src_pass_in_s_status_3;
+    volatile interrupt_core0_src_pass_in_s_status_4_reg_t src_pass_in_s_status_4;
+    volatile interrupt_core0_src_pass_in_s_status_5_reg_t src_pass_in_s_status_5;
+    volatile interrupt_core0_src_pass_in_m_status_0_reg_t src_pass_in_m_status_0;
+    volatile interrupt_core0_src_pass_in_m_status_1_reg_t src_pass_in_m_status_1;
+    volatile interrupt_core0_src_pass_in_m_status_2_reg_t src_pass_in_m_status_2;
+    volatile interrupt_core0_src_pass_in_m_status_3_reg_t src_pass_in_m_status_3;
+    volatile interrupt_core0_src_pass_in_m_status_4_reg_t src_pass_in_m_status_4;
+    volatile interrupt_core0_src_pass_in_m_status_5_reg_t src_pass_in_m_status_5;
+    volatile interrupt_core0_config_state_reg_t config_state;
+    volatile interrupt_core0_s_status_reg_t s_status;
+    volatile interrupt_core0_m_status_reg_t m_status;
+    volatile interrupt_core0_clock_gate_reg_t clock_gate;
+    uint32_t reserved_300[319];
+    volatile interrupt_core0_interrupt_date_reg_t interrupt_date;
+} interrupt_core0_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_core0_dev_t) == 0x800, "Invalid size of interrupt_core0_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/interrupt_core1_reg.h b/components/soc/esp32s31/register/soc/interrupt_core1_reg.h
new file mode 100644
index 00000000000..391b2cb28fa
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/interrupt_core1_reg.h
@@ -0,0 +1,3925 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** INTERRUPT_CORE1_SYS_ICM_INTR_MAP_REG register
+ *  SYS_ICM_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x0)
+/** INTERRUPT_CORE1_SYS_ICM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYS_ICM_INTR_MAP_M  (INTERRUPT_CORE1_SYS_ICM_INTR_MAP_V << INTERRUPT_CORE1_SYS_ICM_INTR_MAP_S)
+#define INTERRUPT_CORE1_SYS_ICM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SYS_ICM_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SYS_ICM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_REG register
+ *  AXI_PERF_MON_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4)
+/** INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_V << INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PERF_MON_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_REG register
+ *  USB_DEVICE_INTR mapping register
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8)
+/** INTERRUPT_CORE1_USB_DEVICE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_M  (INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_V << INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_S)
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_MAP_S  0
+/** INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_USB_DEVICE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_REG register
+ *  SDIO_HOST_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc)
+/** INTERRUPT_CORE1_SDIO_HOST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_M  (INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_V << INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_S)
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SDIO_HOST_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SPI2_INTR_MAP_REG register
+ *  SPI2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10)
+/** INTERRUPT_CORE1_SPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SPI2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SPI2_INTR_MAP_M  (INTERRUPT_CORE1_SPI2_INTR_MAP_V << INTERRUPT_CORE1_SPI2_INTR_MAP_S)
+#define INTERRUPT_CORE1_SPI2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SPI2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SPI2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SPI3_INTR_MAP_REG register
+ *  SPI3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SPI3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14)
+/** INTERRUPT_CORE1_SPI3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SPI3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SPI3_INTR_MAP_M  (INTERRUPT_CORE1_SPI3_INTR_MAP_V << INTERRUPT_CORE1_SPI3_INTR_MAP_S)
+#define INTERRUPT_CORE1_SPI3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SPI3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SPI3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_I2S0_INTR_MAP_REG register
+ *  I2S0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_I2S0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18)
+/** INTERRUPT_CORE1_I2S0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_I2S0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2S0_INTR_MAP_M  (INTERRUPT_CORE1_I2S0_INTR_MAP_V << INTERRUPT_CORE1_I2S0_INTR_MAP_S)
+#define INTERRUPT_CORE1_I2S0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_I2S0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_I2S0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_I2S1_INTR_MAP_REG register
+ *  I2S1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c)
+/** INTERRUPT_CORE1_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_I2S1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2S1_INTR_MAP_M  (INTERRUPT_CORE1_I2S1_INTR_MAP_V << INTERRUPT_CORE1_I2S1_INTR_MAP_S)
+#define INTERRUPT_CORE1_I2S1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_I2S1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_I2S1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_UHCI0_INTR_MAP_REG register
+ *  UHCI0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20)
+/** INTERRUPT_CORE1_UHCI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_UHCI0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M  (INTERRUPT_CORE1_UHCI0_INTR_MAP_V << INTERRUPT_CORE1_UHCI0_INTR_MAP_S)
+#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_UHCI0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_UART0_INTR_MAP_REG register
+ *  UART0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24)
+/** INTERRUPT_CORE1_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_UART0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART0_INTR_MAP_M  (INTERRUPT_CORE1_UART0_INTR_MAP_V << INTERRUPT_CORE1_UART0_INTR_MAP_S)
+#define INTERRUPT_CORE1_UART0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_UART0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_UART0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_UART1_INTR_MAP_REG register
+ *  UART1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28)
+/** INTERRUPT_CORE1_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_UART1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART1_INTR_MAP_M  (INTERRUPT_CORE1_UART1_INTR_MAP_V << INTERRUPT_CORE1_UART1_INTR_MAP_S)
+#define INTERRUPT_CORE1_UART1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_UART1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_UART1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_UART2_INTR_MAP_REG register
+ *  UART2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c)
+/** INTERRUPT_CORE1_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_UART2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART2_INTR_MAP_M  (INTERRUPT_CORE1_UART2_INTR_MAP_V << INTERRUPT_CORE1_UART2_INTR_MAP_S)
+#define INTERRUPT_CORE1_UART2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_UART2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_UART2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_UART3_INTR_MAP_REG register
+ *  UART3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_UART3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x30)
+/** INTERRUPT_CORE1_UART3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_UART3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_UART3_INTR_MAP_M  (INTERRUPT_CORE1_UART3_INTR_MAP_V << INTERRUPT_CORE1_UART3_INTR_MAP_S)
+#define INTERRUPT_CORE1_UART3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_UART3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_UART3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LCD_CAM_INTR_MAP_REG register
+ *  LCD_CAM_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x34)
+/** INTERRUPT_CORE1_LCD_CAM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LCD_CAM_INTR_MAP_M  (INTERRUPT_CORE1_LCD_CAM_INTR_MAP_V << INTERRUPT_CORE1_LCD_CAM_INTR_MAP_S)
+#define INTERRUPT_CORE1_LCD_CAM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LCD_CAM_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LCD_CAM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PWM0_INTR_MAP_REG register
+ *  PWM0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x38)
+/** INTERRUPT_CORE1_PWM0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PWM0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM0_INTR_MAP_M  (INTERRUPT_CORE1_PWM0_INTR_MAP_V << INTERRUPT_CORE1_PWM0_INTR_MAP_S)
+#define INTERRUPT_CORE1_PWM0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PWM0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PWM0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PWM1_INTR_MAP_REG register
+ *  PWM1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x3c)
+/** INTERRUPT_CORE1_PWM1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PWM1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM1_INTR_MAP_M  (INTERRUPT_CORE1_PWM1_INTR_MAP_V << INTERRUPT_CORE1_PWM1_INTR_MAP_S)
+#define INTERRUPT_CORE1_PWM1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PWM1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PWM1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PWM2_INTR_MAP_REG register
+ *  PWM2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x40)
+/** INTERRUPT_CORE1_PWM2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PWM2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM2_INTR_MAP_M  (INTERRUPT_CORE1_PWM2_INTR_MAP_V << INTERRUPT_CORE1_PWM2_INTR_MAP_S)
+#define INTERRUPT_CORE1_PWM2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PWM2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PWM2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PWM3_INTR_MAP_REG register
+ *  PWM3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x44)
+/** INTERRUPT_CORE1_PWM3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PWM3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PWM3_INTR_MAP_M  (INTERRUPT_CORE1_PWM3_INTR_MAP_V << INTERRUPT_CORE1_PWM3_INTR_MAP_S)
+#define INTERRUPT_CORE1_PWM3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PWM3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PWM3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CAN0_INTR_MAP_REG register
+ *  CAN0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x48)
+/** INTERRUPT_CORE1_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CAN0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN0_INTR_MAP_M  (INTERRUPT_CORE1_CAN0_INTR_MAP_V << INTERRUPT_CORE1_CAN0_INTR_MAP_S)
+#define INTERRUPT_CORE1_CAN0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CAN0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CAN0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_REG register
+ *  CAN0_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x4c)
+/** INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_M  (INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_V << INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CAN0_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CAN1_INTR_MAP_REG register
+ *  CAN1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x50)
+/** INTERRUPT_CORE1_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CAN1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN1_INTR_MAP_M  (INTERRUPT_CORE1_CAN1_INTR_MAP_V << INTERRUPT_CORE1_CAN1_INTR_MAP_S)
+#define INTERRUPT_CORE1_CAN1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CAN1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CAN1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_REG register
+ *  CAN1_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x54)
+/** INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_M  (INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_V << INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CAN1_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_RMT_INTR_MAP_REG register
+ *  RMT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x58)
+/** INTERRUPT_CORE1_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_RMT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_RMT_INTR_MAP_M  (INTERRUPT_CORE1_RMT_INTR_MAP_V << INTERRUPT_CORE1_RMT_INTR_MAP_S)
+#define INTERRUPT_CORE1_RMT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_RMT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_RMT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_I2C0_INTR_MAP_REG register
+ *  I2C0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_I2C0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x5c)
+/** INTERRUPT_CORE1_I2C0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_I2C0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2C0_INTR_MAP_M  (INTERRUPT_CORE1_I2C0_INTR_MAP_V << INTERRUPT_CORE1_I2C0_INTR_MAP_S)
+#define INTERRUPT_CORE1_I2C0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_I2C0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_I2C0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_I2C1_INTR_MAP_REG register
+ *  I2C1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_I2C1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x60)
+/** INTERRUPT_CORE1_I2C1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_I2C1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_I2C1_INTR_MAP_M  (INTERRUPT_CORE1_I2C1_INTR_MAP_V << INTERRUPT_CORE1_I2C1_INTR_MAP_S)
+#define INTERRUPT_CORE1_I2C1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_I2C1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_I2C1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_REG register
+ *  TIMERGRP0_T0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x64)
+/** INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_T0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_REG register
+ *  TIMERGRP0_T1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x68)
+/** INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_T1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_REG register
+ *  TIMERGRP0_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x6c)
+/** INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP0_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_REG register
+ *  TIMERGRP1_T0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x70)
+/** INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_T0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_REG register
+ *  TIMERGRP1_T1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x74)
+/** INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_T1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_REG register
+ *  TIMERGRP1_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x78)
+/** INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_M  (INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_V << INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_TIMERGRP1_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LEDC0_INTR_MAP_REG register
+ *  LEDC0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LEDC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7c)
+/** INTERRUPT_CORE1_LEDC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LEDC0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LEDC0_INTR_MAP_M  (INTERRUPT_CORE1_LEDC0_INTR_MAP_V << INTERRUPT_CORE1_LEDC0_INTR_MAP_S)
+#define INTERRUPT_CORE1_LEDC0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LEDC0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LEDC0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LEDC1_INTR_MAP_REG register
+ *  LEDC1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LEDC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80)
+/** INTERRUPT_CORE1_LEDC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LEDC1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LEDC1_INTR_MAP_M  (INTERRUPT_CORE1_LEDC1_INTR_MAP_V << INTERRUPT_CORE1_LEDC1_INTR_MAP_S)
+#define INTERRUPT_CORE1_LEDC1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LEDC1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LEDC1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_REG register
+ *  SYSTIMER_TARGET0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_REG register
+ *  SYSTIMER_TARGET1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_REG register
+ *  SYSTIMER_TARGET2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8c)
+/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_M  (INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x9c)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_REG register
+ *  AHB_PDMA_IN_CH4_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa0)
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_IN_CH4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa4)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xa8)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xac)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb0)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_REG register
+ *  AHB_PDMA_OUT_CH4_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb4)
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AHB_PDMA_OUT_CH4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_REG register
+ *  ASRC_CHNL0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xb8)
+/** INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_M  (INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_V << INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_S)
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_ASRC_CHNL0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_REG register
+ *  ASRC_CHNL1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xbc)
+/** INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_M  (INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_V << INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_S)
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_ASRC_CHNL1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc0)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc4)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_REG register
+ *  AXI_PDMA_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xc8)
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xcc)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd0)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_REG register
+ *  AXI_PDMA_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd4)
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AXI_PDMA_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_RSA_INTR_MAP_REG register
+ *  RSA_INTR mapping register
+ */
+#define INTERRUPT_CORE1_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xd8)
+/** INTERRUPT_CORE1_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_RSA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_RSA_INTR_MAP_M  (INTERRUPT_CORE1_RSA_INTR_MAP_V << INTERRUPT_CORE1_RSA_INTR_MAP_S)
+#define INTERRUPT_CORE1_RSA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_RSA_INTR_MAP_S  0
+/** INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_RSA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_AES_INTR_MAP_REG register
+ *  AES_INTR mapping register
+ */
+#define INTERRUPT_CORE1_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xdc)
+/** INTERRUPT_CORE1_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_AES_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_AES_INTR_MAP_M  (INTERRUPT_CORE1_AES_INTR_MAP_V << INTERRUPT_CORE1_AES_INTR_MAP_S)
+#define INTERRUPT_CORE1_AES_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_AES_INTR_MAP_S  0
+/** INTERRUPT_CORE1_AES_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_AES_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_AES_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_AES_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_AES_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_AES_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_AES_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SHA_INTR_MAP_REG register
+ *  SHA_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe0)
+/** INTERRUPT_CORE1_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SHA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SHA_INTR_MAP_M  (INTERRUPT_CORE1_SHA_INTR_MAP_V << INTERRUPT_CORE1_SHA_INTR_MAP_S)
+#define INTERRUPT_CORE1_SHA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SHA_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SHA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_ECC_INTR_MAP_REG register
+ *  ECC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe4)
+/** INTERRUPT_CORE1_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_ECC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ECC_INTR_MAP_M  (INTERRUPT_CORE1_ECC_INTR_MAP_V << INTERRUPT_CORE1_ECC_INTR_MAP_S)
+#define INTERRUPT_CORE1_ECC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_ECC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_ECC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_ECDSA_INTR_MAP_REG register
+ *  ECDSA_INTR mapping register
+ */
+#define INTERRUPT_CORE1_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xe8)
+/** INTERRUPT_CORE1_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_ECDSA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ECDSA_INTR_MAP_M  (INTERRUPT_CORE1_ECDSA_INTR_MAP_V << INTERRUPT_CORE1_ECDSA_INTR_MAP_S)
+#define INTERRUPT_CORE1_ECDSA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_ECDSA_INTR_MAP_S  0
+/** INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_ECDSA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_KM_INTR_MAP_REG register
+ *  KM_INTR mapping register
+ */
+#define INTERRUPT_CORE1_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xec)
+/** INTERRUPT_CORE1_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_KM_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_KM_INTR_MAP_M  (INTERRUPT_CORE1_KM_INTR_MAP_V << INTERRUPT_CORE1_KM_INTR_MAP_S)
+#define INTERRUPT_CORE1_KM_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_KM_INTR_MAP_S  0
+/** INTERRUPT_CORE1_KM_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_KM_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_KM_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_KM_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_KM_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_KM_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_KM_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_RMA_INTR_MAP_REG register
+ *  RMA_INTR mapping register
+ */
+#define INTERRUPT_CORE1_RMA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf0)
+/** INTERRUPT_CORE1_RMA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_RMA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_RMA_INTR_MAP_M  (INTERRUPT_CORE1_RMA_INTR_MAP_V << INTERRUPT_CORE1_RMA_INTR_MAP_S)
+#define INTERRUPT_CORE1_RMA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_RMA_INTR_MAP_S  0
+/** INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_RMA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_GPIO_INTR0_MAP_REG register
+ *  GPIO_INTR0 mapping register
+ */
+#define INTERRUPT_CORE1_GPIO_INTR0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf4)
+/** INTERRUPT_CORE1_GPIO_INTR0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR0_MAP_M  (INTERRUPT_CORE1_GPIO_INTR0_MAP_V << INTERRUPT_CORE1_GPIO_INTR0_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INTR0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR0_MAP_S  0
+/** INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL_M  (INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL_V << INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR0_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_GPIO_INTR1_MAP_REG register
+ *  GPIO_INTR1 mapping register
+ */
+#define INTERRUPT_CORE1_GPIO_INTR1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xf8)
+/** INTERRUPT_CORE1_GPIO_INTR1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR1_MAP_M  (INTERRUPT_CORE1_GPIO_INTR1_MAP_V << INTERRUPT_CORE1_GPIO_INTR1_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INTR1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR1_MAP_S  0
+/** INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL_M  (INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL_V << INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR1_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_GPIO_INTR2_MAP_REG register
+ *  GPIO_INTR2 mapping register
+ */
+#define INTERRUPT_CORE1_GPIO_INTR2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xfc)
+/** INTERRUPT_CORE1_GPIO_INTR2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR2_MAP_M  (INTERRUPT_CORE1_GPIO_INTR2_MAP_V << INTERRUPT_CORE1_GPIO_INTR2_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INTR2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR2_MAP_S  0
+/** INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL_M  (INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL_V << INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR2_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_GPIO_INTR3_MAP_REG register
+ *  GPIO_INTR3 mapping register
+ */
+#define INTERRUPT_CORE1_GPIO_INTR3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x100)
+/** INTERRUPT_CORE1_GPIO_INTR3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR3_MAP_M  (INTERRUPT_CORE1_GPIO_INTR3_MAP_V << INTERRUPT_CORE1_GPIO_INTR3_MAP_S)
+#define INTERRUPT_CORE1_GPIO_INTR3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_GPIO_INTR3_MAP_S  0
+/** INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL_M  (INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL_V << INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_GPIO_INTR3_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  CPU_INTR_FROM_CPU_0 mapping register
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x104)
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S  0
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  CPU_INTR_FROM_CPU_1 mapping register
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x108)
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S  0
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  CPU_INTR_FROM_CPU_2 mapping register
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x10c)
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S  0
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  CPU_INTR_FROM_CPU_3 mapping register
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x110)
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S  0
+/** INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CACHE_INTR_MAP_REG register
+ *  CACHE_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x114)
+/** INTERRUPT_CORE1_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CACHE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CACHE_INTR_MAP_M  (INTERRUPT_CORE1_CACHE_INTR_MAP_V << INTERRUPT_CORE1_CACHE_INTR_MAP_S)
+#define INTERRUPT_CORE1_CACHE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CACHE_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CACHE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_REG register
+ *  CPU_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x118)
+/** INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_M  (INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_REG register
+ *  CPU_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x11c)
+/** INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_M  (INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_REG register
+ *  CPU_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x120)
+/** INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_M  (INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_V << INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_REG register
+ *  CPU_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x124)
+/** INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_M  (INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_V << INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_REG register
+ *  HP_MEM_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x128)
+/** INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_REG register
+ *  HP_MEM_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x12c)
+/** INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_REG register
+ *  HP_MEM_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x130)
+/** INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_REG register
+ *  HP_MEM_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x134)
+/** INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_REG register
+ *  HP_MEM_APM_M4_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x138)
+/** INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_REG register
+ *  HP_MEM_APM_M5_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x13c)
+/** INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_M  (INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_V << INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_MEM_APM_M5_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_REG register
+ *  CPU_PERI0_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x140)
+/** INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_REG register
+ *  CPU_PERI1_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x144)
+/** INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_REG register
+ *  HP_PERI0_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x148)
+/** INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PERI0_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_REG register
+ *  HP_PERI1_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x14c)
+/** INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PERI1_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_REG register
+ *  HP_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x150)
+/** INTERRUPT_CORE1_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_REG register
+ *  HP_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x154)
+/** INTERRUPT_CORE1_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_REG register
+ *  HP_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x158)
+/** INTERRUPT_CORE1_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_REG register
+ *  HP_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x15c)
+/** INTERRUPT_CORE1_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_REG register
+ *  HP_APM_M4_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x160)
+/** INTERRUPT_CORE1_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M4_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_REG register
+ *  HP_APM_M5_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x164)
+/** INTERRUPT_CORE1_HP_APM_M5_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M5_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_REG register
+ *  HP_APM_M6_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x168)
+/** INTERRUPT_CORE1_HP_APM_M6_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_M  (INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_V << INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_APM_M6_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_REG register
+ *  HP_PERI0_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x16c)
+/** INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PERI0_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_REG register
+ *  HP_PERI1_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x170)
+/** INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PERI1_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_REG register
+ *  CPU0_PERI_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x174)
+/** INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU0_PERI_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_REG register
+ *  CPU1_PERI_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x178)
+/** INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_M  (INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_V << INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CPU1_PERI_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_REG register
+ *  FLASH_MSPI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x17c)
+/** INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_M  (INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_V << INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_S)
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_FLASH_MSPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LPI_INTR_MAP_REG register
+ *  LPI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x180)
+/** INTERRUPT_CORE1_LPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LPI_INTR_MAP_M  (INTERRUPT_CORE1_LPI_INTR_MAP_V << INTERRUPT_CORE1_LPI_INTR_MAP_S)
+#define INTERRUPT_CORE1_LPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LPI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PMT_INTR_MAP_REG register
+ *  PMT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x184)
+/** INTERRUPT_CORE1_PMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PMT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMT_INTR_MAP_M  (INTERRUPT_CORE1_PMT_INTR_MAP_V << INTERRUPT_CORE1_PMT_INTR_MAP_S)
+#define INTERRUPT_CORE1_PMT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PMT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PMT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SBD_INTR_MAP_REG register
+ *  SBD_INTR mapping register
+ */
+#define INTERRUPT_CORE1_SBD_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x188)
+/** INTERRUPT_CORE1_SBD_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_SBD_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_SBD_INTR_MAP_M  (INTERRUPT_CORE1_SBD_INTR_MAP_V << INTERRUPT_CORE1_SBD_INTR_MAP_S)
+#define INTERRUPT_CORE1_SBD_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_SBD_INTR_MAP_S  0
+/** INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_SBD_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_REG register
+ *  USB_OTGHS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x18c)
+/** INTERRUPT_CORE1_USB_OTGHS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_M  (INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_V << INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_S)
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_USB_OTGHS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG register
+ *  USB_OTGHS_ENDP_MULTI_PROC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x190)
+/** INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_M  (INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S)
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL : R/W; bitpos: [9:8];
+ *  default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_USB_OTGHS_ENDP_MULTI_PROC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_JPEG_INTR_MAP_REG register
+ *  JPEG_INTR mapping register
+ */
+#define INTERRUPT_CORE1_JPEG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x194)
+/** INTERRUPT_CORE1_JPEG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_JPEG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_JPEG_INTR_MAP_M  (INTERRUPT_CORE1_JPEG_INTR_MAP_V << INTERRUPT_CORE1_JPEG_INTR_MAP_S)
+#define INTERRUPT_CORE1_JPEG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_JPEG_INTR_MAP_S  0
+/** INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_JPEG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PPA_INTR_MAP_REG register
+ *  PPA_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PPA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x198)
+/** INTERRUPT_CORE1_PPA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PPA_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PPA_INTR_MAP_M  (INTERRUPT_CORE1_PPA_INTR_MAP_V << INTERRUPT_CORE1_PPA_INTR_MAP_S)
+#define INTERRUPT_CORE1_PPA_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PPA_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PPA_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_REG register
+ *  CORE0_TRACE_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x19c)
+/** INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_M  (INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_S)
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CORE0_TRACE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_REG register
+ *  CORE1_TRACE_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a0)
+/** INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_M  (INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_V << INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_S)
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CORE1_TRACE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_REG register
+ *  DMA2D_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a4)
+/** INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_REG register
+ *  DMA2D_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1a8)
+/** INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_REG register
+ *  DMA2D_IN_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ac)
+/** INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_IN_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_REG register
+ *  DMA2D_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b0)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_REG register
+ *  DMA2D_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b4)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_REG register
+ *  DMA2D_OUT_CH2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1b8)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_REG register
+ *  DMA2D_OUT_CH3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1bc)
+/** INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_M  (INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_V << INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_DMA2D_OUT_CH3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_REG register
+ *  PSRAM_MSPI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c0)
+/** INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_M  (INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_V << INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_S)
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PSRAM_MSPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_REG register
+ *  HP_SYSREG_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c4)
+/** INTERRUPT_CORE1_HP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_V << INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_SYSREG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PCNT0_INTR_MAP_REG register
+ *  PCNT0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PCNT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1c8)
+/** INTERRUPT_CORE1_PCNT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PCNT0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PCNT0_INTR_MAP_M  (INTERRUPT_CORE1_PCNT0_INTR_MAP_V << INTERRUPT_CORE1_PCNT0_INTR_MAP_S)
+#define INTERRUPT_CORE1_PCNT0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PCNT0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PCNT0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PCNT1_INTR_MAP_REG register
+ *  PCNT1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PCNT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1cc)
+/** INTERRUPT_CORE1_PCNT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PCNT1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PCNT1_INTR_MAP_M  (INTERRUPT_CORE1_PCNT1_INTR_MAP_V << INTERRUPT_CORE1_PCNT1_INTR_MAP_S)
+#define INTERRUPT_CORE1_PCNT1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PCNT1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PCNT1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PAU_INTR_MAP_REG register
+ *  HP_PAU_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d0)
+/** INTERRUPT_CORE1_HP_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PAU_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PAU_INTR_MAP_M  (INTERRUPT_CORE1_HP_PAU_INTR_MAP_V << INTERRUPT_CORE1_HP_PAU_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PAU_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PAU_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PAU_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_REG register
+ *  HP_PARLIO_RX_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d4)
+/** INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_M  (INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_V << INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PARLIO_RX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_REG register
+ *  HP_PARLIO_TX_INTR mapping register
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1d8)
+/** INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_M  (INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_V << INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_S)
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_MAP_S  0
+/** INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_HP_PARLIO_TX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_REG register
+ *  BUS_MONITOR_INTR mapping register
+ */
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1dc)
+/** INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_M  (INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_S)
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_MAP_S  0
+/** INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_BUS_MONITOR_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_REG register
+ *  MODEM_WIFI_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e0)
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_REG register
+ *  MODEM_WIFI_MAC_NMI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e4)
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_V << INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_MAC_NMI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_REG register
+ *  MODEM_WIFI_PWR_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1e8)
+/** INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_PWR_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_REG register
+ *  MODEM_WIFI_BB_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1ec)
+/** INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_WIFI_BB_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_REG register
+ *  MODEM_BT_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f0)
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_REG register
+ *  MODEM_BT_BB_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f4)
+/** INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_BB_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_REG register
+ *  MODEM_BT_BB_NMI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1f8)
+/** INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_BB_NMI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_REG register
+ *  MODEM_LP_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x1fc)
+/** INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_LP_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_REG register
+ *  MODEM_COEX_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x200)
+/** INTERRUPT_CORE1_MODEM_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_V << INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_COEX_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_REG register
+ *  MODEM_BLE_TIMER_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x204)
+/** INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BLE_TIMER_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_REG register
+ *  MODEM_BLE_SEC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x208)
+/** INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BLE_SEC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_REG register
+ *  MODEM_I2C_MST_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x20c)
+/** INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_V << INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_I2C_MST_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_REG register
+ *  MODEM_ZB_MAC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x210)
+/** INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_ZB_MAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_REG register
+ *  MODEM_BT_MAC_INT1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x214)
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_M  (INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_V << INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_S)
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MODEM_BT_MAC_INT1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_CORDIC_INTR_MAP_REG register
+ *  CORDIC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_CORDIC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x218)
+/** INTERRUPT_CORE1_CORDIC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_CORDIC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_CORDIC_INTR_MAP_M  (INTERRUPT_CORE1_CORDIC_INTR_MAP_V << INTERRUPT_CORE1_CORDIC_INTR_MAP_S)
+#define INTERRUPT_CORE1_CORDIC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_CORDIC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_CORDIC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_ZERO_DET_INTR_MAP_REG register
+ *  ZERO_DET_INTR mapping register
+ */
+#define INTERRUPT_CORE1_ZERO_DET_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x21c)
+/** INTERRUPT_CORE1_ZERO_DET_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_ZERO_DET_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_ZERO_DET_INTR_MAP_M  (INTERRUPT_CORE1_ZERO_DET_INTR_MAP_V << INTERRUPT_CORE1_ZERO_DET_INTR_MAP_S)
+#define INTERRUPT_CORE1_ZERO_DET_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_ZERO_DET_INTR_MAP_S  0
+/** INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_ZERO_DET_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_WDT_INTR_MAP_REG register
+ *  LP_WDT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x220)
+/** INTERRUPT_CORE1_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_WDT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_WDT_INTR_MAP_M  (INTERRUPT_CORE1_LP_WDT_INTR_MAP_V << INTERRUPT_CORE1_LP_WDT_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_WDT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_WDT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_WDT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_REG register
+ *  LP_TIMER_REG_0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x224)
+/** INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_M  (INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_TIMER_REG_0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_REG register
+ *  LP_TIMER_REG_1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x228)
+/** INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_M  (INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_V << INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_TIMER_REG_1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MB_HP_INTR_MAP_REG register
+ *  MB_HP_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MB_HP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x22c)
+/** INTERRUPT_CORE1_MB_HP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MB_HP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MB_HP_INTR_MAP_M  (INTERRUPT_CORE1_MB_HP_INTR_MAP_V << INTERRUPT_CORE1_MB_HP_INTR_MAP_S)
+#define INTERRUPT_CORE1_MB_HP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MB_HP_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MB_HP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_MB_LP_INTR_MAP_REG register
+ *  MB_LP_INTR mapping register
+ */
+#define INTERRUPT_CORE1_MB_LP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x230)
+/** INTERRUPT_CORE1_MB_LP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_MB_LP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_MB_LP_INTR_MAP_M  (INTERRUPT_CORE1_MB_LP_INTR_MAP_V << INTERRUPT_CORE1_MB_LP_INTR_MAP_S)
+#define INTERRUPT_CORE1_MB_LP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_MB_LP_INTR_MAP_S  0
+/** INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_MB_LP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_REG register
+ *  PMU_REG_0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x234)
+/** INTERRUPT_CORE1_PMU_REG_0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_M  (INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_V << INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_S)
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PMU_REG_0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_REG register
+ *  PMU_REG_1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x238)
+/** INTERRUPT_CORE1_PMU_REG_1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_M  (INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_V << INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_S)
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_PMU_REG_1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_REG register
+ *  LP_ANAPERI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x23c)
+/** INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_M  (INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_V << INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_ANAPERI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_ADC_INTR_MAP_REG register
+ *  LP_ADC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x240)
+/** INTERRUPT_CORE1_LP_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_ADC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_ADC_INTR_MAP_M  (INTERRUPT_CORE1_LP_ADC_INTR_MAP_V << INTERRUPT_CORE1_LP_ADC_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_ADC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_ADC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_ADC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_DAC_INTR_MAP_REG register
+ *  LP_DAC_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_DAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x244)
+/** INTERRUPT_CORE1_LP_DAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_DAC_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_DAC_INTR_MAP_M  (INTERRUPT_CORE1_LP_DAC_INTR_MAP_V << INTERRUPT_CORE1_LP_DAC_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_DAC_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_DAC_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_DAC_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_GPIO_INTR_MAP_REG register
+ *  LP_GPIO_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x248)
+/** INTERRUPT_CORE1_LP_GPIO_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_GPIO_INTR_MAP_M  (INTERRUPT_CORE1_LP_GPIO_INTR_MAP_V << INTERRUPT_CORE1_LP_GPIO_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_GPIO_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_GPIO_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_GPIO_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_I2C_INTR_MAP_REG register
+ *  LP_I2C_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_I2C_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x24c)
+/** INTERRUPT_CORE1_LP_I2C_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_I2C_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_I2C_INTR_MAP_M  (INTERRUPT_CORE1_LP_I2C_INTR_MAP_V << INTERRUPT_CORE1_LP_I2C_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_I2C_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_I2C_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_I2C_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_SPI_INTR_MAP_REG register
+ *  LP_SPI_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_SPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x250)
+/** INTERRUPT_CORE1_LP_SPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_SPI_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SPI_INTR_MAP_M  (INTERRUPT_CORE1_LP_SPI_INTR_MAP_V << INTERRUPT_CORE1_LP_SPI_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_SPI_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_SPI_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_SPI_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_REG register
+ *  LP_TOUCH_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x254)
+/** INTERRUPT_CORE1_LP_TOUCH_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_M  (INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_V << INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_TOUCH_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_TSENS_INTR_MAP_REG register
+ *  LP_TSENS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x258)
+/** INTERRUPT_CORE1_LP_TSENS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TSENS_INTR_MAP_M  (INTERRUPT_CORE1_LP_TSENS_INTR_MAP_V << INTERRUPT_CORE1_LP_TSENS_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_TSENS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_TSENS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_TSENS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_UART_INTR_MAP_REG register
+ *  LP_UART_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x25c)
+/** INTERRUPT_CORE1_LP_UART_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_UART_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_UART_INTR_MAP_M  (INTERRUPT_CORE1_LP_UART_INTR_MAP_V << INTERRUPT_CORE1_LP_UART_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_UART_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_UART_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_UART_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_REG register
+ *  LP_EFUSE_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x260)
+/** INTERRUPT_CORE1_LP_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_M  (INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_V << INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_EFUSE_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_SW_INTR_MAP_REG register
+ *  LP_SW_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_SW_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x264)
+/** INTERRUPT_CORE1_LP_SW_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_SW_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SW_INTR_MAP_M  (INTERRUPT_CORE1_LP_SW_INTR_MAP_V << INTERRUPT_CORE1_LP_SW_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_SW_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_SW_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_SW_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_TRNG_INTR_MAP_REG register
+ *  LP_TRNG_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_TRNG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x268)
+/** INTERRUPT_CORE1_LP_TRNG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_TRNG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_TRNG_INTR_MAP_M  (INTERRUPT_CORE1_LP_TRNG_INTR_MAP_V << INTERRUPT_CORE1_LP_TRNG_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_TRNG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_TRNG_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_TRNG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_REG register
+ *  LP_SYSREG_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x26c)
+/** INTERRUPT_CORE1_LP_SYSREG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_M  (INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_V << INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_SYSREG_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_REG register
+ *  LP_APM_M0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x270)
+/** INTERRUPT_CORE1_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_M  (INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_REG register
+ *  LP_APM_M1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x274)
+/** INTERRUPT_CORE1_LP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_M  (INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_V << INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_REG register
+ *  LP_APM_M2_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x278)
+/** INTERRUPT_CORE1_LP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_M  (INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_V << INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M2_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_REG register
+ *  LP_APM_M3_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x27c)
+/** INTERRUPT_CORE1_LP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_M  (INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_V << INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_APM_M3_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_REG register
+ *  LP_PERI0_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x280)
+/** INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_M  (INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_V << INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_PERI0_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_REG register
+ *  LP_PERI1_PMS_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x284)
+/** INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_M  (INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_V << INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_PERI1_PMS_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_HUK_INTR_MAP_REG register
+ *  LP_HUK_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_HUK_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x288)
+/** INTERRUPT_CORE1_LP_HUK_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_HUK_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_HUK_INTR_MAP_M  (INTERRUPT_CORE1_LP_HUK_INTR_MAP_V << INTERRUPT_CORE1_LP_HUK_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_HUK_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_HUK_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_HUK_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_REG register
+ *  LP_PERI_TIMEOUT_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x28c)
+/** INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_M  (INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_PERI_TIMEOUT_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG register
+ *  LP_AHB_PDMA_IN_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x290)
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_M  (INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG register
+ *  LP_AHB_PDMA_IN_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x294)
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_M  (INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default: 0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_IN_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG register
+ *  LP_AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x298)
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_M  (INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH0_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG register
+ *  LP_AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x29c)
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_M  (INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_AHB_PDMA_OUT_CH1_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_REG register
+ *  LP_SW_INVALID_SLEEP_INTR mapping register
+ */
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2a0)
+/** INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
+ *  Configures the interrupt source into one CPU interrupt.
+ */
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP    0x0000003FU
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_M  (INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_V << INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_S)
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_V  0x0000003FU
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_MAP_S  0
+/** INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL : R/W; bitpos: [9:8]; default:
+ *  0;
+ *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+ *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+ *  feature with M-Level.
+ */
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL    0x00000003U
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_M  (INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V << INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S)
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_V  0x00000003U
+#define INTERRUPT_CORE1_LP_SW_INVALID_SLEEP_INTR_PASS_LEVEL_S  8
+
+/** INTERRUPT_CORE1_SIG_IDX_ASSERT_IN_SEC_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2a4)
+/** INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S : R/W; bitpos: [5:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S    0x0000003FU
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S_M  (INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S_V << INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S_S)
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S_V  0x0000003FU
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_S_S  0
+/** INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M : R/W; bitpos: [11:6]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M    0x0000003FU
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M_M  (INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M_V << INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M_S)
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M_V  0x0000003FU
+#define INTERRUPT_CORE1_INT_SIG_IDX_ASSERT_IN_M_S  6
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_0_REG register
+ *  Status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2a8)
+/** INTERRUPT_CORE1_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
+ *  Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_0_M  (INTERRUPT_CORE1_INT_STATUS_0_V << INTERRUPT_CORE1_INT_STATUS_0_S)
+#define INTERRUPT_CORE1_INT_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_0_S  0
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_1_REG register
+ *  Status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2ac)
+/** INTERRUPT_CORE1_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
+ *  63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_1_M  (INTERRUPT_CORE1_INT_STATUS_1_V << INTERRUPT_CORE1_INT_STATUS_1_S)
+#define INTERRUPT_CORE1_INT_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_1_S  0
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_2_REG register
+ *  Status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2b0)
+/** INTERRUPT_CORE1_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
+ *  95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_2_M  (INTERRUPT_CORE1_INT_STATUS_2_V << INTERRUPT_CORE1_INT_STATUS_2_S)
+#define INTERRUPT_CORE1_INT_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_2_S  0
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_3_REG register
+ *  Status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2b4)
+/** INTERRUPT_CORE1_INT_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 96 ~
+ *  127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_3_M  (INTERRUPT_CORE1_INT_STATUS_3_V << INTERRUPT_CORE1_INT_STATUS_3_S)
+#define INTERRUPT_CORE1_INT_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_3_S  0
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_4_REG register
+ *  Status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2b8)
+/** INTERRUPT_CORE1_INT_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 128 ~
+ *  159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_4_M  (INTERRUPT_CORE1_INT_STATUS_4_V << INTERRUPT_CORE1_INT_STATUS_4_S)
+#define INTERRUPT_CORE1_INT_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_STATUS_4_S  0
+
+/** INTERRUPT_CORE1_INT_STATUS_REG_5_REG register
+ *  Status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE1_INT_STATUS_REG_5_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2bc)
+/** INTERRUPT_CORE1_INT_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the status of the interrupt sources within interrupt-index-range 160 ~
+ *  168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source triggered an interrupt
+ *  1:No interrupt triggered
+ */
+#define INTERRUPT_CORE1_INT_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE1_INT_STATUS_5_M  (INTERRUPT_CORE1_INT_STATUS_5_V << INTERRUPT_CORE1_INT_STATUS_5_S)
+#define INTERRUPT_CORE1_INT_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE1_INT_STATUS_5_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_0_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c0)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_0_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_1_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c4)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_1_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_2_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2c8)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_2_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_3_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2cc)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_3_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_4_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2d0)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_4_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_5_REG register
+ *  supervisor-mode PASS_IN status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_S_STATUS_5_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2d4)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the supervisor-mode PASS_IN status of the interrupt sources with
+ *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+ *  1:The corresponding interrupt source is PASS in supervisor-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_S_STATUS_5_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_0_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 0 ~ 31
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2d8)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_0_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_1_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 32 ~ 63
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2dc)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_1_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_2_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 64 ~ 95
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2e0)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_2_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_3_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 96 ~ 127
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2e4)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_3_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_4_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 128 ~ 159
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_4_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2e8)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4 : RO; bitpos: [31:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources within
+ *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_4_S  0
+
+/** INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_5_REG register
+ *  machine-mode PASS_IN_M status register for interrupt sources 160 ~ 168
+ */
+#define INTERRUPT_CORE1_SRC_PASS_IN_M_STATUS_5_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2ec)
+/** INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5 : RO; bitpos: [8:0]; default: 0;
+ *  Represents the machine-mode PASS_IN status of the interrupt sources with
+ *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+ *  0:The corresponding interrupt source is not PASS in machine-mode.
+ *  1:The corresponding interrupt source is PASS in machine-mode.
+ */
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5    0x000001FFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5_M  (INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5_V << INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5_S)
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5_V  0x000001FFU
+#define INTERRUPT_CORE1_INT_SRC_PASS_IN_M_STATUS_5_S  0
+
+/** INTERRUPT_CORE1_CONFIG_STATE_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE1_CONFIG_STATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2f0)
+/** INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR : RO; bitpos: [0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR    (BIT(0))
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR_M  (INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR_V << INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR_S)
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR_V  0x00000001U
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_S_ERR_S  0
+/** INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR : RO; bitpos: [1]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR    (BIT(1))
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR_M  (INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR_V << INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR_S)
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR_V  0x00000001U
+#define INTERRUPT_CORE1_SIG_IDX_ASSERT_M_ERR_S  1
+
+/** INTERRUPT_CORE1_S_STATUS_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE1_S_STATUS_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2f4)
+/** INTERRUPT_CORE1_INT_S_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_INT_S_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_S_STATUS_M  (INTERRUPT_CORE1_INT_S_STATUS_V << INTERRUPT_CORE1_INT_S_STATUS_S)
+#define INTERRUPT_CORE1_INT_S_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_S_STATUS_S  0
+
+/** INTERRUPT_CORE1_M_STATUS_REG register
+ *  reserved
+ */
+#define INTERRUPT_CORE1_M_STATUS_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2f8)
+/** INTERRUPT_CORE1_INT_M_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  reserved
+ */
+#define INTERRUPT_CORE1_INT_M_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_M_STATUS_M  (INTERRUPT_CORE1_INT_M_STATUS_V << INTERRUPT_CORE1_INT_M_STATUS_S)
+#define INTERRUPT_CORE1_INT_M_STATUS_V  0xFFFFFFFFU
+#define INTERRUPT_CORE1_INT_M_STATUS_S  0
+
+/** INTERRUPT_CORE1_CLOCK_GATE_REG register
+ *  Interrupt clock gating configure register
+ */
+#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x2fc)
+/** INTERRUPT_CORE1_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Interrupt clock gating configure register
+ */
+#define INTERRUPT_CORE1_REG_CLK_EN    (BIT(0))
+#define INTERRUPT_CORE1_REG_CLK_EN_M  (INTERRUPT_CORE1_REG_CLK_EN_V << INTERRUPT_CORE1_REG_CLK_EN_S)
+#define INTERRUPT_CORE1_REG_CLK_EN_V  0x00000001U
+#define INTERRUPT_CORE1_REG_CLK_EN_S  0
+
+/** INTERRUPT_CORE1_INTERRUPT_DATE_REG register
+ *  Version control register
+ */
+#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x7fc)
+/** INTERRUPT_CORE1_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38834448;
+ *  Version control register
+ */
+#define INTERRUPT_CORE1_INTERRUPT_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE1_INTERRUPT_DATE_M  (INTERRUPT_CORE1_INTERRUPT_DATE_V << INTERRUPT_CORE1_INTERRUPT_DATE_S)
+#define INTERRUPT_CORE1_INTERRUPT_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE1_INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/interrupt_core1_struct.h b/components/soc/esp32s31/register/soc/interrupt_core1_struct.h
new file mode 100644
index 00000000000..56e6e0332c1
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/interrupt_core1_struct.h
@@ -0,0 +1,4153 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of sys_icm_intr_map register
+ *  SYS_ICM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sys_icm_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sys_icm_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sys_icm_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sys_icm_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_sys_icm_intr_map_reg_t;
+
+/** Type of axi_perf_mon_intr_map register
+ *  AXI_PERF_MON_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_perf_mon_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_perf_mon_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_perf_mon_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_perf_mon_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_perf_mon_intr_map_reg_t;
+
+/** Type of usb_device_intr_map register
+ *  USB_DEVICE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_device_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_device_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_device_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_device_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_usb_device_intr_map_reg_t;
+
+/** Type of sdio_host_intr_map register
+ *  SDIO_HOST_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sdio_host_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sdio_host_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sdio_host_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sdio_host_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_sdio_host_intr_map_reg_t;
+
+/** Type of spi2_intr_map register
+ *  SPI2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** spi2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t spi2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** spi2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t spi2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_spi2_intr_map_reg_t;
+
+/** Type of spi3_intr_map register
+ *  SPI3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** spi3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t spi3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** spi3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t spi3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_spi3_intr_map_reg_t;
+
+/** Type of i2s0_intr_map register
+ *  I2S0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2s0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2s0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2s0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2s0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_i2s0_intr_map_reg_t;
+
+/** Type of i2s1_intr_map register
+ *  I2S1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2s1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2s1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2s1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_i2s1_intr_map_reg_t;
+
+/** Type of uhci0_intr_map register
+ *  UHCI0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uhci0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uhci0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uhci0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uhci0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_uhci0_intr_map_reg_t;
+
+/** Type of uart0_intr_map register
+ *  UART0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_uart0_intr_map_reg_t;
+
+/** Type of uart1_intr_map register
+ *  UART1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_uart1_intr_map_reg_t;
+
+/** Type of uart2_intr_map register
+ *  UART2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_uart2_intr_map_reg_t;
+
+/** Type of uart3_intr_map register
+ *  UART3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** uart3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t uart3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** uart3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t uart3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_uart3_intr_map_reg_t;
+
+/** Type of lcd_cam_intr_map register
+ *  LCD_CAM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lcd_cam_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lcd_cam_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lcd_cam_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lcd_cam_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lcd_cam_intr_map_reg_t;
+
+/** Type of pwm0_intr_map register
+ *  PWM0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pwm0_intr_map_reg_t;
+
+/** Type of pwm1_intr_map register
+ *  PWM1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pwm1_intr_map_reg_t;
+
+/** Type of pwm2_intr_map register
+ *  PWM2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pwm2_intr_map_reg_t;
+
+/** Type of pwm3_intr_map register
+ *  PWM3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pwm3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pwm3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pwm3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pwm3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pwm3_intr_map_reg_t;
+
+/** Type of can0_intr_map register
+ *  CAN0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_can0_intr_map_reg_t;
+
+/** Type of can0_timer_intr_map register
+ *  CAN0_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can0_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can0_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can0_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can0_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_can0_timer_intr_map_reg_t;
+
+/** Type of can1_intr_map register
+ *  CAN1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_can1_intr_map_reg_t;
+
+/** Type of can1_timer_intr_map register
+ *  CAN1_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** can1_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t can1_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** can1_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t can1_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_can1_timer_intr_map_reg_t;
+
+/** Type of rmt_intr_map register
+ *  RMT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rmt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rmt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rmt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rmt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_rmt_intr_map_reg_t;
+
+/** Type of i2c0_intr_map register
+ *  I2C0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2c0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2c0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2c0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2c0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_i2c0_intr_map_reg_t;
+
+/** Type of i2c1_intr_map register
+ *  I2C1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** i2c1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t i2c1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** i2c1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t i2c1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_i2c1_intr_map_reg_t;
+
+/** Type of timergrp0_t0_intr_map register
+ *  TIMERGRP0_T0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_t0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_t0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_t0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_t0_intr_map_reg_t;
+
+/** Type of timergrp0_t1_intr_map register
+ *  TIMERGRP0_T1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_t1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_t1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_t1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_t1_intr_map_reg_t;
+
+/** Type of timergrp0_wdt_intr_map register
+ *  TIMERGRP0_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp0_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp0_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp0_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp0_wdt_intr_map_reg_t;
+
+/** Type of timergrp1_t0_intr_map register
+ *  TIMERGRP1_T0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_t0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_t0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_t0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_t0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_t0_intr_map_reg_t;
+
+/** Type of timergrp1_t1_intr_map register
+ *  TIMERGRP1_T1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_t1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_t1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_t1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_t1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_t1_intr_map_reg_t;
+
+/** Type of timergrp1_wdt_intr_map register
+ *  TIMERGRP1_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** timergrp1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t timergrp1_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** timergrp1_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t timergrp1_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_timergrp1_wdt_intr_map_reg_t;
+
+/** Type of ledc0_intr_map register
+ *  LEDC0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ledc0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ledc0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ledc0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ledc0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ledc0_intr_map_reg_t;
+
+/** Type of ledc1_intr_map register
+ *  LEDC1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ledc1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ledc1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ledc1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ledc1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ledc1_intr_map_reg_t;
+
+/** Type of systimer_target0_intr_map register
+ *  SYSTIMER_TARGET0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target0_intr_map_reg_t;
+
+/** Type of systimer_target1_intr_map register
+ *  SYSTIMER_TARGET1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target1_intr_map_reg_t;
+
+/** Type of systimer_target2_intr_map register
+ *  SYSTIMER_TARGET2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t systimer_target2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** systimer_target2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t systimer_target2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_systimer_target2_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch0_intr_map register
+ *  AHB_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch1_intr_map register
+ *  AHB_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch2_intr_map register
+ *  AHB_PDMA_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch2_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch3_intr_map register
+ *  AHB_PDMA_IN_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch3_intr_map_reg_t;
+
+/** Type of ahb_pdma_in_ch4_intr_map register
+ *  AHB_PDMA_IN_CH4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_in_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_in_ch4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_in_ch4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_in_ch4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_in_ch4_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch0_intr_map register
+ *  AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch1_intr_map register
+ *  AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch2_intr_map register
+ *  AHB_PDMA_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch2_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch3_intr_map register
+ *  AHB_PDMA_OUT_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch3_intr_map_reg_t;
+
+/** Type of ahb_pdma_out_ch4_intr_map register
+ *  AHB_PDMA_OUT_CH4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ahb_pdma_out_ch4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ahb_pdma_out_ch4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ahb_pdma_out_ch4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ahb_pdma_out_ch4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ahb_pdma_out_ch4_intr_map_reg_t;
+
+/** Type of asrc_chnl0_intr_map register
+ *  ASRC_CHNL0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** asrc_chnl0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t asrc_chnl0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** asrc_chnl0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t asrc_chnl0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_asrc_chnl0_intr_map_reg_t;
+
+/** Type of asrc_chnl1_intr_map register
+ *  ASRC_CHNL1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** asrc_chnl1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t asrc_chnl1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** asrc_chnl1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t asrc_chnl1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_asrc_chnl1_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch0_intr_map register
+ *  AXI_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch1_intr_map register
+ *  AXI_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of axi_pdma_in_ch2_intr_map register
+ *  AXI_PDMA_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_in_ch2_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch0_intr_map register
+ *  AXI_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch1_intr_map register
+ *  AXI_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of axi_pdma_out_ch2_intr_map register
+ *  AXI_PDMA_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** axi_pdma_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t axi_pdma_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** axi_pdma_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t axi_pdma_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_axi_pdma_out_ch2_intr_map_reg_t;
+
+/** Type of rsa_intr_map register
+ *  RSA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rsa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rsa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rsa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rsa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_rsa_intr_map_reg_t;
+
+/** Type of aes_intr_map register
+ *  AES_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** aes_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t aes_intr_map:6;
+        uint32_t reserved_6:2;
+        /** aes_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t aes_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_aes_intr_map_reg_t;
+
+/** Type of sha_intr_map register
+ *  SHA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sha_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sha_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sha_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sha_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_sha_intr_map_reg_t;
+
+/** Type of ecc_intr_map register
+ *  ECC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ecc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ecc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ecc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ecc_intr_map_reg_t;
+
+/** Type of ecdsa_intr_map register
+ *  ECDSA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ecdsa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ecdsa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ecdsa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ecdsa_intr_map_reg_t;
+
+/** Type of km_intr_map register
+ *  KM_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** km_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t km_intr_map:6;
+        uint32_t reserved_6:2;
+        /** km_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t km_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_km_intr_map_reg_t;
+
+/** Type of rma_intr_map register
+ *  RMA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** rma_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t rma_intr_map:6;
+        uint32_t reserved_6:2;
+        /** rma_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t rma_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_rma_intr_map_reg_t;
+
+/** Type of gpio_intr0_map register
+ *  GPIO_INTR0 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr0_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr0_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr0_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_intr0_map_reg_t;
+
+/** Type of gpio_intr1_map register
+ *  GPIO_INTR1 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr1_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr1_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr1_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_intr1_map_reg_t;
+
+/** Type of gpio_intr2_map register
+ *  GPIO_INTR2 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr2_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr2_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr2_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_intr2_map_reg_t;
+
+/** Type of gpio_intr3_map register
+ *  GPIO_INTR3 mapping register
+ */
+typedef union {
+    struct {
+        /** gpio_intr3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t gpio_intr3_map:6;
+        uint32_t reserved_6:2;
+        /** gpio_intr3_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t gpio_intr3_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_gpio_intr3_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_0_map register
+ *  CPU_INTR_FROM_CPU_0 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_0_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_0_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_0_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_intr_from_cpu_0_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_1_map register
+ *  CPU_INTR_FROM_CPU_1 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_1_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_1_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_1_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_intr_from_cpu_1_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_2_map register
+ *  CPU_INTR_FROM_CPU_2 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_2_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_2_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_2_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_intr_from_cpu_2_map_reg_t;
+
+/** Type of cpu_intr_from_cpu_3_map register
+ *  CPU_INTR_FROM_CPU_3 mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_intr_from_cpu_3_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_intr_from_cpu_3_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_intr_from_cpu_3_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_intr_from_cpu_3_map_reg_t;
+
+/** Type of cache_intr_map register
+ *  CACHE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cache_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cache_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cache_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cache_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cache_intr_map_reg_t;
+
+/** Type of cpu_apm_m0_intr_map register
+ *  CPU_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_apm_m0_intr_map_reg_t;
+
+/** Type of cpu_apm_m1_intr_map register
+ *  CPU_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_apm_m1_intr_map_reg_t;
+
+/** Type of cpu_apm_m2_intr_map register
+ *  CPU_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_apm_m2_intr_map_reg_t;
+
+/** Type of cpu_apm_m3_intr_map register
+ *  CPU_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_apm_m3_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m0_intr_map register
+ *  HP_MEM_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m0_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m1_intr_map register
+ *  HP_MEM_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m1_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m2_intr_map register
+ *  HP_MEM_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m2_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m3_intr_map register
+ *  HP_MEM_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m3_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m4_intr_map register
+ *  HP_MEM_APM_M4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m4_intr_map_reg_t;
+
+/** Type of hp_mem_apm_m5_intr_map register
+ *  HP_MEM_APM_M5_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_mem_apm_m5_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_mem_apm_m5_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_mem_apm_m5_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_mem_apm_m5_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_mem_apm_m5_intr_map_reg_t;
+
+/** Type of cpu_peri0_timeout_intr_map register
+ *  CPU_PERI0_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_peri0_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_peri0_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_peri0_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_peri0_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_peri0_timeout_intr_map_reg_t;
+
+/** Type of cpu_peri1_timeout_intr_map register
+ *  CPU_PERI1_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu_peri1_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu_peri1_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu_peri1_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu_peri1_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu_peri1_timeout_intr_map_reg_t;
+
+/** Type of hp_peri0_timeout_intr_map register
+ *  HP_PERI0_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri0_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri0_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri0_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_peri0_timeout_intr_map_reg_t;
+
+/** Type of hp_peri1_timeout_intr_map register
+ *  HP_PERI1_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri1_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri1_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri1_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_peri1_timeout_intr_map_reg_t;
+
+/** Type of hp_apm_m0_intr_map register
+ *  HP_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m0_intr_map_reg_t;
+
+/** Type of hp_apm_m1_intr_map register
+ *  HP_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m1_intr_map_reg_t;
+
+/** Type of hp_apm_m2_intr_map register
+ *  HP_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m2_intr_map_reg_t;
+
+/** Type of hp_apm_m3_intr_map register
+ *  HP_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m3_intr_map_reg_t;
+
+/** Type of hp_apm_m4_intr_map register
+ *  HP_APM_M4_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m4_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m4_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m4_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m4_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m4_intr_map_reg_t;
+
+/** Type of hp_apm_m5_intr_map register
+ *  HP_APM_M5_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m5_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m5_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m5_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m5_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m5_intr_map_reg_t;
+
+/** Type of hp_apm_m6_intr_map register
+ *  HP_APM_M6_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_apm_m6_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_apm_m6_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_apm_m6_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_apm_m6_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_apm_m6_intr_map_reg_t;
+
+/** Type of hp_peri0_pms_intr_map register
+ *  HP_PERI0_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri0_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri0_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri0_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri0_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_peri0_pms_intr_map_reg_t;
+
+/** Type of hp_peri1_pms_intr_map register
+ *  HP_PERI1_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_peri1_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_peri1_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_peri1_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_peri1_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_peri1_pms_intr_map_reg_t;
+
+/** Type of cpu0_peri_pms_intr_map register
+ *  CPU0_PERI_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu0_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu0_peri_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu0_peri_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu0_peri_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu0_peri_pms_intr_map_reg_t;
+
+/** Type of cpu1_peri_pms_intr_map register
+ *  CPU1_PERI_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cpu1_peri_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cpu1_peri_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cpu1_peri_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cpu1_peri_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cpu1_peri_pms_intr_map_reg_t;
+
+/** Type of flash_mspi_intr_map register
+ *  FLASH_MSPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** flash_mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t flash_mspi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** flash_mspi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t flash_mspi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_flash_mspi_intr_map_reg_t;
+
+/** Type of lpi_intr_map register
+ *  LPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lpi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lpi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lpi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lpi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lpi_intr_map_reg_t;
+
+/** Type of pmt_intr_map register
+ *  PMT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pmt_intr_map_reg_t;
+
+/** Type of sbd_intr_map register
+ *  SBD_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** sbd_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t sbd_intr_map:6;
+        uint32_t reserved_6:2;
+        /** sbd_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t sbd_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_sbd_intr_map_reg_t;
+
+/** Type of usb_otghs_intr_map register
+ *  USB_OTGHS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_otghs_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_otghs_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_otghs_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_otghs_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_usb_otghs_intr_map_reg_t;
+
+/** Type of usb_otghs_endp_multi_proc_intr_map register
+ *  USB_OTGHS_ENDP_MULTI_PROC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** usb_otghs_endp_multi_proc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t usb_otghs_endp_multi_proc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** usb_otghs_endp_multi_proc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t usb_otghs_endp_multi_proc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_usb_otghs_endp_multi_proc_intr_map_reg_t;
+
+/** Type of jpeg_intr_map register
+ *  JPEG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** jpeg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t jpeg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** jpeg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t jpeg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_jpeg_intr_map_reg_t;
+
+/** Type of ppa_intr_map register
+ *  PPA_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** ppa_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t ppa_intr_map:6;
+        uint32_t reserved_6:2;
+        /** ppa_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t ppa_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_ppa_intr_map_reg_t;
+
+/** Type of core0_trace_intr_map register
+ *  CORE0_TRACE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core0_trace_intr_map:6;
+        uint32_t reserved_6:2;
+        /** core0_trace_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t core0_trace_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_core0_trace_intr_map_reg_t;
+
+/** Type of core1_trace_intr_map register
+ *  CORE1_TRACE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** core1_trace_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t core1_trace_intr_map:6;
+        uint32_t reserved_6:2;
+        /** core1_trace_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t core1_trace_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_core1_trace_intr_map_reg_t;
+
+/** Type of dma2d_in_ch0_intr_map register
+ *  DMA2D_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_in_ch0_intr_map_reg_t;
+
+/** Type of dma2d_in_ch1_intr_map register
+ *  DMA2D_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_in_ch1_intr_map_reg_t;
+
+/** Type of dma2d_in_ch2_intr_map register
+ *  DMA2D_IN_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_in_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_in_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_in_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_in_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_in_ch2_intr_map_reg_t;
+
+/** Type of dma2d_out_ch0_intr_map register
+ *  DMA2D_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch0_intr_map_reg_t;
+
+/** Type of dma2d_out_ch1_intr_map register
+ *  DMA2D_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch1_intr_map_reg_t;
+
+/** Type of dma2d_out_ch2_intr_map register
+ *  DMA2D_OUT_CH2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch2_intr_map_reg_t;
+
+/** Type of dma2d_out_ch3_intr_map register
+ *  DMA2D_OUT_CH3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** dma2d_out_ch3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t dma2d_out_ch3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** dma2d_out_ch3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t dma2d_out_ch3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_dma2d_out_ch3_intr_map_reg_t;
+
+/** Type of psram_mspi_intr_map register
+ *  PSRAM_MSPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** psram_mspi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t psram_mspi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** psram_mspi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t psram_mspi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_psram_mspi_intr_map_reg_t;
+
+/** Type of hp_sysreg_intr_map register
+ *  HP_SYSREG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_sysreg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_sysreg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_sysreg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_sysreg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_sysreg_intr_map_reg_t;
+
+/** Type of pcnt0_intr_map register
+ *  PCNT0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pcnt0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pcnt0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pcnt0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pcnt0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pcnt0_intr_map_reg_t;
+
+/** Type of pcnt1_intr_map register
+ *  PCNT1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pcnt1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pcnt1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pcnt1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pcnt1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pcnt1_intr_map_reg_t;
+
+/** Type of hp_pau_intr_map register
+ *  HP_PAU_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_pau_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_pau_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_pau_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_pau_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_pau_intr_map_reg_t;
+
+/** Type of hp_parlio_rx_intr_map register
+ *  HP_PARLIO_RX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_parlio_rx_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_parlio_rx_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_parlio_rx_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_parlio_rx_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_parlio_rx_intr_map_reg_t;
+
+/** Type of hp_parlio_tx_intr_map register
+ *  HP_PARLIO_TX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** hp_parlio_tx_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t hp_parlio_tx_intr_map:6;
+        uint32_t reserved_6:2;
+        /** hp_parlio_tx_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t hp_parlio_tx_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_hp_parlio_tx_intr_map_reg_t;
+
+/** Type of bus_monitor_intr_map register
+ *  BUS_MONITOR_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** bus_monitor_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t bus_monitor_intr_map:6;
+        uint32_t reserved_6:2;
+        /** bus_monitor_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t bus_monitor_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_bus_monitor_intr_map_reg_t;
+
+/** Type of modem_wifi_mac_intr_map register
+ *  MODEM_WIFI_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_wifi_mac_intr_map_reg_t;
+
+/** Type of modem_wifi_mac_nmi_intr_map register
+ *  MODEM_WIFI_MAC_NMI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_mac_nmi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_mac_nmi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_mac_nmi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_mac_nmi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_wifi_mac_nmi_intr_map_reg_t;
+
+/** Type of modem_wifi_pwr_intr_map register
+ *  MODEM_WIFI_PWR_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_pwr_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_pwr_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_pwr_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_wifi_pwr_intr_map_reg_t;
+
+/** Type of modem_wifi_bb_intr_map register
+ *  MODEM_WIFI_BB_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_wifi_bb_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_wifi_bb_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_wifi_bb_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_wifi_bb_intr_map_reg_t;
+
+/** Type of modem_bt_mac_intr_map register
+ *  MODEM_BT_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_bt_mac_intr_map_reg_t;
+
+/** Type of modem_bt_bb_intr_map register
+ *  MODEM_BT_BB_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_bb_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_bb_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_bb_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_bt_bb_intr_map_reg_t;
+
+/** Type of modem_bt_bb_nmi_intr_map register
+ *  MODEM_BT_BB_NMI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_bb_nmi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_bb_nmi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_bb_nmi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_bb_nmi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_bt_bb_nmi_intr_map_reg_t;
+
+/** Type of modem_lp_timer_intr_map register
+ *  MODEM_LP_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_lp_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_lp_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_lp_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_lp_timer_intr_map_reg_t;
+
+/** Type of modem_coex_intr_map register
+ *  MODEM_COEX_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_coex_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_coex_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_coex_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_coex_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_coex_intr_map_reg_t;
+
+/** Type of modem_ble_timer_intr_map register
+ *  MODEM_BLE_TIMER_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_ble_timer_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_ble_timer_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_ble_timer_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_ble_timer_intr_map_reg_t;
+
+/** Type of modem_ble_sec_intr_map register
+ *  MODEM_BLE_SEC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_ble_sec_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_ble_sec_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_ble_sec_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_ble_sec_intr_map_reg_t;
+
+/** Type of modem_i2c_mst_intr_map register
+ *  MODEM_I2C_MST_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_i2c_mst_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_i2c_mst_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_i2c_mst_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_i2c_mst_intr_map_reg_t;
+
+/** Type of modem_zb_mac_intr_map register
+ *  MODEM_ZB_MAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_zb_mac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_zb_mac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_zb_mac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_zb_mac_intr_map_reg_t;
+
+/** Type of modem_bt_mac_int1_intr_map register
+ *  MODEM_BT_MAC_INT1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** modem_bt_mac_int1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t modem_bt_mac_int1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** modem_bt_mac_int1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t modem_bt_mac_int1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_modem_bt_mac_int1_intr_map_reg_t;
+
+/** Type of cordic_intr_map register
+ *  CORDIC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** cordic_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t cordic_intr_map:6;
+        uint32_t reserved_6:2;
+        /** cordic_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t cordic_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_cordic_intr_map_reg_t;
+
+/** Type of zero_det_intr_map register
+ *  ZERO_DET_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** zero_det_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t zero_det_intr_map:6;
+        uint32_t reserved_6:2;
+        /** zero_det_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t zero_det_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_zero_det_intr_map_reg_t;
+
+/** Type of lp_wdt_intr_map register
+ *  LP_WDT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_wdt_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_wdt_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_wdt_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_wdt_intr_map_reg_t;
+
+/** Type of lp_timer_reg_0_intr_map register
+ *  LP_TIMER_REG_0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_timer_reg_0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_timer_reg_0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_timer_reg_0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_timer_reg_0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_timer_reg_0_intr_map_reg_t;
+
+/** Type of lp_timer_reg_1_intr_map register
+ *  LP_TIMER_REG_1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_timer_reg_1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_timer_reg_1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_timer_reg_1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_timer_reg_1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_timer_reg_1_intr_map_reg_t;
+
+/** Type of mb_hp_intr_map register
+ *  MB_HP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** mb_hp_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t mb_hp_intr_map:6;
+        uint32_t reserved_6:2;
+        /** mb_hp_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t mb_hp_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_mb_hp_intr_map_reg_t;
+
+/** Type of mb_lp_intr_map register
+ *  MB_LP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** mb_lp_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t mb_lp_intr_map:6;
+        uint32_t reserved_6:2;
+        /** mb_lp_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t mb_lp_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_mb_lp_intr_map_reg_t;
+
+/** Type of pmu_reg_0_intr_map register
+ *  PMU_REG_0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmu_reg_0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmu_reg_0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmu_reg_0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmu_reg_0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pmu_reg_0_intr_map_reg_t;
+
+/** Type of pmu_reg_1_intr_map register
+ *  PMU_REG_1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** pmu_reg_1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t pmu_reg_1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** pmu_reg_1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t pmu_reg_1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_pmu_reg_1_intr_map_reg_t;
+
+/** Type of lp_anaperi_intr_map register
+ *  LP_ANAPERI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_anaperi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_anaperi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_anaperi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_anaperi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_anaperi_intr_map_reg_t;
+
+/** Type of lp_adc_intr_map register
+ *  LP_ADC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_adc_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_adc_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_adc_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_adc_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_adc_intr_map_reg_t;
+
+/** Type of lp_dac_intr_map register
+ *  LP_DAC_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_dac_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_dac_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_dac_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_dac_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_dac_intr_map_reg_t;
+
+/** Type of lp_gpio_intr_map register
+ *  LP_GPIO_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_gpio_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_gpio_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_gpio_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_gpio_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_gpio_intr_map_reg_t;
+
+/** Type of lp_i2c_intr_map register
+ *  LP_I2C_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_i2c_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_i2c_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_i2c_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_i2c_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_i2c_intr_map_reg_t;
+
+/** Type of lp_spi_intr_map register
+ *  LP_SPI_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_spi_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_spi_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_spi_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_spi_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_spi_intr_map_reg_t;
+
+/** Type of lp_touch_intr_map register
+ *  LP_TOUCH_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_touch_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_touch_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_touch_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_touch_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_touch_intr_map_reg_t;
+
+/** Type of lp_tsens_intr_map register
+ *  LP_TSENS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_tsens_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_tsens_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_tsens_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_tsens_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_tsens_intr_map_reg_t;
+
+/** Type of lp_uart_intr_map register
+ *  LP_UART_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_uart_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_uart_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_uart_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_uart_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_uart_intr_map_reg_t;
+
+/** Type of lp_efuse_intr_map register
+ *  LP_EFUSE_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_efuse_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_efuse_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_efuse_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_efuse_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_efuse_intr_map_reg_t;
+
+/** Type of lp_sw_intr_map register
+ *  LP_SW_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sw_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sw_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sw_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sw_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_sw_intr_map_reg_t;
+
+/** Type of lp_trng_intr_map register
+ *  LP_TRNG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_trng_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_trng_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_trng_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_trng_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_trng_intr_map_reg_t;
+
+/** Type of lp_sysreg_intr_map register
+ *  LP_SYSREG_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sysreg_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sysreg_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sysreg_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sysreg_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_sysreg_intr_map_reg_t;
+
+/** Type of lp_apm_m0_intr_map register
+ *  LP_APM_M0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_apm_m0_intr_map_reg_t;
+
+/** Type of lp_apm_m1_intr_map register
+ *  LP_APM_M1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_apm_m1_intr_map_reg_t;
+
+/** Type of lp_apm_m2_intr_map register
+ *  LP_APM_M2_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m2_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m2_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m2_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_apm_m2_intr_map_reg_t;
+
+/** Type of lp_apm_m3_intr_map register
+ *  LP_APM_M3_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_apm_m3_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_apm_m3_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_apm_m3_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_apm_m3_intr_map_reg_t;
+
+/** Type of lp_peri0_pms_intr_map register
+ *  LP_PERI0_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri0_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri0_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri0_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri0_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_peri0_pms_intr_map_reg_t;
+
+/** Type of lp_peri1_pms_intr_map register
+ *  LP_PERI1_PMS_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri1_pms_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri1_pms_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri1_pms_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri1_pms_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_peri1_pms_intr_map_reg_t;
+
+/** Type of lp_huk_intr_map register
+ *  LP_HUK_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_huk_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_huk_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_huk_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_huk_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_huk_intr_map_reg_t;
+
+/** Type of lp_peri_timeout_intr_map register
+ *  LP_PERI_TIMEOUT_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_peri_timeout_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_peri_timeout_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_peri_timeout_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_peri_timeout_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_in_ch0_intr_map register
+ *  LP_AHB_PDMA_IN_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_in_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_in_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_in_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_ahb_pdma_in_ch0_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_in_ch1_intr_map register
+ *  LP_AHB_PDMA_IN_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_in_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_in_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_in_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_ahb_pdma_in_ch1_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_out_ch0_intr_map register
+ *  LP_AHB_PDMA_OUT_CH0_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_out_ch0_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_out_ch0_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_out_ch0_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_ahb_pdma_out_ch0_intr_map_reg_t;
+
+/** Type of lp_ahb_pdma_out_ch1_intr_map register
+ *  LP_AHB_PDMA_OUT_CH1_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_ahb_pdma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_ahb_pdma_out_ch1_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_ahb_pdma_out_ch1_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_ahb_pdma_out_ch1_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_ahb_pdma_out_ch1_intr_map_reg_t;
+
+/** Type of lp_sw_invalid_sleep_intr_map register
+ *  LP_SW_INVALID_SLEEP_INTR mapping register
+ */
+typedef union {
+    struct {
+        /** lp_sw_invalid_sleep_intr_map : R/W; bitpos: [5:0]; default: 0;
+         *  Configures the interrupt source into one CPU interrupt.
+         */
+        uint32_t lp_sw_invalid_sleep_intr_map:6;
+        uint32_t reserved_6:2;
+        /** lp_sw_invalid_sleep_intr_pass_level : R/W; bitpos: [9:8]; default: 0;
+         *  Set as Non-zero value to enable interrupt-remap feature of the interrupt source.
+         *  0=disable remap feature. 1=enable remap feature with S-Level. 2/3=enable remap
+         *  feature with M-Level.
+         */
+        uint32_t lp_sw_invalid_sleep_intr_pass_level:2;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} interrupt_core1_lp_sw_invalid_sleep_intr_map_reg_t;
+
+/** Type of sig_idx_assert_in_sec register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_sig_idx_assert_in_s : R/W; bitpos: [5:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_sig_idx_assert_in_s:6;
+        /** int_sig_idx_assert_in_m : R/W; bitpos: [11:6]; default: 0;
+         *  reserved
+         */
+        uint32_t int_sig_idx_assert_in_m:6;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} interrupt_core1_sig_idx_assert_in_sec_reg_t;
+
+/** Type of clock_gate register
+ *  Interrupt clock gating configure register
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 0;
+         *  Interrupt clock gating configure register
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} interrupt_core1_clock_gate_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of int_status_reg_0 register
+ *  Status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31.
+         *  Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_0_reg_t;
+
+/** Type of int_status_reg_1 register
+ *  Status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 32 ~
+         *  63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_1_reg_t;
+
+/** Type of int_status_reg_2 register
+ *  Status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 64 ~
+         *  95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_2_reg_t;
+
+/** Type of int_status_reg_3 register
+ *  Status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 96 ~
+         *  127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_3_reg_t;
+
+/** Type of int_status_reg_4 register
+ *  Status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 128 ~
+         *  159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_4_reg_t;
+
+/** Type of int_status_reg_5 register
+ *  Status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the status of the interrupt sources within interrupt-index-range 160 ~
+         *  168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source triggered an interrupt
+         *  1:No interrupt triggered
+         */
+        uint32_t int_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core1_int_status_reg_5_reg_t;
+
+/** Type of src_pass_in_s_status_0 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_0_reg_t;
+
+/** Type of src_pass_in_s_status_1 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_1_reg_t;
+
+/** Type of src_pass_in_s_status_2 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_2_reg_t;
+
+/** Type of src_pass_in_s_status_3 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_3_reg_t;
+
+/** Type of src_pass_in_s_status_4 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_4_reg_t;
+
+/** Type of src_pass_in_s_status_5 register
+ *  supervisor-mode PASS_IN status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_s_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the supervisor-mode PASS_IN status of the interrupt sources with
+         *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in supervisor-mode.
+         *  1:The corresponding interrupt source is PASS in supervisor-mode.
+         */
+        uint32_t int_src_pass_in_s_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_s_status_5_reg_t;
+
+/** Type of src_pass_in_m_status_0 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 0 ~ 31
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_0 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_0:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_0_reg_t;
+
+/** Type of src_pass_in_m_status_1 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 32 ~ 63
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_1 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_1:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_1_reg_t;
+
+/** Type of src_pass_in_m_status_2 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 64 ~ 95
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_2 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 64 ~ 95. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_2:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_2_reg_t;
+
+/** Type of src_pass_in_m_status_3 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 96 ~ 127
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_3 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 96 ~ 127. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_3:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_3_reg_t;
+
+/** Type of src_pass_in_m_status_4 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 128 ~ 159
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_4 : RO; bitpos: [31:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources within
+         *  interrupt-index-range 128 ~ 159. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_4:32;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_4_reg_t;
+
+/** Type of src_pass_in_m_status_5 register
+ *  machine-mode PASS_IN_M status register for interrupt sources 160 ~ 168
+ */
+typedef union {
+    struct {
+        /** int_src_pass_in_m_status_5 : RO; bitpos: [8:0]; default: 0;
+         *  Represents the machine-mode PASS_IN status of the interrupt sources with
+         *  interrupt-index-range 160 ~ 168. Each bit corresponds to one interrupt source
+         *  0:The corresponding interrupt source is not PASS in machine-mode.
+         *  1:The corresponding interrupt source is PASS in machine-mode.
+         */
+        uint32_t int_src_pass_in_m_status_5:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} interrupt_core1_src_pass_in_m_status_5_reg_t;
+
+/** Type of config_state register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** sig_idx_assert_s_err : RO; bitpos: [0]; default: 0;
+         *  reserved
+         */
+        uint32_t sig_idx_assert_s_err:1;
+        /** sig_idx_assert_m_err : RO; bitpos: [1]; default: 0;
+         *  reserved
+         */
+        uint32_t sig_idx_assert_m_err:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} interrupt_core1_config_state_reg_t;
+
+/** Type of s_status register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_s_status : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_s_status:32;
+    };
+    uint32_t val;
+} interrupt_core1_s_status_reg_t;
+
+/** Type of m_status register
+ *  reserved
+ */
+typedef union {
+    struct {
+        /** int_m_status : RO; bitpos: [31:0]; default: 0;
+         *  reserved
+         */
+        uint32_t int_m_status:32;
+    };
+    uint32_t val;
+} interrupt_core1_m_status_reg_t;
+
+
+/** Group: Version Register */
+/** Type of interrupt_date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** interrupt_date : R/W; bitpos: [27:0]; default: 38834448;
+         *  Version control register
+         */
+        uint32_t interrupt_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} interrupt_core1_interrupt_date_reg_t;
+
+
+typedef struct {
+    volatile interrupt_core1_sys_icm_intr_map_reg_t sys_icm_intr_map;
+    volatile interrupt_core1_axi_perf_mon_intr_map_reg_t axi_perf_mon_intr_map;
+    volatile interrupt_core1_usb_device_intr_map_reg_t usb_device_intr_map;
+    volatile interrupt_core1_sdio_host_intr_map_reg_t sdio_host_intr_map;
+    volatile interrupt_core1_spi2_intr_map_reg_t spi2_intr_map;
+    volatile interrupt_core1_spi3_intr_map_reg_t spi3_intr_map;
+    volatile interrupt_core1_i2s0_intr_map_reg_t i2s0_intr_map;
+    volatile interrupt_core1_i2s1_intr_map_reg_t i2s1_intr_map;
+    volatile interrupt_core1_uhci0_intr_map_reg_t uhci0_intr_map;
+    volatile interrupt_core1_uart0_intr_map_reg_t uart0_intr_map;
+    volatile interrupt_core1_uart1_intr_map_reg_t uart1_intr_map;
+    volatile interrupt_core1_uart2_intr_map_reg_t uart2_intr_map;
+    volatile interrupt_core1_uart3_intr_map_reg_t uart3_intr_map;
+    volatile interrupt_core1_lcd_cam_intr_map_reg_t lcd_cam_intr_map;
+    volatile interrupt_core1_pwm0_intr_map_reg_t pwm0_intr_map;
+    volatile interrupt_core1_pwm1_intr_map_reg_t pwm1_intr_map;
+    volatile interrupt_core1_pwm2_intr_map_reg_t pwm2_intr_map;
+    volatile interrupt_core1_pwm3_intr_map_reg_t pwm3_intr_map;
+    volatile interrupt_core1_can0_intr_map_reg_t can0_intr_map;
+    volatile interrupt_core1_can0_timer_intr_map_reg_t can0_timer_intr_map;
+    volatile interrupt_core1_can1_intr_map_reg_t can1_intr_map;
+    volatile interrupt_core1_can1_timer_intr_map_reg_t can1_timer_intr_map;
+    volatile interrupt_core1_rmt_intr_map_reg_t rmt_intr_map;
+    volatile interrupt_core1_i2c0_intr_map_reg_t i2c0_intr_map;
+    volatile interrupt_core1_i2c1_intr_map_reg_t i2c1_intr_map;
+    volatile interrupt_core1_timergrp0_t0_intr_map_reg_t timergrp0_t0_intr_map;
+    volatile interrupt_core1_timergrp0_t1_intr_map_reg_t timergrp0_t1_intr_map;
+    volatile interrupt_core1_timergrp0_wdt_intr_map_reg_t timergrp0_wdt_intr_map;
+    volatile interrupt_core1_timergrp1_t0_intr_map_reg_t timergrp1_t0_intr_map;
+    volatile interrupt_core1_timergrp1_t1_intr_map_reg_t timergrp1_t1_intr_map;
+    volatile interrupt_core1_timergrp1_wdt_intr_map_reg_t timergrp1_wdt_intr_map;
+    volatile interrupt_core1_ledc0_intr_map_reg_t ledc0_intr_map;
+    volatile interrupt_core1_ledc1_intr_map_reg_t ledc1_intr_map;
+    volatile interrupt_core1_systimer_target0_intr_map_reg_t systimer_target0_intr_map;
+    volatile interrupt_core1_systimer_target1_intr_map_reg_t systimer_target1_intr_map;
+    volatile interrupt_core1_systimer_target2_intr_map_reg_t systimer_target2_intr_map;
+    volatile interrupt_core1_ahb_pdma_in_ch0_intr_map_reg_t ahb_pdma_in_ch0_intr_map;
+    volatile interrupt_core1_ahb_pdma_in_ch1_intr_map_reg_t ahb_pdma_in_ch1_intr_map;
+    volatile interrupt_core1_ahb_pdma_in_ch2_intr_map_reg_t ahb_pdma_in_ch2_intr_map;
+    volatile interrupt_core1_ahb_pdma_in_ch3_intr_map_reg_t ahb_pdma_in_ch3_intr_map;
+    volatile interrupt_core1_ahb_pdma_in_ch4_intr_map_reg_t ahb_pdma_in_ch4_intr_map;
+    volatile interrupt_core1_ahb_pdma_out_ch0_intr_map_reg_t ahb_pdma_out_ch0_intr_map;
+    volatile interrupt_core1_ahb_pdma_out_ch1_intr_map_reg_t ahb_pdma_out_ch1_intr_map;
+    volatile interrupt_core1_ahb_pdma_out_ch2_intr_map_reg_t ahb_pdma_out_ch2_intr_map;
+    volatile interrupt_core1_ahb_pdma_out_ch3_intr_map_reg_t ahb_pdma_out_ch3_intr_map;
+    volatile interrupt_core1_ahb_pdma_out_ch4_intr_map_reg_t ahb_pdma_out_ch4_intr_map;
+    volatile interrupt_core1_asrc_chnl0_intr_map_reg_t asrc_chnl0_intr_map;
+    volatile interrupt_core1_asrc_chnl1_intr_map_reg_t asrc_chnl1_intr_map;
+    volatile interrupt_core1_axi_pdma_in_ch0_intr_map_reg_t axi_pdma_in_ch0_intr_map;
+    volatile interrupt_core1_axi_pdma_in_ch1_intr_map_reg_t axi_pdma_in_ch1_intr_map;
+    volatile interrupt_core1_axi_pdma_in_ch2_intr_map_reg_t axi_pdma_in_ch2_intr_map;
+    volatile interrupt_core1_axi_pdma_out_ch0_intr_map_reg_t axi_pdma_out_ch0_intr_map;
+    volatile interrupt_core1_axi_pdma_out_ch1_intr_map_reg_t axi_pdma_out_ch1_intr_map;
+    volatile interrupt_core1_axi_pdma_out_ch2_intr_map_reg_t axi_pdma_out_ch2_intr_map;
+    volatile interrupt_core1_rsa_intr_map_reg_t rsa_intr_map;
+    volatile interrupt_core1_aes_intr_map_reg_t aes_intr_map;
+    volatile interrupt_core1_sha_intr_map_reg_t sha_intr_map;
+    volatile interrupt_core1_ecc_intr_map_reg_t ecc_intr_map;
+    volatile interrupt_core1_ecdsa_intr_map_reg_t ecdsa_intr_map;
+    volatile interrupt_core1_km_intr_map_reg_t km_intr_map;
+    volatile interrupt_core1_rma_intr_map_reg_t rma_intr_map;
+    volatile interrupt_core1_gpio_intr0_map_reg_t gpio_intr0_map;
+    volatile interrupt_core1_gpio_intr1_map_reg_t gpio_intr1_map;
+    volatile interrupt_core1_gpio_intr2_map_reg_t gpio_intr2_map;
+    volatile interrupt_core1_gpio_intr3_map_reg_t gpio_intr3_map;
+    volatile interrupt_core1_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map;
+    volatile interrupt_core1_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map;
+    volatile interrupt_core1_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map;
+    volatile interrupt_core1_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map;
+    volatile interrupt_core1_cache_intr_map_reg_t cache_intr_map;
+    volatile interrupt_core1_cpu_apm_m0_intr_map_reg_t cpu_apm_m0_intr_map;
+    volatile interrupt_core1_cpu_apm_m1_intr_map_reg_t cpu_apm_m1_intr_map;
+    volatile interrupt_core1_cpu_apm_m2_intr_map_reg_t cpu_apm_m2_intr_map;
+    volatile interrupt_core1_cpu_apm_m3_intr_map_reg_t cpu_apm_m3_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m0_intr_map_reg_t hp_mem_apm_m0_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m1_intr_map_reg_t hp_mem_apm_m1_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m2_intr_map_reg_t hp_mem_apm_m2_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m3_intr_map_reg_t hp_mem_apm_m3_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m4_intr_map_reg_t hp_mem_apm_m4_intr_map;
+    volatile interrupt_core1_hp_mem_apm_m5_intr_map_reg_t hp_mem_apm_m5_intr_map;
+    volatile interrupt_core1_cpu_peri0_timeout_intr_map_reg_t cpu_peri0_timeout_intr_map;
+    volatile interrupt_core1_cpu_peri1_timeout_intr_map_reg_t cpu_peri1_timeout_intr_map;
+    volatile interrupt_core1_hp_peri0_timeout_intr_map_reg_t hp_peri0_timeout_intr_map;
+    volatile interrupt_core1_hp_peri1_timeout_intr_map_reg_t hp_peri1_timeout_intr_map;
+    volatile interrupt_core1_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map;
+    volatile interrupt_core1_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map;
+    volatile interrupt_core1_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map;
+    volatile interrupt_core1_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map;
+    volatile interrupt_core1_hp_apm_m4_intr_map_reg_t hp_apm_m4_intr_map;
+    volatile interrupt_core1_hp_apm_m5_intr_map_reg_t hp_apm_m5_intr_map;
+    volatile interrupt_core1_hp_apm_m6_intr_map_reg_t hp_apm_m6_intr_map;
+    volatile interrupt_core1_hp_peri0_pms_intr_map_reg_t hp_peri0_pms_intr_map;
+    volatile interrupt_core1_hp_peri1_pms_intr_map_reg_t hp_peri1_pms_intr_map;
+    volatile interrupt_core1_cpu0_peri_pms_intr_map_reg_t cpu0_peri_pms_intr_map;
+    volatile interrupt_core1_cpu1_peri_pms_intr_map_reg_t cpu1_peri_pms_intr_map;
+    volatile interrupt_core1_flash_mspi_intr_map_reg_t flash_mspi_intr_map;
+    volatile interrupt_core1_lpi_intr_map_reg_t lpi_intr_map;
+    volatile interrupt_core1_pmt_intr_map_reg_t pmt_intr_map;
+    volatile interrupt_core1_sbd_intr_map_reg_t sbd_intr_map;
+    volatile interrupt_core1_usb_otghs_intr_map_reg_t usb_otghs_intr_map;
+    volatile interrupt_core1_usb_otghs_endp_multi_proc_intr_map_reg_t usb_otghs_endp_multi_proc_intr_map;
+    volatile interrupt_core1_jpeg_intr_map_reg_t jpeg_intr_map;
+    volatile interrupt_core1_ppa_intr_map_reg_t ppa_intr_map;
+    volatile interrupt_core1_core0_trace_intr_map_reg_t core0_trace_intr_map;
+    volatile interrupt_core1_core1_trace_intr_map_reg_t core1_trace_intr_map;
+    volatile interrupt_core1_dma2d_in_ch0_intr_map_reg_t dma2d_in_ch0_intr_map;
+    volatile interrupt_core1_dma2d_in_ch1_intr_map_reg_t dma2d_in_ch1_intr_map;
+    volatile interrupt_core1_dma2d_in_ch2_intr_map_reg_t dma2d_in_ch2_intr_map;
+    volatile interrupt_core1_dma2d_out_ch0_intr_map_reg_t dma2d_out_ch0_intr_map;
+    volatile interrupt_core1_dma2d_out_ch1_intr_map_reg_t dma2d_out_ch1_intr_map;
+    volatile interrupt_core1_dma2d_out_ch2_intr_map_reg_t dma2d_out_ch2_intr_map;
+    volatile interrupt_core1_dma2d_out_ch3_intr_map_reg_t dma2d_out_ch3_intr_map;
+    volatile interrupt_core1_psram_mspi_intr_map_reg_t psram_mspi_intr_map;
+    volatile interrupt_core1_hp_sysreg_intr_map_reg_t hp_sysreg_intr_map;
+    volatile interrupt_core1_pcnt0_intr_map_reg_t pcnt0_intr_map;
+    volatile interrupt_core1_pcnt1_intr_map_reg_t pcnt1_intr_map;
+    volatile interrupt_core1_hp_pau_intr_map_reg_t hp_pau_intr_map;
+    volatile interrupt_core1_hp_parlio_rx_intr_map_reg_t hp_parlio_rx_intr_map;
+    volatile interrupt_core1_hp_parlio_tx_intr_map_reg_t hp_parlio_tx_intr_map;
+    volatile interrupt_core1_bus_monitor_intr_map_reg_t bus_monitor_intr_map;
+    volatile interrupt_core1_modem_wifi_mac_intr_map_reg_t modem_wifi_mac_intr_map;
+    volatile interrupt_core1_modem_wifi_mac_nmi_intr_map_reg_t modem_wifi_mac_nmi_intr_map;
+    volatile interrupt_core1_modem_wifi_pwr_intr_map_reg_t modem_wifi_pwr_intr_map;
+    volatile interrupt_core1_modem_wifi_bb_intr_map_reg_t modem_wifi_bb_intr_map;
+    volatile interrupt_core1_modem_bt_mac_intr_map_reg_t modem_bt_mac_intr_map;
+    volatile interrupt_core1_modem_bt_bb_intr_map_reg_t modem_bt_bb_intr_map;
+    volatile interrupt_core1_modem_bt_bb_nmi_intr_map_reg_t modem_bt_bb_nmi_intr_map;
+    volatile interrupt_core1_modem_lp_timer_intr_map_reg_t modem_lp_timer_intr_map;
+    volatile interrupt_core1_modem_coex_intr_map_reg_t modem_coex_intr_map;
+    volatile interrupt_core1_modem_ble_timer_intr_map_reg_t modem_ble_timer_intr_map;
+    volatile interrupt_core1_modem_ble_sec_intr_map_reg_t modem_ble_sec_intr_map;
+    volatile interrupt_core1_modem_i2c_mst_intr_map_reg_t modem_i2c_mst_intr_map;
+    volatile interrupt_core1_modem_zb_mac_intr_map_reg_t modem_zb_mac_intr_map;
+    volatile interrupt_core1_modem_bt_mac_int1_intr_map_reg_t modem_bt_mac_int1_intr_map;
+    volatile interrupt_core1_cordic_intr_map_reg_t cordic_intr_map;
+    volatile interrupt_core1_zero_det_intr_map_reg_t zero_det_intr_map;
+    volatile interrupt_core1_lp_wdt_intr_map_reg_t lp_wdt_intr_map;
+    volatile interrupt_core1_lp_timer_reg_0_intr_map_reg_t lp_timer_reg_0_intr_map;
+    volatile interrupt_core1_lp_timer_reg_1_intr_map_reg_t lp_timer_reg_1_intr_map;
+    volatile interrupt_core1_mb_hp_intr_map_reg_t mb_hp_intr_map;
+    volatile interrupt_core1_mb_lp_intr_map_reg_t mb_lp_intr_map;
+    volatile interrupt_core1_pmu_reg_0_intr_map_reg_t pmu_reg_0_intr_map;
+    volatile interrupt_core1_pmu_reg_1_intr_map_reg_t pmu_reg_1_intr_map;
+    volatile interrupt_core1_lp_anaperi_intr_map_reg_t lp_anaperi_intr_map;
+    volatile interrupt_core1_lp_adc_intr_map_reg_t lp_adc_intr_map;
+    volatile interrupt_core1_lp_dac_intr_map_reg_t lp_dac_intr_map;
+    volatile interrupt_core1_lp_gpio_intr_map_reg_t lp_gpio_intr_map;
+    volatile interrupt_core1_lp_i2c_intr_map_reg_t lp_i2c_intr_map;
+    volatile interrupt_core1_lp_spi_intr_map_reg_t lp_spi_intr_map;
+    volatile interrupt_core1_lp_touch_intr_map_reg_t lp_touch_intr_map;
+    volatile interrupt_core1_lp_tsens_intr_map_reg_t lp_tsens_intr_map;
+    volatile interrupt_core1_lp_uart_intr_map_reg_t lp_uart_intr_map;
+    volatile interrupt_core1_lp_efuse_intr_map_reg_t lp_efuse_intr_map;
+    volatile interrupt_core1_lp_sw_intr_map_reg_t lp_sw_intr_map;
+    volatile interrupt_core1_lp_trng_intr_map_reg_t lp_trng_intr_map;
+    volatile interrupt_core1_lp_sysreg_intr_map_reg_t lp_sysreg_intr_map;
+    volatile interrupt_core1_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map;
+    volatile interrupt_core1_lp_apm_m1_intr_map_reg_t lp_apm_m1_intr_map;
+    volatile interrupt_core1_lp_apm_m2_intr_map_reg_t lp_apm_m2_intr_map;
+    volatile interrupt_core1_lp_apm_m3_intr_map_reg_t lp_apm_m3_intr_map;
+    volatile interrupt_core1_lp_peri0_pms_intr_map_reg_t lp_peri0_pms_intr_map;
+    volatile interrupt_core1_lp_peri1_pms_intr_map_reg_t lp_peri1_pms_intr_map;
+    volatile interrupt_core1_lp_huk_intr_map_reg_t lp_huk_intr_map;
+    volatile interrupt_core1_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map;
+    volatile interrupt_core1_lp_ahb_pdma_in_ch0_intr_map_reg_t lp_ahb_pdma_in_ch0_intr_map;
+    volatile interrupt_core1_lp_ahb_pdma_in_ch1_intr_map_reg_t lp_ahb_pdma_in_ch1_intr_map;
+    volatile interrupt_core1_lp_ahb_pdma_out_ch0_intr_map_reg_t lp_ahb_pdma_out_ch0_intr_map;
+    volatile interrupt_core1_lp_ahb_pdma_out_ch1_intr_map_reg_t lp_ahb_pdma_out_ch1_intr_map;
+    volatile interrupt_core1_lp_sw_invalid_sleep_intr_map_reg_t lp_sw_invalid_sleep_intr_map;
+    volatile interrupt_core1_sig_idx_assert_in_sec_reg_t sig_idx_assert_in_sec;
+    volatile interrupt_core1_int_status_reg_0_reg_t int_status_reg_0;
+    volatile interrupt_core1_int_status_reg_1_reg_t int_status_reg_1;
+    volatile interrupt_core1_int_status_reg_2_reg_t int_status_reg_2;
+    volatile interrupt_core1_int_status_reg_3_reg_t int_status_reg_3;
+    volatile interrupt_core1_int_status_reg_4_reg_t int_status_reg_4;
+    volatile interrupt_core1_int_status_reg_5_reg_t int_status_reg_5;
+    volatile interrupt_core1_src_pass_in_s_status_0_reg_t src_pass_in_s_status_0;
+    volatile interrupt_core1_src_pass_in_s_status_1_reg_t src_pass_in_s_status_1;
+    volatile interrupt_core1_src_pass_in_s_status_2_reg_t src_pass_in_s_status_2;
+    volatile interrupt_core1_src_pass_in_s_status_3_reg_t src_pass_in_s_status_3;
+    volatile interrupt_core1_src_pass_in_s_status_4_reg_t src_pass_in_s_status_4;
+    volatile interrupt_core1_src_pass_in_s_status_5_reg_t src_pass_in_s_status_5;
+    volatile interrupt_core1_src_pass_in_m_status_0_reg_t src_pass_in_m_status_0;
+    volatile interrupt_core1_src_pass_in_m_status_1_reg_t src_pass_in_m_status_1;
+    volatile interrupt_core1_src_pass_in_m_status_2_reg_t src_pass_in_m_status_2;
+    volatile interrupt_core1_src_pass_in_m_status_3_reg_t src_pass_in_m_status_3;
+    volatile interrupt_core1_src_pass_in_m_status_4_reg_t src_pass_in_m_status_4;
+    volatile interrupt_core1_src_pass_in_m_status_5_reg_t src_pass_in_m_status_5;
+    volatile interrupt_core1_config_state_reg_t config_state;
+    volatile interrupt_core1_s_status_reg_t s_status;
+    volatile interrupt_core1_m_status_reg_t m_status;
+    volatile interrupt_core1_clock_gate_reg_t clock_gate;
+    uint32_t reserved_300[319];
+    volatile interrupt_core1_interrupt_date_reg_t interrupt_date;
+} interrupt_core1_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(interrupt_core1_dev_t) == 0x800, "Invalid size of interrupt_core1_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/io_mux_reg.h b/components/soc/esp32s31/register/soc/io_mux_reg.h
new file mode 100644
index 00000000000..b2f0c418b2b
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/io_mux_reg.h
@@ -0,0 +1,516 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+#include "soc/soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+
+#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define IO_MUX_GPIO0_REG                    PERIPHS_IO_MUX_U_XTAL32K_HYS_P
+#define IO_MUX_GPIO1_REG                    PERIPHS_IO_MUX_U_XTAL32K_HYS_N
+#define IO_MUX_GPIO2_REG                    PERIPHS_IO_MUX_U_GPIO2
+#define IO_MUX_GPIO3_REG                    PERIPHS_IO_MUX_U_GPIO3
+#define IO_MUX_GPIO4_REG                    PERIPHS_IO_MUX_U_GPIO4
+#define IO_MUX_GPIO5_REG                    PERIPHS_IO_MUX_U_GPIO5
+#define IO_MUX_GPIO6_REG                    PERIPHS_IO_MUX_U_TOUCH_GPIO6
+#define IO_MUX_GPIO7_REG                    PERIPHS_IO_MUX_U_TOUCH_GPIO7
+#define IO_MUX_GPIO8_REG                    PERIPHS_IO_MUX_U_TOUCH_GPIO8
+#define IO_MUX_GPIO9_REG                    PERIPHS_IO_MUX_U_TOUCH_GPIO9
+#define IO_MUX_GPIO10_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO10
+#define IO_MUX_GPIO11_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO11
+#define IO_MUX_GPIO12_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO12
+#define IO_MUX_GPIO13_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO13
+#define IO_MUX_GPIO14_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO14
+#define IO_MUX_GPIO15_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO15
+#define IO_MUX_GPIO16_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO16
+#define IO_MUX_GPIO17_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO17
+#define IO_MUX_GPIO18_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO18
+#define IO_MUX_GPIO19_REG                   PERIPHS_IO_MUX_U_TOUCH_GPIO19
+#define IO_MUX_GPIO20_REG                   PERIPHS_IO_MUX_U_GPIO20
+#define IO_MUX_GPIO21_REG                   PERIPHS_IO_MUX_U_GPIO21
+#define IO_MUX_GPIO22_REG                   PERIPHS_IO_MUX_U_GPIO22
+#define IO_MUX_GPIO23_REG                   PERIPHS_IO_MUX_U_GPIO23
+#define IO_MUX_GPIO24_REG                   PERIPHS_IO_MUX_U_GPIO24
+#define IO_MUX_GPIO25_REG                   PERIPHS_IO_MUX_U_GPIO25
+#define IO_MUX_GPIO26_REG                   PERIPHS_IO_MUX_U_GPIO26
+#define IO_MUX_GPIO27_REG                   PERIPHS_IO_MUX_U_GPIO27
+#define IO_MUX_GPIO28_REG                   PERIPHS_IO_MUX_U_GPIO28
+#define IO_MUX_GPIO29_REG                   PERIPHS_IO_MUX_U_GPIO29
+#define IO_MUX_GPIO30_REG                   PERIPHS_IO_MUX_U_GPIO30
+#define IO_MUX_GPIO31_REG                   PERIPHS_IO_MUX_U_GPIO31
+#define IO_MUX_GPIO32_REG                   PERIPHS_IO_MUX_U_GPIO32
+#define IO_MUX_GPIO33_REG                   PERIPHS_IO_MUX_U_USB_GPIO33
+#define IO_MUX_GPIO34_REG                   PERIPHS_IO_MUX_U_USB_GPIO34
+#define IO_MUX_GPIO35_REG                   PERIPHS_IO_MUX_U_GPIO35
+#define IO_MUX_GPIO36_REG                   PERIPHS_IO_MUX_U_GPIO36
+#define IO_MUX_GPIO37_REG                   PERIPHS_IO_MUX_U_GPIO37
+#define IO_MUX_GPIO38_REG                   PERIPHS_IO_MUX_U_GPIO38
+#define IO_MUX_GPIO39_REG                   PERIPHS_IO_MUX_U_GPIO39
+#define IO_MUX_GPIO40_REG                   PERIPHS_IO_MUX_U_GPIO40
+#define IO_MUX_GPIO41_REG                   PERIPHS_IO_MUX_U_GPIO41
+#define IO_MUX_GPIO42_REG                   PERIPHS_IO_MUX_U_ADC_GPIO42
+#define IO_MUX_GPIO43_REG                   PERIPHS_IO_MUX_U_ADC_GPIO43
+#define IO_MUX_GPIO44_REG                   PERIPHS_IO_MUX_U_ADC_GPIO44
+#define IO_MUX_GPIO45_REG                   PERIPHS_IO_MUX_U_ADC_GPIO45
+#define IO_MUX_GPIO46_REG                   PERIPHS_IO_MUX_U_ADC_GPIO46
+#define IO_MUX_GPIO47_REG                   PERIPHS_IO_MUX_U_ADC_GPIO47
+#define IO_MUX_GPIO48_REG                   PERIPHS_IO_MUX_U_ADC_GPIO48
+#define IO_MUX_GPIO49_REG                   PERIPHS_IO_MUX_U_ADC_GPIO49
+#define IO_MUX_GPIO50_REG                   PERIPHS_IO_MUX_U_ADC_GPIO50
+#define IO_MUX_GPIO51_REG                   PERIPHS_IO_MUX_U_ADC_GPIO51
+#define IO_MUX_GPIO52_REG                   PERIPHS_IO_MUX_U_ADC_GPIO52
+#define IO_MUX_GPIO53_REG                   PERIPHS_IO_MUX_U_ADC_GPIO53
+#define IO_MUX_GPIO54_REG                   PERIPHS_IO_MUX_U_ADC_GPIO54
+#define IO_MUX_GPIO55_REG                   PERIPHS_IO_MUX_U_ADC_GPIO55
+#define IO_MUX_GPIO56_REG                   PERIPHS_IO_MUX_U_ADC_GPIO56
+#define IO_MUX_GPIO57_REG                   PERIPHS_IO_MUX_U_ADC_GPIO57
+#define IO_MUX_GPIO58_REG                   PERIPHS_IO_MUX_U_GPIO58
+#define IO_MUX_GPIO59_REG                   PERIPHS_IO_MUX_U_GPIO59
+#define IO_MUX_GPIO60_REG                   PERIPHS_IO_MUX_U_GPIO60
+#define IO_MUX_GPIO61_REG                   PERIPHS_IO_MUX_U_GPIO61
+#define IO_MUX_GPIO62_REG                   PERIPHS_IO_MUX_U_GPIO62
+
+#define FUNC_GPIO_GPIO                              1
+#define PIN_FUNC_GPIO								1
+
+#define MAX_RTC_GPIO_NUM             7
+#define MAX_PAD_GPIO_NUM             62
+
+
+#define REG_IO_MUX_BASE                              DR_REG_IO_MUX_BASE
+
+// definitions below are generated from pin_txt.csv
+#define PERIPHS_IO_MUX_U_XTAL32K_HYS_P               (REG_IO_MUX_BASE + 0x0)
+#define FUNC_XTAL_32K_N_GPIO0_0                                            0
+#define FUNC_XTAL_32K_N_GPIO0                                              1
+
+#define PERIPHS_IO_MUX_U_XTAL32K_HYS_N               (REG_IO_MUX_BASE + 0x4)
+#define FUNC_XTAL_32K_P_GPIO1_0                                            0
+#define FUNC_XTAL_32K_P_GPIO1                                              1
+
+#define PERIPHS_IO_MUX_U_GPIO2                       (REG_IO_MUX_BASE + 0x8)
+#define FUNC_GPIO2_GPIO2_0                                                 0
+#define FUNC_GPIO2_GPIO2                                                   1
+#define FUNC_GPIO2_LCD_DATA19_OUT_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_GPIO3                       (REG_IO_MUX_BASE + 0xc)
+#define FUNC_GPIO3_GPIO3_0                                                 0
+#define FUNC_GPIO3_GPIO3                                                   1
+#define FUNC_GPIO3_LCD_DATA20_OUT_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_GPIO4                      (REG_IO_MUX_BASE + 0x10)
+#define FUNC_GPIO4_GPIO4_0                                                 0
+#define FUNC_GPIO4_GPIO4                                                   1
+#define FUNC_GPIO4_LCD_DATA21_OUT_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_GPIO5                      (REG_IO_MUX_BASE + 0x14)
+#define FUNC_GPIO5_GPIO5_0                                                 0
+#define FUNC_GPIO5_GPIO5                                                   1
+#define FUNC_GPIO5_LCD_DATA22_OUT_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO6                (REG_IO_MUX_BASE + 0x18)
+#define FUNC_GPIO6_GPIO6_0                                                 0
+#define FUNC_GPIO6_GPIO6                                                   1
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO7                (REG_IO_MUX_BASE + 0x1c)
+#define FUNC_GPIO7_GPIO7_0                                                 0
+#define FUNC_GPIO7_GPIO7                                                   1
+#define FUNC_GPIO7_LCD_DATA23_OUT_PAD                                      3
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO8                (REG_IO_MUX_BASE + 0x20)
+#define FUNC_GPIO8_GPIO8_0                                                 0
+#define FUNC_GPIO8_GPIO8                                                   1
+#define FUNC_GPIO8_GMAC_PHY_TXD0_PAD                                       2
+#define FUNC_GPIO8_LCD_DATA0_OUT_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO9                (REG_IO_MUX_BASE + 0x24)
+#define FUNC_GPIO9_SPI2_HOLD_PAD                                           0
+#define FUNC_GPIO9_GPIO9                                                   1
+#define FUNC_GPIO9_GMAC_PHY_TXD1_PAD                                       2
+#define FUNC_GPIO9_LCD_DATA1_OUT_PAD                                       3
+#define FUNC_GPIO9_DBG_PSRAM_CK_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO10               (REG_IO_MUX_BASE + 0x28)
+#define FUNC_GPIO10_SPI2_CS_PAD                                            0
+#define FUNC_GPIO10_GPIO10                                                 1
+#define FUNC_GPIO10_GMAC_PHY_TXD2_PAD                                      2
+#define FUNC_GPIO10_LCD_DATA2_OUT_PAD                                      3
+#define FUNC_GPIO10_DBG_PSRAM_CS_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO11               (REG_IO_MUX_BASE + 0x2c)
+#define FUNC_GPIO11_SPI2_D_PAD                                             0
+#define FUNC_GPIO11_GPIO11                                                 1
+#define FUNC_GPIO11_GMAC_PHY_TXD3_PAD                                      2
+#define FUNC_GPIO11_LCD_DATA3_OUT_PAD                                      3
+#define FUNC_GPIO11_DBG_PSRAM_D_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO12               (REG_IO_MUX_BASE + 0x30)
+#define FUNC_GPIO12_SPI2_CK_PAD                                            0
+#define FUNC_GPIO12_GPIO12                                                 1
+#define FUNC_GPIO12_GMAC_PHY_TXEN_PAD                                      2
+#define FUNC_GPIO12_LCD_DATA4_OUT_PAD                                      3
+#define FUNC_GPIO12_DBG_PSRAM_Q_PAD                                        4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO13               (REG_IO_MUX_BASE + 0x34)
+#define FUNC_GPIO13_SPI2_Q_PAD                                             0
+#define FUNC_GPIO13_GPIO13                                                 1
+#define FUNC_GPIO13_GMAC_RMII_CLK_PAD                                      2
+#define FUNC_GPIO13_LCD_DATA5_OUT_PAD                                      3
+#define FUNC_GPIO13_DBG_PSRAM_WP_PAD                                       4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO14               (REG_IO_MUX_BASE + 0x38)
+#define FUNC_GPIO14_SPI2_WP_PAD                                            0
+#define FUNC_GPIO14_GPIO14                                                 1
+#define FUNC_GPIO14_GMAC_RX_CLK_PAD                                        2
+#define FUNC_GPIO14_LCD_DATA6_OUT_PAD                                      3
+#define FUNC_GPIO14_DBG_PSRAM_HOLD_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO15               (REG_IO_MUX_BASE + 0x3c)
+#define FUNC_GPIO15_SPI2_IO4_PAD                                           0
+#define FUNC_GPIO15_GPIO15                                                 1
+#define FUNC_GPIO15_GMAC_PHY_RXDV_PAD                                      2
+#define FUNC_GPIO15_LCD_DATA7_OUT_PAD                                      3
+#define FUNC_GPIO15_DBG_PSRAM_DQ4_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO16               (REG_IO_MUX_BASE + 0x40)
+#define FUNC_GPIO16_SPI2_IO5_PAD                                           0
+#define FUNC_GPIO16_GPIO16                                                 1
+#define FUNC_GPIO16_GMAC_PHY_RXD3_PAD                                      2
+#define FUNC_GPIO16_LCD_DATA8_OUT_PAD                                      3
+#define FUNC_GPIO16_DBG_PSRAM_DQ5_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO17               (REG_IO_MUX_BASE + 0x44)
+#define FUNC_GPIO17_SPI2_IO6_PAD                                           0
+#define FUNC_GPIO17_GPIO17                                                 1
+#define FUNC_GPIO17_GMAC_PHY_RXD2_PAD                                      2
+#define FUNC_GPIO17_LCD_DATA9_OUT_PAD                                      3
+#define FUNC_GPIO17_DBG_PSRAM_DQ6_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO18               (REG_IO_MUX_BASE + 0x48)
+#define FUNC_GPIO18_SPI2_IO7_PAD                                           0
+#define FUNC_GPIO18_GPIO18                                                 1
+#define FUNC_GPIO18_GMAC_PHY_RXD1_PAD                                      2
+#define FUNC_GPIO18_LCD_DATA10_OUT_PAD                                     3
+#define FUNC_GPIO18_DBG_PSRAM_DQ7_PAD                                      4
+
+#define PERIPHS_IO_MUX_U_TOUCH_GPIO19               (REG_IO_MUX_BASE + 0x4c)
+#define FUNC_GPIO19_SPI2_DQS_PAD                                           0
+#define FUNC_GPIO19_GPIO19                                                 1
+#define FUNC_GPIO19_GMAC_PHY_RXD0_PAD                                      2
+#define FUNC_GPIO19_LCD_DATA11_OUT_PAD                                     3
+#define FUNC_GPIO19_DBG_PSRAM_DQS_0_PAD                                    4
+
+#define PERIPHS_IO_MUX_U_GPIO20                     (REG_IO_MUX_BASE + 0x50)
+#define FUNC_SDIO_DATA0_GPIO20_0                                           0
+#define FUNC_SDIO_DATA0_GPIO20                                             1
+#define FUNC_SDIO_DATA0_SPI2_CK_PAD                                        2
+#define FUNC_SDIO_DATA0_DBG_FLASH_CK_PAD                                   4
+
+#define PERIPHS_IO_MUX_U_GPIO21                     (REG_IO_MUX_BASE + 0x54)
+#define FUNC_SDIO_DATA1_GPIO21_0                                           0
+#define FUNC_SDIO_DATA1_GPIO21                                             1
+#define FUNC_SDIO_DATA1_SPI2_D_PAD                                         2
+#define FUNC_SDIO_DATA1_DBG_FLASH_D_PAD                                    4
+
+#define PERIPHS_IO_MUX_U_GPIO22                     (REG_IO_MUX_BASE + 0x58)
+#define FUNC_SDIO_DATA2_GPIO22_0                                           0
+#define FUNC_SDIO_DATA2_GPIO22                                             1
+#define FUNC_SDIO_DATA2_SPI2_Q_PAD                                         2
+#define FUNC_SDIO_DATA2_DBG_FLASH_CS_PAD                                   4
+
+#define PERIPHS_IO_MUX_U_GPIO23                     (REG_IO_MUX_BASE + 0x5c)
+#define FUNC_SDIO_DATA3_GPIO23_0                                           0
+#define FUNC_SDIO_DATA3_GPIO23                                             1
+#define FUNC_SDIO_DATA3_SPI2_CS_PAD                                        2
+#define FUNC_SDIO_DATA3_DBG_FLASH_Q_PAD                                    4
+
+#define PERIPHS_IO_MUX_U_GPIO24                     (REG_IO_MUX_BASE + 0x60)
+#define FUNC_SDIO_CLK_GPIO24_0                                             0
+#define FUNC_SDIO_CLK_GPIO24                                               1
+#define FUNC_SDIO_CLK_SPI2_HOLD_PAD                                        2
+#define FUNC_SDIO_CLK_DBG_FLASH_WP_PAD                                     4
+
+#define PERIPHS_IO_MUX_U_GPIO25                     (REG_IO_MUX_BASE + 0x64)
+#define FUNC_SDIO_CMD_GPIO25_0                                             0
+#define FUNC_SDIO_CMD_GPIO25                                               1
+#define FUNC_SDIO_CMD_SPI2_WP_PAD                                          2
+#define FUNC_SDIO_CMD_DBG_FLASH_HOLD_PAD                                   4
+
+#define PERIPHS_IO_MUX_U_GPIO26                     (REG_IO_MUX_BASE + 0x68)
+#define FUNC_SPICS_FLASH_CS_PAD                                            0
+#define FUNC_SPICS_GPIO26                                                  1
+
+#define PERIPHS_IO_MUX_U_GPIO27                     (REG_IO_MUX_BASE + 0x6c)
+#define FUNC_SPIQ_FLASH_Q_PAD                                              0
+#define FUNC_SPIQ_GPIO27                                                   1
+
+#define PERIPHS_IO_MUX_U_GPIO28                     (REG_IO_MUX_BASE + 0x70)
+#define FUNC_SPIWP_FLASH_WP_PAD                                            0
+#define FUNC_SPIWP_GPIO28                                                  1
+
+#define PERIPHS_IO_MUX_U_GPIO29                     (REG_IO_MUX_BASE + 0x74)
+#define FUNC_VDD_SPI_GPIO29_0                                              0
+#define FUNC_VDD_SPI_GPIO29                                                1
+
+#define PERIPHS_IO_MUX_U_GPIO30                     (REG_IO_MUX_BASE + 0x78)
+#define FUNC_SPIHD_FLASH_HOLD_PAD                                          0
+#define FUNC_SPIHD_GPIO30                                                  1
+
+#define PERIPHS_IO_MUX_U_GPIO31                     (REG_IO_MUX_BASE + 0x7c)
+#define FUNC_SPICLK_FLASH_CK_PAD                                           0
+#define FUNC_SPICLK_GPIO31                                                 1
+
+#define PERIPHS_IO_MUX_U_GPIO32                     (REG_IO_MUX_BASE + 0x80)
+#define FUNC_SPID_FLASH_D_PAD                                              0
+#define FUNC_SPID_GPIO32                                                   1
+
+#define PERIPHS_IO_MUX_U_USB_GPIO33                 (REG_IO_MUX_BASE + 0x84)
+#define FUNC_GPIO33_GPIO33_0                                               0
+#define FUNC_GPIO33_GPIO33                                                 1
+#define FUNC_GPIO33_LCD_DATA12_OUT_PAD                                     3
+
+#define PERIPHS_IO_MUX_U_USB_GPIO34                 (REG_IO_MUX_BASE + 0x88)
+#define FUNC_GPIO34_GPIO34_0                                               0
+#define FUNC_GPIO34_GPIO34                                                 1
+#define FUNC_GPIO34_LCD_DATA13_OUT_PAD                                     3
+
+#define PERIPHS_IO_MUX_U_GPIO35                     (REG_IO_MUX_BASE + 0x8c)
+#define FUNC_GPIO35_GPIO35_0                                               0
+#define FUNC_GPIO35_GPIO35                                                 1
+#define FUNC_GPIO35_REF_GMAC_CLK_PAD                                       2
+#define FUNC_GPIO35_LCD_DATA14_OUT_PAD                                     3
+#define FUNC_GPIO35_SD2_CDATA0_PAD                                         4
+
+// Strapping: LDO sel
+#define PERIPHS_IO_MUX_U_GPIO36                     (REG_IO_MUX_BASE + 0x90)
+#define FUNC_GPIO36_GPIO36_0                                               0
+#define FUNC_GPIO36_GPIO36                                                 1
+#define FUNC_GPIO36_GMAC_PHY_RXDV_PAD                                      2
+#define FUNC_GPIO36_LCD_DATA15_OUT_PAD                                     3
+#define FUNC_GPIO36_SD2_CDATA1_PAD                                         4
+
+// Strapping: USB2JTAG select: 1->usb2jtag 0-> pad_jtag
+#define PERIPHS_IO_MUX_U_GPIO37                     (REG_IO_MUX_BASE + 0x94)
+#define FUNC_GPIO37_GPIO37_0                                               0
+#define FUNC_GPIO37_GPIO37                                                 1
+#define FUNC_GPIO37_GMAC_PHY_TXEN_PAD                                      2
+#define FUNC_GPIO37_LCD_DATA16_OUT_PAD                                     3
+#define FUNC_GPIO37_SD2_CDATA2_PAD                                         4
+
+// Strapping: Boot Mode select 0
+#define PERIPHS_IO_MUX_U_GPIO38                     (REG_IO_MUX_BASE + 0x98)
+#define FUNC_GPIO38_GPIO38_0                                               0
+#define FUNC_GPIO38_GPIO38                                                 1
+#define FUNC_GPIO38_GMAC_PHY_RXD3_PAD                                      2
+#define FUNC_GPIO38_LCD_DATA17_OUT_PAD                                     3
+#define FUNC_GPIO38_SD2_CDATA3_PAD                                         4
+
+// Strapping: Boot Mode select 1
+#define PERIPHS_IO_MUX_U_GPIO39                     (REG_IO_MUX_BASE + 0x9c)
+#define FUNC_GPIO39_GPIO39_0                                               0
+#define FUNC_GPIO39_GPIO39                                                 1
+#define FUNC_GPIO39_GMAC_PHY_RXD2_PAD                                      2
+#define FUNC_GPIO39_LCD_DATA18_OUT_PAD                                     3
+#define FUNC_GPIO39_SD2_CCLK_PAD                                           4
+
+// Strapping: Boot Mode select 2
+#define PERIPHS_IO_MUX_U_GPIO40                     (REG_IO_MUX_BASE + 0xa0)
+#define FUNC_GPIO40_GPIO40_0                                               0
+#define FUNC_GPIO40_GPIO40                                                 1
+#define FUNC_GPIO40_GMAC_PHY_RXD1_PAD                                      2
+#define FUNC_GPIO40_LCD_PCLK_PAD                                           3
+#define FUNC_GPIO40_SD2_CCMD_PAD                                           4
+
+#define PERIPHS_IO_MUX_U_GPIO41                     (REG_IO_MUX_BASE + 0xa4)
+#define FUNC_GPIO41_GPIO41_0                                               0
+#define FUNC_GPIO41_GPIO41                                                 1
+#define FUNC_GPIO41_GMAC_PHY_RXD0_PAD                                      2
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO42                 (REG_IO_MUX_BASE + 0xa8)
+#define FUNC_GPIO42_GPIO42_0                                               0
+#define FUNC_GPIO42_GPIO42                                                 1
+#define FUNC_GPIO42_GMAC_RX_CLK_PAD                                        2
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO43                 (REG_IO_MUX_BASE + 0xac)
+#define FUNC_GPIO43_GPIO43_0                                               0
+#define FUNC_GPIO43_GPIO43                                                 1
+#define FUNC_GPIO43_GMAC_RMII_CLK_PAD                                      2
+#define FUNC_GPIO43_LCD_H_ENABLE_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO44                 (REG_IO_MUX_BASE + 0xb0)
+#define FUNC_GPIO44_GPIO44_0                                               0
+#define FUNC_GPIO44_GPIO44                                                 1
+#define FUNC_GPIO44_GMAC_PHY_TXD0_PAD                                      2
+#define FUNC_GPIO44_LCD_H_SYNC_PAD                                         3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO45                 (REG_IO_MUX_BASE + 0xb4)
+#define FUNC_GPIO45_GPIO45_0                                               0
+#define FUNC_GPIO45_GPIO45                                                 1
+#define FUNC_GPIO45_GMAC_PHY_TXD1_PAD                                      2
+#define FUNC_GPIO45_LCD_V_SYNC_PAD                                         3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO46                 (REG_IO_MUX_BASE + 0xb8)
+#define FUNC_GPIO46_GPIO46_0                                               0
+#define FUNC_GPIO46_GPIO46                                                 1
+#define FUNC_GPIO46_GMAC_PHY_TXD2_PAD                                      2
+#define FUNC_GPIO46_CAM_DATA0_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO47                 (REG_IO_MUX_BASE + 0xbc)
+#define FUNC_GPIO47_GPIO47_0                                               0
+#define FUNC_GPIO47_GPIO47                                                 1
+#define FUNC_GPIO47_GMAC_PHY_TXD3_PAD                                      2
+#define FUNC_GPIO47_CAM_DATA1_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO48                 (REG_IO_MUX_BASE + 0xc0)
+#define FUNC_GPIO48_GPIO48_0                                               0
+#define FUNC_GPIO48_GPIO48                                                 1
+#define FUNC_GPIO48_CAM_DATA2_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO49                 (REG_IO_MUX_BASE + 0xc4)
+#define FUNC_GPIO49_GPIO49_0                                               0
+#define FUNC_GPIO49_GPIO49                                                 1
+#define FUNC_GPIO49_CAM_DATA3_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO50                 (REG_IO_MUX_BASE + 0xc8)
+#define FUNC_GPIO50_GPIO50_0                                               0
+#define FUNC_GPIO50_GPIO50                                                 1
+#define FUNC_GPIO50_CAM_DATA4_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO51                 (REG_IO_MUX_BASE + 0xcc)
+#define FUNC_GPIO51_GPIO51_0                                               0
+#define FUNC_GPIO51_GPIO51                                                 1
+#define FUNC_GPIO51_CAM_DATA5_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO52                 (REG_IO_MUX_BASE + 0xd0)
+#define FUNC_GPIO52_GPIO52_0                                               0
+#define FUNC_GPIO52_GPIO52                                                 1
+#define FUNC_GPIO52_SPI2_CS_PAD                                            2
+#define FUNC_GPIO52_CAM_DATA6_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO53                 (REG_IO_MUX_BASE + 0xd4)
+#define FUNC_GPIO53_GPIO53_0                                               0
+#define FUNC_GPIO53_GPIO53                                                 1
+#define FUNC_GPIO53_SPI2_CK_PAD                                            2
+#define FUNC_GPIO53_CAM_DATA7_IN_PAD                                       3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO54                 (REG_IO_MUX_BASE + 0xd8)
+#define FUNC_MTDO_MTDO                                                     0
+#define FUNC_MTDO_GPIO54                                                   1
+#define FUNC_MTDO_SPI2_D_PAD                                               2
+#define FUNC_MTDO_CAM_PCLK_PAD                                             3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO55                 (REG_IO_MUX_BASE + 0xdc)
+#define FUNC_MTCK_MTCK                                                     0
+#define FUNC_MTCK_GPIO55                                                   1
+#define FUNC_MTCK_SPI2_Q_PAD                                               2
+#define FUNC_MTCK_CAM_XCLK_PAD                                             3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO56                 (REG_IO_MUX_BASE + 0xe0)
+#define FUNC_MTDI_MTDI                                                     0
+#define FUNC_MTDI_GPIO56                                                   1
+#define FUNC_MTDI_SPI2_HOLD_PAD                                            2
+#define FUNC_MTDI_CAM_V_SYNC_PAD                                           3
+
+#define PERIPHS_IO_MUX_U_ADC_GPIO57                 (REG_IO_MUX_BASE + 0xe4)
+#define FUNC_MTMS_MTMS                                                     0
+#define FUNC_MTMS_GPIO57                                                   1
+#define FUNC_MTMS_SPI2_WP_PAD                                              2
+#define FUNC_MTMS_CAM_H_SYNC_PAD                                           3
+
+#define PERIPHS_IO_MUX_U_GPIO58                     (REG_IO_MUX_BASE + 0xe8)
+#define FUNC_GPIO58_UART0_TXD_PAD                                          0
+#define FUNC_GPIO58_GPIO58                                                 1
+
+#define PERIPHS_IO_MUX_U_GPIO59                     (REG_IO_MUX_BASE + 0xec)
+#define FUNC_GPIO59_UART0_RXD_PAD                                          0
+#define FUNC_GPIO59_GPIO59                                                 1
+
+// Strapping: Boot Mode select 3
+#define PERIPHS_IO_MUX_U_GPIO60                     (REG_IO_MUX_BASE + 0xf0)
+#define FUNC_GPIO60_GPIO60_0                                               0
+#define FUNC_GPIO60_GPIO60                                                 1
+
+// Strapping: Boot Mode select 4
+#define PERIPHS_IO_MUX_U_GPIO61                     (REG_IO_MUX_BASE + 0xf4)
+#define FUNC_GPIO61_GPIO61_0                                               0
+#define FUNC_GPIO61_GPIO61                                                 1
+
+#define PERIPHS_IO_MUX_U_GPIO62                     (REG_IO_MUX_BASE + 0xf8)
+#define FUNC_GPIO62_GPIO62_0                                               0
+#define FUNC_GPIO62_GPIO62                                                 1
+
+
+#define IO_MUX_DATE_REG          (REG_IO_MUX_BASE + 0x1FC)
+/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2502070 ; */
+/*description: Version control register.*/
+#define IO_MUX_REG_DATE    0x0FFFFFFF
+#define IO_MUX_REG_DATE_M  ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
+#define IO_MUX_REG_DATE_V  0xFFFFFFF
+#define IO_MUX_REG_DATE_S  0
diff --git a/components/soc/esp32s31/register/soc/io_mux_struct.h b/components/soc/esp32s31/register/soc/io_mux_struct.h
new file mode 100644
index 00000000000..aeb5ff87465
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/io_mux_struct.h
@@ -0,0 +1,145 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of gpio register
+ *  IO MUX configuration register for GPIOn
+ */
+typedef union {
+    struct {
+        /** gpio_mcu_oe : R/W; bitpos: [0]; default: 0;
+         *  Configures whether or not to enable the output of GPIOn in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_mcu_oe:1;
+        /** gpio_slp_sel : R/W; bitpos: [1]; default: 0;
+         *  Configures whether or not to enter sleep mode for GPIOn.
+         *  0: Not enter
+         *  1: Enter
+         */
+        uint32_t gpio_slp_sel:1;
+        /** gpio_mcu_wpd : R/W; bitpos: [2]; default: 0;
+         *  Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_mcu_wpd:1;
+        /** gpio_mcu_wpu : R/W; bitpos: [3]; default: 0;
+         *  Configures whether or not to enable pull-up resistor of GPIOn during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_mcu_wpu:1;
+        /** gpio_mcu_ie : R/W; bitpos: [4]; default: 0;
+         *  Configures whether or not to enable the input of GPIOn during sleep mode.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_mcu_ie:1;
+        /** gpio_mcu_drv : R/W; bitpos: [6:5]; default: 0;
+         *  Configures the drive strength of GPIOn during sleep mode.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gpio_mcu_drv:2;
+        /** gpio_fun_wpd : R/W; bitpos: [7]; default: 0;
+         *  Configures whether or not to enable pull-down resistor of GPIOn.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_fun_wpd:1;
+        /** gpio_fun_wpu : R/W; bitpos: [8]; default: 0;
+         *  Configures whether or not enable pull-up resistor of GPIOn.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_fun_wpu:1;
+        /** gpio_fun_ie : R/W; bitpos: [9]; default: 0;
+         *  Configures whether or not to enable input of GPIOn.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_fun_ie:1;
+        /** gpio_fun_drv : R/W; bitpos: [11:10]; default: 2;
+         *  Configures the drive strength of GPIOn.
+         *  0: ~5 mA
+         *  1: ~10 mA
+         *  2: ~20 mA
+         *  3: ~40 mA
+         */
+        uint32_t gpio_fun_drv:2;
+        /** gpio_mcu_sel : R/W; bitpos: [14:12]; default: 1;
+         *  Configures to select IO MUX function for this signal.
+         *  0: Select Function 0
+         *  1: Select Function 1
+         *  ......
+         */
+        uint32_t gpio_mcu_sel:3;
+        /** gpio_filter_en : R/W; bitpos: [15]; default: 0;
+         *  Configures whether or not to enable filter for pin input signals.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_filter_en:1;
+        /** gpio_hys_en : R/W; bitpos: [16]; default: 0;
+         *  Configures whether or not to enable the hysteresis function of the pin when
+         *  IO_MUX_GPIOn_HYS_SEL is set to 1.
+         *  0: Disable
+         *  1: Enable
+         */
+        uint32_t gpio_hys_en:1;
+        /** gpio_hys_sel : R/W; bitpos: [17]; default: 0;
+         *  Configures to choose the signal for enabling the hysteresis function for GPIOn.
+         *  0: Choose the output enable signal of eFuse
+         *  1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN
+         */
+        uint32_t gpio_hys_sel:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} io_mux_gpio_reg_t;
+
+
+/** Group: Version Register */
+/** Type of date register
+ *  Version control register
+ */
+typedef union {
+    struct {
+        /** reg_date : R/W; bitpos: [27:0]; default: 38805616;
+         *  Version control register
+         */
+        uint32_t reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} io_mux_date_reg_t;
+
+
+typedef struct io_mux_dev_t {
+    volatile io_mux_gpio_reg_t gpio[63];
+    uint32_t reserved_0fc[64];
+    volatile io_mux_date_reg_t date;
+} io_mux_dev_t;
+
+extern io_mux_dev_t IO_MUX;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/iomux_mspi_pin_reg.h b/components/soc/esp32s31/register/soc/iomux_mspi_pin_reg.h
new file mode 100644
index 00000000000..b3486b0aa57
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/iomux_mspi_pin_reg.h
@@ -0,0 +1,721 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** IOMUX_MSPI_PIN_CLK_EN0_REG register
+ *  apb registers auto clock gating reg
+ */
+#define IOMUX_MSPI_PIN_CLK_EN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x0)
+/** IOMUX_MSPI_PIN_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  1: auto clock gating on
+ *  0: auto clock gating off
+ */
+#define IOMUX_MSPI_PIN_REG_CLK_EN    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_CLK_EN_M  (IOMUX_MSPI_PIN_REG_CLK_EN_V << IOMUX_MSPI_PIN_REG_CLK_EN_S)
+#define IOMUX_MSPI_PIN_REG_CLK_EN_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_CLK_EN_S  0
+
+/** IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x1c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram d dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram d dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram d sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram d wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram d wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram d drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram d hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_D_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_Q_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x20)
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram q dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram q dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram q sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram q wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram q wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram q drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram q hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_Q_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_WP_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x24)
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram wp dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram wp dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram wp sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram wp wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram wp wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram wp drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram wp hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_WP_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_HOLD_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x28)
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram hold dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram hold dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram hold sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram hold wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram hold wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram hold drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram hold hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_HOLD_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ4_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x2c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq4 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq4 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq4 sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq4 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq4 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram dq4 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram dq4 hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ4_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ5_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x30)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq5 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq5 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq5 sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq5 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq5 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram dq5 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram dq5 hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ5_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ6_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x34)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq6 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq6 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq6 sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq6 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq6 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram dq6 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram dq6 hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ6_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQ7_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x38)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram dq7 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram dq7 dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram dq7 sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram dq7 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram dq7 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram dq7 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram dq7 hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQ7_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_DQS_0_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x3c)
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD : R/W; bitpos: [0]; default: 0;
+ *  psram xpd dqs0
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD    (BIT(0))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_XPD_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE : R/W; bitpos: [2:1]; default: 0;
+ *  psram dqs0 phase
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE    0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_V  0x00000003U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_PHASE_S  1
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI : R/W; bitpos: [6:3]; default: 0;
+ *  psram dqs0 dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DLI_S  3
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90 : R/W; bitpos: [10:7]; default: 0;
+ *  psram dqs0 delay 90
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_90_S  7
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS : R/W; bitpos: [11]; default: 0;
+ *  psram dqs0 sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_HYS_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE : R/W; bitpos: [12]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE    (BIT(12))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_IE_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU : R/W; bitpos: [13]; default: 0;
+ *  psram dqs0 wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU    (BIT(13))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPU_S  13
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD : R/W; bitpos: [14]; default: 0;
+ *  psram dqs0 wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD    (BIT(14))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_WPD_S  14
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV : R/W; bitpos: [17:15]; default: 4;
+ *  psram dqs0 drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DRV_S  15
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270 : R/W; bitpos: [21:18]; default: 0;
+ *  psram dqs0 delay 270
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_0_DELAY_270_S  18
+/** IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD : R/W; bitpos: [22]; default: 0;
+ *  psram dqs hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD    (BIT(22))
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_DQS_HOLD_S  22
+
+/** IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_CK_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x40)
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram ck dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram ck dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram ck sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram ck wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram ck wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram ck drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram ck hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CK_HOLD_S  15
+
+/** IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+#define IOMUX_MSPI_PIN_PSRAM_CS_PIN0_REG (DR_REG_IOMUX_MSPI_PIN_BASE + 0x44)
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI : R/W; bitpos: [3:0]; default: 0;
+ *  psram cs dli
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLI_S  0
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC : R/W; bitpos: [7:4]; default: 0;
+ *  psram cs dlc
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC    0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_V  0x0000000FU
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DLC_S  4
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS : R/W; bitpos: [8]; default: 0;
+ *  psram cs sl
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS    (BIT(8))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HYS_S  8
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_IE : R/W; bitpos: [9]; default: 0;
+ *  Reserved
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE    (BIT(9))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_IE_S  9
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU : R/W; bitpos: [10]; default: 0;
+ *  psram cs wpu
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU    (BIT(10))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPU_S  10
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD : R/W; bitpos: [11]; default: 0;
+ *  psram cs wpd
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD    (BIT(11))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_WPD_S  11
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV : R/W; bitpos: [14:12]; default: 4;
+ *  psram cs drv
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV    0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_V  0x00000007U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_DRV_S  12
+/** IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD : R/W; bitpos: [15]; default: 0;
+ *  psram cs hold
+ */
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD    (BIT(15))
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_M  (IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_V << IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_S)
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_V  0x00000001U
+#define IOMUX_MSPI_PIN_REG_PSRAM_CS_HOLD_S  15
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/soc/esp32s31/register/soc/iomux_mspi_pin_struct.h b/components/soc/esp32s31/register/soc/iomux_mspi_pin_struct.h
new file mode 100644
index 00000000000..1425a3b32ea
--- /dev/null
+++ b/components/soc/esp32s31/register/soc/iomux_mspi_pin_struct.h
@@ -0,0 +1,551 @@
+/**
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: clk_en */
+/** Type of clk_en0 register
+ *  apb registers auto clock gating reg
+ */
+typedef union {
+    struct {
+        /** reg_clk_en : R/W; bitpos: [0]; default: 1;
+         *  1: auto clock gating on
+         *  0: auto clock gating off
+         */
+        uint32_t reg_clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} iomux_mspi_pin_clk_en0_reg_t;
+
+
+/** Group: psram_d_pin */
+/** Type of psram_d_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_d_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram d dli
+         */
+        uint32_t reg_psram_d_dli:4;
+        /** reg_psram_d_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram d dlc
+         */
+        uint32_t reg_psram_d_dlc:4;
+        /** reg_psram_d_hys : R/W; bitpos: [8]; default: 0;
+         *  psram d sl
+         */
+        uint32_t reg_psram_d_hys:1;
+        /** reg_psram_d_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_d_ie:1;
+        /** reg_psram_d_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram d wpu
+         */
+        uint32_t reg_psram_d_wpu:1;
+        /** reg_psram_d_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram d wpd
+         */
+        uint32_t reg_psram_d_wpd:1;
+        /** reg_psram_d_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram d drv
+         */
+        uint32_t reg_psram_d_drv:3;
+        /** reg_psram_d_hold : R/W; bitpos: [15]; default: 0;
+         *  psram d hold
+         */
+        uint32_t reg_psram_d_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_d_pin0_reg_t;
+
+
+/** Group: psram_q_pin */
+/** Type of psram_q_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_q_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram q dli
+         */
+        uint32_t reg_psram_q_dli:4;
+        /** reg_psram_q_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram q dlc
+         */
+        uint32_t reg_psram_q_dlc:4;
+        /** reg_psram_q_hys : R/W; bitpos: [8]; default: 0;
+         *  psram q sl
+         */
+        uint32_t reg_psram_q_hys:1;
+        /** reg_psram_q_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_q_ie:1;
+        /** reg_psram_q_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram q wpu
+         */
+        uint32_t reg_psram_q_wpu:1;
+        /** reg_psram_q_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram q wpd
+         */
+        uint32_t reg_psram_q_wpd:1;
+        /** reg_psram_q_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram q drv
+         */
+        uint32_t reg_psram_q_drv:3;
+        /** reg_psram_q_hold : R/W; bitpos: [15]; default: 0;
+         *  psram q hold
+         */
+        uint32_t reg_psram_q_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_q_pin0_reg_t;
+
+
+/** Group: psram_wp_pin */
+/** Type of psram_wp_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_wp_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram wp dli
+         */
+        uint32_t reg_psram_wp_dli:4;
+        /** reg_psram_wp_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram wp dlc
+         */
+        uint32_t reg_psram_wp_dlc:4;
+        /** reg_psram_wp_hys : R/W; bitpos: [8]; default: 0;
+         *  psram wp sl
+         */
+        uint32_t reg_psram_wp_hys:1;
+        /** reg_psram_wp_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_wp_ie:1;
+        /** reg_psram_wp_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram wp wpu
+         */
+        uint32_t reg_psram_wp_wpu:1;
+        /** reg_psram_wp_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram wp wpd
+         */
+        uint32_t reg_psram_wp_wpd:1;
+        /** reg_psram_wp_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram wp drv
+         */
+        uint32_t reg_psram_wp_drv:3;
+        /** reg_psram_wp_hold : R/W; bitpos: [15]; default: 0;
+         *  psram wp hold
+         */
+        uint32_t reg_psram_wp_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_wp_pin0_reg_t;
+
+
+/** Group: psram_hold_pin */
+/** Type of psram_hold_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_hold_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram hold dli
+         */
+        uint32_t reg_psram_hold_dli:4;
+        /** reg_psram_hold_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram hold dlc
+         */
+        uint32_t reg_psram_hold_dlc:4;
+        /** reg_psram_hold_hys : R/W; bitpos: [8]; default: 0;
+         *  psram hold sl
+         */
+        uint32_t reg_psram_hold_hys:1;
+        /** reg_psram_hold_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_hold_ie:1;
+        /** reg_psram_hold_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram hold wpu
+         */
+        uint32_t reg_psram_hold_wpu:1;
+        /** reg_psram_hold_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram hold wpd
+         */
+        uint32_t reg_psram_hold_wpd:1;
+        /** reg_psram_hold_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram hold drv
+         */
+        uint32_t reg_psram_hold_drv:3;
+        /** reg_psram_hold_hold : R/W; bitpos: [15]; default: 0;
+         *  psram hold hold
+         */
+        uint32_t reg_psram_hold_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_hold_pin0_reg_t;
+
+
+/** Group: psram_dq4_pin */
+/** Type of psram_dq4_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_dq4_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram dq4 dli
+         */
+        uint32_t reg_psram_dq4_dli:4;
+        /** reg_psram_dq4_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram dq4 dlc
+         */
+        uint32_t reg_psram_dq4_dlc:4;
+        /** reg_psram_dq4_hys : R/W; bitpos: [8]; default: 0;
+         *  psram dq4 sl
+         */
+        uint32_t reg_psram_dq4_hys:1;
+        /** reg_psram_dq4_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dq4_ie:1;
+        /** reg_psram_dq4_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram dq4 wpu
+         */
+        uint32_t reg_psram_dq4_wpu:1;
+        /** reg_psram_dq4_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram dq4 wpd
+         */
+        uint32_t reg_psram_dq4_wpd:1;
+        /** reg_psram_dq4_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram dq4 drv
+         */
+        uint32_t reg_psram_dq4_drv:3;
+        /** reg_psram_dq4_hold : R/W; bitpos: [15]; default: 0;
+         *  psram dq4 hold
+         */
+        uint32_t reg_psram_dq4_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dq4_pin0_reg_t;
+
+
+/** Group: psram_dq5_pin */
+/** Type of psram_dq5_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_dq5_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram dq5 dli
+         */
+        uint32_t reg_psram_dq5_dli:4;
+        /** reg_psram_dq5_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram dq5 dlc
+         */
+        uint32_t reg_psram_dq5_dlc:4;
+        /** reg_psram_dq5_hys : R/W; bitpos: [8]; default: 0;
+         *  psram dq5 sl
+         */
+        uint32_t reg_psram_dq5_hys:1;
+        /** reg_psram_dq5_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dq5_ie:1;
+        /** reg_psram_dq5_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram dq5 wpu
+         */
+        uint32_t reg_psram_dq5_wpu:1;
+        /** reg_psram_dq5_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram dq5 wpd
+         */
+        uint32_t reg_psram_dq5_wpd:1;
+        /** reg_psram_dq5_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram dq5 drv
+         */
+        uint32_t reg_psram_dq5_drv:3;
+        /** reg_psram_dq5_hold : R/W; bitpos: [15]; default: 0;
+         *  psram dq5 hold
+         */
+        uint32_t reg_psram_dq5_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dq5_pin0_reg_t;
+
+
+/** Group: psram_dq6_pin */
+/** Type of psram_dq6_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_dq6_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram dq6 dli
+         */
+        uint32_t reg_psram_dq6_dli:4;
+        /** reg_psram_dq6_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram dq6 dlc
+         */
+        uint32_t reg_psram_dq6_dlc:4;
+        /** reg_psram_dq6_hys : R/W; bitpos: [8]; default: 0;
+         *  psram dq6 sl
+         */
+        uint32_t reg_psram_dq6_hys:1;
+        /** reg_psram_dq6_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dq6_ie:1;
+        /** reg_psram_dq6_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram dq6 wpu
+         */
+        uint32_t reg_psram_dq6_wpu:1;
+        /** reg_psram_dq6_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram dq6 wpd
+         */
+        uint32_t reg_psram_dq6_wpd:1;
+        /** reg_psram_dq6_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram dq6 drv
+         */
+        uint32_t reg_psram_dq6_drv:3;
+        /** reg_psram_dq6_hold : R/W; bitpos: [15]; default: 0;
+         *  psram dq6 hold
+         */
+        uint32_t reg_psram_dq6_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dq6_pin0_reg_t;
+
+
+/** Group: psram_dq7_pin */
+/** Type of psram_dq7_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_dq7_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram dq7 dli
+         */
+        uint32_t reg_psram_dq7_dli:4;
+        /** reg_psram_dq7_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram dq7 dlc
+         */
+        uint32_t reg_psram_dq7_dlc:4;
+        /** reg_psram_dq7_hys : R/W; bitpos: [8]; default: 0;
+         *  psram dq7 sl
+         */
+        uint32_t reg_psram_dq7_hys:1;
+        /** reg_psram_dq7_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dq7_ie:1;
+        /** reg_psram_dq7_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram dq7 wpu
+         */
+        uint32_t reg_psram_dq7_wpu:1;
+        /** reg_psram_dq7_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram dq7 wpd
+         */
+        uint32_t reg_psram_dq7_wpd:1;
+        /** reg_psram_dq7_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram dq7 drv
+         */
+        uint32_t reg_psram_dq7_drv:3;
+        /** reg_psram_dq7_hold : R/W; bitpos: [15]; default: 0;
+         *  psram dq7 hold
+         */
+        uint32_t reg_psram_dq7_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dq7_pin0_reg_t;
+
+
+/** Group: psram_dqs_0_pin */
+/** Type of psram_dqs_0_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_dqs_0_xpd : R/W; bitpos: [0]; default: 0;
+         *  psram xpd dqs0
+         */
+        uint32_t reg_psram_dqs_0_xpd:1;
+        /** reg_psram_dqs_0_phase : R/W; bitpos: [2:1]; default: 0;
+         *  psram dqs0 phase
+         */
+        uint32_t reg_psram_dqs_0_phase:2;
+        /** reg_psram_dqs_0_dli : R/W; bitpos: [6:3]; default: 0;
+         *  psram dqs0 dli
+         */
+        uint32_t reg_psram_dqs_0_dli:4;
+        /** reg_psram_dqs_0_delay_90 : R/W; bitpos: [10:7]; default: 0;
+         *  psram dqs0 delay 90
+         */
+        uint32_t reg_psram_dqs_0_delay_90:4;
+        /** reg_psram_dqs_0_hys : R/W; bitpos: [11]; default: 0;
+         *  psram dqs0 sl
+         */
+        uint32_t reg_psram_dqs_0_hys:1;
+        /** reg_psram_dqs_0_ie : R/W; bitpos: [12]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_dqs_0_ie:1;
+        /** reg_psram_dqs_0_wpu : R/W; bitpos: [13]; default: 0;
+         *  psram dqs0 wpu
+         */
+        uint32_t reg_psram_dqs_0_wpu:1;
+        /** reg_psram_dqs_0_wpd : R/W; bitpos: [14]; default: 0;
+         *  psram dqs0 wpd
+         */
+        uint32_t reg_psram_dqs_0_wpd:1;
+        /** reg_psram_dqs_0_drv : R/W; bitpos: [17:15]; default: 4;
+         *  psram dqs0 drv
+         */
+        uint32_t reg_psram_dqs_0_drv:3;
+        /** reg_psram_dqs_0_delay_270 : R/W; bitpos: [21:18]; default: 0;
+         *  psram dqs0 delay 270
+         */
+        uint32_t reg_psram_dqs_0_delay_270:4;
+        /** reg_psram_dqs_hold : R/W; bitpos: [22]; default: 0;
+         *  psram dqs hold
+         */
+        uint32_t reg_psram_dqs_hold:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_dqs_0_pin0_reg_t;
+
+
+/** Group: psram_ck_pin */
+/** Type of psram_ck_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_ck_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram ck dli
+         */
+        uint32_t reg_psram_ck_dli:4;
+        /** reg_psram_ck_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram ck dlc
+         */
+        uint32_t reg_psram_ck_dlc:4;
+        /** reg_psram_ck_hys : R/W; bitpos: [8]; default: 0;
+         *  psram ck sl
+         */
+        uint32_t reg_psram_ck_hys:1;
+        /** reg_psram_ck_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_ck_ie:1;
+        /** reg_psram_ck_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram ck wpu
+         */
+        uint32_t reg_psram_ck_wpu:1;
+        /** reg_psram_ck_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram ck wpd
+         */
+        uint32_t reg_psram_ck_wpd:1;
+        /** reg_psram_ck_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram ck drv
+         */
+        uint32_t reg_psram_ck_drv:3;
+        /** reg_psram_ck_hold : R/W; bitpos: [15]; default: 0;
+         *  psram ck hold
+         */
+        uint32_t reg_psram_ck_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_ck_pin0_reg_t;
+
+
+/** Group: psram_cs_pin */
+/** Type of psram_cs_pin0 register
+ *  IOMUX_MSPI_PIN_PSRAM_D_PIN0_REG
+ */
+typedef union {
+    struct {
+        /** reg_psram_cs_dli : R/W; bitpos: [3:0]; default: 0;
+         *  psram cs dli
+         */
+        uint32_t reg_psram_cs_dli:4;
+        /** reg_psram_cs_dlc : R/W; bitpos: [7:4]; default: 0;
+         *  psram cs dlc
+         */
+        uint32_t reg_psram_cs_dlc:4;
+        /** reg_psram_cs_hys : R/W; bitpos: [8]; default: 0;
+         *  psram cs sl
+         */
+        uint32_t reg_psram_cs_hys:1;
+        /** reg_psram_cs_ie : R/W; bitpos: [9]; default: 0;
+         *  Reserved
+         */
+        uint32_t reg_psram_cs_ie:1;
+        /** reg_psram_cs_wpu : R/W; bitpos: [10]; default: 0;
+         *  psram cs wpu
+         */
+        uint32_t reg_psram_cs_wpu:1;
+        /** reg_psram_cs_wpd : R/W; bitpos: [11]; default: 0;
+         *  psram cs wpd
+         */
+        uint32_t reg_psram_cs_wpd:1;
+        /** reg_psram_cs_drv : R/W; bitpos: [14:12]; default: 4;
+         *  psram cs drv
+         */
+        uint32_t reg_psram_cs_drv:3;
+        /** reg_psram_cs_hold : R/W; bitpos: [15]; default: 0;
+         *  psram cs hold
+         */
+        uint32_t reg_psram_cs_hold:1;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} iomux_mspi_pin_psram_cs_pin0_reg_t;
+
+
+typedef struct {
+    volatile iomux_mspi_pin_clk_en0_reg_t clk_en0;
+    uint32_t reserved_004[6];
+    volatile iomux_mspi_pin_psram_d_pin0_reg_t psram_d_pin0;
+    volatile iomux_mspi_pin_psram_q_pin0_reg_t psram_q_pin0;
+    volatile iomux_mspi_pin_psram_wp_pin0_reg_t psram_wp_pin0;
+    volatile iomux_mspi_pin_psram_hold_pin0_reg_t psram_hold_pin0;
+    volatile iomux_mspi_pin_psram_dq4_pin0_reg_t psram_dq4_pin0;
+    volatile iomux_mspi_pin_psram_dq5_pin0_reg_t psram_dq5_pin0;
+    volatile iomux_mspi_pin_psram_dq6_pin0_reg_t psram_dq6_pin0;
+    volatile iomux_mspi_pin_psram_dq7_pin0_reg_t psram_dq7_pin0;
+    volatile iomux_mspi_pin_psram_dqs_0_pin0_reg_t psram_dqs_0_pin0;
+    volatile iomux_mspi_pin_psram_ck_pin0_reg_t psram_ck_pin0;
+    volatile iomux_mspi_pin_psram_cs_pin0_reg_t psram_cs_pin0;
+} iomux_mspi_pin_dev_t;
+
+extern iomux_mspi_pin_dev_t MSPI_IOMUX;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(iomux_mspi_pin_dev_t) == 0x48, "Invalid size of iomux_mspi_pin_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif