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update(pmu_param): update mdoem icg func clk

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Due to c-channel design, ETM and BUS must be set to 1
This commit is contained in:
Si Bei Bei
2026-06-18 17:14:05 +08:00
parent acf119e26b
commit 898dfb8508
2 changed files with 6 additions and 4 deletions
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components/esp_hw_support/port/esp32s31/pmu_param.c
+5 -4
View File
@@ -140,10 +140,11 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod
}
#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \
.icg_func.clock[0] = 0xffffffff, \
.icg_func.clock[1] = 0xffffffff, \
.icg_apb.clock[0] = 0xffffffff, \
.icg_apb.clock[1] = 0xffffffff, \
.icg_func.clock[0] = 0, \
.icg_func.clock[1] = BIT(PMU_ICG_FUNC_ENA_ETM - 32) \
| BIT(PMU_ICG_FUNC_ENA_BUS - 32), \
.icg_apb.clock[0] = 0, \
.icg_apb.clock[1] = 0, \
.icg_modem.code = PMU_HP_ICG_MODEM_CODE_MODEM, \
.sysclk = { \
.dig_sysclk_nodiv = 0, \
components/esp_hw_support/port/esp32s31/pmu_sleep.c
+1
View File
@@ -331,6 +331,7 @@ static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_confi
pmu_hal_hp_set_control_ready_wait_cycle(ctx->hal, param->hp_sys.isolate_wait_cycle, param->hp_sys.reset_wait_cycle);
pmu_hal_lp_set_control_ready_wait_cycle(ctx->hal, param->lp_sys.isolate_wait_cycle, param->lp_sys.reset_wait_cycle);
pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle);
pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
}