From 898dfb85086a1625b4bee0ba82ebc1f10653b727 Mon Sep 17 00:00:00 2001 From: Si Bei Bei Date: Thu, 18 Jun 2026 17:14:05 +0800 Subject: [PATCH] update(pmu_param): update mdoem icg func clk Due to c-channel design, ETM and BUS must be set to 1 --- components/esp_hw_support/port/esp32s31/pmu_param.c | 9 +++++---- components/esp_hw_support/port/esp32s31/pmu_sleep.c | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/components/esp_hw_support/port/esp32s31/pmu_param.c b/components/esp_hw_support/port/esp32s31/pmu_param.c index 66ef22d2dde..fecd96a0642 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_param.c +++ b/components/esp_hw_support/port/esp32s31/pmu_param.c @@ -140,10 +140,11 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod } #define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \ - .icg_func.clock[0] = 0xffffffff, \ - .icg_func.clock[1] = 0xffffffff, \ - .icg_apb.clock[0] = 0xffffffff, \ - .icg_apb.clock[1] = 0xffffffff, \ + .icg_func.clock[0] = 0, \ + .icg_func.clock[1] = BIT(PMU_ICG_FUNC_ENA_ETM - 32) \ + | BIT(PMU_ICG_FUNC_ENA_BUS - 32), \ + .icg_apb.clock[0] = 0, \ + .icg_apb.clock[1] = 0, \ .icg_modem.code = PMU_HP_ICG_MODEM_CODE_MODEM, \ .sysclk = { \ .dig_sysclk_nodiv = 0, \ diff --git a/components/esp_hw_support/port/esp32s31/pmu_sleep.c b/components/esp_hw_support/port/esp32s31/pmu_sleep.c index 3ef5847737d..84cc9511f9d 100644 --- a/components/esp_hw_support/port/esp32s31/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32s31/pmu_sleep.c @@ -331,6 +331,7 @@ static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_confi pmu_hal_hp_set_control_ready_wait_cycle(ctx->hal, param->hp_sys.isolate_wait_cycle, param->hp_sys.reset_wait_cycle); pmu_hal_lp_set_control_ready_wait_cycle(ctx->hal, param->lp_sys.isolate_wait_cycle, param->lp_sys.reset_wait_cycle); + pmu_ll_set_modem_wait_target_cycle(ctx->hal->dev, param->hp_sys.modem_wakeup_wait_cycle); pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle); pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle); }