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change(esp_libc): use C5 ECO4 ROM newlib functions

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Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
Marius Vikhammer
2026-07-02 10:43:22 +08:00
parent e24f64d20d
commit 7b89184536
3 changed files with 5 additions and 1 deletions
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3
components/esp_hw_support/port/esp32c5/Kconfig.hw_support
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@@ -13,12 +13,15 @@ choice ESP32C5_REV_MIN
bool "Rev v1.0 (ECO2)"
config ESP32C5_REV_MIN_102
bool "Rev v1.2"
config ESP32C5_REV_MIN_103
bool "Rev v1.3"
endchoice
config ESP32C5_REV_MIN_FULL
int
default 100 if ESP32C5_REV_MIN_100
default 102 if ESP32C5_REV_MIN_102
default 103 if ESP32C5_REV_MIN_103
config ESP_REV_MIN_FULL
int

1
components/esp_libc/Kconfig
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@@ -177,6 +177,7 @@ menu "LibC"
bool "Use performance-optimized memXXX/strXXX functions on misaligned memory access"
default y
depends on ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
depends on !(IDF_TARGET_ESP32C5 && ESP32C5_REV_MIN_FULL >= 103)
help
Enables performance-optimized implementations of memory and string functions
when handling misaligned memory.

2
components/esp_rom/esp32c5/esp_rom_caps.h
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@@ -34,7 +34,7 @@
#define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage.
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions before ECO4 are not optimized well for misaligned memory access.
#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
#define ESP_ROM_ECDSA_VERIFY_PATCH (1) // ROM ets_ecdsa_verify API requires a software patch