feat(soc): Add RISC-V trace ecause width and packet format caps

Co-authored-by: Cursor <cursoragent@cursor.com>

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -1359,6 +1359,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 100
+
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 5

components/soc/esp32c6/include/soc/soc_caps.h

@@ -551,4 +551,6 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (100) /*!< Processor Trace v1.0 */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (5) /*!< Bits in the exception cause field (ecause_width_p) */