From 5b4a90da6ee422a949e685bd7c55d94274fd4487 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 2 Sep 2026 23:10:57 +0200 Subject: [PATCH] feat(soc): Add RISC-V trace ecause width and packet format caps Co-authored-by: Cursor --- components/soc/esp32c5/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32c5/include/soc/soc_caps.h | 2 ++ components/soc/esp32c6/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32c6/include/soc/soc_caps.h | 2 ++ components/soc/esp32c61/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32c61/include/soc/soc_caps.h | 2 ++ components/soc/esp32h2/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32h2/include/soc/soc_caps.h | 2 ++ components/soc/esp32h21/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32h21/include/soc/soc_caps.h | 2 ++ components/soc/esp32h4/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32h4/include/soc/soc_caps.h | 2 ++ components/soc/esp32p4/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32p4/include/soc/soc_caps.h | 2 ++ components/soc/esp32s31/include/soc/Kconfig.soc_caps.in | 8 ++++++++ components/soc/esp32s31/include/soc/soc_caps.h | 2 ++ 16 files changed, 80 insertions(+) diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 9023a83634e..ccc1c49be37 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -1623,6 +1623,10 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 200 + config SOC_RISCV_TRACE_HAS_CONFIG_REG bool default y @@ -1638,3 +1642,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 + +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 6 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 3d481cb6f68..34025b7a940 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -647,7 +647,9 @@ #define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */ /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */ #define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */ #define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */ #define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */ diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 35d06122bfc..a106f9d438d 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1359,6 +1359,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 100 + config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 + +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 5 diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index dd5cf8b57f6..30d70887f4e 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -551,4 +551,6 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */ diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index 231d9b9a124..4c5cf3f4497 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -1243,6 +1243,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 200 + config SOC_RISCV_TRACE_HAS_CONFIG_REG bool default y @@ -1258,3 +1262,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 + +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 6 diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index a2c9695607d..1654fbe3b0e 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -501,10 +501,12 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */ #define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */ #define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */ #define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */ /*------------------------------------- No Reset CAPS -------------------------------------*/ // \#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) //TODO: [ESP32C61] IDF-9254 diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 5e13a443cf5..d8b2773abdc 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -1255,6 +1255,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 100 + config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 + +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 5 diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index b165ab36a77..0e94c9b29dd 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -532,4 +532,6 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */ diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in index b798b9856d5..daf24706cb2 100644 --- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in @@ -1155,6 +1155,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 100 + config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 + +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 5 diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h index 9234e0f5267..38deaf28e8e 100644 --- a/components/soc/esp32h21/include/soc/soc_caps.h +++ b/components/soc/esp32h21/include/soc/soc_caps.h @@ -500,4 +500,6 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */ diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in index 290a4a22de6..9639c15154f 100644 --- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in @@ -1391,6 +1391,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 200 + config SOC_RISCV_TRACE_HAS_CONFIG_REG bool default y @@ -1407,6 +1411,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 6 + config SOC_ASRC_SUPPORTED bool default y diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h index 94aa79bef27..eeace47b370 100644 --- a/components/soc/esp32h4/include/soc/soc_caps.h +++ b/components/soc/esp32h4/include/soc/soc_caps.h @@ -571,10 +571,12 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */ #define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */ #define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */ #define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */ /*---------------------------------- ASRC CAPS ----------------------------------*/ #define SOC_ASRC_SUPPORTED (1) diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 6a226079256..01e9faac556 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1939,6 +1939,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 200 + config SOC_RISCV_TRACE_HAS_CONFIG_REG bool default y @@ -1955,6 +1959,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH int default 1 +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 6 + config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 9bd4a3b45c8..0ec9e17a6b2 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -742,8 +742,10 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */ #define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */ #define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */ #define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */ #define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */ #define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */ diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in index ed624043fee..a87080dc4ab 100644 --- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in @@ -1871,6 +1871,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS bool default y +config SOC_RISCV_TRACE_PACKET_FORMAT_VER + int + default 200 + config SOC_RISCV_TRACE_HAS_CONFIG_REG bool default y @@ -1887,6 +1891,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH int default 2 +config SOC_RISCV_TRACE_ECAUSE_WIDTH + int + default 6 + config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM bool default y diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h index 1c095b038ef..bd4a17dfb98 100644 --- a/components/soc/esp32s31/include/soc/soc_caps.h +++ b/components/soc/esp32s31/include/soc/soc_caps.h @@ -697,8 +697,10 @@ #define SOC_DEBUG_HAVE_OCD_STUB_BINS (1) /*-------------------------- RISC-V TRACE CAPS ------------------------------*/ +#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */ #define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */ #define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */ #define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */ #define SOC_RISCV_TRACE_PRIV_WIDTH (2U) /*!< Bits in the privilege field (privilege_width_p) */ +#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */ #define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */