mirror of
https://github.com/espressif/esp-idf.git
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Merge branch 'feat/update_pmu_pau_reg_description_v6.1' into 'release/v6.1'
feat(soc): update esp32c61 PMU & PAU reg header descriptions (v6.1) See merge request espressif/esp-idf!50431
This commit is contained in:
Jiang Jiang Jian
@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -11,53 +11,68 @@ extern "C" {
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#endif
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/** PAU_REGDMA_CONF_REG register
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* Peri backup control register
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* Peripherals backup configuration/control register
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*/
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#define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0)
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/** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
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* backup error type
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* Represents the backup error type.
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* 0: Received software triggered interrupt clear signal
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* 1: Peripheral AHB bus timeout
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* 2: Memory AHB bus timeout
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* 3: Address link list wait timer timeout
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* 4: Address mapping error
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*/
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#define PAU_FLOW_ERR 0x00000007U
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#define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S)
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#define PAU_FLOW_ERR_V 0x00000007U
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#define PAU_FLOW_ERR_S 0
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/** PAU_START : WT; bitpos: [3]; default: 0;
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* backup start signal
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* Write 1 to initiate the backup start signal.
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*/
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#define PAU_START (BIT(3))
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#define PAU_START_M (PAU_START_V << PAU_START_S)
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#define PAU_START_V 0x00000001U
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#define PAU_START_S 3
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/** PAU_TO_MEM : R/W; bitpos: [4]; default: 0;
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* backup direction(reg to mem / mem to reg)
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* Configures the backup direction.
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* 0: register to memory
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* 1: memory to register
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*/
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#define PAU_TO_MEM (BIT(4))
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#define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S)
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#define PAU_TO_MEM_V 0x00000001U
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#define PAU_TO_MEM_S 4
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/** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0;
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* Link select
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* Configures to select the link.
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* 0: PAU_REGDMA_LINK_0_ADDR_REG
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* 1: PAU_REGDMA_LINK_1_ADDR_REG
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* 2: PAU_REGDMA_LINK_2_ADDR_REG
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* 3: PAU_REGDMA_LINK_3_ADDR_REG
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*/
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#define PAU_LINK_SEL 0x00000003U
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#define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S)
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#define PAU_LINK_SEL_V 0x00000003U
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#define PAU_LINK_SEL_S 5
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/** PAU_START_MAC : WT; bitpos: [7]; default: 0;
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* mac sw backup start signal
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* Write 1 to initiate the MAC software backup start signal.
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*/
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#define PAU_START_MAC (BIT(7))
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#define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S)
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#define PAU_START_MAC_V 0x00000001U
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#define PAU_START_MAC_S 7
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/** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0;
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* mac sw backup direction(reg to mem / mem to reg)
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* Configures the MAC software backup direction.
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* 0: register to memory
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* 1: memory to register
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*/
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#define PAU_TO_MEM_MAC (BIT(8))
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#define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S)
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#define PAU_TO_MEM_MAC_V 0x00000001U
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#define PAU_TO_MEM_MAC_S 8
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/** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0;
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* mac hw/sw select
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* Configures the MAC hardware/software selection.
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* 0: select the hardware path
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* 1: select the software path
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*/
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#define PAU_SEL_MAC (BIT(9))
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#define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S)
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@@ -69,7 +84,9 @@ extern "C" {
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*/
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#define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4)
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/** PAU_CLK_EN : R/W; bitpos: [0]; default: 0;
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* clock enable
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* Configures whether or not to enable clock for the PAU module.
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* 0: Disable
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* 1: Enable
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*/
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#define PAU_CLK_EN (BIT(0))
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#define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S)
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@@ -77,32 +94,32 @@ extern "C" {
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#define PAU_CLK_EN_S 0
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/** PAU_REGDMA_ETM_CTRL_REG register
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* ETM start ctrl reg
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* ETM start configuration/control register
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*/
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#define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8)
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/** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0;
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* etm_start_0 reg
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* Write 1 to start ETM operation 0.
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*/
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#define PAU_ETM_START_0 (BIT(0))
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#define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S)
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#define PAU_ETM_START_0_V 0x00000001U
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#define PAU_ETM_START_0_S 0
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/** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0;
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* etm_start_1 reg
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* Write 1 to start ETM operation 1.
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*/
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#define PAU_ETM_START_1 (BIT(1))
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#define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S)
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#define PAU_ETM_START_1_V 0x00000001U
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#define PAU_ETM_START_1_S 1
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/** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0;
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* etm_start_2 reg
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* Write 1 to start ETM operation 2.
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*/
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#define PAU_ETM_START_2 (BIT(2))
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#define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S)
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#define PAU_ETM_START_2_V 0x00000001U
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#define PAU_ETM_START_2_S 2
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/** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0;
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* etm_start_3 reg
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* Write 1 to start ETM operation 3.
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*/
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#define PAU_ETM_START_3 (BIT(3))
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#define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S)
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@@ -110,11 +127,11 @@ extern "C" {
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#define PAU_ETM_START_3_S 3
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/** PAU_REGDMA_LINK_0_ADDR_REG register
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* link_0_addr
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* Link address configuration register 0
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*/
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#define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc)
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/** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0;
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* link_0_addr reg
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* Represents the address for link 0.
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*/
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#define PAU_LINK_ADDR_0 0xFFFFFFFFU
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#define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S)
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@@ -122,11 +139,11 @@ extern "C" {
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#define PAU_LINK_ADDR_0_S 0
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/** PAU_REGDMA_LINK_1_ADDR_REG register
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* Link_1_addr
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* Link address configuration register 1
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*/
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#define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10)
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/** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0;
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* Link_1_addr reg
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* Represents the address for link 1.
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*/
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#define PAU_LINK_ADDR_1 0xFFFFFFFFU
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#define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S)
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@@ -134,11 +151,11 @@ extern "C" {
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#define PAU_LINK_ADDR_1_S 0
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/** PAU_REGDMA_LINK_2_ADDR_REG register
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* Link_2_addr
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* Link address configuration register 2
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*/
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#define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14)
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/** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0;
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* Link_2_addr reg
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* Represents the address for link 2.
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*/
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#define PAU_LINK_ADDR_2 0xFFFFFFFFU
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#define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S)
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@@ -146,11 +163,11 @@ extern "C" {
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#define PAU_LINK_ADDR_2_S 0
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/** PAU_REGDMA_LINK_3_ADDR_REG register
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* Link_3_addr
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* Link address configuration register 3
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*/
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#define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18)
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/** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0;
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* Link_3_addr reg
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* Represents the address for link 3.
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*/
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#define PAU_LINK_ADDR_3 0xFFFFFFFFU
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#define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S)
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@@ -158,11 +175,11 @@ extern "C" {
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#define PAU_LINK_ADDR_3_S 0
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/** PAU_REGDMA_LINK_MAC_ADDR_REG register
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* Link_mac_addr
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* Link MAC address register
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*/
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#define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c)
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/** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0;
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* Link_mac_addr reg
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* Represents the MAC address for the link.
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*/
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#define PAU_LINK_ADDR_MAC 0xFFFFFFFFU
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#define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S)
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@@ -170,11 +187,11 @@ extern "C" {
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#define PAU_LINK_ADDR_MAC_S 0
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/** PAU_REGDMA_CURRENT_LINK_ADDR_REG register
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* current link addr
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* Current link address register
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*/
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#define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20)
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/** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0;
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* current link addr reg
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* Represents the current link address.
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*/
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#define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU
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#define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S)
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@@ -182,11 +199,11 @@ extern "C" {
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#define PAU_CURRENT_LINK_ADDR_S 0
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/** PAU_REGDMA_BACKUP_ADDR_REG register
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* Backup addr
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* Backup address register
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*/
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#define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24)
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/** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0;
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* backup addr reg
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* Represents the backup address.
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*/
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#define PAU_BACKUP_ADDR 0xFFFFFFFFU
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#define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S)
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@@ -194,11 +211,11 @@ extern "C" {
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#define PAU_BACKUP_ADDR_S 0
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/** PAU_REGDMA_MEM_ADDR_REG register
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* mem addr
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* Memory address configuration register
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*/
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#define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28)
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/** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0;
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* mem addr reg
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* Represents the memory address.
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*/
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#define PAU_MEM_ADDR 0xFFFFFFFFU
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#define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S)
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@@ -206,32 +223,32 @@ extern "C" {
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#define PAU_MEM_ADDR_S 0
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/** PAU_REGDMA_BKP_CONF_REG register
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* backup config
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* Link configuration register
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*/
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#define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c)
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/** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32;
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* Link read_interval
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* Configures the read interval for the link.
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*/
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#define PAU_READ_INTERVAL 0x0000007FU
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#define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S)
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#define PAU_READ_INTERVAL_V 0x0000007FU
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#define PAU_READ_INTERVAL_S 0
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/** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50;
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* link wait timeout threshold
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* Configures the link wait timeout threshold.
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*/
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#define PAU_LINK_TOUT_THRES 0x000003FFU
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#define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S)
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#define PAU_LINK_TOUT_THRES_V 0x000003FFU
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#define PAU_LINK_TOUT_THRES_S 7
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/** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8;
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* burst limit
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* Configures the burst limit.
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*/
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#define PAU_BURST_LIMIT 0x0000001FU
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#define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S)
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#define PAU_BURST_LIMIT_V 0x0000001FU
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#define PAU_BURST_LIMIT_S 17
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/** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500;
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* Backup timeout threshold
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* Configures the backup timeout threshold.
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*/
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#define PAU_BACKUP_TOUT_THRES 0x000003FFU
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#define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S)
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@@ -239,18 +256,18 @@ extern "C" {
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#define PAU_BACKUP_TOUT_THRES_S 22
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/** PAU_INT_ENA_REG register
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* Read only register for error and done
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* Interrupt register
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*/
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#define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30)
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/** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
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* backup done flag
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* Write 1 to enable backup done interrupt.
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*/
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#define PAU_DONE_INT_ENA (BIT(0))
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#define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S)
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#define PAU_DONE_INT_ENA_V 0x00000001U
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#define PAU_DONE_INT_ENA_S 0
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/** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0;
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* error flag
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* Write 1 to enable error interrupt.
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*/
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#define PAU_ERROR_INT_ENA (BIT(1))
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#define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S)
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@@ -258,18 +275,18 @@ extern "C" {
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#define PAU_ERROR_INT_ENA_S 1
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/** PAU_INT_RAW_REG register
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* Read only register for error and done
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* Interrupt register
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*/
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#define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34)
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/** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* backup done flag
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* The raw interrupt status for backup completion.
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*/
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#define PAU_DONE_INT_RAW (BIT(0))
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#define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S)
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#define PAU_DONE_INT_RAW_V 0x00000001U
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#define PAU_DONE_INT_RAW_S 0
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/** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
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* error flag
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* The raw interrupt status for errors.
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*/
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#define PAU_ERROR_INT_RAW (BIT(1))
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#define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S)
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@@ -277,18 +294,18 @@ extern "C" {
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#define PAU_ERROR_INT_RAW_S 1
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/** PAU_INT_CLR_REG register
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* Read only register for error and done
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* Interrupt register
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*/
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#define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38)
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/** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
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* backup done flag
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* Write 1 to clear the backup done interrupt.
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*/
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#define PAU_DONE_INT_CLR (BIT(0))
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#define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S)
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#define PAU_DONE_INT_CLR_V 0x00000001U
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#define PAU_DONE_INT_CLR_S 0
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/** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0;
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* error flag
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* Write 1 to clear the error interrupt.
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*/
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#define PAU_ERROR_INT_CLR (BIT(1))
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#define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S)
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@@ -296,18 +313,18 @@ extern "C" {
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#define PAU_ERROR_INT_CLR_S 1
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/** PAU_INT_ST_REG register
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* Read only register for error and done
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* Interrupt register
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*/
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#define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c)
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/** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0;
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* backup done flag
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* Represents the backup completion status.
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*/
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#define PAU_DONE_INT_ST (BIT(0))
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#define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S)
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#define PAU_DONE_INT_ST_V 0x00000001U
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#define PAU_DONE_INT_ST_S 0
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/** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0;
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* error flag
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* Represents the error status.
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*/
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#define PAU_ERROR_INT_ST (BIT(1))
|
||||
#define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S)
|
||||
@@ -315,11 +332,11 @@ extern "C" {
|
||||
#define PAU_ERROR_INT_ST_S 1
|
||||
|
||||
/** PAU_DATE_REG register
|
||||
* Date register.
|
||||
* Version control register
|
||||
*/
|
||||
#define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc)
|
||||
/** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608;
|
||||
* REGDMA date information/ REGDMA version information.
|
||||
* Version control register.
|
||||
*/
|
||||
#define PAU_DATE 0x0FFFFFFFU
|
||||
#define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -12,36 +12,51 @@ extern "C" {
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of regdma_conf register
|
||||
* Peri backup control register
|
||||
* Peripherals backup configuration/control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** flow_err : RO; bitpos: [2:0]; default: 0;
|
||||
* backup error type
|
||||
* Represents the backup error type.
|
||||
* 0: Received software triggered interrupt clear signal
|
||||
* 1: Peripheral AHB bus timeout
|
||||
* 2: Memory AHB bus timeout
|
||||
* 3: Address link list wait timer timeout
|
||||
* 4: Address mapping error
|
||||
*/
|
||||
uint32_t flow_err:3;
|
||||
/** start : WT; bitpos: [3]; default: 0;
|
||||
* backup start signal
|
||||
* Write 1 to initiate the backup start signal.
|
||||
*/
|
||||
uint32_t start:1;
|
||||
/** to_mem : R/W; bitpos: [4]; default: 0;
|
||||
* backup direction(reg to mem / mem to reg)
|
||||
* Configures the backup direction.
|
||||
* 0: register to memory
|
||||
* 1: memory to register
|
||||
*/
|
||||
uint32_t to_mem:1;
|
||||
/** link_sel : R/W; bitpos: [6:5]; default: 0;
|
||||
* Link select
|
||||
* Configures to select the link.
|
||||
* 0: PAU_REGDMA_LINK_0_ADDR_REG
|
||||
* 1: PAU_REGDMA_LINK_1_ADDR_REG
|
||||
* 2: PAU_REGDMA_LINK_2_ADDR_REG
|
||||
* 3: PAU_REGDMA_LINK_3_ADDR_REG
|
||||
*/
|
||||
uint32_t link_sel:2;
|
||||
/** start_mac : WT; bitpos: [7]; default: 0;
|
||||
* mac sw backup start signal
|
||||
* Write 1 to initiate the MAC software backup start signal.
|
||||
*/
|
||||
uint32_t start_mac:1;
|
||||
/** to_mem_mac : R/W; bitpos: [8]; default: 0;
|
||||
* mac sw backup direction(reg to mem / mem to reg)
|
||||
* Configures the MAC software backup direction.
|
||||
* 0: register to memory
|
||||
* 1: memory to register
|
||||
*/
|
||||
uint32_t to_mem_mac:1;
|
||||
/** sel_mac : R/W; bitpos: [9]; default: 0;
|
||||
* mac hw/sw select
|
||||
* Configures the MAC hardware/software selection.
|
||||
* 0: select the hardware path
|
||||
* 1: select the software path
|
||||
*/
|
||||
uint32_t sel_mac:1;
|
||||
uint32_t reserved_10:22;
|
||||
@@ -55,7 +70,9 @@ typedef union {
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* clock enable
|
||||
* Configures whether or not to enable clock for the PAU module.
|
||||
* 0: Disable
|
||||
* 1: Enable
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
@@ -64,24 +81,24 @@ typedef union {
|
||||
} pau_regdma_clk_conf_reg_t;
|
||||
|
||||
/** Type of regdma_etm_ctrl register
|
||||
* ETM start ctrl reg
|
||||
* ETM start configuration/control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_start_0 : WT; bitpos: [0]; default: 0;
|
||||
* etm_start_0 reg
|
||||
* Write 1 to start ETM operation 0.
|
||||
*/
|
||||
uint32_t etm_start_0:1;
|
||||
/** etm_start_1 : WT; bitpos: [1]; default: 0;
|
||||
* etm_start_1 reg
|
||||
* Write 1 to start ETM operation 1.
|
||||
*/
|
||||
uint32_t etm_start_1:1;
|
||||
/** etm_start_2 : WT; bitpos: [2]; default: 0;
|
||||
* etm_start_2 reg
|
||||
* Write 1 to start ETM operation 2.
|
||||
*/
|
||||
uint32_t etm_start_2:1;
|
||||
/** etm_start_3 : WT; bitpos: [3]; default: 0;
|
||||
* etm_start_3 reg
|
||||
* Write 1 to start ETM operation 3.
|
||||
*/
|
||||
uint32_t etm_start_3:1;
|
||||
uint32_t reserved_4:28;
|
||||
@@ -90,12 +107,12 @@ typedef union {
|
||||
} pau_regdma_etm_ctrl_reg_t;
|
||||
|
||||
/** Type of regdma_link_0_addr register
|
||||
* link_0_addr
|
||||
* Link address configuration register 0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** link_addr_0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* link_0_addr reg
|
||||
* Represents the address for link 0.
|
||||
*/
|
||||
uint32_t link_addr_0:32;
|
||||
};
|
||||
@@ -103,12 +120,12 @@ typedef union {
|
||||
} pau_regdma_link_0_addr_reg_t;
|
||||
|
||||
/** Type of regdma_link_1_addr register
|
||||
* Link_1_addr
|
||||
* Link address configuration register 1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** link_addr_1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Link_1_addr reg
|
||||
* Represents the address for link 1.
|
||||
*/
|
||||
uint32_t link_addr_1:32;
|
||||
};
|
||||
@@ -116,12 +133,12 @@ typedef union {
|
||||
} pau_regdma_link_1_addr_reg_t;
|
||||
|
||||
/** Type of regdma_link_2_addr register
|
||||
* Link_2_addr
|
||||
* Link address configuration register 2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** link_addr_2 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Link_2_addr reg
|
||||
* Represents the address for link 2.
|
||||
*/
|
||||
uint32_t link_addr_2:32;
|
||||
};
|
||||
@@ -129,12 +146,12 @@ typedef union {
|
||||
} pau_regdma_link_2_addr_reg_t;
|
||||
|
||||
/** Type of regdma_link_3_addr register
|
||||
* Link_3_addr
|
||||
* Link address configuration register 3
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** link_addr_3 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Link_3_addr reg
|
||||
* Represents the address for link 3.
|
||||
*/
|
||||
uint32_t link_addr_3:32;
|
||||
};
|
||||
@@ -142,12 +159,12 @@ typedef union {
|
||||
} pau_regdma_link_3_addr_reg_t;
|
||||
|
||||
/** Type of regdma_link_mac_addr register
|
||||
* Link_mac_addr
|
||||
* Link MAC address register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** link_addr_mac : R/W; bitpos: [31:0]; default: 0;
|
||||
* Link_mac_addr reg
|
||||
* Represents the MAC address for the link.
|
||||
*/
|
||||
uint32_t link_addr_mac:32;
|
||||
};
|
||||
@@ -155,12 +172,12 @@ typedef union {
|
||||
} pau_regdma_link_mac_addr_reg_t;
|
||||
|
||||
/** Type of regdma_current_link_addr register
|
||||
* current link addr
|
||||
* Current link address register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** current_link_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* current link addr reg
|
||||
* Represents the current link address.
|
||||
*/
|
||||
uint32_t current_link_addr:32;
|
||||
};
|
||||
@@ -168,12 +185,12 @@ typedef union {
|
||||
} pau_regdma_current_link_addr_reg_t;
|
||||
|
||||
/** Type of regdma_backup_addr register
|
||||
* Backup addr
|
||||
* Backup address register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** backup_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* backup addr reg
|
||||
* Represents the backup address.
|
||||
*/
|
||||
uint32_t backup_addr:32;
|
||||
};
|
||||
@@ -181,12 +198,12 @@ typedef union {
|
||||
} pau_regdma_backup_addr_reg_t;
|
||||
|
||||
/** Type of regdma_mem_addr register
|
||||
* mem addr
|
||||
* Memory address configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mem_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* mem addr reg
|
||||
* Represents the memory address.
|
||||
*/
|
||||
uint32_t mem_addr:32;
|
||||
};
|
||||
@@ -194,24 +211,24 @@ typedef union {
|
||||
} pau_regdma_mem_addr_reg_t;
|
||||
|
||||
/** Type of regdma_bkp_conf register
|
||||
* backup config
|
||||
* Link configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** read_interval : R/W; bitpos: [6:0]; default: 32;
|
||||
* Link read_interval
|
||||
* Configures the read interval for the link.
|
||||
*/
|
||||
uint32_t read_interval:7;
|
||||
/** link_tout_thres : R/W; bitpos: [16:7]; default: 50;
|
||||
* link wait timeout threshold
|
||||
* Configures the link wait timeout threshold.
|
||||
*/
|
||||
uint32_t link_tout_thres:10;
|
||||
/** burst_limit : R/W; bitpos: [21:17]; default: 8;
|
||||
* burst limit
|
||||
* Configures the burst limit.
|
||||
*/
|
||||
uint32_t burst_limit:5;
|
||||
/** backup_tout_thres : R/W; bitpos: [31:22]; default: 500;
|
||||
* Backup timeout threshold
|
||||
* Configures the backup timeout threshold.
|
||||
*/
|
||||
uint32_t backup_tout_thres:10;
|
||||
};
|
||||
@@ -219,16 +236,16 @@ typedef union {
|
||||
} pau_regdma_bkp_conf_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Read only register for error and done
|
||||
* Interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** done_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* backup done flag
|
||||
* Write 1 to enable backup done interrupt.
|
||||
*/
|
||||
uint32_t done_int_ena:1;
|
||||
/** error_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* error flag
|
||||
* Write 1 to enable error interrupt.
|
||||
*/
|
||||
uint32_t error_int_ena:1;
|
||||
uint32_t reserved_2:30;
|
||||
@@ -237,16 +254,16 @@ typedef union {
|
||||
} pau_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* Read only register for error and done
|
||||
* Interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* backup done flag
|
||||
* The raw interrupt status for backup completion.
|
||||
*/
|
||||
uint32_t done_int_raw:1;
|
||||
/** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* error flag
|
||||
* The raw interrupt status for errors.
|
||||
*/
|
||||
uint32_t error_int_raw:1;
|
||||
uint32_t reserved_2:30;
|
||||
@@ -255,16 +272,16 @@ typedef union {
|
||||
} pau_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Read only register for error and done
|
||||
* Interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** done_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* backup done flag
|
||||
* Write 1 to clear the backup done interrupt.
|
||||
*/
|
||||
uint32_t done_int_clr:1;
|
||||
/** error_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* error flag
|
||||
* Write 1 to clear the error interrupt.
|
||||
*/
|
||||
uint32_t error_int_clr:1;
|
||||
uint32_t reserved_2:30;
|
||||
@@ -273,16 +290,16 @@ typedef union {
|
||||
} pau_int_clr_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Read only register for error and done
|
||||
* Interrupt register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** done_int_st : RO; bitpos: [0]; default: 0;
|
||||
* backup done flag
|
||||
* Represents the backup completion status.
|
||||
*/
|
||||
uint32_t done_int_st:1;
|
||||
/** error_int_st : RO; bitpos: [1]; default: 0;
|
||||
* error flag
|
||||
* Represents the error status.
|
||||
*/
|
||||
uint32_t error_int_st:1;
|
||||
uint32_t reserved_2:30;
|
||||
@@ -293,12 +310,12 @@ typedef union {
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* Date register.
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36708608;
|
||||
* REGDMA date information/ REGDMA version information.
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -208,7 +208,6 @@ typedef struct pmu_hp_hw_regmap_t{
|
||||
pmu_hp_xtal_reg_t xtal;
|
||||
} pmu_hp_hw_regmap_t;
|
||||
|
||||
/** */
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 21;
|
||||
|
||||
Reference in New Issue
Block a user