diff --git a/components/soc/esp32c61/register/soc/pau_reg.h b/components/soc/esp32c61/register/soc/pau_reg.h index 267554bf73a..8c93bc47548 100644 --- a/components/soc/esp32c61/register/soc/pau_reg.h +++ b/components/soc/esp32c61/register/soc/pau_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -11,53 +11,68 @@ extern "C" { #endif /** PAU_REGDMA_CONF_REG register - * Peri backup control register + * Peripherals backup configuration/control register */ #define PAU_REGDMA_CONF_REG (DR_REG_PAU_BASE + 0x0) /** PAU_FLOW_ERR : RO; bitpos: [2:0]; default: 0; - * backup error type + * Represents the backup error type. + * 0: Received software triggered interrupt clear signal + * 1: Peripheral AHB bus timeout + * 2: Memory AHB bus timeout + * 3: Address link list wait timer timeout + * 4: Address mapping error */ #define PAU_FLOW_ERR 0x00000007U #define PAU_FLOW_ERR_M (PAU_FLOW_ERR_V << PAU_FLOW_ERR_S) #define PAU_FLOW_ERR_V 0x00000007U #define PAU_FLOW_ERR_S 0 /** PAU_START : WT; bitpos: [3]; default: 0; - * backup start signal + * Write 1 to initiate the backup start signal. */ #define PAU_START (BIT(3)) #define PAU_START_M (PAU_START_V << PAU_START_S) #define PAU_START_V 0x00000001U #define PAU_START_S 3 /** PAU_TO_MEM : R/W; bitpos: [4]; default: 0; - * backup direction(reg to mem / mem to reg) + * Configures the backup direction. + * 0: register to memory + * 1: memory to register */ #define PAU_TO_MEM (BIT(4)) #define PAU_TO_MEM_M (PAU_TO_MEM_V << PAU_TO_MEM_S) #define PAU_TO_MEM_V 0x00000001U #define PAU_TO_MEM_S 4 /** PAU_LINK_SEL : R/W; bitpos: [6:5]; default: 0; - * Link select + * Configures to select the link. + * 0: PAU_REGDMA_LINK_0_ADDR_REG + * 1: PAU_REGDMA_LINK_1_ADDR_REG + * 2: PAU_REGDMA_LINK_2_ADDR_REG + * 3: PAU_REGDMA_LINK_3_ADDR_REG */ #define PAU_LINK_SEL 0x00000003U #define PAU_LINK_SEL_M (PAU_LINK_SEL_V << PAU_LINK_SEL_S) #define PAU_LINK_SEL_V 0x00000003U #define PAU_LINK_SEL_S 5 /** PAU_START_MAC : WT; bitpos: [7]; default: 0; - * mac sw backup start signal + * Write 1 to initiate the MAC software backup start signal. */ #define PAU_START_MAC (BIT(7)) #define PAU_START_MAC_M (PAU_START_MAC_V << PAU_START_MAC_S) #define PAU_START_MAC_V 0x00000001U #define PAU_START_MAC_S 7 /** PAU_TO_MEM_MAC : R/W; bitpos: [8]; default: 0; - * mac sw backup direction(reg to mem / mem to reg) + * Configures the MAC software backup direction. + * 0: register to memory + * 1: memory to register */ #define PAU_TO_MEM_MAC (BIT(8)) #define PAU_TO_MEM_MAC_M (PAU_TO_MEM_MAC_V << PAU_TO_MEM_MAC_S) #define PAU_TO_MEM_MAC_V 0x00000001U #define PAU_TO_MEM_MAC_S 8 /** PAU_SEL_MAC : R/W; bitpos: [9]; default: 0; - * mac hw/sw select + * Configures the MAC hardware/software selection. + * 0: select the hardware path + * 1: select the software path */ #define PAU_SEL_MAC (BIT(9)) #define PAU_SEL_MAC_M (PAU_SEL_MAC_V << PAU_SEL_MAC_S) @@ -69,7 +84,9 @@ extern "C" { */ #define PAU_REGDMA_CLK_CONF_REG (DR_REG_PAU_BASE + 0x4) /** PAU_CLK_EN : R/W; bitpos: [0]; default: 0; - * clock enable + * Configures whether or not to enable clock for the PAU module. + * 0: Disable + * 1: Enable */ #define PAU_CLK_EN (BIT(0)) #define PAU_CLK_EN_M (PAU_CLK_EN_V << PAU_CLK_EN_S) @@ -77,32 +94,32 @@ extern "C" { #define PAU_CLK_EN_S 0 /** PAU_REGDMA_ETM_CTRL_REG register - * ETM start ctrl reg + * ETM start configuration/control register */ #define PAU_REGDMA_ETM_CTRL_REG (DR_REG_PAU_BASE + 0x8) /** PAU_ETM_START_0 : WT; bitpos: [0]; default: 0; - * etm_start_0 reg + * Write 1 to start ETM operation 0. */ #define PAU_ETM_START_0 (BIT(0)) #define PAU_ETM_START_0_M (PAU_ETM_START_0_V << PAU_ETM_START_0_S) #define PAU_ETM_START_0_V 0x00000001U #define PAU_ETM_START_0_S 0 /** PAU_ETM_START_1 : WT; bitpos: [1]; default: 0; - * etm_start_1 reg + * Write 1 to start ETM operation 1. */ #define PAU_ETM_START_1 (BIT(1)) #define PAU_ETM_START_1_M (PAU_ETM_START_1_V << PAU_ETM_START_1_S) #define PAU_ETM_START_1_V 0x00000001U #define PAU_ETM_START_1_S 1 /** PAU_ETM_START_2 : WT; bitpos: [2]; default: 0; - * etm_start_2 reg + * Write 1 to start ETM operation 2. */ #define PAU_ETM_START_2 (BIT(2)) #define PAU_ETM_START_2_M (PAU_ETM_START_2_V << PAU_ETM_START_2_S) #define PAU_ETM_START_2_V 0x00000001U #define PAU_ETM_START_2_S 2 /** PAU_ETM_START_3 : WT; bitpos: [3]; default: 0; - * etm_start_3 reg + * Write 1 to start ETM operation 3. */ #define PAU_ETM_START_3 (BIT(3)) #define PAU_ETM_START_3_M (PAU_ETM_START_3_V << PAU_ETM_START_3_S) @@ -110,11 +127,11 @@ extern "C" { #define PAU_ETM_START_3_S 3 /** PAU_REGDMA_LINK_0_ADDR_REG register - * link_0_addr + * Link address configuration register 0 */ #define PAU_REGDMA_LINK_0_ADDR_REG (DR_REG_PAU_BASE + 0xc) /** PAU_LINK_ADDR_0 : R/W; bitpos: [31:0]; default: 0; - * link_0_addr reg + * Represents the address for link 0. */ #define PAU_LINK_ADDR_0 0xFFFFFFFFU #define PAU_LINK_ADDR_0_M (PAU_LINK_ADDR_0_V << PAU_LINK_ADDR_0_S) @@ -122,11 +139,11 @@ extern "C" { #define PAU_LINK_ADDR_0_S 0 /** PAU_REGDMA_LINK_1_ADDR_REG register - * Link_1_addr + * Link address configuration register 1 */ #define PAU_REGDMA_LINK_1_ADDR_REG (DR_REG_PAU_BASE + 0x10) /** PAU_LINK_ADDR_1 : R/W; bitpos: [31:0]; default: 0; - * Link_1_addr reg + * Represents the address for link 1. */ #define PAU_LINK_ADDR_1 0xFFFFFFFFU #define PAU_LINK_ADDR_1_M (PAU_LINK_ADDR_1_V << PAU_LINK_ADDR_1_S) @@ -134,11 +151,11 @@ extern "C" { #define PAU_LINK_ADDR_1_S 0 /** PAU_REGDMA_LINK_2_ADDR_REG register - * Link_2_addr + * Link address configuration register 2 */ #define PAU_REGDMA_LINK_2_ADDR_REG (DR_REG_PAU_BASE + 0x14) /** PAU_LINK_ADDR_2 : R/W; bitpos: [31:0]; default: 0; - * Link_2_addr reg + * Represents the address for link 2. */ #define PAU_LINK_ADDR_2 0xFFFFFFFFU #define PAU_LINK_ADDR_2_M (PAU_LINK_ADDR_2_V << PAU_LINK_ADDR_2_S) @@ -146,11 +163,11 @@ extern "C" { #define PAU_LINK_ADDR_2_S 0 /** PAU_REGDMA_LINK_3_ADDR_REG register - * Link_3_addr + * Link address configuration register 3 */ #define PAU_REGDMA_LINK_3_ADDR_REG (DR_REG_PAU_BASE + 0x18) /** PAU_LINK_ADDR_3 : R/W; bitpos: [31:0]; default: 0; - * Link_3_addr reg + * Represents the address for link 3. */ #define PAU_LINK_ADDR_3 0xFFFFFFFFU #define PAU_LINK_ADDR_3_M (PAU_LINK_ADDR_3_V << PAU_LINK_ADDR_3_S) @@ -158,11 +175,11 @@ extern "C" { #define PAU_LINK_ADDR_3_S 0 /** PAU_REGDMA_LINK_MAC_ADDR_REG register - * Link_mac_addr + * Link MAC address register */ #define PAU_REGDMA_LINK_MAC_ADDR_REG (DR_REG_PAU_BASE + 0x1c) /** PAU_LINK_ADDR_MAC : R/W; bitpos: [31:0]; default: 0; - * Link_mac_addr reg + * Represents the MAC address for the link. */ #define PAU_LINK_ADDR_MAC 0xFFFFFFFFU #define PAU_LINK_ADDR_MAC_M (PAU_LINK_ADDR_MAC_V << PAU_LINK_ADDR_MAC_S) @@ -170,11 +187,11 @@ extern "C" { #define PAU_LINK_ADDR_MAC_S 0 /** PAU_REGDMA_CURRENT_LINK_ADDR_REG register - * current link addr + * Current link address register */ #define PAU_REGDMA_CURRENT_LINK_ADDR_REG (DR_REG_PAU_BASE + 0x20) /** PAU_CURRENT_LINK_ADDR : RO; bitpos: [31:0]; default: 0; - * current link addr reg + * Represents the current link address. */ #define PAU_CURRENT_LINK_ADDR 0xFFFFFFFFU #define PAU_CURRENT_LINK_ADDR_M (PAU_CURRENT_LINK_ADDR_V << PAU_CURRENT_LINK_ADDR_S) @@ -182,11 +199,11 @@ extern "C" { #define PAU_CURRENT_LINK_ADDR_S 0 /** PAU_REGDMA_BACKUP_ADDR_REG register - * Backup addr + * Backup address register */ #define PAU_REGDMA_BACKUP_ADDR_REG (DR_REG_PAU_BASE + 0x24) /** PAU_BACKUP_ADDR : RO; bitpos: [31:0]; default: 0; - * backup addr reg + * Represents the backup address. */ #define PAU_BACKUP_ADDR 0xFFFFFFFFU #define PAU_BACKUP_ADDR_M (PAU_BACKUP_ADDR_V << PAU_BACKUP_ADDR_S) @@ -194,11 +211,11 @@ extern "C" { #define PAU_BACKUP_ADDR_S 0 /** PAU_REGDMA_MEM_ADDR_REG register - * mem addr + * Memory address configuration register */ #define PAU_REGDMA_MEM_ADDR_REG (DR_REG_PAU_BASE + 0x28) /** PAU_MEM_ADDR : RO; bitpos: [31:0]; default: 0; - * mem addr reg + * Represents the memory address. */ #define PAU_MEM_ADDR 0xFFFFFFFFU #define PAU_MEM_ADDR_M (PAU_MEM_ADDR_V << PAU_MEM_ADDR_S) @@ -206,32 +223,32 @@ extern "C" { #define PAU_MEM_ADDR_S 0 /** PAU_REGDMA_BKP_CONF_REG register - * backup config + * Link configuration register */ #define PAU_REGDMA_BKP_CONF_REG (DR_REG_PAU_BASE + 0x2c) /** PAU_READ_INTERVAL : R/W; bitpos: [6:0]; default: 32; - * Link read_interval + * Configures the read interval for the link. */ #define PAU_READ_INTERVAL 0x0000007FU #define PAU_READ_INTERVAL_M (PAU_READ_INTERVAL_V << PAU_READ_INTERVAL_S) #define PAU_READ_INTERVAL_V 0x0000007FU #define PAU_READ_INTERVAL_S 0 /** PAU_LINK_TOUT_THRES : R/W; bitpos: [16:7]; default: 50; - * link wait timeout threshold + * Configures the link wait timeout threshold. */ #define PAU_LINK_TOUT_THRES 0x000003FFU #define PAU_LINK_TOUT_THRES_M (PAU_LINK_TOUT_THRES_V << PAU_LINK_TOUT_THRES_S) #define PAU_LINK_TOUT_THRES_V 0x000003FFU #define PAU_LINK_TOUT_THRES_S 7 /** PAU_BURST_LIMIT : R/W; bitpos: [21:17]; default: 8; - * burst limit + * Configures the burst limit. */ #define PAU_BURST_LIMIT 0x0000001FU #define PAU_BURST_LIMIT_M (PAU_BURST_LIMIT_V << PAU_BURST_LIMIT_S) #define PAU_BURST_LIMIT_V 0x0000001FU #define PAU_BURST_LIMIT_S 17 /** PAU_BACKUP_TOUT_THRES : R/W; bitpos: [31:22]; default: 500; - * Backup timeout threshold + * Configures the backup timeout threshold. */ #define PAU_BACKUP_TOUT_THRES 0x000003FFU #define PAU_BACKUP_TOUT_THRES_M (PAU_BACKUP_TOUT_THRES_V << PAU_BACKUP_TOUT_THRES_S) @@ -239,18 +256,18 @@ extern "C" { #define PAU_BACKUP_TOUT_THRES_S 22 /** PAU_INT_ENA_REG register - * Read only register for error and done + * Interrupt register */ #define PAU_INT_ENA_REG (DR_REG_PAU_BASE + 0x30) /** PAU_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * backup done flag + * Write 1 to enable backup done interrupt. */ #define PAU_DONE_INT_ENA (BIT(0)) #define PAU_DONE_INT_ENA_M (PAU_DONE_INT_ENA_V << PAU_DONE_INT_ENA_S) #define PAU_DONE_INT_ENA_V 0x00000001U #define PAU_DONE_INT_ENA_S 0 /** PAU_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; - * error flag + * Write 1 to enable error interrupt. */ #define PAU_ERROR_INT_ENA (BIT(1)) #define PAU_ERROR_INT_ENA_M (PAU_ERROR_INT_ENA_V << PAU_ERROR_INT_ENA_S) @@ -258,18 +275,18 @@ extern "C" { #define PAU_ERROR_INT_ENA_S 1 /** PAU_INT_RAW_REG register - * Read only register for error and done + * Interrupt register */ #define PAU_INT_RAW_REG (DR_REG_PAU_BASE + 0x34) /** PAU_DONE_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * backup done flag + * The raw interrupt status for backup completion. */ #define PAU_DONE_INT_RAW (BIT(0)) #define PAU_DONE_INT_RAW_M (PAU_DONE_INT_RAW_V << PAU_DONE_INT_RAW_S) #define PAU_DONE_INT_RAW_V 0x00000001U #define PAU_DONE_INT_RAW_S 0 /** PAU_ERROR_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * error flag + * The raw interrupt status for errors. */ #define PAU_ERROR_INT_RAW (BIT(1)) #define PAU_ERROR_INT_RAW_M (PAU_ERROR_INT_RAW_V << PAU_ERROR_INT_RAW_S) @@ -277,18 +294,18 @@ extern "C" { #define PAU_ERROR_INT_RAW_S 1 /** PAU_INT_CLR_REG register - * Read only register for error and done + * Interrupt register */ #define PAU_INT_CLR_REG (DR_REG_PAU_BASE + 0x38) /** PAU_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * backup done flag + * Write 1 to clear the backup done interrupt. */ #define PAU_DONE_INT_CLR (BIT(0)) #define PAU_DONE_INT_CLR_M (PAU_DONE_INT_CLR_V << PAU_DONE_INT_CLR_S) #define PAU_DONE_INT_CLR_V 0x00000001U #define PAU_DONE_INT_CLR_S 0 /** PAU_ERROR_INT_CLR : WT; bitpos: [1]; default: 0; - * error flag + * Write 1 to clear the error interrupt. */ #define PAU_ERROR_INT_CLR (BIT(1)) #define PAU_ERROR_INT_CLR_M (PAU_ERROR_INT_CLR_V << PAU_ERROR_INT_CLR_S) @@ -296,18 +313,18 @@ extern "C" { #define PAU_ERROR_INT_CLR_S 1 /** PAU_INT_ST_REG register - * Read only register for error and done + * Interrupt register */ #define PAU_INT_ST_REG (DR_REG_PAU_BASE + 0x3c) /** PAU_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * backup done flag + * Represents the backup completion status. */ #define PAU_DONE_INT_ST (BIT(0)) #define PAU_DONE_INT_ST_M (PAU_DONE_INT_ST_V << PAU_DONE_INT_ST_S) #define PAU_DONE_INT_ST_V 0x00000001U #define PAU_DONE_INT_ST_S 0 /** PAU_ERROR_INT_ST : RO; bitpos: [1]; default: 0; - * error flag + * Represents the error status. */ #define PAU_ERROR_INT_ST (BIT(1)) #define PAU_ERROR_INT_ST_M (PAU_ERROR_INT_ST_V << PAU_ERROR_INT_ST_S) @@ -315,11 +332,11 @@ extern "C" { #define PAU_ERROR_INT_ST_S 1 /** PAU_DATE_REG register - * Date register. + * Version control register */ #define PAU_DATE_REG (DR_REG_PAU_BASE + 0x3fc) /** PAU_DATE : R/W; bitpos: [27:0]; default: 36708608; - * REGDMA date information/ REGDMA version information. + * Version control register. */ #define PAU_DATE 0x0FFFFFFFU #define PAU_DATE_M (PAU_DATE_V << PAU_DATE_S) diff --git a/components/soc/esp32c61/register/soc/pau_struct.h b/components/soc/esp32c61/register/soc/pau_struct.h index eb5992f8a7b..e86a067be31 100644 --- a/components/soc/esp32c61/register/soc/pau_struct.h +++ b/components/soc/esp32c61/register/soc/pau_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -12,36 +12,51 @@ extern "C" { /** Group: Configuration Register */ /** Type of regdma_conf register - * Peri backup control register + * Peripherals backup configuration/control register */ typedef union { struct { /** flow_err : RO; bitpos: [2:0]; default: 0; - * backup error type + * Represents the backup error type. + * 0: Received software triggered interrupt clear signal + * 1: Peripheral AHB bus timeout + * 2: Memory AHB bus timeout + * 3: Address link list wait timer timeout + * 4: Address mapping error */ uint32_t flow_err:3; /** start : WT; bitpos: [3]; default: 0; - * backup start signal + * Write 1 to initiate the backup start signal. */ uint32_t start:1; /** to_mem : R/W; bitpos: [4]; default: 0; - * backup direction(reg to mem / mem to reg) + * Configures the backup direction. + * 0: register to memory + * 1: memory to register */ uint32_t to_mem:1; /** link_sel : R/W; bitpos: [6:5]; default: 0; - * Link select + * Configures to select the link. + * 0: PAU_REGDMA_LINK_0_ADDR_REG + * 1: PAU_REGDMA_LINK_1_ADDR_REG + * 2: PAU_REGDMA_LINK_2_ADDR_REG + * 3: PAU_REGDMA_LINK_3_ADDR_REG */ uint32_t link_sel:2; /** start_mac : WT; bitpos: [7]; default: 0; - * mac sw backup start signal + * Write 1 to initiate the MAC software backup start signal. */ uint32_t start_mac:1; /** to_mem_mac : R/W; bitpos: [8]; default: 0; - * mac sw backup direction(reg to mem / mem to reg) + * Configures the MAC software backup direction. + * 0: register to memory + * 1: memory to register */ uint32_t to_mem_mac:1; /** sel_mac : R/W; bitpos: [9]; default: 0; - * mac hw/sw select + * Configures the MAC hardware/software selection. + * 0: select the hardware path + * 1: select the software path */ uint32_t sel_mac:1; uint32_t reserved_10:22; @@ -55,7 +70,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * clock enable + * Configures whether or not to enable clock for the PAU module. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -64,24 +81,24 @@ typedef union { } pau_regdma_clk_conf_reg_t; /** Type of regdma_etm_ctrl register - * ETM start ctrl reg + * ETM start configuration/control register */ typedef union { struct { /** etm_start_0 : WT; bitpos: [0]; default: 0; - * etm_start_0 reg + * Write 1 to start ETM operation 0. */ uint32_t etm_start_0:1; /** etm_start_1 : WT; bitpos: [1]; default: 0; - * etm_start_1 reg + * Write 1 to start ETM operation 1. */ uint32_t etm_start_1:1; /** etm_start_2 : WT; bitpos: [2]; default: 0; - * etm_start_2 reg + * Write 1 to start ETM operation 2. */ uint32_t etm_start_2:1; /** etm_start_3 : WT; bitpos: [3]; default: 0; - * etm_start_3 reg + * Write 1 to start ETM operation 3. */ uint32_t etm_start_3:1; uint32_t reserved_4:28; @@ -90,12 +107,12 @@ typedef union { } pau_regdma_etm_ctrl_reg_t; /** Type of regdma_link_0_addr register - * link_0_addr + * Link address configuration register 0 */ typedef union { struct { /** link_addr_0 : R/W; bitpos: [31:0]; default: 0; - * link_0_addr reg + * Represents the address for link 0. */ uint32_t link_addr_0:32; }; @@ -103,12 +120,12 @@ typedef union { } pau_regdma_link_0_addr_reg_t; /** Type of regdma_link_1_addr register - * Link_1_addr + * Link address configuration register 1 */ typedef union { struct { /** link_addr_1 : R/W; bitpos: [31:0]; default: 0; - * Link_1_addr reg + * Represents the address for link 1. */ uint32_t link_addr_1:32; }; @@ -116,12 +133,12 @@ typedef union { } pau_regdma_link_1_addr_reg_t; /** Type of regdma_link_2_addr register - * Link_2_addr + * Link address configuration register 2 */ typedef union { struct { /** link_addr_2 : R/W; bitpos: [31:0]; default: 0; - * Link_2_addr reg + * Represents the address for link 2. */ uint32_t link_addr_2:32; }; @@ -129,12 +146,12 @@ typedef union { } pau_regdma_link_2_addr_reg_t; /** Type of regdma_link_3_addr register - * Link_3_addr + * Link address configuration register 3 */ typedef union { struct { /** link_addr_3 : R/W; bitpos: [31:0]; default: 0; - * Link_3_addr reg + * Represents the address for link 3. */ uint32_t link_addr_3:32; }; @@ -142,12 +159,12 @@ typedef union { } pau_regdma_link_3_addr_reg_t; /** Type of regdma_link_mac_addr register - * Link_mac_addr + * Link MAC address register */ typedef union { struct { /** link_addr_mac : R/W; bitpos: [31:0]; default: 0; - * Link_mac_addr reg + * Represents the MAC address for the link. */ uint32_t link_addr_mac:32; }; @@ -155,12 +172,12 @@ typedef union { } pau_regdma_link_mac_addr_reg_t; /** Type of regdma_current_link_addr register - * current link addr + * Current link address register */ typedef union { struct { /** current_link_addr : RO; bitpos: [31:0]; default: 0; - * current link addr reg + * Represents the current link address. */ uint32_t current_link_addr:32; }; @@ -168,12 +185,12 @@ typedef union { } pau_regdma_current_link_addr_reg_t; /** Type of regdma_backup_addr register - * Backup addr + * Backup address register */ typedef union { struct { /** backup_addr : RO; bitpos: [31:0]; default: 0; - * backup addr reg + * Represents the backup address. */ uint32_t backup_addr:32; }; @@ -181,12 +198,12 @@ typedef union { } pau_regdma_backup_addr_reg_t; /** Type of regdma_mem_addr register - * mem addr + * Memory address configuration register */ typedef union { struct { /** mem_addr : RO; bitpos: [31:0]; default: 0; - * mem addr reg + * Represents the memory address. */ uint32_t mem_addr:32; }; @@ -194,24 +211,24 @@ typedef union { } pau_regdma_mem_addr_reg_t; /** Type of regdma_bkp_conf register - * backup config + * Link configuration register */ typedef union { struct { /** read_interval : R/W; bitpos: [6:0]; default: 32; - * Link read_interval + * Configures the read interval for the link. */ uint32_t read_interval:7; /** link_tout_thres : R/W; bitpos: [16:7]; default: 50; - * link wait timeout threshold + * Configures the link wait timeout threshold. */ uint32_t link_tout_thres:10; /** burst_limit : R/W; bitpos: [21:17]; default: 8; - * burst limit + * Configures the burst limit. */ uint32_t burst_limit:5; /** backup_tout_thres : R/W; bitpos: [31:22]; default: 500; - * Backup timeout threshold + * Configures the backup timeout threshold. */ uint32_t backup_tout_thres:10; }; @@ -219,16 +236,16 @@ typedef union { } pau_regdma_bkp_conf_reg_t; /** Type of int_ena register - * Read only register for error and done + * Interrupt register */ typedef union { struct { /** done_int_ena : R/W; bitpos: [0]; default: 0; - * backup done flag + * Write 1 to enable backup done interrupt. */ uint32_t done_int_ena:1; /** error_int_ena : R/W; bitpos: [1]; default: 0; - * error flag + * Write 1 to enable error interrupt. */ uint32_t error_int_ena:1; uint32_t reserved_2:30; @@ -237,16 +254,16 @@ typedef union { } pau_int_ena_reg_t; /** Type of int_raw register - * Read only register for error and done + * Interrupt register */ typedef union { struct { /** done_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * backup done flag + * The raw interrupt status for backup completion. */ uint32_t done_int_raw:1; /** error_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * error flag + * The raw interrupt status for errors. */ uint32_t error_int_raw:1; uint32_t reserved_2:30; @@ -255,16 +272,16 @@ typedef union { } pau_int_raw_reg_t; /** Type of int_clr register - * Read only register for error and done + * Interrupt register */ typedef union { struct { /** done_int_clr : WT; bitpos: [0]; default: 0; - * backup done flag + * Write 1 to clear the backup done interrupt. */ uint32_t done_int_clr:1; /** error_int_clr : WT; bitpos: [1]; default: 0; - * error flag + * Write 1 to clear the error interrupt. */ uint32_t error_int_clr:1; uint32_t reserved_2:30; @@ -273,16 +290,16 @@ typedef union { } pau_int_clr_reg_t; /** Type of int_st register - * Read only register for error and done + * Interrupt register */ typedef union { struct { /** done_int_st : RO; bitpos: [0]; default: 0; - * backup done flag + * Represents the backup completion status. */ uint32_t done_int_st:1; /** error_int_st : RO; bitpos: [1]; default: 0; - * error flag + * Represents the error status. */ uint32_t error_int_st:1; uint32_t reserved_2:30; @@ -293,12 +310,12 @@ typedef union { /** Group: Version Register */ /** Type of date register - * Date register. + * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 36708608; - * REGDMA date information/ REGDMA version information. + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c61/register/soc/pmu_reg.h b/components/soc/esp32c61/register/soc/pmu_reg.h index 41b4d5b249f..d32f6745b9a 100644 --- a/components/soc/esp32c61/register/soc/pmu_reg.h +++ b/components/soc/esp32c61/register/soc/pmu_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -11,18 +11,22 @@ extern "C" { #endif /** PMU_HP_ACTIVE_DIG_POWER_REG register - * need_des + * Configuration register of digital power domains in HP_ACTIVE state */ #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) /** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; - * need_des + * Configures whether to power down external flash in HP_ACTIVE state. + * 0: Power up + * 1: Power down */ #define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; - * need_des + * Configures whether to put Internal SRAM$x ($x= 0, 1, 2) into Deep-sleep mode in HP_ACTIVE state. + * 0: Do not put Internal SRAM into Deep-sleep + * 1: Put Internal SRAM into Deep-sleep */ #define PMU_HP_ACTIVE_HP_MEM_DSLP (BIT(22)) #define PMU_HP_ACTIVE_HP_MEM_DSLP_M (PMU_HP_ACTIVE_HP_MEM_DSLP_V << PMU_HP_ACTIVE_HP_MEM_DSLP_S) @@ -36,7 +40,9 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x0000000FU #define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23 /** PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to power down MODEM domain in HP_ACTIVE state. + * 0: Power up + * 1: Power down */ #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN (BIT(27)) #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) @@ -50,21 +56,27 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to power down CPU domain in HP_ACTIVE state. + * 0: Power up + * 1: Power down */ #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29)) #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_ACTIVE_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to power down Modem Power domain in HP_ACTIVE state. + * 0: Power up + * 1: Power down */ #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN (BIT(30)) #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_M (PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V << PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_AON_PD_EN_S 30 /** PMU_HP_ACTIVE_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power down Peripherals+ROM domain in HP_ACTIVE state. + * 0: Power up + * 1: Power down */ #define PMU_HP_ACTIVE_PD_TOP_PD_EN (BIT(31)) #define PMU_HP_ACTIVE_PD_TOP_PD_EN_M (PMU_HP_ACTIVE_PD_TOP_PD_EN_V << PMU_HP_ACTIVE_PD_TOP_PD_EN_S) @@ -72,11 +84,13 @@ extern "C" { #define PMU_HP_ACTIVE_PD_TOP_PD_EN_S 31 /** PMU_HP_ACTIVE_ICG_HP_FUNC_REG register - * need_des + * Control register of HP system peripherals' function clocks in HP_ACTIVE state */ #define PMU_HP_ACTIVE_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x4) /** PMU_HP_ACTIVE_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' function clock in HP_ACTIVE state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_M (PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_V << PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S) @@ -84,11 +98,13 @@ extern "C" { #define PMU_HP_ACTIVE_DIG_ICG_FUNC_EN_S 0 /** PMU_HP_ACTIVE_ICG_HP_APB_REG register - * need_des + * Control register of HP system peripherals' APB clocks in HP_ACTIVE state */ #define PMU_HP_ACTIVE_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x8) /** PMU_HP_ACTIVE_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' APB clock in HP_ACTIVE state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_DIG_ICG_APB_EN 0xFFFFFFFFU #define PMU_HP_ACTIVE_DIG_ICG_APB_EN_M (PMU_HP_ACTIVE_DIG_ICG_APB_EN_V << PMU_HP_ACTIVE_DIG_ICG_APB_EN_S) @@ -96,11 +112,11 @@ extern "C" { #define PMU_HP_ACTIVE_DIG_ICG_APB_EN_S 0 /** PMU_HP_ACTIVE_ICG_MODEM_REG register - * need_des + * Control register of HP system Modem clock gating in HP_ACTIVE state */ #define PMU_HP_ACTIVE_ICG_MODEM_REG (DR_REG_PMU_BASE + 0xc) /** PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the Modem clock gate in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE 0x00000003U #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_M (PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_V << PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S) @@ -108,46 +124,58 @@ extern "C" { #define PMU_HP_ACTIVE_DIG_ICG_MODEM_CODE_S 30 /** PMU_HP_ACTIVE_HP_SYS_CNTL_REG register - * need_des + * System control register in HP_ACTIVE state */ #define PMU_HP_ACTIVE_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x10) /** PMU_HP_ACTIVE_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; - * need_des + * Configures whether to enable UART wake-up function in HP_ACTIVE state. + * 0: Disable wake-up function + * 1: Enable wake-up function */ #define PMU_HP_ACTIVE_UART_WAKEUP_EN (BIT(24)) #define PMU_HP_ACTIVE_UART_WAKEUP_EN_M (PMU_HP_ACTIVE_UART_WAKEUP_EN_V << PMU_HP_ACTIVE_UART_WAKEUP_EN_S) #define PMU_HP_ACTIVE_UART_WAKEUP_EN_V 0x00000001U #define PMU_HP_ACTIVE_UART_WAKEUP_EN_S 24 /** PMU_HP_ACTIVE_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; - * need_des + * Configures whether to hold LP GPIOs' configuration in HP_ACTIVE state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL (BIT(25)) #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S) #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_ACTIVE_LP_PAD_HOLD_ALL_S 25 /** PMU_HP_ACTIVE_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to hold HP GPIOs' configuration in HP_ACTIVE state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL (BIT(26)) #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_M (PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V << PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S) #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_ACTIVE_HP_PAD_HOLD_ALL_S 26 /** PMU_HP_ACTIVE_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to use Light-sleep mode configuration for GPIO in HP_ACTIVE state. + * 0: Use normal configuration + * 1: Use Light-sleep mode configuration. */ #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL (BIT(27)) #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_M (PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V << PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S) #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_V 0x00000001U #define PMU_HP_ACTIVE_DIG_PAD_SLP_SEL_S 27 /** PMU_HP_ACTIVE_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to pause watchdog in HP_ACTIVE state. + * 0: Do not pause + * 1: Pause */ #define PMU_HP_ACTIVE_DIG_PAUSE_WDT (BIT(28)) #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_M (PMU_HP_ACTIVE_DIG_PAUSE_WDT_V << PMU_HP_ACTIVE_DIG_PAUSE_WDT_S) #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_V 0x00000001U #define PMU_HP_ACTIVE_DIG_PAUSE_WDT_S 28 /** PMU_HP_ACTIVE_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to stall CPU in HP_ACTIVE state. + * 0: Do not stall + * 1: Stall */ #define PMU_HP_ACTIVE_DIG_CPU_STALL (BIT(29)) #define PMU_HP_ACTIVE_DIG_CPU_STALL_M (PMU_HP_ACTIVE_DIG_CPU_STALL_V << PMU_HP_ACTIVE_DIG_CPU_STALL_S) @@ -155,39 +183,49 @@ extern "C" { #define PMU_HP_ACTIVE_DIG_CPU_STALL_S 29 /** PMU_HP_ACTIVE_HP_CK_POWER_REG register - * need_des + * Control register of clock source's power in HP_ACTIVE state */ #define PMU_HP_ACTIVE_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x14) /** PMU_HP_ACTIVE_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable I2C_ISO in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_I2C_ISO_EN (BIT(26)) #define PMU_HP_ACTIVE_I2C_ISO_EN_M (PMU_HP_ACTIVE_I2C_ISO_EN_V << PMU_HP_ACTIVE_I2C_ISO_EN_S) #define PMU_HP_ACTIVE_I2C_ISO_EN_V 0x00000001U #define PMU_HP_ACTIVE_I2C_ISO_EN_S 26 /** PMU_HP_ACTIVE_I2C_RETENTION : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to enable I2C retention in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_I2C_RETENTION (BIT(27)) #define PMU_HP_ACTIVE_I2C_RETENTION_M (PMU_HP_ACTIVE_I2C_RETENTION_V << PMU_HP_ACTIVE_I2C_RETENTION_S) #define PMU_HP_ACTIVE_I2C_RETENTION_V 0x00000001U #define PMU_HP_ACTIVE_I2C_RETENTION_S 27 /** PMU_HP_ACTIVE_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to enable BB_I2C in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_XPD_BB_I2C (BIT(28)) #define PMU_HP_ACTIVE_XPD_BB_I2C_M (PMU_HP_ACTIVE_XPD_BB_I2C_V << PMU_HP_ACTIVE_XPD_BB_I2C_S) #define PMU_HP_ACTIVE_XPD_BB_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BB_I2C_S 28 /** PMU_HP_ACTIVE_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to enable BBPLL_I2C in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_XPD_BBPLL_I2C (BIT(29)) #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_M (PMU_HP_ACTIVE_XPD_BBPLL_I2C_V << PMU_HP_ACTIVE_XPD_BBPLL_I2C_S) #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BBPLL_I2C_S 29 /** PMU_HP_ACTIVE_XPD_BBPLL : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable BBPLL in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_XPD_BBPLL (BIT(30)) #define PMU_HP_ACTIVE_XPD_BBPLL_M (PMU_HP_ACTIVE_XPD_BBPLL_V << PMU_HP_ACTIVE_XPD_BBPLL_S) @@ -195,32 +233,32 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BBPLL_S 30 /** PMU_HP_ACTIVE_BIAS_REG register - * need_des + * Control register for the operating state of analog circuits (BIAS, DBG, CUR circuits) in HP_ACTIVE state */ #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) /** PMU_HP_ACTIVE_XPD_BIAS : R/W; bitpos: [25]; default: 0; - * need_des + * Configures the power supply of BIAS in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_XPD_BIAS (BIT(25)) #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BIAS_S 25 /** PMU_HP_ACTIVE_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; - * need_des + * Configures the degree of attenuation of the analog band gap in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_DBG_ATTEN 0x0000000FU #define PMU_HP_ACTIVE_DBG_ATTEN_M (PMU_HP_ACTIVE_DBG_ATTEN_V << PMU_HP_ACTIVE_DBG_ATTEN_S) #define PMU_HP_ACTIVE_DBG_ATTEN_V 0x0000000FU #define PMU_HP_ACTIVE_DBG_ATTEN_S 26 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; - * need_des + * Configures the power-down current in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_PD_CUR (BIT(30)) #define PMU_HP_ACTIVE_PD_CUR_M (PMU_HP_ACTIVE_PD_CUR_V << PMU_HP_ACTIVE_PD_CUR_S) #define PMU_HP_ACTIVE_PD_CUR_V 0x00000001U #define PMU_HP_ACTIVE_PD_CUR_S 30 /** PMU_HP_ACTIVE_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; - * need_des + * Configures the sleep or wakeup status of the BIAS circuit in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_BIAS_SLEEP (BIT(31)) #define PMU_HP_ACTIVE_BIAS_SLEEP_M (PMU_HP_ACTIVE_BIAS_SLEEP_V << PMU_HP_ACTIVE_BIAS_SLEEP_S) @@ -228,18 +266,18 @@ extern "C" { #define PMU_HP_ACTIVE_BIAS_SLEEP_S 31 /** PMU_HP_ACTIVE_BACKUP_REG register - * need_des + * Data backup control register in HP_ACTIVE state */ #define PMU_HP_ACTIVE_BACKUP_REG (DR_REG_PMU_BASE + 0x1c) /** PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; - * need_des + * Configures the ICG during backup process when PMU state switches from HP_SLEEP to HP_ACTIVE. */ #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_S 4 /** PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; - * need_des + * Configures the ICG during backup process when PMU state switches from HP_MODEM to HP_ACTIVE. */ #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) @@ -267,42 +305,58 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U #define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; - * need_des + * Configures the backup module's function clock source when PMU state switches from HP_SLEEP to HP_ACTIVE. + * 0: Select XTAL + * 1: Select PLL_CLK + * 2: Select RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_S 14 /** PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * need_des + * Configures the backup module's function clock source when PMU state switches from HP_MODEM to HP_ACTIVE. The configuration is the same as the register above. */ #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 /** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; - * need_des + * Configures the backup direction and link list when PMU state switches switch from HP_SLEEP to HP_ACTIVE. + * Higher two bits: + * 0: From peripheral to memory + * 1: From memory to peripheral + * Lower four bits: + * 0: PAU_LINK_ADDR_0 + * 1: PAU_LINK_ADDR_1 + * 2: PAU_LINK_ADDR_2 + * 3: PAU_LINK_ADDR_3 */ #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 /** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; - * need_des + * Configures the backup direction and link list when PMU state switches from HP_MODEM to HP_ACTIVE. The configuration is the same as the register above. */ #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to enable the backup flow when PMU state switches from HP_SLEEP to HP_ACTIVE. + * 0: Disable backup + * 1: Enable backup */ #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN (BIT(29)) #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_M (PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V << PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S) #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_V 0x00000001U #define PMU_HP_SLEEP2ACTIVE_BACKUP_EN_S 29 /** PMU_HP_MODEM2ACTIVE_BACKUP_EN : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable the backup flow when PMU state switches from HP_MODEM to HP_ACTIVE. + * 0: Disable backup + * 1: Enable backup */ #define PMU_HP_MODEM2ACTIVE_BACKUP_EN (BIT(30)) #define PMU_HP_MODEM2ACTIVE_BACKUP_EN_M (PMU_HP_MODEM2ACTIVE_BACKUP_EN_V << PMU_HP_MODEM2ACTIVE_BACKUP_EN_S) @@ -310,11 +364,13 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_EN_S 30 /** PMU_HP_ACTIVE_BACKUP_CLK_REG register - * need_des + * Control register for the operating clocks of the backup module in HP_ACTIVE state */ #define PMU_HP_ACTIVE_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x20) /** PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; - * need_des + * Configures whether to enable each peripherals' function clock when the target state is HP_ACTIVE. For details, please refer to Chapter link. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_M (PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_V << PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S) @@ -322,39 +378,49 @@ extern "C" { #define PMU_HP_ACTIVE_BACKUP_ICG_FUNC_EN_S 0 /** PMU_HP_ACTIVE_SYSCLK_REG register - * need_des + * Control register of the system clocks in HP_ACTIVE state */ #define PMU_HP_ACTIVE_SYSCLK_REG (DR_REG_PMU_BASE + 0x24) /** PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable the clock division for HP_ROOT_CLK in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV (BIT(26)) #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_M (PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V << PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S) #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_V 0x00000001U #define PMU_HP_ACTIVE_DIG_SYS_CLK_NO_DIV_S 26 /** PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to enable HP_ROOT_CLK in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN (BIT(27)) #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_M (PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V << PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S) #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_V 0x00000001U #define PMU_HP_ACTIVE_ICG_SYS_CLOCK_EN_S 27 /** PMU_HP_ACTIVE_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to allow PMU to control clock source in HP_ACTIVE state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL (BIT(28)) #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_M (PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V << PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S) #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_V 0x00000001U #define PMU_HP_ACTIVE_SYS_CLK_SLP_SEL_S 28 /** PMU_HP_ACTIVE_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to allow PMU to control the clock gating in HP_ACTIVE state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_ACTIVE_ICG_SLP_SEL (BIT(29)) #define PMU_HP_ACTIVE_ICG_SLP_SEL_M (PMU_HP_ACTIVE_ICG_SLP_SEL_V << PMU_HP_ACTIVE_ICG_SLP_SEL_S) #define PMU_HP_ACTIVE_ICG_SLP_SEL_V 0x00000001U #define PMU_HP_ACTIVE_ICG_SLP_SEL_S 29 /** PMU_HP_ACTIVE_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the source of HP_ROOT_CLK in HP_ACTIVE state. + * 0: XTAL + * 1: PLL_CLK + * 2: RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL 0x00000003U #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_M (PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_V << PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S) @@ -362,7 +428,7 @@ extern "C" { #define PMU_HP_ACTIVE_DIG_SYS_CLK_SEL_S 30 /** PMU_HP_ACTIVE_HP_REGULATOR0_REG register - * need_des + * Control register of HP regulators' power in HP_ACTIVE state, controlling all settings except drive */ #define PMU_HP_ACTIVE_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x28) /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [3]; default: 1; @@ -373,21 +439,28 @@ extern "C" { #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_CONNECT_EN_S 3 /** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; - * need_des + * Indicates the voltage level based on PVT_RTC data, which is the feedback from the PVT module in LP_SLEEP state. */ #define PMU_LP_DBIAS_VOL 0x0000001FU #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) #define PMU_LP_DBIAS_VOL_V 0x0000001FU #define PMU_LP_DBIAS_VOL_S 4 /** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; - * need_des + * Indicates the voltage level based on PVT data, which is the feedback from PVT module in HP_SLEEP state. */ #define PMU_HP_DBIAS_VOL 0x0000001FU #define PMU_HP_DBIAS_VOL_M (PMU_HP_DBIAS_VOL_V << PMU_HP_DBIAS_VOL_S) #define PMU_HP_DBIAS_VOL_V 0x0000001FU #define PMU_HP_DBIAS_VOL_S 9 /** PMU_DIG_REGULATOR0_DBIAS_SEL : R/W; bitpos: [14]; default: 1; - * need_des + * Configures to select the DREG configuration source for main HP and LP regulators in different PMU states. + * 0: PMU_HP_DBIAS_VOL + * 1: DREG value of respective main regulators in respective PMU states configured via the following register fields: + * + * - PMU_HP_ACTIVE_HP_REGULATOR_DBIAS + * - PMU_HP_SLEEP_HP_REGULATOR_DBIAS + * - PMU_HP_ACTIVE_LP_REGULATOR_DBIAS + * - PMU_HP_SLEEP_LP_REGULATOR_DBIAS */ #define PMU_DIG_REGULATOR0_DBIAS_SEL (BIT(14)) #define PMU_DIG_REGULATOR0_DBIAS_SEL_M (PMU_DIG_REGULATOR0_DBIAS_SEL_V << PMU_DIG_REGULATOR0_DBIAS_SEL_S) @@ -401,42 +474,48 @@ extern "C" { #define PMU_DIG_DBIAS_INIT_V 0x00000001U #define PMU_DIG_DBIAS_INIT_S 15 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; - * need_des + * Configures whether to enable the secondary regulator powering the HP memory in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_S 16 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; - * need_des + * Configures whether to enable the secondary regulator powering the logic circuit in all HP domains in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_S 17 /** PMU_HP_ACTIVE_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; - * need_des + * Configures whether to enable the main HP regulator in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_HP_REGULATOR_XPD (BIT(18)) #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_M (PMU_HP_ACTIVE_HP_REGULATOR_XPD_V << PMU_HP_ACTIVE_HP_REGULATOR_XPD_S) #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_V 0x00000001U #define PMU_HP_ACTIVE_HP_REGULATOR_XPD_S 18 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the HP memory in HP_ACTIVE state, adjusting its output voltage. */ #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_S 19 /** PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the logic circuits in HP domain in HP_ACTIVE state, adjusting its output voltage. */ #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S) #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU #define PMU_HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 /** PMU_HP_ACTIVE_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; - * need_des + * Configures the DREG value of the main HP regulator in HP_ACTIVE state, adjusting its output voltage. */ #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS 0x0000001FU #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_M (PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_V << PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S) @@ -444,11 +523,11 @@ extern "C" { #define PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S 27 /** PMU_HP_ACTIVE_HP_REGULATOR1_REG register - * need_des + * Control register of HP regulators' power in HP_ACTIVE state, controlling drive settings */ #define PMU_HP_ACTIVE_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x2c) /** PMU_HP_ACTIVE_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; - * need_des + * Configures the drive strength of the main HP regulator in HP_ACTIVE state. */ #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B 0x00FFFFFFU #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_M (PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_V << PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S) @@ -456,11 +535,13 @@ extern "C" { #define PMU_HP_ACTIVE_HP_REGULATOR_DRV_B_S 8 /** PMU_HP_ACTIVE_XTAL_REG register - * need_des + * XTAL_CLK power control register in HP_ACTIVE state */ #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; - * need_des + * Configures whether to enable XTAL_CLK in HP_ACTIVE state. + * 0: Disable + * 1: Enable */ #define PMU_HP_ACTIVE_XPD_XTAL (BIT(31)) #define PMU_HP_ACTIVE_XPD_XTAL_M (PMU_HP_ACTIVE_XPD_XTAL_V << PMU_HP_ACTIVE_XPD_XTAL_S) @@ -468,18 +549,22 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_XTAL_S 31 /** PMU_HP_MODEM_DIG_POWER_REG register - * need_des + * Configuration register of digital power domains in HP_MODEM state */ #define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) /** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; - * need_des + * Configures whether to power down external flash in HP_MODEM state. + * 0: Power up + * 1: Power down */ #define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) #define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) #define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U #define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 /** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; - * need_des + * Configures whether to put Internal SRAM$x ($x= 0, 1, 2) into Deep-sleep mode in HP_MODEM state. + * 0: Do not put Internal SRAM into Deep-sleep + * 1: Put Internal SRAM into Deep-sleep */ #define PMU_HP_MODEM_HP_MEM_DSLP (BIT(22)) #define PMU_HP_MODEM_HP_MEM_DSLP_M (PMU_HP_MODEM_HP_MEM_DSLP_V << PMU_HP_MODEM_HP_MEM_DSLP_S) @@ -493,7 +578,9 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_V 0x0000000FU #define PMU_HP_MODEM_PD_HP_MEM_PD_EN_S 23 /** PMU_HP_MODEM_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to power down MODEM domain in HP_MODEM state. + * 0: Power up + * 1: Power down */ #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN (BIT(27)) #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) @@ -507,21 +594,27 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U #define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to power down CPU domain in HP_MODEM state. + * 0: Power up + * 1: Power down */ #define PMU_HP_MODEM_PD_HP_CPU_PD_EN (BIT(29)) #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_M (PMU_HP_MODEM_PD_HP_CPU_PD_EN_V << PMU_HP_MODEM_PD_HP_CPU_PD_EN_S) #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_V 0x00000001U #define PMU_HP_MODEM_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_MODEM_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to power down Modem Power domain in HP_MODEM state. + * 0: Power up + * 1: Power down */ #define PMU_HP_MODEM_PD_HP_AON_PD_EN (BIT(30)) #define PMU_HP_MODEM_PD_HP_AON_PD_EN_M (PMU_HP_MODEM_PD_HP_AON_PD_EN_V << PMU_HP_MODEM_PD_HP_AON_PD_EN_S) #define PMU_HP_MODEM_PD_HP_AON_PD_EN_V 0x00000001U #define PMU_HP_MODEM_PD_HP_AON_PD_EN_S 30 /** PMU_HP_MODEM_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power down Peripherals+ROM domain in HP_MODEM state. + * 0: Power up + * 1: Power down */ #define PMU_HP_MODEM_PD_TOP_PD_EN (BIT(31)) #define PMU_HP_MODEM_PD_TOP_PD_EN_M (PMU_HP_MODEM_PD_TOP_PD_EN_V << PMU_HP_MODEM_PD_TOP_PD_EN_S) @@ -529,11 +622,13 @@ extern "C" { #define PMU_HP_MODEM_PD_TOP_PD_EN_S 31 /** PMU_HP_MODEM_ICG_HP_FUNC_REG register - * need_des + * Control register of HP system peripherals' function clocks in HP_MODEM state */ #define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38) /** PMU_HP_MODEM_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' function clock in HP_MODEM state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_M (PMU_HP_MODEM_DIG_ICG_FUNC_EN_V << PMU_HP_MODEM_DIG_ICG_FUNC_EN_S) @@ -541,11 +636,13 @@ extern "C" { #define PMU_HP_MODEM_DIG_ICG_FUNC_EN_S 0 /** PMU_HP_MODEM_ICG_HP_APB_REG register - * need_des + * Control register of HP system peripherals' APB clocks in HP_MODEM state */ #define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c) /** PMU_HP_MODEM_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' APB clock in HP_MODEM state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU #define PMU_HP_MODEM_DIG_ICG_APB_EN_M (PMU_HP_MODEM_DIG_ICG_APB_EN_V << PMU_HP_MODEM_DIG_ICG_APB_EN_S) @@ -553,11 +650,11 @@ extern "C" { #define PMU_HP_MODEM_DIG_ICG_APB_EN_S 0 /** PMU_HP_MODEM_ICG_MODEM_REG register - * need_des + * Control register of HP system Modem clock gating in HP_MODEM state */ #define PMU_HP_MODEM_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x40) /** PMU_HP_MODEM_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the Modem clock gate in HP_MODEM state. */ #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE 0x00000003U #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_M (PMU_HP_MODEM_DIG_ICG_MODEM_CODE_V << PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S) @@ -565,46 +662,58 @@ extern "C" { #define PMU_HP_MODEM_DIG_ICG_MODEM_CODE_S 30 /** PMU_HP_MODEM_HP_SYS_CNTL_REG register - * need_des + * System control register in HP_MODEM state */ #define PMU_HP_MODEM_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x44) /** PMU_HP_MODEM_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; - * need_des + * Configures whether to enable UART wake-up function in HP_MODEM state. + * 0: Disable wake-up function + * 1: Enable wake-up function */ #define PMU_HP_MODEM_UART_WAKEUP_EN (BIT(24)) #define PMU_HP_MODEM_UART_WAKEUP_EN_M (PMU_HP_MODEM_UART_WAKEUP_EN_V << PMU_HP_MODEM_UART_WAKEUP_EN_S) #define PMU_HP_MODEM_UART_WAKEUP_EN_V 0x00000001U #define PMU_HP_MODEM_UART_WAKEUP_EN_S 24 /** PMU_HP_MODEM_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; - * need_des + * Configures whether to hold LP GPIOs' configuration in HP_MODEM state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_MODEM_LP_PAD_HOLD_ALL (BIT(25)) #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_M (PMU_HP_MODEM_LP_PAD_HOLD_ALL_V << PMU_HP_MODEM_LP_PAD_HOLD_ALL_S) #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_MODEM_LP_PAD_HOLD_ALL_S 25 /** PMU_HP_MODEM_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to hold HP GPIOs' configuration in HP_MODEM state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_MODEM_HP_PAD_HOLD_ALL (BIT(26)) #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_M (PMU_HP_MODEM_HP_PAD_HOLD_ALL_V << PMU_HP_MODEM_HP_PAD_HOLD_ALL_S) #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_MODEM_HP_PAD_HOLD_ALL_S 26 /** PMU_HP_MODEM_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to use Light-sleep mode configuration for GPIO in HP_MODEM state. + * 0: Use normal configuration + * 1: Use Light-sleep mode configuration. For details please refer to Chapter link > Section link. */ #define PMU_HP_MODEM_DIG_PAD_SLP_SEL (BIT(27)) #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_M (PMU_HP_MODEM_DIG_PAD_SLP_SEL_V << PMU_HP_MODEM_DIG_PAD_SLP_SEL_S) #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_V 0x00000001U #define PMU_HP_MODEM_DIG_PAD_SLP_SEL_S 27 /** PMU_HP_MODEM_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to pause watchdog in HP_MODEM state. + * 0: Do not pause + * 1: Pause */ #define PMU_HP_MODEM_DIG_PAUSE_WDT (BIT(28)) #define PMU_HP_MODEM_DIG_PAUSE_WDT_M (PMU_HP_MODEM_DIG_PAUSE_WDT_V << PMU_HP_MODEM_DIG_PAUSE_WDT_S) #define PMU_HP_MODEM_DIG_PAUSE_WDT_V 0x00000001U #define PMU_HP_MODEM_DIG_PAUSE_WDT_S 28 /** PMU_HP_MODEM_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to stall CPU in HP_MODEM state. + * 0: Do not stall + * 1: Stall */ #define PMU_HP_MODEM_DIG_CPU_STALL (BIT(29)) #define PMU_HP_MODEM_DIG_CPU_STALL_M (PMU_HP_MODEM_DIG_CPU_STALL_V << PMU_HP_MODEM_DIG_CPU_STALL_S) @@ -612,11 +721,13 @@ extern "C" { #define PMU_HP_MODEM_DIG_CPU_STALL_S 29 /** PMU_HP_MODEM_HP_CK_POWER_REG register - * need_des + * Control register of clock source's power in HP_MODEM state */ #define PMU_HP_MODEM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x48) /** PMU_HP_MODEM_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable I2C_ISO in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_I2C_ISO_EN (BIT(26)) #define PMU_HP_MODEM_I2C_ISO_EN_M (PMU_HP_MODEM_I2C_ISO_EN_V << PMU_HP_MODEM_I2C_ISO_EN_S) @@ -630,21 +741,27 @@ extern "C" { #define PMU_HP_MODEM_I2C_RETENTION_V 0x00000001U #define PMU_HP_MODEM_I2C_RETENTION_S 27 /** PMU_HP_MODEM_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to enable BB_I2C in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_XPD_BB_I2C (BIT(28)) #define PMU_HP_MODEM_XPD_BB_I2C_M (PMU_HP_MODEM_XPD_BB_I2C_V << PMU_HP_MODEM_XPD_BB_I2C_S) #define PMU_HP_MODEM_XPD_BB_I2C_V 0x00000001U #define PMU_HP_MODEM_XPD_BB_I2C_S 28 /** PMU_HP_MODEM_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to enable BBPLL_I2C in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_XPD_BBPLL_I2C (BIT(29)) #define PMU_HP_MODEM_XPD_BBPLL_I2C_M (PMU_HP_MODEM_XPD_BBPLL_I2C_V << PMU_HP_MODEM_XPD_BBPLL_I2C_S) #define PMU_HP_MODEM_XPD_BBPLL_I2C_V 0x00000001U #define PMU_HP_MODEM_XPD_BBPLL_I2C_S 29 /** PMU_HP_MODEM_XPD_BBPLL : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable BBPLL in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_XPD_BBPLL (BIT(30)) #define PMU_HP_MODEM_XPD_BBPLL_M (PMU_HP_MODEM_XPD_BBPLL_V << PMU_HP_MODEM_XPD_BBPLL_S) @@ -652,32 +769,32 @@ extern "C" { #define PMU_HP_MODEM_XPD_BBPLL_S 30 /** PMU_HP_MODEM_BIAS_REG register - * need_des + * Control register for the operating state of analog circuits (BIAS, DBG, CUR circuits) in HP_MODEM state */ #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) /** PMU_HP_MODEM_XPD_BIAS : R/W; bitpos: [25]; default: 0; - * need_des + * Configures the power supply of BIAS in HP_MODEM state. */ #define PMU_HP_MODEM_XPD_BIAS (BIT(25)) #define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) #define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U #define PMU_HP_MODEM_XPD_BIAS_S 25 /** PMU_HP_MODEM_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; - * need_des + * Configures the degree of attenuation of the analog band gap in HP_MODEM state. */ #define PMU_HP_MODEM_DBG_ATTEN 0x0000000FU #define PMU_HP_MODEM_DBG_ATTEN_M (PMU_HP_MODEM_DBG_ATTEN_V << PMU_HP_MODEM_DBG_ATTEN_S) #define PMU_HP_MODEM_DBG_ATTEN_V 0x0000000FU #define PMU_HP_MODEM_DBG_ATTEN_S 26 /** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; - * need_des + * Configures the power-down current in HP_MODEM state. */ #define PMU_HP_MODEM_PD_CUR (BIT(30)) #define PMU_HP_MODEM_PD_CUR_M (PMU_HP_MODEM_PD_CUR_V << PMU_HP_MODEM_PD_CUR_S) #define PMU_HP_MODEM_PD_CUR_V 0x00000001U #define PMU_HP_MODEM_PD_CUR_S 30 /** PMU_HP_MODEM_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; - * need_des + * Configures the sleep or wakeup status of the BIAS circuit in HP_MODEM state. */ #define PMU_HP_MODEM_BIAS_SLEEP (BIT(31)) #define PMU_HP_MODEM_BIAS_SLEEP_M (PMU_HP_MODEM_BIAS_SLEEP_V << PMU_HP_MODEM_BIAS_SLEEP_S) @@ -685,11 +802,11 @@ extern "C" { #define PMU_HP_MODEM_BIAS_SLEEP_S 31 /** PMU_HP_MODEM_BACKUP_REG register - * need_des + * Data backup control register in HP_MODEM state */ #define PMU_HP_MODEM_BACKUP_REG (DR_REG_PMU_BASE + 0x50) /** PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [5:4]; default: 0; - * need_des + * Configures the ICG during backup process when PMU state switches from HP_SLEEP to HP_MODEM. */ #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) @@ -710,21 +827,35 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U #define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 /** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; - * need_des + * Configures the backup module's function clock source when PMU state switches from HP_SLEEP to HP_MODEM. + * 0: Select XTAL + * 1: Select PLL_CLK + * 2: Select RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 /** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; - * need_des + * Configures the backup direction and link list when PMU state switches switch from HP_SLEEP to HP_MODEM. + * Highest bit: + * 0: From peripheral to memory + * 1: From memory to peripheral + * Lower two bits: + * 0: PAU_LINK_ADDR_0 + * 1: PAU_LINK_ADDR_1 + * 2: PAU_LINK_ADDR_2 + * 3: PAU_LINK_ADDR_3 */ #define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 /** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to enable the backup flow when PMU state switches from HP_SLEEP to HP_MODEM. + * 0: Disable backup + * 1: Enable backup */ #define PMU_HP_SLEEP2MODEM_BACKUP_EN (BIT(29)) #define PMU_HP_SLEEP2MODEM_BACKUP_EN_M (PMU_HP_SLEEP2MODEM_BACKUP_EN_V << PMU_HP_SLEEP2MODEM_BACKUP_EN_S) @@ -732,11 +863,13 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_EN_S 29 /** PMU_HP_MODEM_BACKUP_CLK_REG register - * need_des + * Control register for the operating clocks of the backup module in HP_MODEM state */ #define PMU_HP_MODEM_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x54) /** PMU_HP_MODEM_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; - * need_des + * Configures whether to enable each peripherals' function clock when the target state is HP_MODEM. For details, please refer to Chapter link. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_M (PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_V << PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S) @@ -744,39 +877,49 @@ extern "C" { #define PMU_HP_MODEM_BACKUP_ICG_FUNC_EN_S 0 /** PMU_HP_MODEM_SYSCLK_REG register - * need_des + * Control register of the system clocks in HP_MODEM state */ #define PMU_HP_MODEM_SYSCLK_REG (DR_REG_PMU_BASE + 0x58) /** PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable the clock division for HP_ROOT_CLK in HP_MODEM state. */ #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV (BIT(26)) #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_M (PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V << PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S) #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_V 0x00000001U #define PMU_HP_MODEM_DIG_SYS_CLK_NO_DIV_S 26 /** PMU_HP_MODEM_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to enable HP_ROOT_CLK in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN (BIT(27)) #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_M (PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V << PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S) #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_V 0x00000001U #define PMU_HP_MODEM_ICG_SYS_CLOCK_EN_S 27 /** PMU_HP_MODEM_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to allow PMU to control the clock source in HP_MODEM state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_MODEM_SYS_CLK_SLP_SEL (BIT(28)) #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_M (PMU_HP_MODEM_SYS_CLK_SLP_SEL_V << PMU_HP_MODEM_SYS_CLK_SLP_SEL_S) #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_V 0x00000001U #define PMU_HP_MODEM_SYS_CLK_SLP_SEL_S 28 /** PMU_HP_MODEM_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to allow PMU to control the clock gating in HP_MODEM state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_MODEM_ICG_SLP_SEL (BIT(29)) #define PMU_HP_MODEM_ICG_SLP_SEL_M (PMU_HP_MODEM_ICG_SLP_SEL_V << PMU_HP_MODEM_ICG_SLP_SEL_S) #define PMU_HP_MODEM_ICG_SLP_SEL_V 0x00000001U #define PMU_HP_MODEM_ICG_SLP_SEL_S 29 /** PMU_HP_MODEM_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the source of HP_ROOT_CLK in HP_MODEM state. + * 0: XTAL + * 1: PLL_CLK + * 2: RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_MODEM_DIG_SYS_CLK_SEL 0x00000003U #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_M (PMU_HP_MODEM_DIG_SYS_CLK_SEL_V << PMU_HP_MODEM_DIG_SYS_CLK_SEL_S) @@ -784,7 +927,7 @@ extern "C" { #define PMU_HP_MODEM_DIG_SYS_CLK_SEL_S 30 /** PMU_HP_MODEM_HP_REGULATOR0_REG register - * need_des + * Control register of HP regulators' power in HP_MODEM state, controlling all settings except drive */ #define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c) /** PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [15]; default: 1; @@ -795,42 +938,48 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_SLP_CONNECT_EN_S 15 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; - * need_des + * Configures whether to enable the secondary regulator powering the HP memory in HP domain in HP_MODEM state. + * 0: Disable the regulator + * 1: Enable the regulator */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; - * need_des + * Configures whether to enable the secondary regulator powering the logic circuit in HP domain in HP_MODEM state. + * 0: Disable the regulator + * 1: Enable the regulator */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17 /** PMU_HP_MODEM_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; - * need_des + * Configures whether to enable the main HP regulator in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18)) #define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S) #define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U #define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18 /** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the HP memory in HP_MODEM state, adjusting its output voltage. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19 /** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the logic circuits in HP domain in HP_MODEM state, adjusting its output voltage. */ #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S) #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU #define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 /** PMU_HP_MODEM_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; - * need_des + * Configures the DREG value of the main HP regulator in HP_MODEM state, adjusting its output voltage. */ #define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_DBIAS_S) @@ -838,11 +987,11 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_DBIAS_S 27 /** PMU_HP_MODEM_HP_REGULATOR1_REG register - * need_des + * Control register of HP regulators' power in HP_MODEM state, controlling drive settings */ #define PMU_HP_MODEM_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x60) /** PMU_HP_MODEM_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; - * need_des + * Configures the drive strength of the main HP regulator in HP_MODEM state. */ #define PMU_HP_MODEM_HP_REGULATOR_DRV_B 0x00FFFFFFU #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_M (PMU_HP_MODEM_HP_REGULATOR_DRV_B_V << PMU_HP_MODEM_HP_REGULATOR_DRV_B_S) @@ -850,11 +999,13 @@ extern "C" { #define PMU_HP_MODEM_HP_REGULATOR_DRV_B_S 8 /** PMU_HP_MODEM_XTAL_REG register - * need_des + * XTAL_CLK power control register in HP_MODEM state */ #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) /** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; - * need_des + * Configures whether to enable XTAL_CLK in HP_MODEM state. + * 0: Disable + * 1: Enable */ #define PMU_HP_MODEM_XPD_XTAL (BIT(31)) #define PMU_HP_MODEM_XPD_XTAL_M (PMU_HP_MODEM_XPD_XTAL_V << PMU_HP_MODEM_XPD_XTAL_S) @@ -862,18 +1013,22 @@ extern "C" { #define PMU_HP_MODEM_XPD_XTAL_S 31 /** PMU_HP_SLEEP_DIG_POWER_REG register - * need_des + * Configuration register of digital power domains in HP_SLEEP state */ #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) /** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; - * need_des + * Configures whether to power down external flash in HP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) #define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) #define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; - * need_des + * Configures whether to put Internal SRAM$x ($x= 0, 1, 2) into Deep-sleep mode in HP_SLEEP state. + * 0: Do not put Internal SRAM into Deep-sleep + * 1: Put Internal SRAM into Deep-sleep */ #define PMU_HP_SLEEP_HP_MEM_DSLP (BIT(22)) #define PMU_HP_SLEEP_HP_MEM_DSLP_M (PMU_HP_SLEEP_HP_MEM_DSLP_V << PMU_HP_SLEEP_HP_MEM_DSLP_S) @@ -887,7 +1042,9 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x0000000FU #define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23 /** PMU_HP_SLEEP_PD_HP_WIFI_PD_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to power down MODEM domain in HP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN (BIT(27)) #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) @@ -901,21 +1058,27 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to power down CPU domain in HP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29)) #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29 /** PMU_HP_SLEEP_PD_HP_AON_PD_EN : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to power down Modem Power domain in HP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_PD_HP_AON_PD_EN (BIT(30)) #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_M (PMU_HP_SLEEP_PD_HP_AON_PD_EN_V << PMU_HP_SLEEP_PD_HP_AON_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_AON_PD_EN_S 30 /** PMU_HP_SLEEP_PD_TOP_PD_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power down Peripherals+ROM domain in HP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_PD_TOP_PD_EN (BIT(31)) #define PMU_HP_SLEEP_PD_TOP_PD_EN_M (PMU_HP_SLEEP_PD_TOP_PD_EN_V << PMU_HP_SLEEP_PD_TOP_PD_EN_S) @@ -923,11 +1086,13 @@ extern "C" { #define PMU_HP_SLEEP_PD_TOP_PD_EN_S 31 /** PMU_HP_SLEEP_ICG_HP_FUNC_REG register - * need_des + * Control register of HP system peripherals' function clocks in HP_SLEEP state */ #define PMU_HP_SLEEP_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x6c) /** PMU_HP_SLEEP_DIG_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' function clock in HP_SLEEP state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_M (PMU_HP_SLEEP_DIG_ICG_FUNC_EN_V << PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S) @@ -935,11 +1100,13 @@ extern "C" { #define PMU_HP_SLEEP_DIG_ICG_FUNC_EN_S 0 /** PMU_HP_SLEEP_ICG_HP_APB_REG register - * need_des + * Control register of HP system peripherals' APB clocks in HP_SLEEP state */ #define PMU_HP_SLEEP_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x70) /** PMU_HP_SLEEP_DIG_ICG_APB_EN : R/W; bitpos: [31:0]; default: 4294967295; - * need_des + * Configures whether to enable HP system peripherals' APB clock in HP_SLEEP state. For detailed configuration please see Chapter link > Table link. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_DIG_ICG_APB_EN 0xFFFFFFFFU #define PMU_HP_SLEEP_DIG_ICG_APB_EN_M (PMU_HP_SLEEP_DIG_ICG_APB_EN_V << PMU_HP_SLEEP_DIG_ICG_APB_EN_S) @@ -947,11 +1114,11 @@ extern "C" { #define PMU_HP_SLEEP_DIG_ICG_APB_EN_S 0 /** PMU_HP_SLEEP_ICG_MODEM_REG register - * need_des + * Control register of HP system Modem clock gating in HP_SLEEP state */ #define PMU_HP_SLEEP_ICG_MODEM_REG (DR_REG_PMU_BASE + 0x74) /** PMU_HP_SLEEP_DIG_ICG_MODEM_CODE : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the Modem clock gate in HP_SLEEP state. */ #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE 0x00000003U #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_M (PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_V << PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S) @@ -959,46 +1126,58 @@ extern "C" { #define PMU_HP_SLEEP_DIG_ICG_MODEM_CODE_S 30 /** PMU_HP_SLEEP_HP_SYS_CNTL_REG register - * need_des + * System control register in HP_SLEEP state */ #define PMU_HP_SLEEP_HP_SYS_CNTL_REG (DR_REG_PMU_BASE + 0x78) /** PMU_HP_SLEEP_UART_WAKEUP_EN : R/W; bitpos: [24]; default: 0; - * need_des + * Configures whether to enable UART wake-up function in HP_SLEEP state. + * 0: Disable wake-up function + * 1: Enable wake-up function */ #define PMU_HP_SLEEP_UART_WAKEUP_EN (BIT(24)) #define PMU_HP_SLEEP_UART_WAKEUP_EN_M (PMU_HP_SLEEP_UART_WAKEUP_EN_V << PMU_HP_SLEEP_UART_WAKEUP_EN_S) #define PMU_HP_SLEEP_UART_WAKEUP_EN_V 0x00000001U #define PMU_HP_SLEEP_UART_WAKEUP_EN_S 24 /** PMU_HP_SLEEP_LP_PAD_HOLD_ALL : R/W; bitpos: [25]; default: 0; - * need_des + * Configures whether to hold LP GPIOs' configuration in HP_SLEEP state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL (BIT(25)) #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S) #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_SLEEP_LP_PAD_HOLD_ALL_S 25 /** PMU_HP_SLEEP_HP_PAD_HOLD_ALL : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to hold HP GPIOs' configuration in HP_SLEEP state. + * 0: Do not hold + * 1: Hold */ #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL (BIT(26)) #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_M (PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V << PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S) #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_V 0x00000001U #define PMU_HP_SLEEP_HP_PAD_HOLD_ALL_S 26 /** PMU_HP_SLEEP_DIG_PAD_SLP_SEL : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to use Light-sleep mode configuration for GPIO in HP_SLEEP state. + * 0: Use normal configuration + * 1: Use Light-sleep mode configuration. For details please refer to Chapter link > Section link. */ #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL (BIT(27)) #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_M (PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V << PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S) #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_V 0x00000001U #define PMU_HP_SLEEP_DIG_PAD_SLP_SEL_S 27 /** PMU_HP_SLEEP_DIG_PAUSE_WDT : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to pause watchdog in HP_SLEEP state. + * 0: Do not pause + * 1: Pause */ #define PMU_HP_SLEEP_DIG_PAUSE_WDT (BIT(28)) #define PMU_HP_SLEEP_DIG_PAUSE_WDT_M (PMU_HP_SLEEP_DIG_PAUSE_WDT_V << PMU_HP_SLEEP_DIG_PAUSE_WDT_S) #define PMU_HP_SLEEP_DIG_PAUSE_WDT_V 0x00000001U #define PMU_HP_SLEEP_DIG_PAUSE_WDT_S 28 /** PMU_HP_SLEEP_DIG_CPU_STALL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to stall CPU in HP_SLEEP state. + * 0: Do not stall + * 1: Stall */ #define PMU_HP_SLEEP_DIG_CPU_STALL (BIT(29)) #define PMU_HP_SLEEP_DIG_CPU_STALL_M (PMU_HP_SLEEP_DIG_CPU_STALL_V << PMU_HP_SLEEP_DIG_CPU_STALL_S) @@ -1006,11 +1185,13 @@ extern "C" { #define PMU_HP_SLEEP_DIG_CPU_STALL_S 29 /** PMU_HP_SLEEP_HP_CK_POWER_REG register - * need_des + * Control register of clock source's power in HP_SLEEP state */ #define PMU_HP_SLEEP_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0x7c) /** PMU_HP_SLEEP_I2C_ISO_EN : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable I2C_ISO in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_I2C_ISO_EN (BIT(26)) #define PMU_HP_SLEEP_I2C_ISO_EN_M (PMU_HP_SLEEP_I2C_ISO_EN_V << PMU_HP_SLEEP_I2C_ISO_EN_S) @@ -1024,21 +1205,27 @@ extern "C" { #define PMU_HP_SLEEP_I2C_RETENTION_V 0x00000001U #define PMU_HP_SLEEP_I2C_RETENTION_S 27 /** PMU_HP_SLEEP_XPD_BB_I2C : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to enable BB_I2C in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_XPD_BB_I2C (BIT(28)) #define PMU_HP_SLEEP_XPD_BB_I2C_M (PMU_HP_SLEEP_XPD_BB_I2C_V << PMU_HP_SLEEP_XPD_BB_I2C_S) #define PMU_HP_SLEEP_XPD_BB_I2C_V 0x00000001U #define PMU_HP_SLEEP_XPD_BB_I2C_S 28 /** PMU_HP_SLEEP_XPD_BBPLL_I2C : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to enable BBPLL_I2C in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_XPD_BBPLL_I2C (BIT(29)) #define PMU_HP_SLEEP_XPD_BBPLL_I2C_M (PMU_HP_SLEEP_XPD_BBPLL_I2C_V << PMU_HP_SLEEP_XPD_BBPLL_I2C_S) #define PMU_HP_SLEEP_XPD_BBPLL_I2C_V 0x00000001U #define PMU_HP_SLEEP_XPD_BBPLL_I2C_S 29 /** PMU_HP_SLEEP_XPD_BBPLL : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable BBPLL in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_XPD_BBPLL (BIT(30)) #define PMU_HP_SLEEP_XPD_BBPLL_M (PMU_HP_SLEEP_XPD_BBPLL_V << PMU_HP_SLEEP_XPD_BBPLL_S) @@ -1046,32 +1233,32 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BBPLL_S 30 /** PMU_HP_SLEEP_BIAS_REG register - * need_des + * Control register for operation state of analog circuits (BIAS, DBG, CUR) in HP_SLEEP */ #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) /** PMU_HP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; - * need_des + * Configures the power supply of BIAS in HP_SLEEP state. */ #define PMU_HP_SLEEP_XPD_BIAS (BIT(25)) #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_HP_SLEEP_XPD_BIAS_S 25 /** PMU_HP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; - * need_des + * Configures the degree of attenuation of the analog band gap in HP_SLEEP state. */ #define PMU_HP_SLEEP_DBG_ATTEN 0x0000000FU #define PMU_HP_SLEEP_DBG_ATTEN_M (PMU_HP_SLEEP_DBG_ATTEN_V << PMU_HP_SLEEP_DBG_ATTEN_S) #define PMU_HP_SLEEP_DBG_ATTEN_V 0x0000000FU #define PMU_HP_SLEEP_DBG_ATTEN_S 26 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; - * need_des + * Configures the power-down current in HP_SLEEP state. */ #define PMU_HP_SLEEP_PD_CUR (BIT(30)) #define PMU_HP_SLEEP_PD_CUR_M (PMU_HP_SLEEP_PD_CUR_V << PMU_HP_SLEEP_PD_CUR_S) #define PMU_HP_SLEEP_PD_CUR_V 0x00000001U #define PMU_HP_SLEEP_PD_CUR_S 30 /** PMU_HP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; - * need_des + * Configures the sleep or wakeup status of the BIAS circuit in HP_SLEEP state. */ #define PMU_HP_SLEEP_BIAS_SLEEP (BIT(31)) #define PMU_HP_SLEEP_BIAS_SLEEP_M (PMU_HP_SLEEP_BIAS_SLEEP_V << PMU_HP_SLEEP_BIAS_SLEEP_S) @@ -1079,18 +1266,18 @@ extern "C" { #define PMU_HP_SLEEP_BIAS_SLEEP_S 31 /** PMU_HP_SLEEP_BACKUP_REG register - * need_des + * Data backup control register in HP_SLEEP state */ #define PMU_HP_SLEEP_BACKUP_REG (DR_REG_PMU_BASE + 0x84) /** PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [7:6]; default: 0; - * need_des + * Configures the ICG during backup process when PMU state switches from HP_MODEM to HP_SLEEP. */ #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_S 6 /** PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE : R/W; bitpos: [9:8]; default: 0; - * need_des + * Configures the ICG during backup process when PMU state switches from HP_ACTIVE to HP_SLEEP. */ #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) @@ -1118,42 +1305,58 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U #define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * need_des + * Configures the backup module's function clock source when PMU state switches from HP_MODEM to HP_SLEEP. + * 0: Select XTAL + * 1: Select PLL_CLK + * 2: Select RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL_S 16 /** PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [19:18]; default: 0; - * need_des + * Configures the backup module function clock source when PMU state switches from HP_ACTIVE to HP_SLEEP. The configuration is the same as the register above. */ #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 /** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; - * need_des + * Configures the backup direction and link list when PMU state switches switch from HP_MODEM to HP_SLEEP. + * Highest bit: + * 0: From peripheral to memory + * 1: From memory to peripheral + * Lower two bits: + * 0: PAU_LINK_ADDR_0 + * 1: PAU_LINK_ADDR_1 + * 2: PAU_LINK_ADDR_2 + * 3: PAU_LINK_ADDR_3 */ #define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 /** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; - * need_des + * Configures the backup direction and link list when PMU state switches from HP_ACTIVE to HP_MODEM. The configuration is the same as the register above. */ #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable the backup flow when PMU state switches from HP_MODEM to HP_SLEEP. + * 0: Disable backup + * 1: Enable backup */ #define PMU_HP_MODEM2SLEEP_BACKUP_EN (BIT(30)) #define PMU_HP_MODEM2SLEEP_BACKUP_EN_M (PMU_HP_MODEM2SLEEP_BACKUP_EN_V << PMU_HP_MODEM2SLEEP_BACKUP_EN_S) #define PMU_HP_MODEM2SLEEP_BACKUP_EN_V 0x00000001U #define PMU_HP_MODEM2SLEEP_BACKUP_EN_S 30 /** PMU_HP_ACTIVE2SLEEP_BACKUP_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to enable the backup flow when PMU state switches from HP_ACTIVE to HP_SLEEP. + * 0: Disable backup + * 1: Enable backup */ #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN (BIT(31)) #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_M (PMU_HP_ACTIVE2SLEEP_BACKUP_EN_V << PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S) @@ -1161,11 +1364,13 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_EN_S 31 /** PMU_HP_SLEEP_BACKUP_CLK_REG register - * need_des + * Control register for the operating clocks of the backup module in HP_SLEEP state */ #define PMU_HP_SLEEP_BACKUP_CLK_REG (DR_REG_PMU_BASE + 0x88) /** PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN : R/W; bitpos: [31:0]; default: 0; - * need_des + * Configures whether to enable each peripherals' function clock when the target state is HP_SLEEP. For details, please refer to Chapter link. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN 0xFFFFFFFFU #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_M (PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_V << PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S) @@ -1173,39 +1378,49 @@ extern "C" { #define PMU_HP_SLEEP_BACKUP_ICG_FUNC_EN_S 0 /** PMU_HP_SLEEP_SYSCLK_REG register - * need_des + * Control register of the system clocks in HP_SLEEP state */ #define PMU_HP_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0x8c) /** PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV : R/W; bitpos: [26]; default: 0; - * need_des + * Configures whether to enable the clock division for HP_ROOT_CLK in HP_SLEEP state. */ #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV (BIT(26)) #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_M (PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V << PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S) #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_V 0x00000001U #define PMU_HP_SLEEP_DIG_SYS_CLK_NO_DIV_S 26 /** PMU_HP_SLEEP_ICG_SYS_CLOCK_EN : R/W; bitpos: [27]; default: 0; - * need_des + * Configures whether to enable HP_ROOT_CLK in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN (BIT(27)) #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_M (PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V << PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S) #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_V 0x00000001U #define PMU_HP_SLEEP_ICG_SYS_CLOCK_EN_S 27 /** PMU_HP_SLEEP_SYS_CLK_SLP_SEL : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to allow PMU to control the clock source in HP_SLEEP state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL (BIT(28)) #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_M (PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V << PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S) #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_V 0x00000001U #define PMU_HP_SLEEP_SYS_CLK_SLP_SEL_S 28 /** PMU_HP_SLEEP_ICG_SLP_SEL : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to allow PMU to control the clock gating in HP_SLEEP state. + * 0: Controlled by PCR registers + * 1: Controlled by PMU */ #define PMU_HP_SLEEP_ICG_SLP_SEL (BIT(29)) #define PMU_HP_SLEEP_ICG_SLP_SEL_M (PMU_HP_SLEEP_ICG_SLP_SEL_V << PMU_HP_SLEEP_ICG_SLP_SEL_S) #define PMU_HP_SLEEP_ICG_SLP_SEL_V 0x00000001U #define PMU_HP_SLEEP_ICG_SLP_SEL_S 29 /** PMU_HP_SLEEP_DIG_SYS_CLK_SEL : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures the source of HP_ROOT_CLK in HP_SLEEP state. + * 0: XTAL + * 1: PLL_CLK + * 2: RC_FAST_CLK + * 3: Invalid value */ #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL 0x00000003U #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_M (PMU_HP_SLEEP_DIG_SYS_CLK_SEL_V << PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S) @@ -1213,7 +1428,7 @@ extern "C" { #define PMU_HP_SLEEP_DIG_SYS_CLK_SEL_S 30 /** PMU_HP_SLEEP_HP_REGULATOR0_REG register - * need_des + * Control register of HP regulators' power in HP_SLEEP state, controlling all settings except drive */ #define PMU_HP_SLEEP_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x90) /** PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN : R/W; bitpos: [15]; default: 1; @@ -1224,42 +1439,48 @@ extern "C" { #define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_V 0x00000001U #define PMU_HP_SLEEP_HP_REGULATOR_SLP_CONNECT_EN_S 15 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD : R/W; bitpos: [16]; default: 1; - * need_des + * Configures whether to enable the secondary HP regulator powering the HP memory in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD (BIT(16)) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_S 16 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD : R/W; bitpos: [17]; default: 1; - * need_des + * Configures whether to enable the secondary HP regulator powering the logic circuits in HP domain in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17)) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_S 17 /** PMU_HP_SLEEP_HP_REGULATOR_XPD : R/W; bitpos: [18]; default: 1; - * need_des + * Configures whether to enable the main HP regulator in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_HP_REGULATOR_XPD (BIT(18)) #define PMU_HP_SLEEP_HP_REGULATOR_XPD_M (PMU_HP_SLEEP_HP_REGULATOR_XPD_V << PMU_HP_SLEEP_HP_REGULATOR_XPD_S) #define PMU_HP_SLEEP_HP_REGULATOR_XPD_V 0x00000001U #define PMU_HP_SLEEP_HP_REGULATOR_XPD_S 18 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS : R/W; bitpos: [22:19]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the HP memory in HP_SLEEP state, adjusting its output voltage. */ #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_S 19 /** PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS : R/W; bitpos: [26:23]; default: 12; - * need_des + * Configures the DREG value of the secondary HP regulator powering the logic circuits in HP domain in HP_SLEEP state, adjusting its output voltage. */ #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S) #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23 /** PMU_HP_SLEEP_HP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; - * need_des + * Configures the DREG value of the main HP regulator in HP_SLEEP state, adjusting its output voltage. */ #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS 0x0000001FU #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_HP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S) @@ -1267,11 +1488,11 @@ extern "C" { #define PMU_HP_SLEEP_HP_REGULATOR_DBIAS_S 27 /** PMU_HP_SLEEP_HP_REGULATOR1_REG register - * need_des + * Control register of HP regulators' power in HP_SLEEP state, controlling drive settings */ #define PMU_HP_SLEEP_HP_REGULATOR1_REG (DR_REG_PMU_BASE + 0x94) /** PMU_HP_SLEEP_HP_REGULATOR_DRV_B : R/W; bitpos: [31:8]; default: 0; - * need_des + * Configures the drive strength of the main HP regulator in HP_SLEEP state. */ #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B 0x00FFFFFFU #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_HP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S) @@ -1279,11 +1500,13 @@ extern "C" { #define PMU_HP_SLEEP_HP_REGULATOR_DRV_B_S 8 /** PMU_HP_SLEEP_XTAL_REG register - * need_des + * XTAL_CLK power control register in HP_SLEEP state */ #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; - * need_des + * Configures whether to enable XTAL_CLK in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_XPD_XTAL (BIT(31)) #define PMU_HP_SLEEP_XPD_XTAL_M (PMU_HP_SLEEP_XPD_XTAL_V << PMU_HP_SLEEP_XPD_XTAL_S) @@ -1291,32 +1514,36 @@ extern "C" { #define PMU_HP_SLEEP_XPD_XTAL_S 31 /** PMU_HP_SLEEP_LP_REGULATOR0_REG register - * need_des + * LP regulator power control register in HP_SLEEP state, controlling all settings except drive */ #define PMU_HP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x9c) /** PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; - * need_des + * Configures whether to enable the secondary LP regulator in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U #define PMU_HP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 /** PMU_HP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; - * need_des + * Configures whether to enable the main LP regulator in HP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_LP_REGULATOR_XPD (BIT(22)) #define PMU_HP_SLEEP_LP_REGULATOR_XPD_M (PMU_HP_SLEEP_LP_REGULATOR_XPD_V << PMU_HP_SLEEP_LP_REGULATOR_XPD_S) #define PMU_HP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U #define PMU_HP_SLEEP_LP_REGULATOR_XPD_S 22 /** PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; - * need_des + * Configures the DREG value of the secondary LP regulator in HP_SLEEP state, adjusting its output voltage. */ #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 /** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; - * need_des + * Configures the DREG value of the main LP regulator in HP_SLEEP state, adjusting its output voltage. */ #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S) @@ -1324,11 +1551,11 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S 27 /** PMU_HP_SLEEP_LP_REGULATOR1_REG register - * need_des + * LP regulator power control register in HP_SLEEP state, controlling drive settings */ #define PMU_HP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xa0) /** PMU_HP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; - * need_des + * Configures the drive strength of the main LP regulator in HP_SLEEP state. */ #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S) @@ -1336,18 +1563,22 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 /** PMU_HP_SLEEP_LP_DIG_POWER_REG register - * need_des + * Configuration register of digital power domains in LP system in HP_SLEEP state */ #define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) /** PMU_HP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable Memory Deep-sleep mode for the 320 KB SRAM in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Disable + * 1: Enable */ #define PMU_HP_SLEEP_LP_MEM_DSLP (BIT(30)) #define PMU_HP_SLEEP_LP_MEM_DSLP_M (PMU_HP_SLEEP_LP_MEM_DSLP_V << PMU_HP_SLEEP_LP_MEM_DSLP_S) #define PMU_HP_SLEEP_LP_MEM_DSLP_V 0x00000001U #define PMU_HP_SLEEP_LP_MEM_DSLP_S 30 /** PMU_HP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power down Peripherals+ROM domain in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Power up + * 1: Power down */ #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S) @@ -1355,32 +1586,40 @@ extern "C" { #define PMU_HP_SLEEP_PD_LP_PERI_PD_EN_S 31 /** PMU_HP_SLEEP_LP_CK_POWER_REG register - * need_des + * Low-speed clock power control register in HP_ACTIVE, HP_MODEM and HP_SLEEP states */ #define PMU_HP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xac) /** PMU_HP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to power up XTAL32K_CLK in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Power down + * 1: Power up */ #define PMU_HP_SLEEP_XPD_XTAL32K (BIT(28)) #define PMU_HP_SLEEP_XPD_XTAL32K_M (PMU_HP_SLEEP_XPD_XTAL32K_V << PMU_HP_SLEEP_XPD_XTAL32K_S) #define PMU_HP_SLEEP_XPD_XTAL32K_V 0x00000001U #define PMU_HP_SLEEP_XPD_XTAL32K_S 28 /** PMU_HP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to power up RC32K_CLK in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Power down + * 1: Power up */ #define PMU_HP_SLEEP_XPD_RC32K (BIT(29)) #define PMU_HP_SLEEP_XPD_RC32K_M (PMU_HP_SLEEP_XPD_RC32K_V << PMU_HP_SLEEP_XPD_RC32K_S) #define PMU_HP_SLEEP_XPD_RC32K_V 0x00000001U #define PMU_HP_SLEEP_XPD_RC32K_S 29 /** PMU_HP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; - * need_des + * Configures whether to power up RC_FAST_CLK in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Power down + * 1: Power up */ #define PMU_HP_SLEEP_XPD_FOSC_CLK (BIT(30)) #define PMU_HP_SLEEP_XPD_FOSC_CLK_M (PMU_HP_SLEEP_XPD_FOSC_CLK_V << PMU_HP_SLEEP_XPD_FOSC_CLK_S) #define PMU_HP_SLEEP_XPD_FOSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_XPD_FOSC_CLK_S 30 /** PMU_HP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power up SOSC_CLK in HP_ACTIVE, HP_MODEM and HP_SLEEP states. + * 0: Power down + * 1: Power up */ #define PMU_HP_SLEEP_PD_OSC_CLK (BIT(31)) #define PMU_HP_SLEEP_PD_OSC_CLK_M (PMU_HP_SLEEP_PD_OSC_CLK_V << PMU_HP_SLEEP_PD_OSC_CLK_S) @@ -1388,32 +1627,36 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 /** PMU_LP_SLEEP_LP_REGULATOR0_REG register - * need_des + * LP regulator power control register in LP_SLEEP state, controlling all settings except drive */ #define PMU_LP_SLEEP_LP_REGULATOR0_REG (DR_REG_PMU_BASE + 0xb4) /** PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD : R/W; bitpos: [21]; default: 1; - * need_des + * Configures whether to enable the secondary LP regulator in LP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD (BIT(21)) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_V 0x00000001U #define PMU_LP_SLEEP_LP_REGULATOR_SLP_XPD_S 21 /** PMU_LP_SLEEP_LP_REGULATOR_XPD : R/W; bitpos: [22]; default: 1; - * need_des + * Configures whether to enable the main LP regulator in LP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_LP_SLEEP_LP_REGULATOR_XPD (BIT(22)) #define PMU_LP_SLEEP_LP_REGULATOR_XPD_M (PMU_LP_SLEEP_LP_REGULATOR_XPD_V << PMU_LP_SLEEP_LP_REGULATOR_XPD_S) #define PMU_LP_SLEEP_LP_REGULATOR_XPD_V 0x00000001U #define PMU_LP_SLEEP_LP_REGULATOR_XPD_S 22 /** PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS : R/W; bitpos: [26:23]; default: 12; - * need_des + * Configures the DREG value of the secondary LP regulator in LP_SLEEP state, adjusting its output voltage. */ #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 /** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 24; - * need_des + * Configures the DREG value of the main LP regulator in LP_SLEEP state, adjusting its output voltage. */ #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S) @@ -1421,11 +1664,11 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS_S 27 /** PMU_LP_SLEEP_LP_REGULATOR1_REG register - * need_des + * LP regulator power control register in LP_SLEEP state, controlling drive settings */ #define PMU_LP_SLEEP_LP_REGULATOR1_REG (DR_REG_PMU_BASE + 0xb8) /** PMU_LP_SLEEP_LP_REGULATOR_DRV_B : R/W; bitpos: [31:28]; default: 0; - * need_des + * Configures the drive strength of the main LP regulator in LP_SLEEP state. */ #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_M (PMU_LP_SLEEP_LP_REGULATOR_DRV_B_V << PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S) @@ -1433,11 +1676,13 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_DRV_B_S 28 /** PMU_LP_SLEEP_XTAL_REG register - * need_des + * XTAL_CLK power control register in LP_SLEEP state */ #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; - * need_des + * Configures whether to enable XTAL_CLK in LP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_LP_SLEEP_XPD_XTAL (BIT(31)) #define PMU_LP_SLEEP_XPD_XTAL_M (PMU_LP_SLEEP_XPD_XTAL_V << PMU_LP_SLEEP_XPD_XTAL_S) @@ -1445,18 +1690,22 @@ extern "C" { #define PMU_LP_SLEEP_XPD_XTAL_S 31 /** PMU_LP_SLEEP_LP_DIG_POWER_REG register - * need_des + * Configuration register of digital power domains in LP system in LP_SLEEP state */ #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) /** PMU_LP_SLEEP_LP_MEM_DSLP : R/W; bitpos: [30]; default: 0; - * need_des + * Configures whether to enable Memory Deep-sleep mode for the 320 KB SRAM in LP_SLEEP state. + * 0: Disable + * 1: Enable */ #define PMU_LP_SLEEP_LP_MEM_DSLP (BIT(30)) #define PMU_LP_SLEEP_LP_MEM_DSLP_M (PMU_LP_SLEEP_LP_MEM_DSLP_V << PMU_LP_SLEEP_LP_MEM_DSLP_S) #define PMU_LP_SLEEP_LP_MEM_DSLP_V 0x00000001U #define PMU_LP_SLEEP_LP_MEM_DSLP_S 30 /** PMU_LP_SLEEP_PD_LP_PERI_PD_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power down the Peripherals+ROM domain in LP_SLEEP state. + * 0: Power up + * 1: Power down */ #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN (BIT(31)) #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_M (PMU_LP_SLEEP_PD_LP_PERI_PD_EN_V << PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S) @@ -1464,32 +1713,40 @@ extern "C" { #define PMU_LP_SLEEP_PD_LP_PERI_PD_EN_S 31 /** PMU_LP_SLEEP_LP_CK_POWER_REG register - * need_des + * Low-speed clock power control register in LP_SLEEP state */ #define PMU_LP_SLEEP_LP_CK_POWER_REG (DR_REG_PMU_BASE + 0xc4) /** PMU_LP_SLEEP_XPD_XTAL32K : R/W; bitpos: [28]; default: 0; - * need_des + * Configures whether to power up XTAL32K_CLK in LP_SLEEP state. + * 0: Power down + * 1: Power up */ #define PMU_LP_SLEEP_XPD_XTAL32K (BIT(28)) #define PMU_LP_SLEEP_XPD_XTAL32K_M (PMU_LP_SLEEP_XPD_XTAL32K_V << PMU_LP_SLEEP_XPD_XTAL32K_S) #define PMU_LP_SLEEP_XPD_XTAL32K_V 0x00000001U #define PMU_LP_SLEEP_XPD_XTAL32K_S 28 /** PMU_LP_SLEEP_XPD_RC32K : R/W; bitpos: [29]; default: 0; - * need_des + * Configures whether to power up RC32K_CLK in LP_SLEEP state. + * 0: Power down + * 1: Power up */ #define PMU_LP_SLEEP_XPD_RC32K (BIT(29)) #define PMU_LP_SLEEP_XPD_RC32K_M (PMU_LP_SLEEP_XPD_RC32K_V << PMU_LP_SLEEP_XPD_RC32K_S) #define PMU_LP_SLEEP_XPD_RC32K_V 0x00000001U #define PMU_LP_SLEEP_XPD_RC32K_S 29 /** PMU_LP_SLEEP_XPD_FOSC_CLK : R/W; bitpos: [30]; default: 1; - * need_des + * Configures whether to power up RC_FAST_CLK in LP_SLEEP state. + * 0: Power down + * 1: Power up */ #define PMU_LP_SLEEP_XPD_FOSC_CLK (BIT(30)) #define PMU_LP_SLEEP_XPD_FOSC_CLK_M (PMU_LP_SLEEP_XPD_FOSC_CLK_V << PMU_LP_SLEEP_XPD_FOSC_CLK_S) #define PMU_LP_SLEEP_XPD_FOSC_CLK_V 0x00000001U #define PMU_LP_SLEEP_XPD_FOSC_CLK_S 30 /** PMU_LP_SLEEP_PD_OSC_CLK : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to power up SOSC_CLK in LP_SLEEP state. + * 0: Power down + * 1: Power up */ #define PMU_LP_SLEEP_PD_OSC_CLK (BIT(31)) #define PMU_LP_SLEEP_PD_OSC_CLK_M (PMU_LP_SLEEP_PD_OSC_CLK_V << PMU_LP_SLEEP_PD_OSC_CLK_S) @@ -1497,32 +1754,32 @@ extern "C" { #define PMU_LP_SLEEP_PD_OSC_CLK_S 31 /** PMU_LP_SLEEP_BIAS_REG register - * need_des + * Control register for operation state of analog circuits (BIAS, DBG, CUR) in LP_SLEEP */ #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; - * need_des + * Configures the power supply of BIAS in LP_SLEEP state. */ #define PMU_LP_SLEEP_XPD_BIAS (BIT(25)) #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_LP_SLEEP_XPD_BIAS_S 25 /** PMU_LP_SLEEP_DBG_ATTEN : R/W; bitpos: [29:26]; default: 0; - * need_des + * Configures the degree of attenuation of the analog band gap in LP_SLEEP state. */ #define PMU_LP_SLEEP_DBG_ATTEN 0x0000000FU #define PMU_LP_SLEEP_DBG_ATTEN_M (PMU_LP_SLEEP_DBG_ATTEN_V << PMU_LP_SLEEP_DBG_ATTEN_S) #define PMU_LP_SLEEP_DBG_ATTEN_V 0x0000000FU #define PMU_LP_SLEEP_DBG_ATTEN_S 26 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; - * need_des + * Configures the power-down current in LP_SLEEP state. */ #define PMU_LP_SLEEP_PD_CUR (BIT(30)) #define PMU_LP_SLEEP_PD_CUR_M (PMU_LP_SLEEP_PD_CUR_V << PMU_LP_SLEEP_PD_CUR_S) #define PMU_LP_SLEEP_PD_CUR_V 0x00000001U #define PMU_LP_SLEEP_PD_CUR_S 30 /** PMU_LP_SLEEP_BIAS_SLEEP : R/W; bitpos: [31]; default: 0; - * need_des + * Configures the sleep or wakeup status of the BIAS circuit in LP_SLEEP state. */ #define PMU_LP_SLEEP_BIAS_SLEEP (BIT(31)) #define PMU_LP_SLEEP_BIAS_SLEEP_M (PMU_LP_SLEEP_BIAS_SLEEP_V << PMU_LP_SLEEP_BIAS_SLEEP_S) @@ -1530,102 +1787,130 @@ extern "C" { #define PMU_LP_SLEEP_BIAS_SLEEP_S 31 /** PMU_IMM_HP_CK_POWER_REG register - * need_des + * Software-controlled enable signal for HP clock power on/off */ #define PMU_IMM_HP_CK_POWER_REG (DR_REG_PMU_BASE + 0xcc) /** PMU_TIE_LOW_GLOBAL_BBPLL_ICG : WT; bitpos: [0]; default: 0; - * need_des + * Configures whether to force disable the integrated clock gating (ICG) of PLL clock + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG (BIT(0)) #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_M (PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V << PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S) #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_V 0x00000001U #define PMU_TIE_LOW_GLOBAL_BBPLL_ICG_S 0 /** PMU_TIE_LOW_GLOBAL_XTAL_ICG : WT; bitpos: [1]; default: 0; - * need_des + * Configures whether to force disable the integrated clock gating (ICG) of XTAL clock. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_GLOBAL_XTAL_ICG (BIT(1)) #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_M (PMU_TIE_LOW_GLOBAL_XTAL_ICG_V << PMU_TIE_LOW_GLOBAL_XTAL_ICG_S) #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_V 0x00000001U #define PMU_TIE_LOW_GLOBAL_XTAL_ICG_S 1 /** PMU_TIE_LOW_I2C_RETENTION : WT; bitpos: [2]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for the analog I2C to low, releasing the reset. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_I2C_RETENTION (BIT(2)) #define PMU_TIE_LOW_I2C_RETENTION_M (PMU_TIE_LOW_I2C_RETENTION_V << PMU_TIE_LOW_I2C_RETENTION_S) #define PMU_TIE_LOW_I2C_RETENTION_V 0x00000001U #define PMU_TIE_LOW_I2C_RETENTION_S 2 /** PMU_TIE_LOW_XPD_BB_I2C : WT; bitpos: [3]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BB_I2C to low, releasing the reset. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_XPD_BB_I2C (BIT(3)) #define PMU_TIE_LOW_XPD_BB_I2C_M (PMU_TIE_LOW_XPD_BB_I2C_V << PMU_TIE_LOW_XPD_BB_I2C_S) #define PMU_TIE_LOW_XPD_BB_I2C_V 0x00000001U #define PMU_TIE_LOW_XPD_BB_I2C_S 3 /** PMU_TIE_LOW_XPD_BBPLL_I2C : WT; bitpos: [4]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BBPLL_I2C to low, releasing the reset. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_XPD_BBPLL_I2C (BIT(4)) #define PMU_TIE_LOW_XPD_BBPLL_I2C_M (PMU_TIE_LOW_XPD_BBPLL_I2C_V << PMU_TIE_LOW_XPD_BBPLL_I2C_S) #define PMU_TIE_LOW_XPD_BBPLL_I2C_V 0x00000001U #define PMU_TIE_LOW_XPD_BBPLL_I2C_S 4 /** PMU_TIE_LOW_XPD_BBPLL : WT; bitpos: [5]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BBPLL to low, releasing the reset. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_XPD_BBPLL (BIT(5)) #define PMU_TIE_LOW_XPD_BBPLL_M (PMU_TIE_LOW_XPD_BBPLL_V << PMU_TIE_LOW_XPD_BBPLL_S) #define PMU_TIE_LOW_XPD_BBPLL_V 0x00000001U #define PMU_TIE_LOW_XPD_BBPLL_S 5 /** PMU_TIE_LOW_XPD_XTAL : WT; bitpos: [6]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for XTAL_CLK to low, releasing the reset. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_XPD_XTAL (BIT(6)) #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U #define PMU_TIE_LOW_XPD_XTAL_S 6 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; - * need_des + * Configures whether to force enable the integrated clock gating (ICG) of PLL clock. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG (BIT(25)) #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_M (PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V << PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S) #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_V 0x00000001U #define PMU_TIE_HIGH_GLOBAL_BBPLL_ICG_S 25 /** PMU_TIE_HIGH_GLOBAL_XTAL_ICG : WT; bitpos: [26]; default: 0; - * need_des + * Configures whether to force enable the integrated clock gating (ICG) of XTAL clock. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG (BIT(26)) #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_M (PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V << PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S) #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_V 0x00000001U #define PMU_TIE_HIGH_GLOBAL_XTAL_ICG_S 26 /** PMU_TIE_HIGH_I2C_RETENTION : WT; bitpos: [27]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for the analog I2C to high, putting it into reset. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_I2C_RETENTION (BIT(27)) #define PMU_TIE_HIGH_I2C_RETENTION_M (PMU_TIE_HIGH_I2C_RETENTION_V << PMU_TIE_HIGH_I2C_RETENTION_S) #define PMU_TIE_HIGH_I2C_RETENTION_V 0x00000001U #define PMU_TIE_HIGH_I2C_RETENTION_S 27 /** PMU_TIE_HIGH_XPD_BB_I2C : WT; bitpos: [28]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BB_I2C to high, putting it into reset. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_XPD_BB_I2C (BIT(28)) #define PMU_TIE_HIGH_XPD_BB_I2C_M (PMU_TIE_HIGH_XPD_BB_I2C_V << PMU_TIE_HIGH_XPD_BB_I2C_S) #define PMU_TIE_HIGH_XPD_BB_I2C_V 0x00000001U #define PMU_TIE_HIGH_XPD_BB_I2C_S 28 /** PMU_TIE_HIGH_XPD_BBPLL_I2C : WT; bitpos: [29]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BBPLL_I2C to high, putting it into reset. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_XPD_BBPLL_I2C (BIT(29)) #define PMU_TIE_HIGH_XPD_BBPLL_I2C_M (PMU_TIE_HIGH_XPD_BBPLL_I2C_V << PMU_TIE_HIGH_XPD_BBPLL_I2C_S) #define PMU_TIE_HIGH_XPD_BBPLL_I2C_V 0x00000001U #define PMU_TIE_HIGH_XPD_BBPLL_I2C_S 29 /** PMU_TIE_HIGH_XPD_BBPLL : WT; bitpos: [30]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for BBPLL to high, putting it into reset. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_XPD_BBPLL (BIT(30)) #define PMU_TIE_HIGH_XPD_BBPLL_M (PMU_TIE_HIGH_XPD_BBPLL_V << PMU_TIE_HIGH_XPD_BBPLL_S) #define PMU_TIE_HIGH_XPD_BBPLL_V 0x00000001U #define PMU_TIE_HIGH_XPD_BBPLL_S 30 /** PMU_TIE_HIGH_XPD_XTAL : WT; bitpos: [31]; default: 0; - * need_des + * Configures whether to force the power-on reset (POR) signal for XTAL_CLK to high, putting it into reset. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_XPD_XTAL (BIT(31)) #define PMU_TIE_HIGH_XPD_XTAL_M (PMU_TIE_HIGH_XPD_XTAL_V << PMU_TIE_HIGH_XPD_XTAL_S) @@ -1633,32 +1918,40 @@ extern "C" { #define PMU_TIE_HIGH_XPD_XTAL_S 31 /** PMU_IMM_SLEEP_SYSCLK_REG register - * need_des + * Software-controlled enable signal for system root clk switching during sleep */ #define PMU_IMM_SLEEP_SYSCLK_REG (DR_REG_PMU_BASE + 0xd0) /** PMU_UPDATE_DIG_ICG_SWITCH : WT; bitpos: [28]; default: 0; - * need_des + * Configures whether to force power up XTAL. + * 0: No effect + * 1: Force enable */ #define PMU_UPDATE_DIG_ICG_SWITCH (BIT(28)) #define PMU_UPDATE_DIG_ICG_SWITCH_M (PMU_UPDATE_DIG_ICG_SWITCH_V << PMU_UPDATE_DIG_ICG_SWITCH_S) #define PMU_UPDATE_DIG_ICG_SWITCH_V 0x00000001U #define PMU_UPDATE_DIG_ICG_SWITCH_S 28 /** PMU_TIE_LOW_ICG_SLP_SEL : WT; bitpos: [29]; default: 0; - * need_des + * Configures whether to force disable the integrated clock gating (ICG) of PMU clock controller. + * 0: No effect + * 1: Force disable */ #define PMU_TIE_LOW_ICG_SLP_SEL (BIT(29)) #define PMU_TIE_LOW_ICG_SLP_SEL_M (PMU_TIE_LOW_ICG_SLP_SEL_V << PMU_TIE_LOW_ICG_SLP_SEL_S) #define PMU_TIE_LOW_ICG_SLP_SEL_V 0x00000001U #define PMU_TIE_LOW_ICG_SLP_SEL_S 29 /** PMU_TIE_HIGH_ICG_SLP_SEL : WT; bitpos: [30]; default: 0; - * need_des + * Configures whether to force enable the integrated clock gating (ICG) of PMU clock controller. + * 0: No effect + * 1: Force enable */ #define PMU_TIE_HIGH_ICG_SLP_SEL (BIT(30)) #define PMU_TIE_HIGH_ICG_SLP_SEL_M (PMU_TIE_HIGH_ICG_SLP_SEL_V << PMU_TIE_HIGH_ICG_SLP_SEL_S) #define PMU_TIE_HIGH_ICG_SLP_SEL_V 0x00000001U #define PMU_TIE_HIGH_ICG_SLP_SEL_S 30 /** PMU_UPDATE_DIG_SYS_CLK_SEL : WT; bitpos: [31]; default: 0; - * need_des + * Configures whether to force update the HP_ROOT_CLK configuration stored in PMU registers. + * 0: No effect + * 1: Force update */ #define PMU_UPDATE_DIG_SYS_CLK_SEL (BIT(31)) #define PMU_UPDATE_DIG_SYS_CLK_SEL_M (PMU_UPDATE_DIG_SYS_CLK_SEL_V << PMU_UPDATE_DIG_SYS_CLK_SEL_S) @@ -1666,11 +1959,13 @@ extern "C" { #define PMU_UPDATE_DIG_SYS_CLK_SEL_S 31 /** PMU_IMM_HP_FUNC_ICG_REG register - * need_des + * Software-controlled configuration for functional clock gating of PMU's forced update output */ #define PMU_IMM_HP_FUNC_ICG_REG (DR_REG_PMU_BASE + 0xd4) /** PMU_UPDATE_DIG_ICG_FUNC_EN : WT; bitpos: [31]; default: 0; - * need_des + * Configure whether to force the PMU to update its ICG enable signals of HP system peripherals' function clocks based on the current PMU state. + * 0: No effect + * 1: Force update */ #define PMU_UPDATE_DIG_ICG_FUNC_EN (BIT(31)) #define PMU_UPDATE_DIG_ICG_FUNC_EN_M (PMU_UPDATE_DIG_ICG_FUNC_EN_V << PMU_UPDATE_DIG_ICG_FUNC_EN_S) @@ -1678,11 +1973,13 @@ extern "C" { #define PMU_UPDATE_DIG_ICG_FUNC_EN_S 31 /** PMU_IMM_HP_APB_ICG_REG register - * need_des + * Software-controlled configuration for APB clock gating of PMU's forced update output */ #define PMU_IMM_HP_APB_ICG_REG (DR_REG_PMU_BASE + 0xd8) /** PMU_UPDATE_DIG_ICG_APB_EN : WT; bitpos: [31]; default: 0; - * need_des + * Configure whether to force the PMU to update its ICG enable signals of HP system peripherals' APB clock based on the current PMU state. + * 0: No effect + * 1: Force update */ #define PMU_UPDATE_DIG_ICG_APB_EN (BIT(31)) #define PMU_UPDATE_DIG_ICG_APB_EN_M (PMU_UPDATE_DIG_ICG_APB_EN_V << PMU_UPDATE_DIG_ICG_APB_EN_S) @@ -1690,11 +1987,13 @@ extern "C" { #define PMU_UPDATE_DIG_ICG_APB_EN_S 31 /** PMU_IMM_MODEM_ICG_REG register - * need_des + * Software-controlled configuration for HP system Modem clock gating of PMU's forced update output */ #define PMU_IMM_MODEM_ICG_REG (DR_REG_PMU_BASE + 0xdc) /** PMU_UPDATE_DIG_ICG_MODEM_EN : WT; bitpos: [31]; default: 0; - * need_des + * Configure whether to force the PMU to update its ICG enable signals its Modem clock based on the current PMU state. + * 0: No effect + * 1: Force update */ #define PMU_UPDATE_DIG_ICG_MODEM_EN (BIT(31)) #define PMU_UPDATE_DIG_ICG_MODEM_EN_M (PMU_UPDATE_DIG_ICG_MODEM_EN_V << PMU_UPDATE_DIG_ICG_MODEM_EN_S) @@ -1721,32 +2020,40 @@ extern "C" { #define PMU_TIE_HIGH_LP_ROOTCLK_SEL_S 31 /** PMU_IMM_PAD_HOLD_ALL_REG register - * need_des + * Software-controlled signal to tie PMU's HP/LP GPIOs HOLD high or low */ #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; - * need_des + * Configures whether to force the PMU LP GPIO HOLD signal to high. + * 0: No effect + * 1: Force to high */ #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL (BIT(28)) #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S) #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_V 0x00000001U #define PMU_TIE_HIGH_LP_PAD_HOLD_ALL_S 28 /** PMU_TIE_LOW_LP_PAD_HOLD_ALL : WT; bitpos: [29]; default: 0; - * need_des + * Configures whether to force the PMU LP GPIO HOLD signal to low. + * 0: No effect + * 1: Force to low */ #define PMU_TIE_LOW_LP_PAD_HOLD_ALL (BIT(29)) #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_M (PMU_TIE_LOW_LP_PAD_HOLD_ALL_V << PMU_TIE_LOW_LP_PAD_HOLD_ALL_S) #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_V 0x00000001U #define PMU_TIE_LOW_LP_PAD_HOLD_ALL_S 29 /** PMU_TIE_HIGH_HP_PAD_HOLD_ALL : WT; bitpos: [30]; default: 0; - * need_des + * Configures whether to force the PMU HP GPIO HOLD signal to high. + * 0: No effect + * 1: Force to high */ #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL (BIT(30)) #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_M (PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V << PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S) #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_V 0x00000001U #define PMU_TIE_HIGH_HP_PAD_HOLD_ALL_S 30 /** PMU_TIE_LOW_HP_PAD_HOLD_ALL : WT; bitpos: [31]; default: 0; - * need_des + * Configures whether to force the PMU HP GPIO HOLD signal to low. + * 0: No effect + * 1: Force to low */ #define PMU_TIE_LOW_HP_PAD_HOLD_ALL (BIT(31)) #define PMU_TIE_LOW_HP_PAD_HOLD_ALL_M (PMU_TIE_LOW_HP_PAD_HOLD_ALL_V << PMU_TIE_LOW_HP_PAD_HOLD_ALL_S) @@ -1754,18 +2061,22 @@ extern "C" { #define PMU_TIE_LOW_HP_PAD_HOLD_ALL_S 31 /** PMU_IMM_I2C_ISO_REG register - * need_des + * Software-controlled signal to tie PMU's i2c iso enable high or low */ #define PMU_IMM_I2C_ISO_REG (DR_REG_PMU_BASE + 0xe8) /** PMU_TIE_HIGH_I2C_ISO_EN : WT; bitpos: [30]; default: 0; - * need_des + * Configures whether to force the PMU I2C_ISO enabling signal to high. + * 0: No effect + * 1: Force to high */ #define PMU_TIE_HIGH_I2C_ISO_EN (BIT(30)) #define PMU_TIE_HIGH_I2C_ISO_EN_M (PMU_TIE_HIGH_I2C_ISO_EN_V << PMU_TIE_HIGH_I2C_ISO_EN_S) #define PMU_TIE_HIGH_I2C_ISO_EN_V 0x00000001U #define PMU_TIE_HIGH_I2C_ISO_EN_S 30 /** PMU_TIE_LOW_I2C_ISO_EN : WT; bitpos: [31]; default: 0; - * need_des + * Configures whether to force the PMU I2C_ISO enabling signal to low. + * 0: No effect + * 1: Force to low */ #define PMU_TIE_LOW_I2C_ISO_EN (BIT(31)) #define PMU_TIE_LOW_I2C_ISO_EN_M (PMU_TIE_LOW_I2C_ISO_EN_V << PMU_TIE_LOW_I2C_ISO_EN_S) @@ -1773,25 +2084,25 @@ extern "C" { #define PMU_TIE_LOW_I2C_ISO_EN_S 31 /** PMU_POWER_WAIT_TIMER0_REG register - * need_des + * Software-controlled power-on/off waiting timer for PMU */ #define PMU_POWER_WAIT_TIMER0_REG (DR_REG_PMU_BASE + 0xec) /** PMU_DG_HP_POWERDOWN_TIMER : R/W; bitpos: [13:5]; default: 255; - * need_des + * Configures the wait cycles before powering down HP power domains. */ #define PMU_DG_HP_POWERDOWN_TIMER 0x000001FFU #define PMU_DG_HP_POWERDOWN_TIMER_M (PMU_DG_HP_POWERDOWN_TIMER_V << PMU_DG_HP_POWERDOWN_TIMER_S) #define PMU_DG_HP_POWERDOWN_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERDOWN_TIMER_S 5 /** PMU_DG_HP_POWERUP_TIMER : R/W; bitpos: [22:14]; default: 255; - * need_des + * Configures the wait cycles before waking up HP power domains. */ #define PMU_DG_HP_POWERUP_TIMER 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_S 14 /** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; - * need_des + * Configures the wait cycles during sleep of HP power domains. */ #define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU #define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) @@ -1799,25 +2110,25 @@ extern "C" { #define PMU_DG_HP_PD_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER1_REG register - * need_des + * Software-controlled power-on/off waiting timer for LP PERI controlled by PMU */ #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) /** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; - * need_des + * Configures the wait cycles before powering down LP power domains. */ #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_S 9 /** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; - * need_des + * Configures the wait cycles before waking up LP power domains. */ #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_S 16 /** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; - * need_des + * Configures the wait cycles during sleep of LP power domains. */ #define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU #define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) @@ -1825,32 +2136,32 @@ extern "C" { #define PMU_DG_LP_PD_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER2_REG register - * need_des + * Software-controlled waiting timer for HP, LP ISO and reset in PMU */ #define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) /** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; - * need_des + * Configures the wait cycles of LP ISO control. */ #define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU #define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) #define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU #define PMU_DG_LP_ISO_WAIT_TIMER_S 0 /** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; - * need_des + * Configures the wait cycles of LP reset control. */ #define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU #define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) #define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU #define PMU_DG_LP_RST_WAIT_TIMER_S 8 /** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; - * need_des + * Configures the wait cycles of HP ISO control. */ #define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU #define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) #define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU #define PMU_DG_HP_ISO_WAIT_TIMER_S 16 /** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; - * need_des + * Configures the wait cycles of HP reset control. */ #define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU #define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) @@ -1858,60 +2169,76 @@ extern "C" { #define PMU_DG_HP_RST_WAIT_TIMER_S 24 /** PMU_POWER_PD_TOP_CNTL_REG register - * need_des + * Configuration register for Peripherals+ROM power domain controlled by PMU */ #define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to force reset Peripherals+ROM domain. + * 0: No effect + * 1: Force reset */ #define PMU_FORCE_TOP_RESET (BIT(0)) #define PMU_FORCE_TOP_RESET_M (PMU_FORCE_TOP_RESET_V << PMU_FORCE_TOP_RESET_S) #define PMU_FORCE_TOP_RESET_V 0x00000001U #define PMU_FORCE_TOP_RESET_S 0 /** PMU_FORCE_TOP_ISO : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of Peripherals+ROM domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_TOP_ISO (BIT(1)) #define PMU_FORCE_TOP_ISO_M (PMU_FORCE_TOP_ISO_V << PMU_FORCE_TOP_ISO_S) #define PMU_FORCE_TOP_ISO_V 0x00000001U #define PMU_FORCE_TOP_ISO_S 1 /** PMU_FORCE_TOP_PU : R/W; bitpos: [2]; default: 1; - * need_des + * Configures whether or not to force power up Peripherals+ROM domain. This setting has a lower priority than PMU_PD_TOP_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_TOP_PU (BIT(2)) #define PMU_FORCE_TOP_PU_M (PMU_FORCE_TOP_PU_V << PMU_FORCE_TOP_PU_S) #define PMU_FORCE_TOP_PU_V 0x00000001U #define PMU_FORCE_TOP_PU_S 2 /** PMU_FORCE_TOP_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des + * Configures whether or not to forcefully prevent the reset of Peripherals+ROM domain. This setting has a lower priority than PMU_FORCE_TOP_RESET. + * 0: No effect + * 1: Force not reset */ #define PMU_FORCE_TOP_NO_RESET (BIT(3)) #define PMU_FORCE_TOP_NO_RESET_M (PMU_FORCE_TOP_NO_RESET_V << PMU_FORCE_TOP_NO_RESET_S) #define PMU_FORCE_TOP_NO_RESET_V 0x00000001U #define PMU_FORCE_TOP_NO_RESET_S 3 /** PMU_FORCE_TOP_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des + * Configures whether or not to disable the force isolation of Peripherals+ROM domain. This setting has a lower priority than PMU_FORCE_TOP_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_TOP_NO_ISO (BIT(4)) #define PMU_FORCE_TOP_NO_ISO_M (PMU_FORCE_TOP_NO_ISO_V << PMU_FORCE_TOP_NO_ISO_S) #define PMU_FORCE_TOP_NO_ISO_V 0x00000001U #define PMU_FORCE_TOP_NO_ISO_S 4 /** PMU_FORCE_TOP_PD : R/W; bitpos: [5]; default: 0; - * need_des + * Configures whether or not to force power down Peripherals+ROM domain. This setting has a lower priority than PMU_FORCE_TOP_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_TOP_PD (BIT(5)) #define PMU_FORCE_TOP_PD_M (PMU_FORCE_TOP_PD_V << PMU_FORCE_TOP_PD_S) #define PMU_FORCE_TOP_PD_V 0x00000001U #define PMU_FORCE_TOP_PD_S 5 /** PMU_PD_TOP_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des + * Configures whether or not to force power up Peripherals+ROM domain, regardless the signals from PMU. + * 0: No effect + * 1: Force power up */ #define PMU_PD_TOP_MASK 0x0000001FU #define PMU_PD_TOP_MASK_M (PMU_PD_TOP_MASK_V << PMU_PD_TOP_MASK_S) #define PMU_PD_TOP_MASK_V 0x0000001FU #define PMU_PD_TOP_MASK_S 6 /** PMU_PD_TOP_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des + * Configures whether or not to force power down Peripherals+ROM domain, regardless the signals from PMU. This setting has a lower priority than PMU_PD_TOP_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_PD_TOP_PD_MASK 0x0000001FU #define PMU_PD_TOP_PD_MASK_M (PMU_PD_TOP_PD_MASK_V << PMU_PD_TOP_PD_MASK_S) @@ -1919,60 +2246,76 @@ extern "C" { #define PMU_PD_TOP_PD_MASK_S 27 /** PMU_POWER_PD_HPAON_CNTL_REG register - * need_des + * Configuration register for Modem Power power domain controlled by PMU */ #define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to force reset Modem Power domain. + * 0: No effect + * 1: Force reset */ #define PMU_FORCE_HP_AON_RESET (BIT(0)) #define PMU_FORCE_HP_AON_RESET_M (PMU_FORCE_HP_AON_RESET_V << PMU_FORCE_HP_AON_RESET_S) #define PMU_FORCE_HP_AON_RESET_V 0x00000001U #define PMU_FORCE_HP_AON_RESET_S 0 /** PMU_FORCE_HP_AON_ISO : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of Modem Power domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_HP_AON_ISO (BIT(1)) #define PMU_FORCE_HP_AON_ISO_M (PMU_FORCE_HP_AON_ISO_V << PMU_FORCE_HP_AON_ISO_S) #define PMU_FORCE_HP_AON_ISO_V 0x00000001U #define PMU_FORCE_HP_AON_ISO_S 1 /** PMU_FORCE_HP_AON_PU : R/W; bitpos: [2]; default: 1; - * need_des + * Configures whether or not to force power up Modem Power domain. This setting has a lower priority than PMU_PD_HP_AON_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_HP_AON_PU (BIT(2)) #define PMU_FORCE_HP_AON_PU_M (PMU_FORCE_HP_AON_PU_V << PMU_FORCE_HP_AON_PU_S) #define PMU_FORCE_HP_AON_PU_V 0x00000001U #define PMU_FORCE_HP_AON_PU_S 2 /** PMU_FORCE_HP_AON_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des + * Configures whether or not to forcefully prevent the reset of Modem Power domain. This setting has a lower priority than PMU_FORCE_HP_AON_RESET. + * 0: No effect + * 1: Force not reset */ #define PMU_FORCE_HP_AON_NO_RESET (BIT(3)) #define PMU_FORCE_HP_AON_NO_RESET_M (PMU_FORCE_HP_AON_NO_RESET_V << PMU_FORCE_HP_AON_NO_RESET_S) #define PMU_FORCE_HP_AON_NO_RESET_V 0x00000001U #define PMU_FORCE_HP_AON_NO_RESET_S 3 /** PMU_FORCE_HP_AON_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des + * Configures whether or not to disable the force isolation of Modem Power domain. This setting has a lower priority than PMU_FORCE_HP_AON_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_HP_AON_NO_ISO (BIT(4)) #define PMU_FORCE_HP_AON_NO_ISO_M (PMU_FORCE_HP_AON_NO_ISO_V << PMU_FORCE_HP_AON_NO_ISO_S) #define PMU_FORCE_HP_AON_NO_ISO_V 0x00000001U #define PMU_FORCE_HP_AON_NO_ISO_S 4 /** PMU_FORCE_HP_AON_PD : R/W; bitpos: [5]; default: 0; - * need_des + * Configures whether or not to force power down Modem Power domain. This setting has a lower priority than PMU_FORCE_HP_AON_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_HP_AON_PD (BIT(5)) #define PMU_FORCE_HP_AON_PD_M (PMU_FORCE_HP_AON_PD_V << PMU_FORCE_HP_AON_PD_S) #define PMU_FORCE_HP_AON_PD_V 0x00000001U #define PMU_FORCE_HP_AON_PD_S 5 /** PMU_PD_HP_AON_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des + * Configures whether or not to force power up Modem Power domain, regardless the signals from PMU. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_AON_MASK 0x0000001FU #define PMU_PD_HP_AON_MASK_M (PMU_PD_HP_AON_MASK_V << PMU_PD_HP_AON_MASK_S) #define PMU_PD_HP_AON_MASK_V 0x0000001FU #define PMU_PD_HP_AON_MASK_S 6 /** PMU_PD_HP_AON_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des + * Configures whether or not to force power down Modem Power domain, regardless the signals from PMU. This setting has a lower priority than PMU_PD_HP_AON_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_AON_PD_MASK 0x0000001FU #define PMU_PD_HP_AON_PD_MASK_M (PMU_PD_HP_AON_PD_MASK_V << PMU_PD_HP_AON_PD_MASK_S) @@ -1980,60 +2323,76 @@ extern "C" { #define PMU_PD_HP_AON_PD_MASK_S 27 /** PMU_POWER_PD_HPCPU_CNTL_REG register - * need_des + * Configuration register for CPU power domain controlled by PMU */ #define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to force reset CPU domain. + * 0: No effect + * 1: Force reset */ #define PMU_FORCE_HP_CPU_RESET (BIT(0)) #define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S) #define PMU_FORCE_HP_CPU_RESET_V 0x00000001U #define PMU_FORCE_HP_CPU_RESET_S 0 /** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of CPU domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_HP_CPU_ISO (BIT(1)) #define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S) #define PMU_FORCE_HP_CPU_ISO_V 0x00000001U #define PMU_FORCE_HP_CPU_ISO_S 1 /** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1; - * need_des + * Configures whether or not to force power up CPU domain. This setting has a lower priority than PMU_PD_HP_CPU_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_HP_CPU_PU (BIT(2)) #define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S) #define PMU_FORCE_HP_CPU_PU_V 0x00000001U #define PMU_FORCE_HP_CPU_PU_S 2 /** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des + * Configures whether or not to forcefully prevent the reset of CPU domain. This setting has a lower priority than PMU_FORCE_HP_CPU_RESET. + * 0: No effect + * 1: Force not reset */ #define PMU_FORCE_HP_CPU_NO_RESET (BIT(3)) #define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S) #define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U #define PMU_FORCE_HP_CPU_NO_RESET_S 3 /** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des + * Configures whether or not to disable the force isolation of CPU domain. This setting has a lower priority than PMU_FORCE_HP_CPU_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_HP_CPU_NO_ISO (BIT(4)) #define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S) #define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U #define PMU_FORCE_HP_CPU_NO_ISO_S 4 /** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0; - * need_des + * Configures whether or not to force power down CPU domain. This setting has a lower priority than PMU_FORCE_HP_CPU_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_HP_CPU_PD (BIT(5)) #define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S) #define PMU_FORCE_HP_CPU_PD_V 0x00000001U #define PMU_FORCE_HP_CPU_PD_S 5 /** PMU_PD_HP_CPU_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des + * Configures whether or not to force power up CPU domain, regardless the signals from PMU. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_CPU_MASK 0x0000001FU #define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S) #define PMU_PD_HP_CPU_MASK_V 0x0000001FU #define PMU_PD_HP_CPU_MASK_S 6 /** PMU_PD_HP_CPU_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des + * Configures whether or not to force power down CPU domain, regardless the signals from PMU. This setting has a lower priority than PMU_PD_HP_CPU_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_CPU_PD_MASK 0x0000001FU #define PMU_PD_HP_CPU_PD_MASK_M (PMU_PD_HP_CPU_PD_MASK_V << PMU_PD_HP_CPU_PD_MASK_S) @@ -2102,60 +2461,76 @@ extern "C" { #define PMU_PD_HP_PERI_PD_MASK_S 27 /** PMU_POWER_PD_HPWIFI_CNTL_REG register - * need_des + * Configuration register for MODEM power domain controlled by PMU */ #define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to force reset MODEM domain. + * 0: No effect + * 1: Force reset */ #define PMU_FORCE_HP_WIFI_RESET (BIT(0)) #define PMU_FORCE_HP_WIFI_RESET_M (PMU_FORCE_HP_WIFI_RESET_V << PMU_FORCE_HP_WIFI_RESET_S) #define PMU_FORCE_HP_WIFI_RESET_V 0x00000001U #define PMU_FORCE_HP_WIFI_RESET_S 0 /** PMU_FORCE_HP_WIFI_ISO : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of MODEM domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_HP_WIFI_ISO (BIT(1)) #define PMU_FORCE_HP_WIFI_ISO_M (PMU_FORCE_HP_WIFI_ISO_V << PMU_FORCE_HP_WIFI_ISO_S) #define PMU_FORCE_HP_WIFI_ISO_V 0x00000001U #define PMU_FORCE_HP_WIFI_ISO_S 1 /** PMU_FORCE_HP_WIFI_PU : R/W; bitpos: [2]; default: 1; - * need_des + * Configures whether or not to force power up MODEM domain. This setting has a lower priority than PMU_PD_HP_WIFI_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_HP_WIFI_PU (BIT(2)) #define PMU_FORCE_HP_WIFI_PU_M (PMU_FORCE_HP_WIFI_PU_V << PMU_FORCE_HP_WIFI_PU_S) #define PMU_FORCE_HP_WIFI_PU_V 0x00000001U #define PMU_FORCE_HP_WIFI_PU_S 2 /** PMU_FORCE_HP_WIFI_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des + * Configures whether or not to forcefully prevent the reset of MODEM domain. This setting has a lower priority than PMU_FORCE_HP_WIFI_RESET. + * 0: No effect + * 1: Force not reset */ #define PMU_FORCE_HP_WIFI_NO_RESET (BIT(3)) #define PMU_FORCE_HP_WIFI_NO_RESET_M (PMU_FORCE_HP_WIFI_NO_RESET_V << PMU_FORCE_HP_WIFI_NO_RESET_S) #define PMU_FORCE_HP_WIFI_NO_RESET_V 0x00000001U #define PMU_FORCE_HP_WIFI_NO_RESET_S 3 /** PMU_FORCE_HP_WIFI_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des + * Configures whether or not to disable the force isolation of MODEM domain. This setting has a lower priority than PMU_FORCE_HP_WIFI_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_HP_WIFI_NO_ISO (BIT(4)) #define PMU_FORCE_HP_WIFI_NO_ISO_M (PMU_FORCE_HP_WIFI_NO_ISO_V << PMU_FORCE_HP_WIFI_NO_ISO_S) #define PMU_FORCE_HP_WIFI_NO_ISO_V 0x00000001U #define PMU_FORCE_HP_WIFI_NO_ISO_S 4 /** PMU_FORCE_HP_WIFI_PD : R/W; bitpos: [5]; default: 0; - * need_des + * Configures whether or not to force power down MODEM domain. This setting has a lower priority than PMU_FORCE_HP_WIFI_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_HP_WIFI_PD (BIT(5)) #define PMU_FORCE_HP_WIFI_PD_M (PMU_FORCE_HP_WIFI_PD_V << PMU_FORCE_HP_WIFI_PD_S) #define PMU_FORCE_HP_WIFI_PD_V 0x00000001U #define PMU_FORCE_HP_WIFI_PD_S 5 /** PMU_PD_HP_WIFI_MASK : R/W; bitpos: [10:6]; default: 0; - * need_des + * Configures whether or not to force power up MODEM domain, regardless the signals from PMU. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_WIFI_MASK 0x0000001FU #define PMU_PD_HP_WIFI_MASK_M (PMU_PD_HP_WIFI_MASK_V << PMU_PD_HP_WIFI_MASK_S) #define PMU_PD_HP_WIFI_MASK_V 0x0000001FU #define PMU_PD_HP_WIFI_MASK_S 6 /** PMU_PD_HP_WIFI_PD_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des + * Configures whether or not to force power down MODEM domain, regardless the signals from PMU. This setting has a lower priority than PMU_PD_HP_WIFI_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_PD_HP_WIFI_PD_MASK 0x0000001FU #define PMU_PD_HP_WIFI_PD_MASK_M (PMU_PD_HP_WIFI_PD_MASK_V << PMU_PD_HP_WIFI_PD_MASK_S) @@ -2163,46 +2538,58 @@ extern "C" { #define PMU_PD_HP_WIFI_PD_MASK_S 27 /** PMU_POWER_PD_LPPERI_CNTL_REG register - * need_des + * Configuration register for LPSYS_OFF power domain controlled by PMU */ #define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to force reset LPSYS_OFF domain. + * 0: No effect + * 1: Force reset */ #define PMU_FORCE_LP_PERI_RESET (BIT(0)) #define PMU_FORCE_LP_PERI_RESET_M (PMU_FORCE_LP_PERI_RESET_V << PMU_FORCE_LP_PERI_RESET_S) #define PMU_FORCE_LP_PERI_RESET_V 0x00000001U #define PMU_FORCE_LP_PERI_RESET_S 0 /** PMU_FORCE_LP_PERI_ISO : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of LPSYS_OFF domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_LP_PERI_ISO (BIT(1)) #define PMU_FORCE_LP_PERI_ISO_M (PMU_FORCE_LP_PERI_ISO_V << PMU_FORCE_LP_PERI_ISO_S) #define PMU_FORCE_LP_PERI_ISO_V 0x00000001U #define PMU_FORCE_LP_PERI_ISO_S 1 /** PMU_FORCE_LP_PERI_PU : R/W; bitpos: [2]; default: 1; - * need_des + * Configures whether or not to force power up LPSYS_OFF domain. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_LP_PERI_PU (BIT(2)) #define PMU_FORCE_LP_PERI_PU_M (PMU_FORCE_LP_PERI_PU_V << PMU_FORCE_LP_PERI_PU_S) #define PMU_FORCE_LP_PERI_PU_V 0x00000001U #define PMU_FORCE_LP_PERI_PU_S 2 /** PMU_FORCE_LP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; - * need_des + * Configures whether or not to forcefully prevent the reset of LPSYS_OFF domain. This setting has a lower priority than PMU_FORCE_LP_PERI_RESET. + * 0: No effect + * 1: Force not reset */ #define PMU_FORCE_LP_PERI_NO_RESET (BIT(3)) #define PMU_FORCE_LP_PERI_NO_RESET_M (PMU_FORCE_LP_PERI_NO_RESET_V << PMU_FORCE_LP_PERI_NO_RESET_S) #define PMU_FORCE_LP_PERI_NO_RESET_V 0x00000001U #define PMU_FORCE_LP_PERI_NO_RESET_S 3 /** PMU_FORCE_LP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; - * need_des + * Configures whether or not to disable the force isolation of LPSYS_OFF domain. This setting has a lower priority than PMU_FORCE_LP_PERI_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_LP_PERI_NO_ISO (BIT(4)) #define PMU_FORCE_LP_PERI_NO_ISO_M (PMU_FORCE_LP_PERI_NO_ISO_V << PMU_FORCE_LP_PERI_NO_ISO_S) #define PMU_FORCE_LP_PERI_NO_ISO_V 0x00000001U #define PMU_FORCE_LP_PERI_NO_ISO_S 4 /** PMU_FORCE_LP_PERI_PD : R/W; bitpos: [5]; default: 0; - * need_des + * Configures whether or not to force power down LPSYS_OFF domain. This setting has a lower priority than PMU_FORCE_LP_PERI_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_LP_PERI_PD (BIT(5)) #define PMU_FORCE_LP_PERI_PD_M (PMU_FORCE_LP_PERI_PD_V << PMU_FORCE_LP_PERI_PD_S) @@ -2210,32 +2597,40 @@ extern "C" { #define PMU_FORCE_LP_PERI_PD_S 5 /** PMU_POWER_PD_MEM_CNTL_REG register - * need_des + * Configuration register for Internal SRAMx power domain's ISO and overall switch controlled by PMU */ #define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; - * need_des + * Configures whether or not to enable the force isolation of Internal SRAMx domain. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_HP_MEM_ISO 0x0000000FU #define PMU_FORCE_HP_MEM_ISO_M (PMU_FORCE_HP_MEM_ISO_V << PMU_FORCE_HP_MEM_ISO_S) #define PMU_FORCE_HP_MEM_ISO_V 0x0000000FU #define PMU_FORCE_HP_MEM_ISO_S 0 /** PMU_FORCE_HP_MEM_PD : R/W; bitpos: [7:4]; default: 0; - * need_des + * Configures whether or not to force power down Internal SRAMx domain. This setting has a lower priority than PMU_FORCE_HP_MEM_PU. + * 0: No effect + * 1: Force power down */ #define PMU_FORCE_HP_MEM_PD 0x0000000FU #define PMU_FORCE_HP_MEM_PD_M (PMU_FORCE_HP_MEM_PD_V << PMU_FORCE_HP_MEM_PD_S) #define PMU_FORCE_HP_MEM_PD_V 0x0000000FU #define PMU_FORCE_HP_MEM_PD_S 4 /** PMU_FORCE_HP_MEM_NO_ISO : R/W; bitpos: [27:24]; default: 15; - * need_des + * Configures whether or not to disable the force isolation of Internal SRAMx domain. This setting has a lower priority than PMU_FORCE_HP_MEM_ISO. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_HP_MEM_NO_ISO 0x0000000FU #define PMU_FORCE_HP_MEM_NO_ISO_M (PMU_FORCE_HP_MEM_NO_ISO_V << PMU_FORCE_HP_MEM_NO_ISO_S) #define PMU_FORCE_HP_MEM_NO_ISO_V 0x0000000FU #define PMU_FORCE_HP_MEM_NO_ISO_S 24 /** PMU_FORCE_HP_MEM_PU : R/W; bitpos: [31:28]; default: 15; - * need_des + * Configures whether or not to force power up Internal SRAMx domain. This setting has a lower priority than PMU_PD_HP_AON_MASK. + * 0: No effect + * 1: Force power up */ #define PMU_FORCE_HP_MEM_PU 0x0000000FU #define PMU_FORCE_HP_MEM_PU_M (PMU_FORCE_HP_MEM_PU_V << PMU_FORCE_HP_MEM_PU_S) @@ -2243,46 +2638,58 @@ extern "C" { #define PMU_FORCE_HP_MEM_PU_S 28 /** PMU_POWER_PD_MEM_MASK_REG register - * need_des + * Configuration register for LDO switch of individual Internal SRAMx power supply controlled by PMU */ #define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; - * need_des + * Configures whether the Internal SRAM2 follows the power up/down state of Peripherals+ROM domain. + * 0: Follows Peripherals+ROM domain + * 1: Does not follow Peripherals+ROM domain. */ #define PMU_PD_HP_MEM2_PD_MASK 0x0000001FU #define PMU_PD_HP_MEM2_PD_MASK_M (PMU_PD_HP_MEM2_PD_MASK_V << PMU_PD_HP_MEM2_PD_MASK_S) #define PMU_PD_HP_MEM2_PD_MASK_V 0x0000001FU #define PMU_PD_HP_MEM2_PD_MASK_S 0 /** PMU_PD_HP_MEM1_PD_MASK : R/W; bitpos: [9:5]; default: 0; - * need_des + * Configures whether the Internal SRAM1 follows the power up/down state of Peripherals+ROM domain. + * 0: Follows Peripherals+ROM domain + * 1: Does not follow Peripherals+ROM domain. */ #define PMU_PD_HP_MEM1_PD_MASK 0x0000001FU #define PMU_PD_HP_MEM1_PD_MASK_M (PMU_PD_HP_MEM1_PD_MASK_V << PMU_PD_HP_MEM1_PD_MASK_S) #define PMU_PD_HP_MEM1_PD_MASK_V 0x0000001FU #define PMU_PD_HP_MEM1_PD_MASK_S 5 /** PMU_PD_HP_MEM0_PD_MASK : R/W; bitpos: [14:10]; default: 0; - * need_des + * Configures whether the Internal SRAM0 follows the power up/down state of Peripherals+ROM domain. + * 0: Follows Peripherals+ROM domain + * 1: Does not follow Peripherals+ROM domain. */ #define PMU_PD_HP_MEM0_PD_MASK 0x0000001FU #define PMU_PD_HP_MEM0_PD_MASK_M (PMU_PD_HP_MEM0_PD_MASK_V << PMU_PD_HP_MEM0_PD_MASK_S) #define PMU_PD_HP_MEM0_PD_MASK_V 0x0000001FU #define PMU_PD_HP_MEM0_PD_MASK_S 10 /** PMU_PD_HP_MEM2_MASK : R/W; bitpos: [21:17]; default: 0; - * need_des + * Configures whether to force power up Internal SRAM2. + * 0: Do not force power up + * 1: Force power up */ #define PMU_PD_HP_MEM2_MASK 0x0000001FU #define PMU_PD_HP_MEM2_MASK_M (PMU_PD_HP_MEM2_MASK_V << PMU_PD_HP_MEM2_MASK_S) #define PMU_PD_HP_MEM2_MASK_V 0x0000001FU #define PMU_PD_HP_MEM2_MASK_S 17 /** PMU_PD_HP_MEM1_MASK : R/W; bitpos: [26:22]; default: 0; - * need_des + * Configures whether to to force power up Internal SRAM1. + * 0: Do not force power up + * 1: Force power up */ #define PMU_PD_HP_MEM1_MASK 0x0000001FU #define PMU_PD_HP_MEM1_MASK_M (PMU_PD_HP_MEM1_MASK_V << PMU_PD_HP_MEM1_MASK_S) #define PMU_PD_HP_MEM1_MASK_V 0x0000001FU #define PMU_PD_HP_MEM1_MASK_S 22 /** PMU_PD_HP_MEM0_MASK : R/W; bitpos: [31:27]; default: 0; - * need_des + * Configures whether to force power up Internal SRAM0. + * 0: Do not force power up + * 1: Force power up */ #define PMU_PD_HP_MEM0_MASK 0x0000001FU #define PMU_PD_HP_MEM0_MASK_M (PMU_PD_HP_MEM0_MASK_V << PMU_PD_HP_MEM0_MASK_S) @@ -2290,18 +2697,22 @@ extern "C" { #define PMU_PD_HP_MEM0_MASK_S 27 /** PMU_POWER_HP_PAD_REG register - * need_des + * Configuration register for HP GPIOs power supply controlled by PMU */ #define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; - * need_des + * Configures whether or not to disable HP GPIOs to enable ISO signal. This setting has a lower priority than PMU_FORCE_HP_PAD_ISO_ALL. + * 0: No effect + * 1: Disable */ #define PMU_FORCE_HP_PAD_NO_ISO_ALL (BIT(0)) #define PMU_FORCE_HP_PAD_NO_ISO_ALL_M (PMU_FORCE_HP_PAD_NO_ISO_ALL_V << PMU_FORCE_HP_PAD_NO_ISO_ALL_S) #define PMU_FORCE_HP_PAD_NO_ISO_ALL_V 0x00000001U #define PMU_FORCE_HP_PAD_NO_ISO_ALL_S 0 /** PMU_FORCE_HP_PAD_ISO_ALL : R/W; bitpos: [1]; default: 0; - * need_des + * Configures whether or not to enable HP GPIOs to enable ISO signal. This setting has a higher priority than PMU_FORCE_HP_PAD_NO_ISO_ALL. + * 0: No effect + * 1: Enable */ #define PMU_FORCE_HP_PAD_ISO_ALL (BIT(1)) #define PMU_FORCE_HP_PAD_ISO_ALL_M (PMU_FORCE_HP_PAD_ISO_ALL_V << PMU_FORCE_HP_PAD_ISO_ALL_S) @@ -2309,25 +2720,27 @@ extern "C" { #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 /** PMU_POWER_VDD_SPI_CNTL_REG register - * need_des + * Configuration register for VDD_SPI power supply controlled by PMU */ #define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x11c) /** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; - * need_des + * Configures the number of cycles to delay before powering up or down the VDD_SPI cell. */ #define PMU_VDD_SPI_PWR_WAIT 0x000007FFU #define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) #define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU #define PMU_VDD_SPI_PWR_WAIT_S 18 /** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; - * need_des + * Configure the power switch signal of VDD_SPI cell of HP GPIOs. */ #define PMU_VDD_SPI_PWR_SW 0x00000003U #define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) #define PMU_VDD_SPI_PWR_SW_V 0x00000003U #define PMU_VDD_SPI_PWR_SW_S 29 /** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; - * need_des + * Configure to select the power switch control signals of VDD_SPI cell of HP GPIOs. + * 0: controlled by PMU + * 1: controlled by PMU_VDD_SPI_PWR_SW */ #define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) #define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) @@ -2335,18 +2748,18 @@ extern "C" { #define PMU_VDD_SPI_PWR_SEL_SW_S 31 /** PMU_POWER_CK_WAIT_CNTL_REG register - * need_des + * Configuration register for system waiting time after clock change controlled by PMU */ #define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x120) /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; - * need_des + * Configures the number of CLK_DYN_FAST_CLK cycles to delay the XTAL_CLK gate opening after XTAL_CLK powers up, ensuring clock stability during startup. */ #define PMU_WAIT_XTL_STABLE 0x0000FFFFU #define PMU_WAIT_XTL_STABLE_M (PMU_WAIT_XTL_STABLE_V << PMU_WAIT_XTL_STABLE_S) #define PMU_WAIT_XTL_STABLE_V 0x0000FFFFU #define PMU_WAIT_XTL_STABLE_S 0 /** PMU_WAIT_PLL_STABLE : R/W; bitpos: [31:16]; default: 256; - * need_des + * Configures the number of CLK_DYN_FAST_CLK cycles to delay the PLL_CLK gate opening after PLL_CLK powers up, ensuring clock stability during startup. */ #define PMU_WAIT_PLL_STABLE 0x0000FFFFU #define PMU_WAIT_PLL_STABLE_M (PMU_WAIT_PLL_STABLE_V << PMU_WAIT_PLL_STABLE_S) @@ -2354,11 +2767,13 @@ extern "C" { #define PMU_WAIT_PLL_STABLE_S 16 /** PMU_SLP_WAKEUP_CNTL0_REG register - * need_des + * Sleep request register */ #define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x124) /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; - * need_des + * Configures whether to switch the chip's PMU state to HP_SLEEP or LP_SLEEP. + * 0: Do not switch + * 1: Switch depending on the status of LP CPU. */ #define PMU_SLEEP_REQ (BIT(31)) #define PMU_SLEEP_REQ_M (PMU_SLEEP_REQ_V << PMU_SLEEP_REQ_S) @@ -2366,18 +2781,20 @@ extern "C" { #define PMU_SLEEP_REQ_S 31 /** PMU_SLP_WAKEUP_CNTL1_REG register - * need_des + * Sleep reject register */ #define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x128) /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; - * need_des + * Configures the sleep rejection source. For the mapping between values and sources please refer to Table link. */ #define PMU_SLEEP_REJECT_ENA 0x7FFFFFFFU #define PMU_SLEEP_REJECT_ENA_M (PMU_SLEEP_REJECT_ENA_V << PMU_SLEEP_REJECT_ENA_S) #define PMU_SLEEP_REJECT_ENA_V 0x7FFFFFFFU #define PMU_SLEEP_REJECT_ENA_S 0 /** PMU_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; - * need_des + * Configures whether to enable sleep rejection function. + * 0: Disable + * 1: Enable */ #define PMU_SLP_REJECT_EN (BIT(31)) #define PMU_SLP_REJECT_EN_M (PMU_SLP_REJECT_EN_V << PMU_SLP_REJECT_EN_S) @@ -2385,11 +2802,11 @@ extern "C" { #define PMU_SLP_REJECT_EN_S 31 /** PMU_SLP_WAKEUP_CNTL2_REG register - * need_des + * Wakeup source enable register */ #define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x12c) /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; - * need_des + * Configures wake-up source. For the mapping between values and sources please refer to Table link. */ #define PMU_WAKEUP_ENA 0xFFFFFFFFU #define PMU_WAKEUP_ENA_M (PMU_WAKEUP_ENA_V << PMU_WAKEUP_ENA_S) @@ -2397,25 +2814,25 @@ extern "C" { #define PMU_WAKEUP_ENA_S 0 /** PMU_SLP_WAKEUP_CNTL3_REG register - * need_des + * PMU state selection signal and waiting time register for sleep-Wakeup */ #define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x130) /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; - * need_des + * Configures the LP_SLEEP sleep/wakeup wait time. */ #define PMU_LP_MIN_SLP_VAL 0x000000FFU #define PMU_LP_MIN_SLP_VAL_M (PMU_LP_MIN_SLP_VAL_V << PMU_LP_MIN_SLP_VAL_S) #define PMU_LP_MIN_SLP_VAL_V 0x000000FFU #define PMU_LP_MIN_SLP_VAL_S 0 /** PMU_HP_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 0; - * need_des + * Configures the HP_SLEEP sleep/wakeup wait time. */ #define PMU_HP_MIN_SLP_VAL 0x000000FFU #define PMU_HP_MIN_SLP_VAL_M (PMU_HP_MIN_SLP_VAL_V << PMU_HP_MIN_SLP_VAL_S) #define PMU_HP_MIN_SLP_VAL_V 0x000000FFU #define PMU_HP_MIN_SLP_VAL_S 8 /** PMU_SLEEP_PRT_SEL : R/W; bitpos: [17:16]; default: 0; - * need_des + * Configures to select the configuration data for sleep start and sleep end events. */ #define PMU_SLEEP_PRT_SEL 0x00000003U #define PMU_SLEEP_PRT_SEL_M (PMU_SLEEP_PRT_SEL_V << PMU_SLEEP_PRT_SEL_S) @@ -2423,11 +2840,11 @@ extern "C" { #define PMU_SLEEP_PRT_SEL_S 16 /** PMU_SLP_WAKEUP_CNTL4_REG register - * need_des + * Sleep reject event clear register */ #define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x134) /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; - * need_des + * Write 1 to clear PMU_REJECT_CAUSE. */ #define PMU_SLP_REJECT_CAUSE_CLR (BIT(31)) #define PMU_SLP_REJECT_CAUSE_CLR_M (PMU_SLP_REJECT_CAUSE_CLR_V << PMU_SLP_REJECT_CAUSE_CLR_S) @@ -2435,18 +2852,18 @@ extern "C" { #define PMU_SLP_REJECT_CAUSE_CLR_S 31 /** PMU_SLP_WAKEUP_CNTL5_REG register - * need_des + * Waiting time register after Wakeup in LP_SLEEP and HP_SLEEP */ #define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x138) /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; - * need_des + * Configures the wait timer after the Modem wakeup. */ #define PMU_MODEM_WAIT_TARGET 0x000FFFFFU #define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S) #define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU #define PMU_MODEM_WAIT_TARGET_S 0 /** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1; - * need_des + * Configures the wait timer after turning on the analog power. */ #define PMU_LP_ANA_WAIT_TARGET 0x000000FFU #define PMU_LP_ANA_WAIT_TARGET_M (PMU_LP_ANA_WAIT_TARGET_V << PMU_LP_ANA_WAIT_TARGET_S) @@ -2454,18 +2871,18 @@ extern "C" { #define PMU_LP_ANA_WAIT_TARGET_S 24 /** PMU_SLP_WAKEUP_CNTL6_REG register - * need_des + * Waiting time register after Wakeup in HP_MODEM phase */ #define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x13c) /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; - * need_des + * Configures the HP_MODEM wakeup wait timer. */ #define PMU_SOC_WAKEUP_WAIT 0x000FFFFFU #define PMU_SOC_WAKEUP_WAIT_M (PMU_SOC_WAKEUP_WAIT_V << PMU_SOC_WAKEUP_WAIT_S) #define PMU_SOC_WAKEUP_WAIT_V 0x000FFFFFU #define PMU_SOC_WAKEUP_WAIT_S 0 /** PMU_SOC_WAKEUP_WAIT_CFG : R/W; bitpos: [31:30]; default: 0; - * need_des + * Configures to select the wait timer for HP_MODEM wakeup. */ #define PMU_SOC_WAKEUP_WAIT_CFG 0x00000003U #define PMU_SOC_WAKEUP_WAIT_CFG_M (PMU_SOC_WAKEUP_WAIT_CFG_V << PMU_SOC_WAKEUP_WAIT_CFG_S) @@ -2473,11 +2890,11 @@ extern "C" { #define PMU_SOC_WAKEUP_WAIT_CFG_S 30 /** PMU_SLP_WAKEUP_CNTL7_REG register - * need_des + * Waiting time register after Wakeup in HP_SWITCH phase */ #define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x140) /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; - * need_des + * Configures the HP_SWITCH wakeup wait timer. */ #define PMU_ANA_WAIT_TARGET 0x0000FFFFU #define PMU_ANA_WAIT_TARGET_M (PMU_ANA_WAIT_TARGET_V << PMU_ANA_WAIT_TARGET_S) @@ -2485,11 +2902,11 @@ extern "C" { #define PMU_ANA_WAIT_TARGET_S 16 /** PMU_SLP_WAKEUP_STATUS0_REG register - * need_des + * Wakeup event register */ #define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x144) /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; - * need_des + * Indicates the wake-up source. For the mapping between values and sources please refer to Table link. */ #define PMU_WAKEUP_CAUSE 0xFFFFFFFFU #define PMU_WAKEUP_CAUSE_M (PMU_WAKEUP_CAUSE_V << PMU_WAKEUP_CAUSE_S) @@ -2497,11 +2914,11 @@ extern "C" { #define PMU_WAKEUP_CAUSE_S 0 /** PMU_SLP_WAKEUP_STATUS1_REG register - * need_des + * Reset reject event register */ #define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x148) /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; - * need_des + * Indicates the wake-up rejection source. For the mapping between values and sources please refer to Table link. */ #define PMU_REJECT_CAUSE 0xFFFFFFFFU #define PMU_REJECT_CAUSE_M (PMU_REJECT_CAUSE_V << PMU_REJECT_CAUSE_S) @@ -2521,18 +2938,18 @@ extern "C" { #define PMU_I2C_POR_WAIT_TARGET_S 0 /** PMU_HP_CK_CNTL_REG register - * need_des + * PMU-set waiting time after ICG configuration adjustment */ #define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x150) /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; - * need_des + * Configures the number of wait cycles required after modifying the input configurations of the Integrated Clock Gating (ICG) module, ensuring the changes take effect and the clock signals stabilize. */ #define PMU_MODIFY_ICG_CNTL_WAIT 0x000000FFU #define PMU_MODIFY_ICG_CNTL_WAIT_M (PMU_MODIFY_ICG_CNTL_WAIT_V << PMU_MODIFY_ICG_CNTL_WAIT_S) #define PMU_MODIFY_ICG_CNTL_WAIT_V 0x000000FFU #define PMU_MODIFY_ICG_CNTL_WAIT_S 0 /** PMU_SWITCH_ICG_CNTL_WAIT : R/W; bitpos: [15:8]; default: 10; - * need_des + * Configures the number of wait cycles required after switching the Integrated Clock Gating (ICG) module to its modified configuration, ensuring the transition is properly completed. */ #define PMU_SWITCH_ICG_CNTL_WAIT 0x000000FFU #define PMU_SWITCH_ICG_CNTL_WAIT_M (PMU_SWITCH_ICG_CNTL_WAIT_V << PMU_SWITCH_ICG_CNTL_WAIT_S) @@ -2552,60 +2969,62 @@ extern "C" { #define PMU_POR_DONE_S 31 /** PMU_RF_PWC_REG register - * need_des + * Configuration for i2c and rf circuits controlled by PMU */ #define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x158) /** PMU_XPD_TC5G_I2C : R/W; bitpos: [24]; default: 0; - * need_des + * Configures the 5G transmitting output. */ #define PMU_XPD_TC5G_I2C (BIT(24)) #define PMU_XPD_TC5G_I2C_M (PMU_XPD_TC5G_I2C_V << PMU_XPD_TC5G_I2C_S) #define PMU_XPD_TC5G_I2C_V 0x00000001U #define PMU_XPD_TC5G_I2C_S 24 /** PMU_XPD_RX5G_I2C : R/W; bitpos: [25]; default: 0; - * need_des + * Configures the 5G receiving output. */ #define PMU_XPD_RX5G_I2C (BIT(25)) #define PMU_XPD_RX5G_I2C_M (PMU_XPD_RX5G_I2C_V << PMU_XPD_RX5G_I2C_S) #define PMU_XPD_RX5G_I2C_V 0x00000001U #define PMU_XPD_RX5G_I2C_S 25 /** PMU_PERIF_I2C_RSTB : R/W; bitpos: [26]; default: 0; - * need_des + * Configures the I2C reset. */ #define PMU_PERIF_I2C_RSTB (BIT(26)) #define PMU_PERIF_I2C_RSTB_M (PMU_PERIF_I2C_RSTB_V << PMU_PERIF_I2C_RSTB_S) #define PMU_PERIF_I2C_RSTB_V 0x00000001U #define PMU_PERIF_I2C_RSTB_S 26 /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; - * need_des + * Configures the I2C SDA output. + * 0: outputs 0 + * 1: outputs analog peripheral output */ #define PMU_XPD_PERIF_I2C (BIT(27)) #define PMU_XPD_PERIF_I2C_M (PMU_XPD_PERIF_I2C_V << PMU_XPD_PERIF_I2C_S) #define PMU_XPD_PERIF_I2C_V 0x00000001U #define PMU_XPD_PERIF_I2C_S 27 /** PMU_XPD_TXRF_I2C : R/W; bitpos: [28]; default: 0; - * need_des + * Configures the RF transmitting output. */ #define PMU_XPD_TXRF_I2C (BIT(28)) #define PMU_XPD_TXRF_I2C_M (PMU_XPD_TXRF_I2C_V << PMU_XPD_TXRF_I2C_S) #define PMU_XPD_TXRF_I2C_V 0x00000001U #define PMU_XPD_TXRF_I2C_S 28 /** PMU_XPD_RFRX_PBUS : R/W; bitpos: [29]; default: 0; - * need_des + * Configures the RF receiving output. */ #define PMU_XPD_RFRX_PBUS (BIT(29)) #define PMU_XPD_RFRX_PBUS_M (PMU_XPD_RFRX_PBUS_V << PMU_XPD_RFRX_PBUS_S) #define PMU_XPD_RFRX_PBUS_V 0x00000001U #define PMU_XPD_RFRX_PBUS_S 29 /** PMU_XPD_CKGEN_I2C : R/W; bitpos: [30]; default: 0; - * need_des + * Configures the 5G clock generation. */ #define PMU_XPD_CKGEN_I2C (BIT(30)) #define PMU_XPD_CKGEN_I2C_M (PMU_XPD_CKGEN_I2C_V << PMU_XPD_CKGEN_I2C_S) #define PMU_XPD_CKGEN_I2C_V 0x00000001U #define PMU_XPD_CKGEN_I2C_S 30 /** PMU_XPD_PLL_I2C : R/W; bitpos: [31]; default: 0; - * need_des + * Configures the PLL clock generation. */ #define PMU_XPD_PLL_I2C (BIT(31)) #define PMU_XPD_PLL_I2C_M (PMU_XPD_PLL_I2C_V << PMU_XPD_PLL_I2C_S) @@ -2613,11 +3032,11 @@ extern "C" { #define PMU_XPD_PLL_I2C_S 31 /** PMU_BACKUP_CFG_REG register - * need_des + * Configuration for backup clock frequency division controlled by PMU */ #define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; - * need_des + * Configures the division number of the backup clock. */ #define PMU_BACKUP_SYS_CLK_NO_DIV (BIT(31)) #define PMU_BACKUP_SYS_CLK_NO_DIV_M (PMU_BACKUP_SYS_CLK_NO_DIV_V << PMU_BACKUP_SYS_CLK_NO_DIV_S) @@ -2625,7 +3044,7 @@ extern "C" { #define PMU_BACKUP_SYS_CLK_NO_DIV_S 31 /** PMU_INT_RAW_REG register - * need_des + * PMU sleep/Wakeup raw interrupt */ #define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; @@ -2636,7 +3055,7 @@ extern "C" { #define PMU_LP_CPU_EXC_INT_RAW_V 0x00000001U #define PMU_LP_CPU_EXC_INT_RAW_S 27 /** PMU_SDIO_IDLE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * need_des + * The raw interrupt status of PMU_SDIO_IDLE_INT. */ #define PMU_SDIO_IDLE_INT_RAW (BIT(28)) #define PMU_SDIO_IDLE_INT_RAW_M (PMU_SDIO_IDLE_INT_RAW_V << PMU_SDIO_IDLE_INT_RAW_S) @@ -2650,14 +3069,14 @@ extern "C" { #define PMU_SW_INT_RAW_V 0x00000001U #define PMU_SW_INT_RAW_S 29 /** PMU_SOC_SLEEP_REJECT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * need_des + * The raw interrupt status of PMU_SOC_SLEEP_REJECT_INT. */ #define PMU_SOC_SLEEP_REJECT_INT_RAW (BIT(30)) #define PMU_SOC_SLEEP_REJECT_INT_RAW_M (PMU_SOC_SLEEP_REJECT_INT_RAW_V << PMU_SOC_SLEEP_REJECT_INT_RAW_S) #define PMU_SOC_SLEEP_REJECT_INT_RAW_V 0x00000001U #define PMU_SOC_SLEEP_REJECT_INT_RAW_S 30 /** PMU_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * need_des + * The raw interrupt status of PMU_SOC_WAKEUP_INT. */ #define PMU_SOC_WAKEUP_INT_RAW (BIT(31)) #define PMU_SOC_WAKEUP_INT_RAW_M (PMU_SOC_WAKEUP_INT_RAW_V << PMU_SOC_WAKEUP_INT_RAW_S) @@ -2665,7 +3084,7 @@ extern "C" { #define PMU_SOC_WAKEUP_INT_RAW_S 31 /** PMU_HP_INT_ST_REG register - * need_des + * PMU sleep/Wakeup status interrupt */ #define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; @@ -2676,7 +3095,7 @@ extern "C" { #define PMU_LP_CPU_EXC_INT_ST_V 0x00000001U #define PMU_LP_CPU_EXC_INT_ST_S 27 /** PMU_SDIO_IDLE_INT_ST : RO; bitpos: [28]; default: 0; - * need_des + * The masked interrupt status of PMU_SDIO_IDLE_INT. */ #define PMU_SDIO_IDLE_INT_ST (BIT(28)) #define PMU_SDIO_IDLE_INT_ST_M (PMU_SDIO_IDLE_INT_ST_V << PMU_SDIO_IDLE_INT_ST_S) @@ -2690,14 +3109,14 @@ extern "C" { #define PMU_SW_INT_ST_V 0x00000001U #define PMU_SW_INT_ST_S 29 /** PMU_SOC_SLEEP_REJECT_INT_ST : RO; bitpos: [30]; default: 0; - * need_des + * The masked interrupt status of PMU_SOC_SLEEP_REJECT_INT. */ #define PMU_SOC_SLEEP_REJECT_INT_ST (BIT(30)) #define PMU_SOC_SLEEP_REJECT_INT_ST_M (PMU_SOC_SLEEP_REJECT_INT_ST_V << PMU_SOC_SLEEP_REJECT_INT_ST_S) #define PMU_SOC_SLEEP_REJECT_INT_ST_V 0x00000001U #define PMU_SOC_SLEEP_REJECT_INT_ST_S 30 /** PMU_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; - * need_des + * The masked interrupt status of PMU_SOC_WAKEUP_INT. */ #define PMU_SOC_WAKEUP_INT_ST (BIT(31)) #define PMU_SOC_WAKEUP_INT_ST_M (PMU_SOC_WAKEUP_INT_ST_V << PMU_SOC_WAKEUP_INT_ST_S) @@ -2705,7 +3124,7 @@ extern "C" { #define PMU_SOC_WAKEUP_INT_ST_S 31 /** PMU_HP_INT_ENA_REG register - * need_des + * PMU sleep/Wakeup interrupt enable */ #define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; @@ -2716,7 +3135,7 @@ extern "C" { #define PMU_LP_CPU_EXC_INT_ENA_V 0x00000001U #define PMU_LP_CPU_EXC_INT_ENA_S 27 /** PMU_SDIO_IDLE_INT_ENA : R/W; bitpos: [28]; default: 0; - * need_des + * Write 1 to enable PMU_SDIO_IDLE_INT. */ #define PMU_SDIO_IDLE_INT_ENA (BIT(28)) #define PMU_SDIO_IDLE_INT_ENA_M (PMU_SDIO_IDLE_INT_ENA_V << PMU_SDIO_IDLE_INT_ENA_S) @@ -2730,14 +3149,14 @@ extern "C" { #define PMU_SW_INT_ENA_V 0x00000001U #define PMU_SW_INT_ENA_S 29 /** PMU_SOC_SLEEP_REJECT_INT_ENA : R/W; bitpos: [30]; default: 0; - * need_des + * Write 1 to enable PMU_SOC_SLEEP_REJECT_INT. */ #define PMU_SOC_SLEEP_REJECT_INT_ENA (BIT(30)) #define PMU_SOC_SLEEP_REJECT_INT_ENA_M (PMU_SOC_SLEEP_REJECT_INT_ENA_V << PMU_SOC_SLEEP_REJECT_INT_ENA_S) #define PMU_SOC_SLEEP_REJECT_INT_ENA_V 0x00000001U #define PMU_SOC_SLEEP_REJECT_INT_ENA_S 30 /** PMU_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; - * need_des + * Write 1 to enable PMU_SOC_WAKEUP_INT. */ #define PMU_SOC_WAKEUP_INT_ENA (BIT(31)) #define PMU_SOC_WAKEUP_INT_ENA_M (PMU_SOC_WAKEUP_INT_ENA_V << PMU_SOC_WAKEUP_INT_ENA_S) @@ -2745,7 +3164,7 @@ extern "C" { #define PMU_SOC_WAKEUP_INT_ENA_S 31 /** PMU_HP_INT_CLR_REG register - * need_des + * PMU sleep/Wakeup interrupt clear */ #define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; @@ -2756,7 +3175,7 @@ extern "C" { #define PMU_LP_CPU_EXC_INT_CLR_V 0x00000001U #define PMU_LP_CPU_EXC_INT_CLR_S 27 /** PMU_SDIO_IDLE_INT_CLR : WT; bitpos: [28]; default: 0; - * need_des + * Write 1 to clear PMU_SDIO_IDLE_INT. */ #define PMU_SDIO_IDLE_INT_CLR (BIT(28)) #define PMU_SDIO_IDLE_INT_CLR_M (PMU_SDIO_IDLE_INT_CLR_V << PMU_SDIO_IDLE_INT_CLR_S) @@ -2770,14 +3189,14 @@ extern "C" { #define PMU_SW_INT_CLR_V 0x00000001U #define PMU_SW_INT_CLR_S 29 /** PMU_SOC_SLEEP_REJECT_INT_CLR : WT; bitpos: [30]; default: 0; - * need_des + * Write 1 to clear PMU_SOC_SLEEP_REJECT_INT. */ #define PMU_SOC_SLEEP_REJECT_INT_CLR (BIT(30)) #define PMU_SOC_SLEEP_REJECT_INT_CLR_M (PMU_SOC_SLEEP_REJECT_INT_CLR_V << PMU_SOC_SLEEP_REJECT_INT_CLR_S) #define PMU_SOC_SLEEP_REJECT_INT_CLR_V 0x00000001U #define PMU_SOC_SLEEP_REJECT_INT_CLR_S 30 /** PMU_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; - * need_des + * Write 1 to clear PMU_SOC_WAKEUP_INT. */ #define PMU_SOC_WAKEUP_INT_CLR (BIT(31)) #define PMU_SOC_WAKEUP_INT_CLR_M (PMU_SOC_WAKEUP_INT_CLR_V << PMU_SOC_WAKEUP_INT_CLR_S) @@ -2785,7 +3204,7 @@ extern "C" { #define PMU_SOC_WAKEUP_INT_CLR_S 31 /** PMU_LP_INT_RAW_REG register - * need_des + * Low-power system raw interrupt */ #define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; @@ -2796,70 +3215,70 @@ extern "C" { #define PMU_LP_CPU_WAKEUP_INT_RAW_V 0x00000001U #define PMU_LP_CPU_WAKEUP_INT_RAW_S 20 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; - * need_des + * The raw interrupt status of PMU_MODEM_SWITCH_ACTIVE_END_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW (BIT(21)) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_END_INT_RAW_S 21 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; - * need_des + * The raw interrupt status of PMU_SLEEP_SWITCH_ACTIVE_END_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW (BIT(22)) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_RAW_S 22 /** PMU_SLEEP_SWITCH_MODEM_END_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; - * need_des + * The raw interrupt status of PMU_SLEEP_SWITCH_MODEM_END_INT. */ #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW (BIT(23)) #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S) #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_END_INT_RAW_S 23 /** PMU_MODEM_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; - * need_des + * The raw interrupt status of PMU_MODEM_SWITCH_SLEEP_END_INT. */ #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW (BIT(24)) #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S) #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_END_INT_RAW_S 24 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; - * need_des + * The raw interrupt status of PMU_ACTIVE_SWITCH_SLEEP_END_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW (BIT(25)) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_V 0x00000001U #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_RAW_S 25 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; - * need_des + * The raw interrupt status of PMU_MODEM_SWITCH_ACTIVE_START_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW (BIT(26)) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_START_INT_RAW_S 26 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; - * need_des + * The raw interrupt status of PMU_SLEEP_SWITCH_ACTIVE_START_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW (BIT(27)) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_RAW_S 27 /** PMU_SLEEP_SWITCH_MODEM_START_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * need_des + * The raw interrupt status of PMU_SLEEP_SWITCH_MODEM_START_INT. */ #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW (BIT(28)) #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_M (PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V << PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S) #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_START_INT_RAW_S 28 /** PMU_MODEM_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * need_des + * The raw interrupt status of PMU_MODEM_SWITCH_SLEEP_START_INT. */ #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW (BIT(29)) #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_M (PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V << PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S) #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_START_INT_RAW_S 29 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * need_des + * The raw interrupt status of PMU_ACTIVE_SWITCH_SLEEP_START_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW (BIT(30)) #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_RAW_S) @@ -2874,7 +3293,7 @@ extern "C" { #define PMU_HP_SW_TRIGGER_INT_RAW_S 31 /** PMU_LP_INT_ST_REG register - * need_des + * PMU state transition interrupt status */ #define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; @@ -2885,70 +3304,70 @@ extern "C" { #define PMU_LP_CPU_WAKEUP_INT_ST_V 0x00000001U #define PMU_LP_CPU_WAKEUP_INT_ST_S 20 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [21]; default: 0; - * need_des + * The masked interrupt status of PMU_MODEM_SWITCH_ACTIVE_END_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST (BIT(21)) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ST_S 21 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST : RO; bitpos: [22]; default: 0; - * need_des + * The masked interrupt status of PMU_SLEEP_SWITCH_ACTIVE_END_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST (BIT(22)) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ST_S 22 /** PMU_SLEEP_SWITCH_MODEM_END_INT_ST : RO; bitpos: [23]; default: 0; - * need_des + * The masked interrupt status of PMU_SLEEP_SWITCH_MODEM_END_INT. */ #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST (BIT(23)) #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S) #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_END_INT_ST_S 23 /** PMU_MODEM_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [24]; default: 0; - * need_des + * The masked interrupt status of PMU_MODEM_SWITCH_SLEEP_END_INT. */ #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST (BIT(24)) #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S) #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_END_INT_ST_S 24 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST : RO; bitpos: [25]; default: 0; - * need_des + * The masked interrupt status of PMU_ACTIVE_SWITCH_SLEEP_END_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST (BIT(25)) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_V 0x00000001U #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ST_S 25 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [26]; default: 0; - * need_des + * The masked interrupt status of PMU_MODEM_SWITCH_ACTIVE_START_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST (BIT(26)) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ST_S 26 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST : RO; bitpos: [27]; default: 0; - * need_des + * The masked interrupt status of PMU_SLEEP_SWITCH_ACTIVE_START_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST (BIT(27)) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ST_S 27 /** PMU_SLEEP_SWITCH_MODEM_START_INT_ST : RO; bitpos: [28]; default: 0; - * need_des + * The masked interrupt status of PMU_SLEEP_SWITCH_MODEM_START_INT. */ #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST (BIT(28)) #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S) #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_START_INT_ST_S 28 /** PMU_MODEM_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [29]; default: 0; - * need_des + * The masked interrupt status of PMU_MODEM_SWITCH_SLEEP_START_INT. */ #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST (BIT(29)) #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S) #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_START_INT_ST_S 29 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST : RO; bitpos: [30]; default: 0; - * need_des + * The masked interrupt status of PMU_ACTIVE_SWITCH_SLEEP_START_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST (BIT(30)) #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ST_S) @@ -2963,7 +3382,7 @@ extern "C" { #define PMU_HP_SW_TRIGGER_INT_ST_S 31 /** PMU_LP_INT_ENA_REG register - * need_des + * PMU state transition interrupt enable */ #define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; @@ -2974,70 +3393,70 @@ extern "C" { #define PMU_LP_CPU_WAKEUP_INT_ENA_V 0x00000001U #define PMU_LP_CPU_WAKEUP_INT_ENA_S 20 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [21]; default: 0; - * need_des + * Write 1 to enable PMU_MODEM_SWITCH_ACTIVE_END_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA (BIT(21)) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_END_INT_ENA_S 21 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA : R/W; bitpos: [22]; default: 0; - * need_des + * Write 1 to enable PMU_SLEEP_SWITCH_ACTIVE_END_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA (BIT(22)) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_ENA_S 22 /** PMU_SLEEP_SWITCH_MODEM_END_INT_ENA : R/W; bitpos: [23]; default: 0; - * need_des + * Write 1 to enable PMU_SLEEP_SWITCH_MODEM_END_INT. */ #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA (BIT(23)) #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S) #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_END_INT_ENA_S 23 /** PMU_MODEM_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [24]; default: 0; - * need_des + * Write 1 to enable PMU_MODEM_SWITCH_SLEEP_END_INT. */ #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA (BIT(24)) #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S) #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_END_INT_ENA_S 24 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA : R/W; bitpos: [25]; default: 0; - * need_des + * Write 1 to enable PMU_ACTIVE_SWITCH_SLEEP_END_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA (BIT(25)) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_V 0x00000001U #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_ENA_S 25 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [26]; default: 0; - * need_des + * Write 1 to enable PMU_MODEM_SWITCH_ACTIVE_START_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA (BIT(26)) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_START_INT_ENA_S 26 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA : R/W; bitpos: [27]; default: 0; - * need_des + * Write 1 to enable PMU_SLEEP_SWITCH_ACTIVE_START_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA (BIT(27)) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_ENA_S 27 /** PMU_SLEEP_SWITCH_MODEM_START_INT_ENA : R/W; bitpos: [28]; default: 0; - * need_des + * Write 1 to enable PMU_SLEEP_SWITCH_MODEM_START_INT. */ #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA (BIT(28)) #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_M (PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V << PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S) #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_START_INT_ENA_S 28 /** PMU_MODEM_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [29]; default: 0; - * need_des + * Write 1 to enable PMU_MODEM_SWITCH_SLEEP_START_INT. */ #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA (BIT(29)) #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_M (PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V << PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S) #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_START_INT_ENA_S 29 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA : R/W; bitpos: [30]; default: 0; - * need_des + * Write 1 to enable PMU_ACTIVE_SWITCH_SLEEP_START_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA (BIT(30)) #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_ENA_S) @@ -3052,7 +3471,7 @@ extern "C" { #define PMU_HP_SW_TRIGGER_INT_ENA_S 31 /** PMU_LP_INT_CLR_REG register - * need_des + * PMU state transition interrupt clear */ #define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; @@ -3063,70 +3482,70 @@ extern "C" { #define PMU_LP_CPU_WAKEUP_INT_CLR_V 0x00000001U #define PMU_LP_CPU_WAKEUP_INT_CLR_S 20 /** PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [21]; default: 0; - * need_des + * Write 1 to clear PMU_MODEM_SWITCH_ACTIVE_END_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR (BIT(21)) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S) #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_END_INT_CLR_S 21 /** PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR : WT; bitpos: [22]; default: 0; - * need_des + * Write 1 to clear PMU_SLEEP_SWITCH_ACTIVE_END_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR (BIT(22)) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S) #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_END_INT_CLR_S 22 /** PMU_SLEEP_SWITCH_MODEM_END_INT_CLR : WT; bitpos: [23]; default: 0; - * need_des + * Write 1 to clear PMU_SLEEP_SWITCH_MODEM_END_INT. */ #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR (BIT(23)) #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S) #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_END_INT_CLR_S 23 /** PMU_MODEM_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [24]; default: 0; - * need_des + * Write 1 to clear PMU_MODEM_SWITCH_SLEEP_END_INT. */ #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR (BIT(24)) #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S) #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_END_INT_CLR_S 24 /** PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR : WT; bitpos: [25]; default: 0; - * need_des + * Write 1 to clear PMU_ACTIVE_SWITCH_SLEEP_END_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR (BIT(25)) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S) #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_V 0x00000001U #define PMU_ACTIVE_SWITCH_SLEEP_END_INT_CLR_S 25 /** PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [26]; default: 0; - * need_des + * Write 1 to clear PMU_MODEM_SWITCH_ACTIVE_START_INT. */ #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR (BIT(26)) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_M (PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V << PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S) #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U #define PMU_MODEM_SWITCH_ACTIVE_START_INT_CLR_S 26 /** PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR : WT; bitpos: [27]; default: 0; - * need_des + * Write 1 to clear PMU_SLEEP_SWITCH_ACTIVE_START_INT. */ #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR (BIT(27)) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_M (PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V << PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S) #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_V 0x00000001U #define PMU_SLEEP_SWITCH_ACTIVE_START_INT_CLR_S 27 /** PMU_SLEEP_SWITCH_MODEM_START_INT_CLR : WT; bitpos: [28]; default: 0; - * need_des + * Write 1 to clear PMU_SLEEP_SWITCH_MODEM_START_INT. */ #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR (BIT(28)) #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_M (PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V << PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S) #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_V 0x00000001U #define PMU_SLEEP_SWITCH_MODEM_START_INT_CLR_S 28 /** PMU_MODEM_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [29]; default: 0; - * need_des + * Write 1 to clear PMU_MODEM_SWITCH_SLEEP_START_INT. */ #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR (BIT(29)) #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_M (PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V << PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S) #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_V 0x00000001U #define PMU_MODEM_SWITCH_SLEEP_START_INT_CLR_S 29 /** PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR : WT; bitpos: [30]; default: 0; - * need_des + * Write 1 to clear PMU_ACTIVE_SWITCH_SLEEP_START_INT. */ #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR (BIT(30)) #define PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_M (PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_V << PMU_ACTIVE_SWITCH_SLEEP_START_INT_CLR_S) @@ -3247,11 +3666,11 @@ extern "C" { #define PMU_HP_TRIGGER_LP_S 31 /** PMU_HP_REGULATOR_CFG_REG register - * need_des + * PMU-controlled update of digital regulator configuration */ #define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; - * need_des + * Configures to enable the digital regulator. */ #define PMU_DIG_REGULATOR_EN_CAL (BIT(31)) #define PMU_DIG_REGULATOR_EN_CAL_M (PMU_DIG_REGULATOR_EN_CAL_V << PMU_DIG_REGULATOR_EN_CAL_S) @@ -3471,11 +3890,11 @@ extern "C" { #define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 /** PMU_DATE_REG register - * need_des + * Version control */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x1a8) /** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36770128; - * need_des + * Version control register. */ #define PMU_PMU_DATE 0x7FFFFFFFU #define PMU_PMU_DATE_M (PMU_PMU_DATE_V << PMU_PMU_DATE_S) diff --git a/components/soc/esp32c61/register/soc/pmu_struct.h b/components/soc/esp32c61/register/soc/pmu_struct.h index a57f02ebb30..bb28782108b 100644 --- a/components/soc/esp32c61/register/soc/pmu_struct.h +++ b/components/soc/esp32c61/register/soc/pmu_struct.h @@ -208,7 +208,6 @@ typedef struct pmu_hp_hw_regmap_t{ pmu_hp_xtal_reg_t xtal; } pmu_hp_hw_regmap_t; -/** */ typedef union { struct { uint32_t reserved0: 21;