From 29d62fa6aecfec33166647a90c06b15ba1611039 Mon Sep 17 00:00:00 2001 From: Song Ruo Jing Date: Wed, 11 Feb 2026 15:37:12 +0800 Subject: [PATCH] feat(mspi): add clear log in psram mspi intr isr for addr misaligned error --- .../esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h | 1 + .../esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h | 1 + .../esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h | 1 + .../esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h | 1 + components/esp_hw_support/mspi/mspi_intr/mspi_intr.c | 4 ++-- components/esp_psram/system_layer/esp_psram_mspi.c | 6 ++++++ 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h b/components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h index 71b722efb28..9f3bd778e7d 100644 --- a/components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h +++ b/components/esp_hal_mspi/esp32c5/include/hal/psram_ctrlr_ll.h @@ -38,6 +38,7 @@ extern "C" { #define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1) #define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1 +#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1 #define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3) #define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4) #define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5) diff --git a/components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h b/components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h index 71b722efb28..9f3bd778e7d 100644 --- a/components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h +++ b/components/esp_hal_mspi/esp32c61/include/hal/psram_ctrlr_ll.h @@ -38,6 +38,7 @@ extern "C" { #define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1) #define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1 +#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1 #define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3) #define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4) #define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5) diff --git a/components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h b/components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h index 9071436ed33..7ce6c2d9f03 100644 --- a/components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h +++ b/components/esp_hal_mspi/esp32h4/include/hal/psram_ctrlr_ll.h @@ -38,6 +38,7 @@ extern "C" { #define PSRAM_CTRLR_LL_PMS_ATTR_READABLE (1<<1) #define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1 +#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1 #define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3) #define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4) #define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5) diff --git a/components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h b/components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h index 775e3d58f76..659a405fb01 100644 --- a/components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h +++ b/components/esp_hal_mspi/esp32p4/include/hal/psram_ctrlr_ll.h @@ -44,6 +44,7 @@ extern "C" { #define PSRAM_CTRLR_LL_THRESH_INT_SUPPORTED 1 #define PSRAM_CTRLR_LL_PMS_INT_SUPPORTED 1 +#define PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED 1 #define PSRAM_CTRLR_LL_EVENT_SLV_ST_END (1<<3) #define PSRAM_CTRLR_LL_EVENT_MST_ST_END (1<<4) #define PSRAM_CTRLR_LL_EVENT_ECC_ERR (1<<5) diff --git a/components/esp_hw_support/mspi/mspi_intr/mspi_intr.c b/components/esp_hw_support/mspi/mspi_intr/mspi_intr.c index 16d0488eaad..94628d26323 100644 --- a/components/esp_hw_support/mspi/mspi_intr/mspi_intr.c +++ b/components/esp_hw_support/mspi/mspi_intr/mspi_intr.c @@ -47,7 +47,7 @@ static void MSPI_ISR_ATTR mspi_isr_handler(void *arg) #if MSPI_LL_ECC_INT_SUPPORTED if (intr_events & MSPI_LL_EVENT_ECC_ERR) { - ESP_DRAM_LOGD(TAG, "ecc error"); + ESP_DRAM_LOGE(TAG, "ecc error"); is_ecc_error = true; } #endif @@ -58,7 +58,7 @@ static void MSPI_ISR_ATTR mspi_isr_handler(void *arg) #endif #if MSPI_LL_ADDR_INT_SUPPORTED if (intr_events & MSPI_LL_EVENT_AXI_RADDR_ERR) { - ESP_DRAM_LOGE(TAG, "read addr error"); + ESP_DRAM_LOGE(TAG, "read address invalid or misaligned"); } if (intr_events & MSPI_LL_EVENT_AXI_WADDR_ERR) { ESP_DRAM_LOGE(TAG, "write addr error"); diff --git a/components/esp_psram/system_layer/esp_psram_mspi.c b/components/esp_psram/system_layer/esp_psram_mspi.c index 5d8d5af8647..66d07792195 100644 --- a/components/esp_psram/system_layer/esp_psram_mspi.c +++ b/components/esp_psram/system_layer/esp_psram_mspi.c @@ -45,6 +45,11 @@ static void PSRAM_ISR_ATTR mspi_psram_isr_handler(void *arg, uint32_t intr_event ESP_DRAM_LOGE(TAG, "psram pms reject"); } #endif +#if PSRAM_CTRLR_LL_ADDR_INT_SUPPORTED + if (intr_events & PSRAM_CTRLR_LL_EVENT_AXI_RADDR_ERR) { + ESP_DRAM_LOGE(TAG, "psram read address invalid or misaligned"); + } +#endif #if PSRAM_CTRLR_LL_THRESH_INT_SUPPORTED if (intr_events & PSRAM_CTRLR_LL_EVENT_RX_TRANS_OVF) { ESP_DRAM_LOGE(TAG, "psram rx trans overflow"); @@ -67,6 +72,7 @@ static void PSRAM_ISR_ATTR mspi_psram_isr_handler_wrapper(void *arg) psram_ctrlr_ll_clear_intr(PSRAM_CTRLR_LL_MSPI_ID_SYSTEM, intr_events); ESP_DRAM_LOGE(TAG, "MSPI PSRAM error"); + ESP_DRAM_LOGD(TAG, "intr_events: 0x%" PRIx32, intr_events); mspi_psram_isr_handler(arg, intr_events);