From 41b52821466ef9e53e228e523df33a730d44fb08 Mon Sep 17 00:00:00 2001 From: wanckl Date: Mon, 31 Aug 2026 20:58:31 +0800 Subject: [PATCH 1/2] refactor(driver_spi): ll header remove unused macro undef --- components/esp_hal_gpspi/esp32/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h | 2 ++ components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h | 1 - components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h | 1 - 13 files changed, 2 insertions(+), 12 deletions(-) diff --git a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h index 90025ae2587..e3f2fa9ab37 100644 --- a/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32/include/hal/spi_ll.h @@ -1300,7 +1300,6 @@ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) return 0; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK #ifdef __cplusplus diff --git a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h index e90d2d88bb6..5abbde05ce9 100644 --- a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h @@ -1612,7 +1612,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slave.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK #ifdef __cplusplus diff --git a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h index 223c297aafa..915e4f050a4 100644 --- a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h @@ -1531,7 +1531,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slave.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h index 2f197801709..be8522f0f4e 100644 --- a/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h @@ -1220,7 +1220,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.slv_last_addr; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h index 7006df33fa9..cb38a838b60 100644 --- a/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h @@ -1516,7 +1516,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slave.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h index 31aa102ce01..02c0dfaa727 100644 --- a/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h @@ -1220,7 +1220,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.slv_last_addr; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h index 814d0e4f0c1..52529adf64f 100644 --- a/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h @@ -1523,7 +1523,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slave.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h index 1e7331c3d3f..1d044f1856f 100644 --- a/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h @@ -1597,6 +1597,8 @@ static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) return 8; } +#undef SPI_LL_UNUSED_INT_MASK + #ifdef __cplusplus } #endif diff --git a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h index ba6cd597220..b58b69ecbc1 100644 --- a/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h @@ -1241,7 +1241,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.slv_last_addr; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h index 250ad57f826..cc85d14d3ad 100644 --- a/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h @@ -1302,7 +1302,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.slv_last_addr; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h index 529a6138a6a..818ef713252 100644 --- a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h @@ -1911,7 +1911,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slv_rd_byte.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h index 209e9f561ce..cd1980bd59b 100644 --- a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h @@ -1573,7 +1573,6 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value) hw->slave.dma_seg_magic_value = magic_value; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** diff --git a/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h index fa89d272182..ebdb4a03bf3 100644 --- a/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s31/include/hal/spi_ll.h @@ -1298,7 +1298,6 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.slv_last_addr; } -#undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK /** From 236a12a51b542d215ffcf3f1e8f813ff236f609f Mon Sep 17 00:00:00 2001 From: wanckl Date: Thu, 3 Sep 2026 14:41:36 +0800 Subject: [PATCH 2/2] fix(driver_spi): re-generate spi_struct header for old chip --- .../esp32c2/include/hal/spi_ll.h | 62 +- .../esp32c3/include/hal/spi_ll.h | 64 +- .../esp32s2/include/hal/spi_ll.h | 86 +- .../esp32s3/include/hal/spi_ll.h | 66 +- .../esp32c2/include/hal/gpspi_flash_ll.h | 12 +- .../esp32c3/include/hal/gpspi_flash_ll.h | 12 +- .../esp32s2/include/hal/gpspi_flash_ll.h | 10 +- .../esp32s3/include/hal/gpspi_flash_ll.h | 12 +- .../soc/esp32c2/register/soc/spi_struct.h | 1774 +++++++--- .../soc/esp32c3/register/soc/spi_struct.h | 1611 +++++++-- .../soc/esp32s2/register/soc/spi_struct.h | 2982 +++++++++++++---- .../soc/esp32s3/register/soc/spi_struct.h | 1771 +++++++--- 12 files changed, 6398 insertions(+), 2064 deletions(-) diff --git a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h index 5abbde05ce9..c1f5132a6d4 100644 --- a/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h @@ -199,9 +199,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->clk_gate.mst_clk_sel = 1; hw->dma_conf.val = 0; - hw->dma_conf.tx_seg_trans_clr_en = 1; - hw->dma_conf.rx_seg_trans_clr_en = 1; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -226,7 +226,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) // Configure DMA In-Link to not be terminated when transaction bit counter exceeds hw->dma_conf.rx_eof_en = 0; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; //Disable unneeded ints hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; @@ -283,7 +283,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) */ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) { - return hw->dma_int_raw.trans_done; + return hw->dma_int_raw.trans_done_int_raw; } /** @@ -374,7 +374,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->dma_int_clr.infifo_full_err = 1; + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; } /** @@ -384,7 +384,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->dma_int_clr.outfifo_empty_err = 1; + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; } /*------------------------------------------------------------------------------ @@ -672,7 +672,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li */ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -1004,11 +1004,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ addr = HAL_SWAP32(addr); //otherwise only addr register is sent - hw->addr = addr; + hw->addr.val = addr; } else { // shift the address to MSB of addr register. // output address will be sent from MSB to LSB of addr register - hw->addr = addr << (32 - addrlen); + hw->addr.val = addr << (32 - addrlen); } } @@ -1084,7 +1084,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - return hw->slave1.data_bitlen; + return hw->slave1.slv_data_bitlen; } /*------------------------------------------------------------------------------ @@ -1093,16 +1093,16 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { @@ -1150,7 +1150,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 0; + hw->dma_int_ena.trans_done_int_ena = 0; } /** @@ -1160,7 +1160,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - hw->dma_int_clr.trans_done = 1; + hw->dma_int_clr.trans_done_int_clr = 1; } /** @@ -1180,7 +1180,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 1; + hw->dma_int_ena.trans_done_int_ena = 1; } /*------------------------------------------------------------------------------ @@ -1188,20 +1188,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - return hw->slave1.data_bitlen / 8; + return hw->slave1.slv_data_bitlen / 8; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - return hw->slave1.last_addr; + return hw->slave1.slv_last_addr; } /** @@ -1574,7 +1574,7 @@ __attribute__((always_inline)) static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); - conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; + conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val; conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val; conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val; diff --git a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h index 915e4f050a4..83b7350a232 100644 --- a/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h @@ -204,9 +204,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->clk_gate.mst_clk_sel = 1; hw->dma_conf.val = 0; - hw->dma_conf.tx_seg_trans_clr_en = 1; - hw->dma_conf.rx_seg_trans_clr_en = 1; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -231,7 +231,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) // Configure DMA In-Link to not be terminated when transaction bit counter exceeds hw->dma_conf.rx_eof_en = 0; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; //Disable unneeded ints hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; @@ -288,7 +288,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) */ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) { - return hw->dma_int_raw.trans_done; + return hw->dma_int_raw.trans_done_int_raw; } /** @@ -379,7 +379,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->dma_int_clr.infifo_full_err = 1; + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; } /** @@ -389,7 +389,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->dma_int_clr.outfifo_empty_err = 1; + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; } /*------------------------------------------------------------------------------ @@ -677,7 +677,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li */ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -1009,11 +1009,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ addr = HAL_SWAP32(addr); //otherwise only addr register is sent - hw->addr = addr; + hw->addr.val = addr; } else { // shift the address to MSB of addr register. // output address will be sent from MSB to LSB of addr register - hw->addr = addr << (32 - addrlen); + hw->addr.val = addr << (32 - addrlen); } } @@ -1089,7 +1089,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - return hw->slave1.data_bitlen; + return hw->slave1.slv_data_bitlen; } /*------------------------------------------------------------------------------ @@ -1098,16 +1098,16 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done=1) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done=1) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done=1) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done=1) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done=1) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done=1) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr=1) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr=1) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr=1) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr=1) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr=1) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr=1) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr=1) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr=1) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr=1) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr=1) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { @@ -1155,7 +1155,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 0; + hw->dma_int_ena.trans_done_int_ena = 0; } /** @@ -1165,7 +1165,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - hw->dma_int_raw.trans_done = 0; + hw->dma_int_raw.trans_done_int_raw = 0; } /** @@ -1175,7 +1175,7 @@ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) */ static inline void spi_ll_set_int_stat(spi_dev_t *hw) { - hw->dma_int_raw.trans_done = 1; + hw->dma_int_raw.trans_done_int_raw = 1; } /** @@ -1185,7 +1185,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 1; + hw->dma_int_ena.trans_done_int_ena = 1; } /*------------------------------------------------------------------------------ @@ -1193,20 +1193,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - return hw->slave1.data_bitlen / 8; + return hw->slave1.slv_data_bitlen / 8; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - return hw->slave1.last_addr; + return hw->slave1.slv_last_addr; } /*------------------------------------------------------------------------------ @@ -1493,7 +1493,7 @@ __attribute__((always_inline)) static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); - conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; + conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val; conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val; conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val; diff --git a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h index 818ef713252..7ab0b8075b5 100644 --- a/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h @@ -384,8 +384,8 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->dma_conf.infifo_full_clr = 1; - hw->dma_conf.infifo_full_clr = 0; + hw->dma_conf.dma_infifo_full_clr = 1; + hw->dma_conf.dma_infifo_full_clr = 0; } /** @@ -395,8 +395,8 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->dma_conf.outfifo_empty_clr = 1; - hw->dma_conf.outfifo_empty_clr = 0; + hw->dma_conf.dma_outfifo_empty_clr = 1; + hw->dma_conf.dma_outfifo_empty_clr = 0; } /*------------------------------------------------------------------------------ @@ -670,7 +670,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -930,7 +930,7 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup) */ static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en) { - hw->dma_conf.dma_seg_trans_en = en; + hw->dma_conf.dma_slv_seg_trans_en = en; } /*------------------------------------------------------------------------------ @@ -944,7 +944,7 @@ static inline void spi_ll_slave_set_seg_en(spi_dev_t *hw, bool en) */ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) { - hw->miso_dlen.usr_miso_bit_len = bitlen - 1; + hw->miso_dlen.usr_miso_dbitlen = bitlen - 1; } /** @@ -955,7 +955,7 @@ static inline void spi_ll_set_miso_bitlen(spi_dev_t *hw, size_t bitlen) */ static inline void spi_ll_set_mosi_bitlen(spi_dev_t *hw, size_t bitlen) { - hw->mosi_dlen.usr_mosi_bit_len = bitlen - 1; + hw->mosi_dlen.usr_mosi_dbitlen = bitlen - 1; } /** @@ -1042,11 +1042,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ addr = HAL_SWAP32(addr); //otherwise only addr register is sent - hw->addr = addr; + hw->addr.val = addr; } else { // shift the address to MSB of addr register. // output address will be sent from MSB to LSB of addr register - hw->addr = addr << (32 - addrlen); + hw->addr.val = addr << (32 - addrlen); } } @@ -1116,7 +1116,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - return hw->slv_rd_byte.data_bytelen * 8; + return hw->slv_rd_byte.slv_data_bytelen * 8; } /*------------------------------------------------------------------------------ @@ -1126,21 +1126,21 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ item(SPI_LL_INTR_TRANS_DONE, slave.int_trans_done_en, slave.trans_done, slave.trans_done=0) \ - item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.rd_buf_done, slv_rdbuf_dlen.rd_buf_done=0) \ - item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.wr_buf_done, slv_wrbuf_dlen.wr_buf_done=0) \ - item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.rd_dma_done, slv_rd_byte.rd_dma_done=0) \ - item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.wr_dma_done, slave1.wr_dma_done=0) \ + item(SPI_LL_INTR_RDBUF, slave.int_rd_buf_done_en, slv_rdbuf_dlen.slv_rd_buf_done, slv_rdbuf_dlen.slv_rd_buf_done=0) \ + item(SPI_LL_INTR_WRBUF, slave.int_wr_buf_done_en, slv_wrbuf_dlen.slv_wr_buf_done, slv_wrbuf_dlen.slv_wr_buf_done=0) \ + item(SPI_LL_INTR_RDDMA, slave.int_rd_dma_done_en, slv_rd_byte.slv_rd_dma_done, slv_rd_byte.slv_rd_dma_done=0) \ + item(SPI_LL_INTR_WRDMA, slave.int_wr_dma_done_en, slave1.slv_wr_dma_done, slave1.slv_wr_dma_done=0) \ item(SPI_LL_INTR_SEG_DONE, slave.int_dma_seg_trans_en, hold.dma_seg_trans_done, hold.dma_seg_trans_done=0) \ - item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof, dma_int_raw.in_suc_eof, dma_int_clr.in_suc_eof=1) \ - item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof, dma_int_raw.out_eof, dma_int_clr.out_eof=1) \ - item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof, dma_int_raw.out_total_eof, dma_int_clr.out_total_eof=1) \ - item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err=1) \ - item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err=1) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7=1) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8=1) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9=1) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda=1) \ - item(SPI_LL_INTR_OUT_DONE, dma_int_ena.out_done, dma_int_raw.out_done, dma_int_clr.out_done=1) + item(SPI_LL_INTR_IN_SUC_EOF, dma_int_ena.in_suc_eof_int_ena, dma_int_raw.in_suc_eof_int_raw, dma_int_clr.in_suc_eof_int_clr=1) \ + item(SPI_LL_INTR_OUT_EOF, dma_int_ena.out_eof_int_ena, dma_int_raw.out_eof_int_raw, dma_int_clr.out_eof_int_clr=1) \ + item(SPI_LL_INTR_OUT_TOTAL_EOF, dma_int_ena.out_total_eof_int_ena, dma_int_raw.out_total_eof_int_raw, dma_int_clr.out_total_eof_int_clr=1) \ + item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err_int_ena, dma_int_raw.infifo_full_err_int_raw, dma_int_clr.infifo_full_err_int_clr=1) \ + item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err_int_ena, dma_int_raw.outfifo_empty_err_int_raw, dma_int_clr.outfifo_empty_err_int_clr=1) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr=1) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr=1) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr=1) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr=1) \ + item(SPI_LL_INTR_OUT_DONE, dma_int_ena.out_done_int_ena, dma_int_raw.out_done_int_raw, dma_int_clr.out_done_int_clr=1) __attribute__((always_inline)) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) @@ -1230,20 +1230,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - hw->slv_rd_byte.rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - hw->slv_rd_byte.wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - hw->slv_rd_byte.rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - hw->slv_rd_byte.wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; + hw->slv_rd_byte.slv_rdbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slv_rd_byte.slv_wrbuf_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slv_rd_byte.slv_rddma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slv_rd_byte.slv_wrdma_bytelen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - return hw->slv_rd_byte.data_bytelen; + return hw->slv_rd_byte.slv_data_bytelen; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, last_addr); + return HAL_FORCE_READ_U32_REG_FIELD(hw->slave1, slv_last_addr); } /*------------------------------------------------------------------------------ @@ -1343,8 +1343,8 @@ static inline void spi_ll_dma_rx_reset(spi_dma_dev_t *dma_in, uint32_t channel) __attribute__((always_inline)) static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, void *addr) { - dma_in->dma_in_link.addr = (int) addr & 0xFFFFF; - dma_in->dma_in_link.start = 1; + dma_in->dma_in_link.inlink_addr = (int) addr & 0xFFFFF; + dma_in->dma_in_link.inlink_start = 1; } /** @@ -1355,7 +1355,7 @@ static inline void spi_ll_dma_rx_start(spi_dma_dev_t *dma_in, uint32_t channel, */ static inline void spi_ll_dma_rx_stop(spi_dma_dev_t *dma_in, uint32_t channel) { - dma_in->dma_in_link.stop = 1; + dma_in->dma_in_link.inlink_stop = 1; } /** @@ -1393,7 +1393,7 @@ __attribute__((always_inline)) static inline uint32_t spi_ll_dma_get_in_suc_eof_desc_addr(spi_dma_dev_t *dma_in, uint32_t channel) { ESP_STATIC_ANALYZER_CHECK(!dma_in, -1); - return dma_in->dma_in_suc_eof_des_addr; + return dma_in->in_suc_eof_des_addr.val; } /** @@ -1435,8 +1435,8 @@ static inline void spi_ll_dma_tx_reset(spi_dma_dev_t *dma_out, uint32_t channel) __attribute__((always_inline)) static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, void *addr) { - dma_out->dma_out_link.addr = (int) addr & 0xFFFFF; - dma_out->dma_out_link.start = 1; + dma_out->dma_out_link.outlink_addr = (int) addr & 0xFFFFF; + dma_out->dma_out_link.outlink_start = 1; } /** @@ -1447,7 +1447,7 @@ static inline void spi_ll_dma_tx_start(spi_dma_dev_t *dma_out, uint32_t channel, */ static inline void spi_ll_dma_tx_stop(spi_dma_dev_t *dma_out, uint32_t channel) { - dma_out->dma_out_link.stop = 1; + dma_out->dma_out_link.outlink_stop = 1; } /** @@ -1509,17 +1509,17 @@ __attribute__((always_inline)) static inline uint32_t spi_ll_dma_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel) { ESP_STATIC_ANALYZER_CHECK(!dma_out, -1); - return dma_out->dma_out_eof_des_addr; + return dma_out->out_eof_des_addr.val; } static inline void spi_ll_dma_rx_restart(spi_dma_dev_t *dma_in, uint32_t channel) { - dma_in->dma_in_link.restart = 1; + dma_in->dma_in_link.inlink_restart = 1; } static inline void spi_ll_dma_tx_restart(spi_dma_dev_t *dma_out, uint32_t channel) { - dma_out->dma_out_link.restart = 1; + dma_out->dma_out_link.outlink_restart = 1; } static inline void spi_ll_dma_rx_disable(spi_dma_dev_t *dma_in) @@ -1534,7 +1534,7 @@ static inline void spi_ll_dma_tx_disable(spi_dma_dev_t *dma_out) static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw) { - return hw->dma_int_raw.outfifo_empty_err; + return hw->dma_int_raw.outfifo_empty_err_int_raw; } /*------------------------------------------------------------------------------ @@ -1861,7 +1861,7 @@ static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFFFFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); conf_buffer[SPI_LL_CMD_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->cmd.val; - conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; + conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val; conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val; conf_buffer[SPI_LL_CTRL1_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl1.val; conf_buffer[SPI_LL_CTRL2_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl2.val; diff --git a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h index cd1980bd59b..58f7a5d78d9 100644 --- a/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h +++ b/components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h @@ -215,9 +215,9 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->clk_gate.mst_clk_sel = 1; hw->dma_conf.val = 0; - hw->dma_conf.tx_seg_trans_clr_en = 1; - hw->dma_conf.rx_seg_trans_clr_en = 1; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.slv_tx_seg_trans_clr_en = 1; + hw->dma_conf.slv_rx_seg_trans_clr_en = 1; + hw->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -242,7 +242,7 @@ static inline void spi_ll_slave_init(spi_dev_t *hw) // Configure DMA In-Link to not be terminated when transaction bit counter exceeds hw->dma_conf.rx_eof_en = 0; - hw->dma_conf.dma_seg_trans_en = 0; + hw->dma_conf.dma_slv_seg_trans_en = 0; //Disable unneeded ints hw->dma_int_ena.val &= ~SPI_LL_UNUSED_INT_MASK; @@ -299,7 +299,7 @@ static inline void spi_ll_apply_config(spi_dev_t *hw) */ static inline bool spi_ll_usr_is_done(spi_dev_t *hw) { - return hw->dma_int_raw.trans_done; + return hw->dma_int_raw.trans_done_int_raw; } /** @@ -390,7 +390,7 @@ static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw) */ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) { - hw->dma_int_clr.infifo_full_err = 1; + hw->dma_int_clr.dma_infifo_full_err_int_clr = 1; } /** @@ -400,7 +400,7 @@ static inline void spi_ll_infifo_full_clr(spi_dev_t *hw) */ static inline void spi_ll_outfifo_empty_clr(spi_dev_t *hw) { - hw->dma_int_clr.outfifo_empty_err = 1; + hw->dma_int_clr.dma_outfifo_empty_err_int_clr = 1; } /*------------------------------------------------------------------------------ @@ -692,7 +692,7 @@ static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t li */ static inline void spi_ll_slave_set_seg_mode(spi_dev_t *hw, bool seg_trans) { - hw->dma_conf.dma_seg_trans_en = seg_trans; + hw->dma_conf.dma_slv_seg_trans_en = seg_trans; } /** @@ -1043,11 +1043,11 @@ static inline void spi_ll_set_address(spi_dev_t *hw, uint64_t addr, int addrlen, */ addr = HAL_SWAP32(addr); //otherwise only addr register is sent - hw->addr = addr; + hw->addr.val = addr; } else { // shift the address to MSB of addr register. // output address will be sent from MSB to LSB of addr register - hw->addr = addr << (32 - addrlen); + hw->addr.val = addr << (32 - addrlen); } } @@ -1124,7 +1124,7 @@ static inline void spi_ll_enable_mosi(spi_dev_t *hw, int enable) */ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) { - return hw->slave1.data_bitlen; + return hw->slave1.slv_data_bitlen; } /*------------------------------------------------------------------------------ @@ -1133,18 +1133,18 @@ static inline uint32_t spi_ll_slave_get_rcv_bitlen(spi_dev_t *hw) //helper macros to generate code for each interrupts #define FOR_EACH_ITEM(op, list) do { list(op) } while(0) #define INTR_LIST(item) \ - item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done, dma_int_raw.trans_done, dma_int_clr.trans_done, dma_int_set.trans_done_int_set) \ - item(SPI_LL_INTR_IN_FULL, dma_int_ena.infifo_full_err, dma_int_raw.infifo_full_err, dma_int_clr.infifo_full_err, dma_int_set.infifo_full_err_int_set) \ - item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.outfifo_empty_err, dma_int_raw.outfifo_empty_err, dma_int_clr.outfifo_empty_err, dma_int_set.outfifo_empty_err_int_set) \ - item(SPI_LL_INTR_RDBUF, dma_int_ena.rd_buf_done, dma_int_raw.rd_buf_done, dma_int_clr.rd_buf_done, dma_int_set.rd_buf_done_int_set) \ - item(SPI_LL_INTR_WRBUF, dma_int_ena.wr_buf_done, dma_int_raw.wr_buf_done, dma_int_clr.wr_buf_done, dma_int_set.wr_buf_done_int_set) \ - item(SPI_LL_INTR_RDDMA, dma_int_ena.rd_dma_done, dma_int_raw.rd_dma_done, dma_int_clr.rd_dma_done, dma_int_set.rd_dma_done_int_set) \ - item(SPI_LL_INTR_WRDMA, dma_int_ena.wr_dma_done, dma_int_raw.wr_dma_done, dma_int_clr.wr_dma_done, dma_int_set.wr_dma_done_int_set) \ - item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done, dma_int_raw.dma_seg_trans_done, dma_int_clr.dma_seg_trans_done, dma_int_set.dma_seg_trans_done_int_set) \ - item(SPI_LL_INTR_CMD7, dma_int_ena.cmd7, dma_int_raw.cmd7, dma_int_clr.cmd7, dma_int_set.cmd7_int_set) \ - item(SPI_LL_INTR_CMD8, dma_int_ena.cmd8, dma_int_raw.cmd8, dma_int_clr.cmd8, dma_int_set.cmd8_int_set) \ - item(SPI_LL_INTR_CMD9, dma_int_ena.cmd9, dma_int_raw.cmd9, dma_int_clr.cmd9, dma_int_set.cmd9_int_set) \ - item(SPI_LL_INTR_CMDA, dma_int_ena.cmda, dma_int_raw.cmda, dma_int_clr.cmda, dma_int_set.cmda_int_set) + item(SPI_LL_INTR_TRANS_DONE, dma_int_ena.trans_done_int_ena, dma_int_raw.trans_done_int_raw, dma_int_clr.trans_done_int_clr, dma_int_set.trans_done_int_set) \ + item(SPI_LL_INTR_IN_FULL, dma_int_ena.dma_infifo_full_err_int_ena, dma_int_raw.dma_infifo_full_err_int_raw, dma_int_clr.dma_infifo_full_err_int_clr, dma_int_set.dma_infifo_full_err_int_set) \ + item(SPI_LL_INTR_OUT_EMPTY, dma_int_ena.dma_outfifo_empty_err_int_ena, dma_int_raw.dma_outfifo_empty_err_int_raw, dma_int_clr.dma_outfifo_empty_err_int_clr, dma_int_set.dma_outfifo_empty_err_int_set) \ + item(SPI_LL_INTR_RDBUF, dma_int_ena.slv_rd_buf_done_int_ena, dma_int_raw.slv_rd_buf_done_int_raw, dma_int_clr.slv_rd_buf_done_int_clr, dma_int_set.slv_rd_buf_done_int_set) \ + item(SPI_LL_INTR_WRBUF, dma_int_ena.slv_wr_buf_done_int_ena, dma_int_raw.slv_wr_buf_done_int_raw, dma_int_clr.slv_wr_buf_done_int_clr, dma_int_set.slv_wr_buf_done_int_set) \ + item(SPI_LL_INTR_RDDMA, dma_int_ena.slv_rd_dma_done_int_ena, dma_int_raw.slv_rd_dma_done_int_raw, dma_int_clr.slv_rd_dma_done_int_clr, dma_int_set.slv_rd_dma_done_int_set) \ + item(SPI_LL_INTR_WRDMA, dma_int_ena.slv_wr_dma_done_int_ena, dma_int_raw.slv_wr_dma_done_int_raw, dma_int_clr.slv_wr_dma_done_int_clr, dma_int_set.slv_wr_dma_done_int_set) \ + item(SPI_LL_INTR_SEG_DONE, dma_int_ena.dma_seg_trans_done_int_ena, dma_int_raw.dma_seg_trans_done_int_raw, dma_int_clr.dma_seg_trans_done_int_clr, dma_int_set.dma_seg_trans_done_int_set) \ + item(SPI_LL_INTR_CMD7, dma_int_ena.slv_cmd7_int_ena, dma_int_raw.slv_cmd7_int_raw, dma_int_clr.slv_cmd7_int_clr, dma_int_set.slv_cmd7_int_set) \ + item(SPI_LL_INTR_CMD8, dma_int_ena.slv_cmd8_int_ena, dma_int_raw.slv_cmd8_int_raw, dma_int_clr.slv_cmd8_int_clr, dma_int_set.slv_cmd8_int_set) \ + item(SPI_LL_INTR_CMD9, dma_int_ena.slv_cmd9_int_ena, dma_int_raw.slv_cmd9_int_raw, dma_int_clr.slv_cmd9_int_clr, dma_int_set.slv_cmd9_int_set) \ + item(SPI_LL_INTR_CMDA, dma_int_ena.slv_cmda_int_ena, dma_int_raw.slv_cmda_int_raw, dma_int_clr.slv_cmda_int_clr, dma_int_set.slv_cmda_int_set) static inline void spi_ll_enable_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) { @@ -1192,7 +1192,7 @@ static inline bool spi_ll_get_intr(spi_dev_t *hw, spi_ll_intr_t intr_mask) */ static inline void spi_ll_disable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 0; + hw->dma_int_ena.trans_done_int_ena = 0; } /** @@ -1202,7 +1202,7 @@ static inline void spi_ll_disable_int(spi_dev_t *hw) */ static inline void spi_ll_clear_int_stat(spi_dev_t *hw) { - hw->dma_int_clr.trans_done = 1; + hw->dma_int_clr.trans_done_int_clr = 1; } /** @@ -1222,7 +1222,7 @@ static inline void spi_ll_set_int_stat(spi_dev_t *hw) */ static inline void spi_ll_enable_int(spi_dev_t *hw) { - hw->dma_int_ena.trans_done = 1; + hw->dma_int_ena.trans_done_int_ena = 1; } /*------------------------------------------------------------------------------ @@ -1230,20 +1230,20 @@ static inline void spi_ll_enable_int(spi_dev_t *hw) *----------------------------------------------------------------------------*/ static inline void spi_ll_slave_hd_set_len_cond(spi_dev_t *hw, spi_ll_trans_len_cond_t cond_mask) { - hw->slave.rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; - hw->slave.wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; - hw->slave.rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; - hw->slave.wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; + hw->slave.slv_rdbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDBUF) ? 1 : 0; + hw->slave.slv_wrbuf_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRBUF) ? 1 : 0; + hw->slave.slv_rddma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_RDDMA) ? 1 : 0; + hw->slave.slv_wrdma_bitlen_en = (cond_mask & SPI_LL_TRANS_LEN_COND_WRDMA) ? 1 : 0; } static inline int spi_ll_slave_get_rx_byte_len(spi_dev_t *hw) { - return hw->slave1.data_bitlen / 8; + return hw->slave1.slv_data_bitlen / 8; } static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) { - return hw->slave1.last_addr; + return hw->slave1.slv_last_addr; } /*------------------------------------------------------------------------------ @@ -1535,7 +1535,7 @@ __attribute__((always_inline)) static inline void spi_ll_init_conf_buffer(spi_dev_t *hw, uint32_t *conf_buffer) { conf_buffer[SPI_LL_CONF_BITMAP_POS] = 0x7FFF | (SPI_LL_SCT_MAGIC_NUMBER << 28); - conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr; + conf_buffer[SPI_LL_ADDR_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->addr.val; conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->ctrl.val; conf_buffer[SPI_LL_CLOCK_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->clock.val; conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] = hw->user.val; diff --git a/components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h b/components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h index d81c10fb21f..3b8fa9edc03 100644 --- a/components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h +++ b/components/esp_hal_mspi/esp32c2/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -48,9 +48,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev) dev->clk_gate.mst_clk_sel = 1; dev->dma_conf.val = 0; - dev->dma_conf.tx_seg_trans_clr_en = 1; - dev->dma_conf.rx_seg_trans_clr_en = 1; - dev->dma_conf.dma_seg_trans_en = 0; + dev->dma_conf.slv_tx_seg_trans_clr_en = 1; + dev->dma_conf.slv_rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -336,7 +336,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, { // The blank region should be all ones uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); - dev->addr = (addr << (32 - bitlen)) | padding_ones; + dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } /** @@ -347,7 +347,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, */ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) { - dev->addr = addr; + dev->addr.val = addr; } /** diff --git a/components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h b/components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h index 417848a0dc3..a028995e45f 100644 --- a/components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h +++ b/components/esp_hal_mspi/esp32c3/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,9 +49,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev) dev->clk_gate.mst_clk_sel = 1; dev->dma_conf.val = 0; - dev->dma_conf.tx_seg_trans_clr_en = 1; - dev->dma_conf.rx_seg_trans_clr_en = 1; - dev->dma_conf.dma_seg_trans_en = 0; + dev->dma_conf.slv_tx_seg_trans_clr_en = 1; + dev->dma_conf.slv_rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -336,7 +336,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, { // The blank region should be all ones uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); - dev->addr = (addr << (32 - bitlen)) | padding_ones; + dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } /** @@ -347,7 +347,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, */ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) { - dev->addr = addr; + dev->addr.val = addr; } /** diff --git a/components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h b/components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h index c9e1a2c9837..6244ef7999f 100644 --- a/components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h +++ b/components/esp_hal_mspi/esp32s2/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -265,7 +265,7 @@ static inline void gpspi_flash_ll_set_clock(spi_dev_t *dev, gpspi_flash_ll_clock static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitlen) { dev->user.usr_miso = bitlen > 0; - dev->miso_dlen.usr_miso_bit_len = bitlen ? (bitlen - 1) : 0; + dev->miso_dlen.usr_miso_dbitlen = bitlen ? (bitlen - 1) : 0; } /** @@ -278,7 +278,7 @@ static inline void gpspi_flash_ll_set_miso_bitlen(spi_dev_t *dev, uint32_t bitle static inline void gpspi_flash_ll_set_mosi_bitlen(spi_dev_t *dev, uint32_t bitlen) { dev->user.usr_mosi = bitlen > 0; - dev->mosi_dlen.usr_mosi_bit_len = bitlen ? (bitlen - 1) : 0; + dev->mosi_dlen.usr_mosi_dbitlen = bitlen ? (bitlen - 1) : 0; } /** @@ -331,7 +331,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, { // The blank region should be all ones uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); - dev->addr = (addr << (32 - bitlen)) | padding_ones; + dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } /** @@ -342,7 +342,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, */ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) { - dev->addr = addr; + dev->addr.val = addr; } /** diff --git a/components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h b/components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h index e4f57357167..943cc55c4a7 100644 --- a/components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h +++ b/components/esp_hal_mspi/esp32s3/include/hal/gpspi_flash_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,9 +55,9 @@ static inline void gpspi_flash_ll_reset(spi_dev_t *dev) dev->clk_gate.mst_clk_sel = 1; dev->dma_conf.val = 0; - dev->dma_conf.tx_seg_trans_clr_en = 1; - dev->dma_conf.rx_seg_trans_clr_en = 1; - dev->dma_conf.dma_seg_trans_en = 0; + dev->dma_conf.slv_tx_seg_trans_clr_en = 1; + dev->dma_conf.slv_rx_seg_trans_clr_en = 1; + dev->dma_conf.dma_slv_seg_trans_en = 0; } /** @@ -342,7 +342,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, { // The blank region should be all ones uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen); - dev->addr = (addr << (32 - bitlen)) | padding_ones; + dev->addr.val = (addr << (32 - bitlen)) | padding_ones; } /** @@ -353,7 +353,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, */ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr) { - dev->addr = addr; + dev->addr.val = addr; } /** diff --git a/components/soc/esp32c2/register/soc/spi_struct.h b/components/soc/esp32c2/register/soc/spi_struct.h index 0bbd2917e97..dc78ea7d830 100644 --- a/components/soc/esp32c2/register/soc/spi_struct.h +++ b/components/soc/esp32c2/register/soc/spi_struct.h @@ -1,420 +1,1380 @@ -/* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 OR MIT + * SPDX-License-Identifier: Apache-2.0 OR MIT */ -#ifndef _SOC_SPI_STRUCT_H_ -#define _SOC_SPI_STRUCT_H_ +#pragma once + +#include #ifdef __cplusplus extern "C" { #endif -#include "soc/soc.h" -typedef volatile struct spi_dev_s{ - union { - struct { - uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ - uint32_t reserved18 : 5; /*reserved*/ - uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/ - uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } cmd; - uint32_t addr; - union { - struct { - uint32_t reserved0 : 3; /*reserved*/ - uint32_t dummy_out : 1; /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved11 : 3; /*reserved*/ - uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ - uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ - uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ - }; - uint32_t val; - } clock; - union { - struct { - uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved1 : 2; /*reserved*/ - uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ - uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ - uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ - uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ - uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ - uint32_t reserved10 : 2; /*reserved*/ - uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ - uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ - uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ - uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved18 : 6; /*reserved*/ - uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ - uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ - }; - uint32_t val; - } user; - union { - struct { - uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ - uint32_t reserved8 : 8; /*reserved*/ - uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ - uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ - uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user1; - union { - struct { - uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/ - uint32_t reserved16 : 11; /*reserved*/ - uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user2; - union { - struct { - uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } ms_dlen; - union { - struct { - uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/ - uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ - uint32_t reserved13 : 3; /*reserved*/ - uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */ - uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ - uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ - uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ - uint32_t reserved20 : 3; /*reserved*/ - uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ - uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ - uint32_t reserved25 : 4; /*reserved*/ - uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ - uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ - uint32_t quad_din_pin_swap : 1; /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.*/ - }; - uint32_t val; - } misc; - union { - struct { - uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ - uint32_t reserved17 : 15; /*reserved*/ - }; - uint32_t val; - } din_mode; - union { - struct { - uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } din_num; - union { - struct { - uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t reserved9 : 23; /*reserved*/ - }; - uint32_t val; - } dout_mode; - union { - struct { - uint32_t dma_outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/ - uint32_t dma_infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ - uint32_t reserved2 : 16; /*reserved*/ - uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t reserved22 : 5; /*reserved*/ - uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ - uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ - uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ - uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ - uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - union { - struct { - uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */ - uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */ - uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ - uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ - uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ - uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ - uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ - uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ - uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ - uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ - uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ - uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ - uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ - uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */ - uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ - uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ - uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/ - uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/ - uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - union { - struct { - uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/ - uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_set; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t data_buf[16]; - uint32_t reserved_d8; - uint32_t reserved_dc; - union { - struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ - uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ - uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ - uint32_t reserved4 : 4; /*reserved*/ - uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ - uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ - uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ - uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ - uint32_t reserved12 : 10; /*reserved*/ - uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/ - uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ - uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/ - uint32_t reserved29 : 3; /*reserved*/ - }; - uint32_t val; - } slave; - union { - struct { - uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */ - uint32_t last_command : 8; /*In the slave mode it is the value of command.*/ - uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/ - }; - uint32_t val; - } slave1; - union { - struct { - uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ - uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/ - uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } clk_gate; - uint32_t reserved_ec; - union { - struct { - uint32_t date : 28; /*SPI register version.*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:10; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : HRO; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : HRO; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : HRO; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : HRO; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : HRO; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34627696; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile uint32_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; } spi_dev_t; + extern spi_dev_t GPSPI2; -extern spi_dev_t GPSPI3; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SPI_STRUCT_H_ */ diff --git a/components/soc/esp32c3/register/soc/spi_struct.h b/components/soc/esp32c3/register/soc/spi_struct.h index 03a765bd013..adfd4bd8d4f 100644 --- a/components/soc/esp32c3/register/soc/spi_struct.h +++ b/components/soc/esp32c3/register/soc/spi_struct.h @@ -1,368 +1,1275 @@ -/* - * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 OR MIT + * SPDX-License-Identifier: Apache-2.0 OR MIT */ + #pragma once #include + #ifdef __cplusplus extern "C" { #endif -typedef volatile struct spi_dev_s { - union { - struct { - uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ - uint32_t reserved18 : 5; /*reserved*/ - uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/ - uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } cmd; - uint32_t addr; - union { - struct { - uint32_t reserved0 : 3; /*reserved*/ - uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved7 : 1; /*reserved*/ - uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved10 : 4; /*reserved*/ - uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22 : 3; /*reserved*/ - uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ - uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ - uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ - }; - uint32_t val; - } clock; - union { - struct { - uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved1 : 2; /*reserved*/ - uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ - uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ - uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ - uint32_t reserved10 : 2; /*reserved*/ - uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ - uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ - uint32_t reserved14 : 1; /*reserved*/ - uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved18 : 6; /*reserved*/ - uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ - uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ - }; - uint32_t val; - } user; - union { - struct { - uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ - uint32_t reserved8 : 8; /*reserved*/ - uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ - uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ - uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user1; - union { - struct { - uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/ - uint32_t reserved16 : 11; /*reserved*/ - uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user2; - union { - struct { - uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } ms_dlen; - union { - struct { - uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/ - uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ - uint32_t reserved13 : 10; /*reserved*/ - uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ - uint32_t reserved24 : 5; /*reserved*/ - uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ - uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ - uint32_t quad_din_pin_swap : 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ - }; - uint32_t val; - } misc; - union { - struct { - uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t reserved8 : 8; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ - uint32_t reserved17 : 15; /*reserved*/ - }; - uint32_t val; - } din_mode; - union { - struct { - uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t reserved8 : 24; /*reserved*/ - }; - uint32_t val; - } din_num; - union { - struct { - uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t reserved4 : 28; /*reserved*/ - }; - uint32_t val; - } dout_mode; - union { - struct { - uint32_t reserved0 : 18; /*reserved*/ - uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t reserved22 : 5; /*reserved*/ - uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ - uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ - uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ - uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ - uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - union { - struct { - uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */ - uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */ - uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ - uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ - uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ - uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ - uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ - uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ - uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ - uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ - uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ - uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ - uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ - uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */ - uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ - uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ - uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/ - uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/ - uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - uint32_t reserved_44; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t data_buf[16]; - uint32_t reserved_d8; - uint32_t reserved_dc; - union { - struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ - uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ - uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ - uint32_t reserved4 : 4; /*reserved*/ - uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ - uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ - uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ - uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ - uint32_t reserved12 : 10; /*reserved*/ - uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/ - uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ - uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/ - uint32_t reserved29 : 3; /*reserved*/ - }; - uint32_t val; - } slave; - union { - struct { - uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */ - uint32_t last_command : 8; /*In the slave mode it is the value of command.*/ - uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/ - }; - uint32_t val; - } slave1; - union { - struct { - uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ - uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/ - uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } clk_gate; - uint32_t reserved_ec; - union { - struct { - uint32_t date : 28; /*SPI register version.*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : HRO; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : HRO; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : HRO; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : HRO; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : HRO; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:3; + /** rd_bit_order : R/W; bitpos: [24]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:1; + /** wr_bit_order : R/W; bitpos: [25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : HRO; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : HRO; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : HRO; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : HRO; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : HRO; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + uint32_t reserved_2:18; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:10; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : HRO; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : HRO; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : HRO; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : HRO; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : HRO; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : HRO; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : HRO; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : HRO; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : HRO; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : HRO; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : HRO; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : HRO; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : HRO; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : HRO; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : HRO; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : HRO; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : HRO; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : HRO; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 33583648; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + uint32_t reserved_044[21]; + volatile uint32_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; } spi_dev_t; extern spi_dev_t GPSPI2; +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + #ifdef __cplusplus } #endif diff --git a/components/soc/esp32s2/register/soc/spi_struct.h b/components/soc/esp32s2/register/soc/spi_struct.h index 396e6188671..e68bf4494e4 100644 --- a/components/soc/esp32s2/register/soc/spi_struct.h +++ b/components/soc/esp32s2/register/soc/spi_struct.h @@ -1,8 +1,9 @@ -/* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 OR MIT + * SPDX-License-Identifier: Apache-2.0 OR MIT */ + #pragma once #include @@ -11,746 +12,2251 @@ extern "C" { #endif -typedef volatile struct spi_dev_s { - union { - struct { - uint32_t conf_bitlen:23; /*Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state.*/ - uint32_t reserved23: 1; /*reserved*/ - uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ - uint32_t reserved25: 7; /*reserved*/ - }; - uint32_t val; - } cmd; - uint32_t addr; /*[31:8]:address to slave [7:0]:Reserved. Can be configured in CONF state.*/ - union { - struct { - uint32_t reserved0: 2; /*reserved*/ - uint32_t ext_hold_en: 1; /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol. Can be configured in CONF state.*/ - uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ - uint32_t reserved4: 1; /*reserved*/ - uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved11: 3; /*reserved*/ - uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved17: 1; /*reserved*/ - uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/ - uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/ - uint32_t reserved20: 1; /*reserved*/ - uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22: 3; /*reserved*/ - uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27: 5; /*reserved*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ - uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ - uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/ - uint32_t w16_17_wr_ena: 1; /*1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written. Can be configured in CONF state.*/ - uint32_t reserved5: 9; /*reserved*/ - uint32_t cs_hold_delay: 6; /*SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.*/ - uint32_t reserved20: 12; /*reserved*/ - }; - uint32_t val; - } ctrl1; - union { - struct { - uint32_t cs_setup_time:13; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ - uint32_t cs_hold_time: 13; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ - uint32_t cs_delay_mode: 3; /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state.*/ - uint32_t cs_delay_num: 2; /*spi_cs signal is delayed by system clock cycles. Can be configured in CONF state.*/ - uint32_t reserved31: 1; /*reserved*/ - }; - uint32_t val; - } ctrl2; - union { - struct { - uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ - uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ - uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ - }; - uint32_t val; - } clock; - union { - struct { - uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved1: 2; /*reserved*/ - uint32_t qpi_mode: 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ - uint32_t opi_mode: 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ - uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ - uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ - uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ - uint32_t rd_byte_order: 1; /*In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state.*/ - uint32_t wr_byte_order: 1; /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state.*/ - uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ - uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ - uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ - uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ - uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_hold_pol: 1; /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state.*/ - uint32_t usr_dout_hold: 1; /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_din_hold: 1; /*spi is hold at data in state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_dummy_hold: 1; /*spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_addr_hold: 1; /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_cmd_hold: 1; /*spi is hold at command state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_prep_hold: 1; /*spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit. Can be configured in CONF state.*/ - uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ - uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_addr: 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_command: 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ - }; - uint32_t val; - } user; - union { - struct { - uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ - uint32_t reserved8: 19; /*reserved*/ - uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user1; - union { - struct { - uint32_t usr_command_value: 16; /*The value of command. Can be configured in CONF state.*/ - uint32_t reserved16: 12; /*reserved*/ - uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user2; - union { - struct { - uint32_t usr_mosi_bit_len:23; /*The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved23: 9; /*reserved*/ - }; - uint32_t val; - } mosi_dlen; - union { - struct { - uint32_t usr_miso_bit_len:23; /*The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved23: 9; /*reserved*/ - }; - uint32_t val; - } miso_dlen; - union { - struct { - uint32_t cs0_dis: 1; /*SPI CS0 pin enable 1: disable CS0 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.*/ - uint32_t cs1_dis: 1; /*SPI CS1 pin enable 1: disable CS1 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.*/ - uint32_t cs2_dis: 1; /*SPI CS2 pin enable 1: disable CS2 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.*/ - uint32_t cs3_dis: 1; /*reserved*/ - uint32_t cs4_dis: 1; /*SPI CS4 pin enable 1: disable CS4 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.*/ - uint32_t cs5_dis: 1; /*SPI CS5 pin enable 1: disable CS5 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.*/ - uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ - uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ - uint32_t reserved13: 3; /*reserved*/ - uint32_t clk_data_dtr_en: 1; /*1: SPI master DTR mode is applied to SPI clk data and spi_dqs*/ - uint32_t data_dtr_en: 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/ - uint32_t addr_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/ - uint32_t cmd_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including master 1/2/4/8-bm. Can be configured in CONF state.*/ - uint32_t cd_data_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ - uint32_t cd_dummy_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ - uint32_t cd_addr_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ - uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ - uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ - uint32_t cd_cmd_set: 1; /*1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd = spi_cd_idle_edge. Can be configured in CONF state.*/ - uint32_t cd_idle_edge: 1; /*The default value of spi_cd. Can be configured in CONF state.*/ - uint32_t reserved27: 2; /*reserved*/ - uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ - uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ - uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ - }; - uint32_t val; - } misc; - union { - struct { - uint32_t reserved0: 4; /*reserved*/ - uint32_t trans_done: 1; /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf.*/ - uint32_t int_rd_buf_done_en: 1; /*spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t int_wr_buf_done_en: 1; /*spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t int_rd_dma_done_en: 1; /*spi_slv_rd_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t int_wr_dma_done_en: 1; /*spi_slv_wr_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t int_trans_done_en: 1; /*spi_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t int_dma_seg_trans_en: 1; /*spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t seg_magic_err_int_en: 1; /*1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state.*/ - uint32_t reserved12: 11; /*reserved*/ - uint32_t trans_cnt: 4; /*The operations counter in both the master mode and the slave mode.*/ - uint32_t reserved27: 1; /*reserved*/ - uint32_t reserved28: 1; /*reserved*/ - uint32_t trans_done_auto_clr_en: 1; /*spi_trans_done auto clear enable clear it 3 apb cycles after the pos edge of spi_trans_done. 0:disable. 1: enable. Can be configured in CONF state.*/ - uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t soft_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ - }; - uint32_t val; - } slave; - union { - struct { - uint32_t reserved0: 10; /*reserved*/ - uint32_t addr_err_clr: 1; /*1: Clear spi_slv_addr_err. 0: not valid. Can be changed by CONF_buf.*/ - uint32_t cmd_err_clr: 1; /*1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf.*/ - uint32_t no_qpi_en: 1; /*1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported.*/ - uint32_t addr_err: 1; /*1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received.*/ - uint32_t cmd_err: 1; /*1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received.*/ - uint32_t wr_dma_done: 1; /*The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf.*/ - uint32_t last_command: 8; /*In the slave mode it is the value of command.*/ - uint32_t last_addr: 8; /*In the slave mode it is the value of address.*/ - }; - uint32_t val; - } slave1; - union { - struct { - uint32_t reserved0: 24; /*reserved*/ - uint32_t wr_buf_done: 1; /*The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf.*/ - uint32_t conf_base_bitlen: 7; /*The basic spi_clk cycles of CONF state. The real cycle length of CONF state if spi_usr_conf is enabled is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0].*/ - }; - uint32_t val; - } slv_wrbuf_dlen; - union { - struct { - uint32_t dma_rd_bytelen: 20; /*In the slave mode it is the length in bytes for read operations. The register value shall be byte_num.*/ - uint32_t reserved20: 4; /*reserved*/ - uint32_t rd_buf_done: 1; /*The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf.*/ - uint32_t seg_magic_err: 1; /*1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others.*/ - uint32_t reserved26: 6; /*reserved*/ - }; - uint32_t val; - } slv_rdbuf_dlen; - union { - struct { - uint32_t data_bytelen: 20; /*The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode this value is controlled by bits [23:20].*/ - uint32_t rddma_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ - uint32_t wrdma_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ - uint32_t rdbuf_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ - uint32_t wrbuf_bytelen_en: 1; /*1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ - uint32_t dma_seg_magic_value: 4; /*The magic value of BM table in master DMA seg-trans.*/ - uint32_t reserved28: 2; /*reserved*/ - uint32_t rd_dma_done: 1; /*The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf.*/ - uint32_t usr_conf: 1; /*1: Enable the DMA CONF phase of current seg-trans operation which means seg-trans will start. 0: This is not seg-trans mode.*/ - }; - uint32_t val; - } slv_rd_byte; - union { - struct { - uint32_t st: 4; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ - uint32_t reserved4: 8; /*reserved*/ - uint32_t mst_dma_rd_bytelen:20; /*Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid when spi_rx_eof_en is 0. Can be configured in CONF state..*/ - }; - uint32_t val; - } fsm; - union { - struct { - uint32_t int_hold_ena: 2; /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state.*/ - uint32_t hold_val: 1; /*spi hold output value which should be used with spi_hold_out_en. Can be configured in CONF state.*/ - uint32_t hold_out_en: 1; /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF state.*/ - uint32_t hold_out_time: 3; /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable. Can be configured in CONF state.*/ - uint32_t dma_seg_trans_done: 1; /*1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf.*/ - uint32_t reserved8: 24; /*reserved*/ - }; - uint32_t val; - } hold; - union { - struct { - uint32_t reserved0: 2; /*reserved*/ - uint32_t in_rst: 1; /*The bit is used to reset in dma fsm and in data fifo pointer.*/ - uint32_t out_rst: 1; /*The bit is used to reset out dma fsm and out data fifo pointer.*/ - uint32_t ahbm_fifo_rst: 1; /*Reset spi dma ahb master fifo pointer.*/ - uint32_t ahbm_rst: 1; /*Reset spi dma ahb master.*/ - uint32_t in_loop_test: 1; /*Set bit to test in link.*/ - uint32_t out_loop_test: 1; /*Set bit to test out link.*/ - uint32_t out_auto_wrback: 1; /*when the bit is set DMA continue to use the next inlink node when the length of inlink is 0.*/ - uint32_t out_eof_mode: 1; /*out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo.*/ - uint32_t outdscr_burst_en: 1; /*read descriptor use burst mode when read data for memory.*/ - uint32_t indscr_burst_en: 1; /*read descriptor use burst mode when write data to memory.*/ - uint32_t out_data_burst_en: 1; /*spi dma read data from memory in burst mode.*/ - uint32_t mem_trans_en: 1; - uint32_t dma_rx_stop: 1; /*spi dma read data stop when in continue tx/rx mode.*/ - uint32_t dma_tx_stop: 1; /*spi dma write data stop when in continue tx/rx mode.*/ - uint32_t dma_continue: 1; /*spi dma continue tx/rx data.*/ - uint32_t last_seg_pop_clr: 1; /*1: Clear spi_slv_seg_frt_pop_mask. 0 : others*/ - uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t infifo_full_clr: 1; /*1:Clear spi_dma_infifo_full_vld. 0: Do not control it.*/ - uint32_t outfifo_empty_clr: 1; /*1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it.*/ - uint32_t reserved24: 2; /*reserved*/ - uint32_t ext_mem_bk_size: 2; /*Select the external memory block size.*/ - uint32_t dma_seg_trans_clr: 1; /*1: End slave seg-trans which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX.*/ - uint32_t reserved29: 3; /*reserved*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t addr: 20; /*The address of the first outlink descriptor.*/ - uint32_t reserved20: 8; /*reserved*/ - uint32_t stop: 1; /*Set the bit to stop to use outlink descriptor.*/ - uint32_t start: 1; /*Set the bit to start to use outlink descriptor.*/ - uint32_t restart: 1; /*Set the bit to mount on new outlink descriptors.*/ - uint32_t dma_tx_ena: 1; /*spi dma write data status bit.*/ - }; - uint32_t val; - } dma_out_link; - union { - struct { - uint32_t addr: 20; /*The address of the first inlink descriptor.*/ - uint32_t auto_ret: 1; /*when the bit is set the inlink descriptor returns to the first link node when a packet is error.*/ - uint32_t reserved21: 7; /*reserved*/ - uint32_t stop: 1; /*Set the bit to stop to use inlink descriptor.*/ - uint32_t start: 1; /*Set the bit to start to use inlink descriptor.*/ - uint32_t restart: 1; /*Set the bit to mount on new inlink descriptors.*/ - uint32_t dma_rx_ena: 1; /*spi dma read data status bit.*/ - }; - uint32_t val; - } dma_in_link; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The enable bit for lack of enough inlink descriptors. Can be configured in CONF state.*/ - uint32_t outlink_dscr_error: 1; /*The enable bit for outlink descriptor error. Can be configured in CONF state.*/ - uint32_t inlink_dscr_error: 1; /*The enable bit for inlink descriptor error. Can be configured in CONF state.*/ - uint32_t in_done: 1; /*The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/ - uint32_t in_err_eof: 1; /*The enable bit for receiving error. Can be configured in CONF state.*/ - uint32_t in_suc_eof: 1; /*The enable bit for completing receiving all the packets from host. Can be configured in CONF state.*/ - uint32_t out_done: 1; /*The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state.*/ - uint32_t out_eof: 1; /*The enable bit for sending a packet to host done. Can be configured in CONF state.*/ - uint32_t out_total_eof: 1; /*The enable bit for sending all the packets to host done. Can be configured in CONF state.*/ - uint32_t infifo_full_err: 1; /*The enable bit for infifo full error interrupt.*/ - uint32_t outfifo_empty_err: 1; /*The enable bit for outfifo empty error interrupt.*/ - uint32_t cmd6: 1; /*The enable bit for SPI slave CMD6 interrupt.*/ - uint32_t cmd7: 1; /*The enable bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The enable bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The enable bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The enable bit for SPI slave CMDA interrupt.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The raw bit for lack of enough inlink descriptors. Can be configured in CONF state.*/ - uint32_t outlink_dscr_error: 1; /*The raw bit for outlink descriptor error. Can be configured in CONF state.*/ - uint32_t inlink_dscr_error: 1; /*The raw bit for inlink descriptor error. Can be configured in CONF state.*/ - uint32_t in_done: 1; /*The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/ - uint32_t in_err_eof: 1; /*The raw bit for receiving error. Can be configured in CONF state.*/ - uint32_t in_suc_eof: 1; /*The raw bit for completing receiving all the packets from host. Can be configured in CONF state.*/ - uint32_t out_done: 1; /*The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state.*/ - uint32_t out_eof: 1; /*The raw bit for sending a packet to host done. Can be configured in CONF state.*/ - uint32_t out_total_eof: 1; /*The raw bit for sending all the packets to host done. Can be configured in CONF state.*/ - uint32_t infifo_full_err: 1; /*1:spi_dma_infifo_full and spi_push_data_prep are valid which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf.*/ - uint32_t outfifo_empty_err: 1; /*1:spi_dma_outfifo_empty and spi_pop_data_prep are valid which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf.*/ - uint32_t cmd6: 1; /*The raw bit for SPI slave CMD6 interrupt.*/ - uint32_t cmd7: 1; /*The raw bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The raw bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The raw bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The raw bit for SPI slave CMDA interrupt.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The status bit for lack of enough inlink descriptors.*/ - uint32_t outlink_dscr_error: 1; /*The status bit for outlink descriptor error.*/ - uint32_t inlink_dscr_error: 1; /*The status bit for inlink descriptor error.*/ - uint32_t in_done: 1; /*The status bit for completing usage of a inlink descriptor.*/ - uint32_t in_err_eof: 1; /*The status bit for receiving error.*/ - uint32_t in_suc_eof: 1; /*The status bit for completing receiving all the packets from host.*/ - uint32_t out_done: 1; /*The status bit for completing usage of a outlink descriptor.*/ - uint32_t out_eof: 1; /*The status bit for sending a packet to host done.*/ - uint32_t out_total_eof: 1; /*The status bit for sending all the packets to host done.*/ - uint32_t infifo_full_err: 1; /*The status bit for infifo full error.*/ - uint32_t outfifo_empty_err: 1; /*The status bit for outfifo empty error.*/ - uint32_t cmd6: 1; /*The status bit for SPI slave CMD6 interrupt.*/ - uint32_t cmd7: 1; /*The status bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The status bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The status bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The status bit for SPI slave CMDA interrupt.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - union { - struct { - uint32_t inlink_dscr_empty: 1; /*The clear bit for lack of enough inlink descriptors. Can be configured in CONF state.*/ - uint32_t outlink_dscr_error: 1; /*The clear bit for outlink descriptor error. Can be configured in CONF state.*/ - uint32_t inlink_dscr_error: 1; /*The clear bit for inlink descriptor error. Can be configured in CONF state.*/ - uint32_t in_done: 1; /*The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state.*/ - uint32_t in_err_eof: 1; /*The clear bit for receiving error. Can be configured in CONF state.*/ - uint32_t in_suc_eof: 1; /*The clear bit for completing receiving all the packets from host. Can be configured in CONF state.*/ - uint32_t out_done: 1; /*The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state.*/ - uint32_t out_eof: 1; /*The clear bit for sending a packet to host done. Can be configured in CONF state.*/ - uint32_t out_total_eof: 1; /*The clear bit for sending all the packets to host done. Can be configured in CONF state.*/ - uint32_t infifo_full_err: 1; /*1: Clear spi_dma_infifo_full_err. 0: not valid. Can be changed by CONF_buf.*/ - uint32_t outfifo_empty_err: 1; /*1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can be changed by CONF_buf.*/ - uint32_t cmd6: 1; /*The clear bit for SPI slave CMD6 interrupt.*/ - uint32_t cmd7: 1; /*The clear bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8: 1; /*The clear bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9: 1; /*The clear bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda: 1; /*The clear bit for SPI slave CMDA interrupt.*/ - uint32_t reserved16: 16; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - uint32_t dma_in_err_eof_des_addr; /*The inlink descriptor address when spi dma produce receiving error.*/ - uint32_t dma_in_suc_eof_des_addr; /*The last inlink descriptor address when spi dma produce from_suc_eof.*/ - uint32_t dma_inlink_dscr; /*The content of current in descriptor pointer.*/ - uint32_t dma_inlink_dscr_bf0; /*The content of next in descriptor pointer.*/ - uint32_t dma_inlink_dscr_bf1; /*The content of current in descriptor data buffer pointer.*/ - uint32_t dma_out_eof_bfr_des_addr; /*The address of buffer relative to the outlink descriptor that produce eof.*/ - uint32_t dma_out_eof_des_addr; /*The last outlink descriptor address when spi dma produce to_eof.*/ - uint32_t dma_outlink_dscr; /*The content of current out descriptor pointer.*/ - uint32_t dma_outlink_dscr_bf0; /*The content of next out descriptor pointer.*/ - uint32_t dma_outlink_dscr_bf1; /*The content of current out descriptor data buffer pointer.*/ - union { - struct { - uint32_t out_dscr_addr: 18; /*SPI dma out descriptor address.*/ - uint32_t out_dscr_state: 2; /*SPI dma out descriptor state.*/ - uint32_t out_state: 3; /*SPI dma out data state.*/ - uint32_t out_fifo_cnt: 7; /*The remains of SPI dma outfifo data.*/ - uint32_t out_fifo_full: 1; /*SPI dma outfifo is full.*/ - uint32_t out_fifo_empty: 1; /*SPI dma outfifo is empty.*/ - }; - uint32_t val; - } dma_out_status; - union { - struct { - uint32_t in_dscr_addr: 18; /*SPI dma in descriptor address.*/ - uint32_t in_dscr_state: 2; /*SPI dma in descriptor state.*/ - uint32_t in_state: 3; /*SPI dma in data state.*/ - uint32_t in_fifo_cnt: 7; /*The remains of SPI dma infifo data.*/ - uint32_t in_fifo_full: 1; /*SPI dma infifo is full.*/ - uint32_t in_fifo_empty: 1; /*SPI dma infifo is empty.*/ - }; - uint32_t val; - } dma_in_status; - uint32_t data_buf[18]; /*data buffer*/ - union { - struct { - uint32_t din0_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din1_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din2_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din3_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din4_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din5_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din6_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din7_mode: 3; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t timing_clk_ena: 1; /*1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state.*/ - uint32_t reserved25: 7; /*reserved*/ - }; - uint32_t val; - } din_mode; - union { - struct { - uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t reserved16:16; /*reserved*/ - }; - uint32_t val; - } din_num; - union { - struct { - uint32_t dout0_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout1_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout2_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout3_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout4_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout5_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout6_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t dout7_mode: 3; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t reserved24: 8; /*reserved*/ - }; - uint32_t val; - } dout_mode; - union { - struct { - uint32_t dout0_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout1_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout2_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout3_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout4_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout5_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout6_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t dout7_num: 2; /*the output signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t reserved16:16; /*reserved*/ - }; - uint32_t val; - } dout_num; - union { - struct { - uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame. Can be configured in CONF state.*/ - uint32_t lcd_va_height:10; /*It is the vertical active height of a frame. Can be configured in CONF state.*/ - uint32_t lcd_vt_height:10; /*It is the vertical total height of a frame. Can be configured in CONF state.*/ - uint32_t lcd_mode_en: 1; /*1: Enable LCD mode output vsync hsync de. 0: Disable. Can be configured in CONF state.*/ - }; - uint32_t val; - } lcd_ctrl; - union { - struct { - uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame. Can be configured in CONF state.*/ - uint32_t lcd_ha_width:12; /*It is the horizontal active width of a frame. Can be configured in CONF state.*/ - uint32_t lcd_ht_width:12; /*It is the horizontal total width of a frame. Can be configured in CONF state.*/ - }; - uint32_t val; - } lcd_ctrl1; - union { - struct { - uint32_t lcd_vsync_width: 7; /*It is the position of spi_vsync active pulse in a line. Can be configured in CONF state.*/ - uint32_t vsync_idle_pol: 1; /*It is the idle value of spi_vsync. Can be configured in CONF state.*/ - uint32_t reserved8: 8; /*reserved*/ - uint32_t lcd_hsync_width: 7; /*It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.*/ - uint32_t hsync_idle_pol: 1; /*It is the idle value of spi_hsync. Can be configured in CONF state.*/ - uint32_t lcd_hsync_position: 8; /*It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.*/ - }; - uint32_t val; - } lcd_ctrl2; - union { - struct { - uint32_t d_dqs_mode: 3; /*the output spi_dqs is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t d_cd_mode: 3; /*the output spi_cd is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t d_de_mode: 3; /*the output spi_de is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t d_hsync_mode: 3; /*the output spi_hsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t d_vsync_mode: 3; /*the output spi_vsync is delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk. Can be configured in CONF state.*/ - uint32_t de_idle_pol: 1; /*It is the idle value of spi_de.*/ - uint32_t hs_blank_en: 1; /*1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans.*/ - uint32_t reserved17: 15; /*reserved*/ - }; - uint32_t val; - } lcd_d_mode; - union { - struct { - uint32_t d_dqs_num: 2; /*the output spi_dqs is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t d_cd_num: 2; /*the output spi_cd is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t d_de_num: 2; /*the output spi_de is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t d_hsync_num: 2; /*the output spi_hsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t d_vsync_num: 2; /*the output spi_vsync is delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ - uint32_t reserved10: 22; /*reserved*/ - }; - uint32_t val; - } lcd_d_num; - uint32_t reserved_104; - uint32_t reserved_108; - uint32_t reserved_10c; - uint32_t reserved_110; - uint32_t reserved_114; - uint32_t reserved_118; - uint32_t reserved_11c; - uint32_t reserved_120; - uint32_t reserved_124; - uint32_t reserved_128; - uint32_t reserved_12c; - uint32_t reserved_130; - uint32_t reserved_134; - uint32_t reserved_138; - uint32_t reserved_13c; - uint32_t reserved_140; - uint32_t reserved_144; - uint32_t reserved_148; - uint32_t reserved_14c; - uint32_t reserved_150; - uint32_t reserved_154; - uint32_t reserved_158; - uint32_t reserved_15c; - uint32_t reserved_160; - uint32_t reserved_164; - uint32_t reserved_168; - uint32_t reserved_16c; - uint32_t reserved_170; - uint32_t reserved_174; - uint32_t reserved_178; - uint32_t reserved_17c; - uint32_t reserved_180; - uint32_t reserved_184; - uint32_t reserved_188; - uint32_t reserved_18c; - uint32_t reserved_190; - uint32_t reserved_194; - uint32_t reserved_198; - uint32_t reserved_19c; - uint32_t reserved_1a0; - uint32_t reserved_1a4; - uint32_t reserved_1a8; - uint32_t reserved_1ac; - uint32_t reserved_1b0; - uint32_t reserved_1b4; - uint32_t reserved_1b8; - uint32_t reserved_1bc; - uint32_t reserved_1c0; - uint32_t reserved_1c4; - uint32_t reserved_1c8; - uint32_t reserved_1cc; - uint32_t reserved_1d0; - uint32_t reserved_1d4; - uint32_t reserved_1d8; - uint32_t reserved_1dc; - uint32_t reserved_1e0; - uint32_t reserved_1e4; - uint32_t reserved_1e8; - uint32_t reserved_1ec; - uint32_t reserved_1f0; - uint32_t reserved_1f4; - uint32_t reserved_1f8; - uint32_t reserved_1fc; - uint32_t reserved_200; - uint32_t reserved_204; - uint32_t reserved_208; - uint32_t reserved_20c; - uint32_t reserved_210; - uint32_t reserved_214; - uint32_t reserved_218; - uint32_t reserved_21c; - uint32_t reserved_220; - uint32_t reserved_224; - uint32_t reserved_228; - uint32_t reserved_22c; - uint32_t reserved_230; - uint32_t reserved_234; - uint32_t reserved_238; - uint32_t reserved_23c; - uint32_t reserved_240; - uint32_t reserved_244; - uint32_t reserved_248; - uint32_t reserved_24c; - uint32_t reserved_250; - uint32_t reserved_254; - uint32_t reserved_258; - uint32_t reserved_25c; - uint32_t reserved_260; - uint32_t reserved_264; - uint32_t reserved_268; - uint32_t reserved_26c; - uint32_t reserved_270; - uint32_t reserved_274; - uint32_t reserved_278; - uint32_t reserved_27c; - uint32_t reserved_280; - uint32_t reserved_284; - uint32_t reserved_288; - uint32_t reserved_28c; - uint32_t reserved_290; - uint32_t reserved_294; - uint32_t reserved_298; - uint32_t reserved_29c; - uint32_t reserved_2a0; - uint32_t reserved_2a4; - uint32_t reserved_2a8; - uint32_t reserved_2ac; - uint32_t reserved_2b0; - uint32_t reserved_2b4; - uint32_t reserved_2b8; - uint32_t reserved_2bc; - uint32_t reserved_2c0; - uint32_t reserved_2c4; - uint32_t reserved_2c8; - uint32_t reserved_2cc; - uint32_t reserved_2d0; - uint32_t reserved_2d4; - uint32_t reserved_2d8; - uint32_t reserved_2dc; - uint32_t reserved_2e0; - uint32_t reserved_2e4; - uint32_t reserved_2e8; - uint32_t reserved_2ec; - uint32_t reserved_2f0; - uint32_t reserved_2f4; - uint32_t reserved_2f8; - uint32_t reserved_2fc; - uint32_t reserved_300; - uint32_t reserved_304; - uint32_t reserved_308; - uint32_t reserved_30c; - uint32_t reserved_310; - uint32_t reserved_314; - uint32_t reserved_318; - uint32_t reserved_31c; - uint32_t reserved_320; - uint32_t reserved_324; - uint32_t reserved_328; - uint32_t reserved_32c; - uint32_t reserved_330; - uint32_t reserved_334; - uint32_t reserved_338; - uint32_t reserved_33c; - uint32_t reserved_340; - uint32_t reserved_344; - uint32_t reserved_348; - uint32_t reserved_34c; - uint32_t reserved_350; - uint32_t reserved_354; - uint32_t reserved_358; - uint32_t reserved_35c; - uint32_t reserved_360; - uint32_t reserved_364; - uint32_t reserved_368; - uint32_t reserved_36c; - uint32_t reserved_370; - uint32_t reserved_374; - uint32_t reserved_378; - uint32_t reserved_37c; - uint32_t reserved_380; - uint32_t reserved_384; - uint32_t reserved_388; - uint32_t reserved_38c; - uint32_t reserved_390; - uint32_t reserved_394; - uint32_t reserved_398; - uint32_t reserved_39c; - uint32_t reserved_3a0; - uint32_t reserved_3a4; - uint32_t reserved_3a8; - uint32_t reserved_3ac; - uint32_t reserved_3b0; - uint32_t reserved_3b4; - uint32_t reserved_3b8; - uint32_t reserved_3bc; - uint32_t reserved_3c0; - uint32_t reserved_3c4; - uint32_t reserved_3c8; - uint32_t reserved_3cc; - uint32_t reserved_3d0; - uint32_t reserved_3d4; - uint32_t reserved_3d8; - uint32_t reserved_3dc; - uint32_t reserved_3e0; - uint32_t reserved_3e4; - uint32_t reserved_3e8; - uint32_t reserved_3ec; - uint32_t reserved_3f0; - uint32_t reserved_3f4; - uint32_t reserved_3f8; - union { - struct { - uint32_t date: 28; /*SPI register version.*/ - uint32_t reserved28: 4; /*reserved*/ - }; - uint32_t val; - } date; +/** Group: Default */ +/** Type of cmd register + * reserved + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [22:0]; default: 0; + * Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:23; + uint32_t reserved_23:1; + /** usr : R/W; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * [31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state. + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * [31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of ctrl register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** ext_hold_en : R/W; bitpos: [2]; default: 0; + * Set the bit to hold spi. The bit is combined with + * spi_usr_prep_hold,spi_usr_cmd_hold,spi_usr_addr_hold,spi_usr_dummy_hold,spi_usr_din_hold,spi_usr_dout_hold + * and spi_usr_hold_pol. Can be configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t ext_hold_en:1; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi controller. Can be + * configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + uint32_t reserved_20:1; + /** wp_reg : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_reg:1; + uint32_t reserved_22:3; + /** rd_bit_order : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:1; + /** wr_bit_order : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:1; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ctrl1 register + * reserved + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + /** w16_17_wr_ena : R/W; bitpos: [4]; default: 1; + * 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be written. Can be + * configured in CONF state. + */ + uint32_t w16_17_wr_ena:1; + uint32_t reserved_5:9; + /** cs_hold_delay : R/W; bitpos: [19:14]; default: 1; + * SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t cs_hold_delay:6; + uint32_t reserved_20:12; + }; + uint32_t val; +} spi_ctrl1_reg_t; + +/** Type of ctrl2 register + * reserved + */ +typedef union { + struct { + /** cs_setup_time : R/W; bitpos: [12:0]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:13; + /** cs_hold_time : R/W; bitpos: [25:13]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:13; + /** cs_delay_mode : R/W; bitpos: [28:26]; default: 0; + * spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or + * spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if + * spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle, else delayed by + * half cycle 3: delayed one cycle. Can be configured in CONF state. + */ + uint32_t cs_delay_mode:3; + /** cs_delay_num : R/W; bitpos: [30:29]; default: 0; + * spi_cs signal is delayed by system clock cycles. Can be configured in CONF state. + */ + uint32_t cs_delay_num:2; + uint32_t reserved_31:1; + }; + uint32_t val; +} spi_ctrl2_reg_t; + +/** Type of clock register + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [30:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:13; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of user register + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : R/W; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + /** rd_byte_order : R/W; bitpos: [10]; default: 0; + * In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF + * state. + */ + uint32_t rd_byte_order:1; + /** wr_byte_order : R/W; bitpos: [11]; default: 0; + * In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be + * configured in CONF state. + */ + uint32_t wr_byte_order:1; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + /** sio : R/W; bitpos: [16]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + /** usr_hold_pol : R/W; bitpos: [17]; default: 0; + * It is combined with hold bits to set the polarity of spi hold line 1: spi will be + * held when spi hold line is high 0: spi will be held when spi hold line is low. Can + * be configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_hold_pol:1; + /** usr_dout_hold : R/W; bitpos: [18]; default: 0; + * spi is hold at data out state the bit are combined with spi_usr_hold_pol bit. Can + * be configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_dout_hold:1; + /** usr_din_hold : R/W; bitpos: [19]; default: 0; + * spi is hold at data in state the bit are combined with spi_usr_hold_pol bit. Can be + * configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_din_hold:1; + /** usr_dummy_hold : R/W; bitpos: [20]; default: 0; + * spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit. Can be + * configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_dummy_hold:1; + /** usr_addr_hold : R/W; bitpos: [21]; default: 0; + * spi is hold at address state the bit are combined with spi_usr_hold_pol bit. Can be + * configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_addr_hold:1; + /** usr_cmd_hold : R/W; bitpos: [22]; default: 0; + * spi is hold at command state the bit are combined with spi_usr_hold_pol bit. Can be + * configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_cmd_hold:1; + /** usr_prep_hold : R/W; bitpos: [23]; default: 0; + * spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit. Can be + * configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t usr_prep_hold:1; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:19; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:12; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + +/** Type of mosi_dlen register + * reserved + */ +typedef union { + struct { + /** usr_mosi_dbitlen : R/W; bitpos: [22:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). Can be + * configured in CONF state. + */ + uint32_t usr_mosi_dbitlen:23; + uint32_t reserved_23:9; + }; + uint32_t val; +} spi_mosi_dlen_reg_t; + +/** Type of miso_dlen register + * reserved + */ +typedef union { + struct { + /** usr_miso_dbitlen : R/W; bitpos: [22:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). Can be + * configured in CONF state. + */ + uint32_t usr_miso_dbitlen:23; + uint32_t reserved_23:9; + }; + uint32_t val; +} spi_miso_dlen_reg_t; + +/** Type of misc register + * 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured + * in CONF state. + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be + * configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be + * configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be + * configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * reserved + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be + * configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be + * configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : R/W; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : R/W; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. Can be configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : R/W; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. Can be configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + /** cd_data_set : R/W; bitpos: [20]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN state. 0: + * spi_cd = spi_cd_idle_edge. Can be configured in CONF state. + */ + uint32_t cd_data_set:1; + /** cd_dummy_set : R/W; bitpos: [21]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: spi_cd = + * spi_cd_idle_edge. Can be configured in CONF state. + */ + uint32_t cd_dummy_set:1; + /** cd_addr_set : R/W; bitpos: [22]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. 0: + * spi_cd = spi_cd_idle_edge. Can be configured in CONF state. + */ + uint32_t cd_addr_set:1; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + /** cd_cmd_set : R/W; bitpos: [25]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. 0: spi_cd + * = spi_cd_idle_edge. Can be configured in CONF state. + */ + uint32_t cd_cmd_set:1; + /** cd_idle_edge : R/W; bitpos: [26]; default: 0; + * The default value of spi_cd. Can be configured in CONF state. + */ + uint32_t cd_idle_edge:1; + uint32_t reserved_27:2; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured + * in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of slave register + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ +typedef union { + struct { + uint32_t reserved_0:4; + /** trans_done : R/W; bitpos: [4]; default: 0; + * The interrupt raw bit for the completion of any operation in both the master mode + * and the slave mode. Can not be changed by CONF_buf. + */ + uint32_t trans_done:1; + /** int_rd_buf_done_en : R/W; bitpos: [5]; default: 0; + * spi_slv_rd_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t int_rd_buf_done_en:1; + /** int_wr_buf_done_en : R/W; bitpos: [6]; default: 0; + * spi_slv_wr_buf Interrupt enable. 1: enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t int_wr_buf_done_en:1; + /** int_rd_dma_done_en : R/W; bitpos: [7]; default: 0; + * spi_slv_rd_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t int_rd_dma_done_en:1; + /** int_wr_dma_done_en : R/W; bitpos: [8]; default: 0; + * spi_slv_wr_dma Interrupt enable. 1: enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t int_wr_dma_done_en:1; + /** int_trans_done_en : R/W; bitpos: [9]; default: 1; + * spi_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t int_trans_done_en:1; + /** int_dma_seg_trans_en : R/W; bitpos: [10]; default: 0; + * spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable. Can be configured in + * CONF state. + */ + uint32_t int_dma_seg_trans_en:1; + /** seg_magic_err_int_en : R/W; bitpos: [11]; default: 0; + * 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF + * state. + */ + uint32_t seg_magic_err_int_en:1; + uint32_t reserved_12:11; + /** trans_cnt : RO; bitpos: [26:23]; default: 0; + * The operations counter in both the master mode and the slave mode. + */ + uint32_t trans_cnt:4; + uint32_t reserved_27:2; + /** trans_done_auto_clr_en : R/W; bitpos: [29]; default: 0; + * spi_trans_done auto clear enable, clear it 3 apb cycles after the pos edge of + * spi_trans_done. 0:disable. 1: enable. Can be configured in CONF state. + */ + uint32_t trans_done_auto_clr_en:1; + /** slave_mode : R/W; bitpos: [30]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : R/W; bitpos: [31]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * In the slave mode it is the value of address. + */ +typedef union { + struct { + uint32_t reserved_0:10; + /** slv_addr_err_clr : R/W; bitpos: [10]; default: 0; + * 1: Clear spi_slv_addr_err. 0: not valid. Can be changed by CONF_buf. + */ + uint32_t slv_addr_err_clr:1; + /** slv_cmd_err_clr : R/W; bitpos: [11]; default: 0; + * 1: Clear spi_slv_cmd_err. 0: not valid. Can be changed by CONF_buf. + */ + uint32_t slv_cmd_err_clr:1; + /** slv_no_qpi_en : R/W; bitpos: [12]; default: 0; + * 1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported. + */ + uint32_t slv_no_qpi_en:1; + /** slv_addr_err : RO; bitpos: [13]; default: 0; + * 1: The address value of the last SPI transfer is not supported by SPI slave. 0: The + * address value is supported or no address value is received. + */ + uint32_t slv_addr_err:1; + /** slv_cmd_err : RO; bitpos: [14]; default: 0; + * 1: The command value of the last SPI transfer is not supported by SPI slave. 0: The + * command value is supported or no command value is received. + */ + uint32_t slv_cmd_err:1; + /** slv_wr_dma_done : R/W; bitpos: [15]; default: 0; + * The interrupt raw bit for the completion of dma write operation in the slave mode. + * Can not be changed by CONF_buf. + */ + uint32_t slv_wr_dma_done:1; + /** slv_last_command : R/W; bitpos: [23:16]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W; bitpos: [31:24]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:8; + }; + uint32_t val; +} spi_slave1_reg_t; + +/** Type of slv_wrbuf_dlen register + * The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if + * spi_usr_conf is enabled, is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0]. + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slv_wr_buf_done : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of write-buffer operation in the slave + * mode. Can not be changed by CONF_buf. + */ + uint32_t slv_wr_buf_done:1; + /** conf_base_bitlen : R/W; bitpos: [31:25]; default: 108; + * The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if + * spi_usr_conf is enabled, is spi_conf_base_bitlen[6:0] + spi_conf_bitlen[23:0]. + */ + uint32_t conf_base_bitlen:7; + }; + uint32_t val; +} spi_slv_wrbuf_dlen_reg_t; + +/** Type of slv_rdbuf_dlen register + * reserved + */ +typedef union { + struct { + /** slv_dma_rd_bytelen : R/W; bitpos: [19:0]; default: 0; + * In the slave mode it is the length in bytes for read operations. The register value + * shall be byte_num. + */ + uint32_t slv_dma_rd_bytelen:20; + uint32_t reserved_20:4; + /** slv_rd_buf_done : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of read-buffer operation in the slave + * mode. Can not be changed by CONF_buf. + */ + uint32_t slv_rd_buf_done:1; + /** seg_magic_err : R/W; bitpos: [25]; default: 0; + * 1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. + * 0: others. + */ + uint32_t seg_magic_err:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} spi_slv_rdbuf_dlen_reg_t; + +/** Type of slv_rd_byte register + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ +typedef union { + struct { + /** slv_data_bytelen : R/W; bitpos: [19:0]; default: 0; + * The full-duplex or half-duplex data byte length of the last SPI transfer in slave + * mode. In half-duplex mode, this value is controlled by bits [23:20]. + */ + uint32_t slv_data_bytelen:20; + /** slv_rddma_bytelen_en : R/W; bitpos: [20]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bytelen_en:1; + /** slv_wrdma_bytelen_en : R/W; bitpos: [21]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data + * length in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bytelen_en:1; + /** slv_rdbuf_bytelen_en : R/W; bitpos: [22]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bytelen_en:1; + /** slv_wrbuf_bytelen_en : R/W; bitpos: [23]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave data + * length in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bytelen_en:1; + /** dma_seg_magic_value : R/W; bitpos: [27:24]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + uint32_t reserved_28:2; + /** slv_rd_dma_done : R/W; bitpos: [30]; default: 0; + * The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. + * Can not be changed by CONF_buf. + */ + uint32_t slv_rd_dma_done:1; + /** usr_conf : R/W; bitpos: [31]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + }; + uint32_t val; +} spi_slv_rd_byte_reg_t; + +/** Type of fsm register + * Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid + * when spi_rx_eof_en is 0. Can be configured in CONF state.. + */ +typedef union { + struct { + /** st : RO; bitpos: [3:0]; default: 0; + * The status of spi state machine. 0: idle state, 1: preparation state, 2: send + * command state, 3: send data state, 4: red data state, 5:write data state, 6: wait + * state, 7: done state. + */ + uint32_t st:4; + uint32_t reserved_4:8; + /** mst_dma_rd_bytelen : R/W; bitpos: [31:12]; default: 0; + * Define the master DMA read byte length in non seg-trans or seg-trans mode. Invalid + * when spi_rx_eof_en is 0. Can be configured in CONF state.. + */ + uint32_t mst_dma_rd_bytelen:20; + }; + uint32_t val; +} spi_fsm_reg_t; + +/** Type of hold register + * reserved + */ +typedef union { + struct { + /** int_hold_ena : R/W; bitpos: [1:0]; default: 0; + * This register is for two SPI masters to share the same cs clock and data signals. + * The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): + * hold at idle phase 2: hold at prepare phase. Can be configured in CONF state. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t int_hold_ena:2; + /** hold_val_reg : R/W; bitpos: [2]; default: 0; + * spi hold output value, which should be used with spi_hold_out_en. Can be configured + * in CONF state. + */ + uint32_t hold_val_reg:1; + /** hold_out_en : R/W; bitpos: [3]; default: 0; + * Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state + * machine with spi_ext_hold_en and other usr hold signals. Can be configured in CONF + * state. + */ + uint32_t hold_out_en:1; + /** hold_out_time : R/W; bitpos: [6:4]; default: 0; + * set the hold cycles of output spi_hold signal when spi_hold_out_en is enable. Can + * be configured in CONF state. + */ + uint32_t hold_out_time:3; + /** dma_seg_trans_done : R/W; bitpos: [7]; default: 0; + * 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex + * seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is + * not ended or not occurred. Can not be changed by CONF_buf. + */ + uint32_t dma_seg_trans_done:1; + uint32_t reserved_8:24; + }; + uint32_t val; +} spi_hold_reg_t; + +/** Type of dma_conf register + * reserved + */ +typedef union { + struct { + uint32_t reserved_0:2; + /** in_rst : R/W; bitpos: [2]; default: 0; + * The bit is used to reset in dma fsm and in data fifo pointer. + */ + uint32_t in_rst:1; + /** out_rst : R/W; bitpos: [3]; default: 0; + * The bit is used to reset out dma fsm and out data fifo pointer. + */ + uint32_t out_rst:1; + /** ahbm_fifo_rst : R/W; bitpos: [4]; default: 0; + * Reset spi dma ahb master fifo pointer. + */ + uint32_t ahbm_fifo_rst:1; + /** ahbm_rst : R/W; bitpos: [5]; default: 0; + * Reset spi dma ahb master. + */ + uint32_t ahbm_rst:1; + /** in_loop_test : R/W; bitpos: [6]; default: 0; + * Set bit to test in link. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t in_loop_test:1; + /** out_loop_test : R/W; bitpos: [7]; default: 0; + * Set bit to test out link. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t out_loop_test:1; + /** out_auto_wrback : R/W; bitpos: [8]; default: 0; + * when the bit is set, DMA continue to use the next inlink node when the length of + * inlink is 0. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t out_auto_wrback:1; + /** out_eof_mode : R/W; bitpos: [9]; default: 1; + * out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push + * all data to fifo. + */ + uint32_t out_eof_mode:1; + /** outdscr_burst_en : R/W; bitpos: [10]; default: 0; + * read descriptor use burst mode when read data for memory. + */ + uint32_t outdscr_burst_en:1; + /** indscr_burst_en : R/W; bitpos: [11]; default: 0; + * read descriptor use burst mode when write data to memory. + */ + uint32_t indscr_burst_en:1; + /** out_data_burst_en : R/W; bitpos: [12]; default: 0; + * spi dma read data from memory in burst mode. + */ + uint32_t out_data_burst_en:1; + /** mem_trans_en : R/W; bitpos: [13]; default: 0; */ + uint32_t mem_trans_en:1; + /** dma_rx_stop : R/W; bitpos: [14]; default: 0; + * spi dma read data stop when in continue tx/rx mode. + */ + uint32_t dma_rx_stop:1; + /** dma_tx_stop : R/W; bitpos: [15]; default: 0; + * spi dma write data stop when in continue tx/rx mode. + */ + uint32_t dma_tx_stop:1; + /** dma_continue : R/W; bitpos: [16]; default: 0; + * spi dma continue tx/rx data. + */ + uint32_t dma_continue:1; + /** slv_last_seg_pop_clr : R/W; bitpos: [17]; default: 0; + * 1: Clear spi_slv_seg_frt_pop_mask. 0 : others + */ + uint32_t slv_last_seg_pop_clr:1; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + /** dma_infifo_full_clr : R/W; bitpos: [22]; default: 0; + * 1:Clear spi_dma_infifo_full_vld. 0: Do not control it. + */ + uint32_t dma_infifo_full_clr:1; + /** dma_outfifo_empty_clr : R/W; bitpos: [23]; default: 0; + * 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it. + */ + uint32_t dma_outfifo_empty_clr:1; + uint32_t reserved_24:2; + /** ext_mem_bk_size : R/W; bitpos: [27:26]; default: 0; + * Select the external memory block size. + */ + uint32_t ext_mem_bk_size:2; + /** dma_seg_trans_clr : R/W; bitpos: [28]; default: 0; + * 1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals + * will induce error in DMA RX. + */ + uint32_t dma_seg_trans_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of dma_out_link register + * spi dma write data status bit. + */ +typedef union { + struct { + /** outlink_addr : R/W; bitpos: [19:0]; default: 0; + * The address of the first outlink descriptor. + */ + uint32_t outlink_addr:20; + uint32_t reserved_20:8; + /** outlink_stop : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use outlink descriptor. + */ + uint32_t outlink_stop:1; + /** outlink_start : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use outlink descriptor. + */ + uint32_t outlink_start:1; + /** outlink_restart : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new outlink descriptors. + */ + uint32_t outlink_restart:1; + /** dma_tx_ena : R/W; bitpos: [31]; default: 0; + * spi dma write data status bit. + */ + uint32_t dma_tx_ena:1; + }; + uint32_t val; +} spi_dma_out_link_reg_t; + +/** Type of dma_in_link register + * spi dma read data status bit. + */ +typedef union { + struct { + /** inlink_addr : R/W; bitpos: [19:0]; default: 0; + * The address of the first inlink descriptor. + */ + uint32_t inlink_addr:20; + /** inlink_auto_ret : R/W; bitpos: [20]; default: 0; + * when the bit is set, the inlink descriptor returns to the first link node when a + * packet is error. + */ + uint32_t inlink_auto_ret:1; + uint32_t reserved_21:7; + /** inlink_stop : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use inlink descriptor. + */ + uint32_t inlink_stop:1; + /** inlink_start : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use inlink descriptor. + */ + uint32_t inlink_start:1; + /** inlink_restart : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new inlink descriptors. + */ + uint32_t inlink_restart:1; + /** dma_rx_ena : R/W; bitpos: [31]; default: 0; + * spi dma read data status bit. + */ + uint32_t dma_rx_ena:1; + }; + uint32_t val; +} spi_dma_in_link_reg_t; + +/** Type of dma_int_ena register + * reserved + */ +typedef union { + struct { + /** inlink_dscr_empty_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for lack of enough inlink descriptors. Can be configured in CONF + * state. + */ + uint32_t inlink_dscr_empty_int_ena:1; + /** outlink_dscr_error_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for outlink descriptor error. Can be configured in CONF state. + */ + uint32_t outlink_dscr_error_int_ena:1; + /** inlink_dscr_error_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for inlink descriptor error. Can be configured in CONF state. + */ + uint32_t inlink_dscr_error_int_ena:1; + /** in_done_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for completing usage of a inlink descriptor. Can be configured in + * CONF state. + */ + uint32_t in_done_int_ena:1; + /** in_err_eof_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for receiving error. Can be configured in CONF state. + */ + uint32_t in_err_eof_int_ena:1; + /** in_suc_eof_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for completing receiving all the packets from host. Can be + * configured in CONF state. + */ + uint32_t in_suc_eof_int_ena:1; + /** out_done_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for completing usage of a outlink descriptor . Can be configured in + * CONF state. + */ + uint32_t out_done_int_ena:1; + /** out_eof_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for sending a packet to host done. Can be configured in CONF state. + */ + uint32_t out_eof_int_ena:1; + /** out_total_eof_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for sending all the packets to host done. Can be configured in CONF + * state. + */ + uint32_t out_total_eof_int_ena:1; + /** infifo_full_err_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for infifo full error interrupt. + */ + uint32_t infifo_full_err_int_ena:1; + /** outfifo_empty_err_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for outfifo empty error interrupt. + */ + uint32_t outfifo_empty_err_int_ena:1; + /** slv_cmd6_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI slave CMD6 interrupt. + */ + uint32_t slv_cmd6_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_raw register + * reserved + */ +typedef union { + struct { + /** inlink_dscr_empty_int_raw : RO; bitpos: [0]; default: 0; + * The raw bit for lack of enough inlink descriptors. Can be configured in CONF state. + */ + uint32_t inlink_dscr_empty_int_raw:1; + /** outlink_dscr_error_int_raw : RO; bitpos: [1]; default: 0; + * The raw bit for outlink descriptor error. Can be configured in CONF state. + */ + uint32_t outlink_dscr_error_int_raw:1; + /** inlink_dscr_error_int_raw : RO; bitpos: [2]; default: 0; + * The raw bit for inlink descriptor error. Can be configured in CONF state. + */ + uint32_t inlink_dscr_error_int_raw:1; + /** in_done_int_raw : RO; bitpos: [3]; default: 0; + * The raw bit for completing usage of a inlink descriptor. Can be configured in CONF + * state. + */ + uint32_t in_done_int_raw:1; + /** in_err_eof_int_raw : RO; bitpos: [4]; default: 0; + * The raw bit for receiving error. Can be configured in CONF state. + */ + uint32_t in_err_eof_int_raw:1; + /** in_suc_eof_int_raw : RO; bitpos: [5]; default: 0; + * The raw bit for completing receiving all the packets from host. Can be configured + * in CONF state. + */ + uint32_t in_suc_eof_int_raw:1; + /** out_done_int_raw : RO; bitpos: [6]; default: 0; + * The raw bit for completing usage of a outlink descriptor. Can be configured in CONF + * state. + */ + uint32_t out_done_int_raw:1; + /** out_eof_int_raw : RO; bitpos: [7]; default: 0; + * The raw bit for sending a packet to host done. Can be configured in CONF state. + */ + uint32_t out_eof_int_raw:1; + /** out_total_eof_int_raw : RO; bitpos: [8]; default: 0; + * The raw bit for sending all the packets to host done. Can be configured in CONF + * state. + */ + uint32_t out_total_eof_int_raw:1; + /** infifo_full_err_int_raw : RO; bitpos: [9]; default: 0; + * 1:spi_dma_infifo_full and spi_push_data_prep are valid, which means that DMA Rx + * buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf. + */ + uint32_t infifo_full_err_int_raw:1; + /** outfifo_empty_err_int_raw : RO; bitpos: [10]; default: 0; + * 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid, which means that there is + * no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf. + */ + uint32_t outfifo_empty_err_int_raw:1; + /** slv_cmd6_int_raw : R/W; bitpos: [11]; default: 0; + * The raw bit for SPI slave CMD6 interrupt. + */ + uint32_t slv_cmd6_int_raw:1; + /** slv_cmd7_int_raw : R/W; bitpos: [12]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/W; bitpos: [13]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/W; bitpos: [14]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/W; bitpos: [15]; default: 0; + * The raw bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_raw:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * reserved + */ +typedef union { + struct { + /** inlink_dscr_empty_int_st : RO; bitpos: [0]; default: 0; + * The status bit for lack of enough inlink descriptors. + */ + uint32_t inlink_dscr_empty_int_st:1; + /** outlink_dscr_error_int_st : RO; bitpos: [1]; default: 0; + * The status bit for outlink descriptor error. + */ + uint32_t outlink_dscr_error_int_st:1; + /** inlink_dscr_error_int_st : RO; bitpos: [2]; default: 0; + * The status bit for inlink descriptor error. + */ + uint32_t inlink_dscr_error_int_st:1; + /** in_done_int_st : RO; bitpos: [3]; default: 0; + * The status bit for completing usage of a inlink descriptor. + */ + uint32_t in_done_int_st:1; + /** in_err_eof_int_st : RO; bitpos: [4]; default: 0; + * The status bit for receiving error. + */ + uint32_t in_err_eof_int_st:1; + /** in_suc_eof_int_st : RO; bitpos: [5]; default: 0; + * The status bit for completing receiving all the packets from host. + */ + uint32_t in_suc_eof_int_st:1; + /** out_done_int_st : RO; bitpos: [6]; default: 0; + * The status bit for completing usage of a outlink descriptor. + */ + uint32_t out_done_int_st:1; + /** out_eof_int_st : RO; bitpos: [7]; default: 0; + * The status bit for sending a packet to host done. + */ + uint32_t out_eof_int_st:1; + /** out_total_eof_int_st : RO; bitpos: [8]; default: 0; + * The status bit for sending all the packets to host done. + */ + uint32_t out_total_eof_int_st:1; + /** infifo_full_err_int_st : RO; bitpos: [9]; default: 0; + * The status bit for infifo full error. + */ + uint32_t infifo_full_err_int_st:1; + /** outfifo_empty_err_int_st : RO; bitpos: [10]; default: 0; + * The status bit for outfifo empty error. + */ + uint32_t outfifo_empty_err_int_st:1; + /** slv_cmd6_int_st : R/W; bitpos: [11]; default: 0; + * The status bit for SPI slave CMD6 interrupt. + */ + uint32_t slv_cmd6_int_st:1; + /** slv_cmd7_int_st : R/W; bitpos: [12]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : R/W; bitpos: [13]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : R/W; bitpos: [14]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : R/W; bitpos: [15]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_clr register + * reserved + */ +typedef union { + struct { + /** inlink_dscr_empty_int_clr : R/W; bitpos: [0]; default: 0; + * The clear bit for lack of enough inlink descriptors. Can be configured in CONF + * state. + */ + uint32_t inlink_dscr_empty_int_clr:1; + /** outlink_dscr_error_int_clr : R/W; bitpos: [1]; default: 0; + * The clear bit for outlink descriptor error. Can be configured in CONF state. + */ + uint32_t outlink_dscr_error_int_clr:1; + /** inlink_dscr_error_int_clr : R/W; bitpos: [2]; default: 0; + * The clear bit for inlink descriptor error. Can be configured in CONF state. + */ + uint32_t inlink_dscr_error_int_clr:1; + /** in_done_int_clr : R/W; bitpos: [3]; default: 0; + * The clear bit for completing usage of a inlink descriptor. Can be configured in + * CONF state. + */ + uint32_t in_done_int_clr:1; + /** in_err_eof_int_clr : R/W; bitpos: [4]; default: 0; + * The clear bit for receiving error. Can be configured in CONF state. + */ + uint32_t in_err_eof_int_clr:1; + /** in_suc_eof_int_clr : R/W; bitpos: [5]; default: 0; + * The clear bit for completing receiving all the packets from host. Can be configured + * in CONF state. + */ + uint32_t in_suc_eof_int_clr:1; + /** out_done_int_clr : R/W; bitpos: [6]; default: 0; + * The clear bit for completing usage of a outlink descriptor. Can be configured in + * CONF state. + */ + uint32_t out_done_int_clr:1; + /** out_eof_int_clr : R/W; bitpos: [7]; default: 0; + * The clear bit for sending a packet to host done. Can be configured in CONF state. + */ + uint32_t out_eof_int_clr:1; + /** out_total_eof_int_clr : R/W; bitpos: [8]; default: 0; + * The clear bit for sending all the packets to host done. Can be configured in CONF + * state. + */ + uint32_t out_total_eof_int_clr:1; + /** infifo_full_err_int_clr : R/W; bitpos: [9]; default: 0; + * 1: Clear spi_dma_infifo_full_err. 0: not valid. Can be changed by CONF_buf. + */ + uint32_t infifo_full_err_int_clr:1; + /** outfifo_empty_err_int_clr : R/W; bitpos: [10]; default: 0; + * 1: Clear spi_dma_outfifo_empty_err signal. 0: not valid. Can be changed by CONF_buf. + */ + uint32_t outfifo_empty_err_int_clr:1; + /** slv_cmd6_int_clr : R/W; bitpos: [11]; default: 0; + * The clear bit for SPI slave CMD6 interrupt. + */ + uint32_t slv_cmd6_int_clr:1; + /** slv_cmd7_int_clr : R/W; bitpos: [12]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : R/W; bitpos: [13]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : R/W; bitpos: [14]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : R/W; bitpos: [15]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of in_err_eof_des_addr register + * The inlink descriptor address when spi dma produce receiving error. + */ +typedef union { + struct { + /** dma_in_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The inlink descriptor address when spi dma produce receiving error. + */ + uint32_t dma_in_err_eof_des_addr:32; + }; + uint32_t val; +} spi_in_err_eof_des_addr_reg_t; + +/** Type of in_suc_eof_des_addr register + * The last inlink descriptor address when spi dma produce from_suc_eof. + */ +typedef union { + struct { + /** dma_in_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The last inlink descriptor address when spi dma produce from_suc_eof. + */ + uint32_t dma_in_suc_eof_des_addr:32; + }; + uint32_t val; +} spi_in_suc_eof_des_addr_reg_t; + +/** Type of inlink_dscr register + * The content of current in descriptor pointer. + */ +typedef union { + struct { + /** dma_inlink_dscr : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor pointer. + */ + uint32_t dma_inlink_dscr:32; + }; + uint32_t val; +} spi_inlink_dscr_reg_t; + +/** Type of inlink_dscr_bf0 register + * The content of next in descriptor pointer. + */ +typedef union { + struct { + /** dma_inlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The content of next in descriptor pointer. + */ + uint32_t dma_inlink_dscr_bf0:32; + }; + uint32_t val; +} spi_inlink_dscr_bf0_reg_t; + +/** Type of inlink_dscr_bf1 register + * The content of current in descriptor data buffer pointer. + */ +typedef union { + struct { + /** dma_inlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor data buffer pointer. + */ + uint32_t dma_inlink_dscr_bf1:32; + }; + uint32_t val; +} spi_inlink_dscr_bf1_reg_t; + +/** Type of out_eof_bfr_des_addr register + * The address of buffer relative to the outlink descriptor that produce eof. + */ +typedef union { + struct { + /** dma_out_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The address of buffer relative to the outlink descriptor that produce eof. + */ + uint32_t dma_out_eof_bfr_des_addr:32; + }; + uint32_t val; +} spi_out_eof_bfr_des_addr_reg_t; + +/** Type of out_eof_des_addr register + * The last outlink descriptor address when spi dma produce to_eof. + */ +typedef union { + struct { + /** dma_out_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The last outlink descriptor address when spi dma produce to_eof. + */ + uint32_t dma_out_eof_des_addr:32; + }; + uint32_t val; +} spi_out_eof_des_addr_reg_t; + +/** Type of outlink_dscr register + * The content of current out descriptor pointer. + */ +typedef union { + struct { + /** dma_outlink_dscr : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor pointer. + */ + uint32_t dma_outlink_dscr:32; + }; + uint32_t val; +} spi_outlink_dscr_reg_t; + +/** Type of outlink_dscr_bf0 register + * The content of next out descriptor pointer. + */ +typedef union { + struct { + /** dma_outlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * The content of next out descriptor pointer. + */ + uint32_t dma_outlink_dscr_bf0:32; + }; + uint32_t val; +} spi_outlink_dscr_bf0_reg_t; + +/** Type of outlink_dscr_bf1 register + * The content of current out descriptor data buffer pointer. + */ +typedef union { + struct { + /** dma_outlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor data buffer pointer. + */ + uint32_t dma_outlink_dscr_bf1:32; + }; + uint32_t val; +} spi_outlink_dscr_bf1_reg_t; + +/** Type of dma_outstatus register + * SPI dma outfifo is empty. + */ +typedef union { + struct { + /** dma_outdscr_addr : RO; bitpos: [17:0]; default: 0; + * SPI dma out descriptor address. + */ + uint32_t dma_outdscr_addr:18; + /** dma_outdscr_state : RO; bitpos: [19:18]; default: 0; + * SPI dma out descriptor state. + */ + uint32_t dma_outdscr_state:2; + /** dma_out_state : RO; bitpos: [22:20]; default: 0; + * SPI dma out data state. + */ + uint32_t dma_out_state:3; + /** dma_outfifo_cnt : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma outfifo data. + */ + uint32_t dma_outfifo_cnt:7; + /** dma_outfifo_full : RO; bitpos: [30]; default: 0; + * SPI dma outfifo is full. + */ + uint32_t dma_outfifo_full:1; + /** dma_outfifo_empty : RO; bitpos: [31]; default: 1; + * SPI dma outfifo is empty. + */ + uint32_t dma_outfifo_empty:1; + }; + uint32_t val; +} spi_dma_out_status_reg_t; + +/** Type of dma_instatus register + * SPI dma infifo is empty. + */ +typedef union { + struct { + /** dma_indscr_addr : RO; bitpos: [17:0]; default: 0; + * SPI dma in descriptor address. + */ + uint32_t dma_indscr_addr:18; + /** dma_indscr_state : RO; bitpos: [19:18]; default: 0; + * SPI dma in descriptor state. + */ + uint32_t dma_indscr_state:2; + /** dma_in_state : RO; bitpos: [22:20]; default: 0; + * SPI dma in data state. + */ + uint32_t dma_in_state:3; + /** dma_infifo_cnt : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma infifo data. + */ + uint32_t dma_infifo_cnt:7; + /** dma_infifo_full : RO; bitpos: [30]; default: 0; + * SPI dma infifo is full. + */ + uint32_t dma_infifo_full:1; + /** dma_infifo_empty : RO; bitpos: [31]; default: 1; + * SPI dma infifo is empty. + */ + uint32_t dma_infifo_empty:1; + }; + uint32_t val; +} spi_dma_in_status_reg_t; + +/** Type of w0 register + * data buffer + */ +typedef union { + struct { + /** buf0 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf0:32; + }; + uint32_t val; +} spi_w0_reg_t; + +/** Type of w1 register + * data buffer + */ +typedef union { + struct { + /** buf1 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf1:32; + }; + uint32_t val; +} spi_w1_reg_t; + +/** Type of w2 register + * data buffer + */ +typedef union { + struct { + /** buf2 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf2:32; + }; + uint32_t val; +} spi_w2_reg_t; + +/** Type of w3 register + * data buffer + */ +typedef union { + struct { + /** buf3 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf3:32; + }; + uint32_t val; +} spi_w3_reg_t; + +/** Type of w4 register + * data buffer + */ +typedef union { + struct { + /** buf4 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf4:32; + }; + uint32_t val; +} spi_w4_reg_t; + +/** Type of w5 register + * data buffer + */ +typedef union { + struct { + /** buf5 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf5:32; + }; + uint32_t val; +} spi_w5_reg_t; + +/** Type of w6 register + * data buffer + */ +typedef union { + struct { + /** buf6 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf6:32; + }; + uint32_t val; +} spi_w6_reg_t; + +/** Type of w7 register + * data buffer + */ +typedef union { + struct { + /** buf7 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf7:32; + }; + uint32_t val; +} spi_w7_reg_t; + +/** Type of w8 register + * data buffer + */ +typedef union { + struct { + /** buf8 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf8:32; + }; + uint32_t val; +} spi_w8_reg_t; + +/** Type of w9 register + * data buffer + */ +typedef union { + struct { + /** buf9 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf9:32; + }; + uint32_t val; +} spi_w9_reg_t; + +/** Type of w10 register + * data buffer + */ +typedef union { + struct { + /** buf10 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf10:32; + }; + uint32_t val; +} spi_w10_reg_t; + +/** Type of w11 register + * data buffer + */ +typedef union { + struct { + /** buf11 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf11:32; + }; + uint32_t val; +} spi_w11_reg_t; + +/** Type of w12 register + * data buffer + */ +typedef union { + struct { + /** buf12 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf12:32; + }; + uint32_t val; +} spi_w12_reg_t; + +/** Type of w13 register + * data buffer + */ +typedef union { + struct { + /** buf13 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf13:32; + }; + uint32_t val; +} spi_w13_reg_t; + +/** Type of w14 register + * data buffer + */ +typedef union { + struct { + /** buf14 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf14:32; + }; + uint32_t val; +} spi_w14_reg_t; + +/** Type of w15 register + * data buffer + */ +typedef union { + struct { + /** buf15 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf15:32; + }; + uint32_t val; +} spi_w15_reg_t; + +/** Type of w16 register + * data buffer + */ +typedef union { + struct { + /** buf16 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf16:32; + }; + uint32_t val; +} spi_w16_reg_t; + +/** Type of w17 register + * data buffer + */ +typedef union { + struct { + /** buf17 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + uint32_t buf17:32; + }; + uint32_t val; +} spi_w17_reg_t; + +/** Type of din_mode register + * reserved + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [2:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:3; + /** din1_mode : R/W; bitpos: [5:3]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:3; + /** din2_mode : R/W; bitpos: [8:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:3; + /** din3_mode : R/W; bitpos: [11:9]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:3; + /** din4_mode : R/W; bitpos: [14:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:3; + /** din5_mode : R/W; bitpos: [17:15]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:3; + /** din6_mode : R/W; bitpos: [20:18]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:3; + /** din7_mode : R/W; bitpos: [23:21]; default: 0; + * the input signals are delayed by system clock cycles, 0: input without delayed, 1: + * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:3; + /** timing_clk_ena : R/W; bitpos: [24]; default: 0; + * 1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state. + */ + uint32_t timing_clk_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * reserved + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * reserved + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [2:0]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout0_mode:3; + /** dout1_mode : R/W; bitpos: [5:3]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout1_mode:3; + /** dout2_mode : R/W; bitpos: [8:6]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout2_mode:3; + /** dout3_mode : R/W; bitpos: [11:9]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout3_mode:3; + /** dout4_mode : R/W; bitpos: [14:12]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout4_mode:3; + /** dout5_mode : R/W; bitpos: [17:15]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout5_mode:3; + /** dout6_mode : R/W; bitpos: [20:18]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout6_mode:3; + /** dout7_mode : R/W; bitpos: [23:21]; default: 0; + * the output signals are delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t dout7_mode:3; + uint32_t reserved_24:8; + }; + uint32_t val; +} spi_dout_mode_reg_t; + +/** Type of dout_num register + * reserved + */ +typedef union { + struct { + /** dout0_num : R/W; bitpos: [1:0]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout0_num:2; + /** dout1_num : R/W; bitpos: [3:2]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout1_num:2; + /** dout2_num : R/W; bitpos: [5:4]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout2_num:2; + /** dout3_num : R/W; bitpos: [7:6]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout3_num:2; + /** dout4_num : R/W; bitpos: [9:8]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout4_num:2; + /** dout5_num : R/W; bitpos: [11:10]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout5_num:2; + /** dout6_num : R/W; bitpos: [13:12]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout6_num:2; + /** dout7_num : R/W; bitpos: [15:14]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t dout7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_dout_num_reg_t; + +/** Type of lcd_ctrl register + * 1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF + * state. + */ +typedef union { + struct { + /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. Can be configured in CONF state. + */ + uint32_t lcd_hb_front:11; + /** lcd_va_height : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. Can be configured in CONF state. + */ + uint32_t lcd_va_height:10; + /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. Can be configured in CONF state. + */ + uint32_t lcd_vt_height:10; + /** lcd_mode_en : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF + * state. + */ + uint32_t lcd_mode_en:1; + }; + uint32_t val; +} spi_lcd_ctrl_reg_t; + +/** Type of lcd_ctrl1 register + * It is the horizontal total width of a frame. Can be configured in CONF state. + */ +typedef union { + struct { + /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. Can be configured in CONF state. + */ + uint32_t lcd_vb_front:8; + /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. Can be configured in CONF state. + */ + uint32_t lcd_ha_width:12; + /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. Can be configured in CONF state. + */ + uint32_t lcd_ht_width:12; + }; + uint32_t val; +} spi_lcd_ctrl1_reg_t; + +/** Type of lcd_ctrl2 register + * It is the position of spi_hsync active pulse in a line. Can be configured in CONF + * state. + */ +typedef union { + struct { + /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1; + * It is the position of spi_vsync active pulse in a line. Can be configured in CONF + * state. + */ + uint32_t lcd_vsync_width:7; + /** vsync_idle_pol : R/W; bitpos: [7]; default: 0; + * It is the idle value of spi_vsync. Can be configured in CONF state. + */ + uint32_t vsync_idle_pol:1; + uint32_t reserved_8:8; + /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1; + * It is the position of spi_hsync active pulse in a line. Can be configured in CONF + * state. + */ + uint32_t lcd_hsync_width:7; + /** hsync_idle_pol : R/W; bitpos: [23]; default: 0; + * It is the idle value of spi_hsync. Can be configured in CONF state. + */ + uint32_t hsync_idle_pol:1; + /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0; + * It is the position of spi_hsync active pulse in a line. Can be configured in CONF + * state. + */ + uint32_t lcd_hsync_position:8; + }; + uint32_t val; +} spi_lcd_ctrl2_reg_t; + +/** Type of lcd_d_mode register + * reserved + */ +typedef union { + struct { + /** d_dqs_mode : R/W; bitpos: [2:0]; default: 0; + * the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: + * output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t d_dqs_mode:3; + /** d_cd_mode : R/W; bitpos: [5:3]; default: 0; + * the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: + * output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t d_cd_mode:3; + /** d_de_mode : R/W; bitpos: [8:6]; default: 0; + * the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: + * output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t d_de_mode:3; + /** d_hsync_mode : R/W; bitpos: [11:9]; default: 0; + * the output spi_hsync is delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t d_hsync_mode:3; + /** d_vsync_mode : R/W; bitpos: [14:12]; default: 0; + * the output spi_vsync is delayed by system clock cycles, 0: output without delayed, + * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: + * output with the spi_clk. Can be configured in CONF state. + */ + uint32_t d_vsync_mode:3; + /** de_idle_pol : R/W; bitpos: [15]; default: 0; + * It is the idle value of spi_de. + */ + uint32_t de_idle_pol:1; + /** hs_blank_en : R/W; bitpos: [16]; default: 0; + * 1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one + * trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans. + */ + uint32_t hs_blank_en:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_lcd_d_mode_reg_t; + +/** Type of lcd_d_num register + * reserved + */ +typedef union { + struct { + /** d_dqs_num : R/W; bitpos: [1:0]; default: 0; + * the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t d_dqs_num:2; + /** d_cd_num : R/W; bitpos: [3:2]; default: 0; + * the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t d_cd_num:2; + /** d_de_num : R/W; bitpos: [5:4]; default: 0; + * the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t d_de_num:2; + /** d_hsync_num : R/W; bitpos: [7:6]; default: 0; + * the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t d_hsync_num:2; + /** d_vsync_num : R/W; bitpos: [9:8]; default: 0; + * the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t d_vsync_num:2; + uint32_t reserved_10:22; + }; + uint32_t val; +} spi_lcd_d_num_reg_t; + +/** Type of reg_date register + * reserved + */ +typedef union { + struct { + /** date : RW; bitpos: [27:0]; default: 26243648; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_reg_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_ctrl1_reg_t ctrl1; + volatile spi_ctrl2_reg_t ctrl2; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_mosi_dlen_reg_t mosi_dlen; + volatile spi_miso_dlen_reg_t miso_dlen; + volatile spi_misc_reg_t misc; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_slv_wrbuf_dlen_reg_t slv_wrbuf_dlen; + volatile spi_slv_rdbuf_dlen_reg_t slv_rdbuf_dlen; + volatile spi_slv_rd_byte_reg_t slv_rd_byte; + volatile spi_fsm_reg_t fsm; + volatile spi_hold_reg_t hold; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_out_link_reg_t dma_out_link; + volatile spi_dma_in_link_reg_t dma_in_link; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_in_err_eof_des_addr_reg_t in_err_eof_des_addr; + volatile spi_in_suc_eof_des_addr_reg_t in_suc_eof_des_addr; + volatile spi_inlink_dscr_reg_t inlink_dscr; + volatile spi_inlink_dscr_bf0_reg_t inlink_dscr_bf0; + volatile spi_inlink_dscr_bf1_reg_t inlink_dscr_bf1; + volatile spi_out_eof_bfr_des_addr_reg_t out_eof_bfr_des_addr; + volatile spi_out_eof_des_addr_reg_t out_eof_des_addr; + volatile spi_outlink_dscr_reg_t outlink_dscr; + volatile spi_outlink_dscr_bf0_reg_t outlink_dscr_bf0; + volatile spi_outlink_dscr_bf1_reg_t outlink_dscr_bf1; + volatile spi_dma_out_status_reg_t dma_out_status; + volatile spi_dma_in_status_reg_t dma_in_status; + volatile uint32_t data_buf[18]; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dout_num_reg_t dout_num; + volatile spi_lcd_ctrl_reg_t lcd_ctrl; + volatile spi_lcd_ctrl1_reg_t lcd_ctrl1; + volatile spi_lcd_ctrl2_reg_t lcd_ctrl2; + volatile spi_lcd_d_mode_reg_t lcd_d_mode; + volatile spi_lcd_d_num_reg_t lcd_d_num; + uint32_t reserved_104[190]; + volatile spi_reg_date_reg_t reg_date; } spi_dev_t; + extern spi_dev_t GPSPI2; //FSPI extern spi_dev_t GPSPI3; //HSPI #ifndef __cplusplus -_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi"); +_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32s3/register/soc/spi_struct.h b/components/soc/esp32s3/register/soc/spi_struct.h index 6bcf5596876..c01e72c726b 100644 --- a/components/soc/esp32s3/register/soc/spi_struct.h +++ b/components/soc/esp32s3/register/soc/spi_struct.h @@ -1,420 +1,1381 @@ -/* - * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 OR MIT + * SPDX-License-Identifier: Apache-2.0 OR MIT */ -#ifndef _SOC_SPI_STRUCT_H_ -#define _SOC_SPI_STRUCT_H_ +#pragma once #include + #ifdef __cplusplus extern "C" { #endif -typedef volatile struct spi_dev_s { - union { - struct { - uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ - uint32_t reserved18 : 5; /*reserved*/ - uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/ - uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ - uint32_t reserved25 : 7; /*reserved*/ - }; - uint32_t val; - } cmd; - uint32_t addr; - union { - struct { - uint32_t reserved0 : 3; /*reserved*/ - uint32_t dummy_out : 1; /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/ - uint32_t reserved4 : 1; /*reserved*/ - uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved11 : 3; /*reserved*/ - uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved17 : 1; /*reserved*/ - uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/ - uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/ - uint32_t reserved22 : 1; /*reserved*/ - uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ - uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ - uint32_t reserved27 : 5; /*reserved*/ - }; - uint32_t val; - } ctrl; - union { - struct { - uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ - uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ - uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ - uint32_t reserved22 : 9; /*reserved*/ - uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ - }; - uint32_t val; - } clock; - union { - struct { - uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved1 : 2; /*reserved*/ - uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ - uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ - uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ - uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ - uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ - uint32_t reserved10 : 2; /*reserved*/ - uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ - uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ - uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ - uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ - uint32_t reserved16 : 1; /*reserved*/ - uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t reserved18 : 6; /*reserved*/ - uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ - uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ - uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ - uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ - }; - uint32_t val; - } user; - union { - struct { - uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ - uint32_t reserved8 : 8; /*reserved*/ - uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ - uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ - uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user1; - union { - struct { - uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/ - uint32_t reserved16 : 11; /*reserved*/ - uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/ - uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - }; - uint32_t val; - } user2; - union { - struct { - uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ - uint32_t reserved18 : 14; /*reserved*/ - }; - uint32_t val; - } ms_dlen; - union { - struct { - uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ - uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/ - uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ - uint32_t reserved13 : 3; /*reserved*/ - uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */ - uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ - uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ - uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ - uint32_t reserved20 : 3; /*reserved*/ - uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ - uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ - uint32_t reserved25 : 4; /*reserved*/ - uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ - uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ - uint32_t quad_din_pin_swap : 1; /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.*/ - }; - uint32_t val; - } misc; - union { - struct { - uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/ - uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ - uint32_t reserved17 : 15; /*reserved*/ - }; - uint32_t val; - } din_mode; - union { - struct { - uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/ - uint32_t reserved16 : 16; /*reserved*/ - }; - uint32_t val; - } din_num; - union { - struct { - uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ - uint32_t reserved9 : 23; /*reserved*/ - }; - uint32_t val; - } dout_mode; - union { - struct { - uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/ - uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/ - uint32_t reserved2 : 16; /*reserved*/ - uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ - uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ - uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ - uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ - uint32_t reserved22 : 5; /*reserved*/ - uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ - uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ - uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/ - uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ - uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/ - }; - uint32_t val; - } dma_conf; - union { - struct { - uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_ena; - union { - struct { - uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_clr; - union { - struct { - uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */ - uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */ - uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ - uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ - uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ - uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ - uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ - uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ - uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ - uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ - uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ - uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ - uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ - uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */ - uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ - uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ - uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/ - uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/ - uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_raw; - union { - struct { - uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/ - uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_st; - union { - struct { - uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ - uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ - uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/ - uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/ - uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/ - uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/ - uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/ - uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/ - uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ - uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ - uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ - uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ - uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/ - uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ - uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ - uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ - uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/ - uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/ - uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/ - uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/ - uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/ - uint32_t reserved21 : 11; /*reserved*/ - }; - uint32_t val; - } dma_int_set; - uint32_t reserved_48; - uint32_t reserved_4c; - uint32_t reserved_50; - uint32_t reserved_54; - uint32_t reserved_58; - uint32_t reserved_5c; - uint32_t reserved_60; - uint32_t reserved_64; - uint32_t reserved_68; - uint32_t reserved_6c; - uint32_t reserved_70; - uint32_t reserved_74; - uint32_t reserved_78; - uint32_t reserved_7c; - uint32_t reserved_80; - uint32_t reserved_84; - uint32_t reserved_88; - uint32_t reserved_8c; - uint32_t reserved_90; - uint32_t reserved_94; - uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/ - uint32_t reserved_d8; - uint32_t reserved_dc; - union { - struct { - uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/ - uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/ - uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */ - uint32_t reserved4 : 4; /*reserved*/ - uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ - uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ - uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ - uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ - uint32_t reserved12 : 10; /*reserved*/ - uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/ - uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ - uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ - uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/ - uint32_t reserved29 : 3; /*reserved*/ - }; - uint32_t val; - } slave; - union { - struct { - uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */ - uint32_t last_command : 8; /*In the slave mode it is the value of command.*/ - uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/ - }; - uint32_t val; - } slave1; - union { - struct { - uint32_t clk_en : 1; /*Set this bit to enable clk gate*/ - uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/ - uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ - uint32_t reserved3 : 29; /*reserved*/ - }; - uint32_t val; - } clk_gate; - uint32_t reserved_ec; - union { - struct { - uint32_t date : 28; /*SPI register version.*/ - uint32_t reserved28 : 4; /*reserved*/ - }; - uint32_t val; - } date; +/** Group: User-defined control registers */ +/** Type of cmd register + * Command control register + */ +typedef union { + struct { + /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + uint32_t conf_bitlen:18; + uint32_t reserved_18:5; + /** update : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI module + * clock domain, which is only used in SPI master mode. + */ + uint32_t update:1; + /** usr : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit is set. + * The bit will be cleared once the operation done.1: enable 0: disable. Can not be + * changed by CONF_buf. + */ + uint32_t usr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} spi_cmd_reg_t; + +/** Type of addr register + * Address value register + */ +typedef union { + struct { + /** usr_addr_value : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + uint32_t usr_addr_value:32; + }; + uint32_t val; +} spi_addr_reg_t; + +/** Type of user register + * SPI USER control register + */ +typedef union { + struct { + /** doutdin : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t doutdin:1; + uint32_t reserved_1:2; + /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. + * Can be configured in CONF state. + */ + uint32_t qpi_mode:1; + /** opi_mode : R/W; bitpos: [4]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. + * Can be configured in CONF state. + */ + uint32_t opi_mode:1; + /** tsck_i_edge : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = + * spi_ck_i. 1:tsck = !spi_ck_i. + */ + uint32_t tsck_i_edge:1; + /** cs_hold : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_hold:1; + /** cs_setup : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + uint32_t cs_setup:1; + /** rsck_i_edge : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = + * !spi_ck_i. 1:rsck = spi_ck_i. + */ + uint32_t rsck_i_edge:1; + /** ck_out_edge : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can + * be configured in CONF state. + */ + uint32_t ck_out_edge:1; + uint32_t reserved_10:2; + /** fwrite_dual : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_dual:1; + /** fwrite_quad : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_quad:1; + /** fwrite_oct : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals. Can be configured in CONF + * state. + */ + uint32_t fwrite_oct:1; + /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans + * will continue. 0: The seg-trans will end after the current SPI seg-trans or this is + * not seg-trans mode. Can be configured in CONF state. + */ + uint32_t usr_conf_nxt:1; + uint32_t reserved_16:1; + /** sio : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso signals share + * the same pin. 1: enable 0: disable. Can be configured in CONF state. + */ + uint32_t sio:1; + uint32_t reserved_18:6; + /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: + * disable. Can be configured in CONF state. + */ + uint32_t usr_miso_highpart:1; + /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable + * 0: disable. Can be configured in CONF state. + */ + uint32_t usr_mosi_highpart:1; + /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be configured in + * CONF state. + */ + uint32_t usr_dummy_idle:1; + /** usr_mosi : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_mosi:1; + /** usr_miso : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in CONF + * state. + */ + uint32_t usr_miso:1; + /** usr_dummy : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_dummy:1; + /** usr_addr : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_addr:1; + /** usr_command : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in CONF state. + */ + uint32_t usr_command:1; + }; + uint32_t val; +} spi_user_reg_t; + +/** Type of user1 register + * SPI USER control register 1 + */ +typedef union { + struct { + /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + uint32_t usr_dummy_cyclelen:8; + uint32_t reserved_8:8; + /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master + * FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in + * GP-SPI master FD/HD-mode. + */ + uint32_t mst_wfull_err_end_en:1; + /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup + * bit. Can be configured in CONF state. + */ + uint32_t cs_setup_time:5; + /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. + * Can be configured in CONF state. + */ + uint32_t cs_hold_time:5; + /** usr_addr_bitlen : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_addr_bitlen:5; + }; + uint32_t val; +} spi_user1_reg_t; + +/** Type of user2 register + * SPI USER control register 2 + */ +typedef union { + struct { + /** usr_command_value : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + uint32_t usr_command_value:16; + uint32_t reserved_16:11; + /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error + * is valid in GP-SPI master FD/HD-mode. + */ + uint32_t mst_rempty_err_end_en:1; + /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be (bit_num-1). Can + * be configured in CONF state. + */ + uint32_t usr_command_bitlen:4; + }; + uint32_t val; +} spi_user2_reg_t; + + +/** Group: Control and configuration registers */ +/** Type of ctrl register + * SPI control register + */ +typedef union { + struct { + uint32_t reserved_0:3; + /** dummy_out : R/W; bitpos: [3]; default: 0; + * 0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, + * the FSPI bus signals are output. Can be configured in CONF state. + */ + uint32_t dummy_out:1; + uint32_t reserved_4:1; + /** faddr_dual : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_dual:1; + /** faddr_quad : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_quad:1; + /** faddr_oct : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t faddr_oct:1; + /** fcmd_dual : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_dual:1; + /** fcmd_quad : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_quad:1; + /** fcmd_oct : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF + * state. + */ + uint32_t fcmd_oct:1; + uint32_t reserved_11:3; + /** fread_dual : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_dual:1; + /** fread_quad : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_quad:1; + /** fread_oct : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can + * be configured in CONF state. + */ + uint32_t fread_oct:1; + uint32_t reserved_17:1; + /** q_pol : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t q_pol:1; + /** d_pol : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in + * CONF state. + */ + uint32_t d_pol:1; + /** hold_pol : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be + * configured in CONF state. + */ + uint32_t hold_pol:1; + /** wp_pol : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output low. Can + * be configured in CONF state. + */ + uint32_t wp_pol:1; + uint32_t reserved_22:1; + /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF + * state. + */ + uint32_t rd_bit_order:2; + /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be + * configured in CONF state. + */ + uint32_t wr_bit_order:2; + uint32_t reserved_27:5; + }; + uint32_t val; +} spi_ctrl_reg_t; + +/** Type of ms_dlen register + * SPI data bit length control register + */ +typedef union { + struct { + /** ms_data_bitlen : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit length in + * master mode DMA controlled transfer or CPU controlled transfer. The value is also + * the configured bit length in slave mode DMA RX controlled transfer. The register + * value shall be (bit_num-1). Can be configured in CONF state. + */ + uint32_t ms_data_bitlen:18; + uint32_t reserved_18:14; + }; + uint32_t val; +} spi_ms_dlen_reg_t; + +/** Type of misc register + * SPI misc register + */ +typedef union { + struct { + /** cs0_dis : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs0_dis:1; + /** cs1_dis : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs1_dis:1; + /** cs2_dis : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs2_dis:1; + /** cs3_dis : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs3_dis:1; + /** cs4_dis : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs4_dis:1; + /** cs5_dis : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can + * be configured in CONF state. + */ + uint32_t cs5_dis:1; + /** ck_dis : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state. + */ + uint32_t ck_dis:1; + /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + uint32_t master_cs_pol:6; + uint32_t reserved_13:3; + /** clk_data_dtr_en : R/W; bitpos: [16]; default: 0; + * 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR + * mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. + */ + uint32_t clk_data_dtr_en:1; + /** data_dtr_en : R/W; bitpos: [17]; default: 0; + * 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. + * Can be configured in CONF state. + */ + uint32_t data_dtr_en:1; + /** addr_dtr_en : R/W; bitpos: [18]; default: 0; + * 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t addr_dtr_en:1; + /** cmd_dtr_en : R/W; bitpos: [19]; default: 0; + * 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master + * 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be + * configured in CONF state. + */ + uint32_t cmd_dtr_en:1; + uint32_t reserved_20:3; + /** slave_cs_pol : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be configured in + * CONF state. + */ + uint32_t slave_cs_pol:1; + /** dqs_idle_edge : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. Can be configured in CONF state. + */ + uint32_t dqs_idle_edge:1; + uint32_t reserved_25:4; + /** ck_idle_edge : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be + * configured in CONF state. + */ + uint32_t ck_idle_edge:1; + /** cs_keep_active : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + uint32_t cs_keep_active:1; + /** quad_din_pin_swap : R/W; bitpos: [31]; default: 0; + * 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: + * spi quad input swap disable. Can be configured in CONF state. + */ + uint32_t quad_din_pin_swap:1; + }; + uint32_t val; +} spi_misc_reg_t; + +/** Type of dma_conf register + * SPI DMA control register + */ +typedef union { + struct { + /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; + * Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: + * DMA TX FIFO is ready for sending data. + */ + uint32_t dma_outfifo_empty:1; + /** dma_infifo_full : RO; bitpos: [1]; default: 1; + * Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. + * 0: DMA RX FIFO is ready for receiving data. + */ + uint32_t dma_infifo_full:1; + uint32_t reserved_2:16; + /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. + */ + uint32_t dma_slv_seg_trans_en:1; + /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + uint32_t slv_rx_seg_trans_clr_en:1; + /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + uint32_t slv_tx_seg_trans_clr_en:1; + /** rx_eof_en : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to + * the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: + * spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or + * spi_dma_seg_trans_done in seg-trans. + */ + uint32_t rx_eof_en:1; + uint32_t reserved_22:5; + /** dma_rx_ena : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + uint32_t dma_rx_ena:1; + /** dma_tx_ena : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + uint32_t dma_tx_ena:1; + /** rx_afifo_rst : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI master and + * slave mode transfer. + */ + uint32_t rx_afifo_rst:1; + /** buf_afifo_rst : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU + * controlled mode transfer and master mode transfer. + */ + uint32_t buf_afifo_rst:1; + /** dma_afifo_rst : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA + * controlled mode transfer. + */ + uint32_t dma_afifo_rst:1; + }; + uint32_t val; +} spi_dma_conf_reg_t; + +/** Type of slave register + * SPI slave control register + */ +typedef union { + struct { + /** clk_mode : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed + * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: + * SPI clock is always on. Can be configured in CONF state. + */ + uint32_t clk_mode:2; + /** clk_mode_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: + * support spi clk mode 0 and 2, first edge output data B[1]/B[6]. + */ + uint32_t clk_mode_13:1; + /** rsck_data_out : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge + * 0: output data at tsck posedge + */ + uint32_t rsck_data_out:1; + uint32_t reserved_4:4; + /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * DMA controlled mode(Rd_DMA). 0: others + */ + uint32_t slv_rddma_bitlen_en:1; + /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in DMA controlled mode(Wr_DMA). 0: others + */ + uint32_t slv_wrdma_bitlen_en:1; + /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in + * CPU controlled mode(Rd_BUF). 0: others + */ + uint32_t slv_rdbuf_bitlen_en:1; + /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length + * in CPU controlled mode(Wr_BUF). 0: others + */ + uint32_t slv_wrbuf_bitlen_en:1; + uint32_t reserved_12:10; + /** dma_seg_magic_value : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + uint32_t dma_seg_magic_value:4; + /** slave_mode : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + uint32_t slave_mode:1; + /** soft_reset : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. Can be + * configured in CONF state. + */ + uint32_t soft_reset:1; + /** usr_conf : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans + * will start. 0: This is not seg-trans mode. + */ + uint32_t usr_conf:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_slave_reg_t; + +/** Type of slave1 register + * SPI slave control register 1 + */ +typedef union { + struct { + /** slv_data_bitlen : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + uint32_t slv_data_bitlen:18; + /** slv_last_command : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + uint32_t slv_last_command:8; + /** slv_last_addr : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + uint32_t slv_last_addr:6; + }; + uint32_t val; +} spi_slave1_reg_t; + + +/** Group: Clock control registers */ +/** Type of clock register + * SPI clock control register + */ +typedef union { + struct { + /** clkcnt_l : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be + * 0. Can be configured in CONF state. + */ + uint32_t clkcnt_l:6; + /** clkcnt_h : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it + * must be 0. Can be configured in CONF state. + */ + uint32_t clkcnt_h:6; + /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + */ + uint32_t clkcnt_n:6; + /** clkdiv_pre : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + */ + uint32_t clkdiv_pre:4; + uint32_t reserved_22:9; + /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system + * clock. Can be configured in CONF state. + */ + uint32_t clk_equ_sysclk:1; + }; + uint32_t val; +} spi_clock_reg_t; + +/** Type of clk_gate register + * SPI module clock and register clock control + */ +typedef union { + struct { + /** clk_en : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + uint32_t clk_en:1; + /** mst_clk_active : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + uint32_t mst_clk_active:1; + /** mst_clk_sel : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. + * 0: XTAL CLK. + */ + uint32_t mst_clk_sel:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} spi_clk_gate_reg_t; + + +/** Group: Timing registers */ +/** Type of din_mode register + * SPI input delay mode configuration + */ +typedef union { + struct { + /** din0_mode : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din0_mode:2; + /** din1_mode : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din1_mode:2; + /** din2_mode : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din2_mode:2; + /** din3_mode : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din3_mode:2; + /** din4_mode : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din4_mode:2; + /** din5_mode : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din5_mode:2; + /** din6_mode : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din6_mode:2; + /** din7_mode : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input without delayed, + * 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input + * with the spi_clk. Can be configured in CONF state. + */ + uint32_t din7_mode:2; + /** timing_hclk_active : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF + * state. + */ + uint32_t timing_hclk_active:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} spi_din_mode_reg_t; + +/** Type of din_num register + * SPI input delay number configuration + */ +typedef union { + struct { + /** din0_num : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din0_num:2; + /** din1_num : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din1_num:2; + /** din2_num : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din2_num:2; + /** din3_num : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din3_num:2; + /** din4_num : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din4_num:2; + /** din5_num : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din5_num:2; + /** din6_num : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din6_num:2; + /** din7_num : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: + * delayed by 2 cycles,... Can be configured in CONF state. + */ + uint32_t din7_num:2; + uint32_t reserved_16:16; + }; + uint32_t val; +} spi_din_num_reg_t; + +/** Type of dout_mode register + * SPI output delay mode configuration + */ +typedef union { + struct { + /** dout0_mode : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout0_mode:1; + /** dout1_mode : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout1_mode:1; + /** dout2_mode : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout2_mode:1; + /** dout3_mode : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout3_mode:1; + /** dout4_mode : R/W; bitpos: [4]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout4_mode:1; + /** dout5_mode : R/W; bitpos: [5]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout5_mode:1; + /** dout6_mode : R/W; bitpos: [6]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout6_mode:1; + /** dout7_mode : R/W; bitpos: [7]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output without delayed, + * 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t dout7_mode:1; + /** d_dqs_mode : R/W; bitpos: [8]; default: 0; + * The output signal SPI_DQS is delayed by the SPI module clock, 0: output without + * delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be + * configured in CONF state. + */ + uint32_t d_dqs_mode:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} spi_dout_mode_reg_t; + + +/** Group: Interrupt registers */ +/** Type of dma_int_ena register + * SPI interrupt enable register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_ena : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_ena:1; + /** dma_outfifo_empty_err_int_ena : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_ena:1; + /** slv_ex_qpi_int_ena : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_ena:1; + /** slv_en_qpi_int_ena : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_ena:1; + /** slv_cmd7_int_ena : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_ena:1; + /** slv_cmd8_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_ena:1; + /** slv_cmd9_int_ena : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_ena:1; + /** slv_cmda_int_ena : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_ena:1; + /** slv_rd_dma_done_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_ena:1; + /** slv_wr_dma_done_int_ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_ena:1; + /** slv_rd_buf_done_int_ena : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_ena:1; + /** slv_wr_buf_done_int_ena : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_ena:1; + /** trans_done_int_ena : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_ena:1; + /** dma_seg_trans_done_int_ena : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_ena:1; + /** seg_magic_err_int_ena : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_ena:1; + /** slv_buf_addr_err_int_ena : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_ena:1; + /** slv_cmd_err_int_ena : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_ena:1; + /** mst_rx_afifo_wfull_err_int_ena : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_ena:1; + /** mst_tx_afifo_rempty_err_int_ena : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_ena:1; + /** app2_int_ena : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_ena:1; + /** app1_int_ena : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_ena:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_ena_reg_t; + +/** Type of dma_int_clr register + * SPI interrupt clear register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_clr : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_clr:1; + /** dma_outfifo_empty_err_int_clr : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_clr:1; + /** slv_ex_qpi_int_clr : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_clr:1; + /** slv_en_qpi_int_clr : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_clr:1; + /** slv_cmd7_int_clr : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_clr:1; + /** slv_cmd8_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_clr:1; + /** slv_cmd9_int_clr : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_clr:1; + /** slv_cmda_int_clr : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_clr:1; + /** slv_rd_dma_done_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_clr:1; + /** slv_wr_dma_done_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_clr:1; + /** slv_rd_buf_done_int_clr : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_clr:1; + /** slv_wr_buf_done_int_clr : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_clr:1; + /** trans_done_int_clr : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_clr:1; + /** dma_seg_trans_done_int_clr : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_clr:1; + /** seg_magic_err_int_clr : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_clr:1; + /** slv_buf_addr_err_int_clr : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_clr:1; + /** slv_cmd_err_int_clr : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_clr:1; + /** mst_rx_afifo_wfull_err_int_clr : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_clr:1; + /** mst_tx_afifo_rempty_err_int_clr : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_clr:1; + /** app2_int_clr : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_clr:1; + /** app1_int_clr : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_clr:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_clr_reg_t; + +/** Type of dma_int_raw register + * SPI interrupt raw register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the + * receive data. 0: Others. + */ + uint32_t dma_infifo_full_err_int_raw:1; + /** dma_outfifo_empty_err_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in + * master mode and send out all 0 in slave mode. 0: Others. + */ + uint32_t dma_outfifo_empty_err_int_raw:1; + /** slv_ex_qpi_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_ex_qpi_int_raw:1; + /** slv_en_qpi_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission + * is ended. 0: Others. + */ + uint32_t slv_en_qpi_int_raw:1; + /** slv_cmd7_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd7_int_raw:1; + /** slv_cmd8_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd8_int_raw:1; + /** slv_cmd9_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is + * ended. 0: Others. + */ + uint32_t slv_cmd9_int_raw:1; + /** slv_cmda_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is + * ended. 0: Others. + */ + uint32_t slv_cmda_int_raw:1; + /** slv_rd_dma_done_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_dma_done_int_raw:1; + /** slv_wr_dma_done_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_dma_done_int_raw:1; + /** slv_rd_buf_done_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_rd_buf_done_int_raw:1; + /** slv_wr_buf_done_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF + * transmission is ended. 0: Others. + */ + uint32_t slv_wr_buf_done_int_raw:1; + /** trans_done_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is + * ended. 0: others. + */ + uint32_t trans_done_int_raw:1; + /** dma_seg_trans_done_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. + * And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans + * is not ended or not occurred. + */ + uint32_t dma_seg_trans_done_int_raw:1; + /** seg_magic_err_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer + * is error in the DMA seg-conf-trans. 0: others. + */ + uint32_t seg_magic_err_int_raw:1; + /** slv_buf_addr_err_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address + * of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is + * bigger than 63. 0: Others. + */ + uint32_t slv_buf_addr_err_int_raw:1; + /** slv_cmd_err_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the + * current SPI slave HD mode transmission is not supported. 0: Others. + */ + uint32_t slv_cmd_err_int_raw:1; + /** mst_rx_afifo_wfull_err_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO + * write-full error when SPI inputs data in master mode. 0: Others. + */ + uint32_t mst_rx_afifo_wfull_err_int_raw:1; + /** mst_tx_afifo_rempty_err_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF + * AFIFO read-empty error when SPI outputs data in master mode. 0: Others. + */ + uint32_t mst_tx_afifo_rempty_err_int_raw:1; + /** app2_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + */ + uint32_t app2_int_raw:1; + /** app1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + */ + uint32_t app1_int_raw:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_raw_reg_t; + +/** Type of dma_int_st register + * SPI interrupt status register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_st : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_st:1; + /** dma_outfifo_empty_err_int_st : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_st:1; + /** slv_ex_qpi_int_st : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_st:1; + /** slv_en_qpi_int_st : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_st:1; + /** slv_cmd7_int_st : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_st:1; + /** slv_cmd8_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_st:1; + /** slv_cmd9_int_st : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_st:1; + /** slv_cmda_int_st : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_st:1; + /** slv_rd_dma_done_int_st : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_st:1; + /** slv_wr_dma_done_int_st : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_st:1; + /** slv_rd_buf_done_int_st : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_st:1; + /** slv_wr_buf_done_int_st : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_st:1; + /** trans_done_int_st : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_st:1; + /** dma_seg_trans_done_int_st : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_st:1; + /** seg_magic_err_int_st : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_st:1; + /** slv_buf_addr_err_int_st : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_st:1; + /** slv_cmd_err_int_st : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_st:1; + /** mst_rx_afifo_wfull_err_int_st : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_st:1; + /** mst_tx_afifo_rempty_err_int_st : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_st:1; + /** app2_int_st : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_st:1; + /** app1_int_st : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_st:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_st_reg_t; + +/** Type of dma_int_set register + * SPI interrupt software set register + */ +typedef union { + struct { + /** dma_infifo_full_err_int_set : WT; bitpos: [0]; default: 0; + * The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + uint32_t dma_infifo_full_err_int_set:1; + /** dma_outfifo_empty_err_int_set : WT; bitpos: [1]; default: 0; + * The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + uint32_t dma_outfifo_empty_err_int_set:1; + /** slv_ex_qpi_int_set : WT; bitpos: [2]; default: 0; + * The software set bit for SPI slave Ex_QPI interrupt. + */ + uint32_t slv_ex_qpi_int_set:1; + /** slv_en_qpi_int_set : WT; bitpos: [3]; default: 0; + * The software set bit for SPI slave En_QPI interrupt. + */ + uint32_t slv_en_qpi_int_set:1; + /** slv_cmd7_int_set : WT; bitpos: [4]; default: 0; + * The software set bit for SPI slave CMD7 interrupt. + */ + uint32_t slv_cmd7_int_set:1; + /** slv_cmd8_int_set : WT; bitpos: [5]; default: 0; + * The software set bit for SPI slave CMD8 interrupt. + */ + uint32_t slv_cmd8_int_set:1; + /** slv_cmd9_int_set : WT; bitpos: [6]; default: 0; + * The software set bit for SPI slave CMD9 interrupt. + */ + uint32_t slv_cmd9_int_set:1; + /** slv_cmda_int_set : WT; bitpos: [7]; default: 0; + * The software set bit for SPI slave CMDA interrupt. + */ + uint32_t slv_cmda_int_set:1; + /** slv_rd_dma_done_int_set : WT; bitpos: [8]; default: 0; + * The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + uint32_t slv_rd_dma_done_int_set:1; + /** slv_wr_dma_done_int_set : WT; bitpos: [9]; default: 0; + * The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + uint32_t slv_wr_dma_done_int_set:1; + /** slv_rd_buf_done_int_set : WT; bitpos: [10]; default: 0; + * The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + uint32_t slv_rd_buf_done_int_set:1; + /** slv_wr_buf_done_int_set : WT; bitpos: [11]; default: 0; + * The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + uint32_t slv_wr_buf_done_int_set:1; + /** trans_done_int_set : WT; bitpos: [12]; default: 0; + * The software set bit for SPI_TRANS_DONE_INT interrupt. + */ + uint32_t trans_done_int_set:1; + /** dma_seg_trans_done_int_set : WT; bitpos: [13]; default: 0; + * The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + uint32_t dma_seg_trans_done_int_set:1; + /** seg_magic_err_int_set : WT; bitpos: [14]; default: 0; + * The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + uint32_t seg_magic_err_int_set:1; + /** slv_buf_addr_err_int_set : WT; bitpos: [15]; default: 0; + * The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + uint32_t slv_buf_addr_err_int_set:1; + /** slv_cmd_err_int_set : WT; bitpos: [16]; default: 0; + * The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + uint32_t slv_cmd_err_int_set:1; + /** mst_rx_afifo_wfull_err_int_set : WT; bitpos: [17]; default: 0; + * The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + uint32_t mst_rx_afifo_wfull_err_int_set:1; + /** mst_tx_afifo_rempty_err_int_set : WT; bitpos: [18]; default: 0; + * The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + uint32_t mst_tx_afifo_rempty_err_int_set:1; + /** app2_int_set : WT; bitpos: [19]; default: 0; + * The software set bit for SPI_APP2_INT interrupt. + */ + uint32_t app2_int_set:1; + /** app1_int_set : WT; bitpos: [20]; default: 0; + * The software set bit for SPI_APP1_INT interrupt. + */ + uint32_t app1_int_set:1; + uint32_t reserved_21:11; + }; + uint32_t val; +} spi_dma_int_set_reg_t; + +/** Group: Version register */ +/** Type of date register + * Version control + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34607504; + * SPI register version. + */ + uint32_t date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} spi_date_reg_t; + + +typedef struct { + volatile spi_cmd_reg_t cmd; + volatile spi_addr_reg_t addr; + volatile spi_ctrl_reg_t ctrl; + volatile spi_clock_reg_t clock; + volatile spi_user_reg_t user; + volatile spi_user1_reg_t user1; + volatile spi_user2_reg_t user2; + volatile spi_ms_dlen_reg_t ms_dlen; + volatile spi_misc_reg_t misc; + volatile spi_din_mode_reg_t din_mode; + volatile spi_din_num_reg_t din_num; + volatile spi_dout_mode_reg_t dout_mode; + volatile spi_dma_conf_reg_t dma_conf; + volatile spi_dma_int_ena_reg_t dma_int_ena; + volatile spi_dma_int_clr_reg_t dma_int_clr; + volatile spi_dma_int_raw_reg_t dma_int_raw; + volatile spi_dma_int_st_reg_t dma_int_st; + volatile spi_dma_int_set_reg_t dma_int_set; + uint32_t reserved_048[20]; + volatile uint32_t data_buf[16]; + uint32_t reserved_0d8[2]; + volatile spi_slave_reg_t slave; + volatile spi_slave1_reg_t slave1; + volatile spi_clk_gate_reg_t clk_gate; + uint32_t reserved_0ec; + volatile spi_date_reg_t date; } spi_dev_t; + extern spi_dev_t GPSPI2; extern spi_dev_t GPSPI3; + +#ifndef __cplusplus +_Static_assert(sizeof(spi_dev_t) == 0xf4, "Invalid size of spi_dev_t structure"); +#endif + #ifdef __cplusplus } #endif - - - -#endif /*_SOC_SPI_STRUCT_H_ */