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On Xtensa the PMS violation shares ETS_MEMACCESS_ERR_INUM with the cache error
and arrives as PANIC_RSN_CACHEERR. ESP32-S2 tells the two apart, ESP32-S3 never
did (//MV note in dd938eb95), so PMS faults were reported as "Cache error".
panic_memprot_fill_info() now claims the panic only when
esp_mprot_get_active_intr() reports a pending violation, and the ESP32-S3 cache
error path consults it, falling back to the cache error report as before.
RISC-V has a dedicated interrupt, so its reporting stays unconditional.
ESP32-S2 and ESP32 are untouched.