b4131c6ac5
The addend in `emac_hal_ptp_start()` was derived from the floating-point `config->ptp_req_accuracy_ns` instead of the integer `base_increment` register that actually drives the sub-second update. The cast to `uint8_t` loses the fractional part, so the un-corrected addend leaves the PTP clock running off-rate. Example: with a 40 MHz XTAL and the default `req_accuracy_ns = 40`, `base_increment` rounds 85.899 up to 86, leaving the clock +1170 ppm fast — well outside the IEEE 802.1AS neighborRateRatio limit (~±200 ppm), so strict-1AS bridges refuse asCapable. Compute the addend from the stored `base_increment` for both rollover modes: `addend = 2^32 * clk_period_ns / increment_ns`. Measured on ESP32-P4: neighborRateRatio drops from +1147.5 ppm to +4.2 ppm, and asCapable is granted. Co-authored-by: Ondrej Kosta <panzer412@gmail.com>
ESP Hardware Abstraction Layer for Ethernet MAC Peripheral
Note
This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
Overview
The esp_hal_emac component provides a Hardware Abstraction Layer for the Ethernet MAC (EMAC) peripherals across all ESP-IDF supported targets. It serves as a foundation for the higher-level Ethernet drivers, offering a consistent interface to interact with Ethernet MAC hardware while hiding the complexities of chip-specific implementations.
Architecture
The HAL architecture consists of two primary layers:
-
HAL Layer (Upper): Defines the operational sequences and data structures required to interact with EMAC peripherals, including:
- Initialization and de-initialization
- MAC configuration (speed, duplex, promiscuous mode)
- DMA descriptor management
- PHY interface management (MII/RMII)
- Address filtering and frame reception/transmission
- Flow control and interrupt handling
-
Low-Level Layer (Bottom): Acts as a translation layer between the HAL and the register definitions in the
soccomponent, handling:- Register access abstractions
- Chip-specific register configurations
- Hardware feature compatibility
Features
- Unified Ethernet MAC interface across all ESP chip families
- Support for MII and RMII PHY interfaces
- DMA-based frame transmission and reception
- MAC address filtering with multiple address support
- Flow control (pause frame) support
- Promiscuous mode and multicast filtering
- Hardware checksum offloading
- IEEE 1588 PTP (Precision Time Protocol) support on compatible chips
- Sleep retention support on compatible chips
- Configurable DMA burst length
- VLAN tag insertion/removal/replacement
- IP checksum insertion for TCP/UDP/ICMP headers
Usage
This component is primarily used by ESP-IDF peripheral drivers such as esp_eth. It is also utilized by system components that require Ethernet functionality.
For advanced developers implementing custom Ethernet solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
Dependencies
soc: Provides chip-specific register definitions and peripheral informationhal: Core hardware abstraction utilities and macros