Marius Vikhammer 11fcd7aa16 fix(riscv): use CSR 0xC10 for privilege mode on ESP32-H21 ...

Reading 0x810 raises an illegal-instruction exception on this chip, which
made the CPU test app panic.

2026-09-17 17:49:12 +08:00

..

include

fix(riscv): use CSR 0xC10 for privilege mode on ESP32-H21

2026-09-17 17:49:12 +08:00

ld

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

test_apps

feat(build): add RISC-V ZCMP post-link workaround check

2026-07-22 13:04:20 +07:00

check_zcmp_workaround.cmake

feat(build): add RISC-V ZCMP post-link workaround check

2026-07-22 13:04:20 +07:00

CMakeLists.txt

fix(ulp): clarify buildv2 child marker

2026-07-29 13:08:23 +09:00

hints.yml

feat(build): add RISC-V ZCMP post-link workaround check

2026-07-22 13:04:20 +07:00

instruction_decode.c

refactor(tools): Tidy up core component files copyright ignore

2024-01-22 18:07:35 +08:00

interrupt_clic.c

fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00

interrupt_intc.c

refactor(riscv): added a new API for the interrupts

2024-01-18 16:36:53 +08:00

interrupt_plic.c

refactor(esp_tee): Revised the secure service ID numbering scheme

2025-01-23 12:39:19 +05:30

interrupt.c

feat(intr): basic interrupt/freertos support for C61

2024-06-12 09:25:47 +08:00

linker.lf

refactor(esp32c61): bus_monitor backward compatible refactor

2025-04-08 22:50:04 +08:00

rv_utils.c

refactor(esp32c61): bus_monitor backward compatible refactor

2025-04-08 22:50:04 +08:00

vectors_clic.S

fix(esp_system): enable linking with LLD on RISC-V targets

2026-08-13 21:23:36 +02:00

vectors_intc.S

refactor(esp_system): Update all references of the memory protection configs

2025-08-04 11:43:01 +05:30

vectors.S

fix(riscv): implement a workaround for Zcmp hardware bug

2026-04-10 15:03:09 +08:00