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fix(riscv): use CSR 0xC10 for privilege mode on ESP32-H21

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Reading 0x810 raises an illegal-instruction exception on this chip, which
made the CPU test app panic.
This commit is contained in:
Marius Vikhammer
2026-09-17 17:49:12 +08:00
parent 3dd1a4671a
commit 11fcd7aa16
2 changed files with 4 additions and 1 deletions
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3
components/esp_hw_support/test_apps/cpu/pytest_cpu.py
View File

@@ -25,6 +25,7 @@ def _run_non_recoverable_case(dut: IdfDut, test_name: str, expected_reason: str)
'config,target',
[
('default', 'supported_targets'),
('default', 'esp32h21'),
],
indirect=['config', 'target'],
)
@@ -37,6 +38,7 @@ def test_cpu(dut: IdfDut) -> None:
'config,target',
[
('default', 'supported_targets'),
('default', 'esp32h21'),
],
indirect=['config', 'target'],
)
@@ -49,6 +51,7 @@ def test_cpu_reset(dut: IdfDut) -> None:
'config,target',
[
('default', 'supported_targets'),
('default', 'esp32h21'),
],
indirect=['config', 'target'],
)

2
components/riscv/include/riscv/csr.h
View File

@@ -203,7 +203,7 @@ extern "C" {
#define STPC2 0xBF2
/* Espressif's custom CSR for the current privilege mode */
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32H21
#define CSR_PRV_MODE 0xC10
#else
#define CSR_PRV_MODE 0x810