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82 lines
3.1 KiB
Markdown
82 lines
3.1 KiB
Markdown
# ESP Hardware Abstraction Layer for Parallel IO Peripheral(s)
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_parlio` component provides a **Hardware Abstraction Layer** for Parallel IO (PARLIO) peripherals across all ESP-IDF supported targets. PARLIO enables high-speed parallel data transfer between the ESP chip and external devices, supporting both transmit (TX) and receive (RX) operations with configurable data widths and timing characteristics.
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## Architecture
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The PARLIO HAL is structured in two main sub-layers:
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1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control PARLIO peripherals (e.g., initialization, unit configuration, transfer start/stop).
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2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
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## Supported PARLIO Units
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This HAL supports PARLIO peripherals with the following units depending on the ESP chip:
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- **TX Unit**: Transmits parallel data to external devices
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- Configurable data width
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- Clock output or external clock input support
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- Chip select (CS) signal support (on some chips)
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- Valid signal generation and delay control
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- **RX Unit**: Receives parallel data from external devices
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- Configurable data width
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- Clock input support
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- Multiple sampling modes (level-controlled, pulse-controlled, software-controlled)
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- Timeout detection support
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## Features
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### Clock Configuration
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- Multiple clock source selection
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- Configurable clock divider with integer and fractional support (on some chips)
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- Independent clock configuration for TX and RX units
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### Data Transfer Control
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- Configurable bus width
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- Bit packing order configuration (LSB/MSB)
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- Sample clock edge selection (rising/falling edge)
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- Frame length configuration
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### RX Unit Features
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- Level-controlled receive mode with active high/low enable signal
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- Pulse-controlled receive mode with configurable start/end pulse counting
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- Software-controlled receive mode
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- RX timeout detection and threshold configuration
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- Clock gating support
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- Data line as enable signal support
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### TX Unit Features
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- Data length configuration
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- Clock gating support
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- Valid signal generation and delay control (on some chips)
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- Idle data value configuration
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- DMA EOF condition support (on some chips)
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### Interrupt and Event Handling
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- TX FIFO empty event
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- RX FIFO full event
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- TX EOF (End of Frame) event
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- Interrupt enable/disable and status management
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### Power Management
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- Sleep retention support (on some chips)
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- Register state preservation during sleep
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## Usage
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The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_parlio`.
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Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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