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70 lines
3.4 KiB
Markdown
70 lines
3.4 KiB
Markdown
# ESP Hardware Abstraction Layer for SPI Peripheral
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_spi` component provides a **Hardware Abstraction Layer** for the General Purpose SPI (GPSPI) peripherals across all ESP-IDF supported targets. It serves as a foundation for the higher-level SPI drivers, offering a consistent interface to interact with SPI hardware while hiding the complexities of chip-specific implementations.
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## Architecture
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The HAL architecture consists of two primary layers:
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1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with SPI peripherals, including:
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- Initialization and de-initialization
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- Clock configuration and timing calculations
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- Device and transaction setup
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- Master, slave, and slave HD (Half Duplex) mode operations
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2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling:
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- Register access abstractions
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- Chip-specific register configurations
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- Hardware feature compatibility
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## Features
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- Unified SPI interface across all ESP chip families
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- Support for multiple operation modes:
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- **Master mode**: Full-duplex and half-duplex communication
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- **Slave mode**: Standard slave operation
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- **Slave HD mode**: Half Duplex slave mode with segment-based transactions (on supported chips)
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- Flexible SPI line configurations (1/2/4-line modes)
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- Configurable clock sources and frequency settings
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- Support for various transaction formats (command, address, dummy, data phases)
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## Usage
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This component is primarily used by ESP-IDF peripheral drivers such as `esp_driver_spi`. It provides the low-level hardware abstraction needed for SPI communication with external devices.
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For advanced developers implementing custom SPI solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
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### Typical Usage Flow
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**Master Mode (without DMA):**
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1. Initialize the SPI bus
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2. Setup clock speed configuration
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3. Call `setup_device` to update parameters for a specific device
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4. Call `setup_trans` to update parameters for a specific transaction
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5. Prepare data to send into hardware registers
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6. Trigger the SPI transaction to start
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7. Wait until the transaction is complete
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8. Fetch the received data
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**Slave Mode (without DMA):**
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1. Initialize the SPI bus with `spi_slave_hal_init`
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2. Configure device parameters (mode, bit order, etc.) in the HAL context
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3. Call `spi_slave_hal_setup_device` to update parameters for the device
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4. Prepare data to send and receiving buffer
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5. Call `spi_slave_hal_set_trans_bitlen` to set transaction bit length
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6. Call `spi_slave_hal_user_start` to trigger the SPI transaction to start
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7. Wait until the transaction is done with `spi_slave_hal_usr_is_done`
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8. Call `spi_slave_hal_store_result` to store the received data
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9. Call `spi_slave_hal_get_rcv_bitlen` to get the received data length
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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- `esp_hal_gpio`: Required for ESP32 to access GPIO matrix delay information
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