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37 lines
1.6 KiB
Markdown
37 lines
1.6 KiB
Markdown
# ESP Hardware Abstraction Layer for GPIO Peripheral
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_gpio` component provides a **Hardware Abstraction Layer** for General-Purpose Input/Output (GPIO) across all ESP-IDF supported targets.
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## Architecture
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The GPIO HAL is structured in two main sub-layers:
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1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to configure and control GPIO pins (e.g., direction, level, pull mode, interrupt enable/disable).
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2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
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## Features
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- Configure pin direction (input/output)
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- Set and get logic levels
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- Internal pull-up/pull-down configuration (on supported chips)
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- Open-drain/output mode selection (on supported chips)
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- Interrupt configuration (edge/level) and handling
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- Drive strength configuration (on supported chips)
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- Deep sleep and light sleep helpers for pin retention (on supported chips)
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## Usage
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The HAL functions primarily serve ESP-IDF peripheral drivers and system components that need efficient and portable GPIO control.
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Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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