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Harshal Patil 938833c3b8 fix(esp_psram): clear the PSRAM ECC configuration when ECC is disabled

An ECC-enabled image sets the ECC attribute on MSPI PMS PSRAM region 0,
and that register survives a digital core reset (USB Serial/JTAG reset,
software reset). An ECC-disabled image never wrote it, so the controller
kept enforcing the 16 byte ECC access rules while the software reported
an MSPI alignment of 1. Program the ECC state on every boot instead.

2026-09-28 12:08:21 +05:30

..

fix(esp_psram): clear the PSRAM ECC configuration when ECC is disabled

2026-09-28 12:08:21 +05:30

fix(esp_psram): fix unused-but-set-variable warning with GCC 16

2026-07-02 07:55:14 +05:30

feat(mspi): supported psram & flash 120MHz timing tuning

2025-10-28 09:52:36 +08:00

feat(mspi): support 120MHz flash and psram for esp32c61

2026-01-21 14:38:04 +08:00

fix(clk): update H4 to use 64MHz clock for mspi

2026-01-04 14:07:01 +08:00

change(psram): use 200M as default

2025-11-17 16:25:57 +08:00

feat(psram): allow PSRAM to enter halfsleep mode during light sleep

2026-02-28 22:33:34 +08:00

refactor(spi_flash): move os layer to esp_mspi and chip configs to spi_flash

2026-09-09 14:17:00 +08:00

feat(ldo): support s31 psram sdmmc power domain

2026-05-21 09:09:14 +08:00

fix(build_system): cleaned up esp_psram dependencies

2026-08-24 11:12:17 +08:00

feat(system_init): introduce pre-scheduler and pre-app main handler registrations

2026-09-02 16:58:44 +03:00

ci(psram): add esp32p4 250M XIP coverage with flash 120M HPM-DC

2026-08-12 17:11:00 +08:00

refactor(esp_common): centralize ALIGN_UP/ALIGN_DOWN into esp_macros.h

2026-07-06 13:36:06 +08:00

CMakeLists.txt

refactor(spi_flash): move os layer to esp_mspi and chip configs to spi_flash

2026-09-09 14:17:00 +08:00

Kconfig

…

Kconfig.spiram.common

change(heap): reserve DMA pool with low priority MALLOC_CAP_DEFAULT caps

2026-07-03 20:54:30 +08:00

linker.lf

feat(ldo): support s31 psram sdmmc power domain

2026-05-21 09:09:14 +08:00

project_include.cmake

feat(cmakev2): add IDF_CUSTOM_TOOLCHAIN for sub-projects with non-IDF toolchains

2026-07-14 16:54:57 +09:00

README.md

feat(mspi): supported mspi flash and psram isr

2025-12-26 01:04:45 +00:00

sdkconfig.rename.esp32s2

…

sdkconfig.rename.esp32s3

…

README.md

PSRAM MSPI Interrupt Handling

Overview

This file (system_layer/esp_psram_mspi.c) handles PSRAM-specific MSPI interrupt registration.

Chip Type	`MSPI_LL_INTR_SHARED`	Behavior
Shared IRQ	1	Register to shared MSPI dispatcher
Separate IRQ	0	Register standalone PSRAM ISR via `esp_intr_alloc()`

Documentation

For detailed architecture, flow diagrams, and API reference, see:

esp_hw_support/README.md - MSPI Interrupt Logic