Commit Graph
22 Commits
Author SHA1 Message Date
chenjianqiang bcfe684951 bugfix(timer): add a macro to control making the XTAL related functions 2019-11-26 12:39:46 +00:00
chenjianqiang 856d9f7d89 bugfix(timer): recover get raw interrupt status function 2019-11-26 12:39:46 +00:00
chenjianqiang 857dec108d feat(ledc): refactor ledc driver
1. add hal and low-level layer for ledc driver
2. support esp32s2beta ledc
2019-11-21 16:25:22 +08:00
chenjianqiang 9f9da9ec96 feat(timer): refator timer group driver
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
2019-11-21 14:14:19 +08:00
chenjianqiang 74e2e46402 bugfix(flash): add spi dio address bitlen configure in psram init 2019-08-14 20:57:30 +08:00
chenjianqiang a97fe5615f feat(timer): refator timer group driver (partly pick) 2019-08-09 13:46:29 +08:00
chenjianqiang e43513b610 bugfix(uart): uniform AT_CMD char configuration 2019-07-18 19:24:13 +08:00
chenjianqiang 91ae40e2ff uart: multichip support 2019-07-18 15:57:00 +08:00
chenjianqiang 4cc962353c feat(uart): update uart driver for esp32s2beta 2019-07-18 15:57:00 +08:00
chenjianqiang d77c74770a bugfix(flash): add flash config in app startup
We fixed some flash bugs in bootloader, but for the users used the old
vrsion bootloader, they can not fix these bugs via OTA, the solution is
add these updates in app startup.

These updates include:
1. SPI flash gpio matrix and drive strength configuration
2. SPI flash clock configuration
3. SPI flash read dummy configuration
4. SPI flash cs timing configuration
5. Update flash id of g_rom_flashchip
2019-07-18 14:40:59 +08:00
chenjianqiang 667113cf94 feat(i2c): update i2c driver for esp32s2beta 2019-07-10 11:41:36 +08:00
chenjianqiang 266baa8839 bugfix(flash): fix flash read error in DIO/26MHz mode 2019-07-08 01:50:07 +00:00
chenjianqiang d6c40c7c1d bugfix(flash): improve spi cs timing settings for flash
cs setup time is recomemded to be 1.5T, and cs hold time is recommended to be 2.5T.
(cs_setup = 1, cs_setup_time = 0; cs_hold = 1, cs_hold_time = 1)
2019-07-05 21:21:17 +08:00
chenjianqiang fd8b526f7c add two APIs into esp32beta.rom.spiflash.ld to fix compile error
When config flash mode as QIO mode, the error that esp_rom_spiflash_wait_idle
and esp_rom_spiflash_config_readmode are undefined happens when compile, so
add these two APIs to fix the error.
2019-06-21 21:50:48 +08:00
chenjianqiang cf2ba210ef uart: multichip support 2019-06-20 11:32:22 +08:00
chenjianqiang db138ae19b feat(psram): config SPI psram pins based on efuse value 2019-05-28 21:25:16 +08:00
chenjianqiang d68f1907ef bugfix(flash): improve flash dio read timing
When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).
2019-05-28 14:51:04 +08:00
chenjianqiang bd8733f74f feature(psram): add psram support for esp32-pico chip
1. esp32-pico use standard spi driver to access psram
2. for esp32-pico, flash and psram share the clock
3. for esp32-pico, psram cs io can be overwrite via menuconfig
2019-01-09 10:49:07 +08:00
chenjianqiang a0beff99d2 bugfix(psram): fix psram size acquisition method
1. Use BIT[7:5] of EID to determine psram size
2. Add ID support for 16Mbit psram
3. Remove module reset on SPI1
4. Confirmed with the vendor that only the old 32Mbit psram need special clock timing. For other psram chips, we should use standard QPI mode.
2018-11-28 17:05:37 +08:00
chenjianqiang a10b7e892c bugfix(psram): fix psram driver
1. remove use EID to distinguish psram voltage
2. 1V8 64Mbit psram and 3V3 64Mbit psram use the same psram driver(standard spi interface)
3. set cs hold time register as 1
2018-10-08 19:55:13 +08:00
chenjianqiang 542373b6ef feature(flash): support for QIO mode of XM25QU64A 2018-07-11 22:28:01 +08:00
chenjianqiang b5de860bcb revise the explain of a parameter(brk_len) in uart driver file 2018-05-14 19:47:16 +08:00