If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
registers (Flashboot protection included) will be re-enabled, and some
seconds later, will trigger an unintended reset.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
When building with BOOTLOADER_LOG_LEVEL lesser then VERBOSE, an error
code variable was being set but not consumed, resulting in a compiler
warning.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Builds for every chip other than ESP32 resulted in a compiler warning
due to "drom_load_addr_aligned" and "irom_load_addr_aligned" not being
used, besides being possible to actually reuse them.
Furthermore, extended the logic for the other similar variables.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
The body of the bootloader_debug_buffer function was conditioned to
macros that were never defined, resulting in deactivated code.
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This prevents the compiler error for the implicit declaration of
function "esp_rom_printf".
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Furthermore, RX_EOF_EN should only be set when SPI Slave is configured
for segment transfer mode and the "ms_data_bitlen" field is configured
to control the "IN_SUC_EOF" interrupt. Since "ms_data_bitlen" is not
set anymore for S2, C3 and S3, "RX_EOF_EN" should be cleared.
The maximum input length for the SPI Slave should be applied to the read
buffer configuration, not for the write buffer. Similarly, the output
configuration should also target the write buffer.
MOSI and MISO enablement were conditioned to the existence of TX
and RX buffers, respectively. This is valid for the SPI Master,
but for the SPI Slave the opposite is expected.
