LP GPIO input, output, interrupt, and wakeup were only tested
while the HP core was awake, or for wakeup alone.
Output is checked with a pulse train that the peer counts before HP
wakes. Releasing pad hold on wake can change a level by itself, so a
single level after wake does not prove LP drove the pin during sleep.
The peer arms its falling-edge counter while it still holds the pin
low, so the first pulse is not missed.
On P4 the edge is only visible with sleep-select left enabled, and
the HP trigger is kept by returning from LP main. The edge is applied
after sleep has settled.
The host side drives both boards through the shared sleep helper.
LP sleep tests repeat the same Unity menu sequence on two boards.
Helpers under test_apps/lp_core let a later app reuse that sequence
instead of copying the sleeper and peer steps.
PSRAM DQS delayline tuning calls mspi_timing_config_psram_set_tuning_delayline()
once per sample (~3100 times on ESP32-P4). A DEBUG print there blocks on UART
long enough to trip the bootloader RTC WDT (default 9s), so DEBUG builds
reset-loop and never reach app_main().
Remove that per-sample log. The selected phase is already reported once by
the phase-tuning stage. Add a startup test config that boots with SPIRAM
and DEBUG logging.
Closes https://github.com/espressif/esp-idf/issues/19158
Co-authored-by: Cursor <cursoragent@cursor.com>
GetGitRevisionDescription.cmake is a vendored copy of a file that many
third-party CMake projects ship too. The copies are not interchangeable:
this one takes git_describe(<var> <repo dir>) while the upstream one
takes
git_describe(<var>).
Whichever copy is included first sets the include guard variable and
every
later include returns early. Since this build system includes its copy
from the top level of the project, a component that vendors the upstream
variant and calls git_describe(<var>) ends up calling this function
without
the repository argument and fails to configure with "Function invoked
with
incorrect arguments". Components currently work around it by clearing
the
guard variable, which only works if they know about it.
Accept the one-argument form and resolve it against
CMAKE_CURRENT_SOURCE_DIR,
which is the directory of the caller, so the vendored copy describes the
repository it actually lives in. The argument list is unchanged, so the
existing git_describe(<var> <repo dir> [<extra git args>...]) calls keep
working, and no public function is renamed.
usb_serial_jtag_is_connected() is SOF-based and starts out connected, so a
transport committed while the bus was still enumerating could be dropped by
the configuration transition. The driver then never sees
SERIAL_IN_EP_DATA_FREE set again, and the TX path stays dead with the ring
filling until a chip reset.
Wait for the SET_LINE_CODE/DTR_CHG/RTS_CHG latch in INT_RAW, which the host
sets when it programs the port and the driver never clears. Transports from
before that open take the not-connected drop path, so the boot window is lost
instead of risking the wedge. C3 and S3 have no such interrupt, so the gate
falls back to the SOF check there, which is the behaviour from before.
The README documents the two states the gate does not cover, re-enumeration
without a chip reset and SERIAL_IN_EP_DATA_FREE reading 0 from boot.
C6-class chips have no USB OTG. Gate the new peripheral on a hidden
BUS_BUSY symbol so console, esp_trace, and OpenThread RCP keep the
USJ FIFO unless the operator releases it; do not steal the console.
Mute C3/S3 ROM dual-write once the driver owns the FIFO.
cjin
Wang Ning
Meet Patel
Island
C.S.M
Mahavir Jain
morris
guozifan
Erhan Kurubas
Gao Xu
Wang Meng Yang
Yi Ying
Roland Dobai
Jan Beran
Zhang Shuxian
Nachiket Kukade
Pranav Sonawane
Ren Peiying
Zhang Wen Xu
Guillaume Souchere
Zhou Xiao
Wan Lei
Jin ChengandCursor
Song Ruo Jing
Hu Rui