- The ROM text and data sections share the address range
(see SOC_I/DROM_MASK_LOW - SOC_I/DROM_MASK_HIGH).
- Initially, we had two PMP entries for this address range - one marking the
region as RX and the other as R.
- However, the latter entry is redundant as the former locks the PMP settings.
- We can divide the ROM region into text and data sections later when we
define boundaries marking these regions from the ROM.
- This change will introduce a breaking change for SoCs with the HMAC
peripheral. Turning on flash encryption will no longer enable NVS
encryption automatically.
Closes https://github.com/espressif/esp-idf/issues/12549
- This features allows the NVS encryption keys to be derived and protected using
the HMAC peripheral. Since the encryption keys are derived at runtime, they
are not stored anywhere in the flash and hence this feature does not require
a separate `nvs_keys` partition.
- As per the memory block diagram for ESP32-S3, the
internal memory address ranges as follows:
DRAM: 0x3FC88000 (== SOC_MEM_INTERNAL_LOW) <-> 0x3FCF0000
IRAM: 0x40378000 <-> 0x403E0000 (== SOC_MEM_INTERNAL_HIGH)
- to acknowledge the unused DCACHE added to DRAM for ESP32-S3
- For ESP32-S3, when the DCACHE size is set to 16 kB, the unused 48 kB is added to
the heap in 2 blocks of 32 kB (from 0x3FCF0000) and 16 kB (from 0x3C000000).
- But, if we try allocating memory from the 16 kB block and run an `esp_ptr_internal`
check on that memory pointer, it fails as the address block from 0x3C000000
corresponds to the external memory symbols SOC_DROM_LOW and SOC_EXTRAM_DATA_LOW.
(E.g. freertos - If the IDLE task stack buffer gets allocated from this region,
the firmware will abort due to this failure).
- Thus, the checks `esp_ptr_internal`, `esp_ptr_in_drom` and `esp_ptr_byte_accessible`
have been updated to acknowledge this memory as a part of the DRAM.
Co-authored-by: Mahavir Jain <mahavir@espressif.com>
- For esp32-c2, the `CONFIG_NEWLIB_NANO_FORMAT` is enabled by
default which does not allow printing `int64_t` values
- Copied these values to a `uint32_t` variable for printing
them properly
- Use DPORT_WRITE_REG (volatile writes) wrappers to write to the
MPI peripheral
- Updated the previous workaround added for the same issue as it
was failing in some long runs and with `COMPILER_OPTIMIZATION_PERF`
enabled.
- The test performance numbers had to be updated due to the
performance penalty introduced by this fix.
Closes https://github.com/espressif/esp-idf/issues/10403
- Add support for esp32s2, esp32c3 and esp32c2 for the `memprot`-related tests
- Preliminary support for esp32s3 has also been added,
the test app will be enabled for esp32s3 later when
the memprot-related issues are fixed.
- Override panic handler to dump the violation intr status
- Dump the `memprot` violation registers before calling the
real panic handler
- Handle `Illegal Instruction` exception in case of memprot permission violation
* In esp32c3 with `memprot` enabled, if we try to execute arbitrary code
from RTC_FAST_MEM we get an `Illegal Instruction` exception from the panic
handler rather than a `Memory Protection Fault`.
* This is because the Illegal Instruction interrupt occurs earlier than the
memory protection interrupt due to a higher interrupt latency.
- Added minor improvements to `panic` test app
* Replaced existing API to disable flash cache which did not disabled cache always
(`esp_flash_default_chip->os_func->start(esp_flash_default_chip->os_func_data)`)
with `spi_flash_enable_interrupts_caches_and_other_cpu`
* Included some required headers explicitly (`esp_memory_utils.h` and `esp_heap_caps.h`)
- `protocomm` depends on a config option `CONFIG_WIFI_PROV_BLE_FORCE_ENCRYPTION`
from `wifi_provisioning`; however, a lower layer component (`protocomm`) should
not have any `#ifdef` guard dependent on an upper layer component (`wifi_provisioning`).
- Added a new `ble_link_encryption` flag in `protocomm_ble_config_t` to manage the same
Closes https://github.com/espressif/esp-idf/issues/9443
- If internet connectivity weakened or disappeared suddenly while we were
in the TLS handshake stage, the app got stuck at that point indefinitely.
- This was because when timeout was not explicitly specified in esp_tls_cfg_t,
the default timeout was set at the wrong place. This causes the sockets to be
setup with zero timeout, hence the indefinite wait.
- When PSRAM is enabled, the heap integrity check APIs
(`heap_caps_check_integrity` and `heap_caps_check_integrity_all`)
take more time to execute and keep the interrupts disabled for a
longer time.
- While checking if ciphersuite uses RSA key exchange methods,
the APIs `mbedtls_ssl_get_ciphersuite_id_from_ssl` and
`mbedtls_ssl_ciphersuite_from_id` were used to get the ciphersuite
info.
- However, this is incorrect as we need the ciphersuite info from the
handshake instance and not the ssl_session instance.
- The callback `open_fn` is used for creating a new SSL session
with httpd_sess_new.
- If the call fails, the active socket count (httpd_data->hd_sd_active_count)
is not incremented. But, httpd_sess_delete is called, which decrements the
count, resulting in a negative value for several failed session creations
in a row.
Closes https://github.com/espressif/esp-idf/issues/9683
- Made tcp_transport_errors codes public to indicate
TCP connection issues not covered in socket's errno
- Added API to translate tcp_transport_error codes
to esp_err_t codes for TCP Transport
Co-authored-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Laukik Hase
