Extends esp_backtrace_print_all_tasks() to RISC-V targets. For running
tasks, registers are captured using UNW_GET_CONTEXT(); for suspended
tasks, the saved RvExcFrame on the task stack is used. Dual-core support
follows the same IPC pattern as the Xtensa implementation.
Backtrace output adapts to the configured backtrace method:
EH-frame, frame-pointer, or register dump (with a hint to enable
frame-pointer mode).
This is a workaround for rom code issue, which can cause the chip to end in infinite loop
when reset is triggered from esptool/idf-monitor. This is only applicable to ESP32-C5 rev <= 1.0.
Closes https://github.com/espressif/esp-idf/issues/18089
Configure the ESP32-H4 ICACHE1_USAGE SRAM ownership bit during app startup
instead of relying on the value left by the bootloader.
Clear ICACHE1_USAGE before external memory/cache setup so single-core apps can
reclaim the ICACHE1 SRAM region as RAM. For multicore apps, set the bit again
when applying multicore cache settings so the region is assigned back to
ICACHE1.
This keeps the app behavior aligned with its own single-core or multicore
configuration even when bootloader and app configs differ.
bugfix: fix wifi loss packet and missing interrupt issues when switching root clock source
Closes WIFI-7270, IDF-13957, and IDF-11064
See merge request espressif/esp-idf!46459
The configured maximum should match each target's fixed LP/RTC
reservations so menuconfig does not advertise values that the linker
cannot support.
Keep the linker failure explicit about CONFIG_ULP_COPROC_RESERVE_MEM
because application RTC sections still share the remaining LP/RTC RAM.
On RISC-V chips with SPIRAM support (esp32c5, esp32c61, esp32h4, esp32p4,
esp32s31), esp_restart_noos() was disabling the cache while the current
stack pointer could still be in external RAM. Any stack access after cache
disable (function call, local variable spill) would then fault with
"Cache disabled but cached memory region accessed".
Xtensa chips (esp32, esp32s2, esp32s3) already had this guard via the
SET_STACK macro. Add the equivalent for RISC-V:
- Add rv_utils_set_sp() to riscv/rv_utils.h (plain "mv sp, %0" with a
memory clobber; no window register management needed on RISC-V)
- In each affected system_internal.c, under
CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM, check whether the current
SP is in PSRAM and if so switch it to the top of internal BSS before
any cache disable or writeback operation
- Fix xTaskCreateStaticPinnedToCore() stack size argument in the
spiram_stack test (was passing bytes instead of word count)
- Mark the null-pointer write in func_do_exception() as volatile to
prevent the compiler from optimizing it away
- Extend the [spiram_stack] tests to RISC-V by sharing fibonacci() and
the task/finish helpers across architectures, guarding only the
Xtensa-specific WINDOWBASE/WINDOWSTART prints
Konstantin Kondrashov
Meet Patel
Konstantin Kondrashov
wuzhenghui
Renz Christian Bagaporo
Peter Dragun
Renz Bagaporo
hebinglin
Li Shuai
Gao Xu
Alexey Gerenkov
Marius VikhammerandCursor
Chen Jichang
Jiang Jiang Jian
sibeibei
Guillaume Souchere
Samuel Obuch
C.S.M
yinqingzhao
Alexey Lapshin
morris
armando
Song Ruo Jing
Roland Dobai