Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-08-13 04:42:01 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_system): update cache livelock workaround bind to interrupt WDT configuration

Browse Source
This commit is contained in:
wuzhenghui
2026-05-28 12:10:59 +08:00
parent ddfb7e4b58
commit b88a809b8c
6 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/bt/controller/esp32/hli_vectors.S
View File

@@ -47,7 +47,7 @@ _l4_save_ctx:
xt_highint4:
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/*
Here, Timer2 is used to count a little time(50us).
The subsequent dram0 write operation is blocked due to live lock, which will
@@ -101,7 +101,7 @@ xt_highint4:
rsr a2, EPC1
s32i a2, a0, 24
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
movi a0, 0
xsr a0, XT_REG_INTENABLE /* disable all interrupts */
movi a2, ~(1<<16)

2
components/esp_system/include/esp_private/esp_int_wdt.h
View File

@@ -36,7 +36,7 @@ void esp_int_wdt_init(void);
*/
void esp_int_wdt_cpu_init(void);
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/**
* @brief Reconfigure WDT stage timeouts (ticks).
*

8
components/esp_system/int_wdt.c
View File

@@ -29,7 +29,7 @@
#include "esp_private/sleep_retention.h"
#endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#include "esp_private/eco3_livelock_workaround.h"
#endif
@@ -102,7 +102,7 @@ static void ESP_SYSTEM_IRAM_ATTR reconfigure_ticks(uint32_t stage0_ticks, uint32
wdt_hal_write_protect_enable(&iwdt_context);
}
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
static portMUX_TYPE s_iwdt_configure_lock = portMUX_INITIALIZER_UNLOCKED;
void ESP_SYSTEM_IRAM_ATTR esp_int_wdt_reconfigure_ticks(uint32_t stage0_ticks, uint32_t stage1_ticks)
{
@@ -131,7 +131,7 @@ static void ESP_SYSTEM_IRAM_ATTR tick_hook(void)
return;
}
#endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
esp_int_wdt_set_livelock_params(CONFIG_ESP_INT_WDT_TIMEOUT_MS);
esp_int_wdt_reconfigure_ticks(esp_int_wdt_livelock_get_feed_stage0_ticks(), IWDT_STAGE1_TIMEOUT_US);
#else
@@ -163,7 +163,7 @@ void esp_int_wdt_init(void)
esp_int_wdt_retention_enable(IWDT_TIMER_GROUP);
#endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/*
* This is a workaround for issue WDT-3.15 in "ESP32 ECO and workarounds for
* Bugs" document.

4
components/esp_system/port/include/private/esp_private/eco3_livelock_workaround.h
View File

@@ -14,7 +14,7 @@
extern "C" {
#endif
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#if CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/**
* @brief Enable or disable the livelock workaround and reconfigure the interrupt WDT.
@@ -49,7 +49,7 @@ void esp_int_wdt_set_livelock_params(uint32_t timeout_ms);
*/
void esp_int_wdt_reset_livelock_params(void);
#endif // CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
#endif // (CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX)
#ifdef __cplusplus
}

3
components/esp_system/port/soc/esp32/eco3_livelock_workaround.c
View File

@@ -45,6 +45,9 @@ uint32_t ESP_SYSTEM_IRAM_ATTR esp_int_wdt_livelock_get_feed_stage0_ticks(void)
void ESP_SYSTEM_IRAM_ATTR esp_int_wdt_livelock_workaround(bool enable)
{
if (!soc_has_cache_lock_bug()) {
return;
}
uint32_t stage0_ticks = IWDT_STAGE0_TIMEOUT_US;
if (enable) {
esp_int_wdt_set_livelock_params(CONFIG_ESP_INT_WDT_TIMEOUT_MS);

8
components/xtensa/xtensa_vectors.S
View File

@@ -474,7 +474,7 @@ _DebugExceptionVector:
.type _xt_debugexception,@function
.align 4
_xt_debugexception:
#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#if (CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
s32i a0, sp, XT_STK_EXIT
#define XT_DEBUGCAUSE_DI (5)
@@ -489,7 +489,7 @@ _xt_debugexception:
extui a0, a0, XT_DEBUGCAUSE_DI, 1
bnez a0, _xt_debug_di_exc
1:
#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#endif //(CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
movi a0,PANIC_RSN_DEBUGEXCEPTION
wsr a0,XT_REG_EXCCAUSE
@@ -507,7 +507,7 @@ _xt_debugexception:
#endif // CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME
rfi XCHAL_DEBUGLEVEL
#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#if (CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
.align 4
_xt_debug_di_exc:
@@ -566,7 +566,7 @@ _xt_debug_di_exc:
rsr a0, XT_REG_EXCSAVE+XCHAL_DEBUGLEVEL
rfi XCHAL_DEBUGLEVEL
#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#endif //(CONFIG_ESP_INT_WDT && CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
#endif // XCHAL_HAVE_DEBUG
/*