- Remove GPTIMER and TIMG related definitions from soc_caps_full.h files
- Move timer peripheral definitions to appropriate HAL layer files
- Update references across components to use proper HAL abstractions
- Consolidate timer group and GPTIMER capabilities organization
- Ensure consistent timer configuration across all ESP32 variants
This refactoring improves the separation of concerns between SOC
capabilities and HAL implementations for timer-related functionality.
feat(ledc): Add LEDC support for ESP32H21 and ESP32H4
Closes IDF-12343, IDF-12344, IDF-12920, IDF-11568, IDF-11569, IDF-12115, and IDF-13672
See merge request espressif/esp-idf!41172
The `-mtune=esp-base` option is identical to the default tuning profile,
except that `slow_unaligned_access` is set to false.
This reduces the instruction count for built-in `memcpy` and improves
performance, since our chips can handle misaligned access with minimal
penalty (without triggering exceptions).
Example:
void load(uint32_t *r, char* x) {
memcpy(r, x, sizeof(uint32_t));
}
void store(char* x, uint32_t v) {
memcpy(x, &v, sizeof(uint32_t));
}
Previously generated code:
load:
lbu a5,2(a1)
lbu a3,0(a1)
lbu a4,1(a1)
sb a5,2(a0)
sb a3,0(a0)
sb a4,1(a0)
lbu a5,3(a1)
sb a5,3(a0)
ret
store:
srli a3,a1,8
srli a4,a1,16
srli a5,a1,24
addi sp,sp,-16
sb a1,0(a0)
sb a3,1(a0)
sb a4,2(a0)
sb a5,3(a0)
addi sp,sp,16
jr ra
With `-mtune=esp-base`:
load:
lw a5,0(a1)
sw a5,0(a0)
ret
store:
sw a1,0(a0)
ret
Inlining behavior
=================
Without `-mtune=esp-base`:
- `memcpy()` is inlined only when the compile-time size is ≤ 12 bytes.
- Maximum cost: ~25 instructions
With `-mtune=esp-base`:
- `memcpy()` is inlined for all compile-time constant sizes.
- Maximum cost: ~14 instructions
As a result, some applications may see reduced code size, while others
may increase slightly. However, performance always improves because
extra `memcpy` calls are eliminated.
Performance results
===================
esp32p4 (Ethernet iperf):
- No noticeable difference
esp32c61 (Wi-Fi iperf):
- ~2 Mb/s increase for TCP and UDP TX (may be within measurement error)
NOTE
====
Applies only to RISC-V chips that do not have the hardware issue marked
by the SOC_CPU_MISALIGNED_ACCESS_ON_PMP_MISMATCH_ISSUE macro.
PMP configurations for load and store addresses may
have different permissions (e.g., "R" vs. "RW").
Due to the timing alignment of internal signals, the address
permission check may be incorrectly applied during the second
part of a misaligned access transaction.
As a workaround, insert two instructions (e.g. ADDI/NOP) between
accessing to different memory regions. This spacing avoids the
false permission check caused by signal timing overlap.
liuning
Song Ruo Jing
wanckl
morris
laokaiyao
Jiang Jiang Jian
harshal.patil
muhaidong
Chen Jichang
C.S.M
Alexey Lapshin
Gao Xu
Armando (Dou Yiwen)
Yuan Yu
Wu Zheng Hui