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Merge branch 'feat/flash_enc_using_key_manager_v6.0' into 'release/v6.0'

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Support Flash Encryption using Key Manager (v6.0)

See merge request espressif/esp-idf!43459
This commit is contained in:
Jiang Jiang Jian
2025-11-24 10:35:48 +08:00
parent e497972772 9a18386202
commit ee4be1af57
64 changed files with 1382 additions and 766 deletions
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29
components/bootloader/Kconfig.projbuild
View File

@@ -839,6 +839,26 @@ menu "Security features"
Read https://docs.espressif.com/projects/esp-idf/en/latest/security/flash-encryption.html
before enabling.
choice SECURE_FLASH_ENCRYPTION_KEY_SOURCE
bool "Flash Encryption Key Source"
depends on SECURE_FLASH_ENC_ENABLED
default SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES
help
Specify the key source for the Flash Encryption Key
config SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES
bool "eFuse Key Block"
help
Use a key that is stored in the eFuses key blocks.
config SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
bool "Key Manager"
depends on SOC_KEY_MANAGER_SUPPORTED && SOC_KEY_MANAGER_FE_KEY_DEPLOY && \
!(IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3)
help
Use a key that is deployed using the Key Manager
endchoice
choice SECURE_FLASH_ENCRYPTION_KEYSIZE
bool "Size of generated XTS-AES key"
default SECURE_FLASH_ENCRYPTION_AES128
@@ -860,11 +880,16 @@ menu "Security features"
config SECURE_FLASH_ENCRYPTION_AES128
bool "AES-128 (256-bit key)"
depends on SOC_FLASH_ENCRYPTION_XTS_AES_128 && !(IDF_TARGET_ESP32C2 && SECURE_BOOT)
depends on SOC_FLASH_ENCRYPTION_XTS_AES_128 && \
((SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES && SOC_EFUSE_XTS_AES_KEY_128) || \
(SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR && SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128)) && \
!(IDF_TARGET_ESP32C2 && SECURE_BOOT)
config SECURE_FLASH_ENCRYPTION_AES256
bool "AES-256 (512-bit key)"
depends on SOC_FLASH_ENCRYPTION_XTS_AES_256
depends on SOC_FLASH_ENCRYPTION_XTS_AES_256 && \
((SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES && SOC_EFUSE_XTS_AES_KEY_256) || \
(SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR && SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256))
endchoice
choice SECURE_FLASH_ENCRYPTION_MODE

5
components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in
View File

@@ -91,6 +91,11 @@ SECTIONS
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:huk_hal.*(.literal .text .literal.* .text.*)
*libhal.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

1
components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in
View File

@@ -90,6 +90,7 @@ SECTIONS
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage)
*libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
*libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)

6
components/bootloader/subproject/main/ld/esp32p4/bootloader.rev3.ld.in
View File

@@ -89,8 +89,12 @@ SECTIONS
*libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
*libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
*libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
*libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage)
*libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
*libhal.a:huk_hal.*(.literal .text .literal.* .text.*)
*libhal.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
*libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)

2
components/bootloader_support/CMakeLists.txt
View File

@@ -93,6 +93,8 @@ endif()
if(BOOTLOADER_BUILD)
list(APPEND srcs "src/bootloader_panic.c")
list(APPEND priv_requires esp_security)
if(CONFIG_SECURE_FLASH_ENC_ENABLED)
list(APPEND srcs "src/flash_encryption/flash_encrypt.c"
"src/${IDF_TARGET}/flash_encryption_secure_features.c")

9
components/bootloader_support/include/esp_flash_encrypt.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include "esp_attr.h"
#include "esp_err.h"
#include "soc/soc_caps.h"
#include "hal/efuse_ll.h"
#include "sdkconfig.h"
#ifdef __cplusplus
@@ -184,14 +183,14 @@ void esp_flash_encryption_init_checks(void);
*/
esp_err_t esp_flash_encryption_enable_secure_features(void);
#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY
/** @brief Enable the key manager for flash encryption
*
* @return
* - ESP_OK - On success
*/
esp_err_t esp_flash_encryption_enable_key_mgr(void);
#endif // CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
esp_err_t esp_flash_encryption_use_efuse_key(void);
#endif // SOC_KEY_MANAGER_FE_KEY_DEPLOY
#endif /* BOOTLOADER_BUILD && CONFIG_SECURE_FLASH_ENC_ENABLED */

17
components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c
View File

@@ -11,10 +11,13 @@
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_log.h"
#include "hal/key_mgr_ll.h"
#include "esp_crypto_periph_clk.h"
#include "esp_key_mgr.h"
#include "hal/key_mgr_hal.h"
#include "hal/mspi_ll.h"
#include "soc/soc_caps.h"
#include "sdkconfig.h"
#include "hal/key_mgr_ll.h"
ESP_LOG_ATTR_TAG(TAG, "flash_encrypt");
@@ -69,18 +72,12 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
return ESP_OK;
}
esp_err_t esp_flash_encryption_enable_key_mgr(void)
esp_err_t esp_flash_encryption_use_efuse_key(void)
{
_key_mgr_ll_enable_bus_clock(true);
_key_mgr_ll_enable_peripheral_clock(true);
_key_mgr_ll_reset_register();
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
};
esp_crypto_key_mgr_enable_periph_clk(true);
// Force Key Manager to use eFuse key for XTS-AES operation
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
_mspi_timing_ll_reset_mspi();
key_mgr_hal_set_key_usage(ESP_KEY_MGR_FLASH_XTS_AES_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
return ESP_OK;
}

15
components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c
View File

@@ -11,6 +11,9 @@
#include "esp_efuse_table.h"
#include "esp_log.h"
#include "sdkconfig.h"
#include "esp_crypto_periph_clk.h"
#include "esp_key_mgr.h"
#include "hal/key_mgr_hal.h"
#include "hal/key_mgr_ll.h"
#include "hal/mspi_ll.h"
@@ -51,18 +54,12 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
return ESP_OK;
}
esp_err_t esp_flash_encryption_enable_key_mgr(void)
esp_err_t esp_flash_encryption_use_efuse_key(void)
{
_key_mgr_ll_enable_bus_clock(true);
_key_mgr_ll_enable_peripheral_clock(true);
_key_mgr_ll_reset_register();
while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) {
};
esp_crypto_key_mgr_enable_periph_clk(true);
// Force Key Manager to use eFuse key for XTS-AES operation
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
_mspi_timing_ll_reset_mspi();
key_mgr_hal_set_key_usage(ESP_KEY_MGR_FLASH_XTS_AES_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
return ESP_OK;
}

26
components/bootloader_support/src/flash_encrypt.c
View File

@@ -16,6 +16,10 @@
#include "hal/spi_flash_encrypt_hal.h"
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "esp_key_mgr.h"
#endif /* SOC_KEY_MANAGER_SUPPORTED */
#if CONFIG_IDF_TARGET_ESP32
#define CRYPT_CNT ESP_EFUSE_FLASH_CRYPT_CNT
#define WR_DIS_CRYPT_CNT ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT
@@ -444,12 +448,13 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
}
#endif
#if CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES
esp_efuse_purpose_t purposes[] = {
#if SOC_FLASH_ENCRYPTION_XTS_AES_256
#if SOC_EFUSE_XTS_AES_KEY_256
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1,
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2,
#endif
#if SOC_FLASH_ENCRYPTION_XTS_AES_128
#if SOC_EFUSE_XTS_AES_KEY_128
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#endif
};
@@ -482,6 +487,23 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
}
}
result &= secure;
#elif CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
#if CONFIG_SECURE_FLASH_ENCRYPTION_AES128
secure = esp_efuse_read_field_bit(ESP_EFUSE_KM_XTS_KEY_LENGTH_256);
result &= secure;
if (!secure) {
ESP_LOGW(TAG, "Not enabled Key Manager XTS-AES-128 key (set KM_XTS_KEY_LENGTH_256->1)");
}
#endif
const uint32_t force_key_mgr_key = esp_efuse_read_field_bit(ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY);
secure = (force_key_mgr_key & (1 << ESP_KEY_MGR_FORCE_USE_KM_XTS_AES_KEY));
result &= secure;
if (!secure) {
ESP_LOGW(TAG, "Not forcing Key Manager to use XTS-AES key (set FORCE_USE_KEY_MANAGER_KEY->1)");
}
#endif
#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {

214
components/bootloader_support/src/flash_encryption/flash_encrypt.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,14 @@
#include "esp_log.h"
#include "hal/wdt_hal.h"
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#if SOC_KEY_MANAGER_SUPPORTED
#include "esp_key_mgr.h"
#include "hal/key_mgr_ll.h"
#include "rom/key_mgr.h"
#include "esp_rom_crc.h"
#endif
#ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
#include "soc/sensitive_reg.h"
@@ -124,8 +132,158 @@ esp_err_t esp_flash_encrypt_check_and_update(void)
return ESP_OK;
}
#if CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
static esp_err_t key_manager_read_key_recovery_info(esp_key_mgr_key_recovery_info_t *key_recovery_info)
{
esp_err_t err = ESP_FAIL;
uint32_t crc = 0;
for (int i = 0; i < 2; i++) {
err = bootloader_flash_read(KEY_HUK_SECTOR_OFFSET(i), (uint32_t *)key_recovery_info, sizeof(esp_key_mgr_key_recovery_info_t), false);
if (err != ESP_OK) {
ESP_LOGD(TAG, "Failed to read key recovery info from Key Manager sector %d: %x", i, err);
continue;
}
// check Key Recovery Info magic
if (key_recovery_info->magic != KEY_HUK_SECTOR_MAGIC) {
ESP_LOGD(TAG, "Key Manager sector %d Magic %08x failed", i, key_recovery_info->magic);
continue;
}
if (key_recovery_info->key_type != ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
ESP_LOGD(TAG, "Key Manager sector %d has incorrect key type %d", i, key_recovery_info->key_type);
continue;
}
#if CONFIG_SECURE_FLASH_ENCRYPTION_AES256
if (key_recovery_info->key_len != ESP_KEY_MGR_XTS_AES_LEN_256) {
ESP_LOGD(TAG, "Key Manager sector %d has incorrect key length %d", i, key_recovery_info->key_len);
continue;
}
#else
if (key_recovery_info->key_len != ESP_KEY_MGR_XTS_AES_LEN_128) {
ESP_LOGD(TAG, "Key Manager sector %d has incorrect key length %d", i, key_recovery_info->key_len);
continue;
}
#endif
// check HUK Info CRC
crc = esp_rom_crc32_le(0, key_recovery_info->huk_info.info, HUK_INFO_LEN);
if (crc != key_recovery_info->huk_info.crc) {
ESP_LOGD(TAG, "Key Manager sector %d HUK Info CRC error", i);
continue;
}
// check Key Info 0 CRC
crc = esp_rom_crc32_le(0, key_recovery_info->key_info[0].info, KEY_INFO_LEN);
if (crc != key_recovery_info->key_info[0].crc) {
ESP_LOGD(TAG, "Key Manager sector %d Key Info 0 CRC error", i);
continue;
}
#if CONFIG_SECURE_FLASH_ENCRYPTION_AES256
// check Key Info 1 CRC
crc = esp_rom_crc32_le(0, key_recovery_info->key_info[1].info, KEY_INFO_LEN);
if (crc != key_recovery_info->key_info[1].crc) {
ESP_LOGD(TAG, "Key Manager sector %d Key Info 1 CRC error", i);
continue;
}
#endif
ESP_LOGI(TAG, "Valid Key Manager key recovery info found in sector %d", i);
return ESP_OK;
}
ESP_LOGD(TAG, "No valid key recovery info found");
return ESP_ERR_NOT_FOUND;
}
static esp_err_t key_manager_generate_key(esp_key_mgr_key_recovery_info_t *key_recovery_info)
{
ESP_LOGI(TAG, "Deploying new flash encryption key using Key Manager");
esp_key_mgr_random_key_config_t key_config;
memset(&key_config, 0, sizeof(esp_key_mgr_random_key_config_t));
key_config.key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
#if CONFIG_SECURE_FLASH_ENCRYPTION_AES256
key_config.key_len = ESP_KEY_MGR_XTS_AES_LEN_256;
#else
key_config.key_len = ESP_KEY_MGR_XTS_AES_LEN_128;
#endif
// Generate a new key and load it into Key Manager
esp_err_t err = esp_key_mgr_deploy_key_in_random_mode(&key_config, key_recovery_info);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to generate key for Key Manager: %x", err);
return err;
}
ESP_LOGV(TAG, "Successfully deployed new flash encryption key using Key Manager");
// Write the key recovery info of the newly generated key into the flash
for (int i = 0; i < 2; i++) {
err = bootloader_flash_erase_sector(i);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to erase sector %d: %x", i, err);
return err;
}
}
// Write the key recovery info of the newly generated key into the flash
err = bootloader_flash_write(KEY_HUK_SECTOR_OFFSET(0), (uint32_t *)key_recovery_info, sizeof(esp_key_mgr_key_recovery_info_t), false);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to write key recovery info to flash: %x", err);
return err;
}
ESP_LOGV(TAG, "Successfully wrote the newly generated Flash Encryption key recovery info into the flash");
return ESP_OK;
}
static esp_err_t key_manager_check_and_generate_key(void)
{
/*
1. Check if we have a valid key info in the first two sectors of the flash
2. If we have a valid key info, check if it is valid
1. If the key is valid, use it
2. If the key is not valid, generate a new key and load it into key manager
3. If not, generate a new key and load it into key manager
*/
esp_key_mgr_key_recovery_info_t key_recovery_info;
memset(&key_recovery_info, 0, sizeof(esp_key_mgr_key_recovery_info_t));
esp_err_t err = key_manager_read_key_recovery_info(&key_recovery_info);
if (err == ESP_ERR_NOT_FOUND) {
// No valid key recovery info found, generate a new key
err = key_manager_generate_key(&key_recovery_info);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to generate key for Key Manager: %x", err);
return err;
}
} else {
// Valid key recovery info found, use it
ESP_LOGI(TAG, "Using pre-deployed Key Manager key for flash encryption");
}
// Recover key using the key recovery info
err = esp_key_mgr_activate_key(&key_recovery_info);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to activate Key Manager key: %x", err);
return err;
}
return ESP_OK;
}
#endif
static esp_err_t check_and_generate_encryption_keys(void)
{
#if CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_EFUSES
size_t key_size = 32;
#ifdef CONFIG_IDF_TARGET_ESP32
enum { BLOCKS_NEEDED = 1 };
@@ -214,12 +372,60 @@ static esp_err_t check_and_generate_encryption_keys(void)
ESP_LOGI(TAG, "Using pre-loaded flash encryption key in efuse");
}
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY
// In the case of Key Manager supported targets, the default XTS-AES key source is set to Key Manager.
esp_flash_encryption_use_efuse_key();
#endif
#elif CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
esp_err_t err = key_manager_check_and_generate_key();
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to check and generate key using Key Manager: %x", err);
return err;
}
#if CONFIG_SECURE_FLASH_ENCRYPTION_AES128
err = esp_efuse_write_field_bit(ESP_EFUSE_KM_XTS_KEY_LENGTH_256);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to set the efuse bit KM_XTS_KEY_LENGTH_256: %x", err);
return err;
}
#endif
const uint32_t force_key_mgr_key_for_fe = 1 << ESP_KEY_MGR_FORCE_USE_KM_XTS_AES_KEY;
err = esp_efuse_write_field_blob(ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY, &force_key_mgr_key_for_fe, ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[0]->bit_count);
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to set the efuse bit %d (XTS-AES key) of FORCE_USE_KEY_MANAGER_KEY: %x", ESP_KEY_MGR_FORCE_USE_KM_XTS_AES_KEY, err);
return err;
}
ESP_LOGV(TAG, "Successfully activated the flash encryption key using Key Manager");
#endif
return ESP_OK;
}
esp_err_t esp_flash_encrypt_init(void)
{
if (esp_flash_encryption_enabled() || esp_flash_encrypt_initialized_once()) {
if (esp_flash_encryption_enabled()) {
return ESP_OK;
}
#if CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
if (!(key_mgr_ll_is_supported() && key_mgr_ll_flash_encryption_supported())) {
ESP_LOGE(TAG, "Flash Encryption using Key Manager is not supported, please use efuses instead");
return ESP_ERR_NOT_SUPPORTED;
}
#endif
if (esp_flash_encrypt_initialized_once()) {
#if CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR
// Allow generating a new key if the key recovery info is not present in the flash
esp_err_t err = key_manager_check_and_generate_key();
if (err != ESP_OK) {
ESP_LOGE(TAG, "Failed to recover key using Key Manager: %x", err);
return err;
}
#endif
return ESP_OK;
}
@@ -260,10 +466,6 @@ esp_err_t esp_flash_encrypt_contents(void)
REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1);
#endif
#if CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY
esp_flash_encryption_enable_key_mgr();
#endif
err = encrypt_bootloader(); // PART_SUBTYPE_BOOTLOADER_PRIMARY
if (err != ESP_OK) {
return err;

6
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
View File

@@ -286,7 +286,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
#if SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
if (block == EFUSE_BLK9 && (
#if SOC_FLASH_ENCRYPTION_XTS_AES_256
#if SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif
@@ -301,10 +301,10 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
#endif // SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY ||
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
#ifdef SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
#endif //#ifdef SOC_EFUSE_XTS_AES_KEY_256
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif

10
components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
View File

@@ -57,7 +57,7 @@ TEST_CASE("Test efuse API blocks burning XTS and ECDSA keys into BLOCK9", "[efus
uint8_t key[32] = {0};
esp_efuse_purpose_t purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY;
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
#if SOC_FLASH_ENCRYPTION_XTS_AES_256
#if SOC_EFUSE_XTS_AES_KEY_256
purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1;
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_write_key(EFUSE_BLK9, purpose, &key, sizeof(key)));
purpose = ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2;
@@ -86,7 +86,7 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
TEST_ASSERT_TRUE(esp_efuse_get_key_dis_write(num_key));
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY ||
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
#ifdef SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif
@@ -180,7 +180,7 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
esp_efuse_purpose_t purpose = g_purpose;
#if SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
if (num_key == EFUSE_BLK9 && (
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
#ifdef SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
#endif //#ifdef SOC_EFUSE_SUPPORT_XTS_AES_256_KEYS
@@ -224,7 +224,7 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
#else
ESP_EFUSE_KEY_PURPOSE_RESERVED,
#endif
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
#ifdef SOC_EFUSE_XTS_AES_KEY_256
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1,
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2,
#else
@@ -300,7 +300,7 @@ TEST_CASE("Test esp_efuse_write_keys", "[efuse]")
esp_efuse_block_t key_block = EFUSE_BLK_MAX;
enum { BLOCKS_NEEDED1 = 2 };
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_256
#ifdef SOC_EFUSE_XTS_AES_KEY_256
esp_efuse_purpose_t purpose1[BLOCKS_NEEDED1] = {
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1,
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2,

2
components/esp_hw_support/include/esp_private/esp_crypto_lock_internal.h
View File

@@ -15,7 +15,7 @@ extern "C" {
// NOTE: [ESP-TEE] Since the clock configuration APIs are part
// of the TEE, the XYZ_RCC_ATOMIC macros need to be defined as void.
#if SOC_RCC_IS_INDEPENDENT || ESP_TEE_BUILD
#if SOC_RCC_IS_INDEPENDENT || NON_OS_BUILD
#define MPI_RCC_ATOMIC()
#define ECC_RCC_ATOMIC()
#define HMAC_RCC_ATOMIC()

10
components/esp_security/CMakeLists.txt
View File

@@ -6,7 +6,7 @@ if(${target} STREQUAL "linux")
endif()
set(srcs "")
set(priv_requires "")
set(priv_requires esp_hw_support hal efuse)
set(priv_includes "")
if(NOT non_os_build)
@@ -30,7 +30,7 @@ if(NOT non_os_build)
endif()
list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
list(APPEND priv_requires efuse esp_system esp_timer)
list(APPEND priv_requires esp_system esp_timer)
elseif(esp_tee_build)
list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
list(APPEND includes "src/${IDF_TARGET}")
@@ -42,6 +42,12 @@ elseif(esp_tee_build)
if(CONFIG_SOC_DIG_SIGN_SUPPORTED)
list(APPEND srcs "src/esp_ds.c")
endif()
else() # BOOTLOADER_BUILD
list(APPEND srcs "src/esp_crypto_lock.c" "src/esp_crypto_periph_clk.c")
if(CONFIG_SOC_KEY_MANAGER_FE_KEY_DEPLOY)
list(APPEND srcs "src/esp_key_mgr.c")
endif()
endif()
idf_component_register(SRCS ${srcs}

21
components/esp_security/include/esp_key_mgr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,6 +25,8 @@ extern "C" {
#define KEY_MGR_HUK_INFO_SIZE HUK_INFO_LEN
#define KEY_MGR_HUK_RISK_ALERT_LEVEL HUK_RISK_ALERT_LEVEL
#define KEY_MGR_KEY_INFO_SIZE KEY_INFO_LEN
/* AES deploy mode */
#define KEY_MGR_K2_INFO_SIZE 64
#define KEY_MGR_K1_ENCRYPTED_SIZE 32
@@ -33,6 +35,7 @@ extern "C" {
typedef struct {
esp_key_mgr_key_type_t key_type;
esp_key_mgr_key_len_t key_len;
bool use_pre_generated_huk_info;
bool use_pre_generated_sw_init_key;
WORD_ALIGNED_ATTR esp_key_mgr_huk_info_t huk_info;
@@ -43,6 +46,7 @@ typedef struct {
typedef struct {
esp_key_mgr_key_type_t key_type;
esp_key_mgr_key_len_t key_len;
bool use_pre_generated_huk_info;
WORD_ALIGNED_ATTR esp_key_mgr_huk_info_t huk_info;
WORD_ALIGNED_ATTR uint8_t k1_G[2][KEY_MGR_ECDH0_INFO_SIZE];
@@ -50,21 +54,30 @@ typedef struct {
typedef struct {
esp_key_mgr_key_type_t key_type;
esp_key_mgr_key_len_t key_len;
bool use_pre_generated_huk_info;
WORD_ALIGNED_ATTR esp_key_mgr_huk_info_t huk_info;
} esp_key_mgr_random_key_config_t;
typedef struct {
esp_key_mgr_key_type_t key_type;
esp_key_mgr_key_len_t key_len;
WORD_ALIGNED_ATTR uint8_t k2_G[2][KEY_MGR_ECDH0_INFO_SIZE];
} esp_key_mgr_ecdh0_info_t;
/**
* @brief Wait for the Key Manager to reach the given state
*
* @param state The state to wait for
*/
void key_mgr_wait_for_state(esp_key_mgr_state_t state);
/**
* @brief Deploy key in AES deployment mode
* @input
* key_config(input) AES key configuration
* key_info(output) A writable struct of esp_key_mgr_key_info_t type.
* The recovery information for the the deployed key shall be stored here
* The recovery information for the the deployed key shall be stored here (Make sure that the memory is valid during the deployment process).
* @return
* ESP_OK for success
* ESP_FAIL/relevant error code for failure
@@ -75,7 +88,7 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t
* @brief Deploy key in ECDH0 deployment mode
* @input
* key_config(input) ECDH0 key configuration
* key_info(output) A writable struct of esp_key_mgr_key_info_t type. The recovery key info for the deployed key shall be stored here
* key_info(output) A writable struct of esp_key_mgr_key_info_t type. The recovery key info for the deployed key shall be stored here (Make sure that the memory is valid during the deployment process).
* ecdh0_key_info A writable struct of esp_key_mgr_ecdh0_info_t. The ecdh0 info to recover the actual key shall be stored here.
* @return
* ESP_OK for success
@@ -87,7 +100,7 @@ esp_err_t esp_key_mgr_deploy_key_in_ecdh0_mode(const esp_key_mgr_ecdh0_key_confi
* @brief Deploy key in Random deployment mode
* @input
* key_config(input) Random key configuration
* key_info(output) A writable struct of esp_key_mgr_key_info_t type. The recovery key info for the deployed key shall be stored here
* key_info(output) A writable struct of esp_key_mgr_key_info_t type. The recovery key info for the deployed key shall be stored here (Make sure that the memory is valid during the deployment process).
* @return
* ESP_OK for success
* ESP_FAIL/relevant error code for failure

6
components/esp_security/src/esp_crypto_periph_clk.c
View File

@@ -7,6 +7,7 @@
#include "soc/soc_caps.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "sdkconfig.h"
#include "esp_crypto_periph_clk.h"
#if SOC_AES_SUPPORTED
#include "hal/aes_ll.h"
@@ -38,6 +39,11 @@
#include "hal/crypto_dma_ll.h"
#endif
#if NON_OS_BUILD
// To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV
int __DECLARE_RCC_ATOMIC_ENV __attribute__((unused));
#endif
#if SOC_AES_SUPPORTED
void esp_crypto_aes_enable_periph_clk(bool enable)
{

609
components/esp_security/src/esp_key_mgr.c
View File

@@ -6,13 +6,11 @@
// The Hardware Support layer for Key manager
#include <assert.h>
#include <string.h>
#include <sys/lock.h>
#include "esp_key_mgr.h"
#include "esp_crypto_periph_clk.h"
#include "esp_crypto_lock.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_heap_caps.h"
#include "esp_rom_crc.h"
#include "esp_efuse.h"
#include "hal/key_mgr_types.h"
@@ -24,26 +22,26 @@
#if SOC_KEY_MANAGER_SUPPORTED
static const char *TAG = "esp_key_mgr";
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_recovery_info_t) == sizeof(struct huk_key_block), "Size of esp_key_mgr_key_recovery_info_t should match huk_key_block (from ROM)");
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_info_t) == sizeof(struct key_info), "Size of esp_key_mgr_key_info_t should match key_info (from ROM)");
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_huk_info_t) == sizeof(struct huk_info), "Size of esp_key_mgr_huk_info_t should match huk_info (from ROM)");
#if !NON_OS_BUILD
#include <sys/lock.h>
static _lock_t s_key_mgr_ecdsa_key_lock;
static _lock_t s_key_mgr_xts_aes_key_lock;
static _lock_t s_key_mgr_hmac_key_lock;
static _lock_t s_key_mgr_ds_key_lock;
static _lock_t s_key_mgr_psram_key_lock;
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_recovery_info_t) == sizeof(struct huk_key_block), "Size of esp_key_mgr_key_recovery_info_t should match huk_key_block (from ROM)");
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_info_t) == sizeof(struct key_info), "Size of esp_key_mgr_key_info_t should match key_info (from ROM)");
ESP_STATIC_ASSERT(sizeof(esp_key_mgr_huk_info_t) == sizeof(struct huk_info), "Size of esp_key_mgr_huk_info_t should match huk_info (from ROM)");
static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
_lock_acquire(&s_key_mgr_ecdsa_key_lock);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
_lock_acquire(&s_key_mgr_xts_aes_key_lock);
break;
case ESP_KEY_MGR_HMAC_KEY:
@@ -52,8 +50,7 @@ static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type)
case ESP_KEY_MGR_DS_KEY:
_lock_acquire(&s_key_mgr_ds_key_lock);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
_lock_acquire(&s_key_mgr_psram_key_lock);
break;
default:
@@ -66,13 +63,10 @@ static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type)
static void esp_key_mgr_release_key_lock(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
_lock_release(&s_key_mgr_ecdsa_key_lock);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
_lock_release(&s_key_mgr_xts_aes_key_lock);
break;
case ESP_KEY_MGR_HMAC_KEY:
@@ -81,8 +75,7 @@ static void esp_key_mgr_release_key_lock(esp_key_mgr_key_type_t key_type)
case ESP_KEY_MGR_DS_KEY:
_lock_release(&s_key_mgr_ds_key_lock);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
_lock_release(&s_key_mgr_psram_key_lock);
break;
default:
@@ -91,6 +84,39 @@ static void esp_key_mgr_release_key_lock(esp_key_mgr_key_type_t key_type)
}
ESP_LOGV(TAG, "Key lock released for key type %d", key_type);
}
#else /* !NON_OS_BUILD */
static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
case ESP_KEY_MGR_HMAC_KEY:
case ESP_KEY_MGR_DS_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
break;
default:
ESP_LOGE(TAG, "Invalid key type");
break;
}
ESP_LOGV(TAG, "Key lock acquired for key type %d", key_type);
}
static void esp_key_mgr_release_key_lock(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
case ESP_KEY_MGR_HMAC_KEY:
case ESP_KEY_MGR_DS_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
break;
default:
ESP_LOGE(TAG, "Invalid key type");
break;
}
ESP_LOGV(TAG, "Key lock released for key type %d", key_type);
}
#endif /* NON_OS_BUILD */
static void esp_key_mgr_acquire_hardware(bool deployment_mode)
{
@@ -107,30 +133,103 @@ static void esp_key_mgr_acquire_hardware(bool deployment_mode)
static void esp_key_mgr_release_hardware(bool deployment_mode)
{
if (deployment_mode) {
esp_crypto_ecc_lock_release();
esp_crypto_sha_aes_lock_release();
esp_crypto_key_manager_lock_release();
esp_crypto_sha_aes_lock_release();
esp_crypto_ecc_lock_release();
}
// Reset the Key Manager Clock
esp_crypto_key_mgr_enable_periph_clk(false);
}
static void key_mgr_wait_for_state(esp_key_mgr_state_t state)
/**
* @brief Check if a key purpose requires a secondary deployment stage
*
* Multi-part keys (256-bit XTS-AES and 384-bit ECDSA) require two deployment stages.
* This function identifies the primary purposes that need a follow-up secondary deployment.
*
* @param purpose Key purpose to check
* @return true if this purpose requires a secondary deployment, false otherwise
*/
static inline bool is_multi_stage_key_purpose(esp_key_mgr_key_purpose_t purpose)
{
return (purpose == ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1 ||
purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1 ||
purpose == ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_H);
}
/**
* @brief Get the secondary key purpose for a given primary purpose
*
* @param primary_purpose The primary key purpose
* @return The corresponding secondary purpose, or ESP_KEY_MGR_KEY_PURPOSE_INVALID if not applicable
*/
static inline esp_key_mgr_key_purpose_t get_secondary_key_purpose(esp_key_mgr_key_purpose_t primary_purpose)
{
switch (primary_purpose) {
case ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1:
return ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2;
case ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1:
return ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2;
case ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_H:
return ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_L;
default:
return ESP_KEY_MGR_KEY_PURPOSE_INVALID;
}
}
static esp_key_mgr_key_purpose_t get_key_purpose(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_KEY:
switch (key_len) {
case ESP_KEY_MGR_ECDSA_LEN_192:
return ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192;
case ESP_KEY_MGR_ECDSA_LEN_256:
return ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256;
case ESP_KEY_MGR_ECDSA_LEN_384:
return ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_H;
default:
return ESP_KEY_MGR_KEY_PURPOSE_INVALID;
}
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
return ESP_KEY_MGR_KEY_PURPOSE_FLASH_128;
case ESP_KEY_MGR_XTS_AES_LEN_256:
return ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1;
default:
return ESP_KEY_MGR_KEY_PURPOSE_INVALID;
}
case ESP_KEY_MGR_HMAC_KEY:
return ESP_KEY_MGR_KEY_PURPOSE_HMAC;
case ESP_KEY_MGR_DS_KEY:
return ESP_KEY_MGR_KEY_PURPOSE_DS;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
return ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128;
case ESP_KEY_MGR_XTS_AES_LEN_256:
return ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1;
default:
return ESP_KEY_MGR_KEY_PURPOSE_INVALID;
}
default:
return ESP_KEY_MGR_KEY_PURPOSE_INVALID;
}
}
void key_mgr_wait_for_state(esp_key_mgr_state_t state)
{
while (key_mgr_hal_get_state() != state) {
;
}
}
typedef struct aes_deploy {
esp_key_mgr_key_purpose_t key_purpose;
const uint8_t *k1_encrypted;
const esp_key_mgr_aes_key_config_t *key_config;
esp_key_mgr_key_recovery_info_t *key_info;
bool huk_deployed;
} aes_deploy_config_t;
static void check_huk_risk_level(void)
{
uint8_t huk_risk_level = huk_hal_get_risk_level();
@@ -139,7 +238,7 @@ static void check_huk_risk_level(void)
"It is recommended to immediately regenerate HUK in order"
"to avoid permanently losing the deployed keys", huk_risk_level);
} else {
ESP_LOGD(TAG, "HUK Risk level - %" PRId8 " within acceptable limit (%" PRIu32 ")", huk_risk_level, (uint32_t)KEY_MGR_HUK_RISK_ALERT_LEVEL);
ESP_LOGD(TAG, "HUK Risk level - %d within acceptable limit (%d)", huk_risk_level, (int) KEY_MGR_HUK_RISK_ALERT_LEVEL);
}
}
@@ -197,99 +296,98 @@ static esp_err_t configure_huk(esp_huk_mode_t huk_mode, uint8_t *huk_info)
static esp_err_t deploy_huk(huk_deploy_config_t *config)
{
esp_err_t esp_ret = ESP_FAIL;
uint8_t *huk_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_HUK_INFO_SIZE, MALLOC_CAP_INTERNAL);
if (!huk_recovery_info) {
return ESP_ERR_NO_MEM;
}
if (config->use_pre_generated_huk_info) {
ESP_LOGD(TAG, "Using pre-generated HUK info");
// If HUK info is provided then recover the HUK from given info
check_huk_risk_level();
if (!check_huk_info_validity(config->pre_generated_huk_info)) {
ESP_LOGE(TAG, "HUK info is not valid");
heap_caps_free(huk_recovery_info);
return ESP_ERR_INVALID_ARG;
}
memcpy(huk_recovery_info, config->pre_generated_huk_info->info, KEY_MGR_HUK_INFO_SIZE);
ESP_LOGD(TAG, "Recovering HUK from given HUK recovery info");
esp_ret = configure_huk(ESP_HUK_MODE_RECOVERY, huk_recovery_info);
esp_ret = configure_huk(ESP_HUK_MODE_RECOVERY, (uint8_t *) config->pre_generated_huk_info->info);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to recover HUK");
heap_caps_free(huk_recovery_info);
return esp_ret;
}
// Copy the pre generated huk info in the output key recovery info
memcpy(config->huk_recovery_info->info, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE);
memcpy(config->huk_recovery_info->info, config->pre_generated_huk_info->info, KEY_MGR_HUK_INFO_SIZE);
config->huk_recovery_info->crc = config->pre_generated_huk_info->crc;
} else {
// Generate new HUK and corresponding HUK info
ESP_LOGD(TAG, "Generating new HUK");
esp_ret = configure_huk(ESP_HUK_MODE_GENERATION, huk_recovery_info);
esp_ret = configure_huk(ESP_HUK_MODE_GENERATION, config->huk_recovery_info->info);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to generate HUK");
heap_caps_free(huk_recovery_info);
memset(config->huk_recovery_info->info, 0, KEY_MGR_HUK_INFO_SIZE);
return esp_ret;
}
memcpy(config->huk_recovery_info->info, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE);
config->huk_recovery_info->crc = esp_rom_crc32_le(0, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE);
config->huk_recovery_info->crc = esp_rom_crc32_le(0, config->huk_recovery_info->info, KEY_MGR_HUK_INFO_SIZE);
}
ESP_LOG_BUFFER_HEX_LEVEL("HUK INFO", huk_recovery_info, KEY_MGR_HUK_INFO_SIZE, ESP_LOG_DEBUG);
// Free the local buffer for huk recovery info
heap_caps_free(huk_recovery_info);
return ESP_OK;
}
typedef struct aes_deploy {
esp_key_mgr_key_purpose_t key_purpose;
const uint8_t *k1_encrypted;
const esp_key_mgr_aes_key_config_t *key_config;
esp_key_mgr_key_recovery_info_t *key_info;
bool huk_deployed;
} aes_deploy_config_t;
static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config)
{
esp_err_t esp_ret = ESP_FAIL;
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) {
// For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
huk_deploy_config_t huk_deploy_config = {};
huk_deploy_config.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info;
huk_deploy_config.pre_generated_huk_info = &config->key_config->huk_info;
huk_deploy_config.huk_recovery_info = &config->key_info->huk_info;
// For purpose ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
huk_deploy_config_t huk_deploy_config = {
.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info,
.pre_generated_huk_info = &config->key_config->huk_info,
.huk_recovery_info = &config->key_info->huk_info,
};
esp_ret = deploy_huk(&huk_deploy_config);
if (esp_ret != ESP_OK) {
return esp_ret;
}
ESP_LOGD(TAG, "HUK deployed successfully");
}
uint8_t key_recovery_info_index = is_multi_stage_key_purpose(config->key_purpose) ? 0 : 1;
uint8_t *key_recovery_info = config->key_info->key_info[key_recovery_info_index].info;
// STEP 1: Init Step
// Set mode
key_mgr_hal_set_key_generator_mode(ESP_KEY_MGR_KEYGEN_MODE_AES);
uint8_t *key_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_KEY_RECOVERY_INFO_SIZE, MALLOC_CAP_INTERNAL);
if (!key_recovery_info) {
return ESP_ERR_NO_MEM;
}
// Set key purpose
ESP_LOGD(TAG, "Key purpose = %d", config->key_purpose);
key_mgr_hal_set_key_purpose(config->key_purpose);
// Set key length for XTS-AES key
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type;
esp_key_mgr_key_type_t key_type = config->key_config->key_type;
esp_key_mgr_key_len_t key_len = config->key_config->key_len;
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256);
} else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512);
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY || key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, key_len);
}
if (config->key_config->use_pre_generated_sw_init_key) {
key_mgr_hal_use_sw_init_key();
} else if (!esp_efuse_find_purpose(ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY, NULL)) {
ESP_LOGE(TAG, "Could not find key with purpose KM_INIT_KEY");
heap_caps_free(key_recovery_info);
return ESP_FAIL;
}
@@ -300,16 +398,12 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config)
if (config->key_config->use_pre_generated_sw_init_key) {
key_mgr_hal_write_sw_init_key(config->key_config->sw_init_key, KEY_MGR_SW_INIT_KEY_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("SW_INIT_KEY", config->key_config->sw_init_key, KEY_MGR_SW_INIT_KEY_SIZE, ESP_LOG_DEBUG);
}
ESP_LOGD(TAG, "Writing Information into Key Manager Registers");
key_mgr_hal_write_assist_info(config->key_config->k2_info, KEY_MGR_K2_INFO_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("K2_INFO", config->key_config->k2_info, KEY_MGR_K2_INFO_SIZE, ESP_LOG_DEBUG);
key_mgr_hal_write_public_info(config->k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("K1_ENCRYPTED", config->k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE, ESP_LOG_DEBUG);
key_mgr_hal_continue();
@@ -317,32 +411,26 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config)
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN);
key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("KEY_RECOVERY_INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG);
if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) {
if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) {
// Check if key deployment validation should be skipped for this purpose
// Primary purposes in multi-stage deployments skip validation after the first stage
// because the key is not yet completely deployed.
if (!is_multi_stage_key_purpose(config->key_purpose)) {
if (!key_mgr_hal_is_key_deployment_valid(key_type, key_len)) {
ESP_LOGE(TAG, "Key deployment is not valid");
heap_caps_free(key_recovery_info);
return ESP_FAIL;
}
ESP_LOGD(TAG, "Key deployment valid");
}
ESP_LOGD(TAG, "Key deployment valid");
// Wait till Key Manager deployment is complete
key_mgr_hal_continue();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) {
memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
} else {
memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
}
heap_caps_free(key_recovery_info);
config->key_info->key_type = config->key_config->key_type;
config->key_info->key_info[key_recovery_info_index].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_type = key_type;
config->key_info->key_len = key_len;
config->key_info->key_deployment_mode = ESP_KEY_MGR_KEYGEN_MODE_AES;
config->key_info->magic = KEY_HUK_SECTOR_MAGIC;
return ESP_OK;
@@ -356,38 +444,14 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t
ESP_LOGD(TAG, "Key deployment in AES mode");
aes_deploy_config_t aes_deploy_config = {};
aes_deploy_config.key_config = key_config;
aes_deploy_config.key_info = key_recovery_info;
aes_deploy_config.k1_encrypted = key_config->k1_encrypted[0];
aes_deploy_config_t aes_deploy_config = {
.key_config = key_config,
.key_info = key_recovery_info,
.k1_encrypted = key_config->k1_encrypted[0],
};
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type;
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192;
break;
case ESP_KEY_MGR_ECDSA_256_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256;
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128;
break;
case ESP_KEY_MGR_XTS_AES_256_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1;
break;
case ESP_KEY_MGR_HMAC_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC;
break;
case ESP_KEY_MGR_DS_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS;
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128;
break;
case ESP_KEY_MGR_PSRAM_256_KEY:
aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1;
break;
default:
aes_deploy_config.key_purpose = get_key_purpose(key_config->key_type, key_config->key_len);
if (aes_deploy_config.key_purpose == ESP_KEY_MGR_KEY_PURPOSE_INVALID) {
ESP_LOGE(TAG, "Invalid key type");
return ESP_ERR_INVALID_ARG;
}
@@ -402,8 +466,8 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t
aes_deploy_config.huk_deployed = true;
if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
aes_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2;
if (is_multi_stage_key_purpose(aes_deploy_config.key_purpose)) {
aes_deploy_config.key_purpose = get_secondary_key_purpose(aes_deploy_config.key_purpose);
aes_deploy_config.k1_encrypted = key_config->k1_encrypted[1];
esp_ret = key_mgr_deploy_key_aes_mode(&aes_deploy_config);
if (esp_ret != ESP_OK) {
@@ -413,7 +477,7 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t
}
// Set the Key Manager Static Register to use own key for the respective key type
key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY);
key_mgr_hal_set_key_usage(key_config->key_type, ESP_KEY_MGR_USE_OWN_KEY);
cleanup:
esp_key_mgr_release_hardware(true);
@@ -429,6 +493,7 @@ typedef struct key_recovery_config {
static esp_err_t key_mgr_recover_key(key_recovery_config_t *config)
{
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if (!check_huk_info_validity(&config->key_recovery_info->huk_info)) {
ESP_LOGE(TAG, "HUK info is not valid");
return ESP_ERR_INVALID_ARG;
@@ -444,18 +509,17 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config)
}
ESP_LOGD(TAG, "HUK recovered successfully");
ESP_LOG_BUFFER_HEX_LEVEL("HUK INFO", config->key_recovery_info->huk_info.info, KEY_MGR_HUK_INFO_SIZE, ESP_LOG_DEBUG);
config->huk_recovered = true;
}
key_mgr_hal_set_key_generator_mode(ESP_KEY_MGR_KEYGEN_MODE_RECOVER);
// Set AES-XTS key len
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_recovery_info->key_type;
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256);
} else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512);
// Set XTS-AES key length
esp_key_mgr_key_type_t key_type = config->key_recovery_info->key_type;
esp_key_mgr_key_len_t key_len = config->key_recovery_info->key_len;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY || key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, key_len);
}
key_mgr_hal_set_key_purpose(config->key_purpose);
@@ -464,32 +528,27 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config)
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD);
if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) {
if (!check_key_info_validity(&config->key_recovery_info->key_info[1])) {
ESP_LOGE(TAG, "Key info not valid");
return ESP_FAIL;
}
key_mgr_hal_write_assist_info(config->key_recovery_info->key_info[1].info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("RECOVERY_INFO[1]", config->key_recovery_info->key_info[0].info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG);
} else {
if (!check_key_info_validity(&config->key_recovery_info->key_info[0])) {
ESP_LOGE(TAG, "Key info not valid");
return ESP_FAIL;
}
key_mgr_hal_write_assist_info(config->key_recovery_info->key_info[0].info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("RECOVERY_INFO[0]", config->key_recovery_info->key_info[0].info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG);
uint8_t key_recovery_info_index = is_multi_stage_key_purpose(config->key_purpose) ? 0 : 1;
if (!check_key_info_validity(&config->key_recovery_info->key_info[key_recovery_info_index])) {
ESP_LOGE(TAG, "Key info not valid");
return ESP_FAIL;
}
key_mgr_hal_write_assist_info(config->key_recovery_info->key_info[key_recovery_info_index].info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
key_mgr_hal_continue();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN);
if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1) {
if (!key_mgr_hal_is_key_deployment_valid(config->key_recovery_info->key_type)) {
// Check if key deployment validation should be skipped for this purpose
// Primary purposes in multi-stage deployments skip validation after the first stage
// because the key is not yet completely deployed.
if (!is_multi_stage_key_purpose(config->key_purpose)) {
if (!key_mgr_hal_is_key_deployment_valid(key_type, key_len)) {
ESP_LOGD(TAG, "Key deployment is not valid");
return ESP_FAIL;
}
ESP_LOGD(TAG, "Key Recovery valid");
}
ESP_LOGD(TAG, "Key Recovery valid");
key_mgr_hal_continue();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
@@ -502,59 +561,33 @@ esp_err_t esp_key_mgr_activate_key(esp_key_mgr_key_recovery_info_t *key_recovery
return ESP_ERR_INVALID_ARG;
}
ESP_LOGD(TAG, "Activating key of type %d", key_recovery_info->key_type);
esp_key_mgr_key_type_t key_type = key_recovery_info->key_type;
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_recovery_info->key_type;
esp_key_mgr_key_purpose_t key_purpose;
ESP_LOGD(TAG, "Activating key of type %d", key_type);
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192;
break;
case ESP_KEY_MGR_ECDSA_256_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256;
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128;
break;
case ESP_KEY_MGR_XTS_AES_256_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1;
break;
case ESP_KEY_MGR_HMAC_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC;
break;
case ESP_KEY_MGR_DS_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS;
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128;
break;
case ESP_KEY_MGR_PSRAM_256_KEY:
key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1;
break;
default:
key_recovery_config_t key_recovery_config = {
.key_recovery_info = key_recovery_info,
};
key_recovery_config.key_purpose = get_key_purpose(key_type, key_recovery_info->key_len);
if (key_recovery_config.key_purpose == ESP_KEY_MGR_KEY_PURPOSE_INVALID) {
ESP_LOGE(TAG, "Invalid key type");
return ESP_ERR_INVALID_ARG;
}
esp_err_t esp_ret = ESP_FAIL;
esp_key_mgr_acquire_key_lock(key_type);
key_recovery_config_t key_recovery_config = {
.key_recovery_info = key_recovery_info,
.key_purpose = key_purpose,
};
esp_key_mgr_acquire_hardware(false);
esp_ret = key_mgr_recover_key(&key_recovery_config);
esp_err_t esp_ret = key_mgr_recover_key(&key_recovery_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to recover key");
esp_key_mgr_release_key_lock(key_type);
goto cleanup;
}
if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
key_recovery_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2;
if (is_multi_stage_key_purpose(key_recovery_config.key_purpose)) {
key_recovery_config.key_purpose = get_secondary_key_purpose(key_recovery_config.key_purpose);
esp_ret = key_mgr_recover_key(&key_recovery_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to recover key");
@@ -565,7 +598,6 @@ esp_err_t esp_key_mgr_activate_key(esp_key_mgr_key_recovery_info_t *key_recovery
// Set the Key Manager Static Register to use own key for the respective key type
key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY);
esp_key_mgr_release_key_lock(key_type);
ESP_LOGD(TAG, "Key activation for type %d successful", key_type);
return ESP_OK;
@@ -599,38 +631,40 @@ static esp_err_t key_mgr_deploy_key_ecdh0_mode(ecdh0_deploy_config_t *config)
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) {
// For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
huk_deploy_config_t huk_deploy_config;
huk_deploy_config.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info;
huk_deploy_config.pre_generated_huk_info = &config->key_config->huk_info;
huk_deploy_config.huk_recovery_info = &config->key_info->huk_info;
// For purpose ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
huk_deploy_config_t huk_deploy_config = {
.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info,
.pre_generated_huk_info = &config->key_config->huk_info,
.huk_recovery_info = &config->key_info->huk_info,
};
esp_ret = deploy_huk(&huk_deploy_config);
if (esp_ret != ESP_OK) {
return esp_ret;
}
ESP_LOGD(TAG, "HUK deployed successfully");
}
uint8_t *key_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_KEY_RECOVERY_INFO_SIZE, MALLOC_CAP_INTERNAL);
if (!key_recovery_info) {
return ESP_ERR_NO_MEM;
}
uint8_t key_recovery_info_index = is_multi_stage_key_purpose(config->key_purpose) ? 0 : 1;
uint8_t *key_recovery_info = config->key_info->key_info[key_recovery_info_index].info;
// Step 1 : Initialization
// Configure deployment mode to ECDH0
key_mgr_hal_set_key_generator_mode(ESP_KEY_MGR_KEYGEN_MODE_ECDH0);
// Set AES-XTS key len
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type;
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256);
} else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512);
}
// Set key purpose
key_mgr_hal_set_key_purpose(config->key_purpose);
// Set XTS-AES key length
esp_key_mgr_key_type_t key_type = config->key_config->key_type;
esp_key_mgr_key_len_t key_len = config->key_config->key_len;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY || key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, key_len);
}
key_mgr_hal_start();
// Step 2: Load phase
@@ -646,35 +680,28 @@ static esp_err_t key_mgr_deploy_key_ecdh0_mode(ecdh0_deploy_config_t *config)
key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
key_mgr_hal_read_assist_info(config->ecdh0_key_info);
ESP_LOG_BUFFER_HEX_LEVEL("KEY_MGR KEY INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG);
ESP_LOGD(TAG, "HUK deployed is valid");
if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) {
if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) {
// Check if key deployment validation should be skipped for this purpose
// Primary purposes in multi-stage deployments skip validation after the first stage
// because the key is not yet completely deployed.
if (!is_multi_stage_key_purpose(config->key_purpose)) {
if (!key_mgr_hal_is_key_deployment_valid(key_type, key_len)) {
ESP_LOGE(TAG, "Key deployment is not valid");
heap_caps_free(key_recovery_info);
return ESP_FAIL;
}
ESP_LOGD(TAG, "Key deployment valid");
}
ESP_LOGD(TAG, "Key deployment valid");
// Wait till Key Manager deployment is complete
key_mgr_hal_continue();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) {
memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
} else {
memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
}
config->key_info->key_type = config->key_config->key_type;
config->key_info->key_info[key_recovery_info_index].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_type = key_type;
config->key_info->key_len = key_len;
config->key_info->key_deployment_mode = ESP_KEY_MGR_KEYGEN_MODE_ECDH0;
config->key_info->magic = KEY_HUK_SECTOR_MAGIC;
heap_caps_free(key_recovery_info);
return ESP_OK;
}
@@ -687,48 +714,15 @@ esp_err_t esp_key_mgr_deploy_key_in_ecdh0_mode(const esp_key_mgr_ecdh0_key_confi
ESP_LOGD(TAG, "Key Deployment in ECDH0 mode");
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type;
ecdh0_deploy_config_t ecdh0_deploy_config = {
.key_config = key_config,
.key_info = key_info,
.k1_G = key_config->k1_G[0],
.ecdh0_key_info = ecdh0_key_info->k2_G[0],
};
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_ECDSA_256_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_XTS_AES_256_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_HMAC_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_DS_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
case ESP_KEY_MGR_PSRAM_256_KEY:
ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1;
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0];
break;
default:
ecdh0_deploy_config.key_purpose = get_key_purpose(key_config->key_type, key_config->key_len);
if (ecdh0_deploy_config.key_purpose == ESP_KEY_MGR_KEY_PURPOSE_INVALID) {
ESP_LOGE(TAG, "Invalid key type");
return ESP_ERR_INVALID_ARG;
}
@@ -737,26 +731,29 @@ esp_err_t esp_key_mgr_deploy_key_in_ecdh0_mode(const esp_key_mgr_ecdh0_key_confi
esp_err_t esp_ret = key_mgr_deploy_key_ecdh0_mode(&ecdh0_deploy_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to deploy key in ECDH0 mode");
ESP_LOGE(TAG, "Key deployment in ECDH0 mode failed");
goto cleanup;
}
ecdh0_deploy_config.huk_deployed = true;
if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
ecdh0_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2;
if (is_multi_stage_key_purpose(ecdh0_deploy_config.key_purpose)) {
ecdh0_deploy_config.key_purpose = get_secondary_key_purpose(ecdh0_deploy_config.key_purpose);
ecdh0_deploy_config.k1_G = key_config->k1_G[1];
ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[1];
esp_ret = key_mgr_deploy_key_ecdh0_mode(&ecdh0_deploy_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Failed to deploy key in ECDH0 mode");
ESP_LOGE(TAG, "Key deployment in ECDH0 mode failed");
goto cleanup;
}
}
// Set the Key Manager Static Register to use own key for the respective key type
key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY);
key_mgr_hal_set_key_usage(key_config->key_type, ESP_KEY_MGR_USE_OWN_KEY);
cleanup:
esp_key_mgr_release_hardware(true);
return ESP_OK;
return esp_ret;
}
typedef struct random_deploy {
@@ -772,7 +769,7 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config)
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) {
// For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
// For purpose ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed
huk_deploy_config_t huk_deploy_config = {
.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info,
.pre_generated_huk_info = &config->key_config->huk_info,
@@ -786,25 +783,24 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config)
ESP_LOGD(TAG, "HUK deployed successfully");
}
uint8_t key_recovery_info_index = is_multi_stage_key_purpose(config->key_purpose) ? 0 : 1;
uint8_t *key_recovery_info = config->key_info->key_info[key_recovery_info_index].info;
// Configure deployment mode to RANDOM
key_mgr_hal_set_key_generator_mode(ESP_KEY_MGR_KEYGEN_MODE_RANDOM);
// Set AES-XTS key len
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type;
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256);
} else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512);
}
uint8_t *key_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_KEY_RECOVERY_INFO_SIZE, MALLOC_CAP_INTERNAL);
if (!key_recovery_info) {
return ESP_ERR_NO_MEM;
}
// Set key purpose (XTS/ECDSA)
// Set key purpose
key_mgr_hal_set_key_purpose(config->key_purpose);
// Set XTS-AES key length
esp_key_mgr_key_type_t key_type = config->key_config->key_type;
esp_key_mgr_key_len_t key_len = config->key_config->key_len;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY || key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_mgr_hal_set_xts_aes_key_len(key_type, key_len);
}
key_mgr_hal_start();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD);
@@ -814,33 +810,28 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config)
// No configuration for Random deploy mode
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN);
key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
ESP_LOG_BUFFER_HEX_LEVEL("KEY_MGR KEY INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG);
if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) {
if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) {
// Check if key deployment validation should be skipped for this purpose
// Primary purposes in multi-stage deployments skip validation after the first stage
// because the key is not yet completely deployed.
if (!is_multi_stage_key_purpose(config->key_purpose)) {
if (!key_mgr_hal_is_key_deployment_valid(key_type, key_len)) {
ESP_LOGE(TAG, "Key deployment is not valid");
heap_caps_free(key_recovery_info);
return ESP_FAIL;
}
ESP_LOGD(TAG, "Key deployment valid");
}
ESP_LOGD(TAG, "Key deployment valid");
// Wait till Key Manager deployment is complete
key_mgr_hal_continue();
key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE);
if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) {
memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
} else {
memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
}
heap_caps_free(key_recovery_info);
config->key_info->key_type = config->key_config->key_type;
config->key_info->key_info[key_recovery_info_index].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE);
config->key_info->key_type = key_type;
config->key_info->key_len = key_len;
config->key_info->key_deployment_mode = ESP_KEY_MGR_KEYGEN_MODE_RANDOM;
config->key_info->magic = KEY_HUK_SECTOR_MAGIC;
return ESP_OK;
}
@@ -857,34 +848,8 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con
.key_info = key_recovery_info,
};
esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type;
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192;
break;
case ESP_KEY_MGR_ECDSA_256_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256;
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128;
break;
case ESP_KEY_MGR_XTS_AES_256_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1;
break;
case ESP_KEY_MGR_HMAC_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC;
break;
case ESP_KEY_MGR_DS_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS;
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128;
break;
case ESP_KEY_MGR_PSRAM_256_KEY:
random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1;
break;
default:
random_deploy_config.key_purpose = get_key_purpose(key_config->key_type, key_config->key_len);
if (random_deploy_config.key_purpose == ESP_KEY_MGR_KEY_PURPOSE_INVALID) {
ESP_LOGE(TAG, "Invalid key type");
return ESP_ERR_INVALID_ARG;
}
@@ -894,25 +859,25 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con
esp_err_t esp_ret = key_mgr_deploy_key_random_mode(&random_deploy_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Key deployment in Random mode failed");
return ESP_FAIL;
goto cleanup;
}
random_deploy_config.huk_deployed = true;
if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
random_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2;
if (is_multi_stage_key_purpose(random_deploy_config.key_purpose)) {
random_deploy_config.key_purpose = get_secondary_key_purpose(random_deploy_config.key_purpose);
esp_ret = key_mgr_deploy_key_random_mode(&random_deploy_config);
if (esp_ret != ESP_OK) {
ESP_LOGE(TAG, "Key deployment in Random mode failed");
return ESP_FAIL;
goto cleanup;
}
}
// Set the Key Manager Static Register to use own key for the respective key type
key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY);
key_mgr_hal_set_key_usage(key_config->key_type, ESP_KEY_MGR_USE_OWN_KEY);
cleanup:
esp_key_mgr_release_hardware(true);
return esp_ret;
}
#endif

2
components/esp_security/src/init.c
View File

@@ -48,7 +48,7 @@ static void esp_key_mgr_init(void)
};
// Force Key Manager to use eFuse key by-default for an XTS-AES operation.
key_mgr_ll_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
key_mgr_ll_set_key_usage(ESP_KEY_MGR_FLASH_XTS_AES_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
}
}
#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */

12
components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c
View File

@@ -147,7 +147,8 @@ TEST_CASE("Key Manager AES mode: XTS-AES-128 key deployment", "[hw_crypto] [key_
memcpy(key_config->k1_encrypted, (uint8_t*) k1_encrypt, KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE);
key_config->use_pre_generated_sw_init_key = 1;
key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
key_config->key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config->key_len = ESP_KEY_MGR_XTS_AES_LEN_128;
esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t));
TEST_ASSERT_NOT_NULL(key_recovery_info);
@@ -167,7 +168,8 @@ TEST_CASE("Key Manager ECDH0 mode: XTS-AES-128 key deployment", "[hw_crypto] [ke
TEST_ASSERT_NOT_NULL(key_config);
memcpy(key_config->k1_G, (uint8_t*) k1_G, KEY_MGR_ECDH0_INFO_SIZE);
key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
key_config->key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config->key_len = ESP_KEY_MGR_XTS_AES_LEN_128;
esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t));
TEST_ASSERT_NOT_NULL(key_recovery_info);
@@ -190,7 +192,8 @@ TEST_CASE("Key Manager Random mode: XTS-AES-128 key deployment", "[hw_crypto] [k
esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t));
TEST_ASSERT_NOT_NULL(key_config);
key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
key_config->key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config->key_len = ESP_KEY_MGR_XTS_AES_LEN_128;
esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t));
TEST_ASSERT_NOT_NULL(key_recovery_info);
@@ -211,7 +214,8 @@ TEST_CASE("Key Manager random mode: ECDSA key deployment", "[hw_crypto] [key_mgr
esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t));
TEST_ASSERT_NOT_NULL(key_config);
key_config->key_type = ESP_KEY_MGR_ECDSA_256_KEY;
key_config->key_type = ESP_KEY_MGR_ECDSA_KEY;
key_config->key_len = ESP_KEY_MGR_ECDSA_LEN_256;
esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t));
TEST_ASSERT_NOT_NULL(key_recovery_info);

1
components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_sec_stg.c
View File

@@ -480,7 +480,6 @@ static void test_ecdsa_sign(mbedtls_ecp_group_id gid)
.grp_id = gid,
.tee_key_id = key_id,
.load_pubkey = true,
.use_tee_sec_stg_key = true,
};
TEST_ASSERT_EQUAL(0, esp_ecdsa_tee_set_pk_context(&key_ctx, &conf));

14
components/hal/ecdsa_hal.c
View File

@@ -49,21 +49,13 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf)
HAL_ASSERT(false && "Key manager is not supported");
}
// Force Key Manager to use eFuse key for XTS-AES operation
if (conf->curve == ECDSA_CURVE_SECP192R1) {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_192_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
} else {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_256_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
}
// Force Key Manager to use eFuse key for ECDSA operation
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
#endif
}
#if SOC_KEY_MANAGER_SUPPORTED
else {
if (conf->curve == ECDSA_CURVE_SECP192R1) {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_192_KEY, ESP_KEY_MGR_USE_OWN_KEY);
} else {
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_256_KEY, ESP_KEY_MGR_USE_OWN_KEY);
}
key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_OWN_KEY);
}
#endif

8
components/hal/esp32c5/include/hal/huk_ll.h
View File

@@ -29,6 +29,14 @@
extern "C" {
#endif
static inline void huk_ll_power_up(void)
{
/* huk force_pd MUST be cleared!!! */
REG_CLR_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PD);
/* huk force_pu MUST be set!!! */
REG_SET_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PU);
}
/* @brief Configure the HUK mode */
static inline void huk_ll_configure_mode(const esp_huk_mode_t huk_mode)
{

144
components/hal/esp32c5/include/hal/key_mgr_ll.h
View File

@@ -20,6 +20,7 @@
#include "soc/keymng_reg.h"
#include "soc/pcr_struct.h"
#include "soc/pcr_reg.h"
#include "hal/efuse_hal.h"
#ifdef __cplusplus
extern "C" {
@@ -162,9 +163,7 @@ static inline void key_mgr_ll_use_sw_init_key(void)
static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
} else {
@@ -172,8 +171,7 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
}
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
} else {
@@ -197,8 +195,7 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
}
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
} else {
@@ -214,30 +211,30 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
break;
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
break;
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
break;
default:
HAL_ASSERT(false && "Unsupported key type");
return ESP_KEY_MGR_USAGE_INVALID;
}
return ESP_KEY_MGR_USAGE_INVALID;
}
/**
@@ -258,14 +255,11 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
{
switch(key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
break;
@@ -277,8 +271,7 @@ static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
break;
@@ -317,32 +310,53 @@ static inline bool key_mgr_ll_is_result_success(void)
* @return 1 for Success
* 0 for failure
*/
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type)
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_384_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
switch (key_len) {
case ESP_KEY_MGR_ECDSA_LEN_192:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_LEN_384:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
break;
case ESP_KEY_MGR_HMAC_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
break;
case ESP_KEY_MGR_DS_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
default:
HAL_ASSERT(false && "Unsupported key type");
HAL_ASSERT(false && "Unsupported mode");
return 0;
}
}
@@ -410,22 +424,54 @@ static inline bool key_mgr_ll_is_huk_valid(void)
}
/* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len)
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len);
} else if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN, key_len);
uint32_t key_len_bit_mask;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
key_len_bit_mask = KEYMNG_FLASH_KEY_LEN;
} else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_len_bit_mask = KEYMNG_PSRAM_KEY_LEN;
} else {
HAL_ASSERT(false && "Unsupported key type");
return;
}
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
break;
case ESP_KEY_MGR_XTS_AES_LEN_256:
REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
break;
default:
HAL_ASSERT(false && "Unsupported key length");
return;
}
}
/* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
static inline esp_key_mgr_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
{
if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
uint32_t key_len_bit = 0;
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
key_len_bit = REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
} else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
key_len_bit = REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
} else {
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
HAL_ASSERT(false && "Unsupported key type");
return (esp_key_mgr_key_len_t) key_len_bit;
}
switch (key_len_bit) {
case 0:
return ESP_KEY_MGR_XTS_AES_LEN_128;
case 1:
return ESP_KEY_MGR_XTS_AES_LEN_256;
default:
HAL_ASSERT(false && "Unsupported key length");
return (esp_key_mgr_key_len_t) key_len_bit;
}
}
@@ -443,6 +489,14 @@ static inline bool key_mgr_ll_is_supported(void)
return true;
}
static inline bool key_mgr_ll_flash_encryption_supported(void)
{
if (!key_mgr_ll_is_supported() || efuse_hal_chip_revision() <= 100) {
return false;
}
return true;
}
#ifdef __cplusplus
}
#endif

7
components/hal/esp32p4/include/hal/huk_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -27,6 +27,11 @@
extern "C" {
#endif
static inline void huk_ll_power_up(void)
{
}
/* @brief Configure the HUK mode */
static inline void huk_ll_configure_mode(const esp_huk_mode_t huk_mode)
{

205
components/hal/esp32p4/include/hal/key_mgr_ll.h
View File

@@ -187,9 +187,7 @@ static inline void key_mgr_ll_use_sw_init_key(void)
static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
} else {
@@ -197,39 +195,38 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
}
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
}
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
}
break;
case ESP_KEY_MGR_DS_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
}
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
}
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
}
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
}
break;
case ESP_KEY_MGR_DS_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
}
break;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
} else {
REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
}
break;
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
@@ -240,35 +237,26 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ
static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
break;
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
break;
case ESP_KEY_MGR_HMAC_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
break;
case ESP_KEY_MGR_DS_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
break;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
return ESP_KEY_MGR_USAGE_INVALID;
}
return ESP_KEY_MGR_USAGE_INVALID;
}
/**
@@ -289,29 +277,26 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
{
switch(key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
case ESP_KEY_MGR_ECDSA_256_KEY:
case ESP_KEY_MGR_ECDSA_384_KEY:
case ESP_KEY_MGR_ECDSA_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
break;
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
break;
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
break;
case ESP_KEY_MGR_HMAC_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
break;
case ESP_KEY_MGR_DS_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
break;
case ESP_KEY_MGR_DS_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
break;
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
break;
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
break;
#endif
default:
HAL_ASSERT(false && "Unsupported key type");
@@ -348,19 +333,33 @@ static inline bool key_mgr_ll_is_result_success(void)
* @return 1 for Success
* 0 for failure
*/
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type)
static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
switch (key_type) {
case ESP_KEY_MGR_ECDSA_192_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_384_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
case ESP_KEY_MGR_ECDSA_KEY:
switch (key_len) {
case ESP_KEY_MGR_ECDSA_LEN_192:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
case ESP_KEY_MGR_ECDSA_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
case ESP_KEY_MGR_ECDSA_LEN_384:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
case ESP_KEY_MGR_XTS_AES_128_KEY:
case ESP_KEY_MGR_XTS_AES_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case ESP_KEY_MGR_HMAC_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
@@ -368,9 +367,16 @@ static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type
case ESP_KEY_MGR_DS_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
case ESP_KEY_MGR_PSRAM_128_KEY:
case ESP_KEY_MGR_PSRAM_256_KEY:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
switch (key_len) {
case ESP_KEY_MGR_XTS_AES_LEN_128:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
case ESP_KEY_MGR_XTS_AES_LEN_256:
return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
default:
HAL_ASSERT(false && "Unsupported key type");
return 0;
}
#endif
default:
HAL_ASSERT(false && "Unsupported mode");
@@ -440,29 +446,32 @@ static inline bool key_mgr_ll_is_huk_valid(void)
return REG_GET_FIELD(KEYMNG_HUK_VLD_REG, KEYMNG_HUK_VALID);
}
/* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len)
static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) {
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len);
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
else if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) {
else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN, key_len);
}
#endif
}
/* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */
static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
static inline esp_key_mgr_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
{
if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) {
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
} else {
if (key_type == ESP_KEY_MGR_FLASH_XTS_AES_KEY) {
return (esp_key_mgr_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN);
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
#else
HAL_ASSERT(false && "Unsupported key type");
else if (key_type == ESP_KEY_MGR_PSRAM_XTS_AES_KEY) {
return (esp_key_mgr_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN);
}
#endif
else {
HAL_ASSERT(false && "Unsupported key type");
return (esp_key_mgr_key_len_t) 0;
}
}
@@ -484,6 +493,14 @@ static inline bool key_mgr_ll_is_supported(void)
#endif
}
static inline bool key_mgr_ll_flash_encryption_supported(void)
{
if (!key_mgr_ll_is_supported()) {
return false;
}
return true;
}
#ifdef __cplusplus
}
#endif

2
components/hal/huk_hal.c
View File

@@ -30,6 +30,8 @@ static void inline huk_hal_wait_for_state(esp_huk_state_t state)
esp_err_t huk_hal_configure(const esp_huk_mode_t huk_mode, uint8_t *huk_info_buf)
{
huk_ll_power_up();
if (esp_rom_km_huk_conf(huk_mode, huk_info_buf) != ETS_OK) {
return ESP_FAIL;
}

6
components/hal/include/hal/key_mgr_hal.h
View File

@@ -57,7 +57,7 @@ bool key_mgr_hal_is_result_success(void);
* @return 1 for Success
* 0 for failure
*/
bool key_mgr_hal_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type);
bool key_mgr_hal_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len);
/**
* @brief Check if the HUK is valid or not
@@ -112,10 +112,10 @@ void key_mgr_hal_write_public_info(const uint8_t *public_info_buf, const size_t
void key_mgr_hal_read_public_info(uint8_t *public_info_buf, const size_t read_len);
/* @brief Set the XTS-AES key length for the Key Manager */
void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len);
void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len);
/* @brief Get the XTS-AES key length for the Key Manager */
esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type);
esp_key_mgr_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type);
/**
* @brief Read state of Key Manager

55
components/hal/include/hal/key_mgr_types.h
View File

@@ -20,41 +20,32 @@ extern "C" {
* @brief State of Key Manager: idle, load, gain or busy.
*/
typedef enum {
ESP_KEY_MGR_STATE_IDLE = 0, /* Key Manager is idle */
ESP_KEY_MGR_STATE_IDLE = 0, /* Key Manager is idle */
ESP_KEY_MGR_STATE_LOAD = 1, /* Key Manager is ready to receive input */
ESP_KEY_MGR_STATE_GAIN = 2, /* Key Manager is ready to provide output */
ESP_KEY_MGR_STATE_BUSY = 3, /* Key Manager is busy */
ESP_KEY_MGR_STATE_BUSY = 3, /* Key Manager is busy */
} esp_key_mgr_state_t;
/**
* @brief Length of the XTS AES key
* @brief Length of the deployed key (XTS-AES, ECDSA)
*/
typedef enum {
ESP_KEY_MGR_XTS_AES_LEN_256 = 0, /* xts-aes key is 256 bit, please note that xts-aes algorithm is XTS_AES_128 */
ESP_KEY_MGR_XTS_AES_LEN_512, /* xts-aes key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */
} esp_key_mgr_xts_aes_key_len_t;
ESP_KEY_MGR_ECDSA_LEN_192 = 0, /* ecdsa key is 192 bit */
ESP_KEY_MGR_ECDSA_LEN_256, /* ecdsa key is 256 bit */
ESP_KEY_MGR_ECDSA_LEN_384, /* ecdsa key is 384 bit */
ESP_KEY_MGR_XTS_AES_LEN_128, /* xts-aes key is 128 bit */
ESP_KEY_MGR_XTS_AES_LEN_256, /* xts-aes key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */
} esp_key_mgr_key_len_t;
/**
* @brief Length of the PSRAM key
* @brief Type of the key
*/
typedef enum {
ESP_KEY_MGR_PSRAM_LEN_256 = 0, /* psram key is 256 bit, please note that xts-aes algorithm is XTS_AES_128 */
ESP_KEY_MGR_PSRAM_LEN_512, /* psram key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */
} esp_key_mgr_psram_key_len_t;
/**
* @brief Type of the key: ECDSA, XTS
*/
typedef enum {
ESP_KEY_MGR_XTS_AES_128_KEY, /* XTS-AES 128-bit key */
ESP_KEY_MGR_XTS_AES_256_KEY, /* XTS-AES 256-bit key */
ESP_KEY_MGR_ECDSA_192_KEY, /* ECDSA 192-bit key */
ESP_KEY_MGR_ECDSA_256_KEY, /* ECDSA 256-bit key */
ESP_KEY_MGR_ECDSA_384_KEY, /* ECDSA 384-bit key */
ESP_KEY_MGR_HMAC_KEY, /* HMAC key */
ESP_KEY_MGR_DS_KEY, /* Digital signature key */
ESP_KEY_MGR_PSRAM_128_KEY, /* PSRAM 128-bit key */
ESP_KEY_MGR_PSRAM_256_KEY, /* PSRAM 256-bit key */
ESP_KEY_MGR_ECDSA_KEY = 0, /* ECDSA key */
ESP_KEY_MGR_FLASH_XTS_AES_KEY, /* XTS-AES key */
ESP_KEY_MGR_HMAC_KEY, /* HMAC key */
ESP_KEY_MGR_DS_KEY, /* Digital signature key */
ESP_KEY_MGR_PSRAM_XTS_AES_KEY, /* PSRAM XTS-AES key */
} esp_key_mgr_key_type_t;
/*
@@ -70,6 +61,7 @@ typedef enum {
* @brief Key Purpose to be set for a particular key in the Key Manager
*/
typedef enum {
ESP_KEY_MGR_KEY_PURPOSE_INVALID = 0,
ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192 = 1, /* ECDSA 192-bit key */
ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256 = 2, /* ECDSA 256-bit key */
ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1 = 3, /* First half of flash 256-bit key */
@@ -109,6 +101,17 @@ typedef enum {
ESP_KEY_MGR_INT_POST_DONE,
} esp_key_mgr_interrupt_type_t;
/**
* @brief Force use key manager key type
* @note This is used to force the key manager to use a specific key type.
*/
typedef enum {
ESP_KEY_MGR_FORCE_USE_KM_ECDSA_KEY = 0,
ESP_KEY_MGR_FORCE_USE_KM_XTS_AES_KEY = 1,
ESP_KEY_MGR_FORCE_USE_KM_HMAC_KEY = 2,
ESP_KEY_MGR_FORCE_USE_KM_DS_KEY = 3,
} esp_key_mgr_force_use_km_key_t;
// store huk info, occupy 96 words
typedef struct PACKED_ATTR {
#define HUK_INFO_LEN 660
@@ -128,7 +131,9 @@ typedef struct WORD_ALIGNED_ATTR PACKED_ATTR {
uint32_t magic;
uint32_t version; // for backward compatibility
uint8_t key_type;
uint8_t reserved[15];
uint8_t key_len;
uint8_t key_deployment_mode;
uint8_t reserved[13];
esp_key_mgr_huk_info_t huk_info;
esp_key_mgr_key_info_t key_info[2]; // at most 2 key info (XTS-512_1 and XTS-512_2), at least use 1
} esp_key_mgr_key_recovery_info_t;

8
components/hal/key_mgr_hal.c
View File

@@ -44,9 +44,9 @@ bool key_mgr_hal_is_result_success(void)
return key_mgr_ll_is_result_success();
}
bool key_mgr_hal_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type)
bool key_mgr_hal_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
return key_mgr_ll_is_key_deployment_valid(key_type);
return key_mgr_ll_is_key_deployment_valid(key_type, key_len);
}
void key_mgr_hal_write_sw_init_key(const uint8_t *sw_init_key_buf, const size_t data_len)
@@ -79,12 +79,12 @@ bool key_mgr_hal_is_huk_valid(void)
return key_mgr_ll_is_huk_valid();
}
void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len)
void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
{
key_mgr_ll_set_xts_aes_key_len(key_type, key_len);
}
esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
esp_key_mgr_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type)
{
return key_mgr_ll_get_xts_aes_key_len(key_type);
}

5
components/hal/test_apps/crypto/main/key_manager/ecdsa_192_key.pem Normal file
View File

@@ -0,0 +1,5 @@
-----BEGIN EC PRIVATE KEY-----
MF8CAQEEGDXkbV5pWiMz+DCRueuWFyVZh/evy5rYyaAKBggqhkjOPQMBAaE0AzIA
BNaaJCemMzzHS5Eo8+3Dk5cHda8oYh1FadIbVLhnJA5EHrDv8QfStCVMSwV4mKoV
4A==
-----END EC PRIVATE KEY-----

6
components/hal/test_apps/crypto/main/key_manager/ecdsa_256_key.pem
View File

@@ -1,5 +1,5 @@
-----BEGIN EC PRIVATE KEY-----
MHcCAQEEICySt/VCEPFi962COuQDE+cXD3Bz8XjZy2O5SM1LsHsGoAoGCCqGSM49
AwEHoUQDQgAEBYu5KXarLURySNNaeZcxtBTxC0vJAM/evz9NC01IjCVQlOLJ4Y6i
3UviK3bgk+3FqpJBM+SQCqeDgd7ktPtr9Q==
MHcCAQEEIDXkbV5pWiMz+DCRueuWFyVZh/evy5rYybp9nCInR4ADoAoGCCqGSM49
AwEHoUQDQgAEtK2sL4kKVX9prPt6DqZBxJ24ZkXHnY2/oQZqnn4E1w4XtSHvIgFT
XdPWQ84RYC7IbrPmL36o0ftKY1xWtgMhFQ==
-----END EC PRIVATE KEY-----

6
components/hal/test_apps/crypto/main/key_manager/ecdsa_384_key.pem Normal file
View File

@@ -0,0 +1,6 @@
-----BEGIN EC PRIVATE KEY-----
MIGkAgEBBDA15G1eaVojM/gwkbnrlhclWYf3r8ua2Mm6fZwiJ0eAA14RGq+Kl7Ap
1rabwaNfV2+gBwYFK4EEACKhZANiAAQSh7nvJpR8mRriSCjrNV2pAobLOigdosYt
u9I7EvTU4DmUthIIuFIoOdjkg8qvK2sucHc7sTdTx2BVwT8BeBCkTwPwqWPc5vnN
GEvVeg/3DrbA4k8MjT5z4C2cn752AM0=
-----END EC PRIVATE KEY-----

139
components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py
View File

@@ -1,6 +1,5 @@
# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Unlicense OR CC0-1.0
import argparse
import hashlib
import hmac
import os
@@ -18,9 +17,6 @@ from cryptography.hazmat.primitives.ciphers import modes
from cryptography.utils import int_to_bytes
from ecdsa.curves import NIST256p
supported_targets = {'esp32p4', 'esp32c5'}
supported_ds_key_size = {'esp32p4': [4096, 3072, 2048, 1024], 'esp32c5': [3072, 2048, 1024]}
# Constants
TEST_COUNT = 5
STORAGE_PARTITION_OFFSET = 0x160000
@@ -100,24 +96,32 @@ def generate_xts_test_data(key: bytes, base_flash_address: int = STORAGE_PARTITI
return xts_test_data
def generate_ecdsa_256_key_and_pub_key(filename: str) -> tuple:
with open(filename, 'rb') as f:
private_number = int.from_bytes(f.read(), byteorder='big')
def generate_ecdsa_key_and_pub_key(key: bytes, key_size: int) -> tuple:
private_number = int.from_bytes(key, byteorder='big')
private_key = ec.derive_private_key(private_number, ec.SECP256R1())
if key_size == 192:
curve = ec.SECP192R1()
elif key_size == 256:
curve = ec.SECP256R1()
elif key_size == 384:
curve = ec.SECP384R1()
else:
raise ValueError(f'Unsupported key size: {key_size}')
private_key = ec.derive_private_key(private_number, curve)
pem = private_key.private_bytes(
encoding=serialization.Encoding.PEM,
format=serialization.PrivateFormat.TraditionalOpenSSL,
encryption_algorithm=serialization.NoEncryption(),
)
with open('ecdsa_256_key.pem', 'wb') as pem_file:
with open(f'ecdsa_{key_size}_key.pem', 'wb') as pem_file:
pem_file.write(pem)
public_key = private_key.public_key()
pub_numbers = public_key.public_numbers()
pubx = pub_numbers.x.to_bytes(32, byteorder='little')
puby = pub_numbers.y.to_bytes(32, byteorder='little')
pubx = pub_numbers.x.to_bytes(key_size // 8, byteorder='little')
puby = pub_numbers.y.to_bytes(key_size // 8, byteorder='little')
return pubx, puby
@@ -128,20 +132,16 @@ def perform_ecc_point_multiplication(k1_int: int) -> Any:
return k1_G
def generate_k1_G(key_file_path: str) -> tuple:
def generate_k1_G(k1_bytes: bytes) -> tuple:
k1_G = []
if os.path.exists(key_file_path):
with open(key_file_path, 'rb') as key_file:
k1_bytes = key_file.read()
k1_int = int.from_bytes(k1_bytes, byteorder='big')
k1_G_point = perform_ecc_point_multiplication(k1_int)
k1_G = k1_G_point.to_bytes()[:64]
k1_int = int.from_bytes(k1_bytes, byteorder='big')
k1_G_point = perform_ecc_point_multiplication(k1_int)
k1_G = k1_G_point.to_bytes()[:64]
k1_G = k1_G[::-1]
k1_G_x = k1_G[:32]
k1_G_y = k1_G[32:]
k1_G = k1_G_y + k1_G_x
k1_G = k1_G[::-1]
k1_G_x = k1_G[:32]
k1_G_y = k1_G[32:]
k1_G = k1_G_y + k1_G_x
return k1_G, k1_G
@@ -238,14 +238,22 @@ def write_to_c_header(
init_key: bytes,
k1: bytes,
k2_info: bytes,
k1_encrypted_24: list,
k1_encrypted_24_reversed: list,
k1_encrypted_32: list,
k1_encrypted_32_reversed: list,
k1_encrypted_48: list,
k1_encrypted_48_reversed: list,
test_data_xts_aes_128: list,
k1_encrypted_64: list,
k1_encrypted_64_reversed: list,
xts_test_data_xts_aes_256: list,
pubx: bytes,
puby: bytes,
ecdsa_p192_pubx: bytes,
ecdsa_p192_puby: bytes,
ecdsa_p256_pubx: bytes,
ecdsa_p256_puby: bytes,
ecdsa_p384_pubx: bytes,
ecdsa_p384_puby: bytes,
k1_G_0: bytes,
k1_G_1: bytes,
hmac_message: bytes,
@@ -271,8 +279,12 @@ typedef struct test_xts_data {{
}} test_xts_data_t;
typedef struct test_ecdsa_data {{
uint8_t pubx[32];
uint8_t puby[32];
uint8_t ecdsa_p192_pubx[24];
uint8_t ecdsa_p192_puby[24];
uint8_t ecdsa_p256_pubx[32];
uint8_t ecdsa_p256_puby[32];
uint8_t ecdsa_p384_pubx[48];
uint8_t ecdsa_p384_puby[48];
}} test_ecdsa_data_t;
typedef struct test_hmac_data {{
@@ -297,7 +309,9 @@ typedef struct test_ds_data {{
typedef struct test_data {{
uint8_t init_key[32];
uint8_t k2_info[64];
uint8_t k1_encrypted[2][32]; // For both 256-bit and 512-bit keys
// [0] for XTS-AES-128 / ECDSA-P192 / HMAC / DS, [1] for XTS-AES-256 / ECDSA-P256
// [2] for ECDSA-P384-H, [3] for ECDSA-P384-L
uint8_t k1_encrypted[4][32];
uint8_t plaintext_data[128];
union {{
test_xts_data_t xts_test_data[TEST_COUNT];
@@ -354,10 +368,19 @@ test_data_aes_mode_t test_data_xts_aes_128 = {{
test_data_aes_mode_t test_data_ecdsa = {{
.init_key = {{ {key_to_c_format(init_key)} }},
.k2_info = {{ {key_to_c_format(k2_info)} }},
.k1_encrypted = {{ {{ {key_to_c_format(k1_encrypted_32_reversed[0])} }}, {{ }} }},
.k1_encrypted = {{
{{ {key_to_c_format(k1_encrypted_24_reversed[0])} }},
{{ {key_to_c_format(k1_encrypted_32_reversed[0])} }},
{{ {key_to_c_format(k1_encrypted_48_reversed[0])} }},
{{ {key_to_c_format(k1_encrypted_48_reversed[1])} }},
}},
.ecdsa_test_data = {{
.pubx = {{ {key_to_c_format(pubx)} }},
.puby = {{ {key_to_c_format(puby)} }}
.ecdsa_p192_pubx = {{ {key_to_c_format(ecdsa_p192_pubx)} }},
.ecdsa_p192_puby = {{ {key_to_c_format(ecdsa_p192_puby)} }},
.ecdsa_p256_pubx = {{ {key_to_c_format(ecdsa_p256_pubx)} }},
.ecdsa_p256_puby = {{ {key_to_c_format(ecdsa_p256_puby)} }},
.ecdsa_p384_pubx = {{ {key_to_c_format(ecdsa_p384_pubx)} }},
.ecdsa_p384_puby = {{ {key_to_c_format(ecdsa_p384_puby)} }},
}}
}};
"""
@@ -413,7 +436,7 @@ test_data_aes_mode_t test_data_ds = {{
file.write(header_content)
def generate_tests_cases(target: str) -> None:
def generate_tests_cases() -> None:
# Main script logic follows as per your provided structure
init_key = key_from_file_or_generate('init_key.bin', 32)
k2 = key_from_file_or_generate('k2.bin', 32)
@@ -423,28 +446,47 @@ def generate_tests_cases(target: str) -> None:
temp_result_outer = calculate_aes_cipher(temp_result_inner + rand_num, init_key)
k2_info = temp_result_outer
k1_32 = key_from_file_or_generate('k1.bin', 32)
k1_64 = key_from_file_or_generate('k1_64.bin', 64)
k1 = key_from_file_or_generate('k1_64.bin', 64)
k1_24 = k1[:24]
k1_32 = k1[:32]
k1_48 = k1[:48]
k1_64 = k1[:]
k1_24_reversed = k1_24[::-1]
k1_32_reversed = k1_32[::-1]
k1_48_1 = k1_48[:16]
k1_48_1_reversed = k1_48_1[::-1]
k1_48_2 = k1_48[16:]
k1_48_2_reversed = k1_48_2[::-1]
k1_64_1 = k1_64[:32]
k1_64_1_reversed = k1_64_1[::-1]
k1_64_2 = k1_64[32:]
k1_64_2_reversed = k1_64_2[::-1]
k1_encrypted_24 = [calculate_aes_cipher(b'\x00' * 8 + k1_24, k2)]
k1_encrypted_32 = [calculate_aes_cipher(k1_32, k2)]
k1_encrypted_48 = [calculate_aes_cipher(b'\x00' * 16 + k1_48_1, k2), calculate_aes_cipher(k1_48_2, k2)]
k1_encrypted_64 = [calculate_aes_cipher(k1_64_1, k2), calculate_aes_cipher(k1_64_2, k2)]
k1_encrypted_24_reversed = [calculate_aes_cipher(k1_24_reversed + b'\x00' * 8, k2)]
k1_encrypted_32_reversed = [calculate_aes_cipher(k1_32_reversed, k2)]
k1_encrypted_48_reversed = [
calculate_aes_cipher(k1_48_1_reversed + b'\x00' * 16, k2),
calculate_aes_cipher(k1_48_2_reversed, k2),
]
k1_encrypted_64_reversed = [calculate_aes_cipher(k1_64_1_reversed, k2), calculate_aes_cipher(k1_64_2_reversed, k2)]
test_data_xts_aes_128 = generate_xts_test_data(k1_32)
xts_test_data_xts_aes_256 = generate_xts_test_data(k1_64)
pubx, puby = generate_ecdsa_256_key_and_pub_key('k1.bin')
ecdsa_p192_pubx, ecdsa_p192_puby = generate_ecdsa_key_and_pub_key(k1_24, 192)
ecdsa_p256_pubx, ecdsa_p256_puby = generate_ecdsa_key_and_pub_key(k1_32, 256)
ecdsa_p384_pubx, ecdsa_p384_puby = generate_ecdsa_key_and_pub_key(k1_48, 384)
k1_G_0, k1_G_1 = generate_k1_G('k1.bin')
k1_G_0, k1_G_1 = generate_k1_G(k1_32)
hmac_message, hmac_result = generate_hmac_test_data(k1_32)
@@ -462,14 +504,22 @@ def generate_tests_cases(target: str) -> None:
init_key,
k1_32,
k2_info,
k1_encrypted_24,
k1_encrypted_24_reversed,
k1_encrypted_32,
k1_encrypted_32_reversed,
k1_encrypted_48,
k1_encrypted_48_reversed,
test_data_xts_aes_128,
k1_encrypted_64,
k1_encrypted_64_reversed,
xts_test_data_xts_aes_256,
pubx,
puby,
ecdsa_p192_pubx,
ecdsa_p192_puby,
ecdsa_p256_pubx,
ecdsa_p256_puby,
ecdsa_p384_pubx,
ecdsa_p384_puby,
k1_G_0,
k1_G_1,
hmac_message,
@@ -485,15 +535,4 @@ def generate_tests_cases(target: str) -> None:
if __name__ == '__main__':
parser = argparse.ArgumentParser(description="""Generates Digital Signature Test Cases""")
parser.add_argument(
'--target',
required=True,
choices=supported_targets,
help='Target to generate test cases for, different targets support different max key length',
)
args = parser.parse_args()
generate_tests_cases(args.target)
generate_tests_cases()

67
components/hal/test_apps/crypto/main/key_manager/key_manager_test_cases.h
View File

File diff suppressed because one or more lines are too long

326
components/hal/test_apps/crypto/main/key_manager/test_key_manager.c
View File

@@ -84,80 +84,88 @@ static void test_xts_aes_key_ecdh0_mode(test_data_ecdh0_mode_t *test_data)
ESP_LOG_BUFFER_HEXDUMP("Encrypted data", read_data, data_size, ESP_LOG_DEBUG);
}
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128
static void key_mgr_test_xts_aes_128_aes_mode(void)
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
static void key_mgr_test_xts_aes_key_aes_mode(esp_key_mgr_key_len_t key_len, test_data_aes_mode_t *test_data)
{
static esp_key_mgr_aes_key_config_t key_config;
memcpy(key_config.k2_info, (uint8_t*) test_data_xts_aes_128.k2_info, KEY_MGR_K2_INFO_SIZE);
memcpy(key_config.k1_encrypted, (uint8_t*) test_data_xts_aes_128.k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config.sw_init_key, (uint8_t*) test_data_xts_aes_128.init_key, KEY_MGR_SW_INIT_KEY_SIZE);
key_config.use_pre_generated_sw_init_key = 1;
key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info));
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
test_xts_aes_key_aes_mode(&test_data_xts_aes_128);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
static void key_mgr_test_xts_aes_128_ecdh0_mode(void)
{
static esp_key_mgr_ecdh0_key_config_t key_config;
memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE);
key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
static esp_key_mgr_ecdh0_info_t ecdh0_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info));
ESP_LOG_BUFFER_HEXDUMP("K2_G", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
test_xts_aes_key_ecdh0_mode(&test_data_ecdh0);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 */
memcpy(key_config.k2_info, (uint8_t*) test_data->k2_info, KEY_MGR_K2_INFO_SIZE);
memcpy(key_config.k1_encrypted[0], (uint8_t*) test_data->k1_encrypted[0], KEY_MGR_K1_ENCRYPTED_SIZE);
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
static void key_mgr_test_xts_aes_256_aes_mode(void)
{
static esp_key_mgr_aes_key_config_t key_config;
memcpy(key_config.k2_info, (uint8_t*) test_data_xts_aes_256.k2_info, KEY_MGR_K2_INFO_SIZE);
memcpy(key_config.k1_encrypted[0], (uint8_t*) test_data_xts_aes_256.k1_encrypted[0], KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config.k1_encrypted[1], (uint8_t*) test_data_xts_aes_256.k1_encrypted[1], KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config.sw_init_key, (uint8_t*) test_data_xts_aes_256.init_key, KEY_MGR_SW_INIT_KEY_SIZE);
if (key_len == ESP_KEY_MGR_XTS_AES_LEN_256) {
memcpy(key_config.k1_encrypted[1], (uint8_t*) test_data->k1_encrypted[1], KEY_MGR_K1_ENCRYPTED_SIZE);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
memcpy(key_config.sw_init_key, (uint8_t*) test_data->init_key, KEY_MGR_SW_INIT_KEY_SIZE);
key_config.use_pre_generated_sw_init_key = 1;
key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY;
key_config.key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info));
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
test_xts_aes_key_aes_mode(&test_data_xts_aes_256);
test_xts_aes_key_aes_mode(test_data);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
static void key_mgr_test_xts_aes_256_ecdh0_mode(void)
static void key_mgr_test_xts_aes_key_ecdh0_mode(esp_key_mgr_key_len_t key_len)
{
static esp_key_mgr_ecdh0_key_config_t key_config;
memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE);
memcpy(key_config.k1_G[1], (uint8_t*) test_data_ecdh0.k1_G[1], KEY_MGR_ECDH0_INFO_SIZE);
key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY;
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
if (key_len == ESP_KEY_MGR_XTS_AES_LEN_256) {
memcpy(key_config.k1_G[1], (uint8_t*) test_data_ecdh0.k1_G[1], KEY_MGR_ECDH0_INFO_SIZE);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
key_config.key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
static esp_key_mgr_ecdh0_info_t ecdh0_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info));
ESP_LOG_BUFFER_HEXDUMP("K2_G_0", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEXDUMP("K2_G_1", ecdh0_info.k2_G[1], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
if (key_len == ESP_KEY_MGR_XTS_AES_LEN_256) {
ESP_LOG_BUFFER_HEXDUMP("K2_G_1", ecdh0_info.k2_G[1], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
test_xts_aes_key_ecdh0_mode(&test_data_ecdh0);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128
static void key_mgr_test_xts_aes_128_aes_mode(void)
{
key_mgr_test_xts_aes_key_aes_mode(ESP_KEY_MGR_XTS_AES_LEN_128, &test_data_xts_aes_128);
}
static void key_mgr_test_xts_aes_128_ecdh0_mode(void)
{
key_mgr_test_xts_aes_key_ecdh0_mode(ESP_KEY_MGR_XTS_AES_LEN_128);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 */
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
static void key_mgr_test_xts_aes_256_aes_mode(void)
{
key_mgr_test_xts_aes_key_aes_mode(ESP_KEY_MGR_XTS_AES_LEN_256, &test_data_xts_aes_256);
}
static void key_mgr_test_xts_aes_256_ecdh0_mode(void)
{
key_mgr_test_xts_aes_key_ecdh0_mode(ESP_KEY_MGR_XTS_AES_LEN_256);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
static void test_xts_aes_key_random_mode(void)
{
const esp_partition_t *partition = get_test_storage_partition();
@@ -173,11 +181,11 @@ static void test_xts_aes_key_random_mode(void)
}
}
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128
static void key_mgr_test_xts_aes_128_random_mode(void)
static void key_mgr_test_xts_aes_key_random_mode(esp_key_mgr_key_len_t key_len)
{
static esp_key_mgr_random_key_config_t key_config;
key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY;
key_config.key_type = ESP_KEY_MGR_FLASH_XTS_AES_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info));
@@ -185,19 +193,19 @@ static void key_mgr_test_xts_aes_128_random_mode(void)
test_xts_aes_key_random_mode();
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128
static void key_mgr_test_xts_aes_128_random_mode(void)
{
key_mgr_test_xts_aes_key_random_mode(ESP_KEY_MGR_XTS_AES_LEN_128);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 */
#if SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256
static void key_mgr_test_xts_aes_256_random_mode(void)
{
static esp_key_mgr_random_key_config_t key_config;
key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info));
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
test_xts_aes_key_random_mode();
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
key_mgr_test_xts_aes_key_random_mode(ESP_KEY_MGR_XTS_AES_LEN_256);
}
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 */
#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */
@@ -205,103 +213,182 @@ static void key_mgr_test_xts_aes_256_random_mode(void)
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
#if SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
extern void test_ecdsa_export_pubkey(bool is_p256, uint8_t *ecdsa_pub_x, uint8_t *ecdsa_pub_y, bool use_km_key);
extern void test_ecdsa_export_pubkey_inner(bool is_p256, uint8_t *exported_pub_x, uint8_t *exported_pub_y, bool use_km_key, uint16_t *len);
extern void test_ecdsa_export_pubkey(ecdsa_curve_t curve, uint8_t *ecdsa_pub_x, uint8_t *ecdsa_pub_y, bool use_km_key);
extern void test_ecdsa_export_pubkey_inner(ecdsa_curve_t curve, uint8_t *exported_pub_x, uint8_t *exported_pub_y, bool use_km_key, uint16_t *len);
#endif
extern void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, bool use_km_key, ecdsa_sign_type_t k_type);
extern int test_ecdsa_verify(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, uint8_t *pub_x, uint8_t *pub_y);
extern void test_ecdsa_sign_and_verify(bool is_p256, uint8_t* sha, uint8_t* pub_x, uint8_t* pub_y, bool use_km_key, ecdsa_sign_type_t k_type);
extern void test_ecdsa_sign(ecdsa_curve_t curve, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, bool use_km_key, ecdsa_sign_type_t k_type);
extern int test_ecdsa_verify(ecdsa_curve_t curve, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, uint8_t *pub_x, uint8_t *pub_y);
extern void test_ecdsa_sign_and_verify(ecdsa_curve_t curve, uint8_t* sha, uint8_t* pub_x, uint8_t* pub_y, bool use_km_key, ecdsa_sign_type_t k_type);
/*
const uint8_t message[32] = { 0xDF, 0xDE, 0xD7, 0x4A, 0x47, 0xB1, 0x4F, 0x73, 0x00, 0x21, 0x62, 0xC7, 0x66, 0x6D, 0xA3, 0x95, 0x66, 0x19, 0x62, 0x7F, 0x71, 0x7B, 0x3C, 0x66, 0x82, 0xD3, 0x9F, 0x71, 0xAC, 0x9C, 0xC3, 0x39 };
*/
/* sha384 digest of the above message */
uint8_t sha_digest[48] = { 0xF0, 0x94, 0xC4, 0x4A, 0xF0, 0xEE, 0x68, 0xDB, 0x5B, 0x6A, 0x12, 0x84, 0xAC, 0xAF, 0x49, 0x0C, 0x24, 0xED, 0x70, 0x41, 0xE6, 0xE3, 0xBD, 0x74, 0x2B, 0x8D, 0xCF, 0x46, 0x19, 0xE1, 0xC2, 0x61, 0xCA, 0x79, 0xF3, 0x86, 0xF9, 0x04, 0xC0, 0x63, 0xC6, 0xF0, 0xEE, 0x36, 0x7C, 0x5C, 0x82, 0x89 };
/* sha256 digest of the above message */
uint8_t sha256_digest[32] = { 0x47, 0xA6, 0xEF, 0xBE, 0x39, 0x5E, 0xE4, 0xAE, 0x2B, 0xEC, 0x83, 0xB1, 0xED, 0xAF, 0xC6, 0x78, 0x57, 0x7A, 0x16, 0x8C, 0x22, 0x16, 0x13, 0xE2, 0xAC, 0xA8, 0x50, 0xD5, 0x67, 0x95, 0x9F, 0x71 };
void test_ecdsa_key_aes_mode(test_data_aes_mode_t *ecdsa_test_data, ecdsa_sign_type_t k_type)
void test_ecdsa_key_aes_mode(ecdsa_curve_t curve, uint8_t *sha_digest, uint8_t *pub_x, uint8_t *pub_y, ecdsa_sign_type_t k_type)
{
test_ecdsa_sign_and_verify(1, sha256_digest, ecdsa_test_data->ecdsa_test_data.pubx, ecdsa_test_data->ecdsa_test_data.puby, 1, k_type);
test_ecdsa_sign_and_verify(curve, sha_digest, pub_x, pub_y, 1, k_type);
#ifdef SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
test_ecdsa_export_pubkey(1, ecdsa_test_data->ecdsa_test_data.pubx, ecdsa_test_data->ecdsa_test_data.puby, 1);
test_ecdsa_export_pubkey(curve, pub_x, pub_y, 1);
#endif
}
void key_mgr_test_ecdsa_key(bool is_p256, ecdsa_sign_type_t k_type)
void key_mgr_test_ecdsa_key(esp_key_mgr_key_len_t key_len, ecdsa_sign_type_t k_type)
{
uint8_t pub_x[32] = {};
uint8_t pub_y[32] = {};
uint8_t r_le[32] = {0};
uint8_t s_le[32] = {0};
uint8_t pub_x[48] = {};
uint8_t pub_y[48] = {};
uint8_t r_le[48] = {0};
uint8_t s_le[48] = {0};
test_ecdsa_sign(is_p256, sha256_digest, r_le, s_le, 1, k_type);
uint16_t sha_digest_len = 0;
ESP_LOG_BUFFER_HEXDUMP("ECDSA message sha256 digest", sha256_digest, sizeof(sha256_digest), ESP_LOG_DEBUG);
ecdsa_curve_t curve = ECDSA_CURVE_SECP192R1;
switch (key_len) {
case ESP_KEY_MGR_ECDSA_LEN_192:
sha_digest_len = 24;
curve = ECDSA_CURVE_SECP192R1;
break;
case ESP_KEY_MGR_ECDSA_LEN_256:
sha_digest_len = 32;
curve = ECDSA_CURVE_SECP256R1;
break;
#if SOC_ECDSA_SUPPORT_CURVE_P384
case ESP_KEY_MGR_ECDSA_LEN_384:
sha_digest_len = 48;
curve = ECDSA_CURVE_SECP384R1;
break;
#endif
default:
TEST_FAIL_MESSAGE("Unsupported key length");
return;
}
test_ecdsa_sign(curve, sha_digest, r_le, s_le, 1, k_type);
ESP_LOG_BUFFER_HEXDUMP("ECDSA message digest", sha_digest, sha_digest_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEXDUMP("ECDSA signature r_le", r_le, sizeof(r_le), ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEXDUMP("ECDSA signature s_le", s_le, sizeof(s_le), ESP_LOG_DEBUG);
// Export the pubkey from ECDSA peripheral
uint16_t pubkey_len = 0;
test_ecdsa_export_pubkey_inner(is_p256, pub_x, pub_y, 1, &pubkey_len);
test_ecdsa_export_pubkey_inner(curve, pub_x, pub_y, 1, &pubkey_len);
ESP_LOG_BUFFER_HEXDUMP("ECDSA key pubx", pub_x, pubkey_len, ESP_LOG_DEBUG);
ESP_LOG_BUFFER_HEXDUMP("ECDSA key puby", pub_y, pubkey_len, ESP_LOG_DEBUG);
TEST_ASSERT_EQUAL(0, test_ecdsa_verify(is_p256, sha256_digest, r_le, s_le, pub_x, pub_y));
TEST_ASSERT_EQUAL(0, test_ecdsa_verify(curve, sha_digest, r_le, s_le, pub_x, pub_y));
}
static void key_mgr_test_ecdsa_p256_aes_mode(void)
/* Generic ECDSA AES mode test function */
static void key_mgr_test_ecdsa_key_aes_mode(esp_key_mgr_key_len_t key_len, test_data_aes_mode_t *test_data)
{
static esp_key_mgr_aes_key_config_t key_config;
memcpy(key_config.k2_info, (uint8_t*) test_data_ecdsa.k2_info, KEY_MGR_K2_INFO_SIZE);
memcpy(key_config.k1_encrypted, (uint8_t*) test_data_ecdsa.k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config.sw_init_key, (uint8_t*) test_data_ecdsa.init_key, KEY_MGR_SW_INIT_KEY_SIZE);
ecdsa_curve_t curve = ECDSA_CURVE_SECP192R1;
uint8_t *pub_x = NULL;
uint8_t *pub_y = NULL;
memcpy(key_config.k2_info, (uint8_t*) test_data->k2_info, KEY_MGR_K2_INFO_SIZE);
if (key_len == ESP_KEY_MGR_ECDSA_LEN_192) {
memcpy(key_config.k1_encrypted[0], (uint8_t*) test_data->k1_encrypted[0], KEY_MGR_K1_ENCRYPTED_SIZE);
pub_x = test_data->ecdsa_test_data.ecdsa_p192_pubx;
pub_y = test_data->ecdsa_test_data.ecdsa_p192_puby;
curve = ECDSA_CURVE_SECP192R1;
}
else if (key_len == ESP_KEY_MGR_ECDSA_LEN_256) {
memcpy(key_config.k1_encrypted[0], (uint8_t*) test_data->k1_encrypted[1], KEY_MGR_K1_ENCRYPTED_SIZE);
pub_x = test_data->ecdsa_test_data.ecdsa_p256_pubx;
pub_y = test_data->ecdsa_test_data.ecdsa_p256_puby;
curve = ECDSA_CURVE_SECP256R1;
}
#if SOC_ECDSA_SUPPORT_CURVE_P384
else if (key_len == ESP_KEY_MGR_ECDSA_LEN_384) {
memcpy(key_config.k1_encrypted[0], (uint8_t*) test_data->k1_encrypted[2], KEY_MGR_K1_ENCRYPTED_SIZE);
memcpy(key_config.k1_encrypted[1], (uint8_t*) test_data->k1_encrypted[3], KEY_MGR_K1_ENCRYPTED_SIZE);
pub_x = test_data->ecdsa_test_data.ecdsa_p384_pubx;
pub_y = test_data->ecdsa_test_data.ecdsa_p384_puby;
curve = ECDSA_CURVE_SECP384R1;
}
#endif
memcpy(key_config.sw_init_key, (uint8_t*) test_data->init_key, KEY_MGR_SW_INIT_KEY_SIZE);
key_config.use_pre_generated_sw_init_key = 1;
key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY;
key_config.key_type = ESP_KEY_MGR_ECDSA_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info));
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
test_ecdsa_key_aes_mode(&test_data_ecdsa, ECDSA_K_TYPE_DETERMINISITIC);
#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
test_ecdsa_key_aes_mode(curve, sha_digest, pub_x, pub_y, ECDSA_K_TYPE_DETERMINISITIC);
#endif
test_ecdsa_key_aes_mode(&test_data_ecdsa, ECDSA_K_TYPE_TRNG);
test_ecdsa_key_aes_mode(curve, sha_digest, pub_x, pub_y, ECDSA_K_TYPE_TRNG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
static void key_mgr_test_ecdsa_ecdh0_mode(void)
/* Generic ECDSA ECDH0 mode test function */
static void key_mgr_test_ecdsa_key_ecdh0_mode(esp_key_mgr_key_len_t key_len)
{
static esp_key_mgr_ecdh0_key_config_t key_config;
memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE);
key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY;
#if SOC_ECDSA_SUPPORT_CURVE_P384
// For 384-bit keys, copy the second k1_G block
if (key_len == ESP_KEY_MGR_ECDSA_LEN_384) {
memcpy(key_config.k1_G[1], (uint8_t*) test_data_ecdh0.k1_G[1], KEY_MGR_ECDH0_INFO_SIZE);
}
#endif
key_config.key_type = ESP_KEY_MGR_ECDSA_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
static esp_key_mgr_ecdh0_info_t ecdh0_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info));
ESP_LOG_BUFFER_HEXDUMP("K2_G", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_DETERMINISITIC);
ESP_LOG_BUFFER_HEXDUMP("K2_G_0", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
#if SOC_ECDSA_SUPPORT_CURVE_P384
if (key_len == ESP_KEY_MGR_ECDSA_LEN_384) {
ESP_LOG_BUFFER_HEXDUMP("K2_G_1", ecdh0_info.k2_G[1], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG);
}
#endif
key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_TRNG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
#if SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
key_mgr_test_ecdsa_key(key_len, ECDSA_K_TYPE_DETERMINISITIC);
#endif
key_mgr_test_ecdsa_key(key_len, ECDSA_K_TYPE_TRNG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
static void key_mgr_test_ecdsa_random_mode(void)
/* Generic ECDSA random mode test function */
static void key_mgr_test_ecdsa_key_random_mode(esp_key_mgr_key_len_t key_len)
{
static esp_key_mgr_random_key_config_t key_config;
key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY;
key_config.key_type = ESP_KEY_MGR_ECDSA_KEY;
key_config.key_len = key_len;
static esp_key_mgr_key_recovery_info_t key_recovery_info;
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info));
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info));
if (key_len == ESP_KEY_MGR_ECDSA_LEN_256) {
#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_DETERMINISITIC);
key_mgr_test_ecdsa_key(ECDSA_CURVE_SECP256R1, ECDSA_K_TYPE_DETERMINISITIC);
#endif
key_mgr_test_ecdsa_key(ECDSA_CURVE_SECP256R1, ECDSA_K_TYPE_TRNG);
}
#if SOC_ECDSA_SUPPORT_CURVE_P384
else if (key_len == ESP_KEY_MGR_ECDSA_LEN_384) {
#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
key_mgr_test_ecdsa_key(ECDSA_CURVE_SECP384R1, ECDSA_K_TYPE_DETERMINISITIC);
#endif
key_mgr_test_ecdsa_key(ECDSA_CURVE_SECP384R1, ECDSA_K_TYPE_TRNG);
}
#endif
key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_TRNG);
TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type));
}
#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */
@@ -330,7 +417,6 @@ static void key_mgr_test_hmac_key_aes_random_mode(const uint8_t *message, size_t
// We cannot verify the result here as the HMAC key deployed is unknown.
}
static void key_mgr_test_hmac_aes_mode(void)
{
static esp_key_mgr_aes_key_config_t key_config;
@@ -476,20 +562,52 @@ TEST(key_manager, xts_key_256_random_deployment)
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
TEST(key_manager, ecdsa_p192_key_aes_deployment)
{
key_mgr_test_ecdsa_key_aes_mode(ESP_KEY_MGR_ECDSA_LEN_192, &test_data_ecdsa);
}
TEST(key_manager, ecdsa_p192_key_ecdh0_deployment)
{
key_mgr_test_ecdsa_key_ecdh0_mode(ESP_KEY_MGR_ECDSA_LEN_192);
}
TEST(key_manager, ecdsa_p192_key_random_deployment)
{
key_mgr_test_ecdsa_key_random_mode(ESP_KEY_MGR_ECDSA_LEN_192);
}
TEST(key_manager, ecdsa_p256_key_aes_deployment)
{
key_mgr_test_ecdsa_p256_aes_mode();
key_mgr_test_ecdsa_key_aes_mode(ESP_KEY_MGR_ECDSA_LEN_256, &test_data_ecdsa);
}
TEST(key_manager, ecdsa_p256_key_ecdh0_deployment)
{
key_mgr_test_ecdsa_ecdh0_mode();
key_mgr_test_ecdsa_key_ecdh0_mode(ESP_KEY_MGR_ECDSA_LEN_256);
}
TEST(key_manager, ecdsa_p256_key_random_deployment)
{
key_mgr_test_ecdsa_random_mode();
key_mgr_test_ecdsa_key_random_mode(ESP_KEY_MGR_ECDSA_LEN_256);
}
#if SOC_ECDSA_SUPPORT_CURVE_P384
TEST(key_manager, ecdsa_p384_key_aes_deployment)
{
key_mgr_test_ecdsa_key_aes_mode(ESP_KEY_MGR_ECDSA_LEN_384, &test_data_ecdsa);
}
TEST(key_manager, ecdsa_p384_key_ecdh0_deployment)
{
key_mgr_test_ecdsa_key_ecdh0_mode(ESP_KEY_MGR_ECDSA_LEN_384);
}
TEST(key_manager, ecdsa_p384_key_random_deployment)
{
key_mgr_test_ecdsa_key_random_mode(ESP_KEY_MGR_ECDSA_LEN_384);
}
#endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */
#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY
@@ -538,9 +656,19 @@ TEST_GROUP_RUNNER(key_manager)
#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */
#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY
RUN_TEST_CASE(key_manager, ecdsa_p192_key_aes_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p192_key_ecdh0_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p192_key_random_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p256_key_aes_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p256_key_ecdh0_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p256_key_random_deployment);
#if SOC_ECDSA_SUPPORT_CURVE_P384
RUN_TEST_CASE(key_manager, ecdsa_p384_key_aes_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p384_key_ecdh0_deployment);
RUN_TEST_CASE(key_manager, ecdsa_p384_key_random_deployment);
#endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */
#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */
#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY

4
components/hal/test_apps/crypto/sdkconfig.defaults
View File

@@ -1,3 +1,7 @@
CONFIG_COMPILER_STACK_CHECK=y
CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
CONFIG_ESP_TASK_WDT_EN=y
CONFIG_ESP_TASK_WDT_INIT=n
CONFIG_UNITY_ENABLE_FIXTURE=y

2
components/mbedtls/port/ecdsa/ecdsa_alt.c
View File

@@ -595,7 +595,7 @@ int esp_ecdsa_tee_set_pk_context(mbedtls_pk_context *key_ctx, esp_ecdsa_pk_conf_
return ret;
}
if (!conf->use_tee_sec_stg_key) {
if (!conf->tee_key_id) {
ESP_LOGE(TAG, "Invalid esp_ecdsa_pk_conf_t configuration");
return ret;
}

14
components/mbedtls/port/include/ecdsa/ecdsa_alt.h
View File

@@ -30,19 +30,15 @@ typedef struct {
mbedtls_ecp_group_id grp_id; /*!< MbedTLS ECP group identifier */
union {
uint8_t efuse_block; /*!< EFuse block id for ECDSA private key */
#if CONFIG_MBEDTLS_TEE_SEC_STG_ECDSA_SIGN
const char *tee_key_id; /*!< TEE secure storage key id for ECDSA private key */
}; /*!< Union to hold either EFuse block id or TEE secure storage key id for ECDSA private key */
#endif
bool use_km_key; /*!< Use key deployed in the key manager for ECDSA operation. Note: The key must be already deployed by the application and it must be activated for the lifetime of this context */
}; /*!< Union to hold either EFuse block id or TEE secure storage key id or use key deployed in the key manager for ECDSA operation for ECDSA private key */
#if SOC_ECDSA_SUPPORT_EXPORT_PUBKEY || CONFIG_MBEDTLS_TEE_SEC_STG_ECDSA_SIGN
bool load_pubkey; /*!< Export ECDSA public key from the hardware */
#endif
bool use_km_key; /*!< Use key deployed in the key manager for ECDSA operation.
Note: The key must be already deployed by the application and it must be activated for the lifetime of this context */
#if CONFIG_MBEDTLS_TEE_SEC_STG_ECDSA_SIGN
bool use_tee_sec_stg_key; /*!< Use key deployed in the TEE secure storage for ECDSA operation.
Note: The key must be already deployed by the application and it must be activated for the lifetime of this context */
#endif
} esp_ecdsa_pk_conf_t; //TODO: IDF-9008 (Add a config to select the ecdsa key from the key manager peripheral)
} esp_ecdsa_pk_conf_t;
#if SOC_ECDSA_SUPPORT_EXPORT_PUBKEY || __DOXYGEN__

27
components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c
View File

@@ -359,12 +359,13 @@ TEST_CASE("mbedtls ECDSA signature generation on SECP384R1", "[mbedtls][efuse_ke
#if SOC_KEY_MANAGER_SUPPORTED
static void deploy_key_in_key_manager(const uint8_t *k1_encrypted, esp_key_mgr_key_type_t key_type) {
static void deploy_key_in_key_manager(const uint8_t *k1_encrypted, esp_key_mgr_key_type_t key_type, esp_key_mgr_key_len_t key_len) {
esp_key_mgr_aes_key_config_t *key_config = NULL;
key_config = heap_caps_calloc(1, sizeof(esp_key_mgr_aes_key_config_t), MALLOC_CAP_INTERNAL);
TEST_ASSERT_NOT_NULL(key_config);
key_config->key_type = key_type;
key_config->key_len = key_len;
key_config->use_pre_generated_sw_init_key = 1;
memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE);
memcpy(key_config->k1_encrypted[0], (uint8_t*) k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE);
@@ -389,9 +390,9 @@ TEST_CASE("mbedtls ECDSA signature generation on SECP192R1", "[mbedtls][key_mana
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY);
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_192);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_pub_x, ecdsa192_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][key_manager_key]")
@@ -400,9 +401,9 @@ TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][key_mana
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY);
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_256);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_pub_x, ecdsa256_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
#endif /* SOC_KEY_MANAGER_SUPPORTED */
@@ -443,9 +444,9 @@ TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP192R1", "[mbe
if (!ecdsa_ll_is_deterministic_mode_supported()) {
ESP_LOGI(TAG, "Skipping test because ECDSA deterministic mode is not supported.");
} else {
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY);
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_192);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_pub_x, ecdsa192_pub_y, true, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
}
@@ -454,9 +455,9 @@ TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP256R1", "[mbe
if (!ecdsa_ll_is_deterministic_mode_supported()) {
ESP_LOGI(TAG, "Skipping test because ECDSA deterministic mode is not supported.");
} else {
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY);
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_256);
test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_pub_x, ecdsa256_pub_y, true, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
}
#endif /* SOC_KEY_MANAGER_SUPPORTED */
@@ -532,9 +533,9 @@ TEST_CASE("mbedtls ECDSA export public key on SECP192R1", "[mbedtls][key_manager
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY);
deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_192);
test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP192R1, ecdsa192_pub_x, ecdsa192_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
TEST_CASE("mbedtls ECDSA export public key on SECP256R1", "[mbedtls][key_manager_key]")
@@ -543,9 +544,9 @@ TEST_CASE("mbedtls ECDSA export public key on SECP256R1", "[mbedtls][key_manager
TEST_IGNORE_MESSAGE("Key manager is not supported");
}
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY);
deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_ECDSA_LEN_256);
test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP256R1, ecdsa256_pub_x, ecdsa256_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY);
esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY);
}
#endif
#endif /* SOC_ECDSA_SUPPORT_EXPORT_PUBKEY */

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -603,6 +603,10 @@ config SOC_EFUSE_DIS_DIRECT_BOOT
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_ECC
bool
default y

1
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -275,6 +275,7 @@
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_PAD_JTAG 1
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_ECC 1

4
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -879,6 +879,10 @@ config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -374,6 +374,7 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

12
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -1291,6 +1291,10 @@ config SOC_EFUSE_ECDSA_KEY_P384
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_HUK_MEM_NEEDS_RECHARGE
bool
default y
@@ -1351,10 +1355,18 @@ config SOC_FLASH_ENCRYPTION_XTS_AES
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
bool
default y

7
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -513,6 +513,7 @@
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_ECDSA_KEY_P192 1
#define SOC_EFUSE_ECDSA_KEY_P384 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- HUK CAPS----------------------------*/
#define SOC_HUK_MEM_NEEDS_RECHARGE 1
@@ -535,8 +536,10 @@
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 /* SOC_EFUSE_XTS_AES_KEY_128 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 (1) */
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 /* SOC_EFUSE_XTS_AES_KEY_256 (0) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 (1) */
#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1
/*-------------------------- PSRAM Encryption CAPS----------------------------*/

4
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@@ -1123,6 +1123,10 @@ config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32c6/include/soc/soc_caps.h
View File

@@ -455,6 +455,7 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

4
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -923,6 +923,10 @@ config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default n

1
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -381,6 +381,7 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 0
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 0

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -1135,6 +1135,10 @@ config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -474,6 +474,7 @@
#define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#endif
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

4
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
View File

@@ -823,6 +823,10 @@ config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32h21/include/soc/soc_caps.h
View File

@@ -452,6 +452,7 @@
#define SOC_EFUSE_DIS_ICACHE 1
// #define SOC_EFUSE_ECDSA_USE_HARDWARE_K 1 // Force use hardware TRNG supplied K for ECDSA
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

4
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -843,6 +843,10 @@ config SOC_EFUSE_ECDSA_KEY
bool
default n
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

1
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -443,6 +443,7 @@
#define SOC_EFUSE_DIS_ICACHE 0
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_ECDSA_KEY 0 // TODO: [ESP32H4] IDF-12259
#define SOC_EFUSE_XTS_AES_KEY_128 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1695,6 +1695,14 @@ config SOC_EFUSE_ECDSA_KEY
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_EFUSE_XTS_AES_KEY_256
bool
default y
config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
bool
default y

6
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -640,6 +640,8 @@
/* Capability to disable the MSPI access in download mode */
#define SOC_EFUSE_DIS_DOWNLOAD_MSPI 1
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
#define SOC_EFUSE_XTS_AES_KEY_256 1
/*-------------------------- Key Manager CAPS----------------------------*/
#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */
@@ -661,8 +663,8 @@
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 /* SOC_EFUSE_XTS_AES_KEY_128 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 (1) */
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 /* SOC_EFUSE_XTS_AES_KEY_256 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 (1) */
/*-------------------------- MEMPROT CAPS ------------------------------------*/
/*-------------------------- UART CAPS ---------------------------------------*/

8
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -915,6 +915,14 @@ config SOC_EFUSE_DIS_ICACHE
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_EFUSE_XTS_AES_KEY_256
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

2
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -396,6 +396,8 @@
#define SOC_EFUSE_DIS_BOOT_REMAP 1
#define SOC_EFUSE_DIS_LEGACY_SPI_BOOT 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
#define SOC_EFUSE_XTS_AES_KEY_256 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

8
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -1163,6 +1163,14 @@ config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
bool
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_EFUSE_XTS_AES_KEY_256
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y

2
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -470,6 +470,8 @@
#define SOC_EFUSE_DIS_DIRECT_BOOT 1
#define SOC_EFUSE_DIS_ICACHE 1
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_XTS_AES_KEY_128 1
#define SOC_EFUSE_XTS_AES_KEY_256 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1

2
tools/test_apps/system/.build-test-rules.yml
View File

@@ -3,6 +3,8 @@
tools/test_apps/system/bootloader_sections:
disable:
- if: CONFIG_NAME == "rtc_retain" and SOC_RTC_FAST_MEM_SUPPORTED != 1
- if: CONFIG_NAME == "flash_encryption_key_mgr" and (SOC_KEY_MANAGER_FE_KEY_DEPLOY != 1 or IDF_TARGET == "esp32p4")
- if: CONFIG_NAME == "flash_encryption_key_mgr_esp32p4" and IDF_TARGET != "esp32p4"
tools/test_apps/system/build_test:
disable:

4
tools/test_apps/system/bootloader_sections/sdkconfig.ci.flash_encryption_key_mgr Normal file
View File

@@ -0,0 +1,4 @@
CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y
CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR=y
CONFIG_PARTITION_TABLE_OFFSET=0xC000

6
tools/test_apps/system/bootloader_sections/sdkconfig.ci.flash_encryption_key_mgr_esp32p4 Normal file
View File

@@ -0,0 +1,6 @@
CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=y
CONFIG_SECURE_FLASH_ENCRYPTION_KEY_SOURCE_KEY_MGR=y
CONFIG_PARTITION_TABLE_OFFSET=0xC000
CONFIG_ESP32P4_SELECTS_REV_LESS_V3=n