fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage
Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464
See merge request espressif/esp-idf!47432
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the
peripheral in soc_caps, and port the HP-side and LP-core-side SPI
drivers to use the new LL abstraction.
Several LP core pytest files were either hardcoded to specific chip lists
or using a less-precise SOC capability filter:
- test_lp_core_multi_device: was locked to ['esp32c6'] pending a workaround
for LP I2C on esp32p4; all three active LP core chips now have
SOC_LP_I2C_SUPPORTED=1, so switch to soc_filtered_targets.
- test_lp_uart_wakeup_modes: was using SOC_LP_CORE_SUPPORTED which is
semantically wrong for a UART test; change to SOC_ULP_LP_UART_SUPPORTED.
- LP core example pytests (build_system, interrupt, gpio_intr_pulse_counter,
lp_timer_interrupt): replace hardcoded ['esp32c5', 'esp32c6', 'esp32p4']
with soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1') so that new
chips automatically get coverage when their SOC cap is enabled.
This example shows how to have both ULP FSM and RISCV enabled in kconfig
simultaneously, and use them one after another at run time. A new
parameter TYPE is passed to ulp_embed_binary() function to specify fsm
or riscv in CMakeLists.txt. This way, both ulp_fsm and ulp_riscv source
files can be compiled by their respective toolchains under the same
project.
The example shows ULP FSM incrementing a counter from 0 to 100, ULP
RISC-V incrementing from 100 to 500 and main CPU incrementing from 500
to 1500.
Updated kconfig option type and other supporting changes in build system
to allow enabling both ULP FSM and ULP RISCV simultaneously. Users can
choose at run time which one to initialize and use.
NOTE: Both ULP FSM and ULP RISCV can't be used simultaneously at run
time because they share some common hardware like RTC slow memory space.
Closes https://github.com/espressif/esp-idf/issues/12999
Fixes for LP ADC to work when used from the LP core
Closes PM-646, IDFCI-5374, IDFCI-5375, IDFCI-5376, and IDFCI-5377
See merge request espressif/esp-idf!45165
Added a pulse counter example code for ulp riscv chips. The example
works by HP core generating high frequency pulses on a GPIO, which
are counted by ULP core to find out the highest possible frequency
of pulses that can be achieved without missing any edges.
Currently, several example dependencies rely on the fact that all
registered components are added to the build, along with components
specified in common requirements. This results in longer build times
because even unused components must be built. Switch all examples to use
idf_minimal_build to compile only the components actually required by
the example.
Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
Currently, several examples do not explicitly state their component
dependencies, relying instead on the default behavior that includes all
registered components and commonly required ones in the build.
Explicitly adding component dependencies can reduce build time when
set(COMPONENTS main) is used.
Signed-off-by: Frantisek Hrbata <frantisek.hrbata@espressif.com>
This commit adds the lp_core_uart_flush() API to flush the LP UART Tx
FIFO. This API is automatically called once the program returns from the
main function().
Closes https://github.com/espressif/esp-idf/issues/14530
