Report whether the SHA peripheral can run the SM3 mode. The LL function
sha_ll_is_sm3_supported() exists on every chip. ESP32-S31 reads the
DIS_SM_CRYPT eFuse, which disables SM2 and SM3 permanently. ESP32-C5 and
ESP32-H4 have SM3 but no such eFuse. All other chips have no SM3.
The ESP32-S2 Crypto DMA in-channel stalls silently when a receive
descriptor list transitions from external to internal RAM. The AES
driver hits this when a PSRAM-output operation has a trailing partial
block, as the internal stream descriptor is linked after the external
RAM data descriptors.
- esp_aes_process_dma(): process the block-aligned part and the partial
block as two separate DMA operations, keeping each descriptor list
uniform
- crypto_dma_ll_reset(): also reset the in-channel (per the TRM receive
reset sequence), otherwise stale state from a preceding external-RAM
operation corrupts the next operation's output
The GCM DMA path is unaffected; it never operates on PSRAM buffers.
