Commit Graph
286 Commits
Author SHA1 Message Date
Jiang Jiang Jian d27b57156f Merge branch 'feat/pm_components_ram_optimize_v6.0' into 'release/v6.0'
feat(pm): pm components ram optimize (v6.0)

See merge request espressif/esp-idf!52426
2026-09-15 12:03:15 +08:00
wuzhenghuiandCursor ddfaf24b06 change(esp_hw_support): optimize retention driver RAM cost
Co-authored-by: Cursor <cursoragent@cursor.com>
2026-09-04 14:51:00 +08:00
Erhan Kurubas 1c397699b2 feat(system): add OCD stub bin support for more targets
Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21 and esp32p4. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
2026-09-03 13:04:45 +02:00
muhaidong dd8653bbeb fix(coex): remove unsupported external coex soc caps 2026-07-07 14:07:47 +08:00
Jiang Jiang Jian 87d6d58dc8 Merge branch 'fix/move_system_retention_to_esp_hw_support_v6.0' into 'release/v6.0'
refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support (v6.0)

See merge request espressif/esp-idf!49750
2026-06-29 15:41:21 +08:00
wuzhenghui c669729707 refactor(esp_hw_support): move system_periph_retention from soc to esp_hw_support 2026-06-17 12:18:57 +08:00
Song Ruo Jing a242565623 fix(spi_flash): gpspi flash clock could reach higher frequency 2026-06-09 21:56:36 +08:00
Marius Vikhammer 97c1ba269a Merge branch 'feature/update_efuse_table_esp32h4_v6.0' into 'release/v6.0'
feat(efuse): Update efuse table for ESP32-H4 (v6.0)

See merge request espressif/esp-idf!48248
2026-05-15 09:54:28 +08:00
Konstantin Kondrashov 9e03819d91 feat(efuse): Update efuse table for ESP32-H4 2026-05-14 14:42:49 +08:00
igor.masar bcb9d60812 feat(soc): add SOC_USB_FSLS_PHY_NUM for USB-OTG targets
Introduce SOC_USB_FSLS_PHY_NUM on ESP32-S2, ESP32-S3, ESP32-P4 and
ESP32-H4 to expose the number of FSLS USB_WRAP PHYs available on each
target. This separates FSLS USB_WRAP support from OTG/UTMI support so
that downstream code can gate FSLS PHY handling independently.
2026-05-12 18:03:56 +08:00
morris b4424ddf4d Merge branch 'feature/dma2d_with_flash_encryption_v6.0' into 'release/v6.0'
feat(dma2d, ppa): Support flash encryption for DMA2D and PPA (v6.0)

See merge request espressif/esp-idf!46796
2026-03-23 11:07:58 +08:00
Jiang Jiang Jian 81daeadf9f Merge branch 'esp32h4_debug_asistant_v6.0' into 'release/v6.0'
feat(esp32h4): add assist_debug/bus_monitor support (v6.0)

See merge request espressif/esp-idf!45949
2026-03-23 10:38:51 +08:00
Song Ruo Jing 163a95614c feat(dma2d,ppa): Support flash encryption for DMA2D and PPA 2026-03-20 16:53:29 +08:00
morris ba4fe933c2 Merge branch 'feat/usb_max_size_backport_v6.0' into 'release/v6.0'
fix(esp_hal_usb): Add API for transfer max size (backport v6.0)

See merge request espressif/esp-idf!46222
2026-03-20 10:21:12 +08:00
Jiang Jiang Jian 204ad1c7ef Merge branch 'feat/support_rv_fp_retention_v6.0' into 'release/v6.0'
feat(esp_hw_support): support rv fp retention (v6.0)

See merge request espressif/esp-idf!46521
2026-03-20 10:17:11 +08:00
Marius Vikhammer 613f8eaaed Merge branch 'feat/esp_hal_sdmmc_v6.0' into 'release/v6.0'
sd: esp_hal_sd component (v6.0)

See merge request espressif/esp-idf!45623
2026-03-20 10:04:21 +08:00
morris 751231cb64 Merge branch 'bugfix/lp_io_clock_control_v6.0' into 'release/v6.0'
fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists (v6.0)

See merge request espressif/esp-idf!46595
2026-03-19 23:17:09 +08:00
Erhan Kurubas 4a7d67df84 feat(esp32h4): add assist_debug stack monitoring support 2026-03-19 11:40:44 +08:00
Tomas Rezucha ea86272a6a fix(esp_hal_usb): Add API for transfer max size 2026-03-13 14:52:45 +08:00
Song Ruo Jing 68ed9e912b fix(rtcio): RTC GPIO configuration should be written if LP IO clock exists 2026-03-13 11:22:37 +08:00
wuzhenghui 659dbbe5f8 feat(esp_hw_support): support esp32p4 & esp32h4 RV FPU context retention in pd_cpu sleep 2026-03-12 11:06:43 +08:00
wanckl 5bcea31dd7 feat(driver_twai): new driver sleep retention support 2026-02-28 20:11:32 +08:00
armando e8f1938361 change(gpio): move gpio_num.h to gpio hal 2026-02-04 19:00:57 +08:00
Jiang Jiang Jian 31056d5db9 Merge branch 'refactor/spi_flash_private_v6.0' into 'release/v6.0'
refactor(spi_flash): reorganize header files, improve encapsulation and simplify ROM implementation (v6.0)

See merge request espressif/esp-idf!45488
2026-02-02 10:57:34 +08:00
Jiang Jiang Jian d0f992c02f Merge branch 'fix/make_deepsleep_gpio_wakeup_usable_for_pd_top_lightsleep_v6.0' into 'release/v6.0'
change(esp_hw_support): deepsleep gpio wakeup API renaming to support PD_TOP lightsleep wakeup (v6.0)

See merge request espressif/esp-idf!45416
2026-02-02 10:48:40 +08:00
morris 88a2632a27 Merge branch 'feat/support_parlio_on_esp32h4_v6.0' into 'release/v6.0'
feat(parlio): support parlio on esp32h4 (v6.0)

See merge request espressif/esp-idf!44178
2026-02-02 09:50:59 +08:00
wuzhenghui 85601ccb69 change(soc): rename peripheral powerdowned sleep wakeable IO soc_caps
rename SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_MASK
rename SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT to SOC_GPIO_HP_PERIPH_PD_SLEEP_WAKEABLE_PIN_CNT
rename SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP to SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP
2026-02-01 12:16:20 +08:00
wuzhenghui 2d8c6ed6b4 change(esp_hal_rtc_timer): unify lp_timer/rtc_timer naming to RTC_TIMER 2026-01-31 22:31:34 +08:00
Xiao Xufeng 170061e971 refactor(spi_flash): move internal types to private headers and refactor initialization
This commit refactors the SPI flash component to improve encapsulation and
modularity by moving internal types and functions to private headers, and
reorganizing initialization code.

Key changes:

1. Move PSRAM frequency constraint macro from soc_caps.h to mspi_ll.h
   - Rename SOC_SPI_MEM_PSRAM_FREQ_AXI_CONSTRAINED to
     MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED
   - Move macro definition to chip-specific mspi_ll.h files (C5, C61, H4, P4, S31)
   - Update usage in clk_utils.c and esp_flash_spi_init.c
   - Remove old macro from all soc_caps.h files

2. Move internal types to private headers
   - Move esp_flash_t structure to esp_private/esp_flash_types.h
   - Move esp_flash_os_functions_t to esp_private/spi_flash_os.h
   - Update all internal files to include private headers
   - Keep forward declarations in public esp_flash.h

3. Move chip driver header to internal directory
   - Move spi_flash_chip_driver.h to esp_flash_port/spi_flash_chip_driver.h
   - Update all references to use new path
   - Add esp_private/esp_flash_types.h include to the moved header

4. Refactor initialization functions
   - Move init_flash from esp_system/startup_funcs.c to
     spi_flash/esp_flash_spi_init.c
   - Create new init_pm_flash_freq_limit function in startup_funcs.c
     to call esp_pm_flash_freq_limit_init() conditionally
   - Update system_init_fn.txt with new function locations

5. Improve API encapsulation
   - Replace direct access to esp_flash_t->size in
     esp_partition_register_external() with esp_flash_get_size() API
   - Move esp_flash_is_quad_mode from inline function to regular function
     in esp_flash_api.c

6. Update component dependencies
   - Add esp_driver_gpio to spi_flash component PRIV_REQUIRES
   - Remove unused includes and clean up header dependencies

These changes improve code organization by clearly separating public APIs
from internal implementation details, making the codebase more maintainable
and reducing the risk of breaking changes to internal structures.
2026-01-29 03:28:30 +08:00
Chen Chen b7e82de9d8 refactor(i2c): cleanup I2C definitions in soc_caps.h 2026-01-13 17:29:23 +08:00
Chen Jichang 954a7619a2 feat(parlio): support parlio on esp32h4 2026-01-13 17:07:28 +08:00
liuning 9c9f884f3a bugfix(wifi): fix incomplete phy initialization due to absence of bb clocks at coexistence scenarios 2026-01-09 16:53:20 +08:00
Song Ruo Jing 6eec16cf66 refactor(uart): clean up uart soc_caps 2026-01-04 16:02:57 +08:00
Song Ruo Jing a0c91ea082 refactor(uart): remove soc/uart_channel.h 2026-01-04 16:02:57 +08:00
Song Ruo Jing ce475d901d refactor(uart): split UART HAL into separate component 2026-01-04 16:02:57 +08:00
Song Ruo Jing 6ca90bd14a refactor(ledc): split ledc hal into a separate component 2025-12-25 17:23:27 +08:00
Jiang Jiang Jian 9b74192f14 Merge branch 'fix/update_breakpoint_nums_on_c5_h4_v6.0' into 'release/v6.0'
fix(soc): update breakpoint nums on c5 and h4 (v6.0)

See merge request espressif/esp-idf!44355
2025-12-21 15:30:36 +08:00
Jiang Jiang Jian f409428bf3 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0'
fix(spi_flash): Add CPU frequency switching during flash encrypted write (v6.0)

See merge request espressif/esp-idf!44304
2025-12-21 15:28:33 +08:00
Chen Jichang 23f1428356 fix(soc): update breakpoint nums on c5 and h4 2025-12-18 11:21:48 +08:00
Chen Jichang 10c473fbbd feat(hal): graudate the RMT hal driver into a new component 2025-12-17 22:31:25 +08:00
morris 311bec8f82 Merge branch 'fix/spi_edma_and_hal_component_6.0' into 'release/v6.0'
feat(driver_spi): split esp_hal_gpspi and support master driver edma (v6.0)

See merge request espressif/esp-idf!44222
2025-12-17 14:54:05 +08:00
Xiao Xufeng ae7124abe3 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-17 01:21:45 +08:00
wanckl d12f941787 feat(driver_spi): split spi hal component 2025-12-16 20:38:09 +08:00
Chen Chen 1b015d22eb refactor(esp_system): clear dependency on hal components 2025-12-16 09:11:59 +08:00
morris 11ce7a9011 refactor(soc): remove soc_caps_full.h 2025-12-11 10:29:01 +08:00
laokaiyao b8824d2d1a refactor(parlio): refactor of the private parlio caps 2025-12-11 10:26:07 +08:00
laokaiyao 73ebd544fd refactor(i2s): refactor of the private i2s caps 2025-12-11 10:25:42 +08:00
laokaiyao fd918efe43 feat(hal): graudate the I2S hal driver into a new component 2025-12-11 10:25:40 +08:00
morris 37c614d626 feat(twai): graduate the hal drivers into esp_hal_twai component 2025-12-10 13:56:47 +08:00
Song Ruo Jing 4d3a9b0157 refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio 2025-12-08 14:33:26 +08:00