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294 Commits
Author SHA1 Message Date
Jiang Jiang Jian 103e6ef6d3 Merge branch 'feat/pm_components_ram_optimize_v5.4' into 'release/v5.4' 
feat(pm): pm components ram optimize (v5.4)

See merge request espressif/esp-idf!52428
 2026-09-18 10:33:09 +08:00
morris 97f74a7fdf Merge branch 'fix/usb_bbpll_light_sleep_backport_v5.4' into 'release/v5.4' 
fix(usb_phy): Fixed USB PHY clock during low-power modes (backport to v5.4)

See merge request espressif/esp-idf!52784
 2026-09-17 09:59:10 +08:00
wuzhenghui 791360a0f2 change(esp_hw_support): optimize retention driver RAM cost 
(cherry picked from commit 11c590c053)
Co-authored-by: Cursor <cursoragent@cursor.com>
 2026-09-16 19:56:17 +08:00
Tomas Rezucha b3f98785e7 fix(usb_phy): Fixed USB PHY clock during low-power modes 
On ESP32-S3, USB PHY is clocked from BBPLL,
however if the BBPLL is not used as CPU clock source,
the power management unit can turn it off.
This commit registers USB as BBPLL consumer so it is not turned off.

Closes https://github.com/espressif/esp-idf/issues/15451
 2026-09-15 13:59:58 +02:00
cjin 74b9e617d5 fix(phy): add fe dependency when enable rf with regdma 2026-09-15 11:36:18 +08:00
cjin ff113a01f9 feat(modem): add phy retention related api 2026-09-15 11:36:15 +08:00
cjin 520f9ec6a5 feat(phy): add skip list to sleep phy link context and fix deinit crash 2026-09-14 19:37:59 +08:00
cjin 7d9240e67d feat(sleep): add config SOC_PM_SUPPORT_REGDMA_TRIGGERED_PHY 2026-09-14 19:37:59 +08:00
cjin 85fece0652 feat(sleep_modem): allow multi modem to enable rf with regdma 2026-09-14 19:37:57 +08:00
cjin fd844bd2d3 feat(modem): rename the sleep modem functions 2026-09-14 19:18:40 +08:00
cjin 740bb89567 feat(phy): added skip method for phy retention list 2026-09-14 19:18:40 +08:00
cjin 5f74a4da51 feat(phy): rename sleep modem state to sleep phy 2026-09-14 19:18:39 +08:00
wanckl 8ee2dce0d6 fix(esp_hw_support): fixed spi buslock multi dev acq/release logic issue 2026-06-24 16:27:09 +08:00
Xiao Xufeng c8447b51e2 fix(mspi): fixed possible boot failure in some builds when psram is enabled 
A typical scenario is: when XIP on PSRAM enabled, compiler optimization level is Os. Under certain binary layout, boot hangs and backtrace points to `esp_sleep_config_gpio_isolate`.

The root cause is that, during PSRAM initialization, it calls esp_gpio_reserve, which happens to place before the reported function. However, after call, there is no barrier before the clock adjustment in `mspi_timing_enter_low_speed_mode`. The clock gets changed when the cache is still fetching data, resulting in the corrupted data in the end of the cache line.

This commits add spi_flash_disable_cache as a barrier to make sure the cache transactions is finished before the clock switch.
 2026-05-31 01:46:45 +08:00
gaoxu e9120b7572 fix(tsens): fix temp_sensor affect by adc reset 2026-04-22 14:53:57 +08:00
Li Shuai 475900c1fa fix(esp_hw_support): fix analog i2c master race cause by phy retention link 2026-03-12 14:44:13 +08:00
Jiang Jiang Jian d1733defe6 Merge branch 'feat/support_modify_regdma_link_skip_flag_dynamiclly_v5.4' into 'release/v5.4' 
feat(esp_hw_support): add API to supoport modify retention skip flag dynamically (v5.4)

See merge request espressif/esp-idf!46492
 2026-03-12 14:29:44 +08:00
wuzhenghui af9c605877 feat(esp_hw_support): add API to supoport modify retention skip flag dynamically 2026-03-11 19:59:23 +08:00
muhaidong 89b8ccbba9 fix(wifi): fix external coexistence depends on wifi connect issue 2026-03-10 16:28:03 +08:00
liuning cb683b0192 fix(wifi): allow to disable wifi modem clocks if wifi is not inited 2026-03-09 16:54:51 +08:00
liuning 11f962d8c7 feat(phy): add check for required clock bits during phy enable 2026-03-09 16:54:45 +08:00
liuning 3ce165d115 bugfix(wifi): fix incomplete phy initialization due to absence of bb clocks at coexistence scenarios 2026-03-06 17:27:05 +08:00
Jiang Jiang Jian fb9c37ee48 Merge branch 'refactor/spi_flash_private_v5.4' into 'release/v5.4' 
fix(spi_flash): fixed overboundary check skipping of erase and write_encrypted (v5.4)

See merge request espressif/esp-idf!45664
 2026-03-03 10:48:35 +08:00
hebinglin 1d2ffd5941 fix(hal): fix the issue of dual-core contention for RTC_CNTL regs 2026-03-02 12:22:15 +08:00
Xiao Xufeng a0cdaad414 change(spi_flash): Flash frequency will not be decreased during DFS on ESP32-P4, when PSRAM is not enabled. 2026-02-05 16:04:14 +08:00
Song Ruo Jing 1c3a4aafcf feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5 2025-11-18 11:30:24 +08:00
wuzhenghui c87b576745 fix(esp_hw_support): add PD_TOP lightsleep mspi failure workaround for p4 rev3 2025-11-04 16:03:29 +08:00
wuzhenghui d4b3d01b4d feat(esp_hw_support): update cpu_pd support for esp32p4 v3.0 2025-11-04 16:03:27 +08:00
wuzhenghui 7635a54b1e feat(esp_hw_support): add new API to get all wakeup sources 2025-08-26 21:53:01 +08:00
Jiang Jiang Jian b53f520ebc Merge branch 'fix/fix_esp_timer_accuracy_when_do_dfs_v5.4' into 'release/v5.4' 
fix(esp_hw_support): improve esp timer accuracy on DFS for esp32 & esp32s2 (v5.4)

See merge request espressif/esp-idf!39340
 2025-05-26 19:46:58 +08:00
wuzhenghui 78e9c47580 fix(esp_hw_support): update LACT clock prescale immediately when APB changes on esp32 2025-05-22 15:18:16 +08:00
wuzhenghui 1811757ad9 fix(esp_hw_support): Fix deepsleep leakage after initializing USB HS phy 2025-05-15 16:05:05 +08:00
Li Shuai 7014cfc831 fix(esp_hw_support): fix modem wakeup req always high caused by pmu min slp cycle update 2025-05-07 14:25:05 +08:00
wuzhenghui 8cfe912053 fix(esp_hw_support): fix wrong APB clock freq on retenion 2025-04-25 17:13:26 +08:00
wuzhenghui 41e6e25e2d feat(esp_hw_support): remeasure sleep_time_overhead_out if min_freq_mhz changed 2025-04-25 17:13:26 +08:00
wuzhenghui 81860c55d6 feat(esp_hw_support): use non-lock regi2c fast-up cpll/mpll enable process after sleep wakeup 2025-04-25 17:13:22 +08:00
Armando 419e8b2e20 fix(mspi): fixed cpu and mspi freq mismatch issue when in dfs/sleep on p4 2025-03-08 14:06:09 +08:00
wuzhenghui 8e6ec50bcc fix(esp_hw_support): fix esp32s2/esp32s3 RTC IOMUX clock management 2025-02-21 09:50:42 +08:00
Jiang Jiang Jian f9ae8dfb04 Merge branch 'fix/esp32p4_lightsleep_fixes_v5.4' into 'release/v5.4' 
fix(esp_hw_support): some fixes of esp32p4 lightsleep retention & power switch process (v5.4)

See merge request espressif/esp-idf!37086
 2025-02-20 13:48:50 +08:00
wuzhenghui 4542c463c6 change(esp_hw_support): not use ROM Cache invalidate in sleep process to avoid dirtying the L1 Cache 2025-02-19 14:32:12 +08:00
wuzhenghui 67a4de4e77 change(esp_hw_support): switch to sleep_flags earlier to identify sleep state 2025-02-17 16:53:28 +08:00
wuzhenghui 9b7ce542f2 fix(esp_hw_support): fix p4 OTG phy bad suspend cause high power consumption on sleep 2025-01-14 14:22:39 +08:00
Jiang Jiang Jian 569f6c0213 Merge branch 'fix/fix_modem_module_clock_missing_after_ota_v5.4' into 'release/v5.4' 
fix(esp_system): deselect all modem modules lp clock source selection before clk initialization (v5.4)

See merge request espressif/esp-idf!34923
 2024-11-22 13:41:23 +08:00
Li Shuai 78b272c092 feat(esp_hw_support): extend sleep retention module bitmap bit width 2024-11-18 15:57:42 +08:00
wuzhenghui a2d26ab56f fix(esp_system): deselect all modem modules clk source selection before clk init 2024-11-15 11:00:54 +08:00
Xiao Xufeng 802e7b2192 feat(sleep_retention): allow drivers taking TOP power lock 
Also add a dump function
 2024-11-05 03:22:01 +08:00
wuzhenghui 71ddc5a79f fix(esp_hw_support): fix mmu retention code cache safety 2024-10-22 22:10:13 +08:00
Song Ruo Jing ed91ad56da Merge branch 'refactor/pll_pd_in_sleep_logic' into 'master' 
fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL

See merge request espressif/esp-idf!34241
 2024-10-18 14:12:15 +08:00
Armando (Dou Yiwen) e05fce3c9c Merge branch 'feat/lp_i2s_vad' into 'master' 
lp_i2s: vad lp driver and lp/hp core wakeup feature

Closes IDF-10211 and IDF-6517

See merge request espressif/esp-idf!33804
 2024-10-17 15:01:08 +08:00
Song Ruo Jing 7c0b1dc98c fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code
 2024-10-17 12:41:15 +08:00