6 Commits

Author	SHA1	Message	Date
Ashish Sharma	8956f3b86c	feat(sha): add sha_hal_is_sm3_supported() ... Report whether the SHA peripheral can run the SM3 mode. The LL function sha_ll_is_sm3_supported() exists on every chip. ESP32-S31 reads the DIS_SM_CRYPT eFuse, which disables SM2 and SM3 permanently. ESP32-C5 and ESP32-H4 have SM3 but no such eFuse. All other chips have no SM3.	2026-09-04 14:26:23 +08:00
wuzhenghui	a04dc898db	feat(esp_security): support s31 security clock management	2026-07-22 16:32:45 +08:00
harshal.patil	554cce6937	fix(mbedtls): validate ECDSA signature range and harden ECC memory power-down	2026-06-09 10:59:11 +05:30
Konstantin Kondrashov	f870ed9d61	feat(efuse): Update efuse table for ESP32H21	2026-05-21 16:29:09 +03:00
nilesh.kale	f400c78d42	feat(hal): enable ecdsa support in esp32h4	2026-05-12 15:26:17 +05:30
Aditya Patwardhan	eb4a871eca	refactor(esp_hal_security): Updated esp_hal_security build and includes	2026-01-21 10:02:44 +05:30