muhaidong
fc20d3f1e5
fix(esp_security): fix ECDH1 key manager multi-stage helper
2026-05-11 12:04:44 +05:30
harshal.patil
98bbe26aea
feat(esp_security): add ECDH1 deployment mode to Key Manager driver
2026-05-11 09:38:00 +05:30
nilesh.kale
1f506e7a54
test(esp_security): re-enable crypto drivers test app for ESP32P4
...
Also remove common_components dep for security-related tests
2026-05-04 18:18:20 +05:30
harshal.patil
7da92d6f82
test(esp_security): Update the Key Manager test to support ESP32-P4
2026-05-04 18:18:20 +05:30
harshal.patil
ba5fdc77fd
fix(esp_security): guard key manager APIs against unsupported chip revs
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On ESP32-P4 rev < 3.0, Key Manager is software-disabled, but the public
esp_key_mgr.h APIs had no runtime check.
Calls using HMAC/DS/PSRAM key types fell through to
HAL_ASSERT("Unsupported ...") paths in key_mgr_ll.h. Gate
each public API with key_mgr_ll_is_supported() and return
ESP_ERR_NOT_SUPPORTED cleanly instead.
2026-05-04 18:18:20 +05:30
harshal.patil
63b2f2c8e8
fix(esp_security): Fix the flipped key info slot when deploying a Key Manager-based key
2026-05-04 15:42:30 +05:30
harshal.patil
1caafa9e2b
fix(esp_security): Enable ECC clock while using the Key Manager's ECDH key deployment mode
2026-05-04 15:42:30 +05:30
Jiang Jiang Jian
9d3893303c
Merge branch 'fix/enable_key_mgr_clk_for_efuse_key_ops_v6.0' into 'release/v6.0'
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Enable Key Manager clock even for efuses-based key operations (v6.0)
See merge request espressif/esp-idf!46754
2026-03-25 16:02:08 +08:00
harshal.patil
1db26df63d
fix(esp_security): Fixes incorrect key manager configuration for ESP32-P4 rev < 3
2026-03-24 16:33:25 +05:30
harshal.patil
2339834e4a
fix(esp_security): Enable Key Manager clocks even for efuse key operations
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The Key Manager holds a key usage register, thus, the Key Manager peripheral
clock must be enabled even for efuses-based key operations to route the
crypto operations to correctly to the efuses (default is Key Manager)
2026-03-24 16:23:16 +05:30
harshal.patil
fe3b5ca898
fix(esp_security): Add more validation checks
2026-03-23 10:46:23 +05:30
harshal.patil
45d5ef45a5
feat(esp_ds): Support using the AES key used by DS peripheral for encrypting params
2026-03-23 10:46:22 +05:30
igor.udot
e2a8bbe639
ci: update build-test-rules to use common_components
2026-03-20 15:53:26 +08:00
Jiang Jiang Jian
779fd7a52c
Merge branch 'feat/support_p4_clk_tree_ref_cnt_v6.0' into 'release/v6.0'
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feat(esp_hw_support): support clock tree management for esp32p4 (v6.0)
See merge request espressif/esp-idf!46444
2026-03-20 10:16:53 +08:00
harshal.patil
629a4e2444
docs(key-manager): Add Key-Manager peripheral related documentation
2026-03-18 16:42:21 +05:30
wuzhenghui
15345f9d8c
feat(esp_hw_support): support clock tree management for esp32p4
2026-03-10 14:10:36 +08:00
Xiao Xufeng
3d263e7304
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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This reverts commit 7145fc9558
2026-02-06 11:48:27 +08:00
Aditya Patwardhan
4d3cfefc2e
refactor(esp_hal_security): Updated esp_hal_security build and includes
2026-01-30 17:12:54 +05:30
Xiao Xufeng
32e4e83f84
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
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This reverts commit cca0ac8c56
2026-01-15 23:44:05 +08:00
Xiao Xufeng
cca0ac8c56
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
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This reverts commit 7145fc9558
2025-12-24 02:31:42 +08:00
Xiao Xufeng
469953bd04
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption"
...
This reverts commit 3c5d2e6b58
2025-12-17 01:21:46 +08:00
Jiang Jiang Jian
ee4be1af57
Merge branch 'feat/flash_enc_using_key_manager_v6.0' into 'release/v6.0'
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Support Flash Encryption using Key Manager (v6.0)
See merge request espressif/esp-idf!43459
2025-11-24 10:35:48 +08:00
armando
714b022a43
ci(p4): disable p4 rev3 invalid tests temporarily
2025-11-21 02:48:05 +00:00
harshal.patil
9a18386202
feat(esp_security): Support ECDSA-P384 key deployment using Key Manager
2025-11-20 11:37:07 +05:30
harshal.patil
cd0770cd39
change(esp_key_mgr): Store key_len field in the key_info
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- Update the Key Manager key types to be generic
- Define a new enum to determine the length of the keys
- Refactor the Key Manager driver support generic key types and key lengths
- Also store key deployment mode in the key recovery info
2025-11-20 11:37:07 +05:30
harshal.patil
7212b517d4
change(esp_key_mgr): Make Key Manager driver bootloader compatible
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- Independent of heap
2025-11-20 11:37:07 +05:30
harshal.patil
c1503cd847
feat(bootloader_support): Support Flash Encryption using Key Manager
2025-11-20 11:37:05 +05:30
harshal.patil
46e2cd21d4
fix(esp_security/esp_key_mgr): Fix missed error codes and some cleanup
2025-11-20 11:35:22 +05:30
Laukik Hase
2cb0fa5c34
feat(esp_tee): Support for ESP32-C61 - the rest of the components
2025-11-19 10:57:42 +05:30
Jiang Jiang Jian
6472c8215a
Merge branch 'bugfix/esp32c5_encrypted_flash_write_v6.0' into 'release/v6.0'
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fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v6.0)
See merge request espressif/esp-idf!43325
2025-11-18 12:27:21 +08:00
Mahavir Jain
0f77374746
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption
...
Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.
This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
2025-11-13 13:25:57 +05:30
harshal.patil
54c5c760ba
fix(esp_security): Set WR_DIS_SECURE_BOOT_SHA384_EN by default when
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Flash Encryption Release mode is enabled and Secure Boot P384 scheme not is enabled.
2025-11-11 17:52:21 +05:30
harshal.patil
488dcb58e1
fix(esp_security): Fix undefined efuse build failure in case of ESP32-P4
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- The `wr_dis` efuse bit corresponding to `SECURE_BOOT_SHA384_EN` is absent in P4
2025-11-11 17:52:21 +05:30
harshal.patil
609d52c6bf
feat(esp32p4): Support newer Key Manager key sources for ESP32-P4 V3
2025-10-15 15:49:20 +05:30
Harshal Patil
fd7d9c9ee9
Merge branch 'fix/key_mgr_use_default_efuse_key' into 'master'
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Configure the Key Manager to use XTS-AES efuse key by-default
Closes IDFCI-3135 and IDFCI-3136
See merge request espressif/esp-idf!42032
2025-09-26 12:34:19 +05:30
harshal.patil
8b663ebe4d
fix(esp_security): Configure the Key Manager to use XTS-AES efuse key by-default
2025-09-22 12:22:07 +05:30
harshal.patil
5aa5366e7f
fix(bootloader_support): Reorder write disabling ECDSA_CURVE_MODE
2025-09-19 17:01:23 +05:30
harshal.patil
d6c1184676
fix(bootloader_support): Reorder write protection bits of some shared security efuses
2025-09-19 13:02:00 +05:30
harshal.patil
854ec3590f
fix(esp_key_mgr): Fix incorrect key manager state management
2025-09-12 11:02:45 +05:30
Marek Fiala
9d35d63651
feat(cmake): Update minimum cmake version to 3.22 (whole repository)
2025-08-19 14:44:32 +02:00
harshal.patil
9e87b50307
change(mbedtls/ecdsa): The ECDSA module of ESP32-H2 ECO5 does not use MPI module
2025-08-11 12:08:51 +05:30
harshal.patil
55e0730a8d
change(esp_hw_support): Move security-related modules to the esp_security component
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- Also adds support to whitelist target specific expected dependency violations
in check_dependencies.py
2025-08-04 11:43:01 +05:30
Marius Vikhammer
bf84ab652a
change(test_utils): moved test_utils component to tools/test_apps/components/
2025-07-21 14:05:50 +08:00
harshal.patil
dce0925f40
fix(esp_security/esp_key_mgr): Incorrect overlapping comparisons
2025-07-03 15:05:50 +05:30
harshal.patil
bba1448128
feat(esp_key_mgr): Support PSRAM XTS-AES key deployments using Key Manager
2025-06-27 15:15:26 +05:30
harshal.patil
eb7c5654f6
test(esp_security): Extend the key manager tests
2025-06-27 15:15:26 +05:30
harshal.patil
50c41c3b59
change(esp_key_mgr): Refactor Key Manager driver to reduce logs
2025-06-27 15:15:26 +05:30
harshal.patil
a7af364112
fix(esp_security): Power up MPI memory registers when enabling MPI
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Co-authored-by: Li HongXi <lihongxi@espressif.com >
2025-06-27 15:15:26 +05:30
harshal.patil
33d8c05d95
feat(esp_key_mgr): Support Digital Signature key deployments using Key Manager
2025-06-27 15:15:26 +05:30
harshal.patil
265b0d7579
feat(esp_key_mgr): Support HMAC key deployments using Key Manager
2025-06-27 15:15:26 +05:30
