Commit Graph

25 Commits

Author SHA1 Message Date
Mahavir Jain
231dc0e884 feat(esp_psram): add esp_psram_ptr_is_no_enc() helper
Drivers that allocate from the unencrypted PSRAM carve-out via
MALLOC_CAP_SPIRAM_NO_ENC currently have no way to verify after the fact
which pool a buffer came from. This is particularly relevant for callers
using heap_caps_malloc_prefer(MALLOC_CAP_SPIRAM_NO_ENC, MALLOC_CAP_SPIRAM),
where a silent fallback to encrypted PSRAM would still pass the typical
esp_ptr_external_ram() check.

Expose esp_psram_ptr_is_no_enc() in the public esp_psram.h header. It
performs a range check against the carve-out's virtual-address window and
returns false when PSRAM is not initialized or CONFIG_SPIRAM_ENC_EXEMPT is
disabled, so callers do not need to guard the call site with #if.

Also reference the helper from the External RAM documentation alongside
the heap_caps_malloc(MALLOC_CAP_SPIRAM_NO_ENC) usage example.
2026-05-20 10:28:06 +05:30
Mahavir Jain
99fe60f404 fix(esp_psram): handle carve-out vaddr exhaustion and add region to self-test
If the virtual-address pool is exhausted when reserving the unencrypted
PSRAM carve-out (the warning at L388 may already have fired for the main
mapping), esp_mmu_map_reserve_block_with_caps() returns an error rather
than aborting. Convert the previous assert() into a logged fallback that
disables the carve-out for this boot, mirroring the SPIRAM_ENC_EXEMPT_SIZE
>= psram_available_size path.

Also extend esp_psram_extram_test() to run the standard memory test on
the carve-out region when CONFIG_SPIRAM_ENC_EXEMPT is enabled, so the
unencrypted mapping is exercised on startup like the other PSRAM regions.
2026-05-20 10:24:28 +05:30
harshal.patil
b4517542ae change(esp_psram): Consider all PSRAM regions in PMP protection 2026-05-19 21:32:29 +05:30
Mahavir Jain
23aba459f5 feat(esp_psram): add option to carve unencrypted PSRAM region
Adds CONFIG_SPIRAM_ENC_EXEMPT, available on chips that support per-page
PSRAM encryption configuration (esp32c5, esp32c61, esp32p4). When
enabled, esp_psram carves CONFIG_SPIRAM_ENC_EXEMPT_SIZE off the top of
PSRAM and maps it via the new mmu_hal_map_region_no_enc() helper, which
writes MMU entries without the SENSITIVE bit. The region is registered
as a separate heap pool reachable only through the new
MALLOC_CAP_SPIRAM_NO_ENC capability bit, so default SPIRAM allocations
cannot accidentally land there.

PSRAM encryption imposes alignment constraints that some DMA engines
(e.g. 2D-DMA) cannot satisfy. This option lets such workloads place
their buffers in unencrypted PSRAM while keeping the rest of PSRAM
(and flash) encrypted. Default disabled; security implications are
documented in the Kconfig help text.
2026-05-14 19:21:18 +05:30
armando
ab026ecc01 feat(mmu): configurable page size s31 support 2026-04-20 16:58:29 +08:00
C.S.M
62d5f34b53 feat(ldo): Add ldo support for psram on esp32s31 2026-04-01 16:31:35 +08:00
Song Ruo Jing
29d62fa6ae feat(mspi): add clear log in psram mspi intr isr for addr misaligned error 2026-02-26 16:38:06 +08:00
Xiao Xufeng
59313eb01f fix: fix psram, rtc_clk on P4 v3.1 2026-01-19 22:32:20 +08:00
Xiao Xufeng
e644aed729 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-19 16:58:16 +08:00
morris
cf33484844 fix(dma): add PSRAM memory barrier for external RAM buffers 2026-01-15 10:11:25 +08:00
armando
41e854d7df fix(mspi): fixed mspi dma burst timing issue 2026-01-09 10:37:49 +08:00
Michael (XIAO Xufeng)
276e01c85b Merge branch 'fix/psram_encryption_warning_c5c61' into 'master'
fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on...

See merge request espressif/esp-idf!44618
2025-12-29 11:42:43 +08:00
Xiao Xufeng
84781bc4bc fix(psram): fix inaccurate warning that encryption not enabled on PSRAM on ESP32-C5 v1.2 and C61 v1.1 2025-12-28 21:25:26 +08:00
armando
7fe40f12ba feat(mspi): supported mspi flash and psram isr 2025-12-26 01:04:45 +00:00
armando
9fadbf2588 fix(psram): fixed p4 rev3 xip stuck after board reset issue 2025-10-20 03:09:47 +00:00
Marius Vikhammer
484d2c5c2f fix(system): fixed issues with unused variable warnings when compiling with NDEBUG 2025-09-19 15:42:07 +08:00
Mahavir Jain
54c7803cd3 fix(psram): provide boot warning about PSRAM encryption issue on C5/C61
For C5/C61 revision 1.0, PSRAM encryption has hardware issue. This will
be addressed in future silicon version. Add explicit warning about this.
2025-08-11 18:06:11 +05:30
armando
7a6cd632c5 fix(psram): fixed psram ptr check under xip_psram condition
Closes https://github.com/espressif/esp-idf/pull/15999
Closes https://github.com/espressif/esp-idf/issues/15997
2025-06-06 10:11:32 +08:00
John Boiles
0e680775f9 fix(memory-utils): Add _instruction_reserved_start/end to esp_psram_check_ptr_addr
Adds missing range check that can be used when SPIRAM_XIP_FROM_PSRAM is enabled.
2025-06-06 10:11:32 +08:00
harshal.patil
3123fff18a fix(esp_psram): Add XIP PSRAM alignment gaps in heap only if PSRAM protection is enabled 2025-05-05 10:50:19 +05:30
harshal.patil
ab229a34b3 feat(cpu_region_protect): Enable basic memory protection for SPIRAM 2025-04-29 11:48:27 +05:30
harshal.patil
49f253361e feat(esp_psram): Add the gap created due to alignment of XIP segments in heap 2025-04-29 11:48:27 +05:30
harshal.patil
0f628496c8 feat(esp_psram): Add some helper APIs to get usable PSRAM memory size 2025-04-29 11:48:27 +05:30
harshal.patil
46225a4026 feat(esp_psram): Add a new API to just detect and enable the PSRAM
- esp_psram_chip_init() just detects and does basic initialisations of PSRAM
- esp_psram_init() initialises and maps/loads the PSRAM pages
2025-04-29 11:48:27 +05:30
armando
ac8cfadab0 refactor(psram): cleanup psram component code structure 2025-03-20 15:17:01 +08:00