feat(esp_hw_support): support esp32s31 lowpower features
Closes IDF-5660, IDF-14643, IDF-14645, IDF-14647, IDF-14648, IDF-14784, PM-708, and PM-714
See merge request espressif/esp-idf!47216
fix(ulp/lp_core): fix LP UART data_bits validation and add full word-length test coverage
Closes PM-715, PM-660, IDFCI-10410, and IDFCI-10464
See merge request espressif/esp-idf!47432
Add LP SPI HAL LL layer for ESP32-S31 and ESP32-P4, enable the
peripheral in soc_caps, and port the HP-side and LP-core-side SPI
drivers to use the new LL abstraction.
Several LP core pytest files were either hardcoded to specific chip lists
or using a less-precise SOC capability filter:
- test_lp_core_multi_device: was locked to ['esp32c6'] pending a workaround
for LP I2C on esp32p4; all three active LP core chips now have
SOC_LP_I2C_SUPPORTED=1, so switch to soc_filtered_targets.
- test_lp_uart_wakeup_modes: was using SOC_LP_CORE_SUPPORTED which is
semantically wrong for a UART test; change to SOC_ULP_LP_UART_SUPPORTED.
- LP core example pytests (build_system, interrupt, gpio_intr_pulse_counter,
lp_timer_interrupt): replace hardcoded ['esp32c5', 'esp32c6', 'esp32p4']
with soc_filtered_targets('SOC_LP_CORE_SUPPORTED == 1') so that new
chips automatically get coverage when their SOC cap is enabled.
fix(otatool): fix flaky serial port handoff in otatool CI test
Closes IDFCI-3263, IDFCI-3302, IDFCI-3402, IDFCI-3410, IDFCI-4548, IDFCI-5191, IDFCI-6937, and IDFCI-7329
See merge request espressif/esp-idf!47318
The otatool pytest calls dut.serial.close() and then immediately
launches otatool_example.py as a subprocess that re-opens the same
serial port via esptool. This fails intermittently because:
1. pytest-embedded's QueueFeederThread still holds a reference to
the serial port file descriptor when close() returns, causing
'argument must be an int, or have a fileno() method' error.
2. The OS has not fully released the serial port by the time the
subprocess tries to open it.
Add a delay after serial close and retry logic for the subprocess
to handle transient serial port contention.
Made-with: Cursor
The hw-reference/modules-and-boards page was removed from esp-idf docs
and moved to esp-dev-kits. The ESP32-S2-Saola-1 user guide similarly
moved. The configure-builtin-jtag link used the now-obsolete chip-less
stable URL format.
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
- Move the linux repl chip and deprecate chip related functions
- Update location of driver specific default config
- Add missing comments on the newly added functions in the affected components.
Use real CI config names and minimal config aliases so these tests are
collected and built again instead of silently being skipped.
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Made-with: Cursor
This example shows how to have both ULP FSM and RISCV enabled in kconfig
simultaneously, and use them one after another at run time. A new
parameter TYPE is passed to ulp_embed_binary() function to specify fsm
or riscv in CMakeLists.txt. This way, both ulp_fsm and ulp_riscv source
files can be compiled by their respective toolchains under the same
project.
The example shows ULP FSM incrementing a counter from 0 to 100, ULP
RISC-V incrementing from 100 to 500 and main CPU incrementing from 500
to 1500.
Updated kconfig option type and other supporting changes in build system
to allow enabling both ULP FSM and ULP RISCV simultaneously. Users can
choose at run time which one to initialize and use.
NOTE: Both ULP FSM and ULP RISCV can't be used simultaneously at run
time because they share some common hardware like RTC slow memory space.
Closes https://github.com/espressif/esp-idf/issues/12999
