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feat(parlio): move parlio retention info from esp_hal_parlio to esp_driver_parlio

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morris
2026-04-22 13:53:32 +08:00
parent daa204381a
commit efabe471c3
18 changed files with 305 additions and 251 deletions
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components/soc/esp32h4/register/soc/parl_io_reg.h
+23 -23
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -13,7 +13,7 @@ extern "C" {
/** PARL_IO_RX_MODE_CFG_REG register
* Parallel RX Sampling mode configuration register.
*/
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_BASE + 0x0)
#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0)
/** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7;
* Configures rx external enable signal selection from IO PAD.
*/
@@ -62,7 +62,7 @@ extern "C" {
/** PARL_IO_RX_DATA_CFG_REG register
* Parallel RX data configuration register.
*/
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x4)
#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4)
/** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of received data.
*/
@@ -92,7 +92,7 @@ extern "C" {
/** PARL_IO_RX_GENRL_CFG_REG register
* Parallel RX general configuration register.
*/
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x8)
#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8)
/** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0;
* Write 1 to enable the clock gating of output rx clock.
*/
@@ -126,7 +126,7 @@ extern "C" {
/** PARL_IO_RX_START_CFG_REG register
* Parallel RX Start configuration register.
*/
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_BASE + 0xc)
#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc)
/** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start rx data sampling.
*/
@@ -138,7 +138,7 @@ extern "C" {
/** PARL_IO_TX_DATA_CFG_REG register
* Parallel TX data configuration register.
*/
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x10)
#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10)
/** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0;
* Configures expected byte number of sent data.
*/
@@ -168,7 +168,7 @@ extern "C" {
/** PARL_IO_TX_START_CFG_REG register
* Parallel TX Start configuration register.
*/
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_BASE + 0x14)
#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14)
/** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0;
* Write 1 to start tx data transmit.
*/
@@ -180,7 +180,7 @@ extern "C" {
/** PARL_IO_TX_GENRL_CFG_REG register
* Parallel TX general configuration register.
*/
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x18)
#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18)
/** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0;
* Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length.
* 1'b1: eof generated by DMA eof.
@@ -214,7 +214,7 @@ extern "C" {
/** PARL_IO_FIFO_CFG_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_BASE + 0x1c)
#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c)
/** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0;
* Write 1 to reset async fifo in tx module.
*/
@@ -233,7 +233,7 @@ extern "C" {
/** PARL_IO_REG_UPDATE_REG register
* Parallel IO FIFO configuration register.
*/
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_BASE + 0x20)
#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20)
/** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0;
* Write 1 to update rx register configuration.
*/
@@ -245,7 +245,7 @@ extern "C" {
/** PARL_IO_ST_REG register
* Parallel IO module status register0.
*/
#define PARL_IO_ST_REG (DR_REG_PARL_BASE + 0x24)
#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24)
/** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0;
* Represents the status that tx is ready to transmit.
*/
@@ -257,7 +257,7 @@ extern "C" {
/** PARL_IO_INT_ENA_REG register
* Parallel IO interrupt enable signal configuration register.
*/
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_BASE + 0x28)
#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28)
/** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable TX_FIFO_REMPTY_INT.
*/
@@ -283,7 +283,7 @@ extern "C" {
/** PARL_IO_INT_RAW_REG register
* Parallel IO interrupt raw signal status register.
*/
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_BASE + 0x2c)
#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c)
/** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
* The raw interrupt status of TX_FIFO_REMPTY_INT.
*/
@@ -309,7 +309,7 @@ extern "C" {
/** PARL_IO_INT_ST_REG register
* Parallel IO interrupt signal status register.
*/
#define PARL_IO_INT_ST_REG (DR_REG_PARL_BASE + 0x30)
#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30)
/** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of TX_FIFO_REMPTY_INT.
*/
@@ -335,7 +335,7 @@ extern "C" {
/** PARL_IO_INT_CLR_REG register
* Parallel IO interrupt clear signal configuration register.
*/
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_BASE + 0x34)
#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34)
/** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear TX_FIFO_REMPTY_INT.
*/
@@ -361,7 +361,7 @@ extern "C" {
/** PARL_IO_RX_ST0_REG register
* Parallel IO RX status register0
*/
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_BASE + 0x38)
#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38)
/** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0;
* Indicates the cycle number of reading Rx FIFO.
*/
@@ -380,7 +380,7 @@ extern "C" {
/** PARL_IO_RX_ST1_REG register
* Parallel IO RX status register1
*/
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_BASE + 0x3c)
#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c)
/** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0;
* Indicates the current read bit number from Rx FIFO.
*/
@@ -392,7 +392,7 @@ extern "C" {
/** PARL_IO_TX_ST0_REG register
* Parallel IO TX status register0
*/
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_BASE + 0x40)
#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40)
/** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0;
* Indicates the cycle number of reading Tx FIFO.
*/
@@ -411,7 +411,7 @@ extern "C" {
/** PARL_IO_RX_CLK_CFG_REG register
* Parallel IO RX clk configuration register
*/
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x44)
#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44)
/** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Rx core clock.
*/
@@ -430,7 +430,7 @@ extern "C" {
/** PARL_IO_TX_CLK_CFG_REG register
* Parallel IO TX clk configuration register
*/
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x48)
#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48)
/** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0;
* Write 1 to invert the input Tx core clock.
*/
@@ -449,7 +449,7 @@ extern "C" {
/** PARL_IO_TX_CS_CFG_REG register
* Parallel IO tx_cs_o generate configuration
*/
#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_BASE + 0x4c)
#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c)
/** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0;
* configure the delay between data tx end and tx_cs_o posedge
*/
@@ -468,7 +468,7 @@ extern "C" {
/** PARL_IO_CLK_REG register
* Parallel IO clk configuration register
*/
#define PARL_IO_CLK_REG (DR_REG_PARL_BASE + 0x120)
#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120)
/** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0;
* Force clock on for this register file
*/
@@ -480,7 +480,7 @@ extern "C" {
/** PARL_IO_VERSION_REG register
* Version register.
*/
#define PARL_IO_VERSION_REG (DR_REG_PARL_BASE + 0x3fc)
#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc)
/** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160;
* Version of this register file
*/