From efabe471c31f5b7b56de88d47a9b1cabf5497ce5 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 21 Apr 2026 19:39:47 +0800 Subject: [PATCH] feat(parlio): move parlio retention info from esp_hal_parlio to esp_driver_parlio --- components/esp_driver_parlio/CMakeLists.txt | 7 ++- .../esp32c5/parlio_retention.c | 38 +++++++++++++++ .../esp32c6/parlio_retention.c | 36 +++++++++++++++ .../esp32h2/parlio_retention.c | 38 +++++++++++++++ .../esp32h21/parlio_retention.c | 36 +++++++++++++++ .../esp32h4/parlio_retention.c | 38 +++++++++++++++ .../esp32p4/parlio_retention.c | 38 +++++++++++++++ .../esp_driver_parlio/src/parlio_common.c | 14 +++--- .../esp_driver_parlio/src/parlio_priv.h | 12 ++++- .../esp_hal_parlio/esp32c5/parlio_periph.c | 33 +------------ .../esp_hal_parlio/esp32c6/parlio_periph.c | 31 +------------ .../esp_hal_parlio/esp32h2/parlio_periph.c | 33 +------------ .../esp_hal_parlio/esp32h21/parlio_periph.c | 29 +----------- .../esp_hal_parlio/esp32h4/parlio_periph.c | 33 +------------ .../esp_hal_parlio/esp32p4/parlio_periph.c | 33 +------------ .../include/hal/parlio_periph.h | 17 +------ .../soc/esp32h21/register/soc/parl_io_reg.h | 44 +++++++++--------- .../soc/esp32h4/register/soc/parl_io_reg.h | 46 +++++++++---------- 18 files changed, 305 insertions(+), 251 deletions(-) create mode 100644 components/esp_driver_parlio/esp32c5/parlio_retention.c create mode 100644 components/esp_driver_parlio/esp32c6/parlio_retention.c create mode 100644 components/esp_driver_parlio/esp32h2/parlio_retention.c create mode 100644 components/esp_driver_parlio/esp32h21/parlio_retention.c create mode 100644 components/esp_driver_parlio/esp32h4/parlio_retention.c create mode 100644 components/esp_driver_parlio/esp32p4/parlio_retention.c diff --git a/components/esp_driver_parlio/CMakeLists.txt b/components/esp_driver_parlio/CMakeLists.txt index 57d2a8b61e9..04174045e6c 100644 --- a/components/esp_driver_parlio/CMakeLists.txt +++ b/components/esp_driver_parlio/CMakeLists.txt @@ -7,6 +7,10 @@ if(CONFIG_SOC_PARLIO_SUPPORTED) "src/parlio_tx.c" "src/parlio_rx.c") + if(CONFIG_SOC_PAU_SUPPORTED AND CONFIG_SOC_PARLIO_SUPPORT_SLEEP_RETENTION) + list(APPEND srcs "${target}/parlio_retention.c") + endif() + if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED) list(APPEND srcs "src/parlio_bitscrambler.c") endif() @@ -21,7 +25,8 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${public_include} + PRIV_INCLUDE_DIRS "src" PRIV_REQUIRES "${priv_requires}" REQUIRES esp_hal_parlio LDFRAGMENTS "linker.lf" - ) + ) diff --git a/components/esp_driver_parlio/esp32c5/parlio_retention.c b/components/esp_driver_parlio/esp32c5/parlio_retention.c new file mode 100644 index 00000000000..27ca647e5f6 --- /dev/null +++ b/components/esp_driver_parlio/esp32c5/parlio_retention.c @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG + * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG + * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG + */ +#define PARLIO_RETENTION_REGS_CNT 8 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/esp32c6/parlio_retention.c b/components/esp_driver_parlio/esp32c6/parlio_retention.c new file mode 100644 index 00000000000..02e21f48a2c --- /dev/null +++ b/components/esp_driver_parlio/esp32c6/parlio_retention.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Configuration registers, e.g.: PARL_IO_RX_CFG0_REG, PARL_IO_RX_CFG1_REG, PARL_IO_TX_CFG0_REG, PARL_IO_TX_CFG1_REG, PARL_IO_CLK_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG +*/ +#define PARLIO_RETENTION_REGS_CNT 6 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x2f, 0x0, 0x100, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/esp32h2/parlio_retention.c b/components/esp_driver_parlio/esp32h2/parlio_retention.c new file mode 100644 index 00000000000..27ca647e5f6 --- /dev/null +++ b/components/esp_driver_parlio/esp32h2/parlio_retention.c @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG + * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG + * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG + */ +#define PARLIO_RETENTION_REGS_CNT 8 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/esp32h21/parlio_retention.c b/components/esp_driver_parlio/esp32h21/parlio_retention.c new file mode 100644 index 00000000000..218a7772c0a --- /dev/null +++ b/components/esp_driver_parlio/esp32h21/parlio_retention.c @@ -0,0 +1,36 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG + * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG + * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG + */ +#define PARLIO_RETENTION_REGS_CNT 8 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/esp32h4/parlio_retention.c b/components/esp_driver_parlio/esp32h4/parlio_retention.c new file mode 100644 index 00000000000..27ca647e5f6 --- /dev/null +++ b/components/esp_driver_parlio/esp32h4/parlio_retention.c @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG + * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG + * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG + */ +#define PARLIO_RETENTION_REGS_CNT 8 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ + PARLIO_RETENTION_REGS_CNT, 0, 0, \ + parlio_regs_map[0], parlio_regs_map[1], \ + parlio_regs_map[2], parlio_regs_map[3]), \ + .owner = ENTRY(0) | ENTRY(2) + }, \ +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/esp32p4/parlio_retention.c b/components/esp_driver_parlio/esp32p4/parlio_retention.c new file mode 100644 index 00000000000..324e5ba095a --- /dev/null +++ b/components/esp_driver_parlio/esp32p4/parlio_retention.c @@ -0,0 +1,38 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "parlio_priv.h" + +/** + * PARLIO Registers to be saved during sleep retention + * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG + * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG + * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG + * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG + */ +#define PARLIO_RETENTION_REGS_CNT 8 +#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) +static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; +static const regdma_entries_config_t parlio_regs_retention[] = { + // backup stage: save configuration registers + // restore stage: restore the configuration registers + [0] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), + PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, + PARLIO_RETENTION_REGS_CNT, 0, 0, + parlio_regs_map[0], parlio_regs_map[1], + parlio_regs_map[2], parlio_regs_map[3]), + .owner = ENTRY(0) + }, +}; + +const parlio_retention_desc_t parlio_retention_infos[1] = { + [0] = { + .regdma_entry_array = parlio_regs_retention, + .array_size = ARRAY_SIZE(parlio_regs_retention), + .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 + }, +}; diff --git a/components/esp_driver_parlio/src/parlio_common.c b/components/esp_driver_parlio/src/parlio_common.c index 1f3de27658f..3078d400ce3 100644 --- a/components/esp_driver_parlio/src/parlio_common.c +++ b/components/esp_driver_parlio/src/parlio_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,7 +34,7 @@ parlio_group_t *parlio_acquire_group_handle(int group_id) parlio_ll_reset_register(group_id); } #if PARLIO_USE_RETENTION_LINK - sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module; + sleep_retention_module_t module_id = parlio_retention_infos[group_id].retention_module; sleep_retention_module_init_param_t init_param = { .cbs = { .create = { @@ -92,7 +92,7 @@ void parlio_release_group_handle(parlio_group_t *group) if (do_deinitialize) { #if PARLIO_USE_RETENTION_LINK - const periph_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module; + const periph_retention_module_t module_id = parlio_retention_infos[group_id].retention_module; if (sleep_retention_is_module_created(module_id)) { assert(sleep_retention_is_module_inited(module_id)); sleep_retention_module_free(module_id); @@ -167,9 +167,9 @@ esp_err_t parlio_create_sleep_retention_link_cb(void *arg) { parlio_group_t *group = (parlio_group_t *)arg; int group_id = group->group_id; - sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module; - esp_err_t err = sleep_retention_entries_create(parlio_reg_retention_info[group_id].regdma_entry_array, - parlio_reg_retention_info[group_id].array_size, + sleep_retention_module_t module_id = parlio_retention_infos[group_id].retention_module; + esp_err_t err = sleep_retention_entries_create(parlio_retention_infos[group_id].regdma_entry_array, + parlio_retention_infos[group_id].array_size, REGDMA_LINK_PRI_PARLIO, module_id); ESP_RETURN_ON_ERROR(err, TAG, "create retention link failed"); return ESP_OK; @@ -178,7 +178,7 @@ esp_err_t parlio_create_sleep_retention_link_cb(void *arg) void parlio_create_retention_module(parlio_group_t *group) { int group_id = group->group_id; - sleep_retention_module_t module_id = parlio_reg_retention_info[group_id].retention_module; + sleep_retention_module_t module_id = parlio_retention_infos[group_id].retention_module; _lock_acquire(&s_platform.mutex); if (sleep_retention_is_module_inited(module_id) && !sleep_retention_is_module_created(module_id)) { diff --git a/components/esp_driver_parlio/src/parlio_priv.h b/components/esp_driver_parlio/src/parlio_priv.h index 8d3cd59e177..142c5bf49c8 100644 --- a/components/esp_driver_parlio/src/parlio_priv.h +++ b/components/esp_driver_parlio/src/parlio_priv.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,6 +71,16 @@ // Use retention link only when the target supports sleep retention is enabled #define PARLIO_USE_RETENTION_LINK (SOC_PARLIO_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP) +#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION +typedef struct { + const periph_retention_module_t retention_module; + const regdma_entries_config_t *regdma_entry_array; + uint32_t array_size; +} parlio_retention_desc_t; + +extern const parlio_retention_desc_t parlio_retention_infos[PARLIO_LL_GET(INST_NUM)]; +#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION + #define PARLIO_DMA_DESCRIPTOR_BUFFER_MAX_SIZE 4095 #if defined(SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS) // Parlio uses GDMA diff --git a/components/esp_hal_parlio/esp32c5/parlio_periph.c b/components/esp_hal_parlio/esp32c5/parlio_periph.c index 73bd7e51bd2..0fb22c7f00d 100644 --- a/components/esp_hal_parlio/esp32c5/parlio_periph.c +++ b/components/esp_hal_parlio/esp32c5/parlio_periph.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -47,33 +48,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG - * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG - * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 8 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) - }, \ -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/esp32c6/parlio_periph.c b/components/esp_hal_parlio/esp32c6/parlio_periph.c index 182e8b08223..36c2d3929e9 100644 --- a/components/esp_hal_parlio/esp32c6/parlio_periph.c +++ b/components/esp_hal_parlio/esp32c6/parlio_periph.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -63,31 +64,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Configuration registers, e.g.: PARL_IO_RX_CFG0_REG, PARL_IO_RX_CFG1_REG, PARL_IO_TX_CFG0_REG, PARL_IO_TX_CFG1_REG, PARL_IO_CLK_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 6 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x2f, 0x0, 0x100, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) - }, \ -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/esp32h2/parlio_periph.c b/components/esp_hal_parlio/esp32h2/parlio_periph.c index 5d27330c526..1c2d5133511 100644 --- a/components/esp_hal_parlio/esp32h2/parlio_periph.c +++ b/components/esp_hal_parlio/esp32h2/parlio_periph.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -47,33 +48,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG - * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG - * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 8 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) - }, \ -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/esp32h21/parlio_periph.c b/components/esp_hal_parlio/esp32h21/parlio_periph.c index 32ebbefb9e7..f5848133dbb 100644 --- a/components/esp_hal_parlio/esp32h21/parlio_periph.c +++ b/components/esp_hal_parlio/esp32h21/parlio_periph.c @@ -6,6 +6,7 @@ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -47,31 +48,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG - * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG - * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 8 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) - }, \ -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/esp32h4/parlio_periph.c b/components/esp_hal_parlio/esp32h4/parlio_periph.c index 91c0b2fa0e9..911ea62b186 100644 --- a/components/esp_hal_parlio/esp32h4/parlio_periph.c +++ b/components/esp_hal_parlio/esp32h4/parlio_periph.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -47,33 +48,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG - * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG - * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 8 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), \ - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, \ - PARLIO_RETENTION_REGS_CNT, 0, 0, \ - parlio_regs_map[0], parlio_regs_map[1], \ - parlio_regs_map[2], parlio_regs_map[3]), \ - .owner = ENTRY(0) | ENTRY(2) - }, \ -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/esp32p4/parlio_periph.c b/components/esp_hal_parlio/esp32p4/parlio_periph.c index be359819b0f..952dd4dacb8 100644 --- a/components/esp_hal_parlio/esp32p4/parlio_periph.c +++ b/components/esp_hal_parlio/esp32p4/parlio_periph.c @@ -1,11 +1,12 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include "hal/parlio_periph.h" #include "soc/gpio_sig_map.h" +#include "soc/interrupts.h" const soc_parlio_signal_desc_t soc_parlio_signals[1] = { [0] = { @@ -63,33 +64,3 @@ const soc_parlio_signal_desc_t soc_parlio_signals[1] = { } } }; - -/** - * PARLIO Registers to be saved during sleep retention - * - Tx Configuration registers, e.g.: PARL_IO_TX_DATA_CFG_REG, PARL_IO_TX_GENRL_CFG_REG - * - Rx Configuration registers, e.g.: PARL_IO_RX_MODE_CFG_REG, PARL_IO_RX_DATA_CFG_REG, PARL_IO_RX_GENRL_CFG_REG - * - CLK Configuration registers, e.g.: PARL_IO_RX_CLK_CFG_REG, PARL_IO_TX_CLK_CFG_REG - * - Interrupt enable registers, e.g.: PARL_IO_INT_ENA_REG -*/ -#define PARLIO_RETENTION_REGS_CNT 8 -#define PARLIO_RETENTION_REGS_BASE (DR_REG_PARL_IO_BASE + 0x0) -static const uint32_t parlio_regs_map[4] = {0x60457, 0x0, 0x0, 0x0}; -static const regdma_entries_config_t parlio_regs_retention[] = { - // backup stage: save configuration registers - // restore stage: restore the configuration registers - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PARLIO_LINK(0x00), - PARLIO_RETENTION_REGS_BASE, PARLIO_RETENTION_REGS_BASE, - PARLIO_RETENTION_REGS_CNT, 0, 0, - parlio_regs_map[0], parlio_regs_map[1], - parlio_regs_map[2], parlio_regs_map[3]), - .owner = ENTRY(0) - }, -}; -const parlio_reg_retention_info_t parlio_reg_retention_info[1] = { - [0] = { - .regdma_entry_array = parlio_regs_retention, - .array_size = ARRAY_SIZE(parlio_regs_retention), - .retention_module = SLEEP_RETENTION_MODULE_PARLIO0 - }, -}; diff --git a/components/esp_hal_parlio/include/hal/parlio_periph.h b/components/esp_hal_parlio/include/hal/parlio_periph.h index 1059cae525f..5610b8fc865 100644 --- a/components/esp_hal_parlio/include/hal/parlio_periph.h +++ b/components/esp_hal_parlio/include/hal/parlio_periph.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,16 +8,11 @@ #include #include "soc/soc_caps.h" -#include "soc/periph_defs.h" #if SOC_PARLIO_SUPPORTED #include "soc/parl_io_reg.h" #include "soc/parl_io_struct.h" #include "hal/parlio_ll.h" #endif -#include "soc/regdma.h" -#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION -#include "soc/retention_periph_defs.h" -#endif #ifdef __cplusplus extern "C" { @@ -43,16 +38,6 @@ typedef struct { extern const soc_parlio_signal_desc_t soc_parlio_signals[PARLIO_LL_GET(INST_NUM)]; -#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION -typedef struct { - const periph_retention_module_t retention_module; - const regdma_entries_config_t *regdma_entry_array; - uint32_t array_size; -} parlio_reg_retention_info_t; - -extern const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)]; -#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION - #endif #ifdef __cplusplus diff --git a/components/soc/esp32h21/register/soc/parl_io_reg.h b/components/soc/esp32h21/register/soc/parl_io_reg.h index 802b7a6ce43..c5badd49cbc 100644 --- a/components/soc/esp32h21/register/soc/parl_io_reg.h +++ b/components/soc/esp32h21/register/soc/parl_io_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -13,7 +13,7 @@ extern "C" { /** PARL_IO_RX_MODE_CFG_REG register * Parallel RX Sampling mode configuration register. */ -#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_BASE + 0x0) +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) /** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; * Configures rx external enable signal selection from IO PAD. */ @@ -62,7 +62,7 @@ extern "C" { /** PARL_IO_RX_DATA_CFG_REG register * Parallel RX data configuration register. */ -#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x4) +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) /** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; * Configures expected byte number of received data. */ @@ -92,7 +92,7 @@ extern "C" { /** PARL_IO_RX_GENRL_CFG_REG register * Parallel RX general configuration register. */ -#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x8) +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) /** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; * Write 1 to enable the clock gating of output rx clock. */ @@ -126,7 +126,7 @@ extern "C" { /** PARL_IO_RX_START_CFG_REG register * Parallel RX Start configuration register. */ -#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_BASE + 0xc) +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) /** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; * Write 1 to start rx data sampling. */ @@ -138,7 +138,7 @@ extern "C" { /** PARL_IO_TX_DATA_CFG_REG register * Parallel TX data configuration register. */ -#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x10) +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) /** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; * Configures expected byte number of sent data. */ @@ -168,7 +168,7 @@ extern "C" { /** PARL_IO_TX_START_CFG_REG register * Parallel TX Start configuration register. */ -#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_BASE + 0x14) +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) /** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; * Write 1 to start tx data transmit. */ @@ -180,7 +180,7 @@ extern "C" { /** PARL_IO_TX_GENRL_CFG_REG register * Parallel TX general configuration register. */ -#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x18) +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) /** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0; * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. * 1'b1: eof generated by DMA eof. @@ -214,7 +214,7 @@ extern "C" { /** PARL_IO_FIFO_CFG_REG register * Parallel IO FIFO configuration register. */ -#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_BASE + 0x1c) +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) /** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; * Write 1 to reset async fifo in tx module. */ @@ -233,7 +233,7 @@ extern "C" { /** PARL_IO_REG_UPDATE_REG register * Parallel IO FIFO configuration register. */ -#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_BASE + 0x20) +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) /** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; * Write 1 to update rx register configuration. */ @@ -245,7 +245,7 @@ extern "C" { /** PARL_IO_ST_REG register * Parallel IO module status register0. */ -#define PARL_IO_ST_REG (DR_REG_PARL_BASE + 0x24) +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) /** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; * Represents the status that tx is ready to transmit. */ @@ -257,7 +257,7 @@ extern "C" { /** PARL_IO_INT_ENA_REG register * Parallel IO interrupt enable signal configuration register. */ -#define PARL_IO_INT_ENA_REG (DR_REG_PARL_BASE + 0x28) +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; * Write 1 to enable TX_FIFO_REMPTY_INT. */ @@ -283,7 +283,7 @@ extern "C" { /** PARL_IO_INT_RAW_REG register * Parallel IO interrupt raw signal status register. */ -#define PARL_IO_INT_RAW_REG (DR_REG_PARL_BASE + 0x2c) +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status of TX_FIFO_REMPTY_INT. */ @@ -309,7 +309,7 @@ extern "C" { /** PARL_IO_INT_ST_REG register * Parallel IO interrupt signal status register. */ -#define PARL_IO_INT_ST_REG (DR_REG_PARL_BASE + 0x30) +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status of TX_FIFO_REMPTY_INT. */ @@ -335,7 +335,7 @@ extern "C" { /** PARL_IO_INT_CLR_REG register * Parallel IO interrupt clear signal configuration register. */ -#define PARL_IO_INT_CLR_REG (DR_REG_PARL_BASE + 0x34) +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear TX_FIFO_REMPTY_INT. */ @@ -361,7 +361,7 @@ extern "C" { /** PARL_IO_RX_ST0_REG register * Parallel IO RX status register0 */ -#define PARL_IO_RX_ST0_REG (DR_REG_PARL_BASE + 0x38) +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) /** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0; * Indicates the cycle number of reading Rx FIFO. */ @@ -380,7 +380,7 @@ extern "C" { /** PARL_IO_RX_ST1_REG register * Parallel IO RX status register1 */ -#define PARL_IO_RX_ST1_REG (DR_REG_PARL_BASE + 0x3c) +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) /** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; * Indicates the current read bit number from Rx FIFO. */ @@ -392,7 +392,7 @@ extern "C" { /** PARL_IO_TX_ST0_REG register * Parallel IO TX status register0 */ -#define PARL_IO_TX_ST0_REG (DR_REG_PARL_BASE + 0x40) +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) /** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; * Indicates the cycle number of reading Tx FIFO. */ @@ -411,7 +411,7 @@ extern "C" { /** PARL_IO_RX_CLK_CFG_REG register * Parallel IO RX clk configuration register */ -#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x44) +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) /** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; * Write 1 to invert the input Rx core clock. */ @@ -430,7 +430,7 @@ extern "C" { /** PARL_IO_TX_CLK_CFG_REG register * Parallel IO TX clk configuration register */ -#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x48) +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) /** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; * Write 1 to invert the input Tx core clock. */ @@ -449,7 +449,7 @@ extern "C" { /** PARL_IO_CLK_REG register * Parallel IO clk configuration register */ -#define PARL_IO_CLK_REG (DR_REG_PARL_BASE + 0x120) +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) /** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; * Force clock on for this register file */ @@ -461,7 +461,7 @@ extern "C" { /** PARL_IO_VERSION_REG register * Version register. */ -#define PARL_IO_VERSION_REG (DR_REG_PARL_BASE + 0x3fc) +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) /** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 35725920; * Version of this register file */ diff --git a/components/soc/esp32h4/register/soc/parl_io_reg.h b/components/soc/esp32h4/register/soc/parl_io_reg.h index 524d09ec2e5..822d929b5cf 100644 --- a/components/soc/esp32h4/register/soc/parl_io_reg.h +++ b/components/soc/esp32h4/register/soc/parl_io_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 OR MIT */ @@ -13,7 +13,7 @@ extern "C" { /** PARL_IO_RX_MODE_CFG_REG register * Parallel RX Sampling mode configuration register. */ -#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_BASE + 0x0) +#define PARL_IO_RX_MODE_CFG_REG (DR_REG_PARL_IO_BASE + 0x0) /** PARL_IO_RX_EXT_EN_SEL : R/W; bitpos: [24:21]; default: 7; * Configures rx external enable signal selection from IO PAD. */ @@ -62,7 +62,7 @@ extern "C" { /** PARL_IO_RX_DATA_CFG_REG register * Parallel RX data configuration register. */ -#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x4) +#define PARL_IO_RX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x4) /** PARL_IO_RX_BITLEN : R/W; bitpos: [27:9]; default: 0; * Configures expected byte number of received data. */ @@ -92,7 +92,7 @@ extern "C" { /** PARL_IO_RX_GENRL_CFG_REG register * Parallel RX general configuration register. */ -#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x8) +#define PARL_IO_RX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x8) /** PARL_IO_RX_GATING_EN : R/W; bitpos: [12]; default: 0; * Write 1 to enable the clock gating of output rx clock. */ @@ -126,7 +126,7 @@ extern "C" { /** PARL_IO_RX_START_CFG_REG register * Parallel RX Start configuration register. */ -#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_BASE + 0xc) +#define PARL_IO_RX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0xc) /** PARL_IO_RX_START : R/W; bitpos: [31]; default: 0; * Write 1 to start rx data sampling. */ @@ -138,7 +138,7 @@ extern "C" { /** PARL_IO_TX_DATA_CFG_REG register * Parallel TX data configuration register. */ -#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_BASE + 0x10) +#define PARL_IO_TX_DATA_CFG_REG (DR_REG_PARL_IO_BASE + 0x10) /** PARL_IO_TX_BITLEN : R/W; bitpos: [27:9]; default: 0; * Configures expected byte number of sent data. */ @@ -168,7 +168,7 @@ extern "C" { /** PARL_IO_TX_START_CFG_REG register * Parallel TX Start configuration register. */ -#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_BASE + 0x14) +#define PARL_IO_TX_START_CFG_REG (DR_REG_PARL_IO_BASE + 0x14) /** PARL_IO_TX_START : R/W; bitpos: [31]; default: 0; * Write 1 to start tx data transmit. */ @@ -180,7 +180,7 @@ extern "C" { /** PARL_IO_TX_GENRL_CFG_REG register * Parallel TX general configuration register. */ -#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_BASE + 0x18) +#define PARL_IO_TX_GENRL_CFG_REG (DR_REG_PARL_IO_BASE + 0x18) /** PARL_IO_TX_EOF_GEN_SEL : R/W; bitpos: [13]; default: 0; * Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. * 1'b1: eof generated by DMA eof. @@ -214,7 +214,7 @@ extern "C" { /** PARL_IO_FIFO_CFG_REG register * Parallel IO FIFO configuration register. */ -#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_BASE + 0x1c) +#define PARL_IO_FIFO_CFG_REG (DR_REG_PARL_IO_BASE + 0x1c) /** PARL_IO_TX_FIFO_SRST : R/W; bitpos: [30]; default: 0; * Write 1 to reset async fifo in tx module. */ @@ -233,7 +233,7 @@ extern "C" { /** PARL_IO_REG_UPDATE_REG register * Parallel IO FIFO configuration register. */ -#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_BASE + 0x20) +#define PARL_IO_REG_UPDATE_REG (DR_REG_PARL_IO_BASE + 0x20) /** PARL_IO_RX_REG_UPDATE : WT; bitpos: [31]; default: 0; * Write 1 to update rx register configuration. */ @@ -245,7 +245,7 @@ extern "C" { /** PARL_IO_ST_REG register * Parallel IO module status register0. */ -#define PARL_IO_ST_REG (DR_REG_PARL_BASE + 0x24) +#define PARL_IO_ST_REG (DR_REG_PARL_IO_BASE + 0x24) /** PARL_IO_TX_READY : RO; bitpos: [31]; default: 0; * Represents the status that tx is ready to transmit. */ @@ -257,7 +257,7 @@ extern "C" { /** PARL_IO_INT_ENA_REG register * Parallel IO interrupt enable signal configuration register. */ -#define PARL_IO_INT_ENA_REG (DR_REG_PARL_BASE + 0x28) +#define PARL_IO_INT_ENA_REG (DR_REG_PARL_IO_BASE + 0x28) /** PARL_IO_TX_FIFO_REMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; * Write 1 to enable TX_FIFO_REMPTY_INT. */ @@ -283,7 +283,7 @@ extern "C" { /** PARL_IO_INT_RAW_REG register * Parallel IO interrupt raw signal status register. */ -#define PARL_IO_INT_RAW_REG (DR_REG_PARL_BASE + 0x2c) +#define PARL_IO_INT_RAW_REG (DR_REG_PARL_IO_BASE + 0x2c) /** PARL_IO_TX_FIFO_REMPTY_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; * The raw interrupt status of TX_FIFO_REMPTY_INT. */ @@ -309,7 +309,7 @@ extern "C" { /** PARL_IO_INT_ST_REG register * Parallel IO interrupt signal status register. */ -#define PARL_IO_INT_ST_REG (DR_REG_PARL_BASE + 0x30) +#define PARL_IO_INT_ST_REG (DR_REG_PARL_IO_BASE + 0x30) /** PARL_IO_TX_FIFO_REMPTY_INT_ST : RO; bitpos: [0]; default: 0; * The masked interrupt status of TX_FIFO_REMPTY_INT. */ @@ -335,7 +335,7 @@ extern "C" { /** PARL_IO_INT_CLR_REG register * Parallel IO interrupt clear signal configuration register. */ -#define PARL_IO_INT_CLR_REG (DR_REG_PARL_BASE + 0x34) +#define PARL_IO_INT_CLR_REG (DR_REG_PARL_IO_BASE + 0x34) /** PARL_IO_TX_FIFO_REMPTY_INT_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear TX_FIFO_REMPTY_INT. */ @@ -361,7 +361,7 @@ extern "C" { /** PARL_IO_RX_ST0_REG register * Parallel IO RX status register0 */ -#define PARL_IO_RX_ST0_REG (DR_REG_PARL_BASE + 0x38) +#define PARL_IO_RX_ST0_REG (DR_REG_PARL_IO_BASE + 0x38) /** PARL_IO_RX_CNT : RO; bitpos: [12:8]; default: 0; * Indicates the cycle number of reading Rx FIFO. */ @@ -380,7 +380,7 @@ extern "C" { /** PARL_IO_RX_ST1_REG register * Parallel IO RX status register1 */ -#define PARL_IO_RX_ST1_REG (DR_REG_PARL_BASE + 0x3c) +#define PARL_IO_RX_ST1_REG (DR_REG_PARL_IO_BASE + 0x3c) /** PARL_IO_RX_FIFO_RD_BIT_CNT : RO; bitpos: [31:13]; default: 0; * Indicates the current read bit number from Rx FIFO. */ @@ -392,7 +392,7 @@ extern "C" { /** PARL_IO_TX_ST0_REG register * Parallel IO TX status register0 */ -#define PARL_IO_TX_ST0_REG (DR_REG_PARL_BASE + 0x40) +#define PARL_IO_TX_ST0_REG (DR_REG_PARL_IO_BASE + 0x40) /** PARL_IO_TX_CNT : RO; bitpos: [12:6]; default: 0; * Indicates the cycle number of reading Tx FIFO. */ @@ -411,7 +411,7 @@ extern "C" { /** PARL_IO_RX_CLK_CFG_REG register * Parallel IO RX clk configuration register */ -#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x44) +#define PARL_IO_RX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x44) /** PARL_IO_RX_CLK_I_INV : R/W; bitpos: [30]; default: 0; * Write 1 to invert the input Rx core clock. */ @@ -430,7 +430,7 @@ extern "C" { /** PARL_IO_TX_CLK_CFG_REG register * Parallel IO TX clk configuration register */ -#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_BASE + 0x48) +#define PARL_IO_TX_CLK_CFG_REG (DR_REG_PARL_IO_BASE + 0x48) /** PARL_IO_TX_CLK_I_INV : R/W; bitpos: [30]; default: 0; * Write 1 to invert the input Tx core clock. */ @@ -449,7 +449,7 @@ extern "C" { /** PARL_IO_TX_CS_CFG_REG register * Parallel IO tx_cs_o generate configuration */ -#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_BASE + 0x4c) +#define PARL_IO_TX_CS_CFG_REG (DR_REG_PARL_IO_BASE + 0x4c) /** PARL_IO_TX_CS_STOP_DELAY : R/W; bitpos: [15:0]; default: 0; * configure the delay between data tx end and tx_cs_o posedge */ @@ -468,7 +468,7 @@ extern "C" { /** PARL_IO_CLK_REG register * Parallel IO clk configuration register */ -#define PARL_IO_CLK_REG (DR_REG_PARL_BASE + 0x120) +#define PARL_IO_CLK_REG (DR_REG_PARL_IO_BASE + 0x120) /** PARL_IO_CLK_EN : R/W; bitpos: [31]; default: 0; * Force clock on for this register file */ @@ -480,7 +480,7 @@ extern "C" { /** PARL_IO_VERSION_REG register * Version register. */ -#define PARL_IO_VERSION_REG (DR_REG_PARL_BASE + 0x3fc) +#define PARL_IO_VERSION_REG (DR_REG_PARL_IO_BASE + 0x3fc) /** PARL_IO_DATE : R/W; bitpos: [27:0]; default: 37786160; * Version of this register file */