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refactor(isp): avoid isp ll functions using hal.hw before initialization

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This commit is contained in:
gaoxu
2026-04-24 11:05:01 +08:00
parent afd5c10bfd
commit ee198b507d
2 changed files with 9 additions and 14 deletions
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components/esp_driver_isp/src/isp_core.c
+5 -5
View File
@@ -46,8 +46,8 @@ static esp_err_t s_isp_claim_processor(isp_processor_t *proc)
s_platform.processors[i] = proc;
proc->proc_id = i;
PERIPH_RCC_ATOMIC() {
isp_ll_enable_module_clock(proc->hal.hw, true);
isp_ll_reset_module_clock(proc->hal.hw);
isp_ll_enable_module_clock(true);
isp_ll_reset_module_clock();
}
break;
}
@@ -67,7 +67,7 @@ static esp_err_t s_isp_declaim_processor(isp_processor_t *proc)
_lock_acquire(&s_platform.mutex);
s_platform.processors[proc->proc_id] = NULL;
PERIPH_RCC_ATOMIC() {
isp_ll_enable_module_clock(proc->hal.hw, false);
isp_ll_enable_module_clock(false);
}
_lock_release(&s_platform.mutex);
@@ -118,8 +118,8 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_
}
ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed");
PERIPH_RCC_ATOMIC() {
isp_ll_select_clk_source(proc->hal.hw, clk_src);
isp_ll_set_clock_div(proc->hal.hw, &clk_div);
isp_ll_select_clk_source(clk_src);
isp_ll_set_clock_div(&clk_div);
}
isp_hal_init(&proc->hal, proc->proc_id);
components/hal/esp32p4/include/hal/isp_ll.h
+4 -9
View File
@@ -252,10 +252,9 @@ typedef enum {
/**
* @brief Enable the bus clock for ISP module
*
* @param hw Hardware instance address
* @param en enable / disable
*/
static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
static inline void isp_ll_enable_module_clock(bool en)
{
HP_SYS_CLKRST.peri_clk_ctrl25.reg_isp_clk_en = en;
}
@@ -266,10 +265,8 @@ static inline void isp_ll_enable_module_clock(isp_dev_t *hw, bool en)
/**
* @brief Reset the ISP module
*
* @param hw Hardware instance address
*/
static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
static inline void isp_ll_reset_module_clock(void)
{
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 1;
HP_SYS_CLKRST.hp_rst_en0.reg_rst_en_isp = 0;
@@ -282,10 +279,9 @@ static inline void isp_ll_reset_module_clock(isp_dev_t *hw)
/**
* @brief Select ISP clock source
*
* @param hw Hardware instance address
* @param clk_src clock source, see valid sources in type `soc_periph_isp_clk_src_t`
*/
static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_src_t clk_src)
static inline void isp_ll_select_clk_source(soc_periph_isp_clk_src_t clk_src)
{
uint32_t clk_val = 0;
switch (clk_src) {
@@ -313,10 +309,9 @@ static inline void isp_ll_select_clk_source(isp_dev_t *hw, soc_periph_isp_clk_sr
/**
* @brief Set ISP clock div
*
* @param hw Hardware instance address
* @param div Clock division with integral and decimal part
*/
static inline void isp_ll_set_clock_div(isp_dev_t *hw, const hal_utils_clk_div_t *clk_div)
static inline void isp_ll_set_clock_div(const hal_utils_clk_div_t *clk_div)
{
HAL_ASSERT(clk_div->integer > 0 && clk_div->integer <= ISP_LL_TX_MAX_CLK_INT_DIV);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl26, reg_isp_clk_div_num, clk_div->integer - 1);