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feat(asrc): Support asrc hal on esp32s31

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Closes IDF-14564
This commit is contained in:
Ma Jing Jing
2026-03-16 10:19:21 +08:00
parent b1d68624e1
commit eb9ecfd4ec
7 changed files with 697 additions and 435 deletions
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70
components/esp_hal_asrc/esp32s31/asrc_hal.c Normal file
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include "hal/asrc_ll.h"
#include "hal/asrc_hal.h"
void asrc_hal_init(asrc_hal_context_t *hal)
{
hal->dev = ASRC_LL_GET_HW();
}
void asrc_hal_enable_asrc_module(asrc_hal_context_t *hal, bool enable)
{
asrc_ll_enable_asrc_module(enable);
}
void asrc_hal_init_stream(asrc_hal_context_t *hal, asrc_hal_config_t *asrc_cfg, uint8_t asrc_idx)
{
asrc_ll_stop_stream(hal->dev, asrc_idx);
asrc_ll_reset_stream(hal->dev, asrc_idx);
asrc_ll_reset_input_fifo(hal->dev, asrc_idx);
asrc_ll_reset_output_fifo(hal->dev, asrc_idx);
asrc_ll_set_channel_mode(hal->dev, asrc_idx, asrc_cfg->src_info.channel,
asrc_cfg->dest_info.channel, asrc_cfg->weight, asrc_cfg->weight_len);
asrc_ll_set_rate_reg(hal->dev, asrc_idx, asrc_cfg->src_info.sample_rate, asrc_cfg->dest_info.sample_rate);
asrc_ll_clear_incnt_counter(hal->dev, asrc_idx);
asrc_ll_clear_outcnt_counter(hal->dev, asrc_idx);
asrc_ll_enable_outcnt_counter(hal->dev, asrc_idx);
asrc_ll_set_eof_mode(hal->dev, asrc_idx, 0);
asrc_ll_enable_outsample_comp(hal->dev, asrc_idx);
}
void asrc_hal_deinit_stream(asrc_hal_context_t *hal, uint8_t asrc_idx)
{
asrc_ll_stop_stream(hal->dev, asrc_idx);
asrc_ll_reset_stream(hal->dev, asrc_idx);
asrc_ll_reset_input_fifo(hal->dev, asrc_idx);
asrc_ll_reset_output_fifo(hal->dev, asrc_idx);
asrc_ll_clear_incnt_counter(hal->dev, asrc_idx);
asrc_ll_clear_outcnt_counter(hal->dev, asrc_idx);
}
void asrc_hal_set_in_bytes_num(asrc_hal_context_t *hal, uint8_t asrc_idx, uint32_t in_bytes_num)
{
asrc_ll_set_in_bytes_num(hal->dev, asrc_idx, in_bytes_num);
}
void asrc_hal_set_out_bytes_num(asrc_hal_context_t *hal, uint8_t asrc_idx, uint32_t out_bytes_num)
{
asrc_ll_set_out_bytes_num(hal->dev, asrc_idx, out_bytes_num);
}
void asrc_hal_start(asrc_hal_context_t *hal, uint8_t asrc_idx)
{
asrc_ll_start_stream(hal->dev, asrc_idx);
}
uint32_t asrc_hal_get_out_data_bytes(asrc_hal_context_t *hal, uint8_t asrc_idx)
{
return asrc_ll_get_outbytes_cnt(hal->dev, asrc_idx);
}
void asrc_hal_deinit(asrc_hal_context_t *hal)
{
hal->dev = NULL;
}

63
components/esp_hal_asrc/esp32s31/asrc_periph.c Normal file
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/asrc_periph.h"
/**
* @brief ASRC rate conversion configuration lookup table
* Table structure: asrc_periph_rate_table[src_rate_index][dest_rate_index]
* Rate index mapping: 0=8kHz, 1=16kHz, 2=24kHz, 3=32kHz, 4=44.1kHz, 5=48kHz
*/
const asrc_periph_rate_config_t asrc_periph_rate_table[6][6] = {
{
{1, 1, 1, 0, 0, 0, 0, 0, 0}, // 8k->8k (bypass)
{1, 0, 1, 0, 0, 0, 0, 0, 0}, // 8k->16k (up_2)
{0, 0, 0, 0, 0, 0, 4, 3, (int)(((1 << 20) + 3) / (2 * 3))}, // 8k->32k->24k (up_4 + frac: 4/3)
{0, 0, 1, 0, 0, 0, 0, 0, 0}, // 8k->32k (up_4)
{0, 0, 0, 0, 0, 0, 320, 441, (int)(((1 << 20) + 441) / (2 * 441))}, // 8k->32k->44.1k (up_4 + frac: 320/441)
{0, 0, 0, 0, 0, 0, 2, 3, (int)(((1 << 20) + 3) / (2 * 3))} // 8k->32k->48k (up_4 + frac: 2/3)
},
{
{1, 0, 1, 0, 1, 0, 0, 0, 0}, // 16k->8k (down_2)
{1, 1, 1, 0, 0, 0, 0, 0, 0}, // 16k->16k (bypass)
{1, 0, 0, 0, 0, 0, 4, 3, (int)(((1 << 20) + 3) / (2 * 3))}, // 16k->32k->24k (up_2 + frac: 4/3)
{1, 0, 1, 0, 0, 0, 0, 0, 0}, // 16k->32k (up_2)
{1, 0, 0, 0, 0, 0, 320, 441, (int)(((1 << 20) + 441) / (2 * 441))}, // 16k->32k->44.1k (up_2 + frac: 320/441)
{1, 0, 0, 0, 0, 0, 2, 3, (int)(((1 << 20) + 3) / (2 * 3))} // 16k->32k->48k (up_2 + frac: 2/3)
},
{
{0, 0, 0, 1, 1, 1, 3, 4, (int)(((1 << 20) + 4) / (2 * 4))}, // 24k->32k->8k (frac: 3/4 + down_4)
{1, 0, 0, 0, 1, 1, 3, 4, (int)(((1 << 20) + 4) / (2 * 4))}, // 24k->32k->16k (frac: 3/4 + down_2)
{1, 1, 1, 0, 0, 0, 0, 0, 0}, // 24k->24k (bypass)
{1, 1, 0, 0, 0, 1, 3, 4, (int)(((1 << 20) + 4) / (2 * 4))}, // 24k->32k (frac: 3/4)
{0, 0, 0, 0, 0, 0, 320, 147, (int)(((1 << 20) + 147) / (2 * 147))}, // 24k->96k->44.1k (up_4 + frac: 320/147)
{1, 0, 1, 0, 0, 0, 0, 0, 0} // 24k->48k (up_2)
},
{
{0, 0, 1, 1, 1, 0, 0, 0, 0}, // 32k->8k (down_4)
{1, 0, 1, 0, 1, 0, 0, 0, 0}, // 32k->16k (down_2)
{1, 1, 0, 0, 0, 0, 4, 3, (int)(((1 << 20) + 3) / (2 * 3))}, // 32k->24k (frac: 4/3)
{1, 1, 1, 0, 0, 0, 0, 0, 0}, // 32k->32k (bypass)
{1, 0, 0, 0, 0, 0, 640, 441, (int)(((1 << 20) + 441) / (2 * 441))}, // 32k->64k->44.1k (up_2 + frac: 640/441)
{1, 0, 0, 0, 0, 0, 4, 3, (int)(((1 << 20) + 3) / (2 * 3))} // 32k->64k->48k (up_2 + frac: 4/3)
},
{
{0, 0, 0, 1, 1, 1, 441, 320, (int)(((1 << 20) + 320) / (2 * 320))}, // 44.1k->32k->8k (frac: 441/320 + down_4)
{1, 0, 0, 0, 1, 1, 441, 320, (int)(((1 << 20) + 320) / (2 * 320))}, // 44.1k->32k->16k (frac: 441/320 + down_2)
{0, 0, 0, 1, 1, 1, 147, 320, (int)(((1 << 20) + 320) / (2 * 320))}, // 44.1k->96k->24k (frac: 147/320 + down_4)
{1, 0, 0, 0, 1, 1, 441, 640, (int)(((1 << 20) + 640) / (2 * 640))}, // 44.1k->64k->32k (frac: 441/640 + down_2)
{1, 1, 1, 0, 0, 0, 0, 0, 0}, // 44.1k->44.1k (bypass)
{1, 0, 0, 0, 0, 0, 147, 80, (int)(((1 << 20) + 80) / (2 * 80))} // 44.1k->88.2k->48k (up_2 + frac: 147/80)
},
{
{0, 0, 0, 1, 1, 1, 3, 2, (int)(((1 << 20) + 2) / (2 * 2))}, // 48k->32k->8k (frac: 3/2 + down_4)
{1, 0, 0, 0, 1, 1, 3, 2, (int)(((1 << 20) + 2) / (2 * 2))}, // 48k->32k->16k (frac: 3/2 + down_2)
{1, 0, 1, 0, 1, 0, 0, 0, 0}, // 48k->24k (down_2)
{1, 0, 0, 0, 1, 1, 3, 4, (int)(((1 << 20) + 4) / (2 * 4))}, // 48k->64k->32k (frac: 3/4 + down_2)
{1, 0, 0, 0, 1, 1, 80, 147, (int)(((1 << 20) + 147) / (2 * 147))}, // 48k->88.2k->44.1k (frac: 80/147 + down_2)
{1, 1, 1, 0, 0, 0, 0, 0, 0} // 48k->48k (bypass)
},
};

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components/esp_hal_asrc/esp32s31/include/hal/asrc_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "soc/asrc_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/asrc_periph.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define ASRC_LL_GET_HW() (&ASRC)
#define ASRC_LL_STREAM_NUM (2)
/**
* @brief ASRC interrupt types
*/
typedef enum {
ASRC_LL_INTR_OUTCNT_EOF = (1 << 0), /**< Output counter EOF interrupt */
} asrc_ll_intr_type_t;
/**
* @brief Convert sample rate to table index
*
* @param[in] rate Sample rate in Hz (8000/16000/24000/32000/44100/48000)
*
* @return
* - Table index
* - -1 if rate not supported
*/
static inline int8_t asrc_ll_get_rate_index(uint32_t rate)
{
int32_t idx = rate / 8000;
if (idx == 5) {
return (rate == 44100) ? 4 : -1;
}
if (idx && rate == idx * 8000 && idx <= 6) {
return idx - 1;
}
return -1;
}
/**
* @brief Reset ASRC module
*
* @param[in] hw Peripheral ASRC hardware instance address
*/
static inline void asrc_ll_reset_asrc_module(asrc_dev_t *hw)
{
HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_rst_en = 1;
HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_rst_en = 0;
}
/**
* @brief Enable the bus clock for the ASRC module
*
* @param[in] enable Enable the bus clock
*/
static inline void asrc_ll_enable_asrc_module(bool enable)
{
HP_SYS_CLKRST.ahb_asrc_ctrl0.reg_ahb_asrc_sys_clk_en = enable;
}
/**
* @brief Force enable the register clock for the ASRC module
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] enable Enable the register clock
*/
static inline void asrc_ll_force_enable_reg_clock(asrc_dev_t *hw, bool enable)
{
hw->sys.clk_en = enable;
}
/**
* @brief Reset specific ASRC stream
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_reset_stream(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg3.reset = 1;
hw->asrc_para[asrc_idx].cfg3.reset = 0;
}
/**
* @brief Start ASRC processing
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_start_stream(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg4.start = 1;
}
/**
* @brief Stop ASRC processing
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_stop_stream(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg4.start = 0;
}
/**
* @brief Set ASRC rate register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
* @param[in] src_rate Source sample rate
* @param[in] dest_rate Destination sample rate
*/
static inline void asrc_ll_set_rate_reg(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t src_rate, uint32_t dest_rate)
{
int8_t src_idx = asrc_ll_get_rate_index(src_rate);
int8_t dest_idx = asrc_ll_get_rate_index(dest_rate);
HAL_ASSERT(src_idx != -1 && dest_idx != -1);
const asrc_periph_rate_config_t *config = &asrc_periph_rate_table[src_idx][dest_idx];
hw->asrc_para[asrc_idx].cfg0.rs2_stg0_bypass = config->stg0_bypass;
hw->asrc_para[asrc_idx].cfg0.rs2_stg1_bypass = config->stg1_bypass;
hw->asrc_para[asrc_idx].cfg0.rs2_stg0_mode = config->stg0_mode;
hw->asrc_para[asrc_idx].cfg0.rs2_stg1_mode = config->stg1_mode;
hw->asrc_para[asrc_idx].cfg0.frac_bypass = config->frac_bypass;
hw->asrc_para[asrc_idx].cfg0.frac_ahead = config->frac_ahead;
hw->asrc_para[asrc_idx].cfg1.frac_m = config->frac_m;
hw->asrc_para[asrc_idx].cfg1.frac_l = config->frac_l;
hw->asrc_para[asrc_idx].cfg2.frac_recipl = config->frac_recipl;
}
/**
* @brief Set ASRC channel mode configuration
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
* @param[in] src_ch Source channel number
* @param[in] dest_ch Destination channel number
* @param[in] weight Weight array
* @param[in] weight_len Weight array length
*/
static inline void asrc_ll_set_channel_mode(asrc_dev_t *hw, uint8_t asrc_idx, uint8_t src_ch,
uint8_t dest_ch, float *weight, uint8_t weight_len)
{
if (src_ch == 1 && dest_ch == 1) {
// Mode 0: Mono to Mono (1 channel -> 1 channel)
hw->asrc_para[asrc_idx].cfg0.mode = 0;
} else if (src_ch == 1 && dest_ch == 2) {
// Mode 2: Mono to Dual (1 channel -> 2 channels, duplicate mono channel to both outputs)
hw->asrc_para[asrc_idx].cfg0.mode = 2;
} else if (src_ch == 2 && dest_ch == 1) {
// Mode 3: Dual to Mono (2 channels -> 1 channel)
// ch_sel determines channel selection: 0 = select channel 0 only, 1 = mix both channels
HAL_ASSERT(weight_len == 2);
uint32_t ch_sel = (weight[0] == 1.0f && weight[1] == 0.0f) ? 0 : 1;
hw->asrc_para[asrc_idx].cfg0.mode = 3;
hw->asrc_para[asrc_idx].cfg0.sel = ch_sel;
} else {
// Mode 1: Dual to Dual (2 channels -> 2 channels)
hw->asrc_para[asrc_idx].cfg0.mode = 1;
}
}
/**
* @brief Clear input samples counter register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_clear_incnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg5.in_cnt_clr = 1;
}
/**
* @brief Enable input samples counter register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_enable_incnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg5.in_cnt_ena = 1;
}
/**
* @brief Set expected input samples count register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
* @param[in] in_bytes_num Number of input samples expected
*/
static inline void asrc_ll_set_in_bytes_num(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t in_bytes_num)
{
hw->asrc_para[asrc_idx].cfg5.in_samples = in_bytes_num;
}
/**
* @brief Clear output samples counter register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_clear_outcnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg6.out_cnt_clr = 1;
}
/**
* @brief Enable output samples counter register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_enable_outcnt_counter(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg6.out_cnt_ena = 1;
}
/**
* @brief Enable output samples counter compensation register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_enable_outsample_comp(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].cfg6.out_samples_comp = 1;
}
/**
* @brief Set expected output sample count register
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
* @param[in] out_bytes_num Number of output samples expected
*/
static inline void asrc_ll_set_out_bytes_num(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t out_bytes_num)
{
hw->asrc_para[asrc_idx].cfg6.out_samples = out_bytes_num;
}
/**
* @brief Set EOF (End of Frame) generation mode
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
* @param[in] eof_mode EOF generation mode
*/
static inline void asrc_ll_set_eof_mode(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t eof_mode)
{
hw->asrc_para[asrc_idx].cfg6.out_eof_gen_mode = eof_mode;
}
/**
* @brief Reset input fifo
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_reset_input_fifo(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].fifo_ctrl.infifo_reset = 1;
hw->asrc_para[asrc_idx].fifo_ctrl.infifo_reset = 0;
}
/**
* @brief Reset output fifo
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*/
static inline void asrc_ll_reset_output_fifo(asrc_dev_t *hw, uint8_t asrc_idx)
{
hw->asrc_para[asrc_idx].fifo_ctrl.outfifo_reset = 1;
hw->asrc_para[asrc_idx].fifo_ctrl.outfifo_reset = 0;
}
/**
* @brief Enable ASRC interrupt
*
* @param[in] hw Pointer to ASRC hardware.
* @param[in] asrc_idx ASRC stream index
* @param[in] mask Interrupt mask to enable
*/
static inline void asrc_ll_enable_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
{
hw->asrc_para[asrc_idx].int_ena.val |= mask;
}
/**
* @brief Clear ASRC interrupt
*
* @param[in] hw Pointer to ASRC hardware.
* @param[in] asrc_idx ASRC stream index
* @param[in] mask Interrupt mask to clear
*/
static inline void asrc_ll_clear_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
{
hw->asrc_para[asrc_idx].int_clr.val = mask;
}
/**
* @brief Disable ASRC interrupt
*
* @param[in] hw Pointer to ASRC hardware.
* @param[in] asrc_idx ASRC stream index
* @param[in] mask Interrupt mask to disable
*/
static inline void asrc_ll_disable_intr_mask(asrc_dev_t *hw, uint8_t asrc_idx, uint32_t mask)
{
hw->asrc_para[asrc_idx].int_ena.val &= (~mask);
}
/**
* @brief Get ASRC interrupt status
*
* @param[in] hw Pointer to ASRC hardware.
* @param[in] asrc_idx ASRC stream index
*
* @return
* - Interrupt status (masked)
*/
static inline uint32_t asrc_ll_get_intr_status(asrc_dev_t *hw, uint8_t asrc_idx)
{
return hw->asrc_para[asrc_idx].int_st.val;
}
/**
* @brief Get current output sample count
*
* @param[in] hw Peripheral ASRC hardware instance address
* @param[in] asrc_idx ASRC stream index
*
* @return
* - Current output samples count
*/
static inline uint32_t asrc_ll_get_outbytes_cnt(asrc_dev_t *hw, uint8_t asrc_idx)
{
uint32_t out_cnt = hw->asrc_para[asrc_idx].out_cnt.out_cnt;
return out_cnt;
}
#ifdef __cplusplus
}
#endif /* __cplusplus */

52
components/esp_hal_asrc/esp32s31/include/hal/asrc_periph.h Normal file
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@@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
* @brief ASRC rate conversion register configuration structure
*/
typedef struct {
uint32_t stg1_bypass; /*!< Stage 1 bypass control
- 0: Enable stage 1 processing
- 1: Bypass stage 1 (pass-through) */
uint32_t stg0_bypass; /*!< Stage 0 bypass control
- 0: Enable stage 0 processing
- 1: Bypass stage 0 (pass-through) */
uint32_t frac_bypass; /*!< Fractional resampler bypass control
- 0: Enable fractional resampler
- 1: Bypass fractional resampler */
uint32_t stg1_mode; /*!< Stage 1 operation mode
- 1: Down-sampling by 2 (decimation)
- 0: Up-sampling by 2 (interpolation) */
uint32_t stg0_mode; /*!< Stage 0 operation mode
- 1: Down-sampling by 2 (decimation)
- 0: Up-sampling by 2 (interpolation) */
uint32_t frac_ahead; /*!< Fractional resampler advance flag
- 0: Normal operation
- 1: Advance mode (implementation specific) */
uint32_t frac_m; /*!< Fractional resampler numerator
Used in ratio calculation: frac_m/frac_l
Range: Depends on sample rate conversion ratio */
uint32_t frac_l; /*!< Fractional resampler denominator
Used in ratio calculation: frac_m/frac_l
Range: Depends on sample rate conversion ratio */
uint32_t frac_recipl; /*!< Fractional resampler reciprocal value
Pre-calculated reciprocal for hardware efficiency
Formula: ((1 << 20) + frac_l) / (2 * frac_l) */
} asrc_periph_rate_config_t;
extern const asrc_periph_rate_config_t asrc_periph_rate_table[6][6];
#ifdef __cplusplus
}
#endif /* __cplusplus */

4
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
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@@ -1342,3 +1342,7 @@ config SOC_I2S_PDM_MAX_TX_LINES
config SOC_I2S_PDM_MAX_RX_LINES
int
default 4
config SOC_ASRC_SUPPORTED
bool
default y

3
components/soc/esp32s31/include/soc/soc_caps.h
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@@ -539,3 +539,6 @@
#define SOC_I2S_SUPPORTS_TDM (1)
#define SOC_I2S_PDM_MAX_TX_LINES (2) // On I2S0
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
/*---------------------------------- ASRC CAPS ----------------------------------*/
#define SOC_ASRC_SUPPORTED (1)

585
components/soc/esp32s31/register/soc/asrc_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -8,592 +8,320 @@
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */
/** Group: Control and configuration registers */
/** Type of chnl0_cfg0 register
/** Type of cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
/** rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg1_bypass:1;
/** chnl0_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
uint32_t rs2_stg1_bypass : 1;
/** rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel0.
*/
uint32_t chnl0_rs2_stg0_bypass:1;
/** chnl0_frac_bypass : R/W; bitpos: [2]; default: 1;
uint32_t rs2_stg0_bypass : 1;
/** frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel0.
*/
uint32_t chnl0_frac_bypass:1;
/** chnl0_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
uint32_t frac_bypass : 1;
/** rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg1_mode:1;
/** chnl0_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
uint32_t rs2_stg1_mode : 1;
/** rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel0, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl0_rs2_stg0_mode:1;
/** chnl0_frac_ahead : R/W; bitpos: [5]; default: 0;
uint32_t rs2_stg0_mode : 1;
/** frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel0, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl0_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl0_mode : R/W; bitpos: [8:7]; default: 0;
uint32_t frac_ahead : 1;
uint32_t reserved_6 : 1;
/** mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl0_mode:2;
/** chnl0_sel : R/W; bitpos: [9]; default: 0;
uint32_t mode : 2;
/** sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl0_sel:1;
uint32_t reserved_10:22;
uint32_t sel : 1;
uint32_t reserved_10 : 22;
};
uint32_t val;
} asrc_chnl0_cfg0_reg_t;
} asrc_cfg0_reg_t;
/** Type of chnl0_cfg1 register
/** Type of cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_m : R/W; bitpos: [9:0]; default: 0;
/** frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
* channel0, reg_frac_m and reg_frac_l are relatively prime.
*/
uint32_t chnl0_frac_m:10;
/** chnl0_frac_l : R/W; bitpos: [19:10]; default: 0;
uint32_t frac_m : 10;
/** frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel0, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
* channel0, reg_frac_l and reg_frac_m are relatively prime.
*/
uint32_t chnl0_frac_l:10;
uint32_t reserved_20:12;
uint32_t frac_l : 10;
uint32_t reserved_20 : 12;
};
uint32_t val;
} asrc_chnl0_cfg1_reg_t;
} asrc_cfg1_reg_t;
/** Type of chnl0_cfg2 register
/** Type of cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_frac_recipl : R/W; bitpos: [19:0]; default: 0;
/** frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel0.
*/
uint32_t chnl0_frac_recipl:20;
uint32_t reserved_20:12;
uint32_t frac_recipl : 20;
uint32_t reserved_20 : 12;
};
uint32_t val;
} asrc_chnl0_cfg2_reg_t;
} asrc_cfg2_reg_t;
/** Type of chnl0_cfg3 register
/** Type of cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_reset : WT; bitpos: [0]; default: 0;
/** reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel0.
*/
uint32_t chnl0_reset:1;
uint32_t reserved_1:31;
uint32_t reset : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_cfg3_reg_t;
} asrc_cfg3_reg_t;
/** Type of chnl0_cfg4 register
/** Type of cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_start : R/W; bitpos: [0]; default: 0;
/** start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel0.
*/
uint32_t chnl0_start:1;
uint32_t reserved_1:31;
uint32_t start : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_cfg4_reg_t;
} asrc_cfg4_reg_t;
/** Type of chnl0_cfg5 register
/** Type of cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
/** in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in samples counter.
*/
uint32_t chnl0_in_cnt_ena:1;
/** chnl0_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
uint32_t in_cnt_ena : 1;
/** in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in samples counter.
*/
uint32_t chnl0_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl0_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data from the DMA
uint32_t in_cnt_clr : 1;
uint32_t reserved_2 : 6;
/** in_samples : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the samples number of data from the DMA
*/
uint32_t chnl0_in_len:24;
uint32_t in_samples : 24;
};
uint32_t val;
} asrc_chnl0_cfg5_reg_t;
} asrc_cfg5_reg_t;
/** Type of chnl0_cfg6 register
/** Type of cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
/** out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl0_out_eof_gen_mode:2;
/** chnl0_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
uint32_t out_eof_gen_mode : 2;
/** out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out samples counter.
*/
uint32_t chnl0_out_cnt_ena:1;
/** chnl0_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
uint32_t out_cnt_ena : 1;
/** out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out samples counter.
*/
uint32_t chnl0_out_cnt_clr:1;
/** chnl0_out_len_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl0_out_cnt >=
* reg_chnl0_out_len
uint32_t out_cnt_clr : 1;
/** out_samples_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out samples counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_out_cnt >=
* reg_out_samples
*/
uint32_t chnl0_out_len_comp:1;
uint32_t reserved_5:3;
/** chnl0_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
uint32_t out_samples_comp : 1;
uint32_t reserved_5 : 3;
/** out_samples : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the samples number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl0_out_len:24;
uint32_t out_samples : 24;
};
uint32_t val;
} asrc_chnl0_cfg6_reg_t;
} asrc_cfg6_reg_t;
/** Type of chnl0_fifo_ctrl register
/** Type of fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl0_infifo_reset : WT; bitpos: [0]; default: 0;
/** infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl0_infifo_reset:1;
/** chnl0_outfifo_reset : WT; bitpos: [1]; default: 0;
uint32_t infifo_reset : 1;
/** outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl0_outfifo_reset:1;
uint32_t reserved_2:30;
uint32_t outfifo_reset : 1;
uint32_t reserved_2 : 30;
};
uint32_t val;
} asrc_chnl0_fifo_ctrl_reg_t;
/** Type of chnl1_cfg0 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_rs2_stg1_bypass : R/W; bitpos: [0]; default: 1;
* Set this bit to bypass stage 1 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg1_bypass:1;
/** chnl1_rs2_stg0_bypass : R/W; bitpos: [1]; default: 1;
* Set this bit to bypass stage 0 re-sampler in channel1.
*/
uint32_t chnl1_rs2_stg0_bypass:1;
/** chnl1_frac_bypass : R/W; bitpos: [2]; default: 1;
* Set this bit to bypass fractional re-sampler in channel1.
*/
uint32_t chnl1_frac_bypass:1;
/** chnl1_rs2_stg1_mode : R/W; bitpos: [3]; default: 0;
* Write this bit to configure stage 1 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg1_mode:1;
/** chnl1_rs2_stg0_mode : R/W; bitpos: [4]; default: 0;
* Write this bit to configure stage 0 re-sampler mode in channel1, 0: interpolation
* by factor of 2, 1: decimation by factor of 2.
*/
uint32_t chnl1_rs2_stg0_mode:1;
/** chnl1_frac_ahead : R/W; bitpos: [5]; default: 0;
* Set this bit to move fraction re-sampler to the first stage in channel1, it should
* be 1 when input frequency is higher the output.
*/
uint32_t chnl1_frac_ahead:1;
uint32_t reserved_6:1;
/** chnl1_mode : R/W; bitpos: [8:7]; default: 0;
* Write the bit to configure the channel mode,0: in and out are both mono, 1: in and
* out is both dual, 2: in is mono, out is dual, 3, in is dual, out is mono.
*/
uint32_t chnl1_mode:2;
/** chnl1_sel : R/W; bitpos: [9]; default: 0;
* Write the bit to configure which 16bits data will be processing.
*/
uint32_t chnl1_sel:1;
uint32_t reserved_10:22;
};
uint32_t val;
} asrc_chnl1_cfg0_reg_t;
/** Type of chnl1_cfg1 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_m : R/W; bitpos: [9:0]; default: 0;
* Write the bits to specify the denominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_m and reg_chnl0_frac_l are relatively prime.
*/
uint32_t chnl1_frac_m:10;
/** chnl1_frac_l : R/W; bitpos: [19:10]; default: 0;
* Write the bits to specify the nominator of factor of fraction re-sampler in
* channel1, reg_chnl0_frac_l and reg_chnl0_frac_m are relatively prime.
*/
uint32_t chnl1_frac_l:10;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg1_reg_t;
/** Type of chnl1_cfg2 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_frac_recipl : R/W; bitpos: [19:0]; default: 0;
* Write the bits with ((2^19+L)/(2L)) round down in channel1.
*/
uint32_t chnl1_frac_recipl:20;
uint32_t reserved_20:12;
};
uint32_t val;
} asrc_chnl1_cfg2_reg_t;
/** Type of chnl1_cfg3 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset channel1.
*/
uint32_t chnl1_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg3_reg_t;
/** Type of chnl1_cfg4 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_start : R/W; bitpos: [0]; default: 0;
* Set this bit to start channel1.
*/
uint32_t chnl1_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_cfg4_reg_t;
/** Type of chnl1_cfg5 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_in_cnt_ena : R/W; bitpos: [0]; default: 0;
* Set this bit to enable in data byte counter.
*/
uint32_t chnl1_in_cnt_ena:1;
/** chnl1_in_cnt_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear in data byte counter.
*/
uint32_t chnl1_in_cnt_clr:1;
uint32_t reserved_2:6;
/** chnl1_in_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte numbers of data from the DMA
*/
uint32_t chnl1_in_len:24;
};
uint32_t val;
} asrc_chnl1_cfg5_reg_t;
/** Type of chnl1_cfg6 register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_out_eof_gen_mode : R/W; bitpos: [1:0]; default: 0;
* Write the bits to specify the which eof will be written to DMA. 0: counter eof, 1:
* DMA ineof, 2: both counter eof and DMA ineof, 3 none.
*/
uint32_t chnl1_out_eof_gen_mode:2;
/** chnl1_out_cnt_ena : R/W; bitpos: [2]; default: 0;
* Set this bit to enable out data byte counter.
*/
uint32_t chnl1_out_cnt_ena:1;
/** chnl1_out_cnt_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear out data byte counter.
*/
uint32_t chnl1_out_cnt_clr:1;
/** chnl1_out_samples_comp : R/W; bitpos: [4]; default: 0;
* Set this bit to enable out data byte counter compensation when using fractional
* re-sampler and decimation by factor of 2 which results in reg_chnl1_out_cnt >=
* reg_chnl1_out_len
*/
uint32_t chnl1_out_samples_comp:1;
uint32_t reserved_5:3;
/** chnl1_out_len : R/W; bitpos: [31:8]; default: 0;
* Write the bits to specify the data byte number of data to the DMA, the counter eof
* will be set when the counter approaches.
*/
uint32_t chnl1_out_len:24;
};
uint32_t val;
} asrc_chnl1_cfg6_reg_t;
/** Type of chnl1_fifo_ctrl register
* Control and configuration registers
*/
typedef union {
struct {
/** chnl1_infifo_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset outfifo.
*/
uint32_t chnl1_infifo_reset:1;
/** chnl1_outfifo_reset : WT; bitpos: [1]; default: 0;
* Set this bit to reset infifo.
*/
uint32_t chnl1_outfifo_reset:1;
uint32_t reserved_2:30;
};
uint32_t val;
} asrc_chnl1_fifo_ctrl_reg_t;
} asrc_fifo_ctrl_reg_t;
/** Group: Interrupt Register */
/** Type of chnl0_int_raw register
/** Type of int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
/** outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to
* reg_out_samples.
*/
uint32_t chnl0_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
uint32_t outcnt_eof_int_raw : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_int_raw_reg_t;
} asrc_int_raw_reg_t;
/** Type of chnl0_int_st register
/** Type of int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
/** outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl0_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
uint32_t outcnt_eof_int_st : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_int_st_reg_t;
} asrc_int_st_reg_t;
/** Type of chnl0_int_ena register
/** Type of int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
/** outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl0_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
uint32_t outcnt_eof_int_ena : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_int_ena_reg_t;
} asrc_int_ena_reg_t;
/** Type of chnl0_int_clr register
/** Type of int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl0_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
/** outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl0_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
uint32_t outcnt_eof_int_clr : 1;
uint32_t reserved_1 : 31;
};
uint32_t val;
} asrc_chnl0_int_clr_reg_t;
/** Type of chnl1_int_raw register
* Raw interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* This interrupt raw bit turns to high level when the counter approach to reg_out_len.
*/
uint32_t chnl1_outcnt_eof_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_raw_reg_t;
/** Type of chnl1_int_st register
* Masked interrupt status
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_st : RO; bitpos: [0]; default: 0;
* This is the status bit for reg_out_cnt_eof_int_raw when reg_out_cnt_eof_int_ena is
* set to 1.
*/
uint32_t chnl1_outcnt_eof_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_st_reg_t;
/** Type of chnl1_int_ena register
* Interrupt enable bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_ena : R/W; bitpos: [0]; default: 0;
* This is the enable bit for reg_out_cnt_eof_int_st register.
*/
uint32_t chnl1_outcnt_eof_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_ena_reg_t;
/** Type of chnl1_int_clr register
* Interrupt clear bits
*/
typedef union {
struct {
/** chnl1_outcnt_eof_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the reg_out_cnt_eof_int_raw interrupt.
*/
uint32_t chnl1_outcnt_eof_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} asrc_chnl1_int_clr_reg_t;
} asrc_int_clr_reg_t;
/** Group: Status registers */
/** Type of chnl0_out_cnt register
/** Type of out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl0_out_cnt : RO; bitpos: [23:0]; default: 0;
/** out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the bytes numbers send to the DMA when EOF occurs.
*/
uint32_t chnl0_out_cnt:24;
uint32_t reserved_24:8;
uint32_t out_cnt : 24;
uint32_t reserved_24 : 8;
};
uint32_t val;
} asrc_chnl0_out_cnt_reg_t;
/** Type of chnl1_out_cnt register
* Status Registers
*/
typedef union {
struct {
/** chnl1_out_cnt : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA when EOF occurs.
*/
uint32_t chnl1_out_cnt:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_out_cnt_reg_t;
} asrc_out_cnt_reg_t;
/** Group: DEBUG registers */
/** Type of chnl0_trace1 register
/** Type of trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl0_out_inc : RO; bitpos: [23:0]; default: 0;
/** out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the samples numbers send to the DMA
*/
uint32_t chnl0_out_inc:24;
uint32_t reserved_24:8;
uint32_t out_inc : 24;
uint32_t reserved_24 : 8;
};
uint32_t val;
} asrc_chnl0_trace1_reg_t;
/** Type of chnl1_trace1 register
* Debug Register1
*/
typedef union {
struct {
/** chnl1_out_inc : RO; bitpos: [23:0]; default: 0;
* Represents the data byte numbers send to the DMA
*/
uint32_t chnl1_out_inc:24;
uint32_t reserved_24:8;
};
uint32_t val;
} asrc_chnl1_trace1_reg_t;
} asrc_trace1_reg_t;
/** Group: Configuration registers */
/** Type of sys register
* Control and configuration
* Control and configuration samples
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 0;
* Reserved
*/
uint32_t clk_en:1;
uint32_t clk_en : 1;
/** chnl0_clk_fo : R/W; bitpos: [1]; default: 0;
* Set this bit to make channel0 clock free run.
*/
uint32_t chnl0_clk_fo:1;
uint32_t chnl0_clk_fo : 1;
/** chnl1_clk_fo : R/W; bitpos: [2]; default: 0;
* Set this bit to make channel1 clock free run.
*/
uint32_t chnl1_clk_fo:1;
uint32_t chnl1_clk_fo : 1;
/** chnl0_outfifo_clk_fo : R/W; bitpos: [3]; default: 0;
* Set this bit to make channel0 outfifo clock free run.
*/
uint32_t chnl0_outfifo_clk_fo:1;
uint32_t chnl0_outfifo_clk_fo : 1;
/** chnl0_infifo_clk_fo : R/W; bitpos: [4]; default: 0;
* Set this bit to make channel0 infifo clock free run.
*/
uint32_t chnl0_infifo_clk_fo:1;
uint32_t chnl0_infifo_clk_fo : 1;
/** chnl1_outfifo_clk_fo : R/W; bitpos: [5]; default: 0;
* Set this bit to make channel1 outfifo clock free run.
*/
uint32_t chnl1_outfifo_clk_fo:1;
uint32_t chnl1_outfifo_clk_fo : 1;
/** chnl1_infifo_clk_fo : R/W; bitpos: [6]; default: 0;
* Set this bit to make channel1 infifo clock free run.
*/
uint32_t chnl1_infifo_clk_fo:1;
uint32_t reserved_7:25;
uint32_t chnl1_infifo_clk_fo : 1;
uint32_t reserved_7 : 25;
};
uint32_t val;
} asrc_sys_reg_t;
/** Group: Version register */
/** Type of date register
* Control and configuration registers
@@ -603,54 +331,41 @@ typedef union {
/** date : R/W; bitpos: [27:0]; default: 37777984;
* Reserved
*/
uint32_t date:28;
uint32_t reserved_28:4;
uint32_t date : 28;
uint32_t reserved_28 : 4;
};
uint32_t val;
} asrc_date_reg_t;
typedef struct {
volatile asrc_chnl0_cfg0_reg_t chnl0_cfg0;
volatile asrc_chnl0_cfg1_reg_t chnl0_cfg1;
volatile asrc_chnl0_cfg2_reg_t chnl0_cfg2;
volatile asrc_chnl0_cfg3_reg_t chnl0_cfg3;
volatile asrc_chnl0_cfg4_reg_t chnl0_cfg4;
volatile asrc_chnl0_cfg5_reg_t chnl0_cfg5;
volatile asrc_chnl0_cfg6_reg_t chnl0_cfg6;
volatile asrc_chnl0_fifo_ctrl_reg_t chnl0_fifo_ctrl;
volatile asrc_chnl0_int_raw_reg_t chnl0_int_raw;
volatile asrc_chnl0_int_st_reg_t chnl0_int_st;
volatile asrc_chnl0_int_ena_reg_t chnl0_int_ena;
volatile asrc_chnl0_int_clr_reg_t chnl0_int_clr;
volatile asrc_chnl0_out_cnt_reg_t chnl0_out_cnt;
uint32_t reserved_034;
volatile asrc_chnl0_trace1_reg_t chnl0_trace1;
volatile asrc_chnl1_cfg0_reg_t chnl1_cfg0;
volatile asrc_chnl1_cfg1_reg_t chnl1_cfg1;
volatile asrc_chnl1_cfg2_reg_t chnl1_cfg2;
volatile asrc_chnl1_cfg3_reg_t chnl1_cfg3;
volatile asrc_chnl1_cfg4_reg_t chnl1_cfg4;
volatile asrc_chnl1_cfg5_reg_t chnl1_cfg5;
volatile asrc_chnl1_cfg6_reg_t chnl1_cfg6;
volatile asrc_chnl1_fifo_ctrl_reg_t chnl1_fifo_ctrl;
volatile asrc_chnl1_int_raw_reg_t chnl1_int_raw;
volatile asrc_chnl1_int_st_reg_t chnl1_int_st;
volatile asrc_chnl1_int_ena_reg_t chnl1_int_ena;
volatile asrc_chnl1_int_clr_reg_t chnl1_int_clr;
volatile asrc_chnl1_out_cnt_reg_t chnl1_out_cnt;
uint32_t reserved_070;
volatile asrc_chnl1_trace1_reg_t chnl1_trace1;
uint32_t reserved_078[32];
volatile asrc_sys_reg_t sys;
typedef struct asrc_dev_t {
struct {
volatile asrc_cfg0_reg_t cfg0;
volatile asrc_cfg1_reg_t cfg1;
volatile asrc_cfg2_reg_t cfg2;
volatile asrc_cfg3_reg_t cfg3;
volatile asrc_cfg4_reg_t cfg4;
volatile asrc_cfg5_reg_t cfg5;
volatile asrc_cfg6_reg_t cfg6;
volatile asrc_fifo_ctrl_reg_t fifo_ctrl;
volatile asrc_int_raw_reg_t int_raw;
volatile asrc_int_st_reg_t int_st;
volatile asrc_int_ena_reg_t int_ena;
volatile asrc_int_clr_reg_t int_clr;
volatile asrc_out_cnt_reg_t out_cnt;
uint32_t reserved_32;
volatile asrc_trace1_reg_t trace1;
} asrc_para[2];
uint32_t reserved_078[32];
volatile asrc_sys_reg_t sys;
volatile asrc_date_reg_t date;
} asrc_dev_t;
extern asrc_dev_t ASRC;
#ifndef __cplusplus
_Static_assert(sizeof(asrc_dev_t) == 0x100, "Invalid size of asrc_dev_t structure");
#endif
#endif /* __cplusplus */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */