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Merge branch 'fix/fix_parlio_valid_delay_max_value_v5.5' into 'release/v5.5'

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fix(parlio): fix max valid delay value (v5.5)

See merge request espressif/esp-idf!49392
This commit is contained in:
morris
2026-06-11 14:08:53 +08:00
parent 8a1a4eae3a 0cb56b975b
commit e2face00fa
3 changed files with 4 additions and 5 deletions
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components/hal/esp32h2/include/hal/parlio_ll.h
-1
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@@ -36,7 +36,6 @@
#define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 7 // TXD[7] can be used a valid signal
#define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE 7 // TXD[7] can be used as clock gate signal
#ifdef __cplusplus
extern "C" {
#endif