diff --git a/components/hal/esp32c5/include/hal/parlio_ll.h b/components/hal/esp32c5/include/hal/parlio_ll.h
index fc7b0c904af..fdcec252d95 100644
--- a/components/hal/esp32c5/include/hal/parlio_ll.h
+++ b/components/hal/esp32c5/include/hal/parlio_ll.h
@@ -33,7 +33,7 @@
 #define PARLIO_LL_EVENT_RX_MASK          (PARLIO_LL_EVENT_RX_FIFO_FULL)
 
 #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE  7 // TXD[7] can be used as clock gate signal
-#define PARLIO_LL_TX_VALID_MAX_DELAY        32767
+#define PARLIO_LL_TX_VALID_MAX_DELAY        65535
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/hal/esp32h2/include/hal/parlio_ll.h b/components/hal/esp32h2/include/hal/parlio_ll.h
index 112c75372a8..b30966e63f8 100644
--- a/components/hal/esp32h2/include/hal/parlio_ll.h
+++ b/components/hal/esp32h2/include/hal/parlio_ll.h
@@ -36,7 +36,6 @@
 
 #define PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG 7 // TXD[7] can be used a valid signal
 #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE  7 // TXD[7] can be used as clock gate signal
-
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h
index 33ad55fb1fd..556dea661e9 100644
--- a/components/hal/esp32p4/include/hal/parlio_ll.h
+++ b/components/hal/esp32p4/include/hal/parlio_ll.h
@@ -42,7 +42,7 @@
 #define PARLIO_LL_TX_DATA_LINE_AS_CLK_GATE  15 // TXD[15] can be used as clock gate signal
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-#define PARLIO_LL_TX_VALID_MAX_DELAY        32767
+#define PARLIO_LL_TX_VALID_MAX_DELAY        65535
 #define PARLIO_LL_SUPPORT_TX_EOF_FROM_DMA   1   // Support to treat DMA EOF as TX unit EOF
 #endif
 
@@ -123,6 +123,7 @@ static inline void _parlio_ll_rx_set_clock_source(parl_io_dev_t *dev, parlio_clo
         HAL_ASSERT(false);
         break;
     }
+    LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL);
     HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_src_sel = clk_sel;
 }
 
@@ -175,7 +176,6 @@ __attribute__((always_inline))
 static inline void _parlio_ll_rx_enable_clock(parl_io_dev_t *dev, bool en)
 {
     (void)dev;
-    LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_rx_clk_en = en;
     HP_SYS_CLKRST.peri_clk_ctrl117.reg_parlio_rx_clk_en = en;
 }
 
@@ -461,6 +461,7 @@ static inline void _parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clo
         HAL_ASSERT(false);
         break;
     }
+    LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = (src == PARLIO_CLK_SRC_EXTERNAL);
     HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_src_sel = clk_sel;
 }
 
@@ -514,7 +515,6 @@ __attribute__((always_inline))
 static inline void _parlio_ll_tx_enable_clock(parl_io_dev_t *dev, bool en)
 {
     (void)dev;
-    LP_AON_CLKRST.hp_clk_ctrl.hp_pad_parlio_tx_clk_en = en;
     HP_SYS_CLKRST.peri_clk_ctrl118.reg_parlio_tx_clk_en = en;
 }