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feat(system): add OCD stub bin support for more targets

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Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21, esp32p4, and esp32s31. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
This commit is contained in:
Erhan Kurubas
2026-07-28 08:34:02 +03:00
parent 6e5b4febf8
commit e21ab7e724
16 changed files with 67 additions and 4 deletions
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components/esp_system/Kconfig
+7
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@@ -409,6 +409,7 @@ menu "ESP System Settings"
bool "Preload OpenOCD stub binaries to speed up debugging. 12K memory will be reserved"
default n
depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
depends on !IDF_TARGET_ESP32P4 || ESP32P4_SELECTS_REV_LESS_V3 || CACHE_L2_CACHE_512KB
help
OpenOCD uses stub code to access flash during programming or when inserting and removing
SW flash breakpoints.
@@ -418,6 +419,12 @@ menu "ESP System Settings"
By enabling this option, 12K of memory in RAM will be preallocated with the stub code,
eliminating the need to back up and restore the memory region.
The stub binaries are prebuilt and linked to run at the start of IRAM (_iram_start).
On ESP32-P4 rev >= v3, _iram_start is 0x4FF00000 + L2 cache size, so it only matches the
stub's link address (0x4FF80000) when the L2 cache is 512KB. This option is therefore
only available on ESP32-P4 rev >= v3 when CACHE_L2_CACHE_512KB is selected. Earlier P4
revisions and other targets place _iram_start at a fixed address and are not affected.
config ESP_DEBUG_OCDAWARE
bool "Make exception and panic handlers JTAG/OCD aware"
default y