From e21ab7e72401f6b46d36fd57b2fa77dcf0b60b63 Mon Sep 17 00:00:00 2001
From: Erhan Kurubas <erhan.kurubas@espressif.com>
Date: Mon, 27 Jul 2026 17:04:28 +0300
Subject: [PATCH] feat(system): add OCD stub bin support for more targets

Add SOC_DEBUG_HAVE_OCD_STUB_BINS for esp32c5, esp32c61, esp32h4,
esp32h21, esp32p4, and esp32s31. Update TEE linker scripts with
correct esp_tee_app_config offsets for the 0x3000 stub reservation
---
 components/esp_system/Kconfig                        |  7 +++++++
 .../esp_system/openocd_stub_bins/CMakeLists.txt      | 12 ++++++++----
 .../esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in |  5 +++++
 .../subproject/main/ld/esp32c61/esp_tee.ld.in        |  5 +++++
 .../soc/esp32c5/include/soc/Kconfig.soc_caps.in      |  4 ++++
 components/soc/esp32c5/include/soc/soc_caps.h        |  3 +++
 .../soc/esp32c61/include/soc/Kconfig.soc_caps.in     |  4 ++++
 components/soc/esp32c61/include/soc/soc_caps.h       |  3 +++
 .../soc/esp32h21/include/soc/Kconfig.soc_caps.in     |  4 ++++
 components/soc/esp32h21/include/soc/soc_caps.h       |  3 +++
 .../soc/esp32h4/include/soc/Kconfig.soc_caps.in      |  4 ++++
 components/soc/esp32h4/include/soc/soc_caps.h        |  3 +++
 .../soc/esp32p4/include/soc/Kconfig.soc_caps.in      |  4 ++++
 components/soc/esp32p4/include/soc/soc_caps.h        |  3 +++
 .../soc/esp32s31/include/soc/Kconfig.soc_caps.in     |  4 ++++
 components/soc/esp32s31/include/soc/soc_caps.h       |  3 +++
 16 files changed, 67 insertions(+), 4 deletions(-)

diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
index 0bb456518d6..0804d0d6923 100644
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -409,6 +409,7 @@ menu "ESP System Settings"
         bool "Preload OpenOCD stub binaries to speed up debugging. 12K memory will be reserved"
         default n
         depends on SOC_DEBUG_HAVE_OCD_STUB_BINS
+        depends on !IDF_TARGET_ESP32P4 || ESP32P4_SELECTS_REV_LESS_V3 || CACHE_L2_CACHE_512KB
         help
             OpenOCD uses stub code to access flash during programming or when inserting and removing
             SW flash breakpoints.
@@ -418,6 +419,12 @@ menu "ESP System Settings"
             By enabling this option, 12K of memory in RAM will be preallocated with the stub code,
             eliminating the need to back up and restore the memory region.
 
+            The stub binaries are prebuilt and linked to run at the start of IRAM (_iram_start).
+            On ESP32-P4 rev >= v3, _iram_start is 0x4FF00000 + L2 cache size, so it only matches the
+            stub's link address (0x4FF80000) when the L2 cache is 512KB. This option is therefore
+            only available on ESP32-P4 rev >= v3 when CACHE_L2_CACHE_512KB is selected. Earlier P4
+            revisions and other targets place _iram_start at a fixed address and are not affected.
+
     config ESP_DEBUG_OCDAWARE
         bool "Make exception and panic handlers JTAG/OCD aware"
         default y
diff --git a/components/esp_system/openocd_stub_bins/CMakeLists.txt b/components/esp_system/openocd_stub_bins/CMakeLists.txt
index ebd73f430aa..ee420877f76 100644
--- a/components/esp_system/openocd_stub_bins/CMakeLists.txt
+++ b/components/esp_system/openocd_stub_bins/CMakeLists.txt
@@ -15,10 +15,14 @@ set(openocd_path $ENV{OPENOCD_SCRIPTS})
 
 if(openocd_path)
     set(stub_bin_path ${openocd_path}/../espressif/stub_bins)
-    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${target})
-        set(code_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_code.inc")
-        set(data_bin "${stub_bin_path}/${target}/stub_flash_idf_binary_data.inc")
-        set(img_header "${stub_bin_path}/${target}/stub_flash_idf_image.h")
+    set(stub_target_dir ${target})
+    if(target STREQUAL "esp32p4" AND CONFIG_ESP32P4_REV_MIN_FULL LESS 300)
+        set(stub_target_dir "esp32p4-rev1")
+    endif()
+    if(IS_DIRECTORY ${stub_bin_path} AND IS_DIRECTORY ${stub_bin_path}/${stub_target_dir})
+        set(code_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_code.inc")
+        set(data_bin "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_binary_data.inc")
+        set(img_header "${stub_bin_path}/${stub_target_dir}/stub_flash_idf_image.h")
         if(EXISTS ${code_bin} AND EXISTS ${data_bin} AND EXISTS ${img_header})
             set(dest_dir "${CMAKE_BINARY_DIR}/openocd_stub_bins")
             set(output_code_bin "${dest_dir}/stub_flash_idf_binary_code.inc")
diff --git a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
index becd7e7a5b4..bbb5c11442f 100644
--- a/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c5/esp_tee.ld.in
@@ -32,7 +32,12 @@
  * should be stored via esp_app_tee_config structure
  */
 
+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );
 
 /* SPI Flash functions required from the ROM (refer esp32c5.rom.spiflash.ld) */
diff --git a/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in b/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
index 3e08a50c6bb..cbfa205a646 100644
--- a/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
+++ b/components/esp_tee/subproject/main/ld/esp32c61/esp_tee.ld.in
@@ -32,7 +32,12 @@
  * should be stored via esp_app_tee_config structure
  */
 
+#if CONFIG_ESP_DEBUG_INCLUDE_OCD_STUB_BINS
+PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x32b0 );
+#else
 PROVIDE ( esp_tee_app_config        = SRAM_REE_SEG_START + 0x2b0 );
+#endif
+
 PROVIDE ( GDMA                      = 0x60080000 );
 
 /* SPI Flash functions required from the ROM (refer esp32c61.rom.spiflash.ld) */
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 3068da587d5..e76561f2c3f 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1591,6 +1591,10 @@ config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
     bool
     default y
 
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR
     bool
     default y
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index 936d11ac30a..ca365e2ccc1 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -635,6 +635,9 @@
 // #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)
 
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- ULP CAPS -------------------------------------*/
 #define SOC_LP_CORE_SINGLE_INTERRUPT_VECTOR         (1) /*!< LP Core interrupts all map to a single entry in vector table */
 #define SOC_LP_CORE_SUPPORT_ETM                     (1) /*!< LP Core supports ETM */
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index dba3bad08d5..1319469c2a1 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1226,3 +1226,7 @@ config SOC_PHY_COMBO_MODULE
 config SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT
     bool
     default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index e128393d83d..1fd375e8cb1 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -496,5 +496,8 @@
 #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi, BLE and 15.4*/
 #define SOC_PHY_CALIBRATION_CLOCK_IS_INDEPENDENT (1)
 
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*------------------------------------- No Reset CAPS -------------------------------------*/
 //  \#define SOC_CAPS_NO_RESET_BY_ANA_BOD           (1)   //TODO: [ESP32C61] IDF-9254
diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 497189d1511..afa3ae00885 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -1134,3 +1134,7 @@ config SOC_BLE_SUBRATE_SUPPORTED
 config SOC_BLE_PERIODIC_ADV_WITH_RESPONSE
     bool
     default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index 40e231cc0d9..fbc18642dc1 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -494,3 +494,6 @@
 #define SOC_BLE_CTE_SUPPORTED           (1)    /*!< Support Bluetooth LE Constant Tone Extension (CTE) */
 #define SOC_BLE_SUBRATE_SUPPORTED       (1)    /*!< Support Bluetooth LE Connection Subrating */
 #define SOC_BLE_PERIODIC_ADV_WITH_RESPONSE  (1)    /*!< Support Bluetooth LE Periodic Advertising with Response (PAwR) */
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index 4c0c4684adb..c69bcc969d6 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -1367,6 +1367,10 @@ config SOC_USB_FSLS_PHY_NUM
     int
     default 1
 
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_ASRC_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index bac32073a76..8bdd23bd7a0 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -564,5 +564,8 @@
 #define SOC_USB_OTG_PERIPH_NUM          (1U)
 #define SOC_USB_FSLS_PHY_NUM            (1U)
 
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*---------------------------------- ASRC CAPS ----------------------------------*/
 #define SOC_ASRC_SUPPORTED (1)
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 02034b1cbd8..012b091ee4f 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1935,6 +1935,10 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
     bool
     default y
 
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index bc22129bfa5..8712f221022 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -739,6 +739,9 @@
 #define SOC_LP_CORE_HW_AUTO_CLRWAKEUPCAUSE          (1) /*!< LP core requests sleep, PMU clears both HP and LP wakeup causes */
 #define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
 
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
+
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index cfd4342ee25..fe8128d37ea 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -1838,3 +1838,7 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_ETM
 config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
     bool
     default y
+
+config SOC_DEBUG_HAVE_OCD_STUB_BINS
+    bool
+    default y
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index 00f8b2f19ea..fda586653a0 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -683,3 +683,6 @@
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_ETM                   (1)
 // temperature sensor on esp32s31 in under low power domain.
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION       (1)
+
+/*------------------------------------- DEBUG CAPS -------------------------------------*/
+#define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)