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https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
feat(hal): Add RISC-V trace register read-back accessors
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@@ -112,6 +112,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
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hw->trigger.mem_loop = loop;
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}
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static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
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{
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return hw->trigger.mem_loop;
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}
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static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
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{
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hw->trigger.restart_ena = enable;
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@@ -134,11 +139,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
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hw->resync_prolonged.resync_mode = (mode == RISCV_TRACE_RESYNC_PACKET);
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}
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static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
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{
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return hw->resync_prolonged.resync_mode ? RISCV_TRACE_RESYNC_PACKET : RISCV_TRACE_RESYNC_CYCLE;
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}
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static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
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{
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hw->resync_prolonged.resync_prolonged = threshold;
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}
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static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
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{
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return hw->resync_prolonged.resync_prolonged;
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}
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/*---------------------------------------------------------------------------
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* Interrupts
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*--------------------------------------------------------------------------*/
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