Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(hal): Add RISC-V trace register read-back accessors

Browse Source
This commit is contained in:
Erhan Kurubas
2026-09-03 08:20:11 +02:00
parent 5b4a90da6e
commit e0ffa602f7
10 changed files with 197 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hal_debug_assist/esp32c6/include/hal/riscv_trace_ll.h
+15
View File
@@ -112,6 +112,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
hw->trigger.mem_loop = loop;
}
static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
{
return hw->trigger.mem_loop;
}
static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
{
hw->trigger.restart_ena = enable;
@@ -134,11 +139,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
hw->resync_prolonged.resync_mode = (mode == RISCV_TRACE_RESYNC_PACKET);
}
static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
{
return hw->resync_prolonged.resync_mode ? RISCV_TRACE_RESYNC_PACKET : RISCV_TRACE_RESYNC_CYCLE;
}
static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
{
hw->resync_prolonged.resync_prolonged = threshold;
}
static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
{
return hw->resync_prolonged.resync_prolonged;
}
/*---------------------------------------------------------------------------
* Interrupts
*--------------------------------------------------------------------------*/