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feat(cpu): add support for esp32s31

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This commit is contained in:
Marius Vikhammer
2026-01-20 11:59:45 +08:00
parent 17108935ad
commit e085c21e22
4 changed files with 31 additions and 14 deletions
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components/hal/esp32s31/include/hal/cpu_utility_ll.h
+26 -9
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,32 +20,48 @@ extern "C" {
FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
{
// TODO: [ESP32S31] IDF-14655
if (cpu_no == 0) {
LP_CLKRST.hpcore0_reset_ctrl.hpcore0_sw_reset = 1;
} else {
LP_CLKRST.hpcore1_reset_ctrl.hpcore1_sw_reset = 1;
}
}
#if SOC_CPU_CORES_NUM > 1 // We only allow stalling/unstalling of other cores
FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
{
// TODO: [ESP32S31] IDF-14655
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore0_sw_stall_code, 0x86);
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore1_sw_stall_code, 0x86);
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
{
// TODO: [ESP32S31] IDF-14655
if (cpu_no == 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore0_sw_stall_code, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
} else {
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore1_sw_stall_code, 0xFF);
while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
}
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
{
// TODO: [ESP32S31] IDF-14655
(void) cpu_no;
// TODO: IDF-14675 ASSIST_DEBUG is not supported yet on ESP32S31
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
{
// TODO: [ESP32S31] IDF-14655
(void) cpu_no;
// TODO: IDF-14675 ASSIST_DEBUG is not supported yet on ESP32S31
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
{
// TODO: [ESP32S31] IDF-14655
if (!REG_GET_BIT(HP_SYS_CLKRST_HPCORE1_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
REG_SET_BIT(HP_SYS_CLKRST_HPCORE1_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
}
@@ -61,14 +77,15 @@ FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)
{
return 0;// TODO: [ESP32S31] IDF-14655
return REG_GET_BIT(HP_SYSTEM_CPU_WAITI_CONF_REG, HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON);
}
FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
{
// TODO: [ESP32S31] IDF-14655
}
#endif // SOC_CPU_CORES_NUM > 1
#ifdef __cplusplus
}
#endif