diff --git a/components/hal/esp32s31/include/hal/cpu_utility_ll.h b/components/hal/esp32s31/include/hal/cpu_utility_ll.h
index 5477fa8e86d..d4eb5cd4045 100644
--- a/components/hal/esp32s31/include/hal/cpu_utility_ll.h
+++ b/components/hal/esp32s31/include/hal/cpu_utility_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,32 +20,48 @@ extern "C" {
 
 FORCE_INLINE_ATTR void cpu_utility_ll_reset_cpu(uint32_t cpu_no)
 {
-    // TODO: [ESP32S31] IDF-14655
+    if (cpu_no == 0) {
+        LP_CLKRST.hpcore0_reset_ctrl.hpcore0_sw_reset = 1;
+    } else {
+        LP_CLKRST.hpcore1_reset_ctrl.hpcore1_sw_reset = 1;
+    }
 }
 
+#if SOC_CPU_CORES_NUM > 1   // We only allow stalling/unstalling of other cores
 FORCE_INLINE_ATTR void cpu_utility_ll_stall_cpu(uint32_t cpu_no)
 {
-    // TODO: [ESP32S31] IDF-14655
+    if (cpu_no == 0) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore0_sw_stall_code, 0x86);
+    } else {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore1_sw_stall_code, 0x86);
+    }
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_unstall_cpu(uint32_t cpu_no)
 {
-    // TODO: [ESP32S31] IDF-14655
+    if (cpu_no == 0) {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore0_sw_stall_code, 0xFF);
+        while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE0_CORESTALLED_ST));
+    } else {
+        HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.cpu_stall_sw, hpcore1_sw_stall_code, 0xFF);
+        while(REG_GET_BIT(HP_SYSTEM_CPU_CORESTALLED_ST_REG, HP_SYSTEM_REG_CORE1_CORESTALLED_ST));
+    }
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_enable_debug(uint32_t cpu_no)
 {
-    // TODO: [ESP32S31] IDF-14655
+    (void) cpu_no;
+    // TODO: IDF-14675 ASSIST_DEBUG is not supported yet on ESP32S31
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_enable_record(uint32_t cpu_no)
 {
-    // TODO: [ESP32S31] IDF-14655
+    (void) cpu_no;
+    // TODO: IDF-14675 ASSIST_DEBUG is not supported yet on ESP32S31
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
 {
-    // TODO: [ESP32S31] IDF-14655
     if (!REG_GET_BIT(HP_SYS_CLKRST_HPCORE1_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN)) {
         REG_SET_BIT(HP_SYS_CLKRST_HPCORE1_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
     }
@@ -61,14 +77,15 @@ FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu(void)
 
 FORCE_INLINE_ATTR uint32_t cpu_utility_ll_wait_mode(void)
 {
-    return 0;// TODO: [ESP32S31] IDF-14655
+    return REG_GET_BIT(HP_SYSTEM_CPU_WAITI_CONF_REG, HP_SYSTEM_CPU_WAIT_MODE_FORCE_ON);
 }
 
 FORCE_INLINE_ATTR void cpu_utility_ll_enable_clock_and_reset_app_cpu_int_matrix(void)
 {
-    // TODO: [ESP32S31] IDF-14655
 }
 
+#endif // SOC_CPU_CORES_NUM > 1
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index 80467b602d5..804f62e84fb 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -133,11 +133,11 @@ config SOC_HP_CPU_HAS_MULTIPLE_CORES
 
 config SOC_CPU_BREAKPOINTS_NUM
     int
-    default 3
+    default 4
 
 config SOC_CPU_WATCHPOINTS_NUM
     int
-    default 3
+    default 4
 
 config SOC_CPU_WATCHPOINT_MAX_REGION_SIZE
     hex
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index 3f122cd536f..9d270a65bfb 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -111,7 +111,6 @@
 #define SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE      0
 
 /*-------------------------- CPU CAPS ----------------------------------------*/
-// TODO: [ESP32S31] IDF-14655
 #define SOC_CPU_CORES_NUM               (2U)
 #define SOC_CPU_INTR_NUM                32
 #define SOC_CPU_HAS_FLEXIBLE_INTC       1
@@ -127,8 +126,8 @@
 
 #define SOC_HP_CPU_HAS_MULTIPLE_CORES   1   // Convenience boolean macro used to determine if a target has multiple cores.
 
-#define SOC_CPU_BREAKPOINTS_NUM             3
-#define SOC_CPU_WATCHPOINTS_NUM             3
+#define SOC_CPU_BREAKPOINTS_NUM             4
+#define SOC_CPU_WATCHPOINTS_NUM             4
 #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE  0x100   // bytes
 
 #define SOC_CPU_HAS_PMA                 1
diff --git a/components/soc/esp32s31/register/soc/lp_clkrst_struct.h b/components/soc/esp32s31/register/soc/lp_clkrst_struct.h
index b1ed6877631..a89160c16cc 100644
--- a/components/soc/esp32s31/register/soc/lp_clkrst_struct.h
+++ b/components/soc/esp32s31/register/soc/lp_clkrst_struct.h
@@ -704,6 +704,7 @@ typedef struct {
     volatile lp_aonclkrst_date_reg_t date;
 } lp_aonclkrst_dev_t;
 
+extern lp_aonclkrst_dev_t LP_CLKRST;
 
 #ifndef __cplusplus
 _Static_assert(sizeof(lp_aonclkrst_dev_t) == 0x400, "Invalid size of lp_aonclkrst_dev_t structure");