Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-06-04 20:26:38 +03:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feat/support_esp32p4_eco5_pmu' into 'master'

Browse Source 
feat(esp_hw_support): Update esp32p4 eco5 lowpower features support

See merge request espressif/esp-idf!41162
This commit is contained in:
Wu Zheng Hui
2025-10-15 19:47:43 +08:00
parent 7d7c5f1412 065dd70056
commit dfeae969a4
59 changed files with 459 additions and 174 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/driver/test_apps/legacy_twai/main/test_twai_loop_back.cpp
View File

@@ -143,7 +143,7 @@ static void s_test_sleep_retention(bool allow_pd)
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
esp_sleep_context_t sleep_ctx;
@@ -209,7 +209,7 @@ static void s_test_sleep_retention(bool allow_pd)
}
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}

10
components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -72,14 +72,14 @@ static void test_gptimer_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 2 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if GPTimer driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
@@ -189,14 +189,14 @@ static void test_gptimer_etm_sleep_retention(bool back_up_before_sleep)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 2 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if GPTimer and ETM can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

8
components/esp_driver_i2c/test_apps/i2c_test_apps/main/test_i2c_sleep_retention.cpp
View File

@@ -81,7 +81,7 @@ static void i2c_master_write_sleep_retention_test(void)
TEST_ESP_OK(i2c_master_transmit(dev_handle, data_wr, DATA_LENGTH, -1));
unity_wait_for_signal("i2c slave receive once, master to sleep");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(3 * 1000 * 1000));
@@ -99,7 +99,7 @@ static void i2c_master_write_sleep_retention_test(void)
unity_send_signal("master write again");
unity_wait_for_signal("ready to delete");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
TEST_ESP_OK(i2c_master_bus_rm_device(dev_handle));
@@ -149,7 +149,7 @@ static void i2c_slave_read_sleep_retention_test(void)
unity_send_signal("i2c slave receive once, master to sleep");
// Slave sleep as well..
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
@@ -173,7 +173,7 @@ static void i2c_slave_read_sleep_retention_test(void)
vQueueDelete(event_queue);
unity_send_signal("ready to delete");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
TEST_ESP_OK(i2c_del_slave_device(slave_handle));

4
components/esp_driver_i2s/test_apps/i2s/main/test_i2s_sleep.c
View File

@@ -29,7 +29,7 @@ static void s_test_i2s_enter_light_sleep(int sec, bool allow_power_down)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("Entering light sleep for %d seconds\n", sec);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
printf("Enable CPU power down\n");
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
@@ -37,7 +37,7 @@ static void s_test_i2s_enter_light_sleep(int sec, bool allow_power_down)
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(sec * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
printf("Woke up from light sleep\n");

4
components/esp_driver_ledc/test_apps/ledc/main/test_ledc_sleep.cpp
View File

@@ -44,7 +44,7 @@ static void test_ledc_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
@@ -53,7 +53,7 @@ static void test_ledc_sleep_retention(bool allow_pd)
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if LEDC peripheral can still work...\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

10
components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_sleep.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -71,14 +71,14 @@ static void test_mcpwm_timer_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 1 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if MCPWM driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
@@ -176,14 +176,14 @@ static void test_mcpwm_capture_timer_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 1 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if MCPWM driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

4
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_sleep.c
View File

@@ -120,14 +120,14 @@ static void test_parlio_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 2 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if PARLIO driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

4
components/esp_driver_pcnt/test_apps/pulse_cnt/main/test_pulse_cnt_sleep.c
View File

@@ -85,14 +85,14 @@ static void test_pcnt_sleep_retention(void)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 1 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if PCNT driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

4
components/esp_driver_rmt/test_apps/rmt/main/test_rmt_sleep.c
View File

@@ -94,14 +94,14 @@ static void test_rmt_tx_rx_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 2 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if RMT driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

4
components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm_sleep.cpp
View File

@@ -51,14 +51,14 @@ static void test_sdm_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
printf("go to light sleep for 2 seconds\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
printf("Waked up! Let's see if SDM driver can still work...\r\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif

4
components/esp_driver_spi/test_apps/master/main/test_spi_master.c
View File

@@ -1844,7 +1844,7 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
esp_sleep_context_t sleep_ctx;
@@ -1898,7 +1898,7 @@ TEST_CASE("test_spi_master_sleep_retention", "[spi]")
}
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}

4
components/esp_driver_spi/test_apps/master/main/test_spi_master_sct.c
View File

@@ -305,7 +305,7 @@ static void sleep_master(void)
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
sleep_cpu_configure(true);
#endif
esp_sleep_context_t sleep_ctx;
@@ -378,7 +378,7 @@ static void sleep_master(void)
TEST_ESP_OK(spi_bus_remove_device(handle));
TEST_ESP_OK(spi_bus_free(SPI2_HOST));
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}

4
components/esp_driver_spi/test_apps/slave/main/test_spi_slave.c
View File

@@ -657,7 +657,7 @@ TEST_CASE("test_spi_slave_sleep_retention", "[spi]")
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
sleep_cpu_configure(true);
#endif
esp_sleep_context_t sleep_ctx;
@@ -708,7 +708,7 @@ TEST_CASE("test_spi_slave_sleep_retention", "[spi]")
}
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}

8
components/esp_driver_spi/test_apps/slave_hd/main/test_spi_slave_hd.c
View File

@@ -930,7 +930,7 @@ TEST_CASE("test_spi_slave_hd_sleep_retention", "[spi]")
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
sleep_cpu_configure(true);
#endif
esp_sleep_context_t sleep_ctx;
@@ -1002,7 +1002,7 @@ TEST_CASE("test_spi_slave_hd_sleep_retention", "[spi]")
}
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}
@@ -1012,7 +1012,7 @@ TEST_CASE("test_spi_slave_hd_append_sleep_retention", "[spi]")
{
// Prepare a TOP PD sleep
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(1 * 1000 * 1000));
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
sleep_cpu_configure(true);
#endif
esp_sleep_context_t sleep_ctx;
@@ -1080,7 +1080,7 @@ TEST_CASE("test_spi_slave_hd_append_sleep_retention", "[spi]")
}
spi_slave_hd_deinit(TEST_SLAVE_HOST);
esp_sleep_set_sleep_context(NULL);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
}

4
components/esp_driver_tsens/test_apps/temperature_sensor/main/test_temperature_sensor.cpp
View File

@@ -176,12 +176,12 @@ static void test_temperature_sensor_sleep_retention(bool allow_pd)
esp_sleep_context_t sleep_ctx;
esp_sleep_set_sleep_context(&sleep_ctx);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(true));
#endif
TEST_ESP_OK(esp_sleep_enable_timer_wakeup(2 * 1000 * 1000));
TEST_ESP_OK(esp_light_sleep_start());
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
TEST_ESP_OK(sleep_cpu_configure(false));
#endif
printf("check if the sleep happened as expected\r\n");

6
components/esp_eth/test_apps/main/test_emac_sleep_retention.c
View File

@@ -52,7 +52,7 @@ static void eth_test_start_sleep(esp_eth_handle_t eth_handle, bool pd_top_down)
esp_sleep_set_sleep_context(&sleep_ctx);
// Configure sleep
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (pd_top_down) {
printf("Enable CPU power down\n");
TEST_ESP_OK(sleep_cpu_configure(true));
@@ -69,7 +69,7 @@ static void eth_test_start_sleep(esp_eth_handle_t eth_handle, bool pd_top_down)
printf("\n ( -.-)Zzz\n\n");
TEST_ESP_OK(esp_light_sleep_start());
printf("\n ( o_o)!\n\n");
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (pd_top_down) {
TEST_ESP_OK(sleep_cpu_configure(false));
}
@@ -349,7 +349,7 @@ TEST_CASE("internal emac sleep retention", "[sleep_retention]")
ESP_LOGI(TAG, "Testing with PD_TOP powered up");
test_emac_sleep_retention(false);
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
ESP_LOGI(TAG, "Testing with PD_TOP powered down");
test_emac_sleep_retention(true);
#endif

12
components/esp_hw_support/include/esp_private/sleep_cpu.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,7 +22,7 @@ extern "C" {
* This file contains declarations of cpu retention related functions in light sleep mode.
*/
#if ESP_SLEEP_POWER_DOWN_CPU || SOC_PM_SUPPORT_CPU_PD
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU || (SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
/**
* @brief Whether to allow the cpu power domain to be powered off.
*
@@ -32,7 +32,7 @@ extern "C" {
bool cpu_domain_pd_allowed(void);
#endif
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
/**
* @brief Configure the parameters of the CPU domain during the sleep process
*
@@ -65,9 +65,9 @@ void sleep_disable_cpu_retention(void);
esp_err_t esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool),
uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp);
#endif // SOC_PM_CPU_RETENTION_BY_SW
#endif // ESP_SLEEP_POWER_DOWN_CPU
#endif // CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
#if !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU
#if !CONFIG_FREERTOS_UNICORE && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
/**
* Do sleep prepare for other smp cores
*/
@@ -82,7 +82,7 @@ void sleep_smp_cpu_wakeup_prepare(void);
* Notify the other core that this sleep does not require retention.
*/
void esp_sleep_cpu_skip_retention(void);
#endif // !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU
#endif // !CONFIG_FREERTOS_UNICORE && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
#ifdef __cplusplus
}

8
components/esp_hw_support/include/esp_sleep.h
View File

@@ -72,7 +72,7 @@ typedef enum {
#if SOC_PM_SUPPORT_RC_FAST_PD
ESP_PD_DOMAIN_RC_FAST, //!< Internal Fast oscillator
#endif
#if SOC_PM_SUPPORT_CPU_PD
#if SOC_PM_SUPPORT_CPU_PD && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
ESP_PD_DOMAIN_CPU, //!< CPU core
#endif
#if SOC_PM_SUPPORT_VDDSDIO_PD
@@ -140,8 +140,6 @@ enum {
ESP_ERR_SLEEP_TOO_SHORT_SLEEP_DURATION = ESP_ERR_INVALID_ARG,
};
#define ESP_SLEEP_POWER_DOWN_CPU (CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || (SOC_CPU_IN_TOP_DOMAIN && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
/**
* @brief Disable wakeup source
*
@@ -777,7 +775,7 @@ void esp_deep_sleep_disable_rom_logging(void);
void esp_sleep_enable_lowpower_analog_mode(bool enable);
#endif
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
#if SOC_PM_CPU_RETENTION_BY_RTCCNTL
/**
@@ -816,7 +814,7 @@ esp_err_t esp_sleep_cpu_retention_init(void);
* Release system retention memory.
*/
esp_err_t esp_sleep_cpu_retention_deinit(void);
#endif // ESP_SLEEP_POWER_DOWN_CPU
#endif // CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
/**
* @brief Configure to isolate all GPIO pins in sleep state

2
components/esp_hw_support/lowpower/CMakeLists.txt
View File

@@ -7,7 +7,7 @@ endif()
set(srcs)
if(CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP OR
(CONFIG_SOC_CPU_IN_TOP_DOMAIN AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
(CONFIG_ESP32P4_SELECTS_REV_LESS_V3 AND CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
list(APPEND srcs "port/${target}/sleep_cpu.c")
if(CONFIG_PM_CPU_RETENTION_DYNAMIC)
list(APPEND srcs "port/${target}/sleep_cpu_dynamic.c")

2
components/esp_hw_support/lowpower/port/esp32c3/sleep_cpu.c
View File

@@ -101,7 +101,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

2
components/esp_hw_support/lowpower/port/esp32c5/sleep_cpu.c
View File

@@ -339,7 +339,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

2
components/esp_hw_support/lowpower/port/esp32c6/sleep_cpu.c
View File

@@ -363,7 +363,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

2
components/esp_hw_support/lowpower/port/esp32c61/sleep_cpu.c
View File

@@ -339,7 +339,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

2
components/esp_hw_support/lowpower/port/esp32h2/sleep_cpu.c
View File

@@ -363,7 +363,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

2
components/esp_hw_support/lowpower/port/esp32h21/sleep_cpu.c
View File

@@ -359,7 +359,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

20
components/esp_hw_support/lowpower/port/esp32h4/sleep_cpu.c
View File

@@ -38,7 +38,7 @@
#include "hal/uart_hal.h"
#endif
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
static DRAM_ATTR smp_retention_state_t s_smp_retention_state[portNUM_PROCESSORS];
#endif
@@ -344,7 +344,7 @@ static IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
#endif
REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_DONE);
while (atomic_load(&s_smp_retention_state[!core_id]) != SMP_BACKUP_DONE) {
;
@@ -367,7 +367,7 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
{
esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
uint8_t core_id = esp_cpu_get_core_id();
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
#endif
@@ -388,7 +388,7 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
validate_retention_frame_crc((uint32_t*)frame, sizeof(RvCoreNonCriticalSleepFrame) - sizeof(long), (uint32_t *)(&frame->frame_crc));
#endif
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
// Start core1
if (core_id == 0) {
REG_SET_BIT(PCR_CORE1_CONF_REG, PCR_CORE1_CLK_EN);
@@ -403,7 +403,7 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clint_frame[core_id]);
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_DONE);
#endif
return err;
@@ -411,7 +411,7 @@ esp_err_t IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uin
esp_err_t esp_sleep_cpu_retention_init(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
return esp_sleep_cpu_retention_init_impl(& s_cpu_retention, s_smp_retention_state);
#else
return esp_sleep_cpu_retention_init_impl(& s_cpu_retention);
@@ -440,7 +440,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {
@@ -451,7 +451,7 @@ esp_err_t sleep_cpu_configure(bool light_sleep_enable)
}
#if !CONFIG_FREERTOS_UNICORE
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
static IRAM_ATTR void smp_core_do_retention(void)
{
uint8_t core_id = esp_cpu_get_core_id();
@@ -527,7 +527,7 @@ IRAM_ATTR void esp_sleep_cpu_skip_retention(void) {
void sleep_smp_cpu_sleep_prepare(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
while (atomic_load(&s_smp_retention_state[!esp_cpu_get_core_id()]) != SMP_IDLE) {
;
}
@@ -539,7 +539,7 @@ void sleep_smp_cpu_sleep_prepare(void)
void sleep_smp_cpu_wakeup_prepare(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
uint8_t core_id = esp_cpu_get_core_id();
if (atomic_load(&s_smp_retention_state[core_id]) == SMP_RESTORE_DONE) {
ESP_COMPILER_DIAGNOSTIC_PUSH_IGNORE("-Wanalyzer-infinite-loop")

2
components/esp_hw_support/lowpower/port/esp32h4/sleep_cpu_dynamic.c
View File

@@ -73,7 +73,7 @@ static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
return cpu_domain_dev_sleep_frame_alloc_and_init(regions[core_id], sizeof(regions[core_id]) / sizeof(regions[core_id][0]));
}
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state)
{
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {

4
components/esp_hw_support/lowpower/port/esp32h4/sleep_cpu_retention.h
View File

@@ -11,7 +11,7 @@
#include "freertos/FreeRTOS.h"
#include "esp_err.h"
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#include <stdatomic.h>
#include "soc/hp_system_reg.h"
typedef enum {
@@ -48,7 +48,7 @@ typedef struct {
} retent;
} sleep_cpu_retention_t;
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state);
#else
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr);

2
components/esp_hw_support/lowpower/port/esp32h4/sleep_cpu_static.c
View File

@@ -142,7 +142,7 @@ static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
return cpu_domain_dev_sleep_frame_alloc_and_init(regions[core_id], sizeof(regions[core_id]) / sizeof(regions[core_id][0]), sleep_frame[core_id]);
}
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state)
{
static DRAM_ATTR uint8_t rv_core_critical_regs[RV_SLEEP_CTX_FRMSZ * portNUM_PROCESSORS] __attribute__((aligned(4)));

3
components/esp_hw_support/lowpower/port/esp32p4/rvsleep-frames.h
View File

@@ -80,6 +80,9 @@ STRUCT_BEGIN
STRUCT_FIELD (long, 4, RV_SLP_CTX_MSTATUS, mstatus) /* Machine Status */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVEC, mtvec) /* Machine Trap-Vector Base Address */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVT, mtvt)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
STRUCT_FIELD (long, 4, RV_SLP_CTX_MINTTHRESH, mintthresh) /* Machine intr threshold */ // TODO
#endif
STRUCT_FIELD (long, 4, RV_SLP_CTX_MCAUSE, mcause) /* Machine Trap Cause */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MTVAL, mtval) /* Machine Trap Value */
STRUCT_FIELD (long, 4, RV_SLP_CTX_MIE, mie) /* Machine intr enable */

20
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c
View File

@@ -39,7 +39,7 @@
#endif
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
static TCM_DRAM_ATTR smp_retention_state_t s_smp_retention_state[portNUM_PROCESSORS];
#endif
@@ -269,7 +269,7 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
#endif
REG_WRITE(RTC_SLEEP_WAKE_STUB_ADDR_REG, (uint32_t)rv_core_critical_regs_restore);
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_DONE);
while (atomic_load(&s_smp_retention_state[!core_id]) != SMP_BACKUP_DONE) {
;
@@ -292,7 +292,7 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
{
esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
uint8_t core_id = esp_cpu_get_core_id();
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_BACKUP_START);
#endif
cpu_domain_dev_regs_save(s_cpu_retention.retent.clic_frame[core_id]);
@@ -310,7 +310,7 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
validate_retention_frame_crc((uint32_t*)frame, sizeof(RvCoreNonCriticalSleepFrame) - sizeof(long), (uint32_t *)(&frame->frame_crc));
#endif
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
// Start core1
if (core_id == 0) {
REG_SET_BIT(HP_SYS_CLKRST_SOC_CLK_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_CPU_CLK_EN);
@@ -323,7 +323,7 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
cpu_domain_dev_regs_restore(s_cpu_retention.retent.clic_frame[core_id]);
rv_core_noncritical_regs_restore();
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
atomic_store(&s_smp_retention_state[core_id], SMP_RESTORE_DONE);
#endif
return err;
@@ -331,7 +331,7 @@ esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t,
esp_err_t esp_sleep_cpu_retention_init(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
return esp_sleep_cpu_retention_init_impl(& s_cpu_retention, s_smp_retention_state);
#else
return esp_sleep_cpu_retention_init_impl(& s_cpu_retention);
@@ -358,7 +358,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {
@@ -369,7 +369,7 @@ esp_err_t sleep_cpu_configure(bool light_sleep_enable)
}
#if !CONFIG_FREERTOS_UNICORE
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
static TCM_IRAM_ATTR void smp_core_do_retention(void)
{
uint8_t core_id = esp_cpu_get_core_id();
@@ -439,7 +439,7 @@ TCM_IRAM_ATTR void esp_sleep_cpu_skip_retention(void) {
void sleep_smp_cpu_sleep_prepare(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
while (atomic_load(&s_smp_retention_state[!esp_cpu_get_core_id()]) != SMP_IDLE) {
;
}
@@ -451,7 +451,7 @@ void sleep_smp_cpu_sleep_prepare(void)
void sleep_smp_cpu_wakeup_prepare(void)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
uint8_t core_id = esp_cpu_get_core_id();
if (atomic_load(&s_smp_retention_state[core_id]) == SMP_RESTORE_DONE) {
while (atomic_load(&s_smp_retention_state[!core_id]) != SMP_RESTORE_DONE) {

11
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,7 @@
#include "soc/cache_reg.h"
#define CACHE_MAP_L1_CACHE_MASK (BIT(0) | BIT(1) | BIT(4))
#define MTVT (0x307)
#define MINTTHRESH (0x347)
.section .tcm.data,"aw"
.global rv_core_critical_regs_frame
@@ -93,6 +94,10 @@ rv_core_critical_regs_save:
sw t3, RV_SLP_CTX_MCAUSE(t0)
csrr t4, MTVT
sw t4, RV_SLP_CTX_MTVT(t0)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
csrr t4, MINTTHRESH
sw t4, RV_SLP_CTX_MINTTHRESH(t0)
#endif
csrr t1, mtval
sw t1, RV_SLP_CTX_MTVAL(t0)
csrr t2, mie
@@ -177,6 +182,10 @@ rv_core_critical_regs_restore:
csrw mstatus, t2
lw t4, RV_SLP_CTX_MTVT(t0)
csrw MTVT, t4
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lw t1, RV_SLP_CTX_MINTTHRESH(t0)
csrw MINTTHRESH, t1
#endif
lw t3, RV_SLP_CTX_MTVEC(t0)
csrw mtvec, t3
lw t1, RV_SLP_CTX_MCAUSE(t0)

2
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_dynamic.c
View File

@@ -50,7 +50,7 @@ static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
return cpu_domain_dev_sleep_frame_alloc_and_init(regions[core_id], sizeof(regions[core_id]) / sizeof(cpu_domain_dev_regs_region_t));
}
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state)
{
for (uint8_t core_id = 0; core_id < portNUM_PROCESSORS; ++core_id) {

4
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_retention.h
View File

@@ -11,7 +11,7 @@
#include "freertos/FreeRTOS.h"
#include "esp_err.h"
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#include <stdatomic.h>
#include "soc/hp_system_reg.h"
typedef enum {
@@ -46,7 +46,7 @@ typedef struct {
} retent;
} sleep_cpu_retention_t;
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state);
#else
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr);

2
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_static.c
View File

@@ -82,7 +82,7 @@ static inline void * cpu_domain_clic_sleep_frame_alloc_and_init(uint8_t core_id)
return cpu_domain_dev_sleep_frame_alloc_and_init(regions[core_id], sizeof(regions[core_id]) / sizeof(regions[core_id][0]), sleep_frame[core_id]);
}
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
esp_err_t esp_sleep_cpu_retention_init_impl(sleep_cpu_retention_t *sleep_cpu_retention_ptr, smp_retention_state_t *s_smp_retention_state)
{
static DRAM_ATTR uint8_t rv_core_critical_regs[RV_SLEEP_CTX_FRMSZ * portNUM_PROCESSORS] __attribute__((aligned(4)));

2
components/esp_hw_support/lowpower/port/esp32s3/sleep_cpu.c
View File

@@ -231,7 +231,7 @@ bool cpu_domain_pd_allowed(void)
esp_err_t sleep_cpu_configure(bool light_sleep_enable)
{
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
if (light_sleep_enable) {
ESP_RETURN_ON_ERROR(esp_sleep_cpu_retention_init(), TAG, "Failed to enable CPU power down during light sleep.");
} else {

1
components/esp_hw_support/port/esp32p4/pmu_init.c
View File

@@ -133,6 +133,7 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
PMU_HP_PD_TOP,
PMU_HP_PD_CNNT,
PMU_HP_PD_HPMEM,
PMU_HP_PD_CPU
};
for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {

5
components/esp_hw_support/port/esp32p4/pmu_sleep.c
View File

@@ -160,7 +160,9 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
)
{
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
power_default.hp_sys.dig_power.cpu_pd_en = (sleep_flags & PMU_SLEEP_PD_CPU) ? 1 : 0;
#endif
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
@@ -204,6 +206,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
}
power_default.hp_sys.dig_power.dcdc_switch_pd_en = 0;
analog_default.hp_sys.analog.dcm_vset = CONFIG_ESP_SLEEP_DCM_VSET_VAL_IN_SLEEP;
analog_default.hp_sys.analog.xpd = 0;
if (sleep_flags & PMU_SLEEP_PD_VDDSDIO) {
analog_default.hp_sys.analog.xpd_0p1a = 0;
} else {

5
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
View File

@@ -118,7 +118,12 @@ typedef union {
uint32_t dcdc_switch_pd_en: 1;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 1;
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
uint32_t reserved1 : 6;
#else
uint32_t reserved1 : 5;
uint32_t cpu_pd_en : 1;
#endif
uint32_t cnnt_pd_en : 1;
uint32_t top_pd_en : 1;
};

5
components/esp_hw_support/port/regdma_link.c
View File

@@ -10,6 +10,7 @@
#include <sys/cdefs.h>
#include <inttypes.h>
#include "sdkconfig.h"
#include "esp_private/regdma_link.h"
#include "esp_heap_caps.h"
@@ -20,7 +21,11 @@
#define REGDMA_LINK_ADDR_ALIGN (4)
#if CONFIG_IDF_TARGET_ESP32P4
#define REGDMA_LINK_MEM_TYPE_CAPS (MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION)
#else
#define REGDMA_LINK_MEM_TYPE_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
#endif
void * regdma_link_new_continuous(void *backup, void *buff, int len, void *restore, void *next, bool skip_b, bool skip_r, int id, int module)
{

18
components/esp_hw_support/sleep_modes.c
View File

@@ -932,14 +932,14 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
#endif
#if SOC_PMU_SUPPORTED
#if SOC_PM_CPU_RETENTION_BY_SW && ESP_SLEEP_POWER_DOWN_CPU
#if SOC_PM_CPU_RETENTION_BY_SW && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
esp_sleep_execute_event_callbacks(SLEEP_EVENT_HW_GOTO_SLEEP, (void *)0);
if (sleep_flags & (PMU_SLEEP_PD_CPU | PMU_SLEEP_PD_TOP)) {
result = esp_sleep_cpu_retention(pmu_sleep_start, s_config.wakeup_triggers, reject_triggers, config->power.hp_sys.dig_power.mem_dslp, deep_sleep);
} else
#endif
{
#if !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
#if !CONFIG_FREERTOS_UNICORE && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
// Skip smp retention if CPU power domain power-down is not allowed
esp_sleep_cpu_skip_retention();
#endif
@@ -1136,7 +1136,7 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t cl
if (should_skip_sleep) {
result = ESP_ERR_SLEEP_REJECT;
#if ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE && SOC_PM_CPU_RETENTION_BY_SW
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE && SOC_PM_CPU_RETENTION_BY_SW
esp_sleep_cpu_skip_retention();
#endif
} else {
@@ -1438,7 +1438,7 @@ esp_err_t esp_light_sleep_start(void)
#endif
#if !CONFIG_FREERTOS_UNICORE
#if ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
sleep_smp_cpu_sleep_prepare();
#else
esp_ipc_isr_stall_other_cpu();
@@ -1601,7 +1601,7 @@ esp_err_t esp_light_sleep_start(void)
}
esp_set_time_from_rtc();
} else {
#if !CONFIG_FREERTOS_UNICORE && ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
#if !CONFIG_FREERTOS_UNICORE && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
esp_sleep_cpu_skip_retention();
#endif
}
@@ -1618,7 +1618,7 @@ esp_err_t esp_light_sleep_start(void)
#if !CONFIG_FREERTOS_UNICORE
esp_ipc_isr_stall_resume();
#if ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW
sleep_smp_cpu_wakeup_prepare();
#else
esp_ipc_isr_release_other_cpu();
@@ -2558,7 +2558,7 @@ esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option
#if SOC_PM_SUPPORT_TOP_PD && SOC_PAU_SUPPORTED
FORCE_INLINE_ATTR bool top_domain_pd_allowed(void) {
bool top_pd_allowed = true;
#if ESP_SLEEP_POWER_DOWN_CPU
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
top_pd_allowed &= cpu_domain_pd_allowed();
#else
top_pd_allowed = false;
@@ -2689,7 +2689,7 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
}
#endif
#if SOC_PM_SUPPORT_CPU_PD && ESP_SLEEP_POWER_DOWN_CPU
#if SOC_PM_SUPPORT_CPU_PD && CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if ((s_config.domain[ESP_PD_DOMAIN_CPU].pd_option != ESP_PD_OPTION_ON) && cpu_domain_pd_allowed()) {
pd_flags |= RTC_SLEEP_PD_CPU;
}
@@ -2733,7 +2733,7 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
#endif
#if SOC_PM_SUPPORT_CNNT_PD
if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON) {
if (s_config.domain[ESP_PD_DOMAIN_CNNT].pd_option != ESP_PD_OPTION_ON && top_domain_pd_allowed()) {
pd_flags |= PMU_SLEEP_PD_CNNT;
}
#endif

6
components/esp_hw_support/sleep_usb.c
View File

@@ -16,7 +16,7 @@
#if SOC_USB_OTG_SUPPORTED
#if SOC_PM_SUPPORT_CNNT_PD
static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state;
static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state, s_usb_dwc_bvalid_override;
void sleep_usb_otg_phy_backup_and_disable(void)
{
@@ -24,6 +24,9 @@ void sleep_usb_otg_phy_backup_and_disable(void)
if (!s_usb_utmi_bus_clock_state) {
_usb_utmi_ll_enable_bus_clock(true);
}
// Forcing BVALID low to ignore the hardware-detected VBUS BVALID signal to suppress USB leakage.
s_usb_dwc_bvalid_override = usb_dwc_ll_get_bvalid_override(&USB_DWC_HS);
usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, true);
s_usb_utmi_stoppclk_state = usb_dwc_ll_get_stoppclk_st(&USB_DWC_HS);
usb_dwc_ll_set_stoppclk(&USB_DWC_HS, true);
}
@@ -31,6 +34,7 @@ void sleep_usb_otg_phy_backup_and_disable(void)
void sleep_usb_otg_phy_restore(void)
{
_usb_utmi_ll_enable_bus_clock(true);
usb_dwc_ll_enable_bvalid_override(&USB_DWC_HS, s_usb_dwc_bvalid_override);
usb_dwc_ll_set_stoppclk(&USB_DWC_HS, s_usb_utmi_stoppclk_state);
if (!s_usb_utmi_bus_clock_state) {
_usb_utmi_ll_enable_bus_clock(false);

16
components/esp_pm/Kconfig
View File

@@ -94,7 +94,7 @@ menu "Power Management"
config PM_CHECK_SLEEP_RETENTION_FRAME
bool
depends on (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || \
(SOC_CPU_IN_TOP_DOMAIN && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
(ESP32P4_SELECTS_REV_LESS_V3 && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP))
default y if IDF_CI_BUILD
default n
help
@@ -117,7 +117,7 @@ menu "Power Management"
config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
bool "Power down CPU in light sleep"
depends on SOC_PM_SUPPORT_CPU_PD
depends on SOC_PM_SUPPORT_CPU_PD && !ESP32P4_SELECTS_REV_LESS_V3
select PM_RESTORE_CACHE_TAGMEM_AFTER_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
default y
help
@@ -132,8 +132,9 @@ menu "Power Management"
choice
bool "Retentive memory alloaction strategy for light sleep"
depends on SOC_PM_CPU_RETENTION_BY_SW && \
(PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || (PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && SOC_CPU_IN_TOP_DOMAIN))
depends on SOC_PM_CPU_RETENTION_BY_SW
depends on PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP || \
(PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP32P4_SELECTS_REV_LESS_V3)
default PM_CPU_RETENTION_DYNAMIC
help
In light sleep mode, certain CPU states and data need to be preserved in memory while cpu domain
@@ -177,7 +178,7 @@ menu "Power Management"
config PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
bool "Power down Digital Peripheral in light sleep (EXPERIMENTAL)"
depends on SOC_PM_SUPPORT_TOP_PD && SOC_PAU_SUPPORTED
select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !SOC_CPU_IN_TOP_DOMAIN
select PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP if !ESP32P4_SELECTS_REV_LESS_V3
default n #TODO: enable by default if periph init/deinit management supported (WIFI-5252)
help
If enabled, digital peripherals will try to powered down in light sleep, then all related peripherals will
@@ -213,6 +214,11 @@ menu "Power Management"
If any module belonging to the peripheral power domain chooses not to be powered down during sleep,
then the peripheral power domain will not be powered off either.
config PM_ESP_SLEEP_POWER_DOWN_CPU
bool
default y if (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP && !ESP32P4_SELECTS_REV_LESS_V3)
default y if (PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP && ESP32P4_SELECTS_REV_LESS_V3)
config PM_UPDATE_CCOMPARE_HLI_WORKAROUND
bool
default y if PM_ENABLE && BTDM_CTRL_HLI

2
components/esp_pm/linker.lf
View File

@@ -31,7 +31,7 @@ entries:
sleep_system_peripheral:peripheral_domain_pd_allowed (noflash)
if SOC_PM_CPU_RETENTION_BY_RTCCNTL = y && (PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || SOC_PM_SUPPORT_TAGMEM_PD = y):
sleep_cpu:sleep_enable_cpu_retention (noflash)
if PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || (SOC_CPU_IN_TOP_DOMAIN = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y):
if PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y || (ESP32P4_SELECTS_REV_LESS_V3 = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y):
sleep_cpu:cpu_domain_pd_allowed (noflash)
if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD = y && PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP = y:
sleep_mmu:mmu_domain_pd_allowed (noflash)

2
components/esp_pm/pm_impl.c
View File

@@ -380,7 +380,7 @@ static esp_err_t esp_pm_sleep_configure(const esp_pm_config_t *config)
{
esp_err_t err = ESP_OK;
#if ESP_SLEEP_POWER_DOWN_CPU && CONFIG_SOC_LIGHT_SLEEP_SUPPORTED
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && CONFIG_SOC_LIGHT_SLEEP_SUPPORTED
err = sleep_cpu_configure(config->light_sleep_enable);
if (err != ESP_OK) {
return err;

49
components/hal/esp32p4/include/hal/pmu_ll.h
View File

@@ -16,6 +16,7 @@
#include "soc/pmu_struct.h"
#include "hal/pmu_types.h"
#include "hal/misc.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -379,32 +380,68 @@ FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_a
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
{
hw->power.hp_pd[domain].force_reset = rst;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_reset = rst;
#endif
} else {
hw->power.hp_pd[domain].force_reset = rst;
}
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
{
hw->power.hp_pd[domain].force_iso = iso;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_iso = iso;
#endif
} else {
hw->power.hp_pd[domain].force_iso = iso;
}
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
{
hw->power.hp_pd[domain].force_pu = fpu;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_pu = fpu;
#endif
} else {
hw->power.hp_pd[domain].force_pu = fpu;
}
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
{
hw->power.hp_pd[domain].force_no_reset = no_rst;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_reset = no_rst;
#endif
} else {
hw->power.hp_pd[domain].force_no_reset = no_rst;
}
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
{
hw->power.hp_pd[domain].force_no_iso = no_iso;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_no_iso = no_iso;
#endif
} else {
hw->power.hp_pd[domain].force_no_iso = no_iso;
}
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
{
hw->power.hp_pd[domain].force_pd = fpd;
if (domain == PMU_HP_PD_CPU) {
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
hw->power_pd_hp_cpu_cntl.force_hp_cpu_pd = fpd;
#endif
} else {
hw->power.hp_pd[domain].force_pd = fpd;
}
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)

22
components/hal/esp32p4/include/hal/usb_dwc_ll.h
View File

@@ -1028,6 +1028,28 @@ static inline void usb_dwc_ll_qtd_get_status(usb_dwc_ll_dma_qtd_t *qtd, int *rem
qtd->buffer_status_val = 0;
}
/**
* @brief Get the current BVALID override configuration.
*
* @param[out] Get the current BVALID override configuration.
*/
FORCE_INLINE_ATTR bool usb_dwc_ll_get_bvalid_override(usb_dwc_dev_t *hw)
{
return hw->gotgctl_reg.bvalidoven;
}
/**
* @brief Enable BVALID override in USB OTG controller.
*
* When enabled, the controller ignores the hardware-detected VBUS BVALID signal
* and uses the software-defined override value instead. This is typically used
* to reduce USB leakage current during sleep by forcing BVALID low.
*/
FORCE_INLINE_ATTR void usb_dwc_ll_enable_bvalid_override(usb_dwc_dev_t *hw, bool override)
{
hw->gotgctl_reg.bvalidoven = override;
}
// ---------------------------- Power and Clock Gating Register --------------------------------
FORCE_INLINE_ATTR void usb_dwc_ll_set_stoppclk(usb_dwc_dev_t *hw, bool stop)
{

2
components/hal/include/hal/pmu_types.h
View File

@@ -8,6 +8,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -40,6 +41,7 @@ typedef enum {
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
PMU_HP_PD_CNNT = 1, /*!< Power domain of high-speed IO peripherals such as USB/SDIO/Ethernet etc.*/
PMU_HP_PD_HPMEM = 2,
PMU_HP_PD_CPU = 3,
} pmu_hp_power_domain_t;
#else
typedef enum {

37
components/heap/port/esp32p4/memory_layout.c
View File

@@ -26,10 +26,18 @@
/* Index of memory in `soc_memory_types[]` */
enum {
SOC_MEMORY_TYPE_L2MEM = 0,
SOC_MEMORY_TYPE_SPIRAM = 1,
SOC_MEMORY_TYPE_TCM = 2,
SOC_MEMORY_TYPE_RTCRAM = 3,
SOC_MEMORY_TYPE_L2MEM = 0,
/**
* The L2 memory that regdma can access regardless of the l2 cache size. After PD_TOP sleep, the cache
* occupancy MEM configuration is reset, regdma allocates linked list memory from here to avoid being
* unable to access the linked list memory occupied by cache after reset.
* For esp32p4 chips with version < V3.0, the hardware default size of the L2 Cache is 256KB.
* For esp32p4 chips with version >= V3.0, the hardware default size of the L2 Cache is 128KB.
*/
SOC_MEMORY_TYPE_RETENT_MEM = 1,
SOC_MEMORY_TYPE_SPIRAM = 2,
SOC_MEMORY_TYPE_TCM = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};
@@ -54,11 +62,12 @@ enum {
* in turn to continue matching.
*/
const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
/* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }},
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }},
[SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}},
/* Mem Type Name | High Priority Matching | Medium Priority Matching | Low Priority Matching */
[SOC_MEMORY_TYPE_RETENT_MEM] = { "RETENT_RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_RETENTION | MALLOC_CAP_SIMD, 0, 0 }},
[SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }},
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }},
[SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}},
};
const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@@ -96,14 +105,14 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available
{ SOC_EXTRAM_LOW, SOC_EXTRAM_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0, false}, //PSRAM, if available
#endif
{ SOC_DRAM_USABLE_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_USABLE_LOW, SOC_MEMORY_TYPE_L2MEM, SOC_IRAM_USABLE_LOW, false},
{ APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true},
{ SOC_DRAM_USABLE_LOW, APP_USABLE_DIRAM_END - SOC_DRAM_USABLE_LOW, SOC_MEMORY_TYPE_RETENT_MEM, SOC_IRAM_USABLE_LOW, false},
{ APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE, SOC_MEMORY_TYPE_L2MEM, APP_USABLE_DIRAM_END, true},
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
{ 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false},
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false},
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);

8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1915,6 +1915,10 @@ config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
bool
default y
config SOC_PM_SUPPORT_CPU_PD
bool
default y
config SOC_PM_SUPPORT_XTAL32K_PD
bool
default y
@@ -1967,10 +1971,6 @@ config SOC_PAU_IN_TOP_DOMAIN
bool
default y
config SOC_CPU_IN_TOP_DOMAIN
bool
default y
config SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE
bool
default y

2
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -721,6 +721,7 @@
#define SOC_PM_EXT1_WAKEUP_BY_PMU (1)
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
@@ -737,7 +738,6 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_MULTI_ADDR (1)
#define SOC_PAU_IN_TOP_DOMAIN (1)
#define SOC_CPU_IN_TOP_DOMAIN (1)
#define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1)
#define SOC_SLEEP_SYSTIMER_STALL_WORKAROUND 1 //TODO IDF-11381: replace with all xtal field clk gate control

2
components/soc/esp32p4/include/soc/system_periph_retention.h
View File

@@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define CACHE_RETENTION_LINK_LEN 8
#define CACHE_RETENTION_LINK_LEN 10
extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN];
/**

2
components/soc/esp32p4/register/hw_ver1/soc/pmu_struct.h
View File

@@ -7,7 +7,7 @@
#include <stddef.h>
#include <stdint.h>
#include "soc/pmu_reg.h"
#include "pmu_reg.h"
#ifdef __cplusplus
extern "C" {
#endif

1
components/soc/esp32p4/register/hw_ver3/soc/cache_reg.h
View File

@@ -5,7 +5,6 @@
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {

191
components/soc/esp32p4/register/hw_ver3/soc/pmu_reg.h
View File

@@ -11,8 +11,6 @@
extern "C" {
#endif
//TODO: IDF-13420
/** PMU_HP_ACTIVE_DIG_POWER_REG register
* need_des
*/
@@ -38,6 +36,13 @@ extern "C" {
#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_M (PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V << PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S)
#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_V 0x00000001U
#define PMU_HP_ACTIVE_PD_HP_MEM_PD_EN_S 23
/** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN (BIT(29))
#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_M (PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V << PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S)
#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_V 0x00000001U
#define PMU_HP_ACTIVE_PD_HP_CPU_PD_EN_S 29
/** PMU_HP_ACTIVE_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
@@ -514,7 +519,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_MODEM_ICG_HP_FUNC_REG (DR_REG_PMU_BASE + 0x38)
/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 4294967295;
/** PMU_HP_MODEM_DIG_ICG_FUNC_EN : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_ICG_FUNC_EN 0xFFFFFFFFU
@@ -526,7 +531,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_MODEM_ICG_HP_APB_REG (DR_REG_PMU_BASE + 0x3c)
/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 4294967295;
/** PMU_HP_MODEM_DIG_ICG_APB_EN : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DIG_ICG_APB_EN 0xFFFFFFFFU
@@ -637,7 +642,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c)
/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 20;
/** PMU_HP_MODEM_DCM_VSET : WT; bitpos: [22:18]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_DCM_VSET 0x0000001FU
@@ -783,42 +788,42 @@ extern "C" {
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR0_REG (DR_REG_PMU_BASE + 0x5c)
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 1;
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD : WT; bitpos: [16]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD (BIT(16))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_S 16
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 1;
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD : WT; bitpos: [17]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD (BIT(17))
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_S 17
/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 1;
/** PMU_HP_MODEM_HP_REGULATOR_XPD : WT; bitpos: [18]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_XPD (BIT(18))
#define PMU_HP_MODEM_HP_REGULATOR_XPD_M (PMU_HP_MODEM_HP_REGULATOR_XPD_V << PMU_HP_MODEM_HP_REGULATOR_XPD_S)
#define PMU_HP_MODEM_HP_REGULATOR_XPD_V 0x00000001U
#define PMU_HP_MODEM_HP_REGULATOR_XPD_S 18
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 12;
/** PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS : WT; bitpos: [22:19]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_V 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_S 19
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 12;
/** PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS : WT; bitpos: [26:23]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_M (PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V << PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S)
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_V 0x0000000FU
#define PMU_HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_S 23
/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 24;
/** PMU_HP_MODEM_HP_REGULATOR_DBIAS : WT; bitpos: [31:27]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_HP_REGULATOR_DBIAS 0x0000001FU
@@ -842,7 +847,7 @@ extern "C" {
* need_des
*/
#define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64)
/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 1;
/** PMU_HP_MODEM_XPD_XTAL : WT; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_HP_MODEM_XPD_XTAL (BIT(31))
@@ -875,6 +880,13 @@ extern "C" {
#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_M (PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V << PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S)
#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_V 0x00000001U
#define PMU_HP_SLEEP_PD_HP_MEM_PD_EN_S 23
/** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN (BIT(29))
#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_M (PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V << PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S)
#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_V 0x00000001U
#define PMU_HP_SLEEP_PD_HP_CPU_PD_EN_S 29
/** PMU_HP_SLEEP_PD_CNNT_PD_EN : R/W; bitpos: [30]; default: 0;
* need_des
*/
@@ -1310,6 +1322,18 @@ extern "C" {
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000003FU
#define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 26
/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register
* need_des
*/
#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4)
/** PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU
#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_S)
#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU
#define PMU_PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0
/** PMU_HP_SLEEP_LP_DIG_POWER_REG register
* need_des
*/
@@ -1390,6 +1414,18 @@ extern "C" {
#define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U
#define PMU_HP_SLEEP_PD_OSC_CLK_S 31
/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register
* need_des
*/
#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0)
/** PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0;
* need_des
*/
#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU
#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_S)
#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU
#define PMU_PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0
/** PMU_LP_SLEEP_LP_REGULATOR0_REG register
* need_des
*/
@@ -1571,7 +1607,7 @@ extern "C" {
#define PMU_TIE_LOW_CALI_XTAL_ICG_M (PMU_TIE_LOW_CALI_XTAL_ICG_V << PMU_TIE_LOW_CALI_XTAL_ICG_S)
#define PMU_TIE_LOW_CALI_XTAL_ICG_V 0x00000001U
#define PMU_TIE_LOW_CALI_XTAL_ICG_S 0
/** PMU_TIE_LOW_GLOBAL_CPLL_ICG : WT; bitpos: [1]; default: 0;
/** PMU_TIE_LOW_GLOBAL_PLL_ICG : WT; bitpos: [4:1]; default: 0;
* need_des
*/
#define PMU_TIE_LOW_GLOBAL_CPLL_ICG (BIT(1))
@@ -2429,6 +2465,13 @@ extern "C" {
#define PMU_MODEM_WAIT_TARGET_M (PMU_MODEM_WAIT_TARGET_V << PMU_MODEM_WAIT_TARGET_S)
#define PMU_MODEM_WAIT_TARGET_V 0x000FFFFFU
#define PMU_MODEM_WAIT_TARGET_S 0
/** PMU_LP_ANA_WAIT_TARGET_EXPAND : R/W; bitpos: [23:22]; default: 0;
* need_des
*/
#define PMU_LP_ANA_WAIT_TARGET_EXPAND 0x00000003U
#define PMU_LP_ANA_WAIT_TARGET_EXPAND_M (PMU_LP_ANA_WAIT_TARGET_EXPAND_V << PMU_LP_ANA_WAIT_TARGET_EXPAND_S)
#define PMU_LP_ANA_WAIT_TARGET_EXPAND_V 0x00000003U
#define PMU_LP_ANA_WAIT_TARGET_EXPAND_S 22
/** PMU_LP_ANA_WAIT_TARGET : R/W; bitpos: [31:24]; default: 1;
* need_des
*/
@@ -2551,7 +2594,7 @@ extern "C" {
* need_des
*/
#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x158)
/** PMU_POR_DONE : RO; bitpos: [31]; default: 1;
/** PMU_POR_DONE : RO; bitpos: [31]; default: 0;
* need_des
*/
#define PMU_POR_DONE (BIT(31))
@@ -3857,7 +3900,7 @@ extern "C" {
#define PMU_PMU_MAIN_TAR_ST_STATE_M (PMU_PMU_MAIN_TAR_ST_STATE_V << PMU_PMU_MAIN_TAR_ST_STATE_S)
#define PMU_PMU_MAIN_TAR_ST_STATE_V 0x0000007FU
#define PMU_PMU_MAIN_TAR_ST_STATE_S 18
/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4;
/** PMU_PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1;
* need_des
*/
#define PMU_PMU_MAIN_CUR_ST_STATE 0x0000007FU
@@ -3895,14 +3938,14 @@ extern "C" {
* need_des
*/
#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac)
/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 7;
/** PMU_STABLE_XPD_PLL_STATE : RO; bitpos: [2:0]; default: 0;
* need_des
*/
#define PMU_STABLE_XPD_PLL_STATE 0x00000007U
#define PMU_STABLE_XPD_PLL_STATE_M (PMU_STABLE_XPD_PLL_STATE_V << PMU_STABLE_XPD_PLL_STATE_S)
#define PMU_STABLE_XPD_PLL_STATE_V 0x00000007U
#define PMU_STABLE_XPD_PLL_STATE_S 0
/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 1;
/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [3]; default: 0;
* need_des
*/
#define PMU_STABLE_XPD_XTAL_STATE (BIT(3))
@@ -3937,7 +3980,7 @@ extern "C" {
#define PMU_PMU_SYS_CLK_NO_DIV_STATE_M (PMU_PMU_SYS_CLK_NO_DIV_STATE_V << PMU_PMU_SYS_CLK_NO_DIV_STATE_S)
#define PMU_PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U
#define PMU_PMU_SYS_CLK_NO_DIV_STATE_S 13
/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 0;
/** PMU_PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [14]; default: 1;
* need_des
*/
#define PMU_PMU_ICG_SYS_CLK_EN_STATE (BIT(14))
@@ -4000,7 +4043,7 @@ extern "C" {
#define PMU_PMU_ANA_XPD_PLL_STATE_M (PMU_PMU_ANA_XPD_PLL_STATE_V << PMU_PMU_ANA_XPD_PLL_STATE_S)
#define PMU_PMU_ANA_XPD_PLL_STATE_V 0x0000000FU
#define PMU_PMU_ANA_XPD_PLL_STATE_S 27
/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0;
/** PMU_PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1;
* need_des
*/
#define PMU_PMU_ANA_XPD_XTAL_STATE (BIT(31))
@@ -4036,6 +4079,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P0_0P1A_REG (DR_REG_PMU_BASE + 0x1b8)
/** PMU_0P1A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P1A_CNT_CLR_0 (BIT(6))
#define PMU_0P1A_CNT_CLR_0_M (PMU_0P1A_CNT_CLR_0_V << PMU_0P1A_CNT_CLR_0_S)
#define PMU_0P1A_CNT_CLR_0_V 0x00000001U
#define PMU_0P1A_CNT_CLR_0_S 6
/** PMU_0P1A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4137,6 +4187,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P0_0P2A_REG (DR_REG_PMU_BASE + 0x1c0)
/** PMU_0P2A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P2A_CNT_CLR_0 (BIT(6))
#define PMU_0P2A_CNT_CLR_0_M (PMU_0P2A_CNT_CLR_0_V << PMU_0P2A_CNT_CLR_0_S)
#define PMU_0P2A_CNT_CLR_0_V 0x00000001U
#define PMU_0P2A_CNT_CLR_0_S 6
/** PMU_0P2A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4238,6 +4295,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P0_0P3A_REG (DR_REG_PMU_BASE + 0x1c8)
/** PMU_0P3A_CNT_CLR_0 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P3A_CNT_CLR_0 (BIT(6))
#define PMU_0P3A_CNT_CLR_0_M (PMU_0P3A_CNT_CLR_0_V << PMU_0P3A_CNT_CLR_0_S)
#define PMU_0P3A_CNT_CLR_0_V 0x00000001U
#define PMU_0P3A_CNT_CLR_0_S 6
/** PMU_0P3A_FORCE_TIEH_SEL_0 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4339,6 +4403,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P1_0P1A_REG (DR_REG_PMU_BASE + 0x1d0)
/** PMU_0P1A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P1A_CNT_CLR_1 (BIT(6))
#define PMU_0P1A_CNT_CLR_1_M (PMU_0P1A_CNT_CLR_1_V << PMU_0P1A_CNT_CLR_1_S)
#define PMU_0P1A_CNT_CLR_1_V 0x00000001U
#define PMU_0P1A_CNT_CLR_1_S 6
/** PMU_0P1A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4440,6 +4511,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P1_0P2A_REG (DR_REG_PMU_BASE + 0x1d8)
/** PMU_0P2A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P2A_CNT_CLR_1 (BIT(6))
#define PMU_0P2A_CNT_CLR_1_M (PMU_0P2A_CNT_CLR_1_V << PMU_0P2A_CNT_CLR_1_S)
#define PMU_0P2A_CNT_CLR_1_V 0x00000001U
#define PMU_0P2A_CNT_CLR_1_S 6
/** PMU_0P2A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4541,6 +4619,13 @@ extern "C" {
* need_des
*/
#define PMU_EXT_LDO_P1_0P3A_REG (DR_REG_PMU_BASE + 0x1e0)
/** PMU_0P3A_CNT_CLR_1 : WT; bitpos: [6]; default: 0;
* need_des
*/
#define PMU_0P3A_CNT_CLR_1 (BIT(6))
#define PMU_0P3A_CNT_CLR_1_M (PMU_0P3A_CNT_CLR_1_V << PMU_0P3A_CNT_CLR_1_S)
#define PMU_0P3A_CNT_CLR_1_V 0x00000001U
#define PMU_0P3A_CNT_CLR_1_S 6
/** PMU_0P3A_FORCE_TIEH_SEL_1 : R/W; bitpos: [7]; default: 0;
* need_des
*/
@@ -4943,11 +5028,77 @@ extern "C" {
#define PMU_PMU_RDN_ECO_EN_V 0x00000001U
#define PMU_PMU_RDN_ECO_EN_S 31
/** PMU_POWER_PD_HP_CPU_CNTL_REG register
* need_des
*/
#define PMU_POWER_PD_HP_CPU_CNTL_REG (DR_REG_PMU_BASE + 0x218)
/** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0;
* need_des
*/
#define PMU_FORCE_HP_CPU_RESET (BIT(0))
#define PMU_FORCE_HP_CPU_RESET_M (PMU_FORCE_HP_CPU_RESET_V << PMU_FORCE_HP_CPU_RESET_S)
#define PMU_FORCE_HP_CPU_RESET_V 0x00000001U
#define PMU_FORCE_HP_CPU_RESET_S 0
/** PMU_FORCE_HP_CPU_ISO : R/W; bitpos: [1]; default: 0;
* need_des
*/
#define PMU_FORCE_HP_CPU_ISO (BIT(1))
#define PMU_FORCE_HP_CPU_ISO_M (PMU_FORCE_HP_CPU_ISO_V << PMU_FORCE_HP_CPU_ISO_S)
#define PMU_FORCE_HP_CPU_ISO_V 0x00000001U
#define PMU_FORCE_HP_CPU_ISO_S 1
/** PMU_FORCE_HP_CPU_PU : R/W; bitpos: [2]; default: 1;
* need_des
*/
#define PMU_FORCE_HP_CPU_PU (BIT(2))
#define PMU_FORCE_HP_CPU_PU_M (PMU_FORCE_HP_CPU_PU_V << PMU_FORCE_HP_CPU_PU_S)
#define PMU_FORCE_HP_CPU_PU_V 0x00000001U
#define PMU_FORCE_HP_CPU_PU_S 2
/** PMU_FORCE_HP_CPU_NO_RESET : R/W; bitpos: [3]; default: 1;
* need_des
*/
#define PMU_FORCE_HP_CPU_NO_RESET (BIT(3))
#define PMU_FORCE_HP_CPU_NO_RESET_M (PMU_FORCE_HP_CPU_NO_RESET_V << PMU_FORCE_HP_CPU_NO_RESET_S)
#define PMU_FORCE_HP_CPU_NO_RESET_V 0x00000001U
#define PMU_FORCE_HP_CPU_NO_RESET_S 3
/** PMU_FORCE_HP_CPU_NO_ISO : R/W; bitpos: [4]; default: 1;
* need_des
*/
#define PMU_FORCE_HP_CPU_NO_ISO (BIT(4))
#define PMU_FORCE_HP_CPU_NO_ISO_M (PMU_FORCE_HP_CPU_NO_ISO_V << PMU_FORCE_HP_CPU_NO_ISO_S)
#define PMU_FORCE_HP_CPU_NO_ISO_V 0x00000001U
#define PMU_FORCE_HP_CPU_NO_ISO_S 4
/** PMU_FORCE_HP_CPU_PD : R/W; bitpos: [5]; default: 0;
* need_des
*/
#define PMU_FORCE_HP_CPU_PD (BIT(5))
#define PMU_FORCE_HP_CPU_PD_M (PMU_FORCE_HP_CPU_PD_V << PMU_FORCE_HP_CPU_PD_S)
#define PMU_FORCE_HP_CPU_PD_V 0x00000001U
#define PMU_FORCE_HP_CPU_PD_S 5
/** PMU_POWER_PD_HP_CPU_MASK_REG register
* need_des
*/
#define PMU_POWER_PD_HP_CPU_MASK_REG (DR_REG_PMU_BASE + 0x21c)
/** PMU_XPD_HP_CPU_MASK : R/W; bitpos: [4:0]; default: 0;
* need_des
*/
#define PMU_XPD_HP_CPU_MASK 0x0000001FU
#define PMU_XPD_HP_CPU_MASK_M (PMU_XPD_HP_CPU_MASK_V << PMU_XPD_HP_CPU_MASK_S)
#define PMU_XPD_HP_CPU_MASK_V 0x0000001FU
#define PMU_XPD_HP_CPU_MASK_S 0
/** PMU_PD_HP_CPU_MASK : R/W; bitpos: [31:27]; default: 0;
* need_des
*/
#define PMU_PD_HP_CPU_MASK 0x0000001FU
#define PMU_PD_HP_CPU_MASK_M (PMU_PD_HP_CPU_MASK_V << PMU_PD_HP_CPU_MASK_S)
#define PMU_PD_HP_CPU_MASK_V 0x0000001FU
#define PMU_PD_HP_CPU_MASK_S 27
/** PMU_DATE_REG register
* need_des
*/
#define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc)
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 36712768;
/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 38801456;
* need_des
*/
#define PMU_PMU_DATE 0x7FFFFFFFU

53
components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h
View File

@@ -1,25 +1,24 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/pmu_reg.h"
#include "pmu_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
//TODO: IDF-13420
typedef union {
struct {
uint32_t reserved0 : 21;
uint32_t dcdc_switch_pd_en :1;
uint32_t mem_dslp : 1;
uint32_t mem_pd_en : 1;
uint32_t reserved1 : 6;
uint32_t reserved1 : 5;
uint32_t hp_cpu_pd_en : 1;
uint32_t cnnt_pd_en : 1;
uint32_t top_pd_en : 1;
};
@@ -243,10 +242,10 @@ typedef union {
typedef struct pmu_lp_hw_regmap_t {
pmu_lp_regulator0_reg_t regulator0;
pmu_lp_regulator1_reg_t regulator1;
pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */
pmu_lp_xtal_reg_t xtal; /* HP_SLEEP: PMU_HP_SLEEP_LP_DCDC_RESERVE_REG LP_SLEEP: PMU_LP_SLEEP_XTAL_REG */
pmu_lp_dig_power_reg_t dig_power;
pmu_lp_clk_power_reg_t clk_power;
pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */
pmu_lp_bias_reg_t bias; /* HP_SLEEP: PMU_LP_SLEEP_LP_BIAS_RESERVE_REG LP_SLEEP: PMU_LP_SLEEP_BIAS_REG */
} pmu_lp_hw_regmap_t;
@@ -474,9 +473,10 @@ typedef union {
typedef union {
struct {
uint32_t modem_wait_target : 20;
uint32_t reserved0 : 4;
uint32_t lp_ana_wait_target: 8;
uint32_t modem_wait_target : 20;
uint32_t reserved0 : 2;
uint32_t lp_ana_wait_target_expand : 2;
uint32_t lp_ana_wait_target : 8;
};
uint32_t val;
} pmu_slp_wakeup_cntl5_reg_t;
@@ -703,7 +703,8 @@ typedef struct pmu_lp_ext_hw_regmap_t {
typedef union {
struct {
uint32_t reserved_0:7;
uint32_t reserved_0:6;
uint32_t cnt_clr:1;
uint32_t force_tieh_sel:1;
uint32_t xpd:1;
uint32_t tieh_sel:3;
@@ -771,9 +772,9 @@ typedef union {
typedef union {
struct {
uint32_t ana_vddbat_mode : 2;
uint32_t reserved1 : 29;
uint32_t sw_update : 1;
uint32_t module : 2;
uint32_t reserved1 : 29;
uint32_t sw_update : 1;
};
uint32_t val;
} pmu_vddbat_cfg_t;
@@ -917,8 +918,28 @@ typedef struct pmu_dev_t {
volatile uint32_t val;
} pmu_rdn_eco;
union {
struct {
volatile uint32_t force_hp_cpu_reset : 1;
volatile uint32_t force_hp_cpu_iso : 1;
volatile uint32_t force_hp_cpu_pu : 1;
volatile uint32_t force_hp_cpu_no_reset : 1;
volatile uint32_t force_hp_cpu_no_iso : 1;
volatile uint32_t force_hp_cpu_pd : 1;
volatile uint32_t reserved0 : 26;
};
volatile uint32_t val;
} power_pd_hp_cpu_cntl;
uint32_t reserved[121];
union {
struct {
volatile uint32_t xpd_hp_cpu_mask : 5;
volatile uint32_t pd_hp_cpu_mask : 27;
};
volatile uint32_t val;
} power_pd_hp_cpu_mask;
uint32_t reserved[119];
union {
struct {
@@ -934,7 +955,7 @@ extern pmu_dev_t PMU;
#ifndef __cplusplus
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_RDN_ECO_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_POWER_PD_HP_CPU_MASK_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
#endif
#ifdef __cplusplus

6
components/soc/esp32p4/system_retention_periph.c
View File

@@ -68,7 +68,11 @@ const regdma_entries_config_t cache_regs_retention[] = {
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) },
[5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) },
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
[7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) },
// Reset L2 CACHE SYNC
[8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x09), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) },
};
_Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");

3
docs/en/api-guides/low-power-mode/low-power-mode-soc.rst
View File

@@ -271,6 +271,9 @@ This section introduces the recommended configuration and configuration steps fo
- Power down CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
.. only:: esp32p4
For ESP32P4, only chips with version greater than 3.0 support powering down the CPU power domain independently.
.. only:: SOC_PM_SUPPORT_TAGMEM_PD

3
docs/zh_CN/api-guides/low-power-mode/low-power-mode-soc.rst
View File

@@ -271,6 +271,9 @@ Light-sleep 模式配置
- 关闭 CPU (:ref:`CONFIG_PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP`)
.. only:: esp32p4
对于 ESP32P4, 只有大于 3.0 版本的芯片才支持单独关闭 CPU 电源域。
.. only:: SOC_PM_SUPPORT_TAGMEM_PD