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Merge branch 'trace_encoder_hw_params' into 'master'

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Trace encoder hw params

See merge request espressif/esp-idf!52338
This commit is contained in:
morris
2026-09-04 13:42:31 +08:00
parent 1ae529d059 6f973c5ca8
commit df2192b38f
27 changed files with 306 additions and 35 deletions
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components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+8
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@@ -1619,6 +1619,10 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1634,3 +1638,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
components/soc/esp32c5/include/soc/soc_caps.h
+2
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@@ -645,7 +645,9 @@
#define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED (1) /*!< LP UART wakeup source is kept triggered */
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+8
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@@ -1355,6 +1355,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32c6/include/soc/soc_caps.h
+2
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@@ -549,4 +549,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -1239,6 +1239,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1254,3 +1258,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
components/soc/esp32c61/include/soc/soc_caps.h
+2
View File
@@ -499,10 +499,12 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
/*------------------------------------- No Reset CAPS -------------------------------------*/
// \#define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) //TODO: [ESP32C61] IDF-9254
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -1251,6 +1251,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32h2/include/soc/soc_caps.h
+2
View File
@@ -530,4 +530,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -1151,6 +1151,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 100
config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 5
components/soc/esp32h21/include/soc/soc_caps.h
+2
View File
@@ -499,4 +499,6 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (100) /*!< Processor Trace v1.0 */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (5) /*!< Bits in the exception cause field (ecause_width_p) */
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+8
View File
@@ -1387,6 +1387,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1403,6 +1407,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_ASRC_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+2
View File
@@ -570,10 +570,12 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
/*---------------------------------- ASRC CAPS ----------------------------------*/
#define SOC_ASRC_SUPPORTED (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+8
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@@ -1935,6 +1935,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1951,6 +1955,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 1
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+2
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@@ -740,8 +740,10 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (1U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
#define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+8
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@@ -1867,6 +1867,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
bool
default y
config SOC_RISCV_TRACE_PACKET_FORMAT_VER
int
default 200
config SOC_RISCV_TRACE_HAS_CONFIG_REG
bool
default y
@@ -1883,6 +1887,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
int
default 2
config SOC_RISCV_TRACE_ECAUSE_WIDTH
int
default 6
config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+2
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@@ -695,8 +695,10 @@
#define SOC_DEBUG_HAVE_OCD_STUB_BINS (1)
/*-------------------------- RISC-V TRACE CAPS ------------------------------*/
#define SOC_RISCV_TRACE_PACKET_FORMAT_VER (200) /*!< Efficient Trace v2.0 */
#define SOC_RISCV_TRACE_HAS_CONFIG_REG (1) /*!< Has the encoder config register */
#define SOC_RISCV_TRACE_AHB_CONFIGURABLE (1) /*!< AHB write master is configurable */
#define SOC_RISCV_TRACE_FILTER_SUPPORTED (1) /*!< Has the filter unit */
#define SOC_RISCV_TRACE_PRIV_WIDTH (2U) /*!< Bits in the privilege field (privilege_width_p) */
#define SOC_RISCV_TRACE_ECAUSE_WIDTH (6) /*!< Bits in the exception cause field (ecause_width_p) */
#define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM (1) /*!< Encoder AHB master can reach external PSRAM */