diff --git a/components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h
index 9b1c1aac905..6cbd3c3bb0d 100644
--- a/components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32c5/include/hal/riscv_trace_ll.h
@@ -104,6 +104,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -118,6 +123,11 @@ static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
     hw->config.full_address = full;
 }
 
+static inline bool riscv_trace_ll_get_full_address(trace_dev_t *hw)
+{
+    return hw->config.full_address;
+}
+
 static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
 {
     hw->config.stall_ena = enable;
@@ -154,11 +164,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = mode;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * AHB configuration
  *--------------------------------------------------------------------------*/
@@ -219,7 +239,7 @@ static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
 static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
                                                            bool intr_value, uint32_t ecause_choice)
 {
-    // This target has no supervisor mode, so the selector is 1 bit: 0 = user, 1 = machine.
+    /* Target has no supervisor mode. 0 = user, 1 = machine. */
     hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
     hw->filter_match_control.match_value_interrupt = intr_value;
     hw->filter_match_control.match_choice_ecause = ecause_choice;
diff --git a/components/esp_hal_debug_assist/esp32c6/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32c6/include/hal/riscv_trace_ll.h
index 8333dc86a9c..af93d6fdfdd 100644
--- a/components/esp_hal_debug_assist/esp32c6/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32c6/include/hal/riscv_trace_ll.h
@@ -112,6 +112,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -134,11 +139,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = (mode == RISCV_TRACE_RESYNC_PACKET);
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode ? RISCV_TRACE_RESYNC_PACKET : RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * Interrupts
  *--------------------------------------------------------------------------*/
diff --git a/components/esp_hal_debug_assist/esp32c61/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32c61/include/hal/riscv_trace_ll.h
index 9b1c1aac905..6cbd3c3bb0d 100644
--- a/components/esp_hal_debug_assist/esp32c61/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32c61/include/hal/riscv_trace_ll.h
@@ -104,6 +104,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -118,6 +123,11 @@ static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
     hw->config.full_address = full;
 }
 
+static inline bool riscv_trace_ll_get_full_address(trace_dev_t *hw)
+{
+    return hw->config.full_address;
+}
+
 static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
 {
     hw->config.stall_ena = enable;
@@ -154,11 +164,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = mode;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * AHB configuration
  *--------------------------------------------------------------------------*/
@@ -219,7 +239,7 @@ static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
 static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
                                                            bool intr_value, uint32_t ecause_choice)
 {
-    // This target has no supervisor mode, so the selector is 1 bit: 0 = user, 1 = machine.
+    /* Target has no supervisor mode. 0 = user, 1 = machine. */
     hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
     hw->filter_match_control.match_value_interrupt = intr_value;
     hw->filter_match_control.match_choice_ecause = ecause_choice;
diff --git a/components/esp_hal_debug_assist/esp32h2/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32h2/include/hal/riscv_trace_ll.h
index 189028dd628..61c5617965f 100644
--- a/components/esp_hal_debug_assist/esp32h2/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32h2/include/hal/riscv_trace_ll.h
@@ -112,6 +112,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -134,11 +139,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = (mode == RISCV_TRACE_RESYNC_PACKET);
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode ? RISCV_TRACE_RESYNC_PACKET : RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * Interrupts
  *--------------------------------------------------------------------------*/
diff --git a/components/esp_hal_debug_assist/esp32h21/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32h21/include/hal/riscv_trace_ll.h
index cd301883be0..b41910b4de5 100644
--- a/components/esp_hal_debug_assist/esp32h21/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32h21/include/hal/riscv_trace_ll.h
@@ -112,6 +112,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -134,11 +139,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = (mode == RISCV_TRACE_RESYNC_PACKET);
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode ? RISCV_TRACE_RESYNC_PACKET : RISCV_TRACE_RESYNC_CYCLE;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * Interrupts
  *--------------------------------------------------------------------------*/
diff --git a/components/esp_hal_debug_assist/esp32h4/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32h4/include/hal/riscv_trace_ll.h
index 5320f038d88..fac2ae785e6 100644
--- a/components/esp_hal_debug_assist/esp32h4/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32h4/include/hal/riscv_trace_ll.h
@@ -114,6 +114,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -128,6 +133,11 @@ static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
     hw->config.full_address = full;
 }
 
+static inline bool riscv_trace_ll_get_full_address(trace_dev_t *hw)
+{
+    return hw->config.full_address;
+}
+
 static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
 {
     hw->config.stall_ena = enable;
@@ -164,11 +174,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = mode;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * AHB configuration
  *--------------------------------------------------------------------------*/
@@ -229,7 +249,7 @@ static inline bool riscv_trace_ll_priv_is_supported(uint32_t priv)
 static inline void riscv_trace_ll_set_filter_match_control(trace_dev_t *hw, uint32_t priv_choice,
                                                            bool intr_value, uint32_t ecause_choice)
 {
-    // This target has no supervisor mode, so the selector is 1 bit: 0 = user, 1 = machine.
+    /* Target has no supervisor mode. 0 = user, 1 = machine. */
     hw->filter_match_control.match_choice_privilege = (priv_choice == RISCV_TRACE_PRIV_MACHINE);
     hw->filter_match_control.match_value_interrupt = intr_value;
     hw->filter_match_control.match_choice_ecause = ecause_choice;
diff --git a/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h
index b7710afdf40..95c2d1a49c4 100644
--- a/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32p4/include/hal/riscv_trace_ll.h
@@ -118,6 +118,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -132,6 +137,11 @@ static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
     hw->config.full_address = full;
 }
 
+static inline bool riscv_trace_ll_get_full_address(trace_dev_t *hw)
+{
+    return hw->config.full_address;
+}
+
 static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
 {
     hw->config.stall_ena = enable;
@@ -168,11 +178,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = mode;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * AHB configuration
  *--------------------------------------------------------------------------*/
diff --git a/components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h b/components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h
index 2bf57eb39eb..50a6257acb6 100644
--- a/components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h
+++ b/components/esp_hal_debug_assist/esp32s31/include/hal/riscv_trace_ll.h
@@ -114,6 +114,11 @@ static inline void riscv_trace_ll_set_mem_loop(trace_dev_t *hw, bool loop)
     hw->trigger.mem_loop = loop;
 }
 
+static inline bool riscv_trace_ll_get_mem_loop(trace_dev_t *hw)
+{
+    return hw->trigger.mem_loop;
+}
+
 static inline void riscv_trace_ll_set_restart_ena(trace_dev_t *hw, bool enable)
 {
     hw->trigger.restart_ena = enable;
@@ -128,6 +133,11 @@ static inline void riscv_trace_ll_set_full_address(trace_dev_t *hw, bool full)
     hw->config.full_address = full;
 }
 
+static inline bool riscv_trace_ll_get_full_address(trace_dev_t *hw)
+{
+    return hw->config.full_address;
+}
+
 static inline void riscv_trace_ll_set_stall_ena(trace_dev_t *hw, bool enable)
 {
     hw->config.stall_ena = enable;
@@ -164,11 +174,21 @@ static inline void riscv_trace_ll_set_resync_mode(trace_dev_t *hw, uint32_t mode
     hw->resync_prolonged.resync_mode = mode;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_mode(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_mode;
+}
+
 static inline void riscv_trace_ll_set_resync_threshold(trace_dev_t *hw, uint32_t threshold)
 {
     hw->resync_prolonged.resync_prolonged = threshold;
 }
 
+static inline uint32_t riscv_trace_ll_get_resync_threshold(trace_dev_t *hw)
+{
+    return hw->resync_prolonged.resync_prolonged;
+}
+
 /*---------------------------------------------------------------------------
  * AHB configuration
  *--------------------------------------------------------------------------*/
diff --git a/components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h b/components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h
index fedc5992822..55ee576dedb 100644
--- a/components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h
+++ b/components/esp_hal_debug_assist/include/hal/riscv_trace_hal.h
@@ -8,6 +8,7 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "hal/riscv_trace_types.h"
 
 #ifdef __cplusplus
@@ -40,10 +41,10 @@ typedef struct {
 
 /** @brief One comparator of the filter unit (raw register values). */
 typedef struct {
-    uint32_t input;                /*!< Compared input: 0 = iaddr, 1 = tval */
-    uint32_t function;             /*!< Compare function: 0 ==, 1 !=, 2 <, 3 <=, 4 >, 5 >= */
+    uint32_t input;                /*!< Compared input (0 = iaddr, 1 = tval) */
+    uint32_t function;             /*!< Compare function (0 ==, 1 !=, 2 <, 3 <=, 4 >, 5 >=) */
     uint32_t match_value;          /*!< 32-bit value compared against the input */
-    bool notify;                   /*!< Emit a packet reporting the address that caused the match */
+    bool notify;                   /*!< Send a packet reporting the address that caused the match */
 } riscv_trace_hal_comparator_t;
 
 /** @brief Filter (trace qualifier) configuration. */
@@ -54,7 +55,7 @@ typedef struct {
     bool match_ecause;             /*!< Match from an exception cause (match_ecause) */
     bool match_interrupt;          /*!< Match from an interrupt trap (match_interrupt) */
     uint32_t privilege;            /*!< match_choice_privilege (riscv_trace_priv_t) */
-    bool interrupt_itype2;         /*!< match_value_interrupt: true = itype 2, false = itype 1 */
+    bool interrupt_itype2;         /*!< match_value_interrupt (true = itype 2, false = itype 1) */
     uint32_t ecause;               /*!< match_choice_ecause (6-bit exception cause code) */
     riscv_trace_hal_comparator_t primary;   /*!< Primary comparator */
     riscv_trace_hal_comparator_t secondary; /*!< Secondary comparator */
@@ -102,6 +103,20 @@ bool riscv_trace_hal_fifo_is_overflowed(uint32_t intr_status);
 /** @brief Reset the hardware write pointer and clear interrupts before a new capture. */
 void riscv_trace_hal_prepare_capture(riscv_trace_hal_context_t *ctx);
 
+/** @brief Read back the LOOP-vs-STOP bit of the trace memory configuration. */
+bool riscv_trace_hal_get_mem_loop(riscv_trace_hal_context_t *ctx);
+
+#if SOC_RISCV_TRACE_HAS_CONFIG_REG
+/** @brief Read back whether the encoder is in full-address mode (vs delta). Only on targets with the config register. */
+bool riscv_trace_hal_get_full_address(riscv_trace_hal_context_t *ctx);
+#endif
+
+/** @brief Read back the resynchronization mode (RISCV_TRACE_RESYNC_*). */
+uint32_t riscv_trace_hal_get_resync_mode(riscv_trace_hal_context_t *ctx);
+
+/** @brief Read back the resynchronization counter threshold from the hardware. */
+uint32_t riscv_trace_hal_get_resync_threshold(riscv_trace_hal_context_t *ctx);
+
 /** @brief Apply a filter (trace qualifier) configuration. Set before starting a capture. */
 void riscv_trace_hal_set_filter(riscv_trace_hal_context_t *ctx, const riscv_trace_hal_filter_config_t *config);
 
diff --git a/components/esp_hal_debug_assist/riscv_trace_hal.c b/components/esp_hal_debug_assist/riscv_trace_hal.c
index b315fa96cdc..06262f229fd 100644
--- a/components/esp_hal_debug_assist/riscv_trace_hal.c
+++ b/components/esp_hal_debug_assist/riscv_trace_hal.c
@@ -5,13 +5,11 @@
  */
 
 /*
- * RISC-V trace encoder HAL: register-sequencing layer used by the
- * `esp_riscv_trace` driver. It sits on top of the target-specific LL
- * (hal/riscv_trace_ll.h), which performs the raw register accesses.
+ * RISC-V trace encoder HAL. Register sequencing layer used by the
+ * esp_riscv_trace driver.
  *
- * These interfaces are internal to ESP-IDF and subject to change. The HAL
- * performs no locking: callers that use it directly are responsible for
- * serializing concurrent access to the same trace encoder instance.
+ * Internal to ESP-IDF and subject to change. The HAL performs no locking.
+ * Callers must serialize concurrent access to the same encoder instance.
  */
 
 #include <stddef.h>
@@ -156,6 +154,32 @@ void riscv_trace_hal_prepare_capture(riscv_trace_hal_context_t *ctx)
     riscv_trace_ll_clear_intr(ctx->dev, TRACE_FIFO_OVERFLOW_INTR_RAW | TRACE_MEM_FULL_INTR_RAW);
 }
 
+bool riscv_trace_hal_get_mem_loop(riscv_trace_hal_context_t *ctx)
+{
+    HAL_ASSERT(ctx != NULL);
+    return riscv_trace_ll_get_mem_loop(ctx->dev);
+}
+
+#if SOC_RISCV_TRACE_HAS_CONFIG_REG
+bool riscv_trace_hal_get_full_address(riscv_trace_hal_context_t *ctx)
+{
+    HAL_ASSERT(ctx != NULL);
+    return riscv_trace_ll_get_full_address(ctx->dev);
+}
+#endif
+
+uint32_t riscv_trace_hal_get_resync_mode(riscv_trace_hal_context_t *ctx)
+{
+    HAL_ASSERT(ctx != NULL);
+    return riscv_trace_ll_get_resync_mode(ctx->dev);
+}
+
+uint32_t riscv_trace_hal_get_resync_threshold(riscv_trace_hal_context_t *ctx)
+{
+    HAL_ASSERT(ctx != NULL);
+    return riscv_trace_ll_get_resync_threshold(ctx->dev);
+}
+
 #if SOC_RISCV_TRACE_FILTER_SUPPORTED
 void riscv_trace_hal_set_filter(riscv_trace_hal_context_t *ctx, const riscv_trace_hal_filter_config_t *config)
 {
diff --git a/components/esp_riscv_trace/src/esp_riscv_trace.c b/components/esp_riscv_trace/src/esp_riscv_trace.c
index 79981518ae5..b6f4d0a5f11 100644
--- a/components/esp_riscv_trace/src/esp_riscv_trace.c
+++ b/components/esp_riscv_trace/src/esp_riscv_trace.c
@@ -31,6 +31,9 @@
 
 #define ESP_RISCV_TRACE_BUFFER_ALIGNMENT      4
 
+/* One word is reserved so mem_end_addr can point at the last writable word. */
+#define ESP_RISCV_TRACE_BUFFER_MIN_SIZE       8
+
 static const char *TAG = "esp_riscv_trace";
 
 /* Handles created at startup by esp_riscv_trace_early_init(), one slot per core. */
@@ -41,15 +44,15 @@ static uint8_t *alloc_aligned_buffer(size_t requested, uint32_t caps, size_t *ou
     *out_size = 0;
 
     size_t cache_alignment = 0;
-    ESP_RETURN_ON_FALSE(esp_cache_get_alignment(caps, &cache_alignment) == ESP_OK, NULL, TAG,
-                        "failed to get buffer alignment");
+    ESP_RETURN_ON_FALSE_ISR(esp_cache_get_alignment(caps, &cache_alignment) == ESP_OK, NULL, TAG,
+                            "failed to get buffer alignment");
     size_t alignment = MAX(cache_alignment, ESP_RISCV_TRACE_BUFFER_ALIGNMENT);
 
-    ESP_RETURN_ON_FALSE(requested <= SIZE_MAX - (alignment - 1), NULL, TAG,
-                        "trace buffer size too large");
+    ESP_RETURN_ON_FALSE_ISR(requested <= SIZE_MAX - (alignment - 1), NULL, TAG,
+                            "trace buffer size too large");
     size_t size = ESP_ALIGN_UP(requested, alignment);
     uint8_t *buf = heap_caps_aligned_calloc(alignment, 1, size, caps);
-    ESP_RETURN_ON_FALSE(buf != NULL, NULL, TAG, "failed to allocate buffer");
+    ESP_RETURN_ON_FALSE_ISR(buf != NULL, NULL, TAG, "failed to allocate buffer");
     *out_size = size;
     return buf;
 }
@@ -161,19 +164,23 @@ static esp_err_t validate_filter_config(const esp_riscv_trace_filter_config_t *c
 static esp_err_t validate_trace_config(esp_riscv_trace_core_t core_id, const esp_riscv_trace_config_t *config,
                                        esp_riscv_trace_handle_t *ret_handle)
 {
-    ESP_RETURN_ON_FALSE(config != NULL, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
-    ESP_RETURN_ON_FALSE(ret_handle != NULL, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
-    ESP_RETURN_ON_FALSE((int)core_id >= 0 && (int)core_id < SOC_CPU_CORES_NUM,
-                        ESP_ERR_INVALID_ARG, TAG, "invalid core id");
-    ESP_RETURN_ON_FALSE(config->buffer_size != 0, ESP_ERR_INVALID_SIZE, TAG, "trace buffer size is 0");
-    ESP_RETURN_ON_FALSE(is_valid_address_mode(config->address_mode), ESP_ERR_INVALID_ARG, TAG, "invalid address mode");
-    ESP_RETURN_ON_FALSE(is_valid_mem_mode(config->mem_mode), ESP_ERR_INVALID_ARG, TAG, "invalid memory mode");
-    ESP_RETURN_ON_FALSE(is_valid_resync_mode(config->resync_mode), ESP_ERR_INVALID_ARG, TAG, "invalid resync mode");
-    ESP_RETURN_ON_FALSE(riscv_trace_ll_resync_mode_is_supported((uint32_t)config->resync_mode),
-                        ESP_ERR_NOT_SUPPORTED, TAG, "resync mode not supported on this target");
-    ESP_RETURN_ON_FALSE(is_valid_ahb_burst(config->ahb_burst), ESP_ERR_INVALID_ARG, TAG, "invalid AHB burst");
-    ESP_RETURN_ON_FALSE(is_valid_core_mask(config->core_mask), ESP_ERR_INVALID_ARG, TAG, "invalid core mask");
-    ESP_RETURN_ON_FALSE(is_valid_buffer_mem(config->buffer_mem), ESP_ERR_INVALID_ARG, TAG, "invalid buffer memory");
+    ESP_RETURN_ON_FALSE_ISR(config != NULL, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE_ISR(ret_handle != NULL, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
+    ESP_RETURN_ON_FALSE_ISR((int)core_id >= 0 && (int)core_id < SOC_CPU_CORES_NUM,
+                            ESP_ERR_INVALID_ARG, TAG, "invalid core id");
+    ESP_RETURN_ON_FALSE_ISR(config->buffer_size >= ESP_RISCV_TRACE_BUFFER_MIN_SIZE, ESP_ERR_INVALID_SIZE, TAG,
+                            "trace buffer must be at least %d bytes", ESP_RISCV_TRACE_BUFFER_MIN_SIZE);
+    ESP_RETURN_ON_FALSE_ISR(is_valid_address_mode(config->address_mode), ESP_ERR_INVALID_ARG, TAG,
+                            "invalid address mode");
+    ESP_RETURN_ON_FALSE_ISR(is_valid_mem_mode(config->mem_mode), ESP_ERR_INVALID_ARG, TAG, "invalid memory mode");
+    ESP_RETURN_ON_FALSE_ISR(is_valid_resync_mode(config->resync_mode), ESP_ERR_INVALID_ARG, TAG,
+                            "invalid resync mode");
+    ESP_RETURN_ON_FALSE_ISR(riscv_trace_ll_resync_mode_is_supported((uint32_t)config->resync_mode),
+                            ESP_ERR_NOT_SUPPORTED, TAG, "resync mode not supported on this target");
+    ESP_RETURN_ON_FALSE_ISR(is_valid_ahb_burst(config->ahb_burst), ESP_ERR_INVALID_ARG, TAG, "invalid AHB burst");
+    ESP_RETURN_ON_FALSE_ISR(is_valid_core_mask(config->core_mask), ESP_ERR_INVALID_ARG, TAG, "invalid core mask");
+    ESP_RETURN_ON_FALSE_ISR(is_valid_buffer_mem(config->buffer_mem), ESP_ERR_INVALID_ARG, TAG,
+                            "invalid buffer memory");
 
     return ESP_OK;
 }
@@ -183,21 +190,21 @@ static esp_err_t esp_riscv_trace_new(esp_riscv_trace_core_t core_id, const esp_r
 {
     esp_err_t ret = ESP_OK;
 
-    ESP_RETURN_ON_ERROR(validate_trace_config(core_id, config, ret_handle), TAG, "invalid trace configuration");
+    ESP_RETURN_ON_ERROR_ISR(validate_trace_config(core_id, config, ret_handle), TAG, "invalid trace configuration");
 
     size_t trace_mem_size = 0;
     uint8_t *trace_mem = alloc_aligned_buffer(config->buffer_size, trace_buffer_caps(config->buffer_mem),
                                               &trace_mem_size);
-    ESP_RETURN_ON_FALSE(trace_mem != NULL, ESP_ERR_NO_MEM, TAG, "failed to allocate trace buffer");
+    ESP_RETURN_ON_FALSE_ISR(trace_mem != NULL, ESP_ERR_NO_MEM, TAG, "failed to allocate trace buffer");
 
     esp_riscv_trace_handle_t handle = heap_caps_calloc(1, sizeof(struct esp_riscv_trace_context_t),
                                                        ESP_RISCV_TRACE_OBJ_CAPS);
-    ESP_GOTO_ON_FALSE(handle != NULL, ESP_ERR_NO_MEM, err_alloc, TAG, "no mem for the trace handle");
+    ESP_GOTO_ON_FALSE_ISR(handle != NULL, ESP_ERR_NO_MEM, err_alloc, TAG, "no mem for the trace handle");
 
     riscv_trace_hal_context_t hal_ctx;
     riscv_trace_hal_config_t hal_config = {
         .mem_start_addr = (uint32_t)trace_mem,
-        .mem_end_addr = (uint32_t)trace_mem + trace_mem_size,
+        .mem_end_addr = (uint32_t)trace_mem + trace_mem_size - sizeof(uint32_t),
         .full_address = (config->address_mode == ESP_RISCV_TRACE_ADDR_FULL),
         .mem_loop = (config->mem_mode == ESP_RISCV_TRACE_MEM_LOOP),
         .auto_restart = config->auto_restart,
diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
index 87cb0251cbc..69a3494449a 100644
--- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
@@ -1619,6 +1619,10 @@ config SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 200
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
@@ -1634,3 +1638,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 6
diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h
index f4bed4b404c..2ae9bdc0d73 100644
--- a/components/soc/esp32c5/include/soc/soc_caps.h
+++ b/components/soc/esp32c5/include/soc/soc_caps.h
@@ -645,7 +645,9 @@
 #define SOC_LP_CORE_LP_UART_WAKEUP_KEEP_TRIGGERED   (1) /*!< LP UART wakeup source is kept triggered */
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (200) /*!< Efficient Trace v2.0 */
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
 #define SOC_RISCV_TRACE_FILTER_SUPPORTED            (1) /*!< Has the filter unit */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (6) /*!< Bits in the exception cause field (ecause_width_p) */
diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
index 07570fbbae2..d378d489c2a 100644
--- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
@@ -1355,6 +1355,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 100
+
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 5
diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h
index 2ae34d2b7c0..86ad9603a56 100644
--- a/components/soc/esp32c6/include/soc/soc_caps.h
+++ b/components/soc/esp32c6/include/soc/soc_caps.h
@@ -549,4 +549,6 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (100) /*!< Processor Trace v1.0 */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (5) /*!< Bits in the exception cause field (ecause_width_p) */
diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
index d950c2df246..e68727b92bc 100644
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@@ -1239,6 +1239,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 200
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
@@ -1254,3 +1258,7 @@ config SOC_RISCV_TRACE_FILTER_SUPPORTED
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 6
diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h
index e414be92c8c..0536b88e2e1 100644
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@@ -499,10 +499,12 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (200) /*!< Efficient Trace v2.0 */
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
 #define SOC_RISCV_TRACE_FILTER_SUPPORTED            (1) /*!< Has the filter unit */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (6) /*!< Bits in the exception cause field (ecause_width_p) */
 
 /*------------------------------------- No Reset CAPS -------------------------------------*/
 //  \#define SOC_CAPS_NO_RESET_BY_ANA_BOD           (1)   //TODO: [ESP32C61] IDF-9254
diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
index 6583a2992be..3701ffdeb8d 100644
--- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
@@ -1251,6 +1251,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 100
+
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 5
diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h
index c7a4ca6823a..8e08c1b4c6f 100644
--- a/components/soc/esp32h2/include/soc/soc_caps.h
+++ b/components/soc/esp32h2/include/soc/soc_caps.h
@@ -530,4 +530,6 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (100) /*!< Processor Trace v1.0 */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (5) /*!< Bits in the exception cause field (ecause_width_p) */
diff --git a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
index 4d9ba755b81..c1316304ed5 100644
--- a/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
@@ -1151,6 +1151,14 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 100
+
 config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
+
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 5
diff --git a/components/soc/esp32h21/include/soc/soc_caps.h b/components/soc/esp32h21/include/soc/soc_caps.h
index 9618eb8584c..49f329fb98b 100644
--- a/components/soc/esp32h21/include/soc/soc_caps.h
+++ b/components/soc/esp32h21/include/soc/soc_caps.h
@@ -499,4 +499,6 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (100) /*!< Processor Trace v1.0 */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (5) /*!< Bits in the exception cause field (ecause_width_p) */
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index c49cd55822f..345d9929cf2 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -1387,6 +1387,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 200
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
@@ -1403,6 +1407,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
 
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 6
+
 config SOC_ASRC_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index 68c13ee8d3f..8013422edda 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -570,10 +570,12 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (200) /*!< Efficient Trace v2.0 */
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
 #define SOC_RISCV_TRACE_FILTER_SUPPORTED            (1) /*!< Has the filter unit */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (6) /*!< Bits in the exception cause field (ecause_width_p) */
 
 /*---------------------------------- ASRC CAPS ----------------------------------*/
 #define SOC_ASRC_SUPPORTED (1)
diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
index 20fd8615a5a..d2fb57c3c09 100644
--- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
@@ -1935,6 +1935,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 200
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
@@ -1951,6 +1955,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 1
 
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 6
+
 config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
     bool
     default y
diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h
index 9514d95895c..c5340114575 100644
--- a/components/soc/esp32p4/include/soc/soc_caps.h
+++ b/components/soc/esp32p4/include/soc/soc_caps.h
@@ -740,8 +740,10 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (200) /*!< Efficient Trace v2.0 */
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
 #define SOC_RISCV_TRACE_FILTER_SUPPORTED            (1) /*!< Has the filter unit */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (1U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (6) /*!< Bits in the exception cause field (ecause_width_p) */
 #define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM           (1) /*!< Encoder AHB master can reach external PSRAM */
diff --git a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
index d5f62e19a50..1bea7895fde 100644
--- a/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
@@ -1867,6 +1867,10 @@ config SOC_DEBUG_HAVE_OCD_STUB_BINS
     bool
     default y
 
+config SOC_RISCV_TRACE_PACKET_FORMAT_VER
+    int
+    default 200
+
 config SOC_RISCV_TRACE_HAS_CONFIG_REG
     bool
     default y
@@ -1883,6 +1887,10 @@ config SOC_RISCV_TRACE_PRIV_WIDTH
     int
     default 2
 
+config SOC_RISCV_TRACE_ECAUSE_WIDTH
+    int
+    default 6
+
 config SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM
     bool
     default y
diff --git a/components/soc/esp32s31/include/soc/soc_caps.h b/components/soc/esp32s31/include/soc/soc_caps.h
index 0dc1f8a43eb..b3ccb18e14f 100644
--- a/components/soc/esp32s31/include/soc/soc_caps.h
+++ b/components/soc/esp32s31/include/soc/soc_caps.h
@@ -695,8 +695,10 @@
 #define SOC_DEBUG_HAVE_OCD_STUB_BINS    (1)
 
 /*-------------------------- RISC-V TRACE CAPS ------------------------------*/
+#define SOC_RISCV_TRACE_PACKET_FORMAT_VER           (200) /*!< Efficient Trace v2.0 */
 #define SOC_RISCV_TRACE_HAS_CONFIG_REG              (1) /*!< Has the encoder config register */
 #define SOC_RISCV_TRACE_AHB_CONFIGURABLE            (1) /*!< AHB write master is configurable */
 #define SOC_RISCV_TRACE_FILTER_SUPPORTED            (1) /*!< Has the filter unit */
 #define SOC_RISCV_TRACE_PRIV_WIDTH                  (2U) /*!< Bits in the privilege field (privilege_width_p) */
+#define SOC_RISCV_TRACE_ECAUSE_WIDTH                (6) /*!< Bits in the exception cause field (ecause_width_p) */
 #define SOC_RISCV_TRACE_MEM_SUPPORT_PSRAM           (1) /*!< Encoder AHB master can reach external PSRAM */