mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 11:10:54 +03:00
Merge branch 'fix/spi_buslock_multi_dev_acq_release_issue_v6.0' into 'release/v6.0'
fix(esp_hw_support): fixed spi buslock multi dev acq/release logic issue (v6.0) See merge request espressif/esp-idf!49168
This commit is contained in:
morris
+1
-1
@@ -55,7 +55,7 @@
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#elif CONFIG_IDF_TARGET_ESP32C6
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#define IDF_TARGET_MAX_SPI_CLK_FREQ 26666*1000
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#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 35 //TODO: IDF-9551, check perform
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#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA 37 //TODO: IDF-9551, check perform
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#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA 19
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#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU 32
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#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU 15
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@@ -5,3 +5,4 @@ dependencies:
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path: ${IDF_PATH}/components/driver/test_apps/components/test_driver_utils
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spi_bench_mark:
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path: ${IDF_PATH}/components/esp_driver_spi/test_apps/components/spi_bench_mark
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espressif/esp_serial_slave_link: "^1.1.0"
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -347,3 +347,61 @@ TEST_CASE("spi master can be used on SPI1", "[spi]")
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//TODO: add a case when a non-polling transaction happened in the bus-acquiring time and then release the bus then queue a new trans
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#endif //!(CONFIG_SPIRAM && CONFIG_IDF_TARGET_ESP32)
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#define TEST_LARGE_TRANS_LEN 2048
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static void dev2_polling_task(void *arg)
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{
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task_context_t *ctx = (task_context_t *)arg;
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spi_transaction_t t = {
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.flags = SPI_TRANS_USE_TXDATA,
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.length = 32,
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};
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while (!ctx->finished) {
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TEST_ESP_OK(spi_device_polling_transmit(ctx->handle, &t));
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vTaskDelay(pdMS_TO_TICKS(1));
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}
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vTaskDelete(NULL);
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}
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TEST_CASE("release_bus during flying is safe to other device acquiring", "[spi]")
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{
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spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
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spi_device_interface_config_t devcfg_p = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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spi_device_interface_config_t devcfg_q = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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devcfg_q.spics_io_num = -1;
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devcfg_q.queue_size = 3;
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devcfg_q.clock_speed_hz = 500 * 1000;
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spi_device_handle_t dev_q;
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task_context_t ctx = {};
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg_p, &ctx.handle));
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &devcfg_q, &dev_q));
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// polling task with higher priority than the interrupt task
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xTaskCreate(dev2_polling_task, "spi17860_p", 4096, &ctx, 6, NULL);
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uint8_t *q_txb = heap_caps_malloc(TEST_LARGE_TRANS_LEN, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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spi_transaction_t *ret_trans, trans = {
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.length = TEST_LARGE_TRANS_LEN * 8,
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.tx_buffer = q_txb,
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};
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for (int i = 0; i < 30; i++) {
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TEST_ESP_OK(spi_device_acquire_bus(dev_q, portMAX_DELAY));
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TEST_ESP_OK(spi_device_queue_trans(dev_q, &trans, portMAX_DELAY));
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esp_rom_printf("queue trans %d\n", i);
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spi_device_release_bus(dev_q);
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}
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ctx.finished = true;
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vTaskDelay(pdMS_TO_TICKS(100)); // wait for all trans finished
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for (int i = 0; i < devcfg_q.queue_size; i++) {
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spi_device_get_trans_result(dev_q, &ret_trans, 0);
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}
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free(q_txb);
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TEST_ESP_OK(spi_bus_remove_device(ctx.handle));
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TEST_ESP_OK(spi_bus_remove_device(dev_q));
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TEST_ESP_OK(spi_bus_free(TEST_SPI_HOST));
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}
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -22,12 +22,16 @@
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#include "driver/spi_slave.h"
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#include "esp_heap_caps.h"
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#include "esp_log.h"
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#include "soc/soc_caps.h"
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#include "soc/spi_periph.h"
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#include "soc/gpio_struct.h"
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#include "test_utils.h"
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#include "test_spi_utils.h"
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#include "test_dualboard_utils.h"
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#include "hal/spi_ll.h"
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#include "driver/spi_slave_hd.h"
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#include "esp_serial_slave_link/essl_spi.h"
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#endif
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#if (TEST_SPI_PERIPH_NUM >= 2)
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//These will be only enabled on chips with 2 or more SPI peripherals
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@@ -35,27 +39,6 @@
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/********************************************************************************
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* Test SIO
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********************************************************************************/
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#if CONFIG_IDF_TARGET_ESP32
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#define MASTER_DIN_SIGNAL HSPID_IN_IDX
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#elif CONFIG_IDF_TARGET_ESP32P4
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#define MASTER_DIN_SIGNAL SPI2_D_PAD_IN_IDX
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#else
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#define MASTER_DIN_SIGNAL FSPID_IN_IDX
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#endif
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static void inner_connect(spi_bus_config_t bus)
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{
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//Master MOSI(spid_out) output to `mosi_num`
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spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
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//Slave MOSI(spid_in) input to `mosi_num`
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spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
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//Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data
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spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
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//Slave MISO output(spiq_out)
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spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
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//Force this signal goes through gpio matrix
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GPIO.func_in_sel_cfg[MASTER_DIN_SIGNAL].sig_in_sel = 1;
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}
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TEST_CASE("SPI Single Board Test SIO", "[spi]")
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{
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@@ -76,7 +59,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED));
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same_pin_func_sel(TEST_SPI_HOST, TEST_SLAVE_HOST, bus_cfg, dev_cfg.spics_io_num);
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inner_connect(bus_cfg);
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// fix sio internal connection
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spitest_gpio_input_sel(bus_cfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
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WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
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WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
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@@ -141,185 +125,103 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
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#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
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/********************************************************************************
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* Test SIO Master
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* SIO Slave is not supported, and one unit test is limited to one feature, so,,,
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* sio master test can be split to signal-input and single-output
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*
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* for single-output: master slave
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* cs-----cs ------------- cs
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* clk----clk ------------- clk
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* d------mosi------------- mosi
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* q miso------------- miso
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* master can get input on mosi pin after output finish in sio mode, but in this
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* case, master can get no data from slave, so check assert on the slave.
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*
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* ------------------------------------------------------------------------------
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* for single-input: master slave
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* cs-----cs ------------- cs
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* clk----clk ------------- clk
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* d-\ mosi------------- mosi
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* q \\--miso------------- miso
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* In this case, master can get input data from slave after output finish, but
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* slave can get no data from master due to internal broke, besides output data
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* from both master and slave on miso line will get conflict in master's output
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* frame.
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* Test SIO Master + SIO Slave HD
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********************************************************************************/
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#define TRANS_LEN 1024
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#define MAX_TRANS_BUFF 64
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#define TEST_NUM 8
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WORD_ALIGNED_ATTR uint8_t sio_master_rx_buff[TRANS_LEN];
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WORD_ALIGNED_ATTR uint8_t sio_slave_rx_buff [TRANS_LEN];
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void test_sio_master_trans(bool sio_master_in)
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void test_sio_master_trans(void)
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{
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spi_device_handle_t dev_0;
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uint8_t *master_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
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TEST_ASSERT_NOT_NULL_MESSAGE(master_tx_max, "malloc failed, exit.\n");
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// write something to a long buffer for test long transmission
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for (uint16_t i = 0; i < TRANS_LEN; i++) {
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master_tx_max[i] = i;
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master_tx_max[TRANS_LEN * 2 - i - 1] = i;
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}
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spi_device_handle_t dev;
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uint8_t *master_tx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
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uint8_t *master_rx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
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uint8_t *rx_exp = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
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TEST_ASSERT_TRUE_MESSAGE(master_tx && master_rx && rx_exp, "malloc failed, exit.\n");
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test_fill_random_to_buffers_dualboard(1, master_tx, rx_exp, TRANS_LEN);
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
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if (sio_master_in) {
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// normally, spi read data from port Q and write data to port D
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// test master input from port D (output default.), so link port D (normally named mosi) to miso pin.
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bus_cfg.mosi_io_num = bus_cfg.miso_io_num;
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printf("\n====================Test sio master input====================\n");
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} else {
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printf("\n============Test sio master output, data checked by slave.=============\n");
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}
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bus_cfg.miso_io_num = -1;
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX | SPI_DEVICE_3WIRE;
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dev_cfg.clock_speed_hz = 1 * 1000 * 1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &dev_0));
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printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", dev_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num);
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dev_cfg.command_bits = 8;
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dev_cfg.address_bits = 8;
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dev_cfg.dummy_bits = 8;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &dev));
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printf("CS:CLK:SIO: %d\t%d\t%d\n", dev_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num);
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unity_send_signal("Master ready");
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for (int i = 0; i < TEST_NUM; i ++) {
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spi_transaction_t trans = {};
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if (sio_master_in) {
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// master input only section
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trans.rxlength = (i + 1) * 8 * 8;
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// test a huge data for last transmission
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if (i >= TEST_NUM - 1) {
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trans.rxlength = TRANS_LEN * 8;
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}
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trans.rx_buffer = sio_master_rx_buff;
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trans.length = 0;
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trans.tx_buffer = NULL;
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memset(sio_master_rx_buff, 0, sizeof(sio_master_rx_buff));
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} else {
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// master output only section
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trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
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// test a huge data for last transmission
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if (i >= TEST_NUM - 1) {
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trans.length = TRANS_LEN * 8;
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}
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trans.tx_buffer = master_tx_max;
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trans.rxlength = 0;
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trans.rx_buffer = NULL;
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// use some different data
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trans.tx_buffer += (i % 2) ? TRANS_LEN : 0;
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}
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for (int i = TEST_NUM; i > 0; i --) {
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size_t trans_len = TRANS_LEN >> i;
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//get signal
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unity_wait_for_signal("Slave ready");
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TEST_ESP_OK(essl_spi_wrdma(dev, master_tx, trans_len, -1, 0));
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ESP_LOG_BUFFER_HEXDUMP("master tx", master_tx, trans_len, ESP_LOG_INFO);
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TEST_ESP_OK(spi_device_transmit(dev_0, &trans));
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if (sio_master_in) {
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ESP_LOG_BUFFER_HEXDUMP("master rx", trans.rx_buffer, trans.rxlength / 8, ESP_LOG_INFO);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(master_tx_max + i, trans.rx_buffer, trans.rxlength / 8);
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} else {
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printf("%d master output\n", trans.length / 8);
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ESP_LOG_BUFFER_HEXDUMP("master tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO);
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}
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memset(master_rx, 0, trans_len);
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TEST_ESP_OK(essl_spi_rddma(dev, master_rx, trans_len, -1, 0));
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ESP_LOG_BUFFER_HEXDUMP("master rx", master_rx, trans_len, ESP_LOG_INFO);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(rx_exp, master_rx, trans_len);
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}
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free(master_tx_max);
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master_free_device_bus(dev_0);
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free(master_tx);
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free(master_rx);
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free(rx_exp);
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master_free_device_bus(dev);
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}
|
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|
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void test_sio_slave_emulate(bool sio_master_in)
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void test_sio_slave_trans(void)
|
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{
|
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uint8_t *slave_tx_max = heap_caps_calloc(TRANS_LEN * 2, 1, MALLOC_CAP_DMA);
|
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TEST_ASSERT_NOT_NULL_MESSAGE(slave_tx_max, "malloc failed, exit.\n");
|
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|
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// write something to a long buffer for test long transmission
|
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for (uint16_t i = 0; i < TRANS_LEN; i++) {
|
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slave_tx_max[i] = i;
|
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slave_tx_max[TRANS_LEN * 2 - i - 1] = i;
|
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}
|
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|
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if (sio_master_in) {
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printf("\n==================Test sio master input.================\n");
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} else {
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printf("\n==================Test sio master output.=================\n");
|
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}
|
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spi_slave_hd_data_t *ret_trans;
|
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uint8_t *slave_tx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
|
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uint8_t *slave_rx = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
|
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uint8_t *rx_exp = heap_caps_malloc(TRANS_LEN, MALLOC_CAP_DMA);
|
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TEST_ASSERT_TRUE_MESSAGE(slave_tx && slave_rx && rx_exp, "malloc failed, exit.\n");
|
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test_fill_random_to_buffers_dualboard(1, rx_exp, slave_tx, TRANS_LEN);
|
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|
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spi_bus_config_t bus_cfg = SPI_BUS_TEST_DEFAULT_CONFIG();
|
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spi_slave_interface_config_t slv_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
|
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TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_CH_AUTO));
|
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printf("CS:CLK:MO:MI: %d\t%d\t%d\t%d\n", slv_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num, bus_cfg.miso_io_num);
|
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bus_cfg.miso_io_num = -1;
|
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bus_cfg.max_transfer_sz = TRANS_LEN;
|
||||
spi_slave_hd_slot_config_t slave_hd_cfg = SPI_SLOT_TEST_DEFAULT_CONFIG();
|
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slave_hd_cfg.flags = SPI_SLAVE_HD_3WIRE_MODE;
|
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printf("CS:CLK:SIO: %d\t%d\t%d\n", (int)slave_hd_cfg.spics_io_num, bus_cfg.sclk_io_num, bus_cfg.mosi_io_num);
|
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|
||||
unity_wait_for_signal("Master ready");
|
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for (int i = 0; i < TEST_NUM; i++) {
|
||||
spi_slave_transaction_t trans = { .flags = SPI_SLAVE_TRANS_DMA_BUFFER_ALIGN_AUTO, };
|
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if (sio_master_in) {
|
||||
// slave output only section
|
||||
trans.length = (i + 1) * 8 * 8;
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
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trans.length = TRANS_LEN * 8;
|
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}
|
||||
trans.tx_buffer = slave_tx_max + i;
|
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trans.rx_buffer = NULL;
|
||||
} else {
|
||||
// slave input only section
|
||||
trans.length = MAX_TRANS_BUFF / (i + 1) * 8;
|
||||
// test a huge data for last transmission
|
||||
if (i >= TEST_NUM - 1) {
|
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trans.length = TRANS_LEN * 8;
|
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}
|
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trans.tx_buffer = NULL;
|
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trans.rx_buffer = sio_slave_rx_buff;
|
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memset(sio_slave_rx_buff, 0, sizeof(sio_slave_rx_buff));
|
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}
|
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TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg));
|
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|
||||
TEST_ESP_OK(spi_slave_queue_trans(TEST_SLAVE_HOST, &trans, portMAX_DELAY));
|
||||
for (int i = TEST_NUM; i > 0; i --) {
|
||||
size_t trans_len = TRANS_LEN >> i;
|
||||
spi_slave_hd_data_t rx_trans = {
|
||||
.data = slave_rx,
|
||||
.len = trans_len,
|
||||
.flags = SPI_SLAVE_HD_TRANS_DMA_BUFFER_ALIGN_AUTO,
|
||||
};
|
||||
spi_slave_hd_data_t tx_trans = {
|
||||
.data = slave_tx,
|
||||
.len = trans_len,
|
||||
};
|
||||
|
||||
memset(slave_rx, 0, trans_len);
|
||||
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &rx_trans, portMAX_DELAY));
|
||||
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &tx_trans, portMAX_DELAY));
|
||||
unity_send_signal("Slave ready");
|
||||
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
|
||||
TEST_ASSERT_EQUAL(&rx_trans, ret_trans);
|
||||
ESP_LOG_BUFFER_HEXDUMP("Slave rx", rx_trans.data, trans_len, ESP_LOG_INFO);
|
||||
TEST_ASSERT_EQUAL_HEX8_ARRAY(rx_exp, rx_trans.data, trans_len);
|
||||
|
||||
spi_slave_transaction_t *p_slave_ret;
|
||||
TEST_ESP_OK(spi_slave_get_trans_result(TEST_SLAVE_HOST, &p_slave_ret, portMAX_DELAY));
|
||||
|
||||
if (sio_master_in) {
|
||||
ESP_LOG_BUFFER_HEXDUMP("Slave tx", trans.tx_buffer, trans.length / 8, ESP_LOG_INFO);
|
||||
} else {
|
||||
ESP_LOG_BUFFER_HEXDUMP("Slave rx", trans.rx_buffer, trans.length / 8, ESP_LOG_INFO);
|
||||
TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_tx_max + TRANS_LEN * (i % 2), trans.rx_buffer, trans.length / 8);
|
||||
}
|
||||
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
|
||||
TEST_ASSERT_EQUAL(&tx_trans, ret_trans);
|
||||
ESP_LOG_BUFFER_HEXDUMP("Slave tx", tx_trans.data, trans_len, ESP_LOG_INFO);
|
||||
}
|
||||
|
||||
free(slave_tx_max);
|
||||
spi_slave_free(TEST_SLAVE_HOST);
|
||||
free(slave_tx);
|
||||
free(slave_rx);
|
||||
free(rx_exp);
|
||||
spi_slave_hd_deinit(TEST_SLAVE_HOST);
|
||||
}
|
||||
|
||||
void test_master_run(void)
|
||||
{
|
||||
test_sio_master_trans(false);
|
||||
test_sio_master_trans(true);
|
||||
}
|
||||
|
||||
void test_slave_run(void)
|
||||
{
|
||||
test_sio_slave_emulate(false);
|
||||
test_sio_slave_emulate(true);
|
||||
}
|
||||
|
||||
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test_SIO_Mode_Multi_Board", "[spi_ms][test_env=generic_multi_device]", test_master_run, test_slave_run);
|
||||
TEST_CASE_MULTIPLE_DEVICES("SPI_Master:Test_SIO_Mode_Multi_Board", "[spi_ms][test_env=generic_multi_device]", test_sio_master_trans, test_sio_slave_trans);
|
||||
#endif // SOC_SPI_SUPPORT_SLAVE_HD_VER2
|
||||
|
||||
Reference in New Issue
Block a user